diff --git a/README b/README index 211c3d3..ca098be 100644 --- a/README +++ b/README @@ -191,3 +191,147 @@ Build notes: files in the (committed) upstream repository while being able to generate the final layout through a series of known repeatable steps. + +(25) NOTE: The issue with having to rewrite the openlane scripts for + the "click" package is probably best resolved by running + in a python virtual environment, even though I consider that + solution akin to docker and dislike it immensely. + +(26) Continuing 8/28/2023 after another hiatus. + Testing with the following steps: + (1) Setup + setenv PDK_ROOT /usr/share/pdk + setenv PDK sky130A + (2) Synthesize the digital_locked_loop macro. + cd openlane/digital_locked_loop + ~/gits/openlane/flow.tcl -ignore_mismatches + + --> There is an immediate issue that verilator pulls all .v + files from the PDK, and is catching the newly-added + black-box files. Temporarily renaming them to avoid + a conflict. + --> Another issue is that fakediode_2 is calling a base + cell sky130_fd_sc_hd__diode that does not exist. + Changing name to from diode to diode_2 (need to fix in + the PDK install). + --> Same thing with fill_12 calling base cell fill that + does not exist; this one just needs to be deleted. + --> And verilator just seems to be overly eager to find + errors where they don't exist. Any way to turn it + off??? (Yes---set env variable "RUN_VERILATOR" to 0) + --> Failed due to no SYNTH_CAP_LOAD defined? + Defined it and set to 52 based on an entry in caravel. + No idea what the units are. . . Or why it needs to + be defined (might need an openlane update). + --> Now stuck again with the "click" module issue, in + io_place.py (fixed) and diodes.py (fixed) and + wire_lengths.py (fixed) and power_utils.py (fixed) + --> Started step 30 (stream-out with klayout) but klayout + isn't running in batch. Why would you stream out with + both klayout and magic? Just exiting from klayout + manually (but how to fix. . . and is this step even + needed?). + --> Step 37, cvc_rv does not exist. I have the source, but + it is not installed---and I cannot install it due to + inscrutable errors. (set env variable RUN_CVC = 0 + to disable) + --> Finally, the flow completed (although is it correct?) + (there are max fanout violations reported.) + + (3) Synthesize the picosoc macro. + cd openlane/picosoc + ~/gits/openlane/flow.tcl -ignore_mismatches + + --> Cannot find LEF of digital_locked_loop. + Copied the LEF file manually (but why isn't this done + automatically?) + --> Cannot find GDS of digital_locked_loop. + Copied the GDS file manually (but why isn't this done + automatically?) + --> Need to disable verilator + --> Cannot find .lib of digital_locked_loop. + None was created, so had to copy from the working files + Back-annotated comment: This can be corrected simply + by changing STA_WRITE_LIB to 1. + --> Cannot find gl/.v file of digital_locked_loop + Copied the .v file manually (but why isn't this done + automatically?) + --> Needs SYNTH_CAP_LOAD defined (see above) + --> Yosys error: picorv32 redefined ?? + Added "ifndef PnR"..."endif" around file includes + --> Needs digital_locked_loop.min.spef in + signoff/digital_locked_loop/openlane-signoff/spef/ + (added nom and max for good measure) + --> Now running and spending extensive time in step 16 + (global routing resizer design optimizations) + Letting it run. (Started 5:18pm) + --> And then it died on a totally obscure syntax error of + a line in picosoc.nl.v "wire [38:0] \% Xz ;". Seems + to have been derived from the pnl.v line which has + "wire [38:0] \J\xfd6\x88 ;". Not clear where this + comes from but tool updates (OpenROAD in particular) + are probably in order (wanders off for several hours + on a quest to rebuild OpenROAD. . .) + --> (Returns after finally coercing OpenROAD to compile + again) Now I get a different obscure error earlier + in the sequence: + + File "/home/tim/gits/openlane/scripts/odbpy/reader.py", + line 37, in __init__ + odb.read_def(self.db, def_in) + File "odb_py.py", line 9553, in read_def + TypeError: in method 'read_def', argument 1 of type 'odb::dbTech *' + + Something has gone very wrong here and it is not clear + to me what, other than that it was caused by recompiling + OpenROAD. + +(27) Continuing 8/29/2023 after updating OpenROAD *and* openlane. + + (1) Create python virtual environment this time to avoid issue + with the "click" package. + python3 -m venv ./venv + ./venv/bin/python3 -m pip install --upgrade --no-cache-dir -r \ + /home/tim/gits/openlane/requrements.txt + source ./venv/bin/activate.csh + --> This works! + + (2) Run ~/gits/openlane/flow.tcl -ignore_mismatches + --> RUN_VERILATOR superceded by RUN_LINTER (fixed) + --> yosys fails on command "proc_rom". . . + Need yosys update now. . . (Goes off and rebuilds yosys) + + (3) (Hey, I'm back) Trying again with yosys updated. + Run ~/gits/openlane/flow.tcl -ignore_mismatches + --> Noted that SYNTH_CAP_LOAD is deprecated. Not sure + why that didn't show up before. . . ? Changed to + OUTPUT_CAP_LOAD as requested, for subsequent runs. + --> Now running and at step 15 and going well so far. + --> Now running and at step 26 and going well so far. + --> Now running and at step 35 and going well so far. + --> Success! + +(28) Now run the project wrapper: + (Will presumably need to copy files from the picosoc synthesis + to the top level before this will work.) + + Copy picosoc LEF, GDS, .lib, and GL verilog; + + cd openlane/openframe_project_wrapper + ~/gits/openlane/flow.tcl -ignore_mismatches + + --> Need to also copy the GDS of vccd1_connection + and vssd1_connection from the "_work" branch. + --> Apparently these files can't be compressed, + either. + --> Also need gate-level .v files for vccd1 and + vssd1 connection. + --> Forgot the picosoc SPEF files. (min, max, nom) + --> Now running without problems. + --> Observation: "Generating lef with Magic" seems + to be taking a rather long time. (But not + ridiculously long, so probably okay.) + + Final solution generated but there are hold violations at the + typical corner. (Single violation clk on gpio_in[38] to + openframe_example/_34243_) diff --git a/gds/vccd1_connection.gds b/gds/vccd1_connection.gds new file mode 100644 index 0000000..a9d341c Binary files /dev/null and b/gds/vccd1_connection.gds differ diff --git a/gds/vssd1_connection.gds b/gds/vssd1_connection.gds new file mode 100644 index 0000000..2897e55 Binary files /dev/null and b/gds/vssd1_connection.gds differ diff --git a/openlane/digital_locked_loop/config.tcl b/openlane/digital_locked_loop/config.tcl index 0b0f1ff..1ba50b8 100644 --- a/openlane/digital_locked_loop/config.tcl +++ b/openlane/digital_locked_loop/config.tcl @@ -21,7 +21,11 @@ set ::env(VERILOG_FILES) "\ set ::env(CLOCK_PORT) "" set ::env(RUN_CTS) 0 +# Linting +set ::env(RUN_VERILATOR) 0 + # Synthesis +set ::env(SYNTH_CAP_LOAD) 52 set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_MAX_FANOUT) 7 set ::env(SYNTH_BUFFERING) 0 @@ -67,6 +71,9 @@ set ::env(GRT_REPAIR_ANTENNAS) 1 set ::env(RUN_HEURISTIC_DIODE_INSERTION) 1 set ::env(HEURISTIC_ANTENNA_THRESHOLD) 80 -set ::env(STA_WRITE_LIB) 0 +set ::env(STA_WRITE_LIB) 1 set ::env(FP_PDN_SKIPTRIM) 1 +# ERC +set ::env(RUN_CVC) 0 + diff --git a/openlane/picosoc/config.json b/openlane/picosoc/config.json index e4fde80..0846cee 100644 --- a/openlane/picosoc/config.json +++ b/openlane/picosoc/config.json @@ -22,6 +22,7 @@ "QUIT_ON_SYNTH_CHECKS": false, "SYNTH_READ_BLACKBOX_LIB": 1, "SYNTH_STRATEGY": "DELAY 0", + "OUTPUT_CAP_LOAD": 52, "MAX_TRANSITION_CONSTRAINT": 0.8, "MAX_FANOUT_CONSTRAINT": 16, "ROUTING_CORES": 16, @@ -79,6 +80,7 @@ "FP_PDN_CFG": "dir::pdn_cfg.tcl", "FP_PDN_MACRO_HOOKS": "soc_mem\\.mem\\.SRAM_0 VPWR VGND vccd1 vssd1, soc_mem\\.mem\\.SRAM_1 VPWR VGND vccd1 vssd1, dll VPWR VGND vccd1 vssd1", "RUN_CTS": 1, + "RUN_LINTER": 0, "CTS_CLK_MAX_WIRE_LENGTH": 500, "CLOCK_PORT": "gpio_in[38]", "PL_TARGET_DENSITY": 0.28, diff --git a/verilog/gl/vccd1_connection.v b/verilog/gl/vccd1_connection.v new file mode 100644 index 0000000..52f41c2 --- /dev/null +++ b/verilog/gl/vccd1_connection.v @@ -0,0 +1,2 @@ +module vccd1_connection (); +endmodule \ No newline at end of file diff --git a/verilog/gl/vssd1_connection.v b/verilog/gl/vssd1_connection.v new file mode 100644 index 0000000..9b959dd --- /dev/null +++ b/verilog/gl/vssd1_connection.v @@ -0,0 +1,2 @@ +module vssd1_connection (); +endmodule \ No newline at end of file diff --git a/verilog/rtl/picosoc.v b/verilog/rtl/picosoc.v index b2c4b5c..d9ab90b 100644 --- a/verilog/rtl/picosoc.v +++ b/verilog/rtl/picosoc.v @@ -44,6 +44,7 @@ /* macro instances in mem_wb.v. 1024 words = 4kB (2 2kB SRAM modules) */ `define MEM_WORDS 1024 `ifndef COCOTB_SIM +`ifndef PnR `include "picorv32.v" `include "spimemio.v" `include "simpleuart.v" @@ -61,6 +62,7 @@ `ifdef SIM `include "libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v" `endif +`endif // PnR `endif // COCOTB_SIM /*--------------------------------------------------------------*/