PDIAG shold be connect to all IDE ports

[LordZodiac76]

Hi Jason,

in the german A1K forum i have found a hint that all IDE PDIAG connections should be connected so all IDE devices can communicate with each other.

https://www.a1k.org/forum/index.php?threads/78485/page-73#post-1781294
https://www.a1k.org/forum/index.php?threads/78485/page-74#post-1781338

cheers Marco

[jasonsbeer]

Thanks for pointing that out. They are correct. I'll mark this as an enhancement as it seems to work without this connection. If there are some issues that can be attributed to this, I will move it to bug.

From the ATA-4 Spec:

Device 0 shall sample PDIAG- for assertion by Device 1. Device 0 may sample PDIAG- at any
frequency. This sampling shall not begin until at least 1 ms after RESET- is negated. Device 0 may
stop sampling PDIAG- upon detection of its assertion. The last sample of PDIAG- by Device 0 shall
occur no sooner than 450 ms after RESET- is negated if assertion has not been detected before this
time. Device 0 shall not sample PDIAG- later than 31 s after RESET- is negated;

1. If Device 0 detects that PDIAG- is asserted within 31 s after RESET- is negated, then Device 0 shall
   clear bit 7 to zero in the Error register;
2. If Device 0 does not detect that PDIAG- is asserted within 31 s after RESET- is negated, then
   Device 0 shall set bit 7 to one in the Error register;