diff --git a/.github/scripts/antivirus_scan.py b/.github/scripts/antivirus_scan.py new file mode 100644 index 00000000..afd74940 --- /dev/null +++ b/.github/scripts/antivirus_scan.py @@ -0,0 +1,86 @@ +#!/usr/bin/env python +# -*- python -*- +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +from pathlib import Path +import platform +import re +import sys +import os +import utils +import argparse + +def setup(): + """This function sets up the script env according to cmd line knobs.""" + parser = argparse.ArgumentParser(description='anti-virus scan argument parser') + parser.add_argument('--path', + dest='av_path', + help='Path to anti-virus scan', + type=Path, + default='') + env = vars(parser.parse_args()) + return env + +def get_infected_files(avscan_path: Path) -> int: + """ + Returns the number of possibly infected files + + Args: + avscan_path (Path): a path to malware scan results file + """ + with open(avscan_path, 'r') as f: + lines = f.readlines() + + pattern = r"Possibly Infected:.............\s+(\d+)$" + + for line in lines: + line = " ".join(line.split()) + match = re.match(pattern, line) + if match: + return int(match.group(1)) + + assert False, 'Malware scan summary not found.' # normally shouldn't get here + + +if __name__ == '__main__': + + env = setup() + + os.makedirs('logs', exist_ok=True) + avscan_res_path = Path('logs', 'avscan.txt') + avscan_sum_path = Path('logs', 'antivirus_summary.txt') + # delete previous anti-virus scan results and summary + if avscan_res_path.exists(): os.remove(avscan_res_path) + if avscan_sum_path.exists(): os.remove(avscan_sum_path) + + os = platform.system() + + assert os == 'Linux', 'Anti-virus scan is currently only supported on Linux' + + avargs = '--VERBOSE --RECURSIVE --SUMMARY' + av_scan_cmd = f"{env['av_path']} {avargs} {Path('./')} > {avscan_res_path}" + retval, retlines = utils.run_subprocess(av_scan_cmd) + + # the summary yields number of suspicious files + infected_files = get_infected_files(avscan_res_path) + + with open(avscan_sum_path, 'w') as f: + f.write(f'{infected_files} possibly infected files.') + + sys.exit(retval) diff --git a/.github/workflows/sanity_external.yml b/.github/workflows/sanity_external.yml index a5e8e35d..c025b8e6 100644 --- a/.github/workflows/sanity_external.yml +++ b/.github/workflows/sanity_external.yml @@ -99,3 +99,49 @@ jobs: run: | cd xed python3 .github/scripts/sanity_external.py + + # Malware scan + anti_virus_scan: + needs: init + runs-on: + - self-hosted + - xed-runners + - Linux + env: + AV_SCAN_PATH: ${{ secrets.AV_SCAN_PATH }} + steps: + - name: Checkout + uses: actions/checkout@v3 + with: + path: xed + fetch-depth: 0 + - name: Checkout mbuild + uses: actions/checkout@v3 + with: + repository: intel-innersource/libraries.isa.xed.mbuild + ref: ${{ needs.init.outputs.mbuild_branch }} + path: mbuild + token: ${{ secrets.PAT }} + - name: anti-virus check + run: | + cd xed + python3 .github/scripts/antivirus_scan.py --path "${AV_SCAN_PATH}" + - name: upload full results # uploads anti-virus scan results as artifact + id: upload + uses: actions/upload-artifact@v3 + with: + name: anti-virus-sum + path: xed/logs/avscan.txt + - name: add comment # uploads anti-virus scan summary as pull-request comment + uses: actions/github-script@v6 + if: github.event_name == 'pull_request' # add scan summary as comment only if there is a PR + with: + script: | + const fs = require('fs'); + const antivirusSummary = fs.readFileSync('xed/logs/antivirus_summary.txt', 'utf8'); + github.rest.issues.createComment({ + issue_number: context.issue.number, + owner: context.repo.owner, + repo: context.repo.repo, + body: "Anti-virus scan summary: " + antivirusSummary + }) diff --git a/VERSION b/VERSION index e45eb9df..0acf299d 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -v2023.06.07 +v2023.07.09 diff --git a/datafiles/arrow-lake/arrow-lake-chips.txt b/datafiles/arrow-lake/arrow-lake-chips.txt new file mode 100644 index 00000000..8c693d71 --- /dev/null +++ b/datafiles/arrow-lake/arrow-lake-chips.txt @@ -0,0 +1,29 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +ARROW_LAKE: \ + ALL_OF(ALDER_LAKE) \ + AVX_IFMA \ + AVX_VNNI_INT8 \ + AVX_NE_CONVERT \ + CMPCCXADD \ + UINTR \ + AVX_VNNI_INT16 \ + SM3 \ + SM4 \ + SHA512 diff --git a/datafiles/arrow-lake/files.cfg b/datafiles/arrow-lake/files.cfg new file mode 100644 index 00000000..38496e40 --- /dev/null +++ b/datafiles/arrow-lake/files.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models: arrow-lake-chips.txt + diff --git a/datafiles/avx-vnni-int16/avx-vnni-int16-element-types.txt b/datafiles/avx-vnni-int16/avx-vnni-int16-element-types.txt new file mode 100644 index 00000000..35962aab --- /dev/null +++ b/datafiles/avx-vnni-int16/avx-vnni-int16-element-types.txt @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#XTYPE TYPE BITS-PER-ELEM +2i16 INT 32 +2u16 UINT 32 + + diff --git a/datafiles/avx-vnni-int16/avx-vnni-int16-isa.xed.txt b/datafiles/avx-vnni-int16/avx-vnni-int16-isa.xed.txt new file mode 100644 index 00000000..27d1d342 --- /dev/null +++ b/datafiles/avx-vnni-int16/avx-vnni-int16-isa.xed.txt @@ -0,0 +1,363 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VPDPWSUD (VPDPWSUD-128-2) +{ +ICLASS: VPDPWSUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 REG2=XMM_B():r:dq:2u16 +IFORM: VPDPWSUD_XMMi32_XMM2i16_XMM2u16 +} + +{ +ICLASS: VPDPWSUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 MEM0:r:dq:2u16 +IFORM: VPDPWSUD_XMMi32_XMM2i16_MEM2u16 +} + + +# EMITTING VPDPWSUD (VPDPWSUD-256-2) +{ +ICLASS: VPDPWSUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2i16 REG2=YMM_B():r:qq:2u16 +IFORM: VPDPWSUD_YMMi32_YMM2i16_YMM2u16 +} + +{ +ICLASS: VPDPWSUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2i16 MEM0:r:qq:2u16 +IFORM: VPDPWSUD_YMMi32_YMM2i16_MEM2u16 +} + + +# EMITTING VPDPWSUDS (VPDPWSUDS-128-2) +{ +ICLASS: VPDPWSUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 REG2=XMM_B():r:dq:2u16 +IFORM: VPDPWSUDS_XMMi32_XMM2i16_XMM2u16 +} + +{ +ICLASS: VPDPWSUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 MEM0:r:dq:2u16 +IFORM: VPDPWSUDS_XMMi32_XMM2i16_MEM2u16 +} + + +# EMITTING VPDPWSUDS (VPDPWSUDS-256-2) +{ +ICLASS: VPDPWSUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2i16 REG2=YMM_B():r:qq:2u16 +IFORM: VPDPWSUDS_YMMi32_YMM2i16_YMM2u16 +} + +{ +ICLASS: VPDPWSUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2i16 MEM0:r:qq:2u16 +IFORM: VPDPWSUDS_YMMi32_YMM2i16_MEM2u16 +} + + +# EMITTING VPDPWUSD (VPDPWUSD-128-2) +{ +ICLASS: VPDPWUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2i16 +IFORM: VPDPWUSD_XMMi32_XMM2u16_XMM2i16 +} + +{ +ICLASS: VPDPWUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2i16 +IFORM: VPDPWUSD_XMMi32_XMM2u16_MEM2i16 +} + + +# EMITTING VPDPWUSD (VPDPWUSD-256-2) +{ +ICLASS: VPDPWUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2i16 +IFORM: VPDPWUSD_YMMi32_YMM2u16_YMM2i16 +} + +{ +ICLASS: VPDPWUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2i16 +IFORM: VPDPWUSD_YMMi32_YMM2u16_MEM2i16 +} + + +# EMITTING VPDPWUSDS (VPDPWUSDS-128-2) +{ +ICLASS: VPDPWUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2i16 +IFORM: VPDPWUSDS_XMMi32_XMM2u16_XMM2i16 +} + +{ +ICLASS: VPDPWUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2i16 +IFORM: VPDPWUSDS_XMMi32_XMM2u16_MEM2i16 +} + + +# EMITTING VPDPWUSDS (VPDPWUSDS-256-2) +{ +ICLASS: VPDPWUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2i16 +IFORM: VPDPWUSDS_YMMi32_YMM2u16_YMM2i16 +} + +{ +ICLASS: VPDPWUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2i16 +IFORM: VPDPWUSDS_YMMi32_YMM2u16_MEM2i16 +} + + +# EMITTING VPDPWUUD (VPDPWUUD-128-2) +{ +ICLASS: VPDPWUUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2u16 +IFORM: VPDPWUUD_XMMu32_XMM2u16_XMM2u16 +} + +{ +ICLASS: VPDPWUUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2u16 +IFORM: VPDPWUUD_XMMu32_XMM2u16_MEM2u16 +} + + +# EMITTING VPDPWUUD (VPDPWUUD-256-2) +{ +ICLASS: VPDPWUUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2u16 +IFORM: VPDPWUUD_YMMu32_YMM2u16_YMM2u16 +} + +{ +ICLASS: VPDPWUUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD2 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2u16 +IFORM: VPDPWUUD_YMMu32_YMM2u16_MEM2u16 +} + + +# EMITTING VPDPWUUDS (VPDPWUUDS-128-2) +{ +ICLASS: VPDPWUUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2u16 +IFORM: VPDPWUUDS_XMMu32_XMM2u16_XMM2u16 +} + +{ +ICLASS: VPDPWUUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2u16 +IFORM: VPDPWUUDS_XMMu32_XMM2u16_MEM2u16 +} + + +# EMITTING VPDPWUUDS (VPDPWUUDS-256-2) +{ +ICLASS: VPDPWUUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2u16 +IFORM: VPDPWUUDS_YMMu32_YMM2u16_YMM2u16 +} + +{ +ICLASS: VPDPWUUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT16 +ISA_SET: AVX_VNNI_INT16 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xD3 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2u16 +IFORM: VPDPWUUDS_YMMu32_YMM2u16_MEM2u16 +} + + diff --git a/datafiles/avx-vnni-int16/cpuid.xed.txt b/datafiles/avx-vnni-int16/cpuid.xed.txt new file mode 100644 index 00000000..9a0d421c --- /dev/null +++ b/datafiles/avx-vnni-int16/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_AVX_VNNI_INT16: avx_vnni_int16.7.1.edx.10 diff --git a/datafiles/avx-vnni-int16/files.cfg b/datafiles/avx-vnni-int16/files.cfg new file mode 100644 index 00000000..22f19678 --- /dev/null +++ b/datafiles/avx-vnni-int16/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + cpuid : cpuid.xed.txt + dec-instructions: avx-vnni-int16-isa.xed.txt + enc-instructions: avx-vnni-int16-isa.xed.txt + element-types: avx-vnni-int16-element-types.txt diff --git a/datafiles/lunar-lake/files.cfg b/datafiles/lunar-lake/files.cfg new file mode 100644 index 00000000..7f186a56 --- /dev/null +++ b/datafiles/lunar-lake/files.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models: lunar-lake-chips.txt + diff --git a/datafiles/lunar-lake/lunar-lake-chips.txt b/datafiles/lunar-lake/lunar-lake-chips.txt new file mode 100644 index 00000000..97b199a8 --- /dev/null +++ b/datafiles/lunar-lake/lunar-lake-chips.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +LUNAR_LAKE: \ + ALL_OF(ARROW_LAKE) \ + PBNDKB diff --git a/datafiles/pbndkb/cpuid.xed.txt b/datafiles/pbndkb/cpuid.xed.txt new file mode 100644 index 00000000..d6c72a1b --- /dev/null +++ b/datafiles/pbndkb/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_PBNDKB: pbndkb.7.1.ebx.1 diff --git a/datafiles/pbndkb/files.cfg b/datafiles/pbndkb/files.cfg new file mode 100644 index 00000000..55cf2b66 --- /dev/null +++ b/datafiles/pbndkb/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + cpuid : cpuid.xed.txt + dec-instructions: pbndkb-isa.xed.txt + enc-instructions: pbndkb-isa.xed.txt + diff --git a/datafiles/pbndkb/pbndkb-isa.xed.txt b/datafiles/pbndkb/pbndkb-isa.xed.txt new file mode 100644 index 00000000..73f8aa50 --- /dev/null +++ b/datafiles/pbndkb/pbndkb-isa.xed.txt @@ -0,0 +1,41 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING PBNDKB (PBNDKB-N/A-1) +{ +ICLASS: PBNDKB +CPL: 0 +CATEGORY: PBNDKB +EXTENSION: PBNDKB +ISA_SET: PBNDKB +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b111] no_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RAX:w:SUPP:q:u64 REG1=XED_REG_RBX:r:SUPP:q:u64 REG2=XED_REG_RCX:r:SUPP:q:u64 +IFORM: PBNDKB +} + + diff --git a/datafiles/sha512/cpuid.xed.txt b/datafiles/sha512/cpuid.xed.txt new file mode 100644 index 00000000..4b9372a4 --- /dev/null +++ b/datafiles/sha512/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_SHA512 : sha512.7.1.eax.0 avx.1.0.ecx.28 diff --git a/datafiles/sha512/files.cfg b/datafiles/sha512/files.cfg new file mode 100644 index 00000000..ad660856 --- /dev/null +++ b/datafiles/sha512/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + cpuid : cpuid.xed.txt + dec-instructions: sha512-isa.xed.txt + enc-instructions: sha512-isa.xed.txt diff --git a/datafiles/sha512/sha512-isa.xed.txt b/datafiles/sha512/sha512-isa.xed.txt new file mode 100644 index 00000000..27ad29a2 --- /dev/null +++ b/datafiles/sha512/sha512-isa.xed.txt @@ -0,0 +1,72 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VSHA512MSG1 (VSHA512MSG1-256-1) +{ +ICLASS: VSHA512MSG1 +CPL: 3 +CATEGORY: SHA512 +EXTENSION: SHA512 +ISA_SET: SHA512 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xCC VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=XMM_B():r:dq:u64 +IFORM: VSHA512MSG1_YMMu64_XMMu64 +} + + +# EMITTING VSHA512MSG2 (VSHA512MSG2-256-1) +{ +ICLASS: VSHA512MSG2 +CPL: 3 +CATEGORY: SHA512 +EXTENSION: SHA512 +ISA_SET: SHA512 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xCD VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_B():r:qq:u64 +IFORM: VSHA512MSG2_YMMu64_YMMu64 +} + + +# EMITTING VSHA512RNDS2 (VSHA512RNDS2-256-1) +{ +ICLASS: VSHA512RNDS2 +CPL: 3 +CATEGORY: SHA512 +EXTENSION: SHA512 +ISA_SET: SHA512 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xCB VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:dq:u64 +IFORM: VSHA512RNDS2_YMMu64_YMMu64_XMMu64 +} + + diff --git a/datafiles/sm3/cpuid.xed.txt b/datafiles/sm3/cpuid.xed.txt new file mode 100644 index 00000000..0b2bbdc1 --- /dev/null +++ b/datafiles/sm3/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_SM3: sm3.7.1.eax.1 avx.1.0.ecx.28 diff --git a/datafiles/sm3/files.cfg b/datafiles/sm3/files.cfg new file mode 100644 index 00000000..579d4d1d --- /dev/null +++ b/datafiles/sm3/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + cpuid : cpuid.xed.txt + dec-instructions: sm3-isa.xed.txt + enc-instructions: sm3-isa.xed.txt diff --git a/datafiles/sm3/sm3-isa.xed.txt b/datafiles/sm3/sm3-isa.xed.txt new file mode 100644 index 00000000..2746b94a --- /dev/null +++ b/datafiles/sm3/sm3-isa.xed.txt @@ -0,0 +1,111 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VSM3MSG1 (VSM3MSG1-128-1) +{ +ICLASS: VSM3MSG1 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM3 +ISA_SET: SM3 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VSM3MSG1_XMMu32_XMMu32_XMMu32 +} + +{ +ICLASS: VSM3MSG1 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM3 +ISA_SET: SM3 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VSM3MSG1_XMMu32_XMMu32_MEMu32 +} + + +# EMITTING VSM3MSG2 (VSM3MSG2-128-1) +{ +ICLASS: VSM3MSG2 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM3 +ISA_SET: SM3 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDA V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VSM3MSG2_XMMu32_XMMu32_XMMu32 +} + +{ +ICLASS: VSM3MSG2 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM3 +ISA_SET: SM3 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VSM3MSG2_XMMu32_XMMu32_MEMu32 +} + + +# EMITTING VSM3RNDS2 (VSM3RNDS2-128-1) +{ +ICLASS: VSM3RNDS2 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM3 +ISA_SET: SM3 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b +IFORM: VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8 +} + +{ +ICLASS: VSM3RNDS2 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM3 +ISA_SET: SM3 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8 +} + + diff --git a/datafiles/sm4/cpuid.xed.txt b/datafiles/sm4/cpuid.xed.txt new file mode 100644 index 00000000..da924074 --- /dev/null +++ b/datafiles/sm4/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_SM4: sm4.7.1.eax.2 avx.1.0.ecx.28 + diff --git a/datafiles/sm4/files.cfg b/datafiles/sm4/files.cfg new file mode 100644 index 00000000..f60c3732 --- /dev/null +++ b/datafiles/sm4/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + cpuid : cpuid.xed.txt + dec-instructions: sm4-isa.xed.txt + enc-instructions: sm4-isa.xed.txt diff --git a/datafiles/sm4/sm4-isa.xed.txt b/datafiles/sm4/sm4-isa.xed.txt new file mode 100644 index 00000000..ceffc7b1 --- /dev/null +++ b/datafiles/sm4/sm4-isa.xed.txt @@ -0,0 +1,139 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VSM4KEY4 (VSM4KEY4-128-1) +{ +ICLASS: VSM4KEY4 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM4 +ISA_SET: SM4 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VSM4KEY4_XMMu32_XMMu32_XMMu32 +} + +{ +ICLASS: VSM4KEY4 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM4 +ISA_SET: SM4 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VSM4KEY4_XMMu32_XMMu32_MEMu32 +} + + +# EMITTING VSM4KEY4 (VSM4KEY4-256-1) +{ +ICLASS: VSM4KEY4 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM4 +ISA_SET: SM4 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VSM4KEY4_YMMu32_YMMu32_YMMu32 +} + +{ +ICLASS: VSM4KEY4 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM4 +ISA_SET: SM4 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 +OPERANDS: REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VSM4KEY4_YMMu32_YMMu32_MEMu32 +} + + +# EMITTING VSM4RNDS4 (VSM4RNDS4-128-1) +{ +ICLASS: VSM4RNDS4 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM4 +ISA_SET: SM4 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VSM4RNDS4_XMMu32_XMMu32_XMMu32 +} + +{ +ICLASS: VSM4RNDS4 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM4 +ISA_SET: SM4 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VSM4RNDS4_XMMu32_XMMu32_MEMu32 +} + + +# EMITTING VSM4RNDS4 (VSM4RNDS4-256-1) +{ +ICLASS: VSM4RNDS4 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM4 +ISA_SET: SM4 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VSM4RNDS4_YMMu32_YMMu32_YMMu32 +} + +{ +ICLASS: VSM4RNDS4 +CPL: 3 +CATEGORY: VEX +EXTENSION: SM4 +ISA_SET: SM4 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xDA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 +OPERANDS: REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VSM4RNDS4_YMMu32_YMMu32_MEMu32 +} + + diff --git a/datafiles/srf/srf-chips.txt b/datafiles/srf/srf-chips.txt index 16189a43..878100d1 100644 --- a/datafiles/srf/srf-chips.txt +++ b/datafiles/srf/srf-chips.txt @@ -1,6 +1,6 @@ #BEGIN_LEGAL # -#Copyright (c) 2022 Intel Corporation +#Copyright (c) 2023 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -48,4 +48,6 @@ SIERRA_FOREST: \ AVX_NE_CONVERT \ AVX_VNNI_INT8 \ MSRLIST \ - WRMSRNS \ No newline at end of file + WRMSRNS \ + ENQCMD \ + UINTR diff --git a/pysrc/ild_phash.py b/pysrc/ild_phash.py index c3ecd07a..78ddd0b1 100755 --- a/pysrc/ild_phash.py +++ b/pysrc/ild_phash.py @@ -1,6 +1,6 @@ #BEGIN_LEGAL # -#Copyright (c) 2020 Intel Corporation +#Copyright (c) 2023 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -65,7 +65,7 @@ def add_cgen_key_lines(self, fo): #and RM gets 3 bits shift_val = ('(%s)' % bit_shift) bit_shift += self.cdict.op_widths[cname] - code = 'key += (%s) << (%s)' % (access_str, shift_val) + code = 'key += ((%s) %s) << (%s)' % (key_type, access_str, shift_val) fo.add_code_eol(code) fo.add_code_eol('return %s' % key_str) return nt_lups diff --git a/xed_mbuild.py b/xed_mbuild.py index 8dcf8b3c..666df43e 100755 --- a/xed_mbuild.py +++ b/xed_mbuild.py @@ -626,6 +626,8 @@ def mkenv(): grr=True, # grand ridge srf=True, # sierra forest gnr=True, # granite rapids + arl=True, # arrow lake + lnl=True, # lunar lake future=True, knl=True, knm=True, @@ -871,6 +873,14 @@ def xed_args(env): action="store_false", dest="grr", help="Disable Grand Ridge public instructions") + env.parser.add_option("--no-arl", + action="store_false", + dest="arl", + help="Disable Arrow Lake public instructions") + env.parser.add_option("--no-lnl", + action="store_false", + dest="lnl", + help="Disable Lunar Lake public instructions") env.parser.add_option("--dbghelp", action="store_true", dest="dbghelp", @@ -1517,9 +1527,25 @@ def _add_normal_ext(tenv,x , y='files.cfg'): _add_normal_ext(env,'cmpccxadd') _add_normal_ext(env,'msrlist') _add_normal_ext(env,'wrmsrns') + _add_normal_ext(env,'uintr') + _add_normal_ext(env,'enqcmd') if env['grr']: _add_normal_ext(env,'grr') _add_normal_ext(env,'rao-int') + if env['arl']: + _add_normal_ext(env,'arrow-lake') + _add_normal_ext(env, 'uintr') + _add_normal_ext(env,'avx-ifma') + _add_normal_ext(env,'avx-ne-convert') + _add_normal_ext(env,'avx-vnni-int8') + _add_normal_ext(env,'cmpccxadd') + _add_normal_ext(env,'avx-vnni-int16') + _add_normal_ext(env,'sha512') + _add_normal_ext(env,'sm3') + _add_normal_ext(env,'sm4') + if env['lnl']: + _add_normal_ext(env,'lunar-lake') + _add_normal_ext(env,'pbndkb') if env['future']: _add_normal_ext(env,'future') @@ -2673,7 +2699,7 @@ def run_tests(env): def verify_args(env): if not env['avx']: - mbuild.warn("No AVX -> Disabling SNB, IVB, HSW, BDW, SKL, SKX, CLX, CPX, CNL, ICL, TGL, ADL, SPR, KNL, KNM, GNR, GRR, SRF, Future\n\n\n") + mbuild.warn("No AVX -> Disabling SNB, IVB, HSW, BDW, SKL, SKX, CLX, CPX, CNL, ICL, TGL, ADL, SPR, KNL, KNM, GNR, GRR, SRF, ARL, LNL, Future\n\n\n") env['ivb'] = False env['hsw'] = False env['bdw'] = False @@ -2691,6 +2717,8 @@ def verify_args(env): env['gnr'] = False env['grr'] = False env['srf'] = False + env['arl'] = False + env['lnl'] = False env['future'] = False # default is enabled. oldest disable disables upstream (younger, newer) stuff. @@ -2734,10 +2762,14 @@ def verify_args(env): if not env['tgl']: env['cet'] = False env['spr'] = False + if not env['adl']: + env['arl'] = False if not env['srf']: env['grr'] = False if not env['spr']: env['gnr'] = False + if not env['arl']: + env['lnl'] = False if not env['gnr']: env['future'] = False