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I think it maybe caused by the register spill.
In the composite mode, the private space for spilling maybe always allocated in one tile and all the threads on the other tile has to access the private space across the EMIB bus.
We may need to implement a new softmax kernel which is close to the torch's implementation and re-test the performance.
ZE_FLAT_DEVICE_HIERARCHY=FLAT
ZE_FLAT_DEVICE_HIERARCHY=COMPOSITE
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