From 6ace5c35f8ca19c764c7ca537ca4975e308bf05e Mon Sep 17 00:00:00 2001
From: Duncan Ogilvie <mr.exodia.tpodt@gmail.com>
Date: Tue, 17 Dec 2024 13:57:19 +0100
Subject: [PATCH] WIP

---
 Cargo.toml | 7 ++++++-
 icicle-emu | 2 +-
 src/lib.rs | 9 +++++++--
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index dbe3a35..34c252a 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -15,10 +15,15 @@ icicle-vm = { path = "icicle-emu/icicle-vm" }
 pcode = { path = "icicle-emu/sleigh/pcode" }
 sleigh-runtime = { path = "icicle-emu/sleigh/sleigh-runtime" }
 indexmap = "2.2.6"
-pyo3 = { version = "0.23.2", features = ["extension-module", "indexmap", "abi3-py37"] }
+pyo3 = { version = "0.23.2", features = ["extension-module", "indexmap", "abi3"] }
 target-lexicon = "0.12.7"
 tracing = "*"
 tracing-subscriber = "0.3.17"
 
 [build-dependencies]
 pyo3-build-config = "0.23.2"
+
+# TODO: the bin doesn't build because of https://github.com/PyO3/pyo3/issues/340
+[features]
+extension-module = ["pyo3/extension-module"]
+default = ["extension-module"]
diff --git a/icicle-emu b/icicle-emu
index 964dabb..7f17fc4 160000
--- a/icicle-emu
+++ b/icicle-emu
@@ -1 +1 @@
-Subproject commit 964dabb7276b959d225556ae11a5634f60266611
+Subproject commit 7f17fc4cd09ee868e9225335cf8b66778f500e18
diff --git a/src/lib.rs b/src/lib.rs
index 7b30c3d..54b0f2f 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -334,12 +334,16 @@ impl Icicle {
         config.optimize_instructions = optimize_instructions;
         config.optimize_block = optimize_block;
 
-        let vm = icicle_vm::build(&config)
+        let mut vm = icicle_vm::build(&config)
             .map_err(|e| {
                 PyException::new_err(format!("VM build error: {e}"))
             })?;
 
+        // TODO: export this
+        vm.cpu.mem.set_capacity(250_000_000);
+
         // Populate the lowercase register map
+        // TODO: add support for aliases (like fp and lr for aarch64)
         let mut regs = HashMap::new();
         let sleigh = vm.cpu.sleigh();
         for reg in &sleigh.named_registers {
@@ -455,6 +459,7 @@ impl Icicle {
     }
 
     pub fn reg_write(&mut self, name: &str, value: u64) -> PyResult<()> {
+        // TODO: add aliases for fp and lr (aarch64)
         Ok(self.vm.cpu.write_reg(reg_find(self, name)?.var, value))
     }
 
@@ -524,4 +529,4 @@ fn icicle(m: &Bound<'_, PyModule>) -> PyResult<()> {
     m.add_class::<RunStatus>()?;
     m.add_class::<ExceptionCodePy>()?;
     Ok(())
-}
\ No newline at end of file
+}