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top_level.qsf
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top_level.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2024 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition
# Date created = 09:27:11 July 31, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# top_level_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY top_level
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1STD.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:27:11 JULY 31, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_AB12 -to challenge[0]
set_location_assignment PIN_AC12 -to challenge[1]
set_location_assignment PIN_AF9 -to challenge[2]
set_location_assignment PIN_AF10 -to challenge[3]
set_location_assignment PIN_AD11 -to challenge[4]
set_location_assignment PIN_AD12 -to challenge[5]
set_location_assignment PIN_AE11 -to challenge[6]
set_location_assignment PIN_AC9 -to challenge[7]
set_location_assignment PIN_AE12 -to reset
set_location_assignment PIN_AA14 -to clk
set_location_assignment PIN_AE26 -to segment[0][0]
set_location_assignment PIN_AE27 -to segment[0][1]
set_location_assignment PIN_AE28 -to segment[0][2]
set_location_assignment PIN_AG27 -to segment[0][3]
set_location_assignment PIN_AF28 -to segment[0][4]
set_location_assignment PIN_AG28 -to segment[0][5]
set_location_assignment PIN_AH28 -to segment[0][6]
set_location_assignment PIN_AJ29 -to segment[1][0]
set_location_assignment PIN_AH29 -to segment[1][1]
set_location_assignment PIN_AH30 -to segment[1][2]
set_location_assignment PIN_AG30 -to segment[1][3]
set_location_assignment PIN_AF29 -to segment[1][4]
set_location_assignment PIN_AF30 -to segment[1][5]
set_location_assignment PIN_AD27 -to segment[1][6]
set_location_assignment PIN_AB23 -to segment[2][0]
set_location_assignment PIN_AE29 -to segment[2][1]
set_location_assignment PIN_AD29 -to segment[2][2]
set_location_assignment PIN_AC28 -to segment[2][3]
set_location_assignment PIN_AD30 -to segment[2][4]
set_location_assignment PIN_AC29 -to segment[2][5]
set_location_assignment PIN_AC30 -to segment[2][6]
set_location_assignment PIN_AD26 -to segment[3][0]
set_location_assignment PIN_AC27 -to segment[3][1]
set_location_assignment PIN_AD25 -to segment[3][2]
set_location_assignment PIN_AC25 -to segment[3][3]
set_location_assignment PIN_AB28 -to segment[3][4]
set_location_assignment PIN_AB25 -to segment[3][5]
set_location_assignment PIN_AB22 -to segment[3][6]
set_location_assignment PIN_AA24 -to segment[4][0]
set_location_assignment PIN_Y23 -to segment[4][1]
set_location_assignment PIN_Y24 -to segment[4][2]
set_location_assignment PIN_W22 -to segment[4][3]
set_location_assignment PIN_W24 -to segment[4][4]
set_location_assignment PIN_V23 -to segment[4][5]
set_location_assignment PIN_W25 -to segment[4][6]
set_location_assignment PIN_V25 -to segment[5][0]
set_location_assignment PIN_AA28 -to segment[5][1]
set_location_assignment PIN_Y27 -to segment[5][2]
set_location_assignment PIN_AB27 -to segment[5][3]
set_location_assignment PIN_AB26 -to segment[5][4]
set_location_assignment PIN_AA26 -to segment[5][5]
set_location_assignment PIN_AA25 -to segment[5][6]
set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
set_global_assignment -name SYSTEMVERILOG_FILE fastclk.sv
set_global_assignment -name SYSTEMVERILOG_FILE top_level.sv
set_global_assignment -name SYSTEMVERILOG_FILE shiftreg.sv
set_global_assignment -name SYSTEMVERILOG_FILE sevensegdisp.sv
set_global_assignment -name SYSTEMVERILOG_FILE mux16_1.sv
set_global_assignment -name SYSTEMVERILOG_FILE mux2_1.sv
set_global_assignment -name SYSTEMVERILOG_FILE lut_int.sv
set_global_assignment -name SYSTEMVERILOG_FILE lut.sv
set_global_assignment -name SYSTEMVERILOG_FILE lfsr.sv
set_global_assignment -name SYSTEMVERILOG_FILE d_ff.sv
set_global_assignment -name SYSTEMVERILOG_FILE counter.sv
set_global_assignment -name SYSTEMVERILOG_FILE comparator.sv
set_global_assignment -name SYSTEMVERILOG_FILE chain.sv
set_global_assignment -name SYSTEMVERILOG_FILE arbiter_puf.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top