From 814c703a9e035e1985ee3513c91a400fcd37097a Mon Sep 17 00:00:00 2001
From: hneemann <helmut.neemann@arcor.de>
Date: Mon, 11 Jun 2018 16:43:21 +0200
Subject: [PATCH] updated the release notes

---
 distribution/ReleaseNotes.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/distribution/ReleaseNotes.txt b/distribution/ReleaseNotes.txt
index b1bae2c5f..2cf7bdd3e 100644
--- a/distribution/ReleaseNotes.txt
+++ b/distribution/ReleaseNotes.txt
@@ -4,6 +4,8 @@ HEAD, planned as v0.19
 - Added a tabbed pane to the attributes dialog to make it more beginner friendly.
 - Added support for asynchronous sequential circuits such as the Muller-pipeline.
   Take a look at the new asynchronous examples for illustration.
+- Added export to Verilog. Special thanks to Ivan de Jesus Deras Tabora, who has
+  implemented the Verilog code generator and all the necessary Verilog templates!
 - All examples are translated to english.
 - A "test all" function has been added to start all tests in all circuits in
   the current folder.