diff --git a/distribution/ReleaseNotes.txt b/distribution/ReleaseNotes.txt
index a4a876dfd..cfd822a70 100644
--- a/distribution/ReleaseNotes.txt
+++ b/distribution/ReleaseNotes.txt
@@ -1,12 +1,12 @@
 Release Notes
 
-HEAD, planned as v0.14
+v0.14, released on 31. Aug 2017
+- Added visualization of KV maps (thanks to roy77)
 - Added VHDL export
   (Not yet complete, but the example processor is running on a FPGA.)
 - Type of pin numbers changed from int to string to allow FPGA pin names like "U16".
 - Added support for BASYS3-Board (*.xdc constrains file is written and the mixed mode
   clock manager (MMCM) is used if clock frequency exceeds 37kHz)
-- Added visualization of KV maps (thanks to roy77)
 - Added shortcut 'B' which sets the number of data bits in all selected components.
 - Breaking changes:
   - To generalize the VHDL export, an XML entity in the *.dig files had to be renamed.