From be54870c3b2f7f1c14b0f5527f4928c8a4a4a7ae Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 10:02:24 +0200 Subject: [PATCH 01/40] renesas_ra: add support for HS port --- hw/bsp/ra/family.mk | 2 + src/portable/renesas/rusb2/dcd_rusb2.c | 76 ++++++++++++++++++++++---- src/portable/renesas/rusb2/hcd_rusb2.c | 46 +++++++++++----- src/portable/renesas/rusb2/rusb2_ra.c | 16 ++++++ src/portable/renesas/rusb2/rusb2_ra.h | 37 +++++++++++-- 5 files changed, 147 insertions(+), 30 deletions(-) create mode 100644 src/portable/renesas/rusb2/rusb2_ra.c diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index d48272e61a..3ed17f79f3 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -22,6 +22,7 @@ CFLAGS += \ SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ + src/portable/renesas/rusb2/rusb2_ra.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \ @@ -47,6 +48,7 @@ INC += \ $(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \ $(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \ $(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \ + $(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all \ $(TOP)/$(FSP_MCU_DIR) \ $(TOP)/$(FSP_BOARD_DIR) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 78584125fd..9ae36e2533 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -52,8 +52,10 @@ /* LINK core registers */ #if defined(__CCRX__) #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) +#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE) #else - #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) + #define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE) #endif /* Start of definition of packed structs (used by the CCRX toolchain) */ @@ -81,6 +83,18 @@ typedef union TU_ATTR_PACKED { volatile uint16_t u16; } hw_fifo_t; +typedef union TU_ATTR_PACKED { + struct { + volatile uint32_t : 24; + volatile uint32_t u8: 8; + }; + struct { + volatile uint32_t : 16; + volatile uint32_t u16: 16; + }; + volatile uint32_t u32; +} hw_fifo32_t; + typedef struct TU_ATTR_PACKED { void *buf; /* the start address of a transfer data buffer */ @@ -185,14 +199,18 @@ static inline void pipe_wait_for_ready(unsigned num) static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { +#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo; +#else volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; +#endif uintptr_t addr = (uintptr_t)buf; while (len >= 2) { reg->u16 = *(const uint16_t *)addr; addr += 2; len -= 2; } - if (len) { + if (len > 0) { reg->u8 = *(const uint8_t *)addr; ++addr; } @@ -519,12 +537,17 @@ static void process_bus_reset(uint8_t rhport) ++ctr; } tu_varclr(&_dcd); + +#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, true); +#else dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); +#endif } static void process_set_address(uint8_t rhport) { - const uint32_t addr = RUSB2->USBADDR_b.USBADDR; + const uint32_t addr = RUSB2->USBADDR & 0xFF; if (!addr) return; const tusb_control_request_t setup_packet = { #if defined(__CCRX__) @@ -572,34 +595,53 @@ void dcd_init(uint8_t rhport) { (void)rhport; -#if 0 // previously present in the rx driver before generalization - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); -#endif - +#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + RUSB2->SYSCFG_b.HSE = 1; + RUSB2->PHYSET_b.DIRPD = 0; + R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); + RUSB2->PHYSET_b.PLLRESET = 0; + //RUSB2->PHYSET_b.REPSTART = 1; + RUSB2->SYSCFG_b.DRPD = 0; + RUSB2->SYSCFG_b.USBE = 1; + RUSB2->LPSTS_b.SUSPENDM = 1; + while (!RUSB2->PLLSTA_b.PLLLOCK); + //RUSB2->BUSWAIT |= 0x0F00U; + //RUSB2->PHYSET_b.REPSEL = 1; + RUSB2->CFIFOSEL_b.MBW = 1; + RUSB2->D0FIFOSEL_b.MBW = 1; + RUSB2->D1FIFOSEL_b.MBW = 1; + RUSB2->INTSTS0 = 0; +#else RUSB2->SYSCFG_b.SCKE = 1; while (!RUSB2->SYSCFG_b.SCKE) ; RUSB2->SYSCFG_b.DRPD = 0; RUSB2->SYSCFG_b.DCFM = 0; RUSB2->SYSCFG_b.USBE = 1; +#endif // MCU specific PHY init rusb2_phy_init(); +#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) RUSB2->PHYSLEW = 0x5; RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ + #define USB_VDCEN (0x0080U) /* b7: Regulator ON/OFF control */ + RUSB2->USBMC = (uint16_t) (RUSB2->USBMC | (USB_VDCEN)); +#endif + /* Setup default control pipe */ RUSB2->DCPMAXP_b.MXPS = 64; RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | - RUSB2_INTSTS0_RESM_Msk; + RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk; RUSB2->BEMPENB = 1; RUSB2->BRDYENB = 1; +#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) + RUSB2->SYSCFG_b.DPRPU = 1; /* necessary in this position */ +#endif + if (RUSB2->INTSTS0_b.VBSTS) { dcd_connect(rhport); } @@ -630,6 +672,10 @@ void dcd_remote_wakeup(uint8_t rhport) void dcd_connect(uint8_t rhport) { (void)rhport; + #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + RUSB2->SYSCFG_b.CNEN = 1; + R_BSP_SoftwareDelay((uint32_t) 10, BSP_DELAY_UNITS_MILLISECONDS); + #endif RUSB2->SYSCFG_b.DPRPU = 1; } @@ -672,6 +718,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* setup pipe */ dcd_int_disable(rhport); + #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + RUSB2->PIPEBUF = 0x7C08; + #endif RUSB2->PIPESEL = num; RUSB2->PIPEMAXP = mps; volatile uint16_t *ctr = get_pipectr(num); @@ -826,6 +875,9 @@ void dcd_int_handler(uint8_t rhport) break; } } + if (is0 & RUSB2_INTSTS0_NRDY_Msk) { + RUSB2->NRDYSTS = 0; + } if (is0 & RUSB2_INTSTS0_CTRT_Msk) { if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) { /* A setup packet has been received. */ diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index e4743223e7..03811d63f3 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -48,8 +48,10 @@ /* LINK core registers */ #if defined(__CCRX__) #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) +#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) + #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE) #else - #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) + #define RUSB2 ((R_USB_FS0_Type*) R_USB_FS0_BASE) #endif TU_ATTR_PACKED_BEGIN @@ -477,31 +479,49 @@ bool hcd_init(uint8_t rhport) { (void)rhport; -#if 0 // previously present in the rx driver before generalization - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); -#endif - - RUSB2->SYSCFG_b.SCKE = 1; - while (!RUSB2->SYSCFG_b.SCKE) ; - RUSB2->SYSCFG_b.DPRPU = 0; - RUSB2->SYSCFG_b.DRPD = 0; +#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) + RUSB2->SYSCFG_b.HSE = 1; + RUSB2->PHYSET_b.HSEB = 0; + RUSB2->PHYSET_b.DIRPD = 0; + R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); + RUSB2->PHYSET_b.PLLRESET = 0; + RUSB2->LPSTS_b.SUSPENDM = 1; + while (!RUSB2->PLLSTA_b.PLLLOCK); + RUSB2->SYSCFG_b.DRPD = 1; RUSB2->SYSCFG_b.DCFM = 1; + RUSB2->SYSCFG_b.DPRPU = 0; + RUSB2->SYSCFG_b.CNEN = 1; + RUSB2->BUSWAIT |= 0x0F00U; + RUSB2->SOFCFG_b.INTL = 1; + RUSB2->DVSTCTR0_b.VBUSEN = 1; + RUSB2->CFIFOSEL_b.MBW = 1; + RUSB2->D0FIFOSEL_b.MBW = 1; + RUSB2->D1FIFOSEL_b.MBW = 1; + RUSB2->INTSTS0 = 0; + for (volatile int i = 0; i < 30000; ++i) ; + RUSB2->SYSCFG_b.USBE = 1; +#else + /* HOST DEVICE Full SPEED */ + RUSB2->SYSCFG_b.SCKE = 1; /* USB Clock enable */ + while (!RUSB2->SYSCFG_b.SCKE) ; + RUSB2->SYSCFG_b.DPRPU = 0; /* D+ pull up enable - 0/disable in host mode */ + RUSB2->SYSCFG_b.DRPD = 1; /* D+/D- pull down - 1/in Host mode (pag.834)*/ + RUSB2->SYSCFG_b.DCFM = 1; /* HOST or Device - 1/HOST */ RUSB2->DVSTCTR0_b.VBUSEN = 1; RUSB2->SYSCFG_b.DRPD = 1; for (volatile int i = 0; i < 30000; ++i) ; RUSB2->SYSCFG_b.USBE = 1; +#endif // MCU specific PHY init rusb2_phy_init(); +#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) RUSB2->PHYSLEW = 0x5; RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ +#endif /* Setup default control pipe */ RUSB2->DCPCFG = RUSB2_PIPECFG_SHTNAK_Msk; diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c new file mode 100644 index 0000000000..2b6ce7b2fc --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_ra.c @@ -0,0 +1,16 @@ +#include "tusb_option.h" +#include "rusb2_ra.h" + +#ifdef CFG_TUSB_RHPORT0_MODE +IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn; +void tud_set_irq_usbfs(IRQn_Type q) { + _usb_fs_irqn = q; +} +#endif + +#ifdef CFG_TUSB_RHPORT1_MODE +IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn; +void tud_set_irq_usbhs(IRQn_Type q) { + _usb_hs_irqn = q; +} +#endif \ No newline at end of file diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 5785850ccf..b18b506e5c 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -34,18 +34,45 @@ extern "C" { /* renesas fsp api */ #include "bsp_api.h" -#define RUSB2_REG_BASE (0x40090000) +extern IRQn_Type _usb_fs_irqn; +extern IRQn_Type _usb_hs_irqn; TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { - (void) rhport; - NVIC_EnableIRQ(TU_IRQn); +#ifdef CFG_TUSB_RHPORT1_MODE +#if (CFG_TUSB_RHPORT1_MODE != 0) + if (rhport == 1) { + NVIC_EnableIRQ(_usb_hs_irqn); + } +#endif +#endif + +#ifdef CFG_TUSB_RHPORT0_MODE +#if (CFG_TUSB_RHPORT0_MODE != 0) + if (rhport == 0) { + NVIC_EnableIRQ(_usb_fs_irqn); + } +#endif +#endif } TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { - (void) rhport; - NVIC_DisableIRQ(TU_IRQn); +#ifdef CFG_TUSB_RHPORT1_MODE +#if (CFG_TUSB_RHPORT1_MODE != 0) + if (rhport == 1) { + NVIC_DisableIRQ(_usb_hs_irqn); + } +#endif +#endif + +#ifdef CFG_TUSB_RHPORT0_MODE +#if (CFG_TUSB_RHPORT0_MODE != 0) + if (rhport == 0) { + NVIC_DisableIRQ(_usb_fs_irqn); + } +#endif +#endif } // MCU specific PHY init From 4afed62646d18dd96eef619d7d21b47a2422672f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 10:05:29 +0200 Subject: [PATCH 02/40] renesas_ra: host: handle retry on attach() --- src/portable/renesas/rusb2/hcd_rusb2.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 03811d63f3..9dd4f0a487 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -759,9 +759,10 @@ void hcd_int_handler(uint8_t rhport) 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, 20, 8, 19, 18}; #endif - + static unsigned char attach_attempt = 0; unsigned is1 = RUSB2->INTSTS1; unsigned is0 = RUSB2->INTSTS0; + /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); @@ -772,12 +773,21 @@ void hcd_int_handler(uint8_t rhport) if (is1 & RUSB2_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ RUSB2->DCPCTR_b.SQSET = 1; + attach_attempt = 0; hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } if (is1 & RUSB2_INTSTS1_SIGN_Msk) { hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); + if(attach_attempt > 0) { + RUSB2->DVSTCTR0_b.UACT = 1; + _hcd.need_reset = true; + RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; + hcd_event_device_attach(rhport, true); + } + attach_attempt--; } if (is1 & RUSB2_INTSTS1_ATTCH_Msk) { + attach_attempt = 10; RUSB2->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; From 5f7e7b4b0a9f65a401c679d5045b96b4b56755df Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 10:06:13 +0200 Subject: [PATCH 03/40] renesas_ra: support RA2A1 (FS only) --- src/portable/renesas/rusb2/dcd_rusb2.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 9ae36e2533..f3bda52059 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -41,6 +41,15 @@ #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) #include "rusb2_ra.h" + #if defined(RENESAS_CORTEX_M23) + #define D0FIFO CFIFO + #define D0FIFOSEL CFIFOSEL + #define D0FIFOSEL_b CFIFOSEL_b + #define D1FIFOSEL CFIFOSEL + #define D1FIFOSEL_b CFIFOSEL_b + #define D0FIFOCTR CFIFOCTR + #define D0FIFOCTR_b CFIFOCTR_b + #endif #else #error "Unsupported MCU" #endif @@ -121,6 +130,10 @@ typedef struct //--------------------------------------------------------------------+ static dcd_data_t _dcd; +#ifndef FIRST_BULK_PIPE +#define FIRST_BULK_PIPE 3 +#endif + static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -130,7 +143,7 @@ static unsigned find_pipe(unsigned xfer) } break; case TUSB_XFER_BULK: - for (int i = 3; i <= 5; ++i) { + for (int i = FIRST_BULK_PIPE; i <= 5; ++i) { if (0 == _dcd.pipe[i].ep) return i; } for (int i = 1; i <= 1; ++i) { From a349869906a41f959103b7aead2a1fd839773581 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 10:06:58 +0200 Subject: [PATCH 04/40] renesas_ra: fix existing boards support --- hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h | 2 +- hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c | 2 +- hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h | 2 +- hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h index 37739c12a3..4719e22e69 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h @@ -1,5 +1,5 @@ /* vector numbers are configurable/dynamic, hence this, it will be used inside the port */ -#define TU_IRQn 0 +#define USBFS_INT_IRQn 0 #define USBFS_RESUME_IRQn 1 #define USBFS_FIFO_0_IRQn 2 #define USBFS_FIFO_1_IRQn 3 diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c index ea22048374..300cf61780 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c +++ b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c @@ -151,7 +151,7 @@ void board_init(void) #if CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h index 37739c12a3..4719e22e69 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h @@ -1,5 +1,5 @@ /* vector numbers are configurable/dynamic, hence this, it will be used inside the port */ -#define TU_IRQn 0 +#define USBFS_INT_IRQn 0 #define USBFS_RESUME_IRQn 1 #define USBFS_FIFO_0_IRQn 2 #define USBFS_FIFO_1_IRQn 3 diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c index 327ef71d59..b682280080 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c +++ b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c @@ -153,7 +153,7 @@ void board_init(void) #if CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); From 6ff62c0fe85e825d077d7d803c657181769e542f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 11:47:41 +0200 Subject: [PATCH 05/40] renesas: add fallback for targets not defining CFG_TUSB_RHPORT*_MODE --- src/portable/renesas/rusb2/dcd_rusb2.c | 5 +++++ src/portable/renesas/rusb2/hcd_rusb2.c | 5 +++++ src/portable/renesas/rusb2/rusb2_ra.h | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index f3bda52059..f509dcc568 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -37,6 +37,11 @@ #include "device/dcd.h" #include "rusb2_type.h" +#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) +// fallback +#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE +#endif + #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 9dd4f0a487..1ec25f1e20 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -33,6 +33,11 @@ #include "host/hcd.h" #include "rusb2_type.h" +#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) +// fallback +#define CFG_TUSB_RHPORT0_MODE OPT_MODE_HOST +#endif + #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index b18b506e5c..874492304e 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -37,6 +37,11 @@ extern "C" { extern IRQn_Type _usb_fs_irqn; extern IRQn_Type _usb_hs_irqn; +#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) +// fallback +#define CFG_TUSB_RHPORT0_MODE ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST ) +#endif + TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { #ifdef CFG_TUSB_RHPORT1_MODE From 161c95f1b7d63394b184a351f7bbaa54841c02f6 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 4 May 2023 14:42:32 +0200 Subject: [PATCH 06/40] renesas: update fsp to 4.0.0 --- tools/get_deps.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/get_deps.py b/tools/get_deps.py index d8b0443437..4f2f7b0890 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -27,7 +27,7 @@ 'hw/mcu/nxp/mcux-sdk' : ['f357a1150f6cf6c6b844f53f2d426bfb3e649850', 'https://github.com/NXPmicro/mcux-sdk.git' ], 'hw/mcu/nxp/nxp_sdk' : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git' ], 'hw/mcu/raspberry_pi/Pico-PIO-USB' : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git' ], - 'hw/mcu/renesas/fsp' : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git' ], + 'hw/mcu/renesas/fsp' : ['9860fae1f180340a0e3c097dc6e91323cf83b926', 'https://github.com/renesas/fsp.git' ], 'hw/mcu/renesas/rx' : ['706b4e0cf485605c32351e2f90f5698267996023', 'https://github.com/kkitayam/rx_device.git' ], 'hw/mcu/silabs/cmsis-dfp-efm32gg12b' : ['f1c31b7887669cb230b3ea63f9b56769078960bc', 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git' ], 'hw/mcu/sony/cxd56/spresense-exported-sdk' : ['2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'https://github.com/sonydevworld/spresense-exported-sdk.git' ], From 32f9f452afc4d431d51cb16a02f99d76c88f7fb9 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 17 May 2023 12:13:25 +0200 Subject: [PATCH 07/40] renesas: provide default for CFG_TUSB_RHPORT1_MODE Should fix CI failure for Renesas RX family --- src/portable/renesas/rusb2/dcd_rusb2.c | 1 + src/portable/renesas/rusb2/hcd_rusb2.c | 1 + src/portable/renesas/rusb2/rusb2_ra.h | 1 + 3 files changed, 3 insertions(+) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index f509dcc568..2653d0da6a 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -40,6 +40,7 @@ #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) // fallback #define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE +#define CFG_TUSB_RHPORT1_MODE 0 #endif #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 1ec25f1e20..1e26c931d0 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -36,6 +36,7 @@ #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) // fallback #define CFG_TUSB_RHPORT0_MODE OPT_MODE_HOST +#define CFG_TUSB_RHPORT1_MODE 0 #endif #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 874492304e..a1c58abe5e 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -40,6 +40,7 @@ extern IRQn_Type _usb_hs_irqn; #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) // fallback #define CFG_TUSB_RHPORT0_MODE ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST ) +#define CFG_TUSB_RHPORT1_MODE 0 #endif TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) From cdae66c8371e1c73d28279462fa8598a9daae5a7 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 5 Jun 2023 09:04:52 +0200 Subject: [PATCH 08/40] renesas_rx: fix compilation on latest GCC __CCRX__ only applyes to version 4 of RX family compiler http://tool-support.renesas.com/autoupdate/support/onlinehelp/csp/V4.01.00/CS+.chm/Compiler-CCRX.chm/Output/ccrx04c0201y.html __RX__ is one of the macros exported by latest gcc (gcc_8.3.0.202305_rx_elf) --- src/portable/renesas/rusb2/dcd_rusb2.c | 2 ++ src/portable/renesas/rusb2/hcd_rusb2.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 2653d0da6a..e9ac465173 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -67,6 +67,8 @@ /* LINK core registers */ #if defined(__CCRX__) #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) +#elif defined(__RX__) + #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE) #else diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 1e26c931d0..b97ffd7e90 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -54,6 +54,8 @@ /* LINK core registers */ #if defined(__CCRX__) #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) +#elif defined(__RX__) + #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE) #else From 2b735ee8f5476168d6b5ed1dc32edc52f4d3648a Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 5 Jun 2023 09:31:58 +0200 Subject: [PATCH 09/40] renesas_ra: fix wrong ifdef Since CFG_TUSB_RHPORT1_MODE is always defined now for backwards compatibility --- src/portable/renesas/rusb2/rusb2_ra.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c index 2b6ce7b2fc..ff2191b1f1 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.c +++ b/src/portable/renesas/rusb2/rusb2_ra.c @@ -1,16 +1,16 @@ #include "tusb_option.h" #include "rusb2_ra.h" -#ifdef CFG_TUSB_RHPORT0_MODE +#if (CFG_TUSB_RHPORT0_MODE != 0) IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn; void tud_set_irq_usbfs(IRQn_Type q) { _usb_fs_irqn = q; } #endif -#ifdef CFG_TUSB_RHPORT1_MODE +#if (CFG_TUSB_RHPORT1_MODE != 0) IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn; void tud_set_irq_usbhs(IRQn_Type q) { _usb_hs_irqn = q; } -#endif \ No newline at end of file +#endif From bb0e688b8e950652c70d82b46b7093e14b33c350 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 3 Jul 2023 16:35:22 +0700 Subject: [PATCH 10/40] add jlinkscript for detect rtt --- hw/bsp/ra/boards/ra4m1_ek/board.h | 2 +- hw/bsp/ra/boards/ra4m3_ek/board.h | 2 +- hw/bsp/ra/boards/ra6m1_ek/board.h | 2 +- hw/bsp/ra/boards/ra6m5_ek/board.h | 2 +- hw/bsp/ra/debug.jlinkscript | 4 ++++ hw/bsp/ra/family.c | 12 +++++++----- 6 files changed, 15 insertions(+), 9 deletions(-) create mode 100644 hw/bsp/ra/debug.jlinkscript diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h index ba3698f3dd..c132387bc3 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/board.h +++ b/hw/bsp/ra/boards/ra4m1_ek/board.h @@ -37,7 +37,7 @@ extern "C" { #define SW1 BSP_IO_PORT_01_PIN_05 #define BUTTON_STATE_ACTIVE 0 -const ioport_pin_cfg_t board_pin_cfg[] = { +static const ioport_pin_cfg_t board_pin_cfg[] = { {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, // USB FS D+, D-, VBus diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h index c2f150b33c..4b4735c4fa 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/board.h +++ b/hw/bsp/ra/boards/ra4m3_ek/board.h @@ -37,7 +37,7 @@ extern "C" { #define SW1 (BSP_IO_PORT_00_PIN_05) #define BUTTON_STATE_ACTIVE 0 -const ioport_pin_cfg_t board_pin_cfg[] = { +static const ioport_pin_cfg_t board_pin_cfg[] = { {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, // USB FS D+, D-, VBus diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h index 0b7297fd4d..2765a6a5ff 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/board.h +++ b/hw/bsp/ra/boards/ra6m1_ek/board.h @@ -37,7 +37,7 @@ extern "C" { #define SW1 BSP_IO_PORT_04_PIN_15 #define BUTTON_STATE_ACTIVE 0 -const ioport_pin_cfg_t board_pin_cfg[] = { +static const ioport_pin_cfg_t board_pin_cfg[] = { {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, // USB FS D+, D-, VBus diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h index 87434630f8..c88e9a0a28 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.h +++ b/hw/bsp/ra/boards/ra6m5_ek/board.h @@ -37,7 +37,7 @@ extern "C" { #define SW1 BSP_IO_PORT_00_PIN_05 #define BUTTON_STATE_ACTIVE 0 -const ioport_pin_cfg_t board_pin_cfg[] = { +static const ioport_pin_cfg_t board_pin_cfg[] = { { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, diff --git a/hw/bsp/ra/debug.jlinkscript b/hw/bsp/ra/debug.jlinkscript new file mode 100644 index 0000000000..b34cfaa7f1 --- /dev/null +++ b/hw/bsp/ra/debug.jlinkscript @@ -0,0 +1,4 @@ +int SetupTarget(void) { + JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x80000"); + return 0; +} diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 8b5e911a1b..08823dd521 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -90,12 +90,12 @@ void board_init(void) R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk; #endif - board_led_write(false); + // Enable USB module + R_MSTP->MSTPCRB &= ~(1U << 11U); // FS - /* Enable USB_BASE */ - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; - R_MSTP->MSTPCRB &= ~(1U << 11U); - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +#ifdef R_USB_HS0_BASE + R_MSTP->MSTPCRB &= ~(1U << 12U); // HS +#endif #if CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) @@ -108,6 +108,8 @@ void board_init(void) #if CFG_TUSB_OS == OPT_OS_NONE SysTick_Config(SystemCoreClock / 1000); #endif + + board_led_write(false); } void board_led_write(bool state) { From 071c30f381074c780bfb068cd31ed0801336bea6 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 4 Jul 2023 19:27:37 +0700 Subject: [PATCH 11/40] update fsp to version 4.5, correct RA BSP. Fix ETM Trace with 6m5 by lowering PLL to 128Mhz. --- hw/bsp/family_support.cmake | 4 ++ .../ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h | 6 -- .../boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h | 2 +- hw/bsp/ra/boards/ra6m1_ek/board.h | 10 ++- .../ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h | 7 -- .../boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h | 2 +- hw/bsp/ra/boards/ra6m5_ek/board.h | 16 +++-- .../boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h | 70 +++++++++++-------- hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug | 70 +++++++++++++++++++ hw/bsp/ra/family.c | 15 ++-- hw/bsp/ra/family.cmake | 8 +-- tools/get_deps.py | 2 +- 12 files changed, 142 insertions(+), 70 deletions(-) diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index b2e61a8241..5b97eb5e4b 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -227,6 +227,10 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) if (DEFINED LOG) target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG}) + if (LOG STREQUAL "3") + # no inline for debug level 3 + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=) + endif () endif() if (RTOS STREQUAL "freertos") diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h index 700d9b29f4..19bb473ebc 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -31,12 +31,6 @@ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0 - -#define BSP_FEATURE_TFU_SUPPORTED 0 -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) - // for SystemInit() void bsp_init(void * p_args); diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h index 930fa3547b..554126523e 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_8_0) /* PLL Mul x8 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h index 2765a6a5ff..f73a08fc0b 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/board.h +++ b/hw/bsp/ra/boards/ra6m1_ek/board.h @@ -38,12 +38,10 @@ extern "C" { #define BUTTON_STATE_ACTIVE 0 static const ioport_pin_cfg_t board_pin_cfg[] = { - {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, - {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus - {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, + { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT }, + { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, + // USB FS + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS }, }; #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h index c2b23b16ce..75a331fc2c 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -60,13 +60,6 @@ extern "C" { #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0 -#define BSP_FEATURE_TFU_SUPPORTED 0 -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) - -#define BSP_CFG_USE_LOW_VOLTAGE_MODE 0 - // for SystemInit() void bsp_init(void * p_args); diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h index 1cdfae949f..945a6010ba 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h index c88e9a0a28..779f718101 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.h +++ b/hw/bsp/ra/boards/ra6m5_ek/board.h @@ -41,22 +41,24 @@ static const ioport_pin_cfg_t board_pin_cfg[] = { { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - // USB FS D+, D-, VBus + // USB FS { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - // USB HS D+, D-, VBus + // USB HS { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, // ETM Trace - { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, - { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, - { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, - { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, - { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, + #ifdef TRACE_ETM + { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + #endif }; #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h index 77ac41d0ae..9bb496dd63 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h @@ -1,35 +1,45 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CLOCK_CFG_H_ #define BSP_CLOCK_CFG_H_ -#define BSP_CFG_CLOCKS_SECURE (0) + +#define BSP_CFG_CLOCKS_SECURE (0) #define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ -#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */ -#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ -#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ -#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ -#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */ -#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ -#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ -#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ + +#ifdef TRACE_ETM +// Due to ozone fixed trace clock div = 1, PLL is limited around 100Mhz. This use 128 Mhz +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(16U,0U)) /* PLL Mul x16.0 */ +#else +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ +#endif + +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ + + #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug index fa55d40b24..8a1262138d 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug +++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug @@ -33,3 +33,73 @@ void BeforeTargetConnect (void) { // Trace pin init is done by J-Link script file as J-Link script files are IDE independent // } + +/********************************************************************* +* +* AfterTargetReset +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetReset (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr != 0xFFFFFFFF) { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + } else { + Util.Log("Project file error: failed to get program base"); + } + + PC = Elf.GetEntryPointPC(); + + if (PC != 0xFFFFFFFF) { + Target.SetReg("PC", PC); + } else if (VectorTableAddr != 0xFFFFFFFF) { + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr != 0xFFFFFFFF) { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + } else { + Util.Log("Project file error: failed to get program base"); + } + + PC = Elf.GetEntryPointPC(); + + if (PC != 0xFFFFFFFF) { + Target.SetReg("PC", PC); + } else if (VectorTableAddr != 0xFFFFFFFF) { + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 08823dd521..769678954f 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -36,15 +36,14 @@ #endif #include "bsp_api.h" +#include "r_ioport.h" +#include "r_ioport_api.h" +#include "renesas.h" #ifdef __GNUC__ #pragma GCC diagnostic pop #endif -#include "r_ioport.h" -#include "r_ioport_api.h" -#include "renesas.h" - #include "bsp/board.h" #include "board.h" @@ -86,15 +85,17 @@ void board_init(void) R_IOPORT_Open(&port_ctrl, &family_pin_cfg); #ifdef TRACE_ETM - // Enable trace clock with div 1 (100 Mhz) - R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk; + // Enable trace clock (max 100Mhz) = PLL / div + // Somehow ozone/jtrace always fixed trace div to 1 therefore for ETM tracing working reliably + // PLL is limited around 100Mhz + R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01; #endif // Enable USB module R_MSTP->MSTPCRB &= ~(1U << 11U); // FS #ifdef R_USB_HS0_BASE - R_MSTP->MSTPCRB &= ~(1U << 12U); // HS +// R_MSTP->MSTPCRB &= ~(1U << 12U); // HS #endif #if CFG_TUSB_OS == OPT_OS_FREERTOS diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 828559e5e6..f4e978230b 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -37,14 +37,14 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all/bsp_security.c ${FSP_RA}/src/r_ioport/r_ioport.c ) - target_compile_definitions(${BOARD_TARGET} PUBLIC - _RA_TZ_NONSECURE - ) + # ETM Trace option + if (TRACE_ETM STREQUAL "1") + target_compile_definitions(${BOARD_TARGET} PUBLIC TRACE_ETM) + endif () target_compile_options(${BOARD_TARGET} PUBLIC -ffreestanding ) - target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} diff --git a/tools/get_deps.py b/tools/get_deps.py index fa47a80675..21ad539c4d 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -57,7 +57,7 @@ '58879cfa0eca5725d8db6443ec17f8896a321042', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', - '9860fae1f180340a0e3c097dc6e91323cf83b926', + 'd52e5a6a59b7c638da860c2bb309b6e78e752ff8', 'ra'], 'hw/mcu/renesas/rx': ['https://github.com/kkitayam/rx_device.git', '706b4e0cf485605c32351e2f90f5698267996023', From 1d6ca3bc9b68e0f17f2db61d2d8c2c951b8b32eb Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 4 Jul 2023 20:04:54 +0700 Subject: [PATCH 12/40] fix ra4m3 ek build --- hw/bsp/ra/boards/ra4m3_ek/board.h | 2 +- .../ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h | 46 +- .../ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 408 ++++++++++++------ .../boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h | 42 +- 6 files changed, 341 insertions(+), 173 deletions(-) create mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h index 4b4735c4fa..9dd2545a07 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/board.h +++ b/hw/bsp/ra/boards/ra4m3_ek/board.h @@ -40,7 +40,7 @@ extern "C" { static const ioport_pin_cfg_t board_pin_cfg[] = { {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus + // USB FS {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h index a9cb8210b0..6a47bccc68 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h @@ -1,21 +1,36 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" -#undef RA_NOT_DEFINED +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else #define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED #if defined(_RA_BOOT_IMAGE) #define BSP_CFG_BOOT_IMAGE (1) #endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -#define BSP_CFG_HEAP_BYTES (0x400) +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_HEAP_BYTES (0x400) #define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) #define BSP_CFG_PFS_PROTECT ((1)) @@ -24,14 +39,27 @@ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif // for SystemInit() void bsp_init(void * p_args); +#ifdef __cplusplus +} +#endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 0000000000..444d32e560 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000000..1a0bc02e26 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M3AF3CFB +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (1048576) +#define BSP_RAM_SIZE_BYTES (131072) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (144) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 4ecda1c66f..26e184a94a 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -1,129 +1,181 @@ -/* generated configuration header file through renesas e2 studio */ +/* generated configuration header file - do not edit */ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h" #include "bsp_clock_cfg.h" -#include "bsp_mcu_info.h" - -#define BSP_CFG_MCU_PART_SERIES (4) -#define BSP_MCU_R7FA4M3AF3CFB -#define BSP_ROM_SIZE_BYTES (1048576) -#define BSP_RAM_SIZE_BYTES (131072) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (144) - #define BSP_MCU_GROUP_RA4M3 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) #elif BSP_CFG_HOCO_FREQUENCY == 1 -#define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 -#define BSP_HOCO_HZ (20000000) -#else -#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif -#define BSP_CFG_FLL_ENABLE (0) +#define BSP_CFG_FLL_ENABLE (0) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) -#define BSP_MCU_VBATT_SUPPORT (1) +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) #if defined(_RA_TZ_SECURE) -#define BSP_TZ_SECURE_BUILD (1) -#define BSP_TZ_NONSECURE_BUILD (0) -#elif defined(_RA_TZ_NONSECURE) -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (1) -#else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) #endif /* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) /* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) -#define SCB_NSACR_CP10_11_VAL (3U) +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif -#define FPU_FPCCR_TS_VAL (1U) -#define FPU_FPCCR_CLRONRETS_VAL (1) +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) -#define FPU_FPCCR_CLRONRET_VAL (1) +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif /* The C-Cache line size that is configured during startup. */ -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#ifndef BSP_CFG_C_CACHE_LINE_SIZE +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif /* Type 1 Peripheral Security Attribution */ /* Peripheral Security Attribution Register (PSAR) Settings */ -#define BSP_TZ_CFG_PSARB \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */ -#define BSP_TZ_CFG_PSARC \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */ -#define BSP_TZ_CFG_PSARD \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#define BSP_TZ_CFG_PSARE \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */ -#define BSP_TZ_CFG_MSSAR \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif /* Type 2 Peripheral Security Attribution */ /* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif /* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif /* Security attribution for registers of LVD channels. */ -#define BSP_TZ_CFG_LVDSAR \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ - 0xFFFFFFFCU) +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif /* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif /* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) +#endif /* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR #if BSP_CFG_CLOCKS_SECURE /* Protect all CGC registers from Non-secure write access. */ #define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) @@ -131,58 +183,78 @@ /* Allow Secure and Non-secure write access. */ #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) #endif +#endif /* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif /* Security attribution for registers for IRQ channels. */ -#define BSP_TZ_CFG_ICUSARA \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U) +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif /* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif /* Security attribution for registers for DMAC channels */ -#define BSP_TZ_CFG_ICUSARC \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U) +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif /* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif /* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif /* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif /* Set DTCSTSAR if the Secure program uses the DTC. */ -// #if RA_NOT_DEFINED == RA_NOT_DEFINED +#if RA_NOT_DEFINED == RA_NOT_DEFINED #define BSP_TZ_CFG_DTC_USED (0U) -// #else -// #define BSP_TZ_CFG_DTC_USED (1U) -// #endif +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif /* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR /* If the CGC registers are only accessible in Secure mode, than there is no * reason for nonsecure applications to access FLWT and FCKMHZ. */ #if BSP_CFG_CLOCKS_SECURE @@ -192,69 +264,123 @@ /* Allow Secure and Non-secure write access. */ #define BSP_TZ_CFG_FSAR (0xFFFFU) #endif +#endif /* Security attribution for SRAM registers. */ -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for Non Secure applications to access +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U) +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif /* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif /* Security attribution for the DMAC Bus Master MPU settings. */ -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. - */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif /* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif /* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) /* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) -#define BSP_CFG_ROM_REG_OFS1_SEL \ - (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) #else #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif +#endif -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* Used to create IELS values for the interrupt initialization table - * g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) /* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) +#endif + /* Block Protection Register 0 */ -#define BSP_CFG_ROM_REG_BPS0 (~(0U)) +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif /* Block Protection Register 1 */ -#define BSP_CFG_ROM_REG_BPS1 (~(0U)) +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif /* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) +#endif +/* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 +#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) +#endif /* Permanent Block Protection Register 0 */ -#define BSP_CFG_ROM_REG_PBPS0 (~(0U)) +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif /* Permanent Block Protection Register 1 */ -#define BSP_CFG_ROM_REG_PBPS1 (~(0U)) +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif /* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) -/* Security Attribution for Block Protection Register 0 (If any blocks are - * marked as protected in the secure application, then mark them as secure) */ +#endif +/* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 +#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -/* Security Attribution for Block Protection Register 1 (If any blocks are - * marked as protected in the secure application, then mark them as secure) */ +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -/* Security Attribution for Block Protection Register 2 (If any blocks are - * marked as protected in the secure application, then mark them as secure) */ -#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 +#define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +#ifdef __cplusplus +} +#endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h index 4f490f3409..80641945d6 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h @@ -1,27 +1,25 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CLOCK_CFG_H_ #define BSP_CLOCK_CFG_H_ - -#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_SECURE (0) #define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL Mul x24.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ -#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL2 Mul x24.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */ - +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL Mul x24.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL2 Mul x24.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */ #endif /* BSP_CLOCK_CFG_H_ */ From f79529c09c6e7c0d6ee5586633ceb8c83e345406 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 5 Jul 2023 17:13:01 +0700 Subject: [PATCH 13/40] usb hs work with ra 6m5 ek --- .idea/runConfigurations/ra4m1.xml | 10 ++ .idea/runConfigurations/ra6m1.xml | 10 ++ .idea/runConfigurations/ra6m5.xml | 10 ++ hw/bsp/ra/board_cfg.h | 45 +++++++ .../ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h | 4 +- .../ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h | 4 +- .../ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h | 4 +- hw/bsp/ra/boards/ra6m5_ek/board.cmake | 20 ++- .../ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h | 4 +- hw/bsp/ra/family.c | 118 ++++++++++++------ hw/bsp/ra/vector_data.h | 15 ++- src/common/tusb_mcu.h | 1 + src/portable/renesas/rusb2/dcd_rusb2.c | 3 +- 13 files changed, 188 insertions(+), 60 deletions(-) create mode 100644 .idea/runConfigurations/ra4m1.xml create mode 100644 .idea/runConfigurations/ra6m1.xml create mode 100644 .idea/runConfigurations/ra6m5.xml create mode 100644 hw/bsp/ra/board_cfg.h diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml new file mode 100644 index 0000000000..22bb619491 --- /dev/null +++ b/.idea/runConfigurations/ra4m1.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml new file mode 100644 index 0000000000..438ac40633 --- /dev/null +++ b/.idea/runConfigurations/ra6m1.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml new file mode 100644 index 0000000000..02df116105 --- /dev/null +++ b/.idea/runConfigurations/ra6m5.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/hw/bsp/ra/board_cfg.h b/hw/bsp/ra/board_cfg.h new file mode 100644 index 0000000000..baed46b5fb --- /dev/null +++ b/hw/bsp/ra/board_cfg.h @@ -0,0 +1,45 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _BOARD_CFG_H +#define _BOARD_CFG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) + #define BOARD_HAS_USB_HIGHSPEED +#endif + +// for SystemInit() +void bsp_init(void * p_args); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h index 19bb473ebc..f0577b7027 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -4,6 +4,7 @@ #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" #undef RA_NOT_DEFINED #define BSP_CFG_RTOS (0) @@ -31,7 +32,4 @@ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -// for SystemInit() -void bsp_init(void * p_args); - #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h index 6a47bccc68..47de7747df 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h @@ -7,6 +7,7 @@ extern "C" { #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" #define RA_NOT_DEFINED 0 #ifndef BSP_CFG_RTOS @@ -56,9 +57,6 @@ extern "C" { #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif -// for SystemInit() -void bsp_init(void * p_args); - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h index 75a331fc2c..b5ed53a3b2 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -8,6 +8,7 @@ extern "C" { #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" #define RA_NOT_DEFINED 0 #ifndef BSP_CFG_RTOS @@ -60,9 +61,6 @@ extern "C" { #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif -// for SystemInit() -void bsp_init(void * p_args); - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index 42a4c74178..d934a0c0d8 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -3,8 +3,22 @@ set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) +# default to PORT1 Highspeed +if (NOT DEFINED PORT) +set(PORT 1) +endif() + function(update_board TARGET) -# target_compile_definitions(${TARGET} PUBLIC) -# target_sources(${TARGET} PRIVATE) -# target_include_directories(${BOARD_TARGET} PUBLIC) + target_compile_definitions(${TARGET} PUBLIC + BOARD_TUD_RHPORT=${PORT} + # port 0 is fullspeed, port 1 is highspeed + BOARD_TUD_MAX_SPEED=$ + ) + + if (PORT STREQUAL 1) + target_compile_definitions(${TARGET} PUBLIC + CFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED + CFG_TUSB_RHPORT0_MODE=0 + ) + endif () endfunction() diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h index e41f603ad1..a41536eda5 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h @@ -7,6 +7,7 @@ extern "C" { #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" #define RA_NOT_DEFINED 0 #ifndef BSP_CFG_RTOS @@ -56,9 +57,6 @@ extern "C" { #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif -// for SystemInit() -void bsp_init(void * p_args); - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 769678954f..36b46beabd 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -48,9 +48,9 @@ #include "board.h" /* Key code for writing PRCR register. */ -#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_KEY (0xA500U) #define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) -#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) static const ioport_cfg_t family_pin_cfg = { .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t), @@ -62,25 +62,38 @@ static ioport_instance_ctrl_t port_ctrl; // Vector Data //--------------------------------------------------------------------+ -BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { +BSP_DONT_REMOVE BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) +const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = { [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ [1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ [2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ [3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ + +#ifdef BOARD_HAS_USB_HIGHSPEED + [4] = usbhs_interrupt_handler, /* USBHS INT (USBHS interrupt) */ + [5] = usbhs_d0fifo_handler, /* USBHS FIFO 0 (DMA transfer request 0) */ + [6] = usbhs_d1fifo_handler, /* USBHS FIFO 1 (DMA transfer request 1) */ +#endif }; + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { - [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ - [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ - [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ - [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */ + [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1), /* USBFS FIFO 1 (DMA transfer request 1) */ + +#ifdef BOARD_HAS_USB_HIGHSPEED + [4] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME), /* USBHS USB INT RESUME (USBHS interrupt) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_0), /* USBHS FIFO 0 (DMA transfer request 0) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_1), /* USBHS FIFO 1 (DMA transfer request 1) */ +#endif }; //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ -void board_init(void) -{ +void board_init(void) { /* Configure pins. */ R_IOPORT_Open(&port_ctrl, &family_pin_cfg); @@ -94,8 +107,8 @@ void board_init(void) // Enable USB module R_MSTP->MSTPCRB &= ~(1U << 11U); // FS -#ifdef R_USB_HS0_BASE -// R_MSTP->MSTPCRB &= ~(1U << 12U); // HS +#ifdef BOARD_HAS_USB_HIGHSPEED + R_MSTP->MSTPCRB &= ~(1U << 12U); #endif #if CFG_TUSB_OS == OPT_OS_FREERTOS @@ -145,66 +158,93 @@ void SysTick_Handler(void) { uint32_t board_millis(void) { return system_ticks; } + #endif //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void usbfs_interrupt_handler(void) -{ + +#if CFG_TUD_ENABLED && defined(BOARD_TUD_RHPORT) + #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) +#else + #define PORT_SUPPORT_DEVICE(_n) 0 +#endif + +#if CFG_TUH_ENABLED && defined(BOARD_TUH_RHPORT) + #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) +#else + #define PORT_SUPPORT_HOST(_n) 0 +#endif + +//------------- USB0 FullSpeed -------------// +void usbfs_interrupt_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); -#if CFG_TUH_ENABLED + #if PORT_SUPPORT_HOST(0) tuh_int_handler(0); -#endif + #endif -#if CFG_TUD_ENABLED + #if PORT_SUPPORT_DEVICE(0) tud_int_handler(0); -#endif + #endif } -void usbfs_resume_handler(void) -{ +void usbfs_resume_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); -#if CFG_TUH_ENABLED + #if PORT_SUPPORT_HOST(0) tuh_int_handler(0); -#endif + #endif -#if CFG_TUD_ENABLED + #if PORT_SUPPORT_DEVICE(0) tud_int_handler(0); -#endif + #endif } -void usbfs_d0fifo_handler(void) -{ +void usbfs_d0fifo_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); + // TODO not used yet +} -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif +void usbfs_d1fifo_handler(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + // TODO not used yet +} -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif +//------------- USB1 HighSpeed -------------// +#ifdef BOARD_HAS_USB_HIGHSPEED + +void usbhs_interrupt_handler(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + #if PORT_SUPPORT_HOST(1) + tuh_int_handler(1); + #endif + + #if PORT_SUPPORT_DEVICE(1) + tud_int_handler(1); + #endif } -void usbfs_d1fifo_handler(void) -{ +void usbhs_d0fifo_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); + // TODO not used yet +} -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif +void usbhs_d1fifo_handler(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + // TODO not used yet +} -#if CFG_TUD_ENABLED - tud_int_handler(0); #endif -} //--------------------------------------------------------------------+ // stdlib diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h index 3d8a24634e..ca667faa3f 100644 --- a/hw/bsp/ra/vector_data.h +++ b/hw/bsp/ra/vector_data.h @@ -6,22 +6,29 @@ extern "C" { #endif -#ifndef VECTOR_DATA_IRQ_COUNT - #define VECTOR_DATA_IRQ_COUNT 4 -#endif - /* ISR prototypes */ void usbfs_interrupt_handler(void); void usbfs_resume_handler(void); void usbfs_d0fifo_handler(void); void usbfs_d1fifo_handler(void); +#ifdef BOARD_HAS_USB_HIGHSPEED +void usbhs_interrupt_handler(void); +void usbhs_d0fifo_handler(void); +void usbhs_d1fifo_handler(void); +#endif + /* Vector table allocations */ #define USBFS_INT_IRQn 0 #define USBFS_RESUME_IRQn 1 #define USBFS_FIFO_0_IRQn 2 #define USBFS_FIFO_1_IRQn 3 +#define USBHS_USB_INT_RESUME_IRQn 4 /* USBHS USB INT RESUME (USBHS interrupt) */ +#define USBHS_FIFO_0_IRQn 5 /* USBHS FIFO 0 (DMA transfer request 0) */ +#define USBHS_FIFO_1_IRQn 6 /* USBHS FIFO 1 (DMA transfer request 1) */ + + #ifdef __cplusplus } #endif diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 9f3be78fd4..496ebfc85e 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -327,6 +327,7 @@ // Renesas //--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX) + #define TUP_USBIP_RUSB2 #define TUP_DCD_ENDPOINT_MAX 10 //--------------------------------------------------------------------+ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index e9ac465173..83d2a34c6d 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -31,8 +31,7 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -#if CFG_TUD_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ - TU_CHECK_MCU(OPT_MCU_RAXXX)) +#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2) #include "device/dcd.h" #include "rusb2_type.h" From 4f4c93594d8f82c18f9a1052c4da2e7c31fc1b8c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 5 Jul 2023 17:51:36 +0700 Subject: [PATCH 14/40] minor pipe clean up --- src/portable/renesas/rusb2/dcd_rusb2.c | 74 +++++++++++++++----------- 1 file changed, 43 insertions(+), 31 deletions(-) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 83d2a34c6d..b58e0be015 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -93,20 +93,20 @@ typedef struct TU_ATTR_PACKED { typedef union TU_ATTR_PACKED { struct { - volatile uint16_t u8: 8; - volatile uint16_t : 0; + volatile uint8_t u8; + volatile uint8_t reserved8; }; volatile uint16_t u16; } hw_fifo_t; typedef union TU_ATTR_PACKED { struct { - volatile uint32_t : 24; - volatile uint32_t u8: 8; + volatile uint8_t reserved8[3]; + volatile uint8_t u8; }; struct { - volatile uint32_t : 16; - volatile uint32_t u16: 16; + volatile uint16_t reserved16; + volatile uint16_t u16; }; volatile uint32_t u32; } hw_fifo32_t; @@ -126,6 +126,19 @@ typedef struct TU_ATTR_PACKED TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) TU_ATTR_BIT_FIELD_ORDER_END +// Transfer conditions specifiable for each pipe: +// - Pipe 0: Control transfer with 64-byte single buffer +// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up +// to 2 KB and optional double buffer +// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and +// optional double buffer +// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer +enum { + PIPE_1ST_BULK = 3, + PIPE_1ST_INTERRUPT = 6, + PIPE_COUNT = 10, +}; + typedef struct { pipe_state_t pipe[10]; @@ -137,34 +150,33 @@ typedef struct //--------------------------------------------------------------------+ static dcd_data_t _dcd; -#ifndef FIRST_BULK_PIPE -#define FIRST_BULK_PIPE 3 -#endif - static unsigned find_pipe(unsigned xfer) { switch (xfer) { - case TUSB_XFER_ISOCHRONOUS: - for (int i = 1; i <= 2; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_BULK: - for (int i = FIRST_BULK_PIPE; i <= 5; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - for (int i = 1; i <= 1; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_INTERRUPT: - for (int i = 6; i <= 9; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - default: - /* No support for control transfer */ - break; + case TUSB_XFER_ISOCHRONOUS: + for (int i = 1; i < PIPE_1ST_BULK; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + + case TUSB_XFER_BULK: + for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + for (int i = 1; i < PIPE_1ST_BULK; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + + case TUSB_XFER_INTERRUPT: + for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + + default: + /* No support for control transfer */ + break; } return 0; } From f308435b649c37f0cffc1d5a566fb71c22b57aa1 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 5 Jul 2023 22:09:35 +0700 Subject: [PATCH 15/40] update ra type to include usbhs registers --- hw/bsp/ra/family.cmake | 1 - hw/bsp/ra/family.mk | 1 - src/portable/renesas/rusb2/rusb2_ra.c | 16 -- src/portable/renesas/rusb2/rusb2_ra.h | 83 ++++--- src/portable/renesas/rusb2/rusb2_type.h | 315 +++++++++++++++--------- 5 files changed, 245 insertions(+), 171 deletions(-) delete mode 100644 src/portable/renesas/rusb2/rusb2_ra.c diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index f4e978230b..74329165ff 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -120,7 +120,6 @@ function(family_configure_example TARGET RTOS) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c - ${TOP}/src/portable/renesas/rusb2/rusb2_ra.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 9b6b02c024..b6e1bb0ae1 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -18,7 +18,6 @@ CFLAGS += \ SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ - src/portable/renesas/rusb2/rusb2_ra.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \ diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c deleted file mode 100644 index ff2191b1f1..0000000000 --- a/src/portable/renesas/rusb2/rusb2_ra.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "tusb_option.h" -#include "rusb2_ra.h" - -#if (CFG_TUSB_RHPORT0_MODE != 0) -IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn; -void tud_set_irq_usbfs(IRQn_Type q) { - _usb_fs_irqn = q; -} -#endif - -#if (CFG_TUSB_RHPORT1_MODE != 0) -IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn; -void tud_set_irq_usbhs(IRQn_Type q) { - _usb_hs_irqn = q; -} -#endif diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 07fcafe6fc..ca7c38907f 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -47,55 +47,53 @@ extern "C" { #pragma GCC diagnostic pop #endif -extern IRQn_Type _usb_fs_irqn; -extern IRQn_Type _usb_hs_irqn; +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ -#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) -// fallback -#define CFG_TUSB_RHPORT0_MODE ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST ) -#define CFG_TUSB_RHPORT1_MODE 0 +// IAR does not have __builtin_ctz +#if defined(__ICCARM__) + #define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x)) #endif -#if defined(__ICCARM__) - #define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x)) +typedef struct { + uint32_t reg_base; + int32_t irqnum; +}rusb2_controller_t; + +#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) + #define RUSB2_HAS_HIGHSPEED + #define RUSB2_CONTROLLER_COUNT 2 +#else + #define RUSB2_CONTROLLER_COUNT 1 #endif +// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP +static rusb2_controller_t rusb2_controller[] = { + { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, + #ifdef RUSB2_HAS_HIGHSPEED + { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, + #endif +}; + TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { -#ifdef CFG_TUSB_RHPORT1_MODE -#if (CFG_TUSB_RHPORT1_MODE != 0) - if (rhport == 1) { - NVIC_EnableIRQ(_usb_hs_irqn); - } -#endif -#endif - -#ifdef CFG_TUSB_RHPORT0_MODE -#if (CFG_TUSB_RHPORT0_MODE != 0) - if (rhport == 0) { - NVIC_EnableIRQ(_usb_fs_irqn); - } -#endif -#endif + #if RUSB2_CONTROLLER_COUNT > 1 + NVIC_EnableIRQ(rusb2_controller[rhport].irqnum); + #else + (void) rhport; + NVIC_EnableIRQ(rusb2_controller[0].irqnum); + #endif } TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { -#ifdef CFG_TUSB_RHPORT1_MODE -#if (CFG_TUSB_RHPORT1_MODE != 0) - if (rhport == 1) { - NVIC_DisableIRQ(_usb_hs_irqn); - } -#endif -#endif - -#ifdef CFG_TUSB_RHPORT0_MODE -#if (CFG_TUSB_RHPORT0_MODE != 0) - if (rhport == 0) { - NVIC_DisableIRQ(_usb_fs_irqn); - } -#endif -#endif + #if RUSB2_CONTROLLER_COUNT > 1 + NVIC_DisableIRQ(rusb2_controller[rhport].irqnum); + #else + (void) rhport; + NVIC_DisableIRQ(rusb2_controller[0].irqnum); + #endif } // MCU specific PHY init @@ -103,6 +101,15 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) { } +void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { + #if RUSB2_CONTROLLER_COUNT > 1 + rusb2_controller[rhport].irqnum = irqnum; + #else + (void) rhport; + rusb2_controller[0].irqnum = irqnum; + #endif +} + #ifdef __cplusplus } #endif diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 90ba4f012d..0928f5aebb 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -46,10 +46,10 @@ typedef struct { volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ struct TU_ATTR_PACKED { - uint16_t : 8; + uint16_t : 8; volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ - uint16_t : 6; + uint16_t : 6; } E_b; }; @@ -62,7 +62,8 @@ typedef struct { }; } RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */ -/* LINK_REG Structure */ + +/* RUSB2 Registers Structure */ typedef struct { union { volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ @@ -74,7 +75,7 @@ typedef struct { volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */ volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ - uint16_t : 1; + volatile uint16_t HSE : 1; // [7..7] High-Speed Operation Enable volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ uint16_t : 1; volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ @@ -87,7 +88,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ - uint16_t : 12; + uint16_t : 12; } BUSWAIT_b; }; @@ -98,8 +99,7 @@ typedef struct { volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ uint16_t : 2; - volatile const uint16_t - SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ + volatile const uint16_t SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ uint16_t : 7; volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ @@ -111,7 +111,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */ - uint16_t : 15; + uint16_t : 15; } PLLSTA_b; }; @@ -139,7 +139,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t UTST : 4; /* [3..0] Test Mode */ - uint16_t : 12; + uint16_t : 12; } TESTMODE_b; }; volatile const uint16_t RESERVED1; @@ -295,7 +295,7 @@ typedef struct { volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */ struct TU_ATTR_PACKED { - uint16_t : 8; + uint16_t : 8; volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */ @@ -316,7 +316,10 @@ typedef struct { volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; + uint16_t : 1; + volatile uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + volatile uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ uint16_t : 1; @@ -340,7 +343,7 @@ typedef struct { volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; + uint16_t : 6; } BRDYENB_b; }; @@ -358,7 +361,7 @@ typedef struct { volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; + uint16_t : 6; } NRDYENB_b; }; @@ -376,7 +379,7 @@ typedef struct { volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */ volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */ volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; + uint16_t : 6; } BEMPENB_b; }; @@ -390,7 +393,7 @@ typedef struct { volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ uint16_t : 1; volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; + uint16_t : 7; } SOFCFG_b; }; @@ -467,7 +470,7 @@ typedef struct { volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */ volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */ volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; + uint16_t : 6; } BRDYSTS_b; }; @@ -485,7 +488,7 @@ typedef struct { volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */ volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */ volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; + uint16_t : 6; } NRDYSTS_b; }; @@ -503,7 +506,7 @@ typedef struct { volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */ volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */ volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; + uint16_t : 6; } BEMPSTS_b; }; @@ -609,7 +612,8 @@ typedef struct { volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ uint16_t : 2; volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ - uint16_t : 2; + volatile uint16_t CSSTS : 1; /* [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + volatile uint16_t CSCLR : 1; /* [13..13] Split Transaction CSPLIT Status Clear */ volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ } DCPCTR_b; @@ -621,7 +625,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */ - uint16_t : 12; + uint16_t : 12; } PIPESEL_b; }; volatile const uint16_t RESERVED11; @@ -634,21 +638,31 @@ typedef struct { volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ uint16_t : 2; volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; + volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ uint16_t : 3; volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ } PIPECFG_b; }; - volatile const uint16_t RESERVED12; + + union { + volatile uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct { + volatile uint16_t BUFNMB : 8; // [7..0] Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h) + uint16_t : 2; + volatile uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; union { volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ struct TU_ATTR_PACKED { - volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ - uint16_t : 3; + volatile uint16_t MXPS : 11; /* [10..0] Maximum Packet Size */ + uint16_t : 1; volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ } PIPEMAXP_b; }; @@ -694,11 +708,9 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ - volatile uint16_t - IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - volatile uint16_t - IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ uint16_t : 1; volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ @@ -715,7 +727,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */ - uint16_t : 15; + uint16_t : 15; } UCKSEL_b; }; volatile const uint16_t RESERVED18; @@ -737,11 +749,11 @@ typedef struct { volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */ struct TU_ATTR_PACKED { - uint16_t : 6; + uint16_t : 6; volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; + uint16_t : 1; } DEVADD_b[10]; }; volatile const uint32_t RESERVED21[3]; @@ -754,7 +766,7 @@ typedef struct { volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */ volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */ volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; + uint32_t : 28; } PHYSLEW_b; }; volatile const uint32_t RESERVED22[3]; @@ -763,9 +775,9 @@ typedef struct { volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */ struct TU_ATTR_PACKED { - uint16_t : 7; + uint16_t : 7; volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */ - uint16_t : 8; + uint16_t : 8; } LPCTRL_b; }; @@ -773,9 +785,9 @@ typedef struct { volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */ struct TU_ATTR_PACKED { - uint16_t : 14; + uint16_t : 14; volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */ - uint16_t : 1; + uint16_t : 1; } LPSTS_b; }; volatile const uint32_t RESERVED23[15]; @@ -793,7 +805,7 @@ typedef struct { uint16_t : 2; volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */ volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ - uint16_t : 6; + uint16_t : 6; } BCCTRL_b; }; volatile const uint16_t RESERVED24; @@ -809,7 +821,7 @@ typedef struct { volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ uint16_t : 2; volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; + uint16_t : 1; } PL1CTRL1_b; }; @@ -817,10 +829,10 @@ typedef struct { volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */ struct TU_ATTR_PACKED { - uint16_t : 8; + uint16_t : 8; volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ - uint16_t : 3; + uint16_t : 3; } PL1CTRL2_b; }; @@ -830,7 +842,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ - uint16_t : 13; + uint16_t : 13; } HL1CTRL1_b; }; @@ -846,18 +858,48 @@ typedef struct { volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ } HL1CTRL2_b; }; - volatile const uint32_t RESERVED25[5]; + + volatile uint32_t RESERVED25_1; + + union { + volatile uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct { + volatile uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + volatile uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + volatile uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + volatile uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + volatile uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union { + volatile uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct { + volatile uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + volatile uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + volatile uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + volatile uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + volatile uint32_t RESERVED25_2[3]; union { volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */ struct TU_ATTR_PACKED { - uint32_t : 20; + uint32_t : 20; volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ uint32_t : 1; volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ - uint32_t : 8; + uint32_t : 8; } DPUSR0R_b; }; @@ -865,7 +907,7 @@ typedef struct { volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ struct TU_ATTR_PACKED { - uint32_t : 4; + uint32_t : 4; volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ uint32_t : 1; @@ -875,7 +917,7 @@ typedef struct { volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ uint32_t : 1; volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; + uint32_t : 8; } DPUSR1R_b; }; @@ -891,7 +933,7 @@ typedef struct { uint16_t : 2; volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; + uint16_t : 6; } DPUSR2R_b; }; @@ -901,7 +943,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; + uint16_t : 14; } DPUSRCR_b; }; volatile const uint32_t RESERVED26[165]; @@ -924,7 +966,7 @@ typedef struct { volatile const uint32_t DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ uint32_t : 1; volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ - uint32_t : 8; + uint32_t : 8; } DPUSR0R_FS_b; }; @@ -947,10 +989,10 @@ typedef struct { volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */ uint32_t : 1; volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; + uint32_t : 8; } DPUSR1R_FS_b; }; -} RUSB2_REG_t; /* Size = 1032 (0x408) */ +} rusb2_reg_t; /* Size = 1032 (0x408) */ TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */ TU_ATTR_BIT_FIELD_ORDER_END @@ -970,13 +1012,15 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ #define RUSB2_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ -// LINK_REG +// Core Registers // SYSCFG #define RUSB2_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ #define RUSB2_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ #define RUSB2_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ #define RUSB2_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ +#define RUSB2_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ #define RUSB2_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ #define RUSB2_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ #define RUSB2_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ @@ -1135,6 +1179,10 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ #define RUSB2_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ #define RUSB2_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ +#define RUSB2_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ +#define RUSB2_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ #define RUSB2_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ #define RUSB2_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ #define RUSB2_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ @@ -1299,6 +1347,10 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ #define RUSB2_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ #define RUSB2_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ +#define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ +#define RUSB2_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ +#define RUSB2_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ #define RUSB2_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ #define RUSB2_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ #define RUSB2_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ @@ -1325,6 +1377,8 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ #define RUSB2_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ #define RUSB2_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ +#define RUSB2_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ #define RUSB2_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ #define RUSB2_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ #define RUSB2_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ @@ -1332,6 +1386,12 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ #define RUSB2_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ +// PIPEBUF +#define RUSB2_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ +#define RUSB2_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ +#define RUSB2_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ +#define RUSB2_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ + // PIPEMAXP #define RUSB2_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ #define RUSB2_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ @@ -1478,6 +1538,28 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ #define RUSB2_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ +// PHYTRIM1 +#define RUSB2_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ +#define RUSB2_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ +#define RUSB2_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ +#define RUSB2_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ +#define RUSB2_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ +#define RUSB2_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ +#define RUSB2_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ +#define RUSB2_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ +#define RUSB2_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ + +// PHYTRIM2 +#define RUSB2_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ +#define RUSB2_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ +#define RUSB2_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ +#define RUSB2_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ +#define RUSB2_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ +#define RUSB2_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ +#define RUSB2_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ + // DPUSR0R #define RUSB2_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ #define RUSB2_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ @@ -1599,69 +1681,72 @@ TU_ATTR_BIT_FIELD_ORDER_END //--------------------------------------------------------------------+ TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size"); -TU_VERIFY_STATIC(sizeof(RUSB2_REG_t) == 1032, "incorrect size"); - -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG ) == 0x00000000, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PLLSTA ) == 0x00000006, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFO ) == 0x00000014, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFO ) == 0x00000018, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB0 ) == 0x00000030, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB1 ) == 0x00000032, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYENB ) == 0x00000036, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYENB ) == 0x00000038, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSET ) == 0x0000003E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBADDR ) == 0x00000050, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBREQ ) == 0x00000054, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBVAL ) == 0x00000056, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBINDX ) == 0x00000058, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBLENG ) == 0x0000005A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCTR ) == 0x00000060, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPESEL ) == 0x00000064, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPECFG ) == 0x00000068, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBMC ) == 0x000000CC, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DEVADD ) == 0x000000D0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPCTRL ) == 0x00000100, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPSTS ) == 0x00000102, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BCCTRL ) == 0x00000140, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset"); +TU_VERIFY_STATIC(sizeof(rusb2_reg_t) == 1032, "incorrect size"); + +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSCFG ) == 0x0000, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BUSWAIT ) == 0x0002, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSSTS0 ) == 0x0004, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PLLSTA ) == 0x0006, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DVSTCTR0 ) == 0x0008, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, TESTMODE ) == 0x000C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFO ) == 0x0014, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFO ) == 0x0018, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFO ) == 0x001C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOSEL ) == 0x0020, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOCTR ) == 0x0022, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOSEL ) == 0x0028, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOCTR ) == 0x002A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOSEL ) == 0x002C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOCTR ) == 0x002E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB0 ) == 0x0030, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB1 ) == 0x0032, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYENB ) == 0x0036, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYENB ) == 0x0038, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPENB ) == 0x003A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SOFCFG ) == 0x003C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSET ) == 0x003E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS0 ) == 0x0040, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS1 ) == 0x0042, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYSTS ) == 0x0046, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYSTS ) == 0x0048, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPSTS ) == 0x004A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, FRMNUM ) == 0x004C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UFRMNUM ) == 0x004E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBADDR ) == 0x0050, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBREQ ) == 0x0054, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBVAL ) == 0x0056, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBINDX ) == 0x0058, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBLENG ) == 0x005A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCFG ) == 0x005C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPMAXP ) == 0x005E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCTR ) == 0x0060, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPESEL ) == 0x0064, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPECFG ) == 0x0068, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEBUF ) == 0x006A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEMAXP ) == 0x006C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEPERI ) == 0x006E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_CTR ) == 0x0070, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_TR ) == 0x0090, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBBCCTRL0 ) == 0x00B0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UCKSEL ) == 0x00C4, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBMC ) == 0x00CC, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DEVADD ) == 0x00D0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSLEW ) == 0x00F0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPCTRL ) == 0x0100, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPSTS ) == 0x0102, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BCCTRL ) == 0x0140, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL1 ) == 0x0144, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL2 ) == 0x0146, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL1 ) == 0x0148, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL2 ) == 0x014A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM1 ) == 0x0150, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM2 ) == 0x0152, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R ) == 0x0160, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R ) == 0x0164, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR2R ) == 0x0168, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSRCR ) == 0x016A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R_FS ) == 0x0400, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R_FS ) == 0x0404, "incorrect offset"); #ifdef __cplusplus } From 95b77a0e7356b5f6625fbdb66f35415db3aac7a9 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Jul 2023 15:54:07 +0700 Subject: [PATCH 16/40] add rusb2_module_start(), more update for multiple ports for dcd rusb2 --- hw/bsp/ra/family.c | 7 - src/portable/renesas/rusb2/dcd_rusb2.c | 280 ++++++++++++++---------- src/portable/renesas/rusb2/rusb2_ra.h | 38 ++-- src/portable/renesas/rusb2/rusb2_rx.h | 6 + src/portable/renesas/rusb2/rusb2_type.h | 1 + 5 files changed, 190 insertions(+), 142 deletions(-) diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 36b46beabd..2c21a9967d 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -104,13 +104,6 @@ void board_init(void) { R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01; #endif - // Enable USB module - R_MSTP->MSTPCRB &= ~(1U << 11U); // FS - -#ifdef BOARD_HAS_USB_HIGHSPEED - R_MSTP->MSTPCRB &= ~(1U << 12U); -#endif - #if CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index b58e0be015..27d525b68f 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -65,9 +65,9 @@ /* LINK core registers */ #if defined(__CCRX__) - #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) + #define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE) #elif defined(__RX__) - #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) + #define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE) #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE) #else @@ -145,10 +145,15 @@ typedef struct uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ } dcd_data_t; +static dcd_data_t _dcd; + //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -static dcd_data_t _dcd; + +TU_ATTR_ALWAYS_INLINE static inline bool is_highspeed(uint8_t rhport) { + return rhport == 1; +} static unsigned find_pipe(unsigned xfer) { @@ -543,38 +548,60 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) static void process_bus_reset(uint8_t rhport) { - RUSB2->BEMPENB = 1; - RUSB2->BRDYENB = 1; - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - RUSB2->D1FIFOSEL = 0; - while (RUSB2->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_CTR[0])); - volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_TR[0].E)); + rusb2_reg_t* rusb = RUSB2_REG(rhport); + + rusb->BEMPENB = 1; + rusb->BRDYENB = 1; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + + rusb->D1FIFOSEL = 0; + while (rusb->D1FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + + volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_CTR[0])); + volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_TR[0].E)); + for (int i = 1; i <= 5; ++i) { - RUSB2->PIPESEL = i; - RUSB2->PIPECFG = 0; + rusb->PIPESEL = i; + rusb->PIPECFG = 0; *ctr = RUSB2_PIPE_CTR_ACLRM_Msk; *ctr = 0; ++ctr; *tre = TU_BIT(8); tre += 2; } + for (int i = 6; i <= 9; ++i) { - RUSB2->PIPESEL = i; - RUSB2->PIPECFG = 0; + rusb->PIPESEL = i; + rusb->PIPECFG = 0; *ctr = RUSB2_PIPE_CTR_ACLRM_Msk; *ctr = 0; ++ctr; } tu_varclr(&_dcd); -#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, true); -#else - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); -#endif + TU_LOG3("Bus reset, RHST = %u\r\n", rusb->DVSTCTR0_b.RHST); + tusb_speed_t speed; + switch(rusb->DVSTCTR0 & RUSB2_DVSTCTR0_RHST_Msk) { + case RUSB2_DVSTCTR0_RHST_LS: + speed = TUSB_SPEED_LOW; + break; + + case RUSB2_DVSTCTR0_RHST_FS: + speed = TUSB_SPEED_FULL; + break; + + case RUSB2_DVSTCTR0_RHST_HS: + speed = TUSB_SPEED_HIGH; + break; + + default: + TU_ASSERT(false, ); + } + + dcd_event_bus_reset(rhport, speed, true); } static void process_set_address(uint8_t rhport) @@ -625,56 +652,63 @@ static void enable_interrupt(uint32_t pswi) void dcd_init(uint8_t rhport) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); -#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - RUSB2->SYSCFG_b.HSE = 1; - RUSB2->PHYSET_b.DIRPD = 0; - R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); - RUSB2->PHYSET_b.PLLRESET = 0; - //RUSB2->PHYSET_b.REPSTART = 1; - RUSB2->SYSCFG_b.DRPD = 0; - RUSB2->SYSCFG_b.USBE = 1; - RUSB2->LPSTS_b.SUSPENDM = 1; - while (!RUSB2->PLLSTA_b.PLLLOCK); - //RUSB2->BUSWAIT |= 0x0F00U; - //RUSB2->PHYSET_b.REPSEL = 1; - RUSB2->CFIFOSEL_b.MBW = 1; - RUSB2->D0FIFOSEL_b.MBW = 1; - RUSB2->D1FIFOSEL_b.MBW = 1; - RUSB2->INTSTS0 = 0; -#else - RUSB2->SYSCFG_b.SCKE = 1; - while (!RUSB2->SYSCFG_b.SCKE) ; - RUSB2->SYSCFG_b.DRPD = 0; - RUSB2->SYSCFG_b.DCFM = 0; - RUSB2->SYSCFG_b.USBE = 1; -#endif + rusb2_module_start(rhport, true); - // MCU specific PHY init - rusb2_phy_init(); + if ( is_highspeed(rhport) ) { + rusb->SYSCFG_b.HSE = 1; -#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) - RUSB2->PHYSLEW = 0x5; - RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ + // leave CLKSEL as default (0x11) 24Mhz - #define USB_VDCEN (0x0080U) /* b7: Regulator ON/OFF control */ - RUSB2->USBMC = (uint16_t) (RUSB2->USBMC | (USB_VDCEN)); -#endif + // Power and reset UTMI Phy + uint16_t physet = (rusb->PHYSET | RUSB2_PHYSET_PLLRESET_Msk) & ~RUSB2_PHYSET_DIRPD_Msk; + rusb->PHYSET = physet; + R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); + rusb->PHYSET_b.PLLRESET = 0; + + // set UTMI to operating mode and wait for PLL lock confirmation + rusb->LPSTS_b.SUSPENDM = 1; + while (!rusb->PLLSTA_b.PLLLOCK) {} + + rusb->SYSCFG_b.DRPD = 0; + rusb->SYSCFG_b.USBE = 1; + + // Set CPU bus wait time (fine tunne later) + // rusb2->BUSWAIT |= 0x0F00U; + + rusb->PHYSET_b.REPSEL = 1; + + rusb->CFIFOSEL_b.MBW = 1; + rusb->D0FIFOSEL_b.MBW = 1; + rusb->D1FIFOSEL_b.MBW = 1; + } else { + rusb->SYSCFG_b.SCKE = 1; + while (!rusb->SYSCFG_b.SCKE) {} + rusb->SYSCFG_b.DRPD = 0; + rusb->SYSCFG_b.DCFM = 0; + rusb->SYSCFG_b.USBE = 1; + + // MCU specific PHY init + rusb2_phy_init(); + + rusb->PHYSLEW = 0x5; + rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ + + // rusb2->USBMC = (uint16_t) (rusb2->USBMC | RUSB2_USBMC_VDCEN_Msk); + } /* Setup default control pipe */ - RUSB2->DCPMAXP_b.MXPS = 64; - RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | - RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | - RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk; - RUSB2->BEMPENB = 1; - RUSB2->BRDYENB = 1; - -#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) - RUSB2->SYSCFG_b.DPRPU = 1; /* necessary in this position */ -#endif + rusb->DCPMAXP_b.MXPS = 64; + + rusb->INTSTS0 = 0; + rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | + RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | + RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk; + rusb->BEMPENB = 1; + rusb->BRDYENB = 1; - if (RUSB2->INTSTS0_b.VBSTS) { + if (rusb->INTSTS0_b.VBSTS) { dcd_connect(rhport); } } @@ -697,24 +731,24 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; - RUSB2->DVSTCTR0_b.WKUP = 1; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + rusb->DVSTCTR0_b.WKUP = 1; } void dcd_connect(uint8_t rhport) { - (void)rhport; - #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - RUSB2->SYSCFG_b.CNEN = 1; - R_BSP_SoftwareDelay((uint32_t) 10, BSP_DELAY_UNITS_MILLISECONDS); - #endif - RUSB2->SYSCFG_b.DPRPU = 1; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + + if ( is_highspeed(rhport)) { + rusb->SYSCFG_b.CNEN = 1; + } + rusb->SYSCFG_b.DPRPU = 1; } void dcd_disconnect(uint8_t rhport) { - (void)rhport; - RUSB2->SYSCFG_b.DPRPU = 0; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + rusb->SYSCFG_b.DPRPU = 0; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -861,76 +895,94 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) //--------------------------------------------------------------------+ void dcd_int_handler(uint8_t rhport) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + + uint16_t is0 = rusb->INTSTS0; - unsigned is0 = RUSB2->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk | - RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk; - if (is0 & RUSB2_INTSTS0_VBINT_Msk) { - if (RUSB2->INTSTS0_b.VBSTS) { + rusb->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk | + RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk; + + // VBUS changes + if ( is0 & RUSB2_INTSTS0_VBINT_Msk ) { + if ( rusb->INTSTS0_b.VBSTS ) { dcd_connect(rhport); } else { dcd_disconnect(rhport); } } - if (is0 & RUSB2_INTSTS0_RESM_Msk) { + + // Resumed + if ( is0 & RUSB2_INTSTS0_RESM_Msk ) { dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); -#if (0==USE_SOF) - RUSB2->INTENB0_b.SOFE = 0; +#if (0 == USE_SOF) + rusb->INTENB0_b.SOFE = 0; #endif } - if ((is0 & RUSB2_INTSTS0_SOFR_Msk) && RUSB2->INTENB0_b.SOFE) { + + // SOF received + if ( (is0 & RUSB2_INTSTS0_SOFR_Msk) && rusb->INTENB0_b.SOFE ) { // USBD will exit suspended mode when SOF event is received dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); #if (0 == USE_SOF) - RUSB2->INTENB0_b.SOFE = 0; + rusb->INTENB0_b.SOFE = 0; #endif } - if (is0 & RUSB2_INTSTS0_DVST_Msk) { + + // Device state changes + if ( is0 & RUSB2_INTSTS0_DVST_Msk ) { switch (is0 & RUSB2_INTSTS0_DVSQ_Msk) { - case RUSB2_INTSTS0_DVSQ_STATE_DEF: - process_bus_reset(rhport); - break; - case RUSB2_INTSTS0_DVSQ_STATE_ADDR: - process_set_address(rhport); - break; - case RUSB2_INTSTS0_DVSQ_STATE_SUSP0: - case RUSB2_INTSTS0_DVSQ_STATE_SUSP1: - case RUSB2_INTSTS0_DVSQ_STATE_SUSP2: - case RUSB2_INTSTS0_DVSQ_STATE_SUSP3: - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); -#if (0==USE_SOF) - RUSB2->INTENB0_b.SOFE = 1; + case RUSB2_INTSTS0_DVSQ_STATE_DEF: + process_bus_reset(rhport); + break; + + case RUSB2_INTSTS0_DVSQ_STATE_ADDR: + process_set_address(rhport); + break; + + case RUSB2_INTSTS0_DVSQ_STATE_SUSP0: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP1: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP2: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP3: + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); +#if (0 == USE_SOF) + rusb->INTENB0_b.SOFE = 1; #endif - default: - break; + + default: break; } } - if (is0 & RUSB2_INTSTS0_NRDY_Msk) { - RUSB2->NRDYSTS = 0; + + if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) { + rusb->NRDYSTS = 0; } - if (is0 & RUSB2_INTSTS0_CTRT_Msk) { - if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) { + + // Control transfer stage changes + if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) { + if ( is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA ) { /* A setup packet has been received. */ process_setup_packet(rhport); - } else if (0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk)) { + } else if ( 0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk) ) { /* A ZLP has been sent/received. */ process_status_completion(rhport); } } - if (is0 & RUSB2_INTSTS0_BEMP_Msk) { - const unsigned s = RUSB2->BEMPSTS; - RUSB2->BEMPSTS = 0; - if (s & 1) { + + // Buffer empty + if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) { + const unsigned s = rusb->BEMPSTS; + rusb->BEMPSTS = 0; + if ( s & 1 ) { process_pipe0_bemp(rhport); } } - if (is0 & RUSB2_INTSTS0_BRDY_Msk) { - const unsigned m = RUSB2->BRDYENB; - unsigned s = RUSB2->BRDYSTS & m; + + // Buffer ready + if ( is0 & RUSB2_INTSTS0_BRDY_Msk ) { + const unsigned m = rusb->BRDYENB; + unsigned s = rusb->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - RUSB2->BRDYSTS = ~s; + rusb->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) static const int Mod37BitPosition[] = { diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index ca7c38907f..0dc59331a1 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -76,38 +76,34 @@ static rusb2_controller_t rusb2_controller[] = { #endif }; -TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) -{ - #if RUSB2_CONTROLLER_COUNT > 1 +#define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) + +TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { + uint32_t const mask = 1U << (11+rhport); + if (start) { + R_MSTP->MSTPCRB &= ~mask; + }else { + R_MSTP->MSTPCRB |= mask; + } +} + +TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { NVIC_EnableIRQ(rusb2_controller[rhport].irqnum); - #else - (void) rhport; - NVIC_EnableIRQ(rusb2_controller[0].irqnum); - #endif } -TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) -{ - #if RUSB2_CONTROLLER_COUNT > 1 +TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { NVIC_DisableIRQ(rusb2_controller[rhport].irqnum); - #else - (void) rhport; - NVIC_DisableIRQ(rusb2_controller[0].irqnum); - #endif } // MCU specific PHY init -TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) -{ +TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) { } +//--------------------------------------------------------------------+ +// Application API for setting IRQ number +//--------------------------------------------------------------------+ void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { - #if RUSB2_CONTROLLER_COUNT > 1 rusb2_controller[rhport].irqnum = irqnum; - #else - (void) rhport; - rusb2_controller[0].irqnum = irqnum; - #endif } #ifdef __cplusplus diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index 397c0d56cd..d7f4e0b429 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -37,6 +37,12 @@ extern "C" { #define RUSB2_REG_BASE (0x000A0000) +// Start/Stop MSTP TODO implement later +TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { + (void) rhport; + (void) start; +} + TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { (void) rhport; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 0928f5aebb..b704626f6b 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -1653,6 +1653,7 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_DVSTCTR0_RHST_LS (1U << RUSB2_DVSTCTR0_RHST_Pos) /* Low-speed connection */ #define RUSB2_DVSTCTR0_RHST_FS (2U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */ +#define RUSB2_DVSTCTR0_RHST_HS (3U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */ #define RUSB2_DEVADD_USBSPD_LS (1U << RUSB2_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ #define RUSB2_DEVADD_USBSPD_FS (2U << RUSB2_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ From 1eefc2b3ef2e268e839002a8b5221eebe26f6cd3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Jul 2023 19:35:42 +0700 Subject: [PATCH 17/40] more multiple ports update --- src/portable/renesas/rusb2/dcd_rusb2.c | 344 ++++++++++++++---------- src/portable/renesas/rusb2/rusb2_rx.h | 2 + src/portable/renesas/rusb2/rusb2_type.h | 9 +- 3 files changed, 208 insertions(+), 147 deletions(-) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 27d525b68f..833737181a 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -63,22 +63,11 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -/* LINK core registers */ -#if defined(__CCRX__) - #define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE) -#elif defined(__RX__) - #define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE) -#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE) -#else - #define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE) -#endif - /* Start of definition of packed structs (used by the CCRX toolchain) */ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct TU_ATTR_PACKED { +typedef struct TU_ATTR_PACKED _ccrx_evenaccess { union { struct { uint16_t : 8; @@ -186,52 +175,53 @@ static unsigned find_pipe(unsigned xfer) return 0; } -static volatile uint16_t* get_pipectr(unsigned num) +static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num) { if (num) { - return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]); + return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]); } else { - return (volatile uint16_t*)&(RUSB2->DCPCTR); + return (volatile uint16_t*)&(rusb->DCPCTR); } } -static volatile reg_pipetre_t* get_pipetre(unsigned num) +static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E); + tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E); } return tre; } static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) { - (void)rhport; + rusb2_reg_t *rusb = RUSB2_REG(rhport); const unsigned epn = tu_edpt_number(ep_addr); + if (epn) { const unsigned dir = tu_edpt_dir(ep_addr); const unsigned num = _dcd.ep[dir][epn]; - return get_pipectr(num); + return get_pipectr(rusb, num); } else { - return get_pipectr(0); + return get_pipectr(rusb, 0); } } -static unsigned edpt0_max_packet_size(void) +static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb) { - return RUSB2->DCPMAXP_b.MXPS; + return rusb->DCPMAXP_b.MXPS; } -static unsigned edpt_max_packet_size(unsigned num) +static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num) { - RUSB2->PIPESEL = num; - return RUSB2->PIPEMAXP; + rusb->PIPESEL = num; + return rusb->PIPEMAXP; } -static inline void pipe_wait_for_ready(unsigned num) +static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) { - while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ; - while (!RUSB2->D0FIFOCTR_b.FRDY) ; + while ( rusb->D0FIFOSEL_b.CURPIPE != num ) {} + while ( !rusb->D0FIFOCTR_b.FRDY ) {} } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -284,61 +274,70 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne ops[dir].tu_fifo_advance(f, total_len - rem); } -static bool pipe0_xfer_in(void) +static bool pipe0_xfer_in(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_dcd.pipe[0]; const unsigned rem = pipe->remaining; + if (!rem) { pipe->buf = NULL; return true; } - const unsigned mps = edpt0_max_packet_size(); - const unsigned len = TU_MIN(mps, rem); + + const uint16_t mps = edpt0_max_packet_size(rusb); + const uint16_t len = tu_min16(mps, rem); void *buf = pipe->buf; + if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_IN); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len); + pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } + if (len < mps) { - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } + pipe->remaining = rem - len; return false; } -static bool pipe0_xfer_out(void) +static bool pipe0_xfer_out(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_dcd.pipe[0]; const unsigned rem = pipe->remaining; - const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = RUSB2->CFIFOCTR_b.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + const uint16_t mps = edpt0_max_packet_size(rusb); + const uint16_t vld = rusb->CFIFOCTR_b.DTLN; + const uint16_t len = tu_min16(tu_min16(rem, mps), vld); void *buf = pipe->buf; + if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len); + pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } + if (len < mps) { - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } + pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return true; } + return false; } -static bool pipe_xfer_in(unsigned num) +static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) { pipe_state_t *pipe = &_dcd.pipe[num]; const unsigned rem = pipe->remaining; @@ -348,119 +347,141 @@ static bool pipe_xfer_in(unsigned num) return true; } - RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned len = TU_MIN(rem, mps); + rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); + const uint16_t mps = edpt_max_packet_size(rusb, num); + pipe_wait_for_ready(rusb, num); + const uint16_t len = tu_min16(rem, mps); void *buf = pipe->buf; + if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_IN); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); + pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } + if (len < mps) { - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + return false; } -static bool pipe_xfer_out(unsigned num) +static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) { pipe_state_t *pipe = &_dcd.pipe[num]; - const unsigned rem = pipe->remaining; + const uint16_t rem = pipe->remaining; - RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned vld = RUSB2->D0FIFOCTR_b.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; + const uint16_t mps = edpt_max_packet_size(rusb, num); + pipe_wait_for_ready(rusb, num); + + const uint16_t vld = rusb->D0FIFOCTR_b.DTLN; + const uint16_t len = tu_min16(tu_min16(rem, mps), vld); void *buf = pipe->buf; + if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); + pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } + if (len < mps) { - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return NULL != buf; } + return false; } static void process_setup_packet(uint8_t rhport) { - uint16_t setup_packet[4]; - if (0 == (RUSB2->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return; - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; - setup_packet[0] = tu_le16toh(RUSB2->USBREQ); - setup_packet[1] = RUSB2->USBVAL; - setup_packet[2] = RUSB2->USBINDX; - setup_packet[3] = RUSB2->USBLENG; - RUSB2->INTSTS0 = ~((uint16_t)RUSB2_INTSTS0_VALID_Msk); + rusb2_reg_t* rusb = RUSB2_REG(rhport); + if (0 == (rusb->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return; + + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + uint16_t setup_packet[4] = { + tu_htole16(rusb->USBREQ), + tu_htole16(rusb->USBVAL), + tu_htole16(rusb->USBINDX), + tu_htole16(rusb->USBLENG) + }; + + rusb->INTSTS0 = ~((uint16_t) RUSB2_INTSTS0_VALID_Msk); dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); } static void process_status_completion(uint8_t rhport) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); uint8_t ep_addr; /* Check the data stage direction */ - if (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) { + if (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) { /* IN transfer. */ ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); } else { /* OUT transfer. */ ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT); } + dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true); } -static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +static bool process_pipe0_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) { /* configure fifo direction and access unit settings */ - if (ep_addr) { /* IN, 2 bytes */ - RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | - (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); - while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ; - } else { /* OUT, a byte */ - RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; - while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ; + if ( ep_addr ) { + /* IN, 2 bytes */ + rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); + while ( !(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ) {} + } else { + /* OUT, a byte */ + rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; + while ( rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE ) {} } pipe_state_t *pipe = &_dcd.pipe[0]; pipe->ff = buffer_type; pipe->length = total_bytes; pipe->remaining = total_bytes; - if (total_bytes) { - pipe->buf = buffer; - if (ep_addr) { /* IN */ - TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80)); - pipe0_xfer_in(); + + if ( total_bytes ) { + pipe->buf = buffer; + if ( ep_addr ) { + /* IN */ + TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80)); + pipe0_xfer_in(rusb); } - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; } else { /* ZLP */ - pipe->buf = NULL; - RUSB2->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF; + pipe->buf = NULL; + rusb->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF; } + return true; } -static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +static bool process_pipe_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) { const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir = tu_edpt_dir(ep_addr); @@ -473,49 +494,55 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui pipe->buf = buffer; pipe->length = total_bytes; pipe->remaining = total_bytes; - if (dir) { /* IN */ + + if (dir) { + /* IN */ if (total_bytes) { - pipe_xfer_in(num); - } else { /* ZLP */ - RUSB2->D0FIFOSEL = num; - pipe_wait_for_ready(num); - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe_xfer_in(rusb, num); + } else { + /* ZLP */ + rusb->D0FIFOSEL = num; + pipe_wait_for_ready(rusb, num); + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOSEL = 0; + /* if CURPIPE bits changes, check written value */ + while (rusb->D0FIFOSEL_b.CURPIPE) {} } } else { -#if defined(__CCRX__) - __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num); -#else - volatile reg_pipetre_t *pt = get_pipetre(num); -#endif + // OUT + volatile reg_pipetre_t *pt = get_pipetre(rusb, num); + if (pt) { - const unsigned mps = edpt_max_packet_size(num); - volatile uint16_t *ctr = get_pipectr(num); + const uint16_t mps = edpt_max_packet_size(rusb, num); + volatile uint16_t *ctr = get_pipectr(rusb, num); + if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK; + pt->TRE = TU_BIT(8); pt->TRN = (total_bytes + mps - 1) / mps; pt->TRENB = 1; *ctr = RUSB2_PIPE_CTR_PID_BUF; } } - // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); + + // TU_LOG2("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); return true; } -static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +static bool process_edpt_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) { const unsigned epn = tu_edpt_number(ep_addr); if (0 == epn) { - return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes); + return process_pipe0_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes); } else { - return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes); + return process_pipe_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes); } } static void process_pipe0_bemp(uint8_t rhport) { - bool completed = pipe0_xfer_in(); + rusb2_reg_t* rusb = RUSB2_REG(rhport); + bool completed = pipe0_xfer_in(rusb); if (completed) { pipe_state_t *pipe = &_dcd.pipe[0]; dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN), @@ -525,17 +552,20 @@ static void process_pipe0_bemp(uint8_t rhport) static void process_pipe_brdy(uint8_t rhport, unsigned num) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); pipe_state_t *pipe = &_dcd.pipe[num]; const unsigned dir = tu_edpt_dir(pipe->ep); bool completed; - if (dir) { /* IN */ - completed = pipe_xfer_in(num); + if (dir) { + /* IN */ + completed = pipe_xfer_in(rusb, num); } else { + // OUT if (num) { - completed = pipe_xfer_out(num); + completed = pipe_xfer_out(rusb, num); } else { - completed = pipe0_xfer_out(); + completed = pipe0_xfer_out(rusb); } } if (completed) { @@ -606,8 +636,10 @@ static void process_bus_reset(uint8_t rhport) static void process_set_address(uint8_t rhport) { - const uint32_t addr = RUSB2->USBADDR & 0xFF; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + const uint32_t addr = rusb->USBADDR & 0xFF; if (!addr) return; + const tusb_control_request_t setup_packet = { #if defined(__CCRX__) .bmRequestType = { 0 }, /* Note: CCRX needs the braces over this struct member */ @@ -618,8 +650,9 @@ static void process_set_address(uint8_t rhport) .wValue = addr, .wIndex = 0, .wLength = 0, - }; - dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true); + }; + + dcd_event_setup_received(rhport, (const uint8_t *) &setup_packet, true); } /*------------------------------------------------------------------*/ @@ -704,7 +737,7 @@ void dcd_init(uint8_t rhport) rusb->INTSTS0 = 0; rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | - RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk; + RUSB2_INTSTS0_RESM_Msk; rusb->BEMPENB = 1; rusb->BRDYENB = 1; @@ -766,33 +799,43 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { (void)rhport; + rusb2_reg_t * rusb = RUSB2_REG(rhport); const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir = tu_edpt_dir(ep_addr); const unsigned xfer = ep_desc->bmAttributes.xfer; const unsigned mps = tu_edpt_packet_size(ep_desc); - if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { - /* USBa supports up to 256 bytes */ - return false; + + if (xfer == TUSB_XFER_ISOCHRONOUS) { + // Fullspeed ISO is limit to 256 bytes + if ( !is_highspeed(rhport) && mps > 256) { + return false; + } } const unsigned num = find_pipe(xfer); - if (!num) return false; + TU_ASSERT(num); + _dcd.pipe[num].ep = ep_addr; _dcd.ep[dir][epn] = num; /* setup pipe */ dcd_int_disable(rhport); - #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - RUSB2->PIPEBUF = 0x7C08; - #endif - RUSB2->PIPESEL = num; - RUSB2->PIPEMAXP = mps; - volatile uint16_t *ctr = get_pipectr(num); + + if ( is_highspeed(rhport) ) { + // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed + // depending on the allocation scheme + rusb->PIPEBUF = 0x7C08; + } + + rusb->PIPESEL = num; + rusb->PIPEMAXP = mps; + volatile uint16_t *ctr = get_pipectr(rusb, num); *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk; *ctr = 0; unsigned cfg = (dir << 4) | epn; + if (xfer == TUSB_XFER_BULK) { cfg |= (RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk); } else if (xfer == TUSB_XFER_INTERRUPT) { @@ -800,13 +843,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) } else { cfg |= (RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk); } - RUSB2->PIPECFG = cfg; - RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num); - RUSB2->BRDYENB |= TU_BIT(num); + + rusb->PIPECFG = cfg; + rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num); + rusb->BRDYENB |= TU_BIT(num); + if (dir || (xfer != TUSB_XFER_BULK)) { *ctr = RUSB2_PIPE_CTR_PID_BUF; } - // TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP); + + // TU_LOG1("O %d %x %x\r\n", rusb->PIPESEL, rusb->PIPECFG, rusb->PIPEMAXP); dcd_int_enable(rhport); return true; @@ -826,26 +872,28 @@ void dcd_edpt_close_all(uint8_t rhport) void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + rusb2_reg_t * rusb = RUSB2_REG(rhport); const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir = tu_edpt_dir(ep_addr); const unsigned num = _dcd.ep[dir][epn]; - RUSB2->BRDYENB &= ~TU_BIT(num); - volatile uint16_t *ctr = get_pipectr(num); + rusb->BRDYENB &= ~TU_BIT(num); + volatile uint16_t *ctr = get_pipectr(rusb, num); *ctr = 0; - RUSB2->PIPESEL = num; - RUSB2->PIPECFG = 0; + rusb->PIPESEL = num; + rusb->PIPECFG = 0; _dcd.pipe[num].ep = 0; _dcd.ep[dir][epn] = 0; } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { - bool r; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + dcd_int_disable(rhport); - r = process_edpt_xfer(0, ep_addr, buffer, total_bytes); + bool r = process_edpt_xfer(rusb, 0, ep_addr, buffer, total_bytes); dcd_int_enable(rhport); + return r; } @@ -853,10 +901,12 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_ { // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 TU_ASSERT(ff->item_size == 1); - bool r; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + dcd_int_disable(rhport); - r = process_edpt_xfer(1, ep_addr, ff, total_bytes); + bool r = process_edpt_xfer(rusb, 1, ep_addr, ff, total_bytes); dcd_int_enable(rhport); + return r; } @@ -873,8 +923,10 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + rusb2_reg_t * rusb = RUSB2_REG(rhport); volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); if (!ctr) return; + dcd_int_disable(rhport); *ctr = RUSB2_PIPE_CTR_SQCLR_Msk; @@ -882,8 +934,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) *ctr = RUSB2_PIPE_CTR_PID_BUF; } else { const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; - RUSB2->PIPESEL = num; - if (RUSB2->PIPECFG_b.TYPE != 1) { + rusb->PIPESEL = num; + if (rusb->PIPECFG_b.TYPE != 1) { *ctr = RUSB2_PIPE_CTR_PID_BUF; } } @@ -953,9 +1005,9 @@ void dcd_int_handler(uint8_t rhport) } } - if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) { - rusb->NRDYSTS = 0; - } +// if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) { +// rusb->NRDYSTS = 0; +// } // Control transfer stage changes if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) { @@ -970,7 +1022,7 @@ void dcd_int_handler(uint8_t rhport) // Buffer empty if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) { - const unsigned s = rusb->BEMPSTS; + const uint16_t s = rusb->BEMPSTS; rusb->BEMPSTS = 0; if ( s & 1 ) { process_pipe0_bemp(rhport); diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index d7f4e0b429..21b2527c3d 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -37,6 +37,8 @@ extern "C" { #define RUSB2_REG_BASE (0x000A0000) +#define RUSB2_REG(_p) ((rusb2_reg_t *) RUSB2_REG_BASE) + // Start/Stop MSTP TODO implement later TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { (void) rhport; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index b704626f6b..7a5e370892 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -33,6 +33,13 @@ extern "C" { #endif +// CCRX specific attribute to generate a Code that Accesses Variables in the Declared Size +#ifdef __CCRX__ + #define _ccrx_evenaccess __evenaccess +#else + #define _ccrx_evenaccess +#endif + /*--------------------------------------------------------------------*/ /* Register Definitions */ /*--------------------------------------------------------------------*/ @@ -64,7 +71,7 @@ typedef struct { /* RUSB2 Registers Structure */ -typedef struct { +typedef struct _ccrx_evenaccess { union { volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ From c53acb145589e2733b7d1abe012e85ae590bffb7 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Jul 2023 20:10:58 +0700 Subject: [PATCH 18/40] fix build with rx --- src/portable/renesas/rusb2/dcd_rusb2.c | 37 +++++++++++++++----------- src/portable/renesas/rusb2/rusb2_ra.h | 4 +-- src/portable/renesas/rusb2/rusb2_rx.h | 5 +++- 3 files changed, 27 insertions(+), 19 deletions(-) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 833737181a..81b60b3bc9 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -36,12 +36,6 @@ #include "device/dcd.h" #include "rusb2_type.h" -#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) -// fallback -#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE -#define CFG_TUSB_RHPORT1_MODE 0 -#endif - #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) @@ -86,7 +80,7 @@ typedef union TU_ATTR_PACKED { volatile uint8_t reserved8; }; volatile uint16_t u16; -} hw_fifo_t; +} hw_fifo16_t; typedef union TU_ATTR_PACKED { struct { @@ -140,9 +134,11 @@ static dcd_data_t _dcd; // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline bool is_highspeed(uint8_t rhport) { - return rhport == 1; -} +#ifdef RUSB2_SUPPORT_HIGHSPEED + #define is_highspeed_usbip(_p) (_p == 1) +#else + #define is_highspeed_usbip(_p) (false) +#endif static unsigned find_pipe(unsigned xfer) { @@ -229,14 +225,17 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo; #else - volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; + volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo; #endif + uintptr_t addr = (uintptr_t)buf; + while (len >= 2) { reg->u16 = *(const uint16_t *)addr; addr += 2; len -= 2; } + if (len > 0) { reg->u8 = *(const uint8_t *)addr; ++addr; @@ -260,11 +259,14 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, }; + tu_fifo_buffer_info_t info; ops[dir].tu_fifo_get_info(f, &info); + unsigned total_len = len; len = TU_MIN(total_len, info.len_lin); ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + unsigned rem = total_len - len; if (rem) { len = TU_MIN(rem, info.len_wrap); @@ -689,7 +691,8 @@ void dcd_init(uint8_t rhport) rusb2_module_start(rhport, true); - if ( is_highspeed(rhport) ) { +#ifdef RUSB2_SUPPORT_HIGHSPEED + if ( is_highspeed_usbip(rhport) ) { rusb->SYSCFG_b.HSE = 1; // leave CLKSEL as default (0x11) 24Mhz @@ -715,7 +718,9 @@ void dcd_init(uint8_t rhport) rusb->CFIFOSEL_b.MBW = 1; rusb->D0FIFOSEL_b.MBW = 1; rusb->D1FIFOSEL_b.MBW = 1; - } else { + } else +#endif + { rusb->SYSCFG_b.SCKE = 1; while (!rusb->SYSCFG_b.SCKE) {} rusb->SYSCFG_b.DRPD = 0; @@ -772,7 +777,7 @@ void dcd_connect(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - if ( is_highspeed(rhport)) { + if ( is_highspeed_usbip(rhport)) { rusb->SYSCFG_b.CNEN = 1; } rusb->SYSCFG_b.DPRPU = 1; @@ -809,7 +814,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) if (xfer == TUSB_XFER_ISOCHRONOUS) { // Fullspeed ISO is limit to 256 bytes - if ( !is_highspeed(rhport) && mps > 256) { + if ( !is_highspeed_usbip(rhport) && mps > 256) { return false; } } @@ -823,7 +828,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* setup pipe */ dcd_int_disable(rhport); - if ( is_highspeed(rhport) ) { + if ( is_highspeed_usbip(rhport) ) { // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed // depending on the allocation scheme rusb->PIPEBUF = 0x7C08; diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 0dc59331a1..e04a996856 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -62,7 +62,7 @@ typedef struct { }rusb2_controller_t; #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) - #define RUSB2_HAS_HIGHSPEED + #define RUSB2_SUPPORT_HIGHSPEED #define RUSB2_CONTROLLER_COUNT 2 #else #define RUSB2_CONTROLLER_COUNT 1 @@ -71,7 +71,7 @@ typedef struct { // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP static rusb2_controller_t rusb2_controller[] = { { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, - #ifdef RUSB2_HAS_HIGHSPEED + #ifdef RUSB2_SUPPORT_HIGHSPEED { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, #endif }; diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index 21b2527c3d..17b9a918cd 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -37,7 +37,10 @@ extern "C" { #define RUSB2_REG_BASE (0x000A0000) -#define RUSB2_REG(_p) ((rusb2_reg_t *) RUSB2_REG_BASE) +TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) { + (void) rhport; + return (rusb2_reg_t *) RUSB2_REG_BASE; +} // Start/Stop MSTP TODO implement later TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { From 4bbacb10089856fd6cd6e4c54da8ab2dc8575c60 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 11:07:57 +0700 Subject: [PATCH 19/40] correct setting trace clock --- hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h | 8 -------- hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug | 3 +-- hw/bsp/ra/family.c | 11 ++++++----- hw/bsp/ra/family.cmake | 4 ---- 4 files changed, 7 insertions(+), 19 deletions(-) diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h index 9bb496dd63..0eb5e05167 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h @@ -8,14 +8,7 @@ #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ - -#ifdef TRACE_ETM -// Due to ozone fixed trace clock div = 1, PLL is limited around 100Mhz. This use 128 Mhz -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(16U,0U)) /* PLL Mul x16.0 */ -#else #define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ -#endif - #define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ #define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ @@ -41,5 +34,4 @@ #define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ #define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ - #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug index 8a1262138d..aebb291628 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug +++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug @@ -29,9 +29,8 @@ void OnProjectLoad (void) { ********************************************************************** */ void BeforeTargetConnect (void) { - // // Trace pin init is done by J-Link script file as J-Link script files are IDE independent - // + Project.SetJLinkScript("../../../debug.jlinkscript"); } /********************************************************************* diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 2c21a9967d..b78fdedc7b 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -49,8 +49,6 @@ /* Key code for writing PRCR register. */ #define BSP_PRV_PRCR_KEY (0xA500U) -#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) -#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) static const ioport_cfg_t family_pin_cfg = { .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t), @@ -98,10 +96,13 @@ void board_init(void) { R_IOPORT_Open(&port_ctrl, &family_pin_cfg); #ifdef TRACE_ETM - // Enable trace clock (max 100Mhz) = PLL / div - // Somehow ozone/jtrace always fixed trace div to 1 therefore for ETM tracing working reliably - // PLL is limited around 100Mhz + // TRCKCR is protected by PRCR bit0 register + R_SYSTEM->PRCR = (uint16_t) (BSP_PRV_PRCR_KEY | 0x01); + + // Enable trace clock (max 100Mhz). Since PLL/CPU is 200Mhz, clock div = 2 R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01; + + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_KEY; #endif #if CFG_TUSB_OS == OPT_OS_FREERTOS diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 74329165ff..eb2d4958fa 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -37,10 +37,6 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all/bsp_security.c ${FSP_RA}/src/r_ioport/r_ioport.c ) - # ETM Trace option - if (TRACE_ETM STREQUAL "1") - target_compile_definitions(${BOARD_TARGET} PUBLIC TRACE_ETM) - endif () target_compile_options(${BOARD_TARGET} PUBLIC -ffreestanding From 4c156100fafa682407f1a9a459d8b8800a029446 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 12:27:18 +0700 Subject: [PATCH 20/40] use unaligned access read for hw fifo --- src/common/tusb_common.h | 18 ++++-- src/common/tusb_mcu.h | 12 +++- src/portable/renesas/rusb2/dcd_rusb2.c | 77 ++++++++++++++++---------- 3 files changed, 71 insertions(+), 36 deletions(-) diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 957491aa9d..576cb123ff 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -260,11 +260,21 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_ #else // MCU that could access unaligned memory natively -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32 (const void* mem) { return *((uint32_t const *) mem); } -TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16 (const void* mem) { return *((uint16_t const *) mem); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) { + return *((uint32_t const *) mem); +} + +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) { + return *((uint16_t const *) mem); +} -TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; } -TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; } +TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) { + *((uint32_t *) mem) = value; +} + +TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) { + *((uint16_t *) mem) = value; +} #endif diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 496ebfc85e..89f89182e2 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -34,10 +34,16 @@ //------------- Unaligned Memory Access -------------// -// ARMv7+ (M3-M7, M23-M33) can access unaligned memory -#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7)) - #define TUP_ARCH_STRICT_ALIGN 0 +#ifdef __ARM_ARCH + // ARM Architecture set __ARM_FEATURE_UNALIGNED to 1 for mcu supports unaligned access + #if defined(__ARM_FEATURE_UNALIGNED) && __ARM_FEATURE_UNALIGNED == 1 + #define TUP_ARCH_STRICT_ALIGN 0 + #else + #define TUP_ARCH_STRICT_ALIGN 1 + #endif #else + // TODO default to strict align for others + // Should investigate other architecture such as risv, xtensa, mips for optimal setting #define TUP_ARCH_STRICT_ALIGN 1 #endif diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 81b60b3bc9..4649292243 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -220,6 +220,11 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) while ( !rusb->D0FIFOCTR_b.FRDY ) {} } +//--------------------------------------------------------------------+ +// Pipe FIFO +//--------------------------------------------------------------------+ + +// Write data buffer --> hw fifo static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) @@ -228,54 +233,68 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo; #endif - uintptr_t addr = (uintptr_t)buf; + uint8_t const* buf8 = (uint8_t const*) buf; while (len >= 2) { - reg->u16 = *(const uint16_t *)addr; - addr += 2; + reg->u16 = tu_unaligned_read16(buf8); + buf8 += 2; len -= 2; } if (len > 0) { - reg->u8 = *(const uint8_t *)addr; - ++addr; + reg->u8 = *buf8; + ++buf8; } } +// Read data buffer <-- hw fifo static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) { - uint8_t *p = (uint8_t*)buf; + uint8_t *p = (uint8_t*)buf; volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ while (len--) *p++ = *reg; } -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) -{ - static const struct { - void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); - void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); - void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); - } ops[] = { - /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, - }; +// Write data sw fifo --> hw fifo +static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { + tu_fifo_buffer_info_t info; + tu_fifo_get_read_info(f, &info); + + uint16_t count = tu_min16(total_len, info.len_lin); + pipe_write_packet(info.ptr_lin, fifo, count); + + uint16_t rem = total_len - count; + if (rem) { + rem = tu_min16(rem, info.len_wrap); + pipe_write_packet(info.ptr_wrap, fifo, rem); + count += rem; + } + + tu_fifo_advance_read_pointer(f, count); +} +// Read data sw fifo <-- hw fifo +static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { tu_fifo_buffer_info_t info; - ops[dir].tu_fifo_get_info(f, &info); + tu_fifo_get_write_info(f, &info); - unsigned total_len = len; - len = TU_MIN(total_len, info.len_lin); - ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + uint16_t count = tu_min16(total_len, info.len_lin); + pipe_read_packet(info.ptr_lin, fifo, count); - unsigned rem = total_len - len; + uint16_t rem = total_len - count; if (rem) { - len = TU_MIN(rem, info.len_wrap); - ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); - rem -= len; + rem = tu_min16(rem, info.len_wrap); + pipe_read_packet(info.ptr_wrap, fifo, rem); + count += rem; } - ops[dir].tu_fifo_advance(f, total_len - rem); + + tu_fifo_advance_write_pointer(f, count); } +//--------------------------------------------------------------------+ +// Pipe Transfer +//--------------------------------------------------------------------+ + static bool pipe0_xfer_in(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_dcd.pipe[0]; @@ -292,7 +311,7 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb) if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN); + pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); } else { pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; @@ -319,7 +338,7 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb) if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT); + pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); } else { pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; @@ -357,7 +376,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN); + pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); } else { pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; @@ -391,7 +410,7 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT); + pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); } else { pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; From e0f1ba8b0e9cf46fabcddc72a61d5515df424edf Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 16:07:11 +0700 Subject: [PATCH 21/40] fully work with multiple ports without CFG_TUSB_RHPORT0/1 --- hw/bsp/family_support.cmake | 4 +- hw/bsp/ra/boards/ra6m5_ek/board.cmake | 7 -- src/portable/renesas/rusb2/dcd_rusb2.c | 85 +++++++++++-------------- src/portable/renesas/rusb2/rusb2_type.h | 1 + 4 files changed, 39 insertions(+), 58 deletions(-) diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 5b97eb5e4b..d8298c8ad4 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -227,8 +227,8 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) if (DEFINED LOG) target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG}) - if (LOG STREQUAL "3") - # no inline for debug level 3 + if (LOG STREQUAL "4") + # no inline for debug level 4 target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=) endif () endif() diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index d934a0c0d8..5a615f9b03 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -14,11 +14,4 @@ function(update_board TARGET) # port 0 is fullspeed, port 1 is highspeed BOARD_TUD_MAX_SPEED=$ ) - - if (PORT STREQUAL 1) - target_compile_definitions(${TARGET} PUBLIC - CFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED - CFG_TUSB_RHPORT0_MODE=0 - ) - endif () endfunction() diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 4649292243..3d3e52bfa1 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -74,26 +74,6 @@ typedef struct TU_ATTR_PACKED _ccrx_evenaccess { uint16_t TRN; } reg_pipetre_t; -typedef union TU_ATTR_PACKED { - struct { - volatile uint8_t u8; - volatile uint8_t reserved8; - }; - volatile uint16_t u16; -} hw_fifo16_t; - -typedef union TU_ATTR_PACKED { - struct { - volatile uint8_t reserved8[3]; - volatile uint8_t u8; - }; - struct { - volatile uint16_t reserved16; - volatile uint16_t u16; - }; - volatile uint32_t u32; -} hw_fifo32_t; - typedef struct TU_ATTR_PACKED { void *buf; /* the start address of a transfer data buffer */ @@ -135,9 +115,11 @@ static dcd_data_t _dcd; //--------------------------------------------------------------------+ #ifdef RUSB2_SUPPORT_HIGHSPEED - #define is_highspeed_usbip(_p) (_p == 1) + #define is_highspeed_usbip(_p) (_p == 1) + #define is_highspeed_regbase(_reg) (_reg == RUSB2_REG(1)) #else - #define is_highspeed_usbip(_p) (false) + #define is_highspeed_usbip(_p) (false) + #define is_highspeed_regbase(_reg) (false) #endif static unsigned find_pipe(unsigned xfer) @@ -225,48 +207,57 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) //--------------------------------------------------------------------+ // Write data buffer --> hw fifo -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len) { -#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo; -#else - volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo; -#endif + (void) rusb; + + volatile uint16_t *ff16; + volatile uint8_t *ff8; + + // Highspeed FIFO is 32-bit + if ( is_highspeed_regbase(rusb) ) { + ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2); + ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3); + }else { + ff16 = (volatile uint16_t*) fifo; + ff8 = ((volatile uint8_t*) fifo); + } uint8_t const* buf8 = (uint8_t const*) buf; while (len >= 2) { - reg->u16 = tu_unaligned_read16(buf8); + *ff16 = tu_unaligned_read16(buf8); buf8 += 2; len -= 2; } if (len > 0) { - reg->u8 = *buf8; + *ff8 = *buf8; ++buf8; } } // Read data buffer <-- hw fifo -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len) { + (void) rusb; uint8_t *p = (uint8_t*)buf; volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ while (len--) *p++ = *reg; } // Write data sw fifo --> hw fifo -static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { +static void pipe_write_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { tu_fifo_buffer_info_t info; tu_fifo_get_read_info(f, &info); uint16_t count = tu_min16(total_len, info.len_lin); - pipe_write_packet(info.ptr_lin, fifo, count); + pipe_write_packet(rusb, info.ptr_lin, fifo, count); uint16_t rem = total_len - count; if (rem) { rem = tu_min16(rem, info.len_wrap); - pipe_write_packet(info.ptr_wrap, fifo, rem); + pipe_write_packet(rusb, info.ptr_wrap, fifo, rem); count += rem; } @@ -274,17 +265,17 @@ static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t tot } // Read data sw fifo <-- hw fifo -static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { +static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { tu_fifo_buffer_info_t info; tu_fifo_get_write_info(f, &info); uint16_t count = tu_min16(total_len, info.len_lin); - pipe_read_packet(info.ptr_lin, fifo, count); + pipe_read_packet(rusb, info.ptr_lin, fifo, count); uint16_t rem = total_len - count; if (rem) { rem = tu_min16(rem, info.len_wrap); - pipe_read_packet(info.ptr_wrap, fifo, rem); + pipe_read_packet(rusb, info.ptr_wrap, fifo, rem); count += rem; } @@ -311,9 +302,9 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb) if (len) { if (pipe->ff) { - pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); + pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); } else { - pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len); + pipe_write_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } @@ -338,9 +329,9 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb) if (len) { if (pipe->ff) { - pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); + pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); } else { - pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len); + pipe_read_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } @@ -376,9 +367,9 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) if (len) { if (pipe->ff) { - pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); + pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); } else { - pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len); + pipe_write_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } @@ -410,9 +401,9 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) if (len) { if (pipe->ff) { - pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); + pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); } else { - pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len); + pipe_read_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } @@ -733,10 +724,6 @@ void dcd_init(uint8_t rhport) // rusb2->BUSWAIT |= 0x0F00U; rusb->PHYSET_b.REPSEL = 1; - - rusb->CFIFOSEL_b.MBW = 1; - rusb->D0FIFOSEL_b.MBW = 1; - rusb->D1FIFOSEL_b.MBW = 1; } else #endif { diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 7a5e370892..28cec99998 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -1670,6 +1670,7 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_FIFOSEL_BIGEND (1U << RUSB2_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ #define RUSB2_FIFOSEL_MBW_8BIT (0U << RUSB2_CFIFOSEL_MBW_Pos) /* 8-bit width */ #define RUSB2_FIFOSEL_MBW_16BIT (1U << RUSB2_CFIFOSEL_MBW_Pos) /* 16-bit width */ +#define RUSB2_FIFOSEL_MBW_32BIT (2U << RUSB2_CFIFOSEL_MBW_Pos) /* 32-bit width */ #define RUSB2_INTSTS0_CTSQ_CTRL_RDATA (1U << RUSB2_INTSTS0_CTSQ_Pos) From 88478a9d052edc364561da39382faef72f937ecb Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 16:24:22 +0700 Subject: [PATCH 22/40] add PORT selection for makefile --- hw/bsp/ra/boards/ra6m5_ek/board.mk | 3 +++ hw/bsp/ra/family.cmake | 2 +- hw/bsp/ra/family.mk | 12 ++++++++++++ src/portable/renesas/rusb2/dcd_rusb2.c | 4 ++++ 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk index 567908b633..a5c9337645 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.mk +++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk @@ -4,4 +4,7 @@ MCU_VARIANT = ra6m5 # For flash-jlink target JLINK_DEVICE = R7FA6M5BH +# Port 1 is highspeed +PORT ?= 1 + flash: flash-jlink diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index eb2d4958fa..f09e86a729 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS RA CACHE INTERNAL "") +set(FAMILY_MCUS RAXXX CACHE INTERNAL "") #------------------------------------ # BOARD_TARGET diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index b6e1bb0ae1..f5097460aa 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -3,8 +3,12 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5 FSP_RA = hw/mcu/renesas/fsp/ra/fsp include $(TOP)/$(BOARD_PATH)/board.mk +# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk +PORT ?= 0 + CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_RAXXX \ + -DBOARD_TUD_RHPORT=$(PORT) \ -Wno-error=undef \ -Wno-error=strict-prototypes \ -Wno-error=cast-align \ @@ -15,6 +19,14 @@ CFLAGS += \ -nostartfiles \ -ffreestanding +ifeq ($(PORT), 1) + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + $(info "Using PORT 1 HighSpeed") +else + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + $(info "Using PORT 0 FullSpeed") +endif + SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 3d3e52bfa1..17d22f6969 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -216,6 +216,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo // Highspeed FIFO is 32-bit if ( is_highspeed_regbase(rusb) ) { + // TODO 32-bit access for better performance ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2); ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3); }else { @@ -241,6 +242,9 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len) { (void) rusb; + + // TODO 16/32-bit access for better performance + uint8_t *p = (uint8_t*)buf; volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ while (len--) *p++ = *reg; From f7e7ba92ca7850c3c098fc988bf187a8b12a322a Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 16:27:12 +0700 Subject: [PATCH 23/40] enable host example for ra --- .idea/cmake.xml | 1 + examples/host/bare_api/only.txt | 1 + examples/host/cdc_msc_hid/only.txt | 1 + examples/host/hid_controller/only.txt | 1 + examples/host/msc_file_explorer/only.txt | 1 + 5 files changed, 5 insertions(+) diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 47ca8253e3..864ff615ba 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -46,6 +46,7 @@ + \ No newline at end of file diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index 45da6c3f27..f8aa2186f0 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -9,3 +9,4 @@ mcu:MIMXRT11XX mcu:RP2040 mcu:MSP432E4 mcu:RX65X +mcu:RAXXX diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index 45da6c3f27..f8aa2186f0 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -9,3 +9,4 @@ mcu:MIMXRT11XX mcu:RP2040 mcu:MSP432E4 mcu:RX65X +mcu:RAXXX diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index 45da6c3f27..f8aa2186f0 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -9,3 +9,4 @@ mcu:MIMXRT11XX mcu:RP2040 mcu:MSP432E4 mcu:RX65X +mcu:RAXXX diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index 45da6c3f27..f8aa2186f0 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -9,3 +9,4 @@ mcu:MIMXRT11XX mcu:RP2040 mcu:MSP432E4 mcu:RX65X +mcu:RAXXX From 0f53e746ffa21b6186809b2b896ddc74d38e9058 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 18:41:16 +0700 Subject: [PATCH 24/40] move check highspeed to rusb_ra --- src/portable/renesas/rusb2/dcd_rusb2.c | 31 ++++--------------------- src/portable/renesas/rusb2/rusb2_ra.h | 15 ++++++++---- src/portable/renesas/rusb2/rusb2_rx.h | 9 +++++++ src/portable/renesas/rusb2/rusb2_type.h | 14 +++++++++++ 4 files changed, 39 insertions(+), 30 deletions(-) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 17d22f6969..358e5644b3 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -61,19 +61,6 @@ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct TU_ATTR_PACKED _ccrx_evenaccess { - union { - struct { - uint16_t : 8; - uint16_t TRCLR: 1; - uint16_t TRENB: 1; - uint16_t : 0; - }; - uint16_t TRE; - }; - uint16_t TRN; -} reg_pipetre_t; - typedef struct TU_ATTR_PACKED { void *buf; /* the start address of a transfer data buffer */ @@ -114,14 +101,6 @@ static dcd_data_t _dcd; // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -#ifdef RUSB2_SUPPORT_HIGHSPEED - #define is_highspeed_usbip(_p) (_p == 1) - #define is_highspeed_regbase(_reg) (_reg == RUSB2_REG(1)) -#else - #define is_highspeed_usbip(_p) (false) - #define is_highspeed_regbase(_reg) (false) -#endif - static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -215,7 +194,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo volatile uint8_t *ff8; // Highspeed FIFO is 32-bit - if ( is_highspeed_regbase(rusb) ) { + if ( rusb2_is_highspeed_reg(rusb) ) { // TODO 32-bit access for better performance ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2); ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3); @@ -706,7 +685,7 @@ void dcd_init(uint8_t rhport) rusb2_module_start(rhport, true); #ifdef RUSB2_SUPPORT_HIGHSPEED - if ( is_highspeed_usbip(rhport) ) { + if ( rusb2_is_highspeed_rhport(rhport) ) { rusb->SYSCFG_b.HSE = 1; // leave CLKSEL as default (0x11) 24Mhz @@ -787,7 +766,7 @@ void dcd_connect(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - if ( is_highspeed_usbip(rhport)) { + if ( rusb2_is_highspeed_rhport(rhport)) { rusb->SYSCFG_b.CNEN = 1; } rusb->SYSCFG_b.DPRPU = 1; @@ -824,7 +803,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) if (xfer == TUSB_XFER_ISOCHRONOUS) { // Fullspeed ISO is limit to 256 bytes - if ( !is_highspeed_usbip(rhport) && mps > 256) { + if ( !rusb2_is_highspeed_rhport(rhport) && mps > 256) { return false; } } @@ -838,7 +817,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* setup pipe */ dcd_int_disable(rhport); - if ( is_highspeed_usbip(rhport) ) { + if ( rusb2_is_highspeed_rhport(rhport) ) { // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed // depending on the allocation scheme rusb->PIPEBUF = 0x7C08; diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index e04a996856..28b6905121 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -47,15 +47,15 @@ extern "C" { #pragma GCC diagnostic pop #endif -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - // IAR does not have __builtin_ctz #if defined(__ICCARM__) #define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x)) #endif +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + typedef struct { uint32_t reg_base; int32_t irqnum; @@ -78,6 +78,13 @@ static rusb2_controller_t rusb2_controller[] = { #define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) +#define rusb2_is_highspeed_rhport(_p) (_p == 1) +#define rusb2_is_highspeed_reg(_reg) (_reg == RUSB2_REG(1)) + +//--------------------------------------------------------------------+ +// RUSB2 API +//--------------------------------------------------------------------+ + TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { uint32_t const mask = 1U << (11+rhport); if (start) { diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index 17b9a918cd..7bf4be47e6 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -42,6 +42,15 @@ TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) { return (rusb2_reg_t *) RUSB2_REG_BASE; } + +#define rusb2_is_highspeed_rhport(_p) (false) +#define rusb2_is_highspeed_reg(_reg) (false) + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + + // Start/Stop MSTP TODO implement later TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { (void) rhport; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 28cec99998..aceeb3c3e7 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -48,6 +48,20 @@ extern "C" { TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN +// TODO same as RUSB2_PIPE_TR_t +typedef struct TU_ATTR_PACKED _ccrx_evenaccess { + union { + struct { + uint16_t : 8; + uint16_t TRCLR: 1; + uint16_t TRENB: 1; + uint16_t : 0; + }; + uint16_t TRE; + }; + uint16_t TRN; +} reg_pipetre_t; + typedef struct { union { volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ From fbaa148fe0f4a4b83f41efe9887a8909161710f6 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 18 Jul 2023 15:22:09 +0700 Subject: [PATCH 25/40] updating hcd rusb2 - make osal_task_delay() as weak function in usbh - implement osal_task_delay() in hcd rusb2 (may moved to other places) --- examples/device/cdc_msc_freertos/skip.txt | 1 + .../device/hid_composite_freertos/skip.txt | 1 + examples/dual/host_hid_to_device_cdc/only.txt | 1 + hw/bsp/ra/boards/ra6m5_ek/board.cmake | 7 +- hw/bsp/ra/family.cmake | 2 +- src/host/usbh.c | 2 +- src/portable/renesas/rusb2/dcd_rusb2.c | 12 +- src/portable/renesas/rusb2/hcd_rusb2.c | 123 +++++++++--------- src/portable/renesas/rusb2/rusb2_ra.h | 7 - 9 files changed, 78 insertions(+), 78 deletions(-) diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt index 49b8ee57b8..a6f96b2885 100644 --- a/examples/device/cdc_msc_freertos/skip.txt +++ b/examples/device/cdc_msc_freertos/skip.txt @@ -8,5 +8,6 @@ mcu:RP2040 mcu:SAMD11 mcu:SAMX7X mcu:VALENTYUSB_EPTRI +mcu:RAXXX family:broadcom_32bit family:broadcom_64bit diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt index 49b8ee57b8..a6f96b2885 100644 --- a/examples/device/hid_composite_freertos/skip.txt +++ b/examples/device/hid_composite_freertos/skip.txt @@ -8,5 +8,6 @@ mcu:RP2040 mcu:SAMD11 mcu:SAMX7X mcu:VALENTYUSB_EPTRI +mcu:RAXXX family:broadcom_32bit family:broadcom_64bit diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt index 6ee8e3fdef..d9700677f1 100644 --- a/examples/dual/host_hid_to_device_cdc/only.txt +++ b/examples/dual/host_hid_to_device_cdc/only.txt @@ -1,3 +1,4 @@ board:mimxrt1060_evk board:mimxrt1064_evk mcu:RP2040 +mcu:ra6m5 diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index 5a615f9b03..c91d48a326 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -3,15 +3,20 @@ set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) -# default to PORT1 Highspeed +# Device port default to PORT1 Highspeed if (NOT DEFINED PORT) set(PORT 1) endif() +# Host port will be the other port +set(HOST_PORT $) + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC BOARD_TUD_RHPORT=${PORT} + BOARD_TUH_RHPORT=${HOST_PORT} # port 0 is fullspeed, port 1 is highspeed BOARD_TUD_MAX_SPEED=$ + BOARD_TUH_MAX_SPEED=$ ) endfunction() diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index f09e86a729..2c45b8d71a 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS RAXXX CACHE INTERNAL "") +set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "") #------------------------------------ # BOARD_TARGET diff --git a/src/host/usbh.c b/src/host/usbh.c index 184bda23bf..1418cfb794 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -256,7 +256,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t #if CFG_TUSB_OS == OPT_OS_NONE // TODO rework time-related function later -void osal_task_delay(uint32_t msec) +TU_ATTR_WEAK void osal_task_delay(uint32_t msec) { const uint32_t start = hcd_frame_number(_usbh_controller); while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {} diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 358e5644b3..6fee4edd72 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -27,12 +27,12 @@ #include "tusb_option.h" +#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2) + // Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) // We disable SOF for now until needed later on #define USE_SOF 0 -#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2) - #include "device/dcd.h" #include "rusb2_type.h" @@ -53,6 +53,13 @@ #error "Unsupported MCU" #endif +//--------------------------------------------------------------------+ +// Application API for setting IRQ number +//--------------------------------------------------------------------+ +void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { + rusb2_controller[rhport].irqnum = irqnum; +} + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -681,7 +688,6 @@ static void enable_interrupt(uint32_t pswi) void dcd_init(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - rusb2_module_start(rhport, true); #ifdef RUSB2_SUPPORT_HIGHSPEED diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 4e5ff03594..656051e2ba 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -27,8 +27,7 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ - TU_CHECK_MCU(OPT_MCU_RAXXX)) +#if CFG_TUH_ENABLED && defined(TUP_USBIP_RUSB2) #include "host/hcd.h" #include "rusb2_type.h" @@ -41,8 +40,14 @@ #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" + #elif TU_CHECK_MCU(OPT_MCU_RAXXX) #include "rusb2_ra.h" + + void osal_task_delay(uint32_t msec) { + R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); + } + #else #error "Unsupported MCU" #endif @@ -67,19 +72,6 @@ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct TU_ATTR_PACKED { - union { - struct { - uint16_t : 8; - uint16_t TRCLR: 1; - uint16_t TRENB: 1; - uint16_t : 0; - }; - uint16_t TRE; - }; - uint16_t TRN; -} reg_pipetre_t; - typedef union TU_ATTR_PACKED { struct { volatile uint16_t u8: 8; @@ -308,8 +300,9 @@ static bool pipe_xfer_out(unsigned num) pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) + if (len < mps) { RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + } RUSB2->D0FIFOSEL = 0; while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; @@ -488,60 +481,60 @@ static void enable_interrupt(uint32_t pswi) bool hcd_init(uint8_t rhport) { - (void)rhport; - -#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) - RUSB2->SYSCFG_b.HSE = 1; - RUSB2->PHYSET_b.HSEB = 0; - RUSB2->PHYSET_b.DIRPD = 0; - R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); - RUSB2->PHYSET_b.PLLRESET = 0; - RUSB2->LPSTS_b.SUSPENDM = 1; - while (!RUSB2->PLLSTA_b.PLLLOCK); - RUSB2->SYSCFG_b.DRPD = 1; - RUSB2->SYSCFG_b.DCFM = 1; - RUSB2->SYSCFG_b.DPRPU = 0; - RUSB2->SYSCFG_b.CNEN = 1; - RUSB2->BUSWAIT |= 0x0F00U; - RUSB2->SOFCFG_b.INTL = 1; - RUSB2->DVSTCTR0_b.VBUSEN = 1; - RUSB2->CFIFOSEL_b.MBW = 1; - RUSB2->D0FIFOSEL_b.MBW = 1; - RUSB2->D1FIFOSEL_b.MBW = 1; - RUSB2->INTSTS0 = 0; - for (volatile int i = 0; i < 30000; ++i) ; - RUSB2->SYSCFG_b.USBE = 1; -#else - /* HOST DEVICE Full SPEED */ - RUSB2->SYSCFG_b.SCKE = 1; /* USB Clock enable */ - while (!RUSB2->SYSCFG_b.SCKE) ; - RUSB2->SYSCFG_b.DPRPU = 0; /* D+ pull up enable - 0/disable in host mode */ - RUSB2->SYSCFG_b.DRPD = 1; /* D+/D- pull down - 1/in Host mode (pag.834)*/ - RUSB2->SYSCFG_b.DCFM = 1; /* HOST or Device - 1/HOST */ - - RUSB2->DVSTCTR0_b.VBUSEN = 1; - - RUSB2->SYSCFG_b.DRPD = 1; - for (volatile int i = 0; i < 30000; ++i) ; - RUSB2->SYSCFG_b.USBE = 1; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + rusb2_module_start(rhport, true); + +#ifdef RUSB2_SUPPORT_HIGHSPEED + if (rusb2_is_highspeed_rhport(rhport) ) { + rusb->SYSCFG_b.HSE = 1; + rusb->PHYSET_b.HSEB = 0; + rusb->PHYSET_b.DIRPD = 0; + R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); + rusb->PHYSET_b.PLLRESET = 0; + rusb->LPSTS_b.SUSPENDM = 1; + while ( !rusb->PLLSTA_b.PLLLOCK ); + rusb->SYSCFG_b.DRPD = 1; + rusb->SYSCFG_b.DCFM = 1; + rusb->SYSCFG_b.DPRPU = 0; + rusb->SYSCFG_b.CNEN = 1; + rusb->BUSWAIT |= 0x0F00U; + rusb->SOFCFG_b.INTL = 1; + rusb->DVSTCTR0_b.VBUSEN = 1; + rusb->CFIFOSEL_b.MBW = 1; + rusb->D0FIFOSEL_b.MBW = 1; + rusb->D1FIFOSEL_b.MBW = 1; + rusb->INTSTS0 = 0; + for ( volatile int i = 0; i < 30000; ++i ); + rusb->SYSCFG_b.USBE = 1; + } else #endif + { + rusb->SYSCFG_b.SCKE = 1; + while ( !rusb->SYSCFG_b.SCKE ) {} + rusb->SYSCFG_b.DCFM = 1; // Host function + rusb->SYSCFG_b.DPRPU = 0; // Disable D+ pull up + rusb->SYSCFG_b.DRPD = 1; // Enable D+/D- pull down - // MCU specific PHY init - rusb2_phy_init(); + rusb->DVSTCTR0_b.VBUSEN = 1; + for ( volatile int i = 0; i < 30000; ++i ) {} // FIXME do we need to wait here? how long ? + //R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS); + rusb->SYSCFG_b.USBE = 1; -#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) - RUSB2->PHYSLEW = 0x5; - RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ -#endif + // MCU specific PHY init + rusb2_phy_init(); + + rusb->PHYSLEW = 0x5; + rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ + } /* Setup default control pipe */ - RUSB2->DCPCFG = RUSB2_PIPECFG_SHTNAK_Msk; - RUSB2->DCPMAXP = 64; - RUSB2->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk; - RUSB2->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk; - RUSB2->BEMPENB = 1; - RUSB2->NRDYENB = 1; - RUSB2->BRDYENB = 1; + rusb->DCPCFG = RUSB2_PIPECFG_SHTNAK_Msk; + rusb->DCPMAXP = 64; + rusb->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk; + rusb->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk; + rusb->BEMPENB = 1; + rusb->NRDYENB = 1; + rusb->BRDYENB = 1; return true; } diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 28b6905121..8a4d2ad36c 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -106,13 +106,6 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) { } -//--------------------------------------------------------------------+ -// Application API for setting IRQ number -//--------------------------------------------------------------------+ -void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { - rusb2_controller[rhport].irqnum = irqnum; -} - #ifdef __cplusplus } #endif From 1cb3f0e92a2e35155245452c54f599a733df9604 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Jul 2023 18:56:13 +0700 Subject: [PATCH 26/40] increase stack size for 6 series to 0x1000, 4 series to 0x800 --- hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h | 2 +- hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h | 4 ++-- hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h | 2 +- hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h index f0577b7027..11d5795dfe 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -12,7 +12,7 @@ #define BSP_CFG_BOOT_IMAGE (1) #endif #define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_STACK_MAIN_BYTES (0x800) #define BSP_CFG_HEAP_BYTES (0x1000) #define BSP_CFG_PARAM_CHECKING_ENABLE (1) #define BSP_CFG_ASSERT (0) diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h index 47de7747df..862ec25b7c 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h @@ -27,8 +27,8 @@ extern "C" { #define BSP_CFG_BOOT_IMAGE (1) #endif #define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -#define BSP_CFG_HEAP_BYTES (0x400) +#define BSP_CFG_STACK_MAIN_BYTES (0x800) +#define BSP_CFG_HEAP_BYTES (0x800) #define BSP_CFG_PARAM_CHECKING_ENABLE (1) #define BSP_CFG_ASSERT (0) #define BSP_CFG_ERROR_LOG (0) diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h index b5ed53a3b2..772e5e5b14 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -31,7 +31,7 @@ extern "C" { #endif #define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) #define BSP_CFG_HEAP_BYTES (0x1000) #define BSP_CFG_PARAM_CHECKING_ENABLE (1) #define BSP_CFG_ASSERT (0) diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h index a41536eda5..33d3818501 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h @@ -27,7 +27,7 @@ extern "C" { #define BSP_CFG_BOOT_IMAGE (1) #endif #define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) #define BSP_CFG_HEAP_BYTES (0x1000) #define BSP_CFG_PARAM_CHECKING_ENABLE (1) #define BSP_CFG_ASSERT (0) From 6b6dcc6c099eeafaa6d76bf6133181874beabc0d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Jul 2023 19:50:50 +0700 Subject: [PATCH 27/40] refactored multiple ports for hcd rusb2 --- .idea/cmake.xml | 15 +- .idea/runConfigurations/ra6m5.xml | 2 +- hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug | 4 +- src/portable/renesas/rusb2/dcd_rusb2.c | 37 +- src/portable/renesas/rusb2/hcd_rusb2.c | 452 ++++++++++--------- 5 files changed, 268 insertions(+), 242 deletions(-) diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 864ff615ba..519623b718 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,7 +2,6 @@ - @@ -26,27 +25,27 @@ - - - + + + - + + - - - + + \ No newline at end of file diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml index 02df116105..89f9787a0b 100644 --- a/.idea/runConfigurations/ra6m5.xml +++ b/.idea/runConfigurations/ra6m5.xml @@ -1,5 +1,5 @@ - + diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug index aebb291628..7b8ee9c953 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug +++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug @@ -20,7 +20,9 @@ void OnProjectLoad (void) { Project.SetTraceSource ("Trace Pins"); Project.SetTracePortWidth (4); - File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf"); + //File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf"); + //File.Open ("../../../../../../examples/dual/cmake-build-ra6m5/host_hid_to_device_cdc/host_hid_to_device_cdc.elf"); + File.Open ("../../../../../../examples/cmake-build-ra6m5/host/cdc_msc_hid/cdc_msc_hid.elf"); } /********************************************************************* * diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 6fee4edd72..83f0fdc4a1 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -83,6 +83,18 @@ typedef struct TU_ATTR_PACKED TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) TU_ATTR_BIT_FIELD_ORDER_END +typedef struct +{ + pipe_state_t pipe[10]; + uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ +} dcd_data_t; + +static dcd_data_t _dcd; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ + // Transfer conditions specifiable for each pipe: // - Pipe 0: Control transfer with 64-byte single buffer // - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up @@ -96,18 +108,6 @@ enum { PIPE_COUNT = 10, }; -typedef struct -{ - pipe_state_t pipe[10]; - uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ -} dcd_data_t; - -static dcd_data_t _dcd; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ - static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -746,20 +746,17 @@ void dcd_init(uint8_t rhport) } } -void dcd_int_enable(uint8_t rhport) -{ +void dcd_int_enable(uint8_t rhport) { rusb2_int_enable(rhport); } -void dcd_int_disable(uint8_t rhport) -{ +void dcd_int_disable(uint8_t rhport) { rusb2_int_disable(rhport); } -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - (void)dev_addr; +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; } void dcd_remote_wakeup(uint8_t rhport) diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 656051e2ba..a4b534a051 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -52,23 +52,12 @@ #error "Unsupported MCU" #endif -#define TU_RUSB2_HCD_DBG 0 +#define TU_RUSB2_HCD_DBG 2 //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ -/* LINK core registers */ -#if defined(__CCRX__) - #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) -#elif defined(__RX__) - #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) -#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) - #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE) -#else - #define RUSB2 ((R_USB_FS0_Type*) R_USB_FS0_BASE) -#endif - TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN @@ -108,79 +97,97 @@ typedef struct //--------------------------------------------------------------------+ static hcd_data_t _hcd; -static unsigned find_pipe(unsigned xfer) -{ - switch (xfer) { - case TUSB_XFER_ISOCHRONOUS: - for (int i = 1; i <= 2; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_BULK: - for (int i = 3; i <= 5; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - for (int i = 1; i <= 2; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_INTERRUPT: - for (int i = 6; i <= 9; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - default: - /* No support for control transfer */ - break; +// TODO merged with DCD +// Transfer conditions specifiable for each pipe: +// - Pipe 0: Control transfer with 64-byte single buffer +// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up +// to 2 KB and optional double buffer +// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and +// optional double buffer +// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer +enum { + PIPE_1ST_BULK = 3, + PIPE_1ST_INTERRUPT = 6, + PIPE_COUNT = 10, +}; + +static unsigned find_pipe(unsigned xfer) { + switch ( xfer ) { + case TUSB_XFER_ISOCHRONOUS: + for (int i = 1; i < PIPE_1ST_BULK; ++i) { + if ( 0 == _hcd.pipe[i].ep ) return i; + } + break; + + case TUSB_XFER_BULK: + for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) { + if ( 0 == _hcd.pipe[i].ep ) return i; + } + for (int i = 1; i < PIPE_1ST_BULK; ++i) { + if ( 0 == _hcd.pipe[i].ep ) return i; + } + break; + + case TUSB_XFER_INTERRUPT: + for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) { + if ( 0 == _hcd.pipe[i].ep ) return i; + } + break; + + default: + /* No support for control transfer */ + break; } return 0; } -static volatile uint16_t* get_pipectr(unsigned num) +static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num) { if (num) { - return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]); + return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]); } else { - return (volatile uint16_t*)&(RUSB2->DCPCTR); + return (volatile uint16_t*)&(rusb->DCPCTR); } } -static volatile reg_pipetre_t* get_pipetre(unsigned num) +static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E); + tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E); } return tre; } -static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) +static volatile uint16_t* addr_to_pipectr(uint8_t rhport, uint8_t dev_addr, unsigned ep_addr) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); const unsigned epn = tu_edpt_number(ep_addr); + if (epn) { const unsigned dir_in = tu_edpt_dir(ep_addr); const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; - return get_pipectr(num); + return get_pipectr(rusb, num); } else { - return get_pipectr(0); + return get_pipectr(rusb, 0); } } -static unsigned edpt0_max_packet_size(void) +static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb) { - return RUSB2->DCPMAXP_b.MXPS; + return rusb->DCPMAXP_b.MXPS; } -static unsigned edpt_max_packet_size(unsigned num) +static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num) { - RUSB2->PIPESEL = num; - return RUSB2->PIPEMAXP_b.MXPS; + rusb->PIPESEL = num; + return rusb->PIPEMAXP_b.MXPS; } -static inline void pipe_wait_for_ready(unsigned num) +static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num) { - while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ; - while (!RUSB2->D0FIFOCTR_b.FRDY) ; + while (rusb->D0FIFOSEL_b.CURPIPE != num) ; + while (!rusb->D0FIFOCTR_b.FRDY) {} } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -205,33 +212,33 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) while (len--) *p++ = *reg; } -static bool pipe0_xfer_in(void) +static bool pipe0_xfer_in(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_hcd.pipe[0]; const unsigned rem = pipe->remaining; - const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = RUSB2->CFIFOCTR_b.DTLN; + const unsigned mps = edpt0_max_packet_size(rusb); + const unsigned vld = rusb->CFIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; - pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len); + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return true; } - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; return false; } -static bool pipe0_xfer_out(void) +static bool pipe0_xfer_out(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_hcd.pipe[0]; const unsigned rem = pipe->remaining; @@ -239,40 +246,40 @@ static bool pipe0_xfer_out(void) pipe->buf = NULL; return true; } - const unsigned mps = edpt0_max_packet_size(); + const unsigned mps = edpt0_max_packet_size(rusb); const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len); + pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } pipe->remaining = rem - len; return false; } -static bool pipe_xfer_in(unsigned num) +static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) { pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned rem = pipe->remaining; - RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned vld = RUSB2->D0FIFOCTR_b.DTLN; + rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; + const unsigned mps = edpt_max_packet_size(rusb, num); + pipe_wait_for_ready(rusb, num); + const unsigned vld = rusb->D0FIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); + pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -281,7 +288,7 @@ static bool pipe_xfer_in(unsigned num) return false; } -static bool pipe_xfer_out(unsigned num) +static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) { pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned rem = pipe->remaining; @@ -291,37 +298,39 @@ static bool pipe_xfer_out(unsigned num) return true; } - RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); + rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); + const unsigned mps = edpt_max_packet_size(rusb, num); + pipe_wait_for_ready(rusb, num); const unsigned len = TU_MIN(rem, mps); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); + pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; return false; } -static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +static bool process_pipe0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) { (void)dev_addr; + + rusb2_reg_t* rusb = RUSB2_REG(rhport); const unsigned dir_in = tu_edpt_dir(ep_addr); /* configure fifo direction and access unit settings */ if (dir_in) { /* IN, a byte */ - RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; - while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ; + rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; + while (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ; } else { /* OUT, 2 bytes */ - RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | + rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); - while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ; + while (!(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ; } pipe_state_t *pipe = &_hcd.pipe[0]; @@ -331,26 +340,28 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, if (buflen) { pipe->buf = buffer; if (!dir_in) { /* OUT */ - TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80)); - pipe0_xfer_out(); + TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80)); + pipe0_xfer_out(rusb); } } else { /* ZLP */ pipe->buf = NULL; if (!dir_in) { /* OUT */ - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } - if (dir_in == RUSB2->DCPCFG_b.DIR) { - TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == RUSB2->DCPCTR_b.PID); - RUSB2->DCPCTR_b.SQSET = 1; - RUSB2->DCPCFG_b.DIR = dir_in ^ 1; + if (dir_in == rusb->DCPCFG_b.DIR) { + TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == rusb->DCPCTR_b.PID); + rusb->DCPCTR_b.SQSET = 1; + rusb->DCPCFG_b.DIR = dir_in ^ 1; } } - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; return true; } -static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen) +static bool process_pipe_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); + const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); const unsigned num = _hcd.ep[dev_addr - 1][dir_in][epn - 1]; @@ -363,19 +374,19 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u pipe->remaining = buflen; if (!dir_in) { /* OUT */ if (buflen) { - pipe_xfer_out(num); + pipe_xfer_out(rusb, num); } else { /* ZLP */ - RUSB2->D0FIFOSEL = num; - pipe_wait_for_ready(num); - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + rusb->D0FIFOSEL = num; + pipe_wait_for_ready(rusb, num); + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ } } else { - volatile uint16_t *ctr = get_pipectr(num); - volatile reg_pipetre_t *pt = get_pipetre(num); + volatile uint16_t *ctr = get_pipectr(rusb, num); + volatile reg_pipetre_t *pt = get_pipetre(rusb, num); if (pt) { - const unsigned mps = edpt_max_packet_size(num); + const unsigned mps = edpt_max_packet_size(rusb, num); if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK; pt->TRE = TU_BIT(8); pt->TRN = (buflen + mps - 1) / mps; @@ -386,20 +397,20 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u return true; } -static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +static bool process_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) { const unsigned epn = tu_edpt_number(ep_addr); if (0 == epn) { - return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen); + return process_pipe0_xfer(rhport, dev_addr, ep_addr, buffer, buflen); } else { - return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen); + return process_pipe_xfer(rhport, dev_addr, ep_addr, buffer, buflen); } } static void process_pipe0_bemp(uint8_t rhport) { - (void)rhport; - bool completed = pipe0_xfer_out(); + rusb2_reg_t* rusb = RUSB2_REG(rhport); + bool completed = pipe0_xfer_out(rusb); if (completed) { pipe_state_t *pipe = &_hcd.pipe[0]; hcd_event_xfer_complete(pipe->dev, @@ -411,9 +422,9 @@ static void process_pipe0_bemp(uint8_t rhport) static void process_pipe_nrdy(uint8_t rhport, unsigned num) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); xfer_result_t result; - uint16_t volatile *ctr = get_pipectr(num); + uint16_t volatile *ctr = get_pipectr(rusb, num); TU_LOG(TU_RUSB2_HCD_DBG, "NRDY %d %x\n", num, *ctr); switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) { default: return; @@ -429,19 +440,19 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) static void process_pipe_brdy(uint8_t rhport, unsigned num) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned dir_in = tu_edpt_dir(pipe->ep); bool completed; if (dir_in) { /* IN */ if (num) { - completed = pipe_xfer_in(num); + completed = pipe_xfer_in(rusb, num); } else { - completed = pipe0_xfer_in(); + completed = pipe0_xfer_in(rusb); } } else { - completed = pipe_xfer_out(num); + completed = pipe_xfer_out(rusb, num); } if (completed) { hcd_event_xfer_complete(pipe->dev, pipe->ep, @@ -539,86 +550,88 @@ bool hcd_init(uint8_t rhport) return true; } -void hcd_int_enable(uint8_t rhport) -{ +void hcd_int_enable(uint8_t rhport) { rusb2_int_enable(rhport); } -void hcd_int_disable(uint8_t rhport) -{ +void hcd_int_disable(uint8_t rhport) { rusb2_int_disable(rhport); } uint32_t hcd_frame_number(uint8_t rhport) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + /* The device must be reset at least once after connection * in order to start the frame counter. */ if (_hcd.need_reset) hcd_port_reset(rhport); - return RUSB2->FRMNUM_b.FRNM; + return rusb->FRMNUM_b.FRNM; } /*--------------------------------------------------------------------+ * Port API *--------------------------------------------------------------------+*/ -bool hcd_port_connect_status(uint8_t rhport) -{ - (void)rhport; - return RUSB2->INTSTS1_b.ATTCH ? true : false; +bool hcd_port_connect_status(uint8_t rhport) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); + return rusb->INTSTS1_b.ATTCH ? true : false; } -void hcd_port_reset(uint8_t rhport) -{ - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; - while (RUSB2->DCPCTR_b.PBUSY) ; +void hcd_port_reset(uint8_t rhport) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + while (rusb->DCPCTR_b.PBUSY) {} + hcd_int_disable(rhport); - RUSB2->DVSTCTR0_b.UACT = 0; - if (RUSB2->DCPCTR_b.SUREQ) { - RUSB2->DCPCTR_b.SUREQCLR = 1; + rusb->DVSTCTR0_b.UACT = 0; + if (rusb->DCPCTR_b.SUREQ) { + rusb->DCPCTR_b.SUREQCLR = 1; } hcd_int_enable(rhport); + /* Reset should be asserted 10-20ms. */ - RUSB2->DVSTCTR0_b.USBRST = 1; - for (volatile int i = 0; i < 2400000; ++i) ; - RUSB2->DVSTCTR0_b.USBRST = 0; - RUSB2->DVSTCTR0_b.UACT = 1; + rusb->DVSTCTR0_b.USBRST = 1; + for (volatile int i = 0; i < 2400000; ++i) {} + rusb->DVSTCTR0_b.USBRST = 0; + + rusb->DVSTCTR0_b.UACT = 1; _hcd.need_reset = false; } -void hcd_port_reset_end(uint8_t rhport) -{ +void hcd_port_reset_end(uint8_t rhport) { (void) rhport; } -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ - (void)rhport; - switch (RUSB2->DVSTCTR0_b.RHST) { - default: return TUSB_SPEED_INVALID; +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); + switch (rusb->DVSTCTR0_b.RHST) { + case RUSB2_DVSTCTR0_RHST_HS: return TUSB_SPEED_HIGH; case RUSB2_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL; - case RUSB2_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; + case RUSB2_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; + default: return TUSB_SPEED_INVALID; } } -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); uint16_t volatile *ctr; + TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */ if (!dev_addr) return; + _hcd.ctl_mps[dev_addr] = 0; uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0]; + for (int i = 0; i < 2 * 15; ++i, ++ep) { unsigned num = *ep; if (!num || (dev_addr != _hcd.pipe[num].dev)) continue; - ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1]; + ctr = (uint16_t volatile*)&rusb->PIPE_CTR[num - 1]; *ctr = 0; - RUSB2->NRDYENB &= ~TU_BIT(num); - RUSB2->BRDYENB &= ~TU_BIT(num); - RUSB2->PIPESEL = num; - RUSB2->PIPECFG = 0; - RUSB2->PIPEMAXP = 0; + rusb->NRDYENB &= ~TU_BIT(num); + rusb->BRDYENB &= ~TU_BIT(num); + rusb->PIPESEL = num; + rusb->PIPECFG = 0; + rusb->PIPEMAXP = 0; _hcd.pipe[num].ep = 0; _hcd.pipe[num].dev = 0; @@ -631,52 +644,54 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) *--------------------------------------------------------------------+*/ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { - (void)rhport; - TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, RUSB2->DCPCTR); - TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ); - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, rusb->DCPCTR); + + TU_ASSERT(0 == rusb->DCPCTR_b.SUREQ); + + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; _hcd.pipe[0].buf = NULL; _hcd.pipe[0].length = 8; _hcd.pipe[0].remaining = 0; _hcd.pipe[0].dev = dev_addr; - while (RUSB2->DCPCTR_b.PBUSY) ; - RUSB2->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; + while (rusb->DCPCTR_b.PBUSY) ; + rusb->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; /* Set direction in advance for DATA stage */ uint8_t const bmRequesttype = setup_packet[0]; - RUSB2->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; + rusb->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; - RUSB2->USBREQ = tu_htole16(p[0]); - RUSB2->USBVAL = p[1]; - RUSB2->USBINDX = p[2]; - RUSB2->USBLENG = p[3]; + rusb->USBREQ = tu_htole16(p[0]); + rusb->USBVAL = p[1]; + rusb->USBINDX = p[2]; + rusb->USBLENG = p[3]; - RUSB2->DCPCTR_b.SUREQ = 1; + rusb->DCPCTR_b.SUREQ = 1; return true; } bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc) { - (void)rhport; TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ + rusb2_reg_t* rusb = RUSB2_REG(rhport); const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned mps = tu_edpt_packet_size(ep_desc); + if (0 == epn) { - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; hcd_devtree_info_t devtree; hcd_devtree_get_info(dev_addr, &devtree); - uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &RUSB2->DEVADD[0]; + uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &rusb->DEVADD[0]; devadd += dev_addr; - while (RUSB2->DCPCTR_b.PBUSY) ; - RUSB2->DCPMAXP = (dev_addr << 12) | mps; + while (rusb->DCPCTR_b.PBUSY) {} + rusb->DCPMAXP = (dev_addr << 12) | mps; *devadd = (TUSB_SPEED_FULL == devtree.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS; _hcd.ctl_mps[dev_addr] = mps; return true; @@ -690,17 +705,20 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const } const unsigned num = find_pipe(xfer); if (!num) return false; + _hcd.pipe[num].dev = dev_addr; _hcd.pipe[num].ep = ep_addr; _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num; /* setup pipe */ hcd_int_disable(rhport); - RUSB2->PIPESEL = num; - RUSB2->PIPEMAXP = (dev_addr << 12) | mps; - volatile uint16_t *ctr = get_pipectr(num); + + rusb->PIPESEL = num; + rusb->PIPEMAXP = (dev_addr << 12) | mps; + volatile uint16_t *ctr = get_pipectr(rusb, num); *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk; *ctr = 0; + unsigned cfg = ((1 ^ dir_in) << 4) | epn; if (xfer == TUSB_XFER_BULK) { cfg |= RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk; @@ -709,13 +727,16 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const } else { cfg |= RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk; } - RUSB2->PIPECFG = cfg; - RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num); - RUSB2->NRDYENB |= TU_BIT(num); - RUSB2->BRDYENB |= TU_BIT(num); + + rusb->PIPECFG = cfg; + rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num); + rusb->NRDYENB |= TU_BIT(num); + rusb->BRDYENB |= TU_BIT(num); + if (!dir_in) { *ctr = RUSB2_PIPE_CTR_PID_BUF; } + hcd_int_enable(rhport); return true; @@ -726,14 +747,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b bool r; hcd_int_disable(rhport); TU_LOG(TU_RUSB2_HCD_DBG, "X %d %x %u\n", dev_addr, ep_addr, buflen); - r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); + r = process_edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen); hcd_int_enable(rhport); return r; } bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) { - uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr); + uint8_t rhport = 0; // FIXME change API + uint16_t volatile *ctr = addr_to_pipectr(rhport, dev_addr, ep_addr); TU_ASSERT(ctr); const uint32_t pid = *ctr & 0x3; @@ -756,67 +778,73 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) //--------------------------------------------------------------------+ void hcd_int_handler(uint8_t rhport) { - (void)rhport; -#if defined(__CCRX__) - static const int Mod37BitPosition[] = { - -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, - 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, - 20, 8, 19, 18}; -#endif + rusb2_reg_t* rusb = RUSB2_REG(rhport); static unsigned char attach_attempt = 0; - unsigned is1 = RUSB2->INTSTS1; - unsigned is0 = RUSB2->INTSTS0; + unsigned is0 = rusb->INTSTS0; + unsigned is1 = rusb->INTSTS1; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); - RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); - TU_LOG(TU_RUSB2_HCD_DBG, "IS %04x %04x\n", is0, is1); - is1 &= RUSB2->INTENB1; - is0 &= RUSB2->INTENB0; + rusb->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); + rusb->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); + + TU_LOG3("IS %04x %04x\n", is0, is1); + is1 &= rusb->INTENB1; + is0 &= rusb->INTENB0; if (is1 & RUSB2_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ - RUSB2->DCPCTR_b.SQSET = 1; + rusb->DCPCTR_b.SQSET = 1; attach_attempt = 0; - hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); + hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } + if (is1 & RUSB2_INTSTS1_SIGN_Msk) { - hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); + hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); if(attach_attempt > 0) { - RUSB2->DVSTCTR0_b.UACT = 1; + rusb->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; - RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; + rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; hcd_event_device_attach(rhport, true); } attach_attempt--; } + if (is1 & RUSB2_INTSTS1_ATTCH_Msk) { attach_attempt = 10; - RUSB2->DVSTCTR0_b.UACT = 1; + rusb->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; - RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; + rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; hcd_event_device_attach(rhport, true); } + if (is1 & RUSB2_INTSTS1_DTCH_Msk) { - RUSB2->DVSTCTR0_b.UACT = 0; - if (RUSB2->DCPCTR_b.SUREQ) { - RUSB2->DCPCTR_b.SUREQCLR = 1; + rusb->DVSTCTR0_b.UACT = 0; + if (rusb->DCPCTR_b.SUREQ) { + rusb->DCPCTR_b.SUREQCLR = 1; } - RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk; + rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk; hcd_event_device_remove(rhport, true); } if (is0 & RUSB2_INTSTS0_BEMP_Msk) { - const unsigned s = RUSB2->BEMPSTS; - RUSB2->BEMPSTS = 0; + const unsigned s = rusb->BEMPSTS; + rusb->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } + +#if defined(__CCRX__) + static const int Mod37BitPosition[] = { + -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, + 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, + 20, 8, 19, 18}; +#endif + if (is0 & RUSB2_INTSTS0_NRDY_Msk) { - const unsigned m = RUSB2->NRDYENB; - unsigned s = RUSB2->NRDYSTS & m; - RUSB2->NRDYSTS = ~s; + const unsigned m = rusb->NRDYENB; + unsigned s = rusb->NRDYSTS & m; + rusb->NRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; @@ -828,10 +856,10 @@ void hcd_int_handler(uint8_t rhport) } } if (is0 & RUSB2_INTSTS0_BRDY_Msk) { - const unsigned m = RUSB2->BRDYENB; - unsigned s = RUSB2->BRDYSTS & m; + const unsigned m = rusb->BRDYENB; + unsigned s = rusb->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - RUSB2->BRDYSTS = ~s; + rusb->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; From 6021803d584a95efac5bc10f89ed970b2c1fa60e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Jul 2023 11:33:26 +0700 Subject: [PATCH 28/40] fix ci --- src/portable/renesas/rusb2/dcd_rusb2.c | 13 ++++++------- src/portable/renesas/rusb2/rusb2_ra.h | 9 ++++++--- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 83f0fdc4a1..0380f36b90 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -49,17 +49,16 @@ #define D0FIFOCTR CFIFOCTR #define D0FIFOCTR_b CFIFOCTR_b #endif + + // Application API for setting IRQ number + void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { + rusb2_controller[rhport].irqnum = irqnum; + } + #else #error "Unsupported MCU" #endif -//--------------------------------------------------------------------+ -// Application API for setting IRQ number -//--------------------------------------------------------------------+ -void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { - rusb2_controller[rhport].irqnum = irqnum; -} - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 8a4d2ad36c..7ff272bbc2 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -64,8 +64,14 @@ typedef struct { #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) #define RUSB2_SUPPORT_HIGHSPEED #define RUSB2_CONTROLLER_COUNT 2 + + #define rusb2_is_highspeed_rhport(_p) (_p == 1) + #define rusb2_is_highspeed_reg(_reg) (_reg == RUSB2_REG(1)) #else #define RUSB2_CONTROLLER_COUNT 1 + + #define rusb2_is_highspeed_rhport(_p) (false) + #define rusb2_is_highspeed_reg(_reg) (false) #endif // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP @@ -78,9 +84,6 @@ static rusb2_controller_t rusb2_controller[] = { #define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) -#define rusb2_is_highspeed_rhport(_p) (_p == 1) -#define rusb2_is_highspeed_reg(_reg) (_reg == RUSB2_REG(1)) - //--------------------------------------------------------------------+ // RUSB2 API //--------------------------------------------------------------------+ From e56d5443a8a87e932b22bc6315f30cd537fe0edf Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Jul 2023 12:42:40 +0700 Subject: [PATCH 29/40] - revert usb address - more clean up --- src/portable/renesas/rusb2/dcd_rusb2.c | 6 +++--- src/portable/renesas/rusb2/hcd_rusb2.c | 14 ++++---------- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 0380f36b90..9383923bd2 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -51,7 +51,7 @@ #endif // Application API for setting IRQ number - void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { + void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { rusb2_controller[rhport].irqnum = irqnum; } @@ -638,7 +638,7 @@ static void process_bus_reset(uint8_t rhport) static void process_set_address(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - const uint32_t addr = rusb->USBADDR & 0xFF; + const uint16_t addr = rusb->USBADDR_b.USBADDR; if (!addr) return; const tusb_control_request_t setup_packet = { @@ -821,7 +821,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) if ( rusb2_is_highspeed_rhport(rhport) ) { // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed - // depending on the allocation scheme + // depending on the allocation scheme rusb->PIPEBUF = 0x7C08; } diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index fef8bdf195..c5ed8ae55c 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -32,21 +32,15 @@ #include "host/hcd.h" #include "rusb2_type.h" -#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) -// fallback -#define CFG_TUSB_RHPORT0_MODE OPT_MODE_HOST -#define CFG_TUSB_RHPORT1_MODE 0 -#endif - #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) #include "rusb2_ra.h" - void osal_task_delay(uint32_t msec) { - R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); - } +// void osal_task_delay(uint32_t msec) { +// R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); +// } #else #error "Unsupported MCU" @@ -785,7 +779,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { void hcd_int_handler(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - static unsigned char attach_attempt = 0; + static unsigned char attach_attempt = 0; // TODO remove later unsigned is0 = rusb->INTSTS0; unsigned is1 = rusb->INTSTS1; From feb58ebd54e68bc3b7f21b0d168417053c525f0a Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Jul 2023 19:01:12 +0700 Subject: [PATCH 30/40] add uno r4 wih FLASH_IMAGE_START=0x4000, running but interrupt (systick) does not seems to work --- .idea/runConfigurations/ra4m1.xml | 2 +- .idea/runConfigurations/ra6m1.xml | 2 +- .idea/runConfigurations/ra6m5.xml | 2 +- .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 18 ++-- hw/bsp/ra/boards/uno_r4/board.cmake | 11 +++ hw/bsp/ra/boards/uno_r4/board.h | 53 +++++++++++ hw/bsp/ra/boards/uno_r4/board.mk | 9 ++ hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h | 35 ++++++++ .../uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 ++ .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 +++ .../uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 87 +++++++++++++++++++ .../ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h | 21 +++++ hw/bsp/ra/boards/uno_r4/uno_r4.ld | 25 ++++++ hw/bsp/ra/family.mk | 3 +- src/portable/renesas/rusb2/hcd_rusb2.c | 1 + 15 files changed, 272 insertions(+), 13 deletions(-) create mode 100644 hw/bsp/ra/boards/uno_r4/board.cmake create mode 100644 hw/bsp/ra/boards/uno_r4/board.h create mode 100644 hw/bsp/ra/boards/uno_r4/board.mk create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/uno_r4.ld diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml index 22bb619491..149a157c47 100644 --- a/.idea/runConfigurations/ra4m1.xml +++ b/.idea/runConfigurations/ra4m1.xml @@ -1,5 +1,5 @@ - + diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml index 438ac40633..57af9abd94 100644 --- a/.idea/runConfigurations/ra6m1.xml +++ b/.idea/runConfigurations/ra6m1.xml @@ -1,5 +1,5 @@ - + diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml index 89f9787a0b..1a6358304d 100644 --- a/.idea/runConfigurations/ra6m5.xml +++ b/.idea/runConfigurations/ra6m5.xml @@ -1,5 +1,5 @@ - + diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 3bde2db0db..72cdb89e67 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -12,16 +12,16 @@ #define BSP_MOCO_HZ (8000000) #define BSP_SUB_CLOCK_HZ (32768) #if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (24000000) + #define BSP_HOCO_HZ (24000000) #elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) - #elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) - #elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif + #define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake new file mode 100644 index 0000000000..34780d7767 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/board.cmake @@ -0,0 +1,11 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra4m1) + +set(JLINK_DEVICE R7FA4M1AB) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) + +function(update_board TARGET) +# target_compile_definitions(${TARGET} PUBLIC) +# target_sources(${TARGET} PRIVATE) +# target_include_directories(${BOARD_TARGET} PUBLIC) +endfunction() diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h new file mode 100644 index 0000000000..72abda27f9 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/board.h @@ -0,0 +1,53 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED1 BSP_IO_PORT_01_PIN_11 // D13 +#define LED_STATE_ON 1 + +#define SW1 BSP_IO_PORT_01_PIN_10 // D12 +#define BUTTON_STATE_ACTIVE 0 + +static const ioport_pin_cfg_t board_pin_cfg[] = { + {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, + {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, + // USB FS D+, D-, VBus + {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, + {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, + {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk new file mode 100644 index 0000000000..cbe6c782ca --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/board.mk @@ -0,0 +1,9 @@ +CPU_CORE = cortex-m4 +MCU_VARIANT = ra4m1 + +LD_FILE = $(BOARD_PATH)/${BOARD}.ld + +# For flash-jlink target +JLINK_DEVICE = R7FA4M1AB + +flash: flash-jlink diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 0000000000..c1d1022cc1 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,35 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#undef RA_NOT_DEFINED +#define BSP_CFG_RTOS (0) +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x800) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) + +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 0000000000..444d32e560 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000000..336918800f --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CNE +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (262144) +#define BSP_RAM_SIZE_BYTES (32768) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_QFN +#define BSP_PACKAGE_PINS (48) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 0000000000..fc604eb3b1 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,87 @@ +/* generated configuration header file through renesas e2 studio */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA4M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h new file mode 100644 index 0000000000..63618ec4bb --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/uno_r4.ld b/hw/bsp/ra/boards/uno_r4/uno_r4.ld new file mode 100644 index 0000000000..45f11dfb18 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/uno_r4.ld @@ -0,0 +1,25 @@ +RAM_START = 0x20000000; +RAM_LENGTH = 0x8000; +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x40000; +DATA_FLASH_START = 0x40100000; +DATA_FLASH_LENGTH = 0x2000; +OPTION_SETTING_START = 0x00000000; +OPTION_SETTING_LENGTH = 0x0; +OPTION_SETTING_S_START = 0x80000000; +OPTION_SETTING_S_LENGTH = 0x0; +ID_CODE_START = 0x01010018; +ID_CODE_LENGTH = 0x20; +SDRAM_START = 0x80010000; +SDRAM_LENGTH = 0x0; +QSPI_FLASH_START = 0x60000000; +QSPI_FLASH_LENGTH = 0x0; +OSPI_DEVICE_0_START = 0x80020000; +OSPI_DEVICE_0_LENGTH = 0x0; +OSPI_DEVICE_1_START = 0x80030000; +OSPI_DEVICE_1_LENGTH = 0x0; + +/* Uno R4 has bootloader */ +FLASH_IMAGE_START = 0x4000; + +INCLUDE fsp.ld diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index f5097460aa..a5325306dd 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -59,9 +59,10 @@ INC += \ ifndef LD_FILE LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld -LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc endif +LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc + # For freeRTOS port source # hack to use the port provided by renesas FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index c5ed8ae55c..7f49dc8a97 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -186,6 +186,7 @@ static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num) static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { + // NOTE: unlike DCD, Highspeed 32-bit FIFO does not need to adjust the fifo address volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; uintptr_t addr = (uintptr_t)buf; while (len >= 2) { From 0d9973ef87a55276d14c2aa45647f92a8358e9a2 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 31 Jul 2023 16:21:19 +0700 Subject: [PATCH 31/40] enable_irq since uno bootloader can disable it. systick triggered, however usb still not work with uno --- hw/bsp/ra/family.c | 4 ++++ src/portable/renesas/rusb2/dcd_rusb2.c | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index b78fdedc7b..096f0d0fff 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -92,6 +92,10 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT //--------------------------------------------------------------------+ void board_init(void) { + // Enable global interrupts in CPSR register since board with bootloader such as Arduino Uno R4 + // can transfer CPU control with CPSR.I bit set to 0 (disable IRQ) + __enable_irq(); + /* Configure pins. */ R_IOPORT_Open(&port_ctrl, &family_pin_cfg); diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 9383923bd2..37fd93497a 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -740,6 +740,7 @@ void dcd_init(uint8_t rhport) rusb->BEMPENB = 1; rusb->BRDYENB = 1; + // If VBUS (detect) pin is not used, application need to call tud_connect() manually after tud_init() if (rusb->INTSTS0_b.VBSTS) { dcd_connect(rhport); } From cb47231518d8a33bb9c5ab710c819049274d443b Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 31 Jul 2023 17:13:21 +0700 Subject: [PATCH 32/40] revert out of scope changes --- src/host/usbh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/host/usbh.c b/src/host/usbh.c index c8eb91be30..15c48be47c 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -258,7 +258,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t #if CFG_TUSB_OS == OPT_OS_NONE // TODO rework time-related function later -TU_ATTR_WEAK void osal_task_delay(uint32_t msec) +void osal_task_delay(uint32_t msec) { const uint32_t start = hcd_frame_number(_usbh_controller); while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {} From 3f788a4e5a7758ce51cbcadef4ac21e427cc3c56 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 31 Jul 2023 19:09:40 +0700 Subject: [PATCH 33/40] enable USBMC for uno r4, add board_init_after_tusb() API add BOARD_UPPERCASE for board detection --- examples/device/audio_4_channel_mic/src/main.c | 4 ++++ examples/device/audio_test/src/main.c | 4 ++++ examples/device/audio_test_multi_rate/src/main.c | 4 ++++ examples/device/cdc_dual_ports/src/main.c | 4 ++++ examples/device/cdc_msc/src/main.c | 4 ++++ examples/device/cdc_msc_freertos/src/main.c | 4 ++++ examples/device/dfu/src/main.c | 4 ++++ examples/device/dfu_runtime/src/main.c | 4 ++++ examples/device/dynamic_configuration/src/main.c | 4 ++++ examples/device/hid_boot_interface/src/main.c | 4 ++++ examples/device/hid_composite/src/main.c | 4 ++++ examples/device/hid_composite_freertos/src/main.c | 4 ++++ examples/device/hid_generic_inout/src/main.c | 4 ++++ examples/device/hid_multiple_interface/src/main.c | 4 ++++ examples/device/midi_test/src/main.c | 4 ++++ examples/device/msc_dual_lun/src/main.c | 4 ++++ examples/device/net_lwip_webserver/src/main.c | 4 ++++ examples/device/uac2_headset/src/main.c | 4 ++++ examples/device/usbtmc/src/main.c | 4 ++++ examples/device/video_capture/src/main.c | 4 ++++ examples/device/webusb_serial/src/main.c | 4 ++++ examples/dual/host_hid_to_device_cdc/src/main.c | 4 ++++ examples/host/bare_api/src/main.c | 4 ++++ examples/host/cdc_msc_hid/src/main.c | 4 ++++ examples/host/hid_controller/src/main.c | 4 ++++ examples/host/msc_file_explorer/src/main.c | 5 +++++ examples/make.mk | 2 ++ hw/bsp/board.h | 3 +++ hw/bsp/family_support.cmake | 5 +++++ hw/bsp/ra/boards/uno_r4/board.mk | 2 +- hw/bsp/ra/family.c | 7 +++++++ src/portable/renesas/rusb2/dcd_rusb2.c | 2 -- 32 files changed, 123 insertions(+), 3 deletions(-) diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 2b9c5143de..f5fc884bda 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -84,6 +84,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // Init values sampFreq = AUDIO_SAMPLE_RATE; clkValid = 1; diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index b5ca41d362..6dc655416d 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -85,6 +85,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // Init values sampFreq = AUDIO_SAMPLE_RATE; clkValid = 1; diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c index 078e783ebd..637be2d40d 100644 --- a/examples/device/audio_test_multi_rate/src/main.c +++ b/examples/device/audio_test_multi_rate/src/main.c @@ -99,6 +99,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // Init values sampFreq = sampleRatesList[0]; clkValid = 1; diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c index 70eaea85d9..7ceff73b38 100644 --- a/examples/device/cdc_dual_ports/src/main.c +++ b/examples/device/cdc_dual_ports/src/main.c @@ -42,6 +42,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c index 6dad73cbf1..87fc33181e 100644 --- a/examples/device/cdc_msc/src/main.c +++ b/examples/device/cdc_msc/src/main.c @@ -58,6 +58,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 0e8a24d026..6cfef9ef5c 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -136,6 +136,10 @@ void usb_device_task(void* param) // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // RTOS forever loop while (1) { diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c index 5f37f25e16..bcd5b49420 100644 --- a/examples/device/dfu/src/main.c +++ b/examples/device/dfu/src/main.c @@ -77,6 +77,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c index 4ec3cb1889..beef1037d8 100644 --- a/examples/device/dfu_runtime/src/main.c +++ b/examples/device/dfu_runtime/src/main.c @@ -72,6 +72,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c index 578f01d8c5..6c7789138c 100644 --- a/examples/device/dynamic_configuration/src/main.c +++ b/examples/device/dynamic_configuration/src/main.c @@ -59,6 +59,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c index 1a155996a5..47f68f8fa5 100644 --- a/examples/device/hid_boot_interface/src/main.c +++ b/examples/device/hid_boot_interface/src/main.c @@ -59,6 +59,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index 8d0e6becef..d4c5f5b3e4 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -60,6 +60,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index ca02af1005..bdbe26b86e 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -138,6 +138,10 @@ void usb_device_task(void* param) // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // RTOS forever loop while (1) { diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c index 5db8f5581c..5b3e53b062 100644 --- a/examples/device/hid_generic_inout/src/main.c +++ b/examples/device/hid_generic_inout/src/main.c @@ -83,6 +83,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c index 72240b208b..94f845a84e 100644 --- a/examples/device/hid_multiple_interface/src/main.c +++ b/examples/device/hid_multiple_interface/src/main.c @@ -64,6 +64,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c index 2c3e9d954e..c77207ca25 100644 --- a/examples/device/midi_test/src/main.c +++ b/examples/device/midi_test/src/main.c @@ -65,6 +65,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c index c7f6de7bf2..d8abb51516 100644 --- a/examples/device/msc_dual_lun/src/main.c +++ b/examples/device/msc_dual_lun/src/main.c @@ -57,6 +57,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index 19a0eae9da..22543880e7 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -232,6 +232,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + /* initialize lwip, dhcp-server, dns-server, and http */ init_lwip(); while (!netif_is_up(&netif_data)); diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 19a3f7bae2..c502eb10d8 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -105,6 +105,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + TU_LOG1("Headset running\r\n"); while (1) diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c index 2bba336f1e..fa7de75705 100644 --- a/examples/device/usbtmc/src/main.c +++ b/examples/device/usbtmc/src/main.c @@ -57,6 +57,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 5654e0b61e..b942dd30e4 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -59,6 +59,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c index eaca78c730..f63d0ccea6 100644 --- a/examples/device/webusb_serial/src/main.c +++ b/examples/device/webusb_serial/src/main.c @@ -96,6 +96,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c index 817c63c701..5a31b9dda8 100644 --- a/examples/dual/host_hid_to_device_cdc/src/main.c +++ b/examples/dual/host_hid_to_device_cdc/src/main.c @@ -83,6 +83,10 @@ int main(void) tud_init(BOARD_TUD_RHPORT); tuh_init(BOARD_TUH_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index bb7fa850ef..7286befe01 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -67,6 +67,10 @@ int main(void) // init host stack on configured roothub port tuh_init(BOARD_TUH_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { // tinyusb host task diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index 1f4acb822f..51251be5c9 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -48,6 +48,10 @@ int main(void) // init host stack on configured roothub port tuh_init(BOARD_TUH_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { // tinyusb host task diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c index 4dcc92587d..a4ab2f711d 100644 --- a/examples/host/hid_controller/src/main.c +++ b/examples/host/hid_controller/src/main.c @@ -54,6 +54,10 @@ int main(void) // init host stack on configured roothub port tuh_init(BOARD_TUH_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { // tinyusb host task diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index 7b1c2ef276..fc4b4e6696 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -80,6 +80,11 @@ int main(void) // init host stack on configured roothub port tuh_init(BOARD_TUH_RHPORT); + + if (board_init_after_tusb) { + board_init_after_tusb(); + } + msc_app_init(); while (1) diff --git a/examples/make.mk b/examples/make.mk index 3c3a920cc7..4001a53599 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -116,6 +116,8 @@ INC += \ $(TOP)/$(FAMILY_PATH) \ $(TOP)/src \ +BOARD_UPPER = $(shell echo $(BOARD) | tr a-z A-Z) +CFLAGS += -DBOARD_$(BOARD_UPPER) # Log level is mapped to TUSB DEBUG option ifneq ($(LOG),) diff --git a/hw/bsp/board.h b/hw/bsp/board.h index 0365567316..d782013bb2 100644 --- a/hw/bsp/board.h +++ b/hw/bsp/board.h @@ -54,6 +54,9 @@ // Initialize on-board peripherals : led, button, uart and USB void board_init(void); +// Init board after tinyusb is initialized +void board_init_after_tusb(void) TU_ATTR_WEAK; + // Turn LED on or off void board_led_write(bool state); diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index d8298c8ad4..db1ce988e4 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -181,6 +181,11 @@ endfunction() function(family_configure_common TARGET RTOS) family_add_rtos(${TARGET} ${RTOS}) + string(TOUPPER ${BOARD} BOARD_UPPER) + target_compile_definitions(${TARGET} PUBLIC + BOARD_${BOARD_UPPER} + ) + # run size after build add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} $ diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk index cbe6c782ca..b7075eec0b 100644 --- a/hw/bsp/ra/boards/uno_r4/board.mk +++ b/hw/bsp/ra/boards/uno_r4/board.mk @@ -1,7 +1,7 @@ CPU_CORE = cortex-m4 MCU_VARIANT = ra4m1 -LD_FILE = $(BOARD_PATH)/${BOARD}.ld +LD_FILE = ${BOARD_PATH}/${BOARD}.ld # For flash-jlink target JLINK_DEVICE = R7FA4M1AB diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 096f0d0fff..e6213061dd 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -124,6 +124,13 @@ void board_init(void) { board_led_write(false); } +void board_init_after_tusb(void) { + // For board that use USB LDO regulator +#if defined(BOARD_UNO_R4) + R_USB_FS0->USBMC |= R_USB_FS0_USBMC_VDCEN_Msk; +#endif +} + void board_led_write(bool state) { R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON); } diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 37fd93497a..9a3983f56e 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -726,8 +726,6 @@ void dcd_init(uint8_t rhport) rusb->PHYSLEW = 0x5; rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ - - // rusb2->USBMC = (uint16_t) (rusb2->USBMC | RUSB2_USBMC_VDCEN_Msk); } /* Setup default control pipe */ From 1cccbaf7ec12ecf296644e9b51603261a0d586ac Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Aug 2023 11:18:00 +0700 Subject: [PATCH 34/40] fix board name with dash --- examples/make.mk | 2 +- hw/bsp/family_support.cmake | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/examples/make.mk b/examples/make.mk index 4001a53599..4773189dfc 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -116,7 +116,7 @@ INC += \ $(TOP)/$(FAMILY_PATH) \ $(TOP)/src \ -BOARD_UPPER = $(shell echo $(BOARD) | tr a-z A-Z) +BOARD_UPPER = $(shell echo $(subst -,_,$(BOARD)) | tr a-z A-Z) CFLAGS += -DBOARD_$(BOARD_UPPER) # Log level is mapped to TUSB DEBUG option diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index db1ce988e4..8cc7a14208 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -182,6 +182,7 @@ function(family_configure_common TARGET RTOS) family_add_rtos(${TARGET} ${RTOS}) string(TOUPPER ${BOARD} BOARD_UPPER) + string(REPLACE "-" "_" BOARD_UPPER ${BOARD_UPPER}) target_compile_definitions(${TARGET} PUBLIC BOARD_${BOARD_UPPER} ) From 789e478d4d47cca9bd1cf7983a49c13476c54b78 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Aug 2023 13:16:37 +0700 Subject: [PATCH 35/40] add portenta c33 bsp, add flash by dfu-util --- examples/rules.mk | 15 +- hw/bsp/family_support.cmake | 12 + hw/bsp/ra/boards/portenta_c33/board.cmake | 25 ++ hw/bsp/ra/boards/portenta_c33/board.h | 68 +++ hw/bsp/ra/boards/portenta_c33/board.mk | 12 + .../boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h | 63 +++ .../fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../fsp_cfg/bsp/bsp_mcu_family_cfg.h | 387 ++++++++++++++++++ .../portenta_c33/fsp_cfg/bsp_clock_cfg.h | 37 ++ hw/bsp/ra/boards/portenta_c33/portenta_c33.ld | 25 ++ hw/bsp/ra/family.cmake | 5 + hw/bsp/ra/family.mk | 2 + tools/make/toolchain/arm_gcc_rules.mk | 3 +- 14 files changed, 665 insertions(+), 5 deletions(-) create mode 100644 hw/bsp/ra/boards/portenta_c33/board.cmake create mode 100644 hw/bsp/ra/boards/portenta_c33/board.h create mode 100644 hw/bsp/ra/boards/portenta_c33/board.mk create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/portenta_c33.ld diff --git a/examples/rules.mk b/examples/rules.mk index 44698b0195..44d6b84c81 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -88,7 +88,7 @@ linkermap: $(BUILD)/$(PROJECT).elf # Flash Targets # --------------------------------------- -# Jlink binary +# --------------- Jlink ----------------- ifeq ($(OS),Windows_NT) JLINKEXE = JLink.exe else @@ -110,10 +110,12 @@ $(BUILD)/$(BOARD).jlink: $(BUILD)/$(PROJECT).hex flash-jlink: $(BUILD)/$(BOARD).jlink $(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $< +# --------------- stm32 cube programmer ----------------- # Flash STM32 MCU using stlink with STM32 Cube Programmer CLI flash-stlink: $(BUILD)/$(PROJECT).elf STM32_Programmer_CLI --connect port=swd --write $< --go +# --------------- xfel ----------------- $(BUILD)/$(PROJECT)-sunxi.bin: $(BUILD)/$(PROJECT).bin $(PYTHON) $(TOP)/tools/mksunxi.py $< $@ @@ -121,18 +123,23 @@ flash-xfel: $(BUILD)/$(PROJECT)-sunxi.bin xfel spinor write 0 $< xfel reset -# Flash using pyocd +# --------------- pyocd ----------------- PYOCD_OPTION ?= flash-pyocd: $(BUILD)/$(PROJECT).hex pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $< #pyocd reset -t $(PYOCD_TARGET) -# Flash using openocd +# --------------- openocd ----------------- OPENOCD_OPTION ?= flash-openocd: $(BUILD)/$(PROJECT).elf openocd $(OPENOCD_OPTION) -c "program $< verify reset exit" -# flash with Black Magic Probe +# --------------- dfu-util ----------------- +DFU_UTIL_OPTION ?= -a 0 +flash-dfu-util: $(BUILD)/$(PROJECT).bin + dfu-util -R $(DFU_UTIL_OPTION) -D $< + +# --------------- Black Magic ----------------- # This symlink is created by https://github.com/blacksphere/blackmagic/blob/master/driver/99-blackmagic.rules BMP ?= /dev/ttyBmpGdb diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 8cc7a14208..529bdb8f33 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -407,6 +407,18 @@ function(family_flash_nxplink TARGET) endfunction() +function(family_flash_dfu_util TARGET OPTION) + if (NOT DEFINED DFU_UTIL) + set(DFU_UTIL dfu-util) + endif () + + add_custom_target(${TARGET}-dfu-util + DEPENDS ${TARGET} + COMMAND ${DFU_UTIL} -R -d ${DFU_UTIL_VID_PID} -a 0 -D $/${TARGET}.bin + VERBATIM + ) +endfunction() + #---------------------------------- # Family specific #---------------------------------- diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake new file mode 100644 index 0000000000..1837d8450e --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/board.cmake @@ -0,0 +1,25 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra6m5) + +set(JLINK_DEVICE R7FA6M5BH) +set(DFU_UTIL_VID_PID 2341:0368) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) + +# Device port default to PORT1 Highspeed +if (NOT DEFINED PORT) +set(PORT 1) +endif() + +# Host port will be the other port +set(HOST_PORT $) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + BOARD_TUD_RHPORT=${PORT} + BOARD_TUH_RHPORT=${HOST_PORT} + # port 0 is fullspeed, port 1 is highspeed + BOARD_TUD_MAX_SPEED=$ + BOARD_TUH_MAX_SPEED=$ + ) +endfunction() diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h new file mode 100644 index 0000000000..7841ec8b84 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/board.h @@ -0,0 +1,68 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED1 BSP_IO_PORT_01_PIN_07 // Red LED +#define LED_STATE_ON 1 + +#define SW1 BSP_IO_PORT_04_PIN_08 // D12 +#define BUTTON_STATE_ACTIVE 0 + +static const ioport_pin_cfg_t board_pin_cfg[] = { + { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, + { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, + + // USB FS + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, + { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, + { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, + + // USB HS + { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, + { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, + { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, + + // ETM Trace + #ifdef TRACE_ETM + { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + #endif +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk new file mode 100644 index 0000000000..6a5c2ffce8 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/board.mk @@ -0,0 +1,12 @@ +CPU_CORE = cortex-m33 +MCU_VARIANT = ra6m5 + +LD_FILE = ${BOARD_PATH}/${BOARD}.ld + +# Port 1 is highspeed +PORT ?= 1 + +JLINK_DEVICE = R7FA6M5BH +DFU_UTIL_OPTION = -d 2341:0368 -a 0 + +flash: flash-dfu-util diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 0000000000..33d3818501 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,63 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (2) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) +#else + #define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 0000000000..bd6a901c32 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000000..6845183db5 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M5BH3CFC +#define BSP_MCU_FEATURE_SET ('B') +#define BSP_ROM_SIZE_BYTES (2097152) +#define BSP_RAM_SIZE_BYTES (524288) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (176) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 0000000000..d5428540fb --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,387 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA6M5 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* The C-Cache line size that is configured during startup. */ +#ifndef BSP_CFG_C_CACHE_LINE_SIZE +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif + +/* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + +/* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + +/* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) +#endif +#endif + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) +#endif + +/* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif +/* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif +/* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 +#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) +#endif +/* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 +#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) +#endif +/* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif +/* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif +/* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 +#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) +#endif +/* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 +#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif +/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 +#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h new file mode 100644 index 0000000000..0eb5e05167 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h @@ -0,0 +1,37 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ + +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ + +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld new file mode 100644 index 0000000000..ba15588e61 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld @@ -0,0 +1,25 @@ +RAM_START = 0x20000000; +RAM_LENGTH = 0x80000; +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x200000; +DATA_FLASH_START = 0x08000000; +DATA_FLASH_LENGTH = 0x2000; +OPTION_SETTING_START = 0x0100A100; +OPTION_SETTING_LENGTH = 0x100; +OPTION_SETTING_S_START = 0x0100A200; +OPTION_SETTING_S_LENGTH = 0x100; +ID_CODE_START = 0x00000000; +ID_CODE_LENGTH = 0x0; +SDRAM_START = 0x80010000; +SDRAM_LENGTH = 0x0; +QSPI_FLASH_START = 0x60000000; +QSPI_FLASH_LENGTH = 0x4000000; +OSPI_DEVICE_0_START = 0x68000000; +OSPI_DEVICE_0_LENGTH = 0x8000000; +OSPI_DEVICE_1_START = 0x70000000; +OSPI_DEVICE_1_LENGTH = 0x10000000; + +/* Board has bootloader */ +FLASH_IMAGE_START = 0x10000; + +INCLUDE fsp.ld diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 2c45b8d71a..307e01da86 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -124,4 +124,9 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) + + if (DEFINED DFU_UTIL_VID_PID) + family_add_bin_hex(${TARGET}) + family_flash_dfu_util(${TARGET} ${DFU_UTIL_VID_PID}) + endif () endfunction() diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index a5325306dd..cf8e5d9e90 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -3,6 +3,8 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5 FSP_RA = hw/mcu/renesas/fsp/ra/fsp include $(TOP)/$(BOARD_PATH)/board.mk +OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss + # Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk PORT ?= 0 diff --git a/tools/make/toolchain/arm_gcc_rules.mk b/tools/make/toolchain/arm_gcc_rules.mk index f3482b9a8c..b76d4aec3c 100644 --- a/tools/make/toolchain/arm_gcc_rules.mk +++ b/tools/make/toolchain/arm_gcc_rules.mk @@ -65,9 +65,10 @@ $(BUILD)/obj/%_asm.o: %.S @echo AS $(notdir $@) @$(AS) $(ASFLAGS) -c -o $@ $< +OBJCOPY_BIN_OPTION ?= $(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf @echo CREATE $@ - @$(OBJCOPY) -O binary $^ $@ + $(OBJCOPY) -O binary $(OBJCOPY_BIN_OPTION) $^ $@ $(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf @echo CREATE $@ From 40833b585b2c4ea38dec034c18aacff35c6bcea6 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Aug 2023 15:33:15 +0700 Subject: [PATCH 36/40] enable flto for ra makefile - remove ra from ci make build since it is already in cmake ci --- .github/workflows/build_arm.yml | 1 - .idea/cmake.xml | 6 ++++-- .idea/runConfigurations/uno_r4.xml | 10 ++++++++++ hw/bsp/ra/family.mk | 2 ++ 4 files changed, 16 insertions(+), 3 deletions(-) create mode 100644 .idea/runConfigurations/uno_r4.xml diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index 72ddf164b5..44a5e73636 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -39,7 +39,6 @@ jobs: - 'lpc51 lpc54' - 'mm32 msp432e4' - 'nrf' - - 'ra' - 'samd11 samd21' - 'samd51 same5x' - 'saml2x' diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 519623b718..4147bba590 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -44,8 +44,10 @@ - - + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/uno_r4.xml b/.idea/runConfigurations/uno_r4.xml new file mode 100644 index 0000000000..9982f40391 --- /dev/null +++ b/.idea/runConfigurations/uno_r4.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index cf8e5d9e90..9018089587 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -3,12 +3,14 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5 FSP_RA = hw/mcu/renesas/fsp/ra/fsp include $(TOP)/$(BOARD_PATH)/board.mk +# Don't include options setting in .bin file since it create unnecessary large file due to padding OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss # Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk PORT ?= 0 CFLAGS += \ + -flto \ -DCFG_TUSB_MCU=OPT_MCU_RAXXX \ -DBOARD_TUD_RHPORT=$(PORT) \ -Wno-error=undef \ From 965627e81c63a76bb80d8319cbd9adf931a00595 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 1 Aug 2023 11:41:33 +0200 Subject: [PATCH 37/40] rusb2: move dynamic irq function to c file --- hw/bsp/ra/family.cmake | 5 +++-- hw/bsp/ra/family.mk | 1 + src/portable/renesas/rusb2/dcd_rusb2.c | 5 ----- src/portable/renesas/rusb2/rusb2_ra.c | 16 ++++++++++++++++ src/portable/renesas/rusb2/rusb2_ra.h | 9 +-------- 5 files changed, 21 insertions(+), 15 deletions(-) create mode 100644 src/portable/renesas/rusb2/rusb2_ra.c diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 307e01da86..2d079dc94d 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -114,8 +114,9 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c - ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/rusb2_ra.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index cf8e5d9e90..3394d41b4b 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -32,6 +32,7 @@ endif SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ + src/portable/renesas/rusb2/rusb2_ra.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 9a3983f56e..3ec1b70b5b 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -50,11 +50,6 @@ #define D0FIFOCTR_b CFIFOCTR_b #endif - // Application API for setting IRQ number - void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { - rusb2_controller[rhport].irqnum = irqnum; - } - #else #error "Unsupported MCU" #endif diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c new file mode 100644 index 0000000000..bbffd712ec --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_ra.c @@ -0,0 +1,16 @@ +#include "tusb_option.h" +#include "device/dcd.h" +#include "rusb2_type.h" +#include "rusb2_ra.h" + +rusb2_controller_t rusb2_controller[] = { + { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, + #ifdef RUSB2_SUPPORT_HIGHSPEED + { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, + #endif +}; + +// Application API for setting IRQ number +void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { + rusb2_controller[rhport].irqnum = irqnum; +} \ No newline at end of file diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 7ff272bbc2..4774d2e2cc 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -74,14 +74,7 @@ typedef struct { #define rusb2_is_highspeed_reg(_reg) (false) #endif -// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP -static rusb2_controller_t rusb2_controller[] = { - { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, - #ifdef RUSB2_SUPPORT_HIGHSPEED - { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, - #endif -}; - +extern rusb2_controller_t rusb2_controller[]; #define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) //--------------------------------------------------------------------+ From 04f1a34c39e109002c89e464103ebed6128c2903 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Aug 2023 17:03:07 +0700 Subject: [PATCH 38/40] add rusb2_common.c for dynami irq --- hw/bsp/ra/family.cmake | 1 + hw/bsp/ra/family.mk | 1 + src/portable/renesas/rusb2/dcd_rusb2.c | 5 -- src/portable/renesas/rusb2/hcd_rusb2.c | 6 --- src/portable/renesas/rusb2/rusb2_common.c | 61 +++++++++++++++++++++++ src/portable/renesas/rusb2/rusb2_ra.h | 8 +-- src/portable/renesas/rusb2/rusb2_type.h | 1 + 7 files changed, 65 insertions(+), 18 deletions(-) create mode 100644 src/portable/renesas/rusb2/rusb2_common.c diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 307e01da86..11bc7c6681 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -116,6 +116,7 @@ function(family_configure_example TARGET RTOS) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/rusb2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 9018089587..9afb38e062 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -34,6 +34,7 @@ endif SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ + src/portable/renesas/rusb2/rusb2_common.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 9a3983f56e..3ec1b70b5b 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -50,11 +50,6 @@ #define D0FIFOCTR_b CFIFOCTR_b #endif - // Application API for setting IRQ number - void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { - rusb2_controller[rhport].irqnum = irqnum; - } - #else #error "Unsupported MCU" #endif diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 7f49dc8a97..621320095b 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -34,14 +34,8 @@ #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" - #elif TU_CHECK_MCU(OPT_MCU_RAXXX) #include "rusb2_ra.h" - -// void osal_task_delay(uint32_t msec) { -// R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); -// } - #else #error "Unsupported MCU" #endif diff --git a/src/portable/renesas/rusb2/rusb2_common.c b/src/portable/renesas/rusb2/rusb2_common.c new file mode 100644 index 0000000000..850060777a --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_common.c @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if defined(TUP_USBIP_RUSB2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED) + +#include "rusb2_type.h" + +#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) +#include "rusb2_rx.h" + +#elif TU_CHECK_MCU(OPT_MCU_RAXXX) +#include "rusb2_ra.h" + +// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP +rusb2_controller_t rusb2_controller[] = { + { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, + #ifdef RUSB2_SUPPORT_HIGHSPEED + { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, + #endif +}; + +// Application API for setting IRQ number. May throw warnings for missing prototypes. +void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { + rusb2_controller[rhport].irqnum = irqnum; +} + +// void osal_task_delay(uint32_t msec) { +// R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); +// } + +#else + #error "Unsupported MCU" +#endif + + +#endif diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 7ff272bbc2..259d3cbdb3 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -74,13 +74,7 @@ typedef struct { #define rusb2_is_highspeed_reg(_reg) (false) #endif -// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP -static rusb2_controller_t rusb2_controller[] = { - { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, - #ifdef RUSB2_SUPPORT_HIGHSPEED - { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, - #endif -}; +extern rusb2_controller_t rusb2_controller[]; #define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 005d7f2beb..dd88f66a75 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -28,6 +28,7 @@ #define _TUSB_RUSB2_TYPE_H_ #include +#include #ifdef __cplusplus extern "C" { From 47ae883ba0f02ef268e7e8427f14aaa4fb0c29ce Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Aug 2023 17:26:56 +0700 Subject: [PATCH 39/40] fix build with -flto --- hw/bsp/ra/family.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index e6213061dd..73c64913d4 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -136,7 +136,7 @@ void board_led_write(bool state) { } uint32_t board_button_read(void) { - bsp_io_level_t lvl; + bsp_io_level_t lvl = !BUTTON_STATE_ACTIVE; R_IOPORT_PinRead(&port_ctrl, SW1, &lvl); return lvl == BUTTON_STATE_ACTIVE; } From edee46e7941f56f5024bf60d56921cfe10d1f7a5 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 1 Aug 2023 15:21:31 +0200 Subject: [PATCH 40/40] renesas: host: remove attach_attempt logic --- src/portable/renesas/rusb2/hcd_rusb2.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 621320095b..f6683529a5 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -774,7 +774,6 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { void hcd_int_handler(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - static unsigned char attach_attempt = 0; // TODO remove later unsigned is0 = rusb->INTSTS0; unsigned is1 = rusb->INTSTS1; @@ -789,23 +788,14 @@ void hcd_int_handler(uint8_t rhport) if (is1 & RUSB2_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ rusb->DCPCTR_b.SQSET = 1; - attach_attempt = 0; hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } if (is1 & RUSB2_INTSTS1_SIGN_Msk) { hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); - if(attach_attempt > 0) { - rusb->DVSTCTR0_b.UACT = 1; - _hcd.need_reset = true; - rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; - hcd_event_device_attach(rhport, true); - } - attach_attempt--; } if (is1 & RUSB2_INTSTS1_ATTCH_Msk) { - attach_attempt = 10; rusb->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;