diff --git a/audio/content.asc b/audio/content.asc index fd6d0d4..ea2fc09 100755 --- a/audio/content.asc +++ b/audio/content.asc @@ -88,24 +88,24 @@ Connecting up the headphones ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ On the Papilio One, just plug amplified speakers into the jack and use the following constraint: -[NOTE] -.Constraint for the Papilo One -================================== +[source,ucf] +------------------------------------- +# Constraint for the Papilo One NET "Audio" LOC = "P41"; -================================== +------------------------------------- Connecting headphones to the Basys2 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Unlike the Papilio One + LogicStart MegaWing combo the Basys2 does not have an audio output, so we need to use a PMOD port. The PMODs on the Basys2 board have four signal wires from the FPGA, a ground and a 3.3V power connection. For the JA header on the Basys2 board the constraints are: -[NOTE] -.Contraints for the Basys2 -=============================================== +[source,ucf] +------------------------------------- +# Contraints for the Basys2 NET "JA<0>" LOC = "B2"; NET "JA<1>" LOC = "A3"; NET "JA<2>" LOC = "J3"; NET "JA<3>" LOC = "B5"; -=============================================== +------------------------------------- CAUTION: Make sure that you don't short the power pins. Shorting out ground and power will upset your USB port and/or your FPGA board diff --git a/block-ram/content.asc b/block-ram/content.asc index e9d00aa..6935a5f 100755 --- a/block-ram/content.asc +++ b/block-ram/content.asc @@ -231,7 +231,9 @@ As an aside, there are other ways to do this, allowing you to inject contents (e The finishing touches ~~~~~~~~~~~~~~~~~~~~~ --------------------------------------- +[source,ucf] +-------------------------------------- +# Constraints for Papilio One NET LEDs(7) LOC = "P5" | IOSTANDARD=LVCMOS25; NET LEDs(6) LOC = "P9" | IOSTANDARD=LVCMOS25; NET LEDs(5) LOC = "P10" | IOSTANDARD=LVCMOS25; diff --git a/first-project/content.asc b/first-project/content.asc index daa19ec..8b8f69b 100755 --- a/first-project/content.asc +++ b/first-project/content.asc @@ -161,6 +161,15 @@ Transistor Transistor Logic)" signal levels: NET LED_0 LOC = "P17" | IOSTANDARD=LVTTL; ------------------------------------- +[source,ucf] +------------------------------------- +# Constraints for Papilio Pro +NET switch_1 LOC = "P120" | IOSTANDARD=LVTTL; +NET switch_0 LOC = "P121" | IOSTANDARD=LVTTL; # rightmost Switch +NET LED_1 LOC = "P133" | IOSTANDARD=LVTTL; +NET LED_0 LOC = "P134" | IOSTANDARD=LVTTL; # rightmost LED +------------------------------------- + [source,ucf] ------------------------------------- # Constraints for Basys2 diff --git a/module4/content.asc b/module4/content.asc index 3390370..4241376 100755 --- a/module4/content.asc +++ b/module4/content.asc @@ -80,6 +80,15 @@ NET LEDs(1) LOC = "P16" | IOSTANDARD=LVTTL; NET LEDs(0) LOC = "P17" | IOSTANDARD=LVTTL; -------------------------------------- +[source,ucf] +------------------------------------- +# Constraints for Papilio Pro +NET switches(1) LOC = "P120" | IOSTANDARD=LVTTL; +NET switches(0) LOC = "P121" | IOSTANDARD=LVTTL; # rightmost Switch +NET LEDs(1) LOC = "P133" | IOSTANDARD=LVTTL; +NET LEDs(0) LOC = "P134" | IOSTANDARD=LVTTL; # rightmost LED +------------------------------------- + [source,ucf] ------------------------------------- # Constraints for the Basys2 @@ -119,6 +128,28 @@ NET switches(1) LOC = "P3" | IOSTANDARD=LVTTL; NET switches(0) LOC = "P4" | IOSTANDARD=LVTTL; -------------------------------------- +[source,ucf] +------------------------------------- +# Constraints for Papilio Pro +NET switches(7) LOC = "P114" | IOSTANDARD=LVTTL; +NET switches(6) LOC = "P115" | IOSTANDARD=LVTTL; +NET switches(5) LOC = "P116" | IOSTANDARD=LVTTL; +NET switches(4) LOC = "P117" | IOSTANDARD=LVTTL; +NET switches(3) LOC = "P118" | IOSTANDARD=LVTTL; +NET switches(2) LOC = "P119" | IOSTANDARD=LVTTL; +NET switches(1) LOC = "P120" | IOSTANDARD=LVTTL; +NET switches(0) LOC = "P121" | IOSTANDARD=LVTTL; # rightmost Switch + +NET LEDs(7) LOC = "P123" | IOSTANDARD=LVTTL; +NET LEDs(6) LOC = "P124" | IOSTANDARD=LVTTL; +NET LEDs(5) LOC = "P126" | IOSTANDARD=LVTTL; +NET LEDs(4) LOC = "P127" | IOSTANDARD=LVTTL; +NET LEDs(3) LOC = "P131" | IOSTANDARD=LVTTL; +NET LEDs(2) LOC = "P132" | IOSTANDARD=LVTTL; +NET LEDs(1) LOC = "P133" | IOSTANDARD=LVTTL; +NET LEDs(0) LOC = "P134" | IOSTANDARD=LVTTL; # rightmost LED +-------------------------------------- + [source,ucf] ------------------------------------- # Constraints for the Basys2 diff --git a/module6/content.asc b/module6/content.asc index 0e186b4..6a44ed8 100755 --- a/module6/content.asc +++ b/module6/content.asc @@ -304,6 +304,12 @@ signal to be assigned the correct pin for your FPGA board's "clock" signal. NET "clk" LOC = "P89" | IOSTANDARD = LVCMOS25 ; ------------------------------------- +[source,ucf] +------------------------------------- +# Constraints for Papilio Pro +NET clk LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK +------------------------------------- + [source,ucf] ------------------------------------- # Constraints for the Basys2 diff --git a/vga/content.asc b/vga/content.asc index 04fd4c4..3ce5827 100755 --- a/vga/content.asc +++ b/vga/content.asc @@ -56,10 +56,9 @@ Pins used to drive the VGA connector Ten pins are used to drive the VGA connector - the Red, Green and Blue signals use a passive D2A convertor made out of resistors -[NOTE] -.The constraints for the Papilio board are: -========================================================================= - +[source,ucf] +------------------------------------- +# VGA signal constraints for the Papilio One NET "HSYNC" LOC = "P83" | DRIVE = 2; NET "VSYNC" LOC = "P85" | DRIVE = 2; NET "Red<2>" LOC = "P54" | DRIVE = 2; @@ -70,13 +69,11 @@ Ten pins are used to drive the VGA connector - the Red, Green and Blue signals u NET "Green<0>" LOC = "P68" | DRIVE = 2; NET "Blue<2>" LOC = "P71" | DRIVE = 2; NET "Blue<1>" LOC = "P78" | DRIVE = 2; +------------------------------------- -========================================================================= - -[NOTE] -.The constraints for the Basys2 board are: -======================================================================== - +[source,ucf] +------------------------------------- +# VGA signal constraints for the Basys2 board NET "HSYNC" LOC = "J14" | DRIVE = 2; NET "VSYNC" LOC = "K13" | DRIVE = 2; NET "Red<2>" LOC = "F13" | DRIVE = 2; @@ -87,13 +84,14 @@ Ten pins are used to drive the VGA connector - the Red, Green and Blue signals u NET "Green<0>" LOC = "F14" | DRIVE = 2; NET "Blue<2>" LOC = "J13" | DRIVE = 2; NET "Blue<1>" LOC = "H13" | DRIVE = 2; - -======================================================================== +------------------------------------- Making the timings easy to implement -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + If you multiply the hsync and vsync timings by the pixel clock you will get something close to the following numbers: +.Horizontal timing |================= | Scanline (Horizontal) timing | Duration in pixel clocks | Visible area | 640 @@ -104,6 +102,7 @@ If you multiply the hsync and vsync timings by the pixel clock you will get some |================= The horizontal blanking interval is the front porch + sync pulse + back porch = 160 pixel clocks +.Vertical timing |================= | Frame (vertical) timing | Duration in lines (800 pixel clocks) | Visible area | 480