Raspberry Pi 5 model B #21
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Note: Most benchmarks were run with 16k page size; Geekbench 6 would not work with 16k so I rebooted on 4k page size kernel8. See video: Rasbperry Pi 5: EVERYTHING you need to know And blog post: Testing PCIe on the Raspberry Pi 5 |
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sbc-bench results: ThomasKaiser/sbc-bench#77 |
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Can you please post output from |
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Note that the above |
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The new UART header is presumably to make it easier to attach the Pi Debug Probe. Do we get GPIO 14/15 as a second UART, then? Can we use the UART header for something other than the serial console? |
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Thank you. I'm just trying to figure out how the whole PCIe setup looks like... Does the 'external' PCIe lane originate from the SoC or from RP1? When you force PCIe to Gen3 does this affect only the external 'slot' or also interconnection with RP1? Which USB controller is inside the thing? The NIC has the RPi vendor ID ( |
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They got their own PCIe Vender ID! : D |
@rgov you still get the separate UART via RP1 on GPIO 14/15, that one is configured as always via config.txt — the UART header is direct into the BCM2711 SoC.
@ThomasKaiser ext PCIe from SoC (so when you set
With a 1TB SSD (SanDisk Extreme) attached: Not sure what magic they're pulling, it all seems to route through RP1 on those x4 lanes. |
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Thanks for the idle power value: important for running off-grid, though still higher than my current 3B at about 1W... https://www.earth.org.uk/note-on-Raspberry-Pi-3-setup.html And a short note from me on the RPi5 power: http://www.earth.org.uk/note-on-site-technicals-76.html#2023-09-28 |
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https://gist.github.com/cleverca22/97e46998b5fbd4e2f6772127c0cd034a |
Thanks for this. So in the RP1 Ethernet is Cadence MACB/GEM IP and USB the usual Synopsys DesignWare 3 stuff while the SoC itself also seems to contain a RGMII capable GMAC (if RPi Trading Ltd. comes up with a new CM5 pinout they could maybe use this other Gigabit Ethernet as well) |
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ah, good catch, i missed that |
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Looks like it is still limited to USB OTG 2.0 like the Pi4 [1]. I need a SBC with USB OTG 3.0 for a fast piSCSI USB Drive. |
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@geerlingguy have you tried to power the RPi 5 with something else than their new 5V/5A power brick? Curious whether it supports higher profiles with supply voltages exceeding 5V or whether this limitation is a hard one? Also curious whether Also curious whether USB-C details show up when doing something like And in general providing |
Graph at 9:25 looks suspect: you appear to be using a cumulative plot. So for example the blue "108.9" point is actually at y position 108.9+54.9=163.8. Screenshot: https://sphere.chronosempire.org.uk/~HEx/shots/latency.png Here's what I'd expect it to look like: https://sphere.chronosempire.org.uk/~HEx/pi5.svg Code: |
ROCK 5A and ROCK 5B both has USB OTG 3.0, ROCK 5B OTG is at USB C. ROCK 5A OTG is at the upper double layer USB 3.0. Please check the Tech Spec section: https://radxa.com/rock5a/ |
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Now lets just hope there is plenty of supply! |
@hexwab - Oh my! You're correct. Chalk that up to 'was up too late benchmarking' :O I'm updating the graph and wording in my blog post. |
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@ThomasKaiser - Full Click to show full `dmesg` output |
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Following up on https://mast.hpc.social/deck/@[email protected]/111143860188995259 2 questions:
GPU/Multimedia ASIC: What formats/profile does the HEVC decoder support? is it 8bit 420 only? does it implement 10bit (required for "proper" HDR)? |
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Hello, can you test glmark2 and glmark2-es2 score and do a simple comparison between rpi4b? |
Cheers. While I'm nitpicking: have you considered SVG graphs (rather than JPEG of all things)? |
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@geerlingguy, do you plan to focus more on "tweaking" in order to achieve the lowest possible idle power consumption? (like disabling hdmi, wifi, bluetooth, undervolting, …) //edit: I like how they did indicator of memory version (8G, 4G, 2G, 1G) it's like |
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I would certainly like to know that set of tweaks for my application... B^> |
Gotcha, so looks like we get |
BTW: sbc-bench output collected by Jeff shows Also accessible via |
@Headcrabed - mentioned in my video (linked earlier), GLMark2 scores:
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Threadx is now open source https://www.theregister.com/AMP/2023/11/28/microsoft_opens_sources_threadx/ Hopefully raspberry pi LTD follows suit and open sources their implementation so we can have a truly open bootstack. |
there is no rationale for such conclusion discussed also here https://forums.raspberrypi.com/viewtopic.php?t=360475 |
Haven't read the forum but its not Raspberry the Video-Core loader is prop of Broadcom and likely fat chance. |
I've read the forum and issues linked there. It seems that upstream threadx being open source now places the only barrier on raspberry pi open sourcing their implementation on broadcom, rather than broadcom and microsoft (who wholly own Express Logic Inc). Lets hope broadcom rebases their version on upstream MIT licensed threadx and decides to release their changes under a compatible license. As you can see from the blog post from eclipse https://eclipse-foundation.blog/2023/11/21/introducing-eclipse-threadx/ they do want a future when all efforts are merged upstream. |
Again, there is no reason for this. If Microsoft opensources Windows will Adobe make Photoshop opensource (because it runs on top of Windows)? |
clearly you are not a software developer and do not understand this relationship. Your analogy is extremely misguided. adobe photoshop is not based on Windows and is not an implementation of Windows which your analogy would imply. the bootloader that runs on the broadcom GPU is an implementation based on ThreadX with Broadcom proprietary patches applied on top. They are not separate software such as Windows and Photoshop. Now that the base ThreadX has an MIT licensed version, assuming rpi/broadcom rebase their changes ontop of the upstream MIT licensed ThreadX, the only blocker is rpi/broadcom's own code. Previously, in order to release their the pi bootloader as FOSS, they would have to obtain permission from Microsoft (which they would never give). That is no longer the case. |
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No, ThreadX is an OS and the firmware of the Rpi boards is an *application*
that runs on ThreadX. fanoush was precisely correct in their analogy.
There's no reason to expect that the application will eve be open sourced.
…On Wed, Nov 29, 2023 at 9:20 AM theofficialgman ***@***.***> wrote:
and decides to release their changes under a compatible license.
Again, there is no reason for this. If Microsoft opensources Windows will
Adobe make Photoshop opensource?
clearly you are not a software developer and do not understand this
relationship. Your analogy is extremely misguided. adobe photoshop is not
based on Windows and is not an implementation of Windows which your analogy
would imply.
the bootloader that runs on the broadcom GPU is an implementation based on
ThreadX with Broadcom proprietary patches applied on top. They are not
separate software such as Windows and Photoshop. Now that the base ThreadX
has an MIT licensed version, assuming rpi/broadcom rebase their changes
ontop of the upstream MIT licensed ThreadX, the only blocker is
rpi/broadcom's own code. Previously in order to release their the pi
bootloader as FOSS they would have to obtain permission from Microsoft
(which they would never give). That is no longer the case.
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incorrect. the stage 2 bootloader is the threadx OS with broadcom patches applied on top and is not simply an application that runs on an unmodified threadx OS. As you can see from the official supported architectures of threadx https://github.com/azure-rtos/threadx/#supported-architecture-ports , the broadcom gpu architectures are not official supported architectures. Thus, broadcom's patches involve at least partially, changes necessary to threadX OS itself to run on their gpu architectures. Of course broadcom has developed applications that run ontop of the threadx OS and those have always been wholly owned by rpi/broadcom. |
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@theofficialgman Any news from upstream maintainer about that schci patch? |
Not really sure how decisions for the future affect decisions being made prior to even BroadCom having bought Alphamosaic: https://forums.raspberrypi.com/viewtopic.php?p=1460642#p1460642 And we should always remember: Raspberry Pi Ltd. is a catch basin for VideoCore guys. When Eben Upton (CEO), Gordon Hollingworth (CTO software) and James Adams (CTO hardware) talk in an interview about what 'we did together in the past' then mostly they refer to a situation where they were Broadcom employees (all three for example members of the VC4 design team and Adams even becoming BroadCom employee by acquisition of his former employer and VideoCore inventor Alphamosaic). |
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@Headcrabed Maybe it's a good idea to try to send something on that linux-mmc mailing list? That email is [email protected], maybe Adrian will respond there. |
MD Raid10 on two SDXC Cards 128GB Samsung Pro Plus w/USB Adapter or (one of them) in SD cardslotRPI5B w/4 GiB RAM One card moved to internal SD slot: benchmarkresult_sdcardreader.txt These tests show that we can mirror the SD card with a second card via USB adapter - so we get better availability without losing performance. In my application, I mirror the bootfs partition as well (using RAID 1 w/v0.90 metadata), so both cards are interchangeable and can freely be moved betwenn USB adapter and SD cardslot, and the system always remains bootable as long as at least one of the cards is operational. |
MD Raid10 on two Samsung Portable SSD T7 1TBRPI5B w/4GB RAM |
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Going to close up the previous discussion as it's a support-related question and not particularly related to the test data for this board. |
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@theofficialgman We could improve sd card performance by enabling sd cqe support: https://forums.raspberrypi.com/viewtopic.php?t=367459 |
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After testing the NUMA Emulation patch (and finding the performance impact is... mixed at best?), I also want to do some testing with A2 cards (as mentioned in the link in the comment above), so I'll enable the queuing and run some tests on my SanDisk Extreme 256GB A2 card. |
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Using the following benchmark with a 256 GB SanDisk Extreme A2 microSD card: To enable command queueing, I placed BeforeAfter
Also, running with BeforeAfter |
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GREAT benchmark, thank you Jeff - did not know of iozone. Going to test
SD, eMMC and NVMe on the Banana Pi BPi-F3 too now!
I should submit more SBC specs/tests at some point, but I've been pretty
lazy sorry. Ones I've recently tested, or have here to test;
Debix Model C
Milk-V Meles
Radxa CM5 Lite
BPi-F3
Radxa Fogwise
Luckfox Pico Max
Luckfox Pico Ultra
If any you'd like sooner or have use for, just let me know.
Cheers
…------ Original Message ------
From "Jeff Geerling" ***@***.***>
To "geerlingguy/sbc-reviews" ***@***.***>
Cc "Platima" ***@***.***>; "Comment"
***@***.***>
Date 8/07/2024 06:37:49
Subject Re: [geerlingguy/sbc-reviews] Raspberry Pi 5 model B (Issue #21)
Using the following benchmark:
wget https://raw.githubusercontent.com/geerlingguy/pi-cluster/master/benchmarks/disk-benchmark.sh
chmod +x disk-benchmark.sh
sudo MOUNT_PATH=/ TEST_SIZE=1g ./disk-benchmark.sh
To enable command queueing, I placed dtparam=sd_cqe inside
/boot/firmware/config.txt and rebooted.
Before
***@***.***:~ $ dmesg | grep mmc0
[ 2.546753] mmc0: SDHCI controller on 1000fff000.mmc [1000fff000.mmc] using ADMA 64-bit
[ 2.652792] mmc0: new ultra high speed SDR104 SDXC card at address aaaa
[ 2.659679] mmcblk0: mmc0:aaaa SN256 238 GiB
[ 2.668229] mmcblk0: mmc0:aaaa SN256 238 GiB (quirks 0x00004000)
TODO PASTE BENCHMARK RESULT
After
***@***.***:~ $ dmesg | grep mmc0
TODO PASTE RESULT
TODO PASTE BENCHMARK RESULT
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Late to the game as I just saw that the Pi 5 supports Command Queueing. I only had two A2 cards laying around. Samsung Evo 128gb A2, doesn't seem to be supported, no mmc0: Command Queue Engine enabled, 31 tags after adding dtparam=sd_cqe and no difference in speed before and after. SanDisk Extreme 64gb A2, this card worked before Run 1 After |
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Raspberry Pi is working on some Pi SDRAM timing adjustments, which benefit both the Pi 5 and Pi 4. I've been re-testing things like Geekbench (see linked blog post for those results), showing an 8-20% speedup depending on the specific benchmark. HPL also benefits, and here are Strange seeing it go from 13 GB/sec to 9 GB/sec for memset... Edit: re-testing just editing So something definitely slows down the writes at least for synthetic memory benchmarks. I think someone in the Pi forum thread mentioned the same:
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With the new tweaks hitting apt, I'm going to re-run some of the benchmarks (especially HPL) to see how efficiency is improved for multicore tests. |
and others
Basic information
Linux/system information
Benchmark results
CPU
Power
stress-ng --matrix 0): 9.7 Wtop500HPL benchmark: 11 W (2.75 Gflops/W)Disk
SanDisk Extreme 128GB microSD
Kioxia XG8 1TB NVMe at PCIe Gen 2
Kioxia XG8 1TB NVMe at PCIe Gen 3
Single SanDisk Extreme PRO USB 3.1 Flash Drive
2x SanDisk Extreme PRO USB 3.1 Flash Drives (simultaneous)
Run benchmark on any attached storage device (e.g. eMMC, microSD, NVMe, SATA) and add results under an additional heading. Download the script with
curl -o disk-benchmark.sh [URL_HERE]and runsudo DEVICE_UNDER_TEST=/dev/sda DEVICE_MOUNT_PATH=/mnt/sda1 ./disk-benchmark.sh(assuming the device issda).Network
Built-in Ethernet
iperf3 -c $SERVER_IP: 938 Mbpsiperf3 --reverse -c $SERVER_IP: 942 Mbpsiperf3 --bidir -c $SERVER_IP: 930 Mbps up, 600 Mbps downBuilt-in WiFi
iperf3 -c $SERVER_IP: 186 Mbpsiperf3 --reverse -c $SERVER_IP: 207 Mbpsiperf3 --bidir -c $SERVER_IP: 2.15 Mbps up, 206 Mbps downUSB 3.0 Pluggable USBC-E2500 2.5 Gbps Adapter
iperf3 -c $SERVER_IP: 1.55 Gbpsiperf3 --reverse -c $SERVER_IP: 300 Mbpsiperf3 --bidir -c $SERVER_IP: 1.56 Gbps up, 153 Mbps downASUS XG-C100C 10G Network Adapter (Aquantia AQC107)
iperf3 -c $SERVER_IP: 5.63 Gbpsiperf3 --reverse -c $SERVER_IP: 6.05 Gbpsiperf3 --bidir -c $SERVER_IP: 4.40 Gbps up, 2.50 Gbps downGPU
Compatibility reports:
Memory
tinymembenchresults:Click to expand memory benchmark result
Phoronix Test Suite
Results from pi-general-benchmark.sh:
Other Data
Crypto performance as measured by OpenSSL (see sbc-bench ARMv8 Crypto Extensions):
PTP Hardware Timestamping support via Cadence GEM:
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