AD1939 bugs

[tvannoy]

During testing of the programmable FIR filter, we've found a couple bugs in the AD1939 component

• maxChannel was set to 0 in the tcl script, which caused any incoming channel greater than 0 to not be valid; this was causing the valid signal to never go high for the right channel.
• left and right DAC channels get swapped in the VHDL code

[tvannoy]

It turns out the left and right DAC channels being swapped is more involved than just switching a few signals.

Right now, the left channel gets loaded in when lrclk = 1, even though the channel should be active when lrclk = 0. Vice versa for the right channel. The data from the parallel to serial converts gets shifted out after the load signal is dessarted. Changing the polarity of the load signals in the parallel to serial converters results in no audio output. It might be the case that the polarity of these signals should be inverted as it is right now, however the audio channels are currently being swapped in the output.

In simulation, the data that arrives while lrclk = 0 gets put onto the avalon bus when channel = 1. This might be the true source of the problem, rather than the inverted polarity of the parallel to serial converters. If that's the case, this suggests that something is off in the timing of the state machines that capture the incoming data.