final adoc to edn batch (riscv#1587)

src/c-st-ext.adoc

@@ -409,7 +409,7 @@ attain the greatest code size reduction.
 ==== Register-Based Loads and Stores
 
 [[reg-based-ldnstr]]
-include::images/wavedrom/reg-based-ldnstr.adoc[]
+include::images/wavedrom/reg-based-ldnstr.edn[]
 //.Compressed, register-based load and stores--these instructions use the CL format.
 (((compressed, register-based load and store)))
 These instructions use the CL format.

src/f-st-ext.adoc

@@ -231,7 +231,7 @@ signals.
 
 Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register _rs1_ and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register _rd_. FSW stores a single-precision value from floating-point register _rs2_ to memory.
 
-include::images/wavedrom/sp-load-store-2.adoc[]
+include::images/wavedrom/sp-load-store-2.edn[]
 [[sp-ldst]]
 //.SP load and store
 
@@ -283,7 +283,7 @@ minimumNumber and maximumNumber operations, rather than the IEEE
 handling of signaling NaNs.
 ====
 
-include::images/wavedrom/spfloat.adoc[]
+include::images/wavedrom/spfloat.edn[]
 [[spfloat]]
 //.Single-Precision Floating-Point Computational Instructions
 (((floating point, fused multiply-add)))
@@ -315,7 +315,7 @@ RISC-V FNMSUB and FNMADD instruction names are swapped compared to x86
 and ARM.
 ====
 
-include::images/wavedrom/spfloat2.adoc[]
+include::images/wavedrom/spfloat2.edn[]
 [[fnmaddsub]]
 //.F[N]MADD/F[N]MSUB instructions
 
@@ -389,7 +389,7 @@ All floating-point conversion instructions set the Inexact exception
 flag if the rounded result differs from the operand value and the
 Invalid exception flag is not set.
 
-include::images/wavedrom/spfloat-cn-cmp.adoc[]
+include::images/wavedrom/spfloat-cn-cmp.edn[]
 [[fcvt]]
 //.SP float convert and move
 
@@ -405,7 +405,7 @@ FSGNJN.S _rx, ry, ry_ moves the negation of _ry_ to _rx_ (assembler
 pseudoinstruction FNEG.S _rx, ry_); and FSGNJX.S _rx, ry, ry_ moves the absolute value of _ry_ to _rx_ (assembler pseudoinstruction FABS.S _rx,
 ry_).
 
-include::images/wavedrom/spfloat-sign-inj.adoc[]
+include::images/wavedrom/spfloat-sign-inj.edn[]
 [[inj]]
 
 [NOTE]
@@ -428,7 +428,7 @@ preserved.
 The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.
 ====
 
-include::images/wavedrom/spfloat-mv.adoc[]
+include::images/wavedrom/spfloat-mv.edn[]
 [[spfloat-mv]]
 //.SP floating point move
 
@@ -454,7 +454,7 @@ _signaling_ comparisons: that is, they set the invalid operation
 exception flag if either input is NaN. FEQ.S performs a _quiet_
 comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN.
 
-include::images/wavedrom/spfloat-comp.adoc[]
+include::images/wavedrom/spfloat-comp.edn[]
 [[spfloat-comp]]
 //.SP floating point compare
 
@@ -478,7 +478,7 @@ _rd_ are cleared. Note that exactly one bit in _rd_ will be set.
 FCLASS.S does not set the floating-point exception flags.
 (((floating-point, classification)))
 
-include::images/wavedrom/spfloat-classify.adoc[]
+include::images/wavedrom/spfloat-classify.edn[]
 [[spfloat-classify]]
 //.SP floating point classify
 

src/machine.adoc

@@ -2388,7 +2388,7 @@ not increment the `minstret` CSR.
 Instructions to return from trap are encoded under the PRIV minor
 opcode.
 
-include::images/wavedrom/trap-return.adoc[]
+include::images/wavedrom/trap-return.edn[]
 
 To return after handling a trap, there are separate trap return
 instructions per privilege level, MRET and SRET. MRET is always
@@ -2425,7 +2425,7 @@ privileged modes, and optionally available to U-mode. This instruction
 may raise an illegal-instruction exception when TW=1 in `mstatus`, as
 described in <<virt-control>>.
 
-include::images/wavedrom/wfi.adoc[]
+include::images/wavedrom/wfi.edn[]
 
 If an enabled interrupt is present or later becomes present while the
 hart is stalled, the interrupt trap will be taken on the following

src/q-st-ext.adoc

@@ -17,7 +17,7 @@ value.
 New 128-bit variants of LOAD-FP and STORE-FP instructions are added,
 encoded with a new value for the funct3 width field.
 
-include::images/wavedrom/quad-ls.adoc[]
+include::images/wavedrom/quad-ls.edn[]
 [[quad-ls]]
 //.Quad-precision load and store
 
@@ -47,7 +47,7 @@ The quad-precision floating-point computational instructions are defined
 analogously to their double-precision counterparts, but operate on
 quad-precision operands and produce quad-precision results.
 
-include::images/wavedrom/quad-compute.adoc[]
+include::images/wavedrom/quad-compute.edn[]
 [[quad-compute]]
 //.Quad-precision computational
 
@@ -64,7 +64,7 @@ FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or
 from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only
 instructions. Note FCVT.Q.L[U] always produces an exact result and is unaffected by rounding mode.
 
-include::images/wavedrom/quad-cnvrt-mv.adoc[]
+include::images/wavedrom/quad-cnvrt-mv.edn[]
 [[quad-cnvrt-mv]]
 //.Quad-precision convert and move
 
@@ -76,15 +76,15 @@ single-precision floating-point number, or vice-versa, respectively.
 FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to
 a double-precision floating-point number, or vice-versa, respectively.
 
-include::images/wavedrom/quad-cnvt-interchange.adoc[]
+include::images/wavedrom/quad-cnvt-interchange.edn[]
 [[quad-convrt-interchange]]
 //.Quad-precision convert and move interchangeably
 
 Floating-point to floating-point sign-injection instructions, FSGNJ.Q,
 FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision
 sign-injection instruction.
 
-include::images/wavedrom/quad-cnvrt-intch-xqqx.adoc[]
+include::images/wavedrom/quad-cnvrt-intch-xqqx.edn[]
 [[quad-cnvrt-intch-xqqx]]
 //.Quad-precision convert and move interchangeably XQ-QX
 
@@ -103,7 +103,7 @@ The quad-precision floating-point compare instructions are defined
 analogously to their double-precision counterparts, but operate on
 quad-precision operands.
 
-include::images/wavedrom/quad-float-compare.adoc[]
+include::images/wavedrom/quad-float-compare.edn[]
 [[quad-float-compare]]
 //.Quad-precision floatinf-point compare
 
@@ -113,7 +113,7 @@ The quad-precision floating-point classify instruction, FCLASS.Q, is
 defined analogously to its double-precision counterpart, but operates on
 quad-precision operands.
 
-include::images/wavedrom/quad-float-clssfy.adoc[]
+include::images/wavedrom/quad-float-clssfy.edn[]
 [[quad-float-clssfy]]
 //.Quad-precision floating point classify
 

src/rv64.adoc

@@ -39,7 +39,7 @@ ensure reasonable performance for 32-bit values.
 
 ==== Integer Register-Immediate Instructions
 
-include::images/wavedrom/rv64i-base-int.adoc[]
+include::images/wavedrom/rv64i-base-int.edn[]
 [[rv64i-base-int]]
 //.RV64I register-immediate instructions
 
@@ -50,7 +50,7 @@ immediate to register _rs1_ and produces the proper sign extension of a
 writes the sign extension of the lower 32 bits of register _rs1_ into
 register _rd_ (assembler pseudoinstruction SEXT.W).
 
-include::images/wavedrom/rv64i-slli.adoc[]
+include::images/wavedrom/rv64i-slli.edn[]
 [[rv64i-slli]]
 //.RV64I register-immediate (descr ADDIW) instructions
 
@@ -67,7 +67,7 @@ copied into the vacated upper bits).
 (((RV64I, SRLIW)))
 (((RV64I, RV64I-only)))
 
-include::images/wavedrom/rv64i-slliw.adoc[]
+include::images/wavedrom/rv64i-slliw.edn[]
 [[rv64i-slliw]]
 
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously
@@ -82,7 +82,7 @@ were defined to cause illegal-instruction exceptions, whereas now they
 are marked as reserved. This is a backwards-compatible change.
 ====
 
-include::images/wavedrom/rv64_lui-auipc.adoc[]
+include::images/wavedrom/rv64-lui-auipc.edn[]
 [[rv64_lui-auipc]]
 //.RV64I register-immediate (descr) instructions
 
@@ -108,7 +108,7 @@ with LD, AUIPC with JALR, etc. in RV64I is
 ==== Integer Register-Register Operations
 
 //this diagramdoesn't match the tex specification
-include::images/wavedrom/rv64i_int-reg-reg.adoc[]
+include::images/wavedrom/rv64i-int-reg-reg.edn[]
 [[int_reg-reg]]
 //.RV64I integer register-register instructions
 

src/v-st-ext.adoc

@@ -156,7 +156,7 @@ The `vtype` register has five fields, `vill`, `vma`, `vta`,
 `vsew[2:0]`, and `vlmul[2:0]`.  Bits `vtype[XLEN-2:8]` should be
 written with zero, and non-zero values in this field are reserved.
 
-include::images/wavedrom/vtype-format.adoc[]
+include::images/wavedrom/vtype-format.edn[]
 
 NOTE: A small implementation supporting ELEN=32 requires only seven
 bits of state in `vtype`: two bits for `ma` and `ta`, two bits for
@@ -878,11 +878,11 @@ floating-point load/store 12-bit immediate field to provide further
 vector instruction encoding, with bit 25 holding the standard vector
 mask bit (see <<sec-vector-mask-encoding>>).
 
-include::images/wavedrom/vmem-format.adoc[]
+include::images/wavedrom/vmem-format.edn[]
 
-include::images/wavedrom/valu-format.adoc[]
+include::images/wavedrom/valu-format.edn[]
 
-include::images/wavedrom/vcfg-format.adoc[]
+include::images/wavedrom/vcfg-format.edn[]
 
 Vector instructions can have scalar or vector source operands and
 produce scalar or vector results, and most vector instructions can be
@@ -1143,11 +1143,11 @@ their arguments, and write the new value of `vl` into `rd`.
  vsetvl  rd, rs1, rs2      # rd = new vl, rs1 = AVL, rs2 = new vtype value
 ----
 
-include::images/wavedrom/vcfg-format.adoc[]
+include::images/wavedrom/vcfg-format.edn[]
 
 ==== `vtype` encoding
 
-include::images/wavedrom/vtype-format.adoc[]
+include::images/wavedrom/vtype-format.edn[]
 
 The new `vtype` value is encoded in the immediate fields of `vsetvli`
 and `vsetivli`, and in the `rs2` register for `vsetvl`.
@@ -1345,7 +1345,7 @@ floating-point load/store 12-bit immediate field to provide further
 vector instruction encoding, with bit 25 holding the standard vector
 mask bit (see <<sec-vector-mask-encoding>>).
 
-include::images/wavedrom/vmem-format.adoc[]
+include::images/wavedrom/vmem-format.edn[]
 
 [cols="4,12"]
 |===
@@ -2171,7 +2171,7 @@ The vector arithmetic instructions use a new major opcode (OP-V =
 1010111~2~) which neighbors OP-FP.  The three-bit `funct3` field is
 used to define sub-categories of vector instructions.
 
-include::images/wavedrom/valu-format.adoc[]
+include::images/wavedrom/valu-format.edn[]
 
 [[sec-arithmetic-encoding]]
 ==== Vector Arithmetic Instruction encoding
@@ -3459,7 +3459,7 @@ The following table gives the seven MSBs of the output significand as a
 function of the LSB of the normalized input exponent and the six MSBs of the
 normalized input significand; the other bits of the output significand are zero.
 
-include::images/wavedrom/vfrsqrt7.adoc[]
+include::images/wavedrom/vfrsqrt7.edn[]
 
 NOTE: For example, when SEW=32, vfrsqrt7(0x00718abc ({approx} 1.043e-38)) = 0x5f080000 ({approx} 9.800e18), and vfrsqrt7(0x7f765432 ({approx} 3.274e38)) = 0x1f820000 ({approx} 5.506e-20).
 
@@ -3546,7 +3546,7 @@ The following table gives the seven MSBs of the normalized output significand
 as a function of the seven MSBs of the normalized input significand; the other
 bits of the normalized output significand are zero.
 
-include::images/wavedrom/vfrec7.adoc[]
+include::images/wavedrom/vfrec7.edn[]
 
 If the normalized output exponent is 0 or -1, the result is subnormal: the
 output exponent is 0, and the output significand is given by concatenating
@@ -5322,5 +5322,5 @@ the mask element group is set).
 
 === Vector Instruction Listing
 
-include::images/wavedrom/v-inst-table.adoc[]
+include::images/wavedrom/v-inst-table.edn[]
 

src/zfh.adoc

@@ -27,7 +27,7 @@ halflatexmath:[$+$]singlelatexmath:[$\rightarrow$]half.
 New 16-bit variants of LOAD-FP and STORE-FP instructions are added,
 encoded with a new value for the funct3 width field.
 
-include::images/wavedrom/sp-load-store.adoc[]
+include::images/wavedrom/sp-load-store.edn[]
 [[sp-load-store]]
 //.Half-precision load and store instructions
 
@@ -58,9 +58,9 @@ The half-precision floating-point computational instructions are defined
 analogously to their single-precision counterparts, but operate on
 half-precision operands and produce half-precision results.
 
-include::images/wavedrom/spfloat-zfh.adoc[]
+include::images/wavedrom/spfloat-zfh.edn[]
 
-include::images/wavedrom/spfloat2-zfh.adoc[]
+include::images/wavedrom/spfloat2-zfh.edn[]
 
 === Half-Precision Conversion and Move Instructions
 

src/zifencei.adoc

@@ -61,7 +61,7 @@ given address specified in _rs1_, and/or allowing software to use an ABI
 that relies on machine-mode cache-maintenance operations.
 ====
 
-include::images/wavedrom/zifencei-ff.adoc[]
+include::images/wavedrom/zifencei-ff.edn[]
 [[zifencei-ff]]
 //.FENCE.I instruction
 (((FENCE.I, synchronization)))

src/zihintpause.adoc

@@ -40,7 +40,7 @@ performance.
 PAUSE is encoded as a FENCE instruction with _pred_=`W`, _succ_=`0`, _fm_=`0`,
 _rd_=`x0`, and _rs1_=`x0`.
 
-//include::images/wavedrom/zihintpause-hint.adoc[]
+//include::images/wavedrom/zihintpause-hint.edn[]
 //[zihintpause-hint]
 //.Zihintpause fence instructions