diff --git a/hw/arc/arc_sim.c b/hw/arc/arc_sim.c
index 03d27df519c..134ac5071d1 100644
--- a/hw/arc/arc_sim.c
+++ b/hw/arc/arc_sim.c
@@ -103,7 +103,7 @@ static void arc_sim_init(MachineState *machine)
                            1024);
     memory_region_add_subregion(get_system_memory(), 0xf0000000, system_io);
 
-    if (semihosting_enabled()) {
+    if (semihosting_enabled(false)) {
         if (serial_hd(0)) {
             arc_sim_open_console(serial_hd(0));
         }
diff --git a/hw/arc/virt.c b/hw/arc/virt.c
index 73661d1602a..5b6d5dcf0f0 100644
--- a/hw/arc/virt.c
+++ b/hw/arc/virt.c
@@ -14,6 +14,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/error-report.h"
 #include "qemu/units.h"
 #include "qapi/error.h"
 #include "boot.h"
diff --git a/target/arc/arc-semi.c b/target/arc/arc-semi.c
index 9f932c9367a..e10130e645e 100644
--- a/target/arc/arc-semi.c
+++ b/target/arc/arc-semi.c
@@ -852,9 +852,9 @@ void do_arc_semihosting(CPUARCState *env)
 
     case TARGET_SYS_gettimeofday:
     {
-        qemu_timeval tv;
+        struct timeval tv;
         struct timeval p;
-        uint32_t result = qemu_gettimeofday(&tv);
+        uint32_t result = gettimeofday(&tv, NULL);
         arc_semihosting_errno = errno;
         target_ulong base = regs[0];
         uint32_t sz = sizeof (struct timeval);
diff --git a/target/arc/cpu.c b/target/arc/cpu.c
index a95fec0e0b3..49a0e09dd3e 100644
--- a/target/arc/cpu.c
+++ b/target/arc/cpu.c
@@ -99,6 +99,16 @@ static void arc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb
     env->pc = tb->pc;
 }
 
+static void arc_restore_state_to_opc(CPUState *cs,
+                                     const TranslationBlock *tb,
+                                     const uint64_t *data)
+{
+    ARCCPU *cpu = ARC_CPU(cs);
+    CPUARCState *env = &cpu->env;
+
+    env->pc = data[0];
+}
+
 static void arc_cpu_reset(DeviceState *dev)
 {
     CPUState *s = CPU(dev);
@@ -397,6 +407,7 @@ static const struct SysemuCPUOps arc_sysemu_ops = {
 static struct TCGCPUOps arc_tcg_ops = {
     .initialize = arc_translate_init,
     .synchronize_from_tb = arc_cpu_synchronize_from_tb,
+    .restore_state_to_opc = arc_restore_state_to_opc,
 
 #ifdef CONFIG_USER_ONLY
     .record_sigsegv = arc_cpu_record_sigsegv,
diff --git a/target/arc/cpu.h b/target/arc/cpu.h
index 3876a9c03c2..fc0f271ce62 100644
--- a/target/arc/cpu.h
+++ b/target/arc/cpu.h
@@ -184,7 +184,7 @@ FIELD(STATUS32, Zf,  11, 1)
     tcg_temp_free(temp); \
 }
 #define TCG_SET_STATUS_FIELD_IVALUE(STAT_REG, FIELD, IVALUE) { \
-    TCGv temp = tcg_const_tl((IVALUE << R_STATUS32_ ## FIELD ## _SHIFT) \
+    TCGv temp = tcg_constant_tl((IVALUE << R_STATUS32_ ## FIELD ## _SHIFT) \
                              & R_STATUS32_ ## FIELD ## _MASK); \
     tcg_gen_andi_tl(STAT_REG, STAT_REG, ~R_STATUS32_ ## FIELD ## _MASK); \
     tcg_gen_or_tl(STAT_REG, STAT_REG, temp); \
@@ -408,8 +408,8 @@ static inline int cpu_mmu_index(const CPUARCState *env, bool ifetch)
     return GET_STATUS_BIT(env->stat, Uf) != 0 ? 1 : 0;
 }
 
-static inline void cpu_get_tb_cpu_state(CPUARCState *env, target_ulong *pc,
-                                        target_ulong *cs_base,
+static inline void cpu_get_tb_cpu_state(CPUARCState *env, vaddr *pc,
+                                        uint64_t *cs_base,
                                         uint32_t *pflags)
 {
     *pc = env->pc;
diff --git a/target/arc/decoder-v2.c b/target/arc/decoder-v2.c
index b3c155e5161..f7a5efc8e2e 100644
--- a/target/arc/decoder-v2.c
+++ b/target/arc/decoder-v2.c
@@ -447,7 +447,7 @@ static const char *get_auxreg_v2(const struct arc_opcode *opcode,
             continue;
         }
 
-        if (auxr->subclass != NONE) {
+        if (auxr->subclass != ARC_INSN_SUBCLASS_NONE) {
             return NULL;
         }
 
diff --git a/target/arc/decoder-v3.c b/target/arc/decoder-v3.c
index 2e3f5618322..b808d29cd71 100644
--- a/target/arc/decoder-v3.c
+++ b/target/arc/decoder-v3.c
@@ -473,7 +473,7 @@ static const char *get_auxreg_v3(const struct arc_opcode *opcode,
             continue;
         }
 
-        if (auxr->subclass != NONE) {
+        if (auxr->subclass != ARC_INSN_SUBCLASS_NONE) {
             return NULL;
         }
 
diff --git a/target/arc/decoder.h b/target/arc/decoder.h
index f6e2d3f31be..edc80130bab 100644
--- a/target/arc/decoder.h
+++ b/target/arc/decoder.h
@@ -156,7 +156,7 @@ typedef enum {
 
 /* Instruction Subclass.  */
 typedef enum {
-    NONE     = 0,
+    ARC_INSN_SUBCLASS_NONE     = 0,
     CVT      = (1U << 1),
     BTSCN    = (1U << 2),
     CD       = (1U << 3),
diff --git a/target/arc/decoder_fragments/arc-tbl.h b/target/arc/decoder_fragments/arc-tbl.h
index 84d30f2270b..f636555a76a 100644
--- a/target/arc/decoder_fragments/arc-tbl.h
+++ b/target/arc/decoder_fragments/arc-tbl.h
@@ -22,475 +22,475 @@
  */
 
 /* abs<.f> b,c 00100bbb00101111FBBBCCCCCC001001.  */
-{ "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* abs<.f> 0,c 0010011000101111F111CCCCCC001001.  */
-{ "abs", 0x262F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "abs", 0x262F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* abs<.f> b,u6 00100bbb01101111FBBBuuuuuu001001.  */
-{ "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* abs<.f> 0,u6 0010011001101111F111uuuuuu001001.  */
-{ "abs", 0x266F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "abs", 0x266F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* abs<.f> b,limm 00100bbb00101111FBBB111110001001.  */
-{ "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* abs<.f> 0,limm 0010011000101111F111111110001001.  */
-{ "abs", 0x262F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "abs", 0x262F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* abssw<.f> b,c 00101bbb00101111FBBBCCCCCC000100.  */
-{ "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* abssw<.f> 0,c 0010111000101111F111CCCCCC000100.  */
-{ "abssw", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "abssw", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* abssw<.f> b,u6 00101bbb01101111FBBBuuuuuu000100.  */
-{ "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* abssw<.f> 0,u6 0010111001101111F111uuuuuu000100.  */
-{ "abssw", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "abssw", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* abssw<.f> b,limm 00101bbb00101111FBBB111110000100.  */
-{ "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* abssw<.f> 0,limm 0010111000101111F111111110000100.  */
-{ "abssw", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "abssw", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* abs_s b,c 01111bbbccc10001.  */
-{ "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* acm<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA.  */
-{ "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* acm<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ.  */
-{ "acm", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "acm", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* acm<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA.  */
-{ "acm", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "acm", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* acm<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ.  */
-{ "acm", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "acm", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* acm<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS.  */
-{ "acm", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "acm", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* acm<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA.  */
-{ "acm", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "acm", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* acm<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA.  */
-{ "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* acm<.f><.cc> b,b,limm 00110bbb11101000FBBB1111100QQQQQ.  */
-{ "acm", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "acm", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* adc<.f> a,b,c 00100bbb00000001FBBBCCCCCCAAAAAA.  */
-{ "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* adc<.f> 0,b,c 00100bbb00000001FBBBCCCCCC111110.  */
-{ "adc", 0x2001003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "adc", 0x2001003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* adc<.f><.cc> b,b,c 00100bbb11000001FBBBCCCCCC0QQQQQ.  */
-{ "adc", 0x20C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "adc", 0x20C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* adc<.f> a,b,u6 00100bbb01000001FBBBuuuuuuAAAAAA.  */
-{ "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* adc<.f> 0,b,u6 00100bbb01000001FBBBuuuuuu111110.  */
-{ "adc", 0x2041003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "adc", 0x2041003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* adc<.f><.cc> b,b,u6 00100bbb11000001FBBBuuuuuu1QQQQQ.  */
-{ "adc", 0x20C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "adc", 0x20C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* adc<.f> b,b,s12 00100bbb10000001FBBBssssssSSSSSS.  */
-{ "adc", 0x20810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "adc", 0x20810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* adc<.f> a,limm,c 0010011000000001F111CCCCCCAAAAAA.  */
-{ "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* adc<.f> a,b,limm 00100bbb00000001FBBB111110AAAAAA.  */
-{ "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* adc<.f> 0,limm,c 0010011000000001F111CCCCCC111110.  */
-{ "adc", 0x2601703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "adc", 0x2601703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* adc<.f> 0,b,limm 00100bbb00000001FBBB111110111110.  */
-{ "adc", 0x20010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "adc", 0x20010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* adc<.f><.cc> b,b,limm 00100bbb11000001FBBB1111100QQQQQ.  */
-{ "adc", 0x20C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "adc", 0x20C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* adc<.f><.cc> 0,limm,c 0010011011000001F111CCCCCC0QQQQQ.  */
-{ "adc", 0x26C17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "adc", 0x26C17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* adc<.f> a,limm,u6 0010011001000001F111uuuuuuAAAAAA.  */
-{ "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* adc<.f> 0,limm,u6 0010011001000001F111uuuuuu111110.  */
-{ "adc", 0x2641703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "adc", 0x2641703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* adc<.f><.cc> 0,limm,u6 0010011011000001F111uuuuuu1QQQQQ.  */
-{ "adc", 0x26C17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "adc", 0x26C17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* adc<.f> 0,limm,s12 0010011010000001F111ssssssSSSSSS.  */
-{ "adc", 0x26817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "adc", 0x26817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA.  */
-{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* adc<.f> 0,limm,limm 0010011000000001F111111110111110.  */
-{ "adc", 0x26017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "adc", 0x26017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ.  */
-{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* add<.f> a,b,c 00100bbb00000000FBBBCCCCCCAAAAAA.  */
-{ "add", 0x20000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "add", 0x20000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* add<.f> 0,b,c 00100bbb00000000FBBBCCCCCC111110.  */
-{ "add", 0x2000003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "add", 0x2000003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* add<.f><.cc> b,b,c 00100bbb11000000FBBBCCCCCC0QQQQQ.  */
-{ "add", 0x20C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "add", 0x20C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA.  */
-{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add<.f> 0,b,u6 00100bbb01000000FBBBuuuuuu111110.  */
-{ "add", 0x2040003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "add", 0x2040003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.  */
-{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* add<.f> b,b,s12 00100bbb10000000FBBBssssssSSSSSS.  */
-{ "add", 0x20800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "add", 0x20800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* add<.f> a,limm,c 0010011000000000F111CCCCCCAAAAAA.  */
-{ "add", 0x26007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "add", 0x26007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA.  */
-{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* add<.f> 0,limm,c 0010011000000000F111CCCCCC111110.  */
-{ "add", 0x2600703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "add", 0x2600703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* add<.f> 0,b,limm 00100bbb00000000FBBB111110111110.  */
-{ "add", 0x20000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "add", 0x20000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ.  */
-{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* add<.f><.cc> 0,limm,c 0010011011000000F111CCCCCC0QQQQQ.  */
-{ "add", 0x26C07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "add", 0x26C07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* add<.f> a,limm,u6 0010011001000000F111uuuuuuAAAAAA.  */
-{ "add", 0x26407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "add", 0x26407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add<.f> 0,limm,u6 0010011001000000F111uuuuuu111110.  */
-{ "add", 0x2640703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "add", 0x2640703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add<.f><.cc> 0,limm,u6 0010011011000000F111uuuuuu1QQQQQ.  */
-{ "add", 0x26C07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "add", 0x26C07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* add<.f> 0,limm,s12 0010011010000000F111ssssssSSSSSS.  */
-{ "add", 0x26807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "add", 0x26807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* add<.f> a,limm,limm 0010011000000000F111111110AAAAAA.  */
-{ "add", 0x26007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "add", 0x26007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* add<.f> 0,limm,limm 0010011000000000F111111110111110.  */
-{ "add", 0x26007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "add", 0x26007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* add<.f><.cc> 0,limm,limm 0010011011000000F1111111100QQQQQ.  */
-{ "add", 0x26C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "add", 0x26C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* add1<.f> a,b,c 00100bbb00010100FBBBCCCCCCAAAAAA.  */
-{ "add1", 0x20140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "add1", 0x20140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* add1<.f> 0,b,c 00100bbb00010100FBBBCCCCCC111110.  */
-{ "add1", 0x2014003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "add1", 0x2014003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* add1<.f><.cc> b,b,c 00100bbb11010100FBBBCCCCCC0QQQQQ.  */
-{ "add1", 0x20D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "add1", 0x20D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* add1<.f> a,b,u6 00100bbb01010100FBBBuuuuuuAAAAAA.  */
-{ "add1", 0x20540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "add1", 0x20540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add1<.f> 0,b,u6 00100bbb01010100FBBBuuuuuu111110.  */
-{ "add1", 0x2054003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "add1", 0x2054003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add1<.f><.cc> b,b,u6 00100bbb11010100FBBBuuuuuu1QQQQQ.  */
-{ "add1", 0x20D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "add1", 0x20D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* add1<.f> b,b,s12 00100bbb10010100FBBBssssssSSSSSS.  */
-{ "add1", 0x20940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "add1", 0x20940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* add1<.f> a,limm,c 0010011000010100F111CCCCCCAAAAAA.  */
-{ "add1", 0x26147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "add1", 0x26147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* add1<.f> a,b,limm 00100bbb00010100FBBB111110AAAAAA.  */
-{ "add1", 0x20140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "add1", 0x20140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* add1<.f> 0,limm,c 0010011000010100F111CCCCCC111110.  */
-{ "add1", 0x2614703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "add1", 0x2614703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* add1<.f> 0,b,limm 00100bbb00010100FBBB111110111110.  */
-{ "add1", 0x20140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "add1", 0x20140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* add1<.f><.cc> b,b,limm 00100bbb11010100FBBB1111100QQQQQ.  */
-{ "add1", 0x20D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "add1", 0x20D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* add1<.f><.cc> 0,limm,c 0010011011010100F111CCCCCC0QQQQQ.  */
-{ "add1", 0x26D47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "add1", 0x26D47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* add1<.f> a,limm,u6 0010011001010100F111uuuuuuAAAAAA.  */
-{ "add1", 0x26547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "add1", 0x26547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add1<.f> 0,limm,u6 0010011001010100F111uuuuuu111110.  */
-{ "add1", 0x2654703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "add1", 0x2654703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add1<.f><.cc> 0,limm,u6 0010011011010100F111uuuuuu1QQQQQ.  */
-{ "add1", 0x26D47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "add1", 0x26D47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* add1<.f> 0,limm,s12 0010011010010100F111ssssssSSSSSS.  */
-{ "add1", 0x26947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "add1", 0x26947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* add1<.f> a,limm,limm 0010011000010100F111111110AAAAAA.  */
-{ "add1", 0x26147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "add1", 0x26147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* add1<.f> 0,limm,limm 0010011000010100F111111110111110.  */
-{ "add1", 0x26147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "add1", 0x26147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* add1<.f><.cc> 0,limm,limm 0010011011010100F1111111100QQQQQ.  */
-{ "add1", 0x26D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "add1", 0x26D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* add1_s b,b,c 01111bbbccc10100.  */
-{ "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
+{ "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* add2<.f> a,b,c 00100bbb00010101FBBBCCCCCCAAAAAA.  */
-{ "add2", 0x20150000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "add2", 0x20150000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* add2<.f> 0,b,c 00100bbb00010101FBBBCCCCCC111110.  */
-{ "add2", 0x2015003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "add2", 0x2015003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* add2<.f><.cc> b,b,c 00100bbb11010101FBBBCCCCCC0QQQQQ.  */
-{ "add2", 0x20D50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "add2", 0x20D50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* add2<.f> a,b,u6 00100bbb01010101FBBBuuuuuuAAAAAA.  */
-{ "add2", 0x20550000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "add2", 0x20550000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add2<.f> 0,b,u6 00100bbb01010101FBBBuuuuuu111110.  */
-{ "add2", 0x2055003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "add2", 0x2055003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add2<.f><.cc> b,b,u6 00100bbb11010101FBBBuuuuuu1QQQQQ.  */
-{ "add2", 0x20D50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "add2", 0x20D50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* add2<.f> b,b,s12 00100bbb10010101FBBBssssssSSSSSS.  */
-{ "add2", 0x20950000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "add2", 0x20950000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* add2<.f> a,limm,c 0010011000010101F111CCCCCCAAAAAA.  */
-{ "add2", 0x26157000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "add2", 0x26157000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* add2<.f> a,b,limm 00100bbb00010101FBBB111110AAAAAA.  */
-{ "add2", 0x20150F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "add2", 0x20150F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* add2<.f> 0,limm,c 0010011000010101F111CCCCCC111110.  */
-{ "add2", 0x2615703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "add2", 0x2615703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* add2<.f> 0,b,limm 00100bbb00010101FBBB111110111110.  */
-{ "add2", 0x20150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "add2", 0x20150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* add2<.f><.cc> b,b,limm 00100bbb11010101FBBB1111100QQQQQ.  */
-{ "add2", 0x20D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "add2", 0x20D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* add2<.f><.cc> 0,limm,c 0010011011010101F111CCCCCC0QQQQQ.  */
-{ "add2", 0x26D57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "add2", 0x26D57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* add2<.f> a,limm,u6 0010011001010101F111uuuuuuAAAAAA.  */
-{ "add2", 0x26557000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "add2", 0x26557000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add2<.f> 0,limm,u6 0010011001010101F111uuuuuu111110.  */
-{ "add2", 0x2655703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "add2", 0x2655703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add2<.f><.cc> 0,limm,u6 0010011011010101F111uuuuuu1QQQQQ.  */
-{ "add2", 0x26D57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "add2", 0x26D57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* add2<.f> 0,limm,s12 0010011010010101F111ssssssSSSSSS.  */
-{ "add2", 0x26957000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "add2", 0x26957000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* add2<.f> a,limm,limm 0010011000010101F111111110AAAAAA.  */
-{ "add2", 0x26157F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "add2", 0x26157F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* add2<.f> 0,limm,limm 0010011000010101F111111110111110.  */
-{ "add2", 0x26157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "add2", 0x26157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* add2<.f><.cc> 0,limm,limm 0010011011010101F1111111100QQQQQ.  */
-{ "add2", 0x26D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "add2", 0x26D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* add2_s b,b,c 01111bbbccc10101.  */
-{ "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
+{ "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* add3<.f> a,b,c 00100bbb00010110FBBBCCCCCCAAAAAA.  */
-{ "add3", 0x20160000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "add3", 0x20160000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* add3<.f> 0,b,c 00100bbb00010110FBBBCCCCCC111110.  */
-{ "add3", 0x2016003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "add3", 0x2016003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* add3<.f><.cc> b,b,c 00100bbb11010110FBBBCCCCCC0QQQQQ.  */
-{ "add3", 0x20D60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "add3", 0x20D60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* add3<.f> a,b,u6 00100bbb01010110FBBBuuuuuuAAAAAA.  */
-{ "add3", 0x20560000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "add3", 0x20560000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add3<.f> 0,b,u6 00100bbb01010110FBBBuuuuuu111110.  */
-{ "add3", 0x2056003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "add3", 0x2056003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add3<.f><.cc> b,b,u6 00100bbb11010110FBBBuuuuuu1QQQQQ.  */
-{ "add3", 0x20D60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "add3", 0x20D60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* add3<.f> b,b,s12 00100bbb10010110FBBBssssssSSSSSS.  */
-{ "add3", 0x20960000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "add3", 0x20960000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* add3<.f> a,limm,c 0010011000010110F111CCCCCCAAAAAA.  */
-{ "add3", 0x26167000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "add3", 0x26167000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* add3<.f> a,b,limm 00100bbb00010110FBBB111110AAAAAA.  */
-{ "add3", 0x20160F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "add3", 0x20160F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* add3<.f> 0,limm,c 0010011000010110F111CCCCCC111110.  */
-{ "add3", 0x2616703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "add3", 0x2616703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* add3<.f> 0,b,limm 00100bbb00010110FBBB111110111110.  */
-{ "add3", 0x20160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "add3", 0x20160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* add3<.f><.cc> b,b,limm 00100bbb11010110FBBB1111100QQQQQ.  */
-{ "add3", 0x20D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "add3", 0x20D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* add3<.f><.cc> 0,limm,c 0010011011010110F111CCCCCC0QQQQQ.  */
-{ "add3", 0x26D67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "add3", 0x26D67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* add3<.f> a,limm,u6 0010011001010110F111uuuuuuAAAAAA.  */
-{ "add3", 0x26567000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "add3", 0x26567000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add3<.f> 0,limm,u6 0010011001010110F111uuuuuu111110.  */
-{ "add3", 0x2656703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "add3", 0x2656703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* add3<.f><.cc> 0,limm,u6 0010011011010110F111uuuuuu1QQQQQ.  */
-{ "add3", 0x26D67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "add3", 0x26D67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* add3<.f> 0,limm,s12 0010011010010110F111ssssssSSSSSS.  */
-{ "add3", 0x26967000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "add3", 0x26967000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* add3<.f> a,limm,limm 0010011000010110F111111110AAAAAA.  */
-{ "add3", 0x26167F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "add3", 0x26167F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* add3<.f> 0,limm,limm 0010011000010110F111111110111110.  */
-{ "add3", 0x26167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "add3", 0x26167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* add3<.f><.cc> 0,limm,limm 0010011011010110F1111111100QQQQQ.  */
-{ "add3", 0x26D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "add3", 0x26D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* add3_s b,b,c 01111bbbccc10110.  */
-{ "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
+{ "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* addqbs<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA.  */
-{ "addqbs", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "addqbs", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* addqbs<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ.  */
-{ "addqbs", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "addqbs", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* addqbs<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA.  */
-{ "addqbs", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "addqbs", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* addqbs<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ.  */
-{ "addqbs", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "addqbs", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* addqbs<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS.  */
-{ "addqbs", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "addqbs", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* addqbs<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA.  */
-{ "addqbs", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "addqbs", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* addqbs<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA.  */
-{ "addqbs", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "addqbs", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* addqbs<.f><.cc> b,b,limm 00110bbb11100100FBBB1111100QQQQQ.  */
-{ "addqbs", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "addqbs", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* addsdw<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA.  */
-{ "addsdw", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "addsdw", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* addsdw<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110.  */
-{ "addsdw", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "addsdw", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* addsdw<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ.  */
-{ "addsdw", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "addsdw", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* addsdw<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA.  */
-{ "addsdw", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "addsdw", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* addsdw<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110.  */
-{ "addsdw", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "addsdw", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* addsdw<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ.  */
-{ "addsdw", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "addsdw", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* addsdw<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS.  */
-{ "addsdw", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "addsdw", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* addsdw<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA.  */
-{ "addsdw", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "addsdw", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* addsdw<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA.  */
-{ "addsdw", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "addsdw", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* addsdw<.f> 0,limm,c 0010111000101000F111CCCCCC111110.  */
-{ "addsdw", 0x2E28703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "addsdw", 0x2E28703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* addsdw<.f> 0,b,limm 00101bbb00101000FBBB111110111110.  */
-{ "addsdw", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "addsdw", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* addsdw<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ.  */
-{ "addsdw", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "addsdw", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* addsdw<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ.  */
-{ "addsdw", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "addsdw", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* addsdw<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA.  */
-{ "addsdw", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "addsdw", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* addsdw<.f> 0,limm,u6 0010111001101000F111uuuuuu111110.  */
-{ "addsdw", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "addsdw", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* addsdw<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ.  */
-{ "addsdw", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "addsdw", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* addsdw<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS.  */
-{ "addsdw", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "addsdw", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* addsdw<.f> a,limm,limm 0010111000101000F111111110AAAAAA.  */
-{ "addsdw", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "addsdw", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* addsdw<.f> 0,limm,limm 0010111000101000F111111110111110.  */
-{ "addsdw", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "addsdw", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* addsdw<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ.  */
-{ "addsdw", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "addsdw", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* add_s a,b,c 01100bbbccc11aaa.  */
-{ "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* add_s b,b,h 01110bbbhhh00HHH.  */
-{ "add_s", 0x00007000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_R6H }, { 0 }},
+{ "add_s", 0x00007000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_R6H }, { 0 }},
 
 /* add_s b,b,h 01110bbbhhh000HH.  */
-{ "add_s", 0x00007000, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RH_S }, { 0 }},
+{ "add_s", 0x00007000, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RH_S }, { 0 }},
 
 /* add_s h,h,s3 01110ssshhh001HH.  */
-{ "add_s", 0x00007004, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RH_S, OPERAND_RH_Sdup, OPERAND_SIMM3_5_S }, { 0 }},
+{ "add_s", 0x00007004, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RH_S, OPERAND_RH_Sdup, OPERAND_SIMM3_5_S }, { 0 }},
 
 /* add_s c,b,u3 01101bbbccc00uuu.  */
-{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }},
+{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }},
 
 /* add_s OPERAND_R0,b,u6 01001bbb0UUU1uuu.  */
 { "add_s", 0x00004808, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { OPERAND_R0_S, OPERAND_RB_S, OPERAND_UIMM6_13_S }, { 0 }},
@@ -499,136 +499,136 @@
 { "add_s", 0x00004888, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { OPERAND_R1_S, OPERAND_RB_S, OPERAND_UIMM6_13_S }, { 0 }},
 
 /* add_s b,sp,u7 11000bbb100uuuuu.  */
-{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S }, { 0 }},
+{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S }, { 0 }},
 
 /* add_s b,b,u7 11100bbb0uuuuuuu.  */
-{ "add_s", 0x0000E000, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM7_9_S }, { 0 }},
+{ "add_s", 0x0000E000, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM7_9_S }, { 0 }},
 
 /* add_s SP,SP,u7 11000000101uuuuu.  */
-{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM7_A32_11_S }, { 0 }},
+{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM7_A32_11_S }, { 0 }},
 
 /* add_s OPERAND_R0,GP,s11 1100111sssssssss.  */
-{ "add_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_R0_S, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S }, { 0 }},
+{ "add_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_R0_S, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S }, { 0 }},
 
 /* add_s b,b,limm 01110bbb11000111.  */
-{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }},
+{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }},
 
 /* add_s b,b,limm 01110bbb11000011.  */
-{ "add_s", 0x000070C3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }},
+{ "add_s", 0x000070C3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }},
 
 /* add_s 0,limm,s3 01110sss11000111.  */
-{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA_S, OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }},
+{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA_S, OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }},
 
 /* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR.  */
-{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ.  */
-{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
+{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
 
 /* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR.  */
-{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ.  */
-{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }},
+{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }},
 
 /* aex b,s12 00100bbb10100111RBBBssssssSSSSSS.  */
-{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* aex limm,c 0010011000100111R111CCCCCCRRRRRR.  */
-{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* aex b,limm 00100bbb00100111RBBB111110RRRRRR.  */
-{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ.  */
-{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
+{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
 
 /* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ.  */
-{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_CC }},
+{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_CC }},
 
 /* aex limm,u6 0010011001100111R111uuuuuuRRRRRR.  */
-{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* aex<.cc> limm,u6 0010011011100111R111uuuuuu1QQQQQ.  */
-{ "aex", 0x26E77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }},
+{ "aex", 0x26E77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }},
 
 /* aex limm,s12 0010011010100111R111ssssssSSSSSS.  */
-{ "aex", 0x26A77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "aex", 0x26A77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* aex limm,limm 0010011000100111R111111110RRRRRR.  */
-{ "aex", 0x26277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }},
+{ "aex", 0x26277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }},
 
 /* aex<.cc> limm,limm 0010011011100111R1111111100QQQQQ.  */
-{ "aex", 0x26E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_CC }},
+{ "aex", 0x26E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_CC }},
 
 /* and<.f> a,b,c 00100bbb00000100FBBBCCCCCCAAAAAA.  */
-{ "and", 0x20040000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "and", 0x20040000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* and<.f> 0,b,c 00100bbb00000100FBBBCCCCCC111110.  */
-{ "and", 0x2004003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "and", 0x2004003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* and<.f><.cc> b,b,c 00100bbb11000100FBBBCCCCCC0QQQQQ.  */
-{ "and", 0x20C40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "and", 0x20C40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* and<.f> a,b,u6 00100bbb01000100FBBBuuuuuuAAAAAA.  */
-{ "and", 0x20440000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "and", 0x20440000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* and<.f> 0,b,u6 00100bbb01000100FBBBuuuuuu111110.  */
-{ "and", 0x2044003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "and", 0x2044003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* and<.f><.cc> b,b,u6 00100bbb11000100FBBBuuuuuu1QQQQQ.  */
-{ "and", 0x20C40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "and", 0x20C40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* and<.f> b,b,s12 00100bbb10000100FBBBssssssSSSSSS.  */
-{ "and", 0x20840000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "and", 0x20840000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* and<.f> a,limm,c 0010011000000100F111CCCCCCAAAAAA.  */
-{ "and", 0x26047000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "and", 0x26047000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* and<.f> a,b,limm 00100bbb00000100FBBB111110AAAAAA.  */
-{ "and", 0x20040F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "and", 0x20040F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* and<.f> 0,limm,c 0010011000000100F111CCCCCC111110.  */
-{ "and", 0x2604703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "and", 0x2604703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* and<.f> 0,b,limm 00100bbb00000100FBBB111110111110.  */
-{ "and", 0x20040FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "and", 0x20040FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* and<.f><.cc> b,b,limm 00100bbb11000100FBBB1111100QQQQQ.  */
-{ "and", 0x20C40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "and", 0x20C40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* and<.f><.cc> 0,limm,c 0010011011000100F111CCCCCC0QQQQQ.  */
-{ "and", 0x26C47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "and", 0x26C47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* and<.f> a,limm,u6 0010011001000100F111uuuuuuAAAAAA.  */
-{ "and", 0x26447000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "and", 0x26447000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* and<.f> 0,limm,u6 0010011001000100F111uuuuuu111110.  */
-{ "and", 0x2644703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "and", 0x2644703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* and<.f><.cc> 0,limm,u6 0010011011000100F111uuuuuu1QQQQQ.  */
-{ "and", 0x26C47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "and", 0x26C47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* and<.f> 0,limm,s12 0010011010000100F111ssssssSSSSSS.  */
-{ "and", 0x26847000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "and", 0x26847000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* and<.f> a,limm,limm 0010011000000100F111111110AAAAAA.  */
-{ "and", 0x26047F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "and", 0x26047F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* and<.f> 0,limm,limm 0010011000000100F111111110111110.  */
-{ "and", 0x26047FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "and", 0x26047FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* and<.f><.cc> 0,limm,limm 0010011011000100F1111111100QQQQQ.  */
-{ "and", 0x26C47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "and", 0x26C47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* and_s b,b,c 01111bbbccc00100.  */
-{ "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
+{ "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* asl<.f> b,c 00100bbb00101111FBBBCCCCCC000000.  */
-{ "asl", 0x202F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asl", 0x202F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asl<.f> 0,c 0010011000101111F111CCCCCC000000.  */
-{ "asl", 0x262F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "asl", 0x262F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* asl<.f> a,b,c 00101bbb00000000FBBBCCCCCCAAAAAA.  */
 { "asl", 0x28000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -640,10 +640,10 @@
 { "asl", 0x28C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* asl<.f> b,u6 00100bbb01101111FBBBuuuuuu000000.  */
-{ "asl", 0x206F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asl", 0x206F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asl<.f> 0,u6 0010011001101111F111uuuuuu000000.  */
-{ "asl", 0x266F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "asl", 0x266F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asl<.f> a,b,u6 00101bbb01000000FBBBuuuuuuAAAAAA.  */
 { "asl", 0x28400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
@@ -658,10 +658,10 @@
 { "asl", 0x28800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asl<.f> b,limm 00100bbb00101111FBBB111110000000.  */
-{ "asl", 0x202F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asl", 0x202F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asl<.f> 0,limm 0010011000101111F111111110000000.  */
-{ "asl", 0x262F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "asl", 0x262F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* asl<.f> a,limm,c 0010111000000000F111CCCCCCAAAAAA.  */
 { "asl", 0x2E007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
@@ -703,127 +703,127 @@
 { "asl", 0x2EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* asldw<.f> a,b,c 00101bbb00100001FBBBCCCCCCAAAAAA.  */
-{ "asldw", 0x28210000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asldw", 0x28210000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asldw<.f> 0,b,c 00101bbb00100001FBBBCCCCCC111110.  */
-{ "asldw", 0x2821003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asldw", 0x2821003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asldw<.f><.cc> b,b,c 00101bbb11100001FBBBCCCCCC0QQQQQ.  */
-{ "asldw", 0x28E10000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "asldw", 0x28E10000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* asldw<.f> a,b,u6 00101bbb01100001FBBBuuuuuuAAAAAA.  */
-{ "asldw", 0x28610000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asldw", 0x28610000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asldw<.f> 0,b,u6 00101bbb01100001FBBBuuuuuu111110.  */
-{ "asldw", 0x2861003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asldw", 0x2861003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asldw<.f><.cc> b,b,u6 00101bbb11100001FBBBuuuuuu1QQQQQ.  */
-{ "asldw", 0x28E10020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "asldw", 0x28E10020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* asldw<.f> b,b,s12 00101bbb10100001FBBBssssssSSSSSS.  */
-{ "asldw", 0x28A10000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "asldw", 0x28A10000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asldw<.f> a,limm,c 0010111000100001F111CCCCCCAAAAAA.  */
-{ "asldw", 0x2E217000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "asldw", 0x2E217000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* asldw<.f> a,b,limm 00101bbb00100001FBBB111110AAAAAA.  */
-{ "asldw", 0x28210F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asldw", 0x28210F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asldw<.f> 0,limm,c 0010111000100001F111CCCCCC111110.  */
-{ "asldw", 0x2E21703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "asldw", 0x2E21703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* asldw<.f> 0,b,limm 00101bbb00100001FBBB111110111110.  */
-{ "asldw", 0x28210FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asldw", 0x28210FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asldw<.f><.cc> 0,limm,c 0010111011100001F111CCCCCC0QQQQQ.  */
-{ "asldw", 0x2EE17000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "asldw", 0x2EE17000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* asldw<.f><.cc> b,b,limm 00101bbb11100001FBBB1111100QQQQQ.  */
-{ "asldw", 0x28E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "asldw", 0x28E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* asldw<.f> a,limm,u6 0010111001100001F111uuuuuuAAAAAA.  */
-{ "asldw", 0x2E617000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "asldw", 0x2E617000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asldw<.f> 0,limm,u6 0010111001100001F111uuuuuu111110.  */
-{ "asldw", 0x2E61703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "asldw", 0x2E61703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asldw<.f><.cc> 0,limm,u6 0010111011100001F111uuuuuu1QQQQQ.  */
-{ "asldw", 0x2EE17020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "asldw", 0x2EE17020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* asldw<.f> 0,limm,s12 0010111010100001F111ssssssSSSSSS.  */
-{ "asldw", 0x2EA17000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "asldw", 0x2EA17000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asldw<.f> a,limm,limm 0010111000100001F111111110AAAAAA.  */
-{ "asldw", 0x2E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "asldw", 0x2E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* asldw<.f> 0,limm,limm 0010111000100001F111111110111110.  */
-{ "asldw", 0x2E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "asldw", 0x2E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* asldw<.f><.cc> 0,limm,limm 0010111011100001F1111111100QQQQQ.  */
-{ "asldw", 0x2EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "asldw", 0x2EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* aslsdw<.f> a,b,c 00101bbb00100100FBBBCCCCCCAAAAAA.  */
-{ "aslsdw", 0x28240000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "aslsdw", 0x28240000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* aslsdw<.f> 0,b,c 00101bbb00100100FBBBCCCCCC111110.  */
-{ "aslsdw", 0x2824003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "aslsdw", 0x2824003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* aslsdw<.f><.cc> b,b,c 00101bbb11100100FBBBCCCCCC0QQQQQ.  */
-{ "aslsdw", 0x28E40000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "aslsdw", 0x28E40000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* aslsdw<.f> a,b,u6 00101bbb01100100FBBBuuuuuuAAAAAA.  */
-{ "aslsdw", 0x28640000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "aslsdw", 0x28640000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* aslsdw<.f> 0,b,u6 00101bbb01100100FBBBuuuuuu111110.  */
-{ "aslsdw", 0x2864003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "aslsdw", 0x2864003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* aslsdw<.f><.cc> b,b,u6 00101bbb11100100FBBBuuuuuu1QQQQQ.  */
-{ "aslsdw", 0x28E40020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "aslsdw", 0x28E40020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* aslsdw<.f> b,b,s12 00101bbb10100100FBBBssssssSSSSSS.  */
-{ "aslsdw", 0x28A40000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "aslsdw", 0x28A40000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* aslsdw<.f> a,limm,c 0010111000100100F111CCCCCCAAAAAA.  */
-{ "aslsdw", 0x2E247000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "aslsdw", 0x2E247000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* aslsdw<.f> a,b,limm 00101bbb00100100FBBB111110AAAAAA.  */
-{ "aslsdw", 0x28240F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "aslsdw", 0x28240F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* aslsdw<.f> 0,limm,c 0010111000100100F111CCCCCC111110.  */
-{ "aslsdw", 0x2E24703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "aslsdw", 0x2E24703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* aslsdw<.f> 0,b,limm 00101bbb00100100FBBB111110111110.  */
-{ "aslsdw", 0x28240FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "aslsdw", 0x28240FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* aslsdw<.f><.cc> 0,limm,c 0010111011100100F111CCCCCC0QQQQQ.  */
-{ "aslsdw", 0x2EE47000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "aslsdw", 0x2EE47000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* aslsdw<.f><.cc> b,b,limm 00101bbb11100100FBBB1111100QQQQQ.  */
-{ "aslsdw", 0x28E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "aslsdw", 0x28E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* aslsdw<.f> a,limm,u6 0010111001100100F111uuuuuuAAAAAA.  */
-{ "aslsdw", 0x2E647000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "aslsdw", 0x2E647000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* aslsdw<.f> 0,limm,u6 0010111001100100F111uuuuuu111110.  */
-{ "aslsdw", 0x2E64703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "aslsdw", 0x2E64703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* aslsdw<.f><.cc> 0,limm,u6 0010111011100100F111uuuuuu1QQQQQ.  */
-{ "aslsdw", 0x2EE47020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "aslsdw", 0x2EE47020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* aslsdw<.f> 0,limm,s12 0010111010100100F111ssssssSSSSSS.  */
-{ "aslsdw", 0x2EA47000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "aslsdw", 0x2EA47000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* aslsdw<.f> a,limm,limm 0010111000100100F111111110AAAAAA.  */
-{ "aslsdw", 0x2E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "aslsdw", 0x2E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* aslsdw<.f> 0,limm,limm 0010111000100100F111111110111110.  */
-{ "aslsdw", 0x2E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "aslsdw", 0x2E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* aslsdw<.f><.cc> 0,limm,limm 0010111011100100F1111111100QQQQQ.  */
-{ "aslsdw", 0x2EE47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "aslsdw", 0x2EE47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* asl_s b,c 01111bbbccc11011.  */
-{ "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* asl_s b,b,c 01111bbbccc11000.  */
 { "asl_s", 0x00007818, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
@@ -835,10 +835,10 @@
 { "asl_s", 0x0000B800, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
 
 /* asr<.f> b,c 00100bbb00101111FBBBCCCCCC000001.  */
-{ "asr", 0x202F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asr", 0x202F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asr<.f> 0,c 0010011000101111F111CCCCCC000001.  */
-{ "asr", 0x262F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "asr", 0x262F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* asr<.f> a,b,c 00101bbb00000010FBBBCCCCCCAAAAAA.  */
 { "asr", 0x28020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -850,10 +850,10 @@
 { "asr", 0x28C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* asr<.f> b,u6 00100bbb01101111FBBBuuuuuu000001.  */
-{ "asr", 0x206F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asr", 0x206F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asr<.f> 0,u6 0010011001101111F111uuuuuu000001.  */
-{ "asr", 0x266F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "asr", 0x266F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asr<.f> a,b,u6 00101bbb01000010FBBBuuuuuuAAAAAA.  */
 { "asr", 0x28420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
@@ -868,10 +868,10 @@
 { "asr", 0x28820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asr<.f> b,limm 00100bbb00101111FBBB111110000001.  */
-{ "asr", 0x202F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asr", 0x202F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asr<.f> 0,limm 0010011000101111F111111110000001.  */
-{ "asr", 0x262F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "asr", 0x262F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* asr<.f> a,limm,c 0010111000000010F111CCCCCCAAAAAA.  */
 { "asr", 0x2E027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
@@ -949,187 +949,187 @@
 { "asr8", 0x2E2F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* asrdw<.f> a,b,c 00101bbb00100010FBBBCCCCCCAAAAAA.  */
-{ "asrdw", 0x28220000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asrdw", 0x28220000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asrdw<.f> 0,b,c 00101bbb00100010FBBBCCCCCC111110.  */
-{ "asrdw", 0x2822003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asrdw", 0x2822003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asrdw<.f><.cc> b,b,c 00101bbb11100010FBBBCCCCCC0QQQQQ.  */
-{ "asrdw", 0x28E20000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "asrdw", 0x28E20000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* asrdw<.f> a,b,u6 00101bbb01100010FBBBuuuuuuAAAAAA.  */
-{ "asrdw", 0x28620000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrdw", 0x28620000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrdw<.f> 0,b,u6 00101bbb01100010FBBBuuuuuu111110.  */
-{ "asrdw", 0x2862003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrdw", 0x2862003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrdw<.f><.cc> b,b,u6 00101bbb11100010FBBBuuuuuu1QQQQQ.  */
-{ "asrdw", 0x28E20020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "asrdw", 0x28E20020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* asrdw<.f> b,b,s12 00101bbb10100010FBBBssssssSSSSSS.  */
-{ "asrdw", 0x28A20000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "asrdw", 0x28A20000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asrdw<.f> a,limm,c 0010111000100010F111CCCCCCAAAAAA.  */
-{ "asrdw", 0x2E227000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "asrdw", 0x2E227000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* asrdw<.f> a,b,limm 00101bbb00100010FBBB111110AAAAAA.  */
-{ "asrdw", 0x28220F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asrdw", 0x28220F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asrdw<.f> 0,limm,c 0010111000100010F111CCCCCC111110.  */
-{ "asrdw", 0x2E22703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "asrdw", 0x2E22703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* asrdw<.f> 0,b,limm 00101bbb00100010FBBB111110111110.  */
-{ "asrdw", 0x28220FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asrdw", 0x28220FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asrdw<.f><.cc> 0,limm,c 0010111011100010F111CCCCCC0QQQQQ.  */
-{ "asrdw", 0x2EE27000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "asrdw", 0x2EE27000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* asrdw<.f><.cc> b,b,limm 00101bbb11100010FBBB1111100QQQQQ.  */
-{ "asrdw", 0x28E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "asrdw", 0x28E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* asrdw<.f> a,limm,u6 0010111001100010F111uuuuuuAAAAAA.  */
-{ "asrdw", 0x2E627000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrdw", 0x2E627000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrdw<.f> 0,limm,u6 0010111001100010F111uuuuuu111110.  */
-{ "asrdw", 0x2E62703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrdw", 0x2E62703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrdw<.f><.cc> 0,limm,u6 0010111011100010F111uuuuuu1QQQQQ.  */
-{ "asrdw", 0x2EE27020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "asrdw", 0x2EE27020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* asrdw<.f> 0,limm,s12 0010111010100010F111ssssssSSSSSS.  */
-{ "asrdw", 0x2EA27000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "asrdw", 0x2EA27000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asrdw<.f> a,limm,limm 0010111000100010F111111110AAAAAA.  */
-{ "asrdw", 0x2E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "asrdw", 0x2E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* asrdw<.f> 0,limm,limm 0010111000100010F111111110111110.  */
-{ "asrdw", 0x2E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "asrdw", 0x2E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* asrdw<.f><.cc> 0,limm,limm 0010111011100010F1111111100QQQQQ.  */
-{ "asrdw", 0x2EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "asrdw", 0x2EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* asrs<.f> a,b,c 00101bbb00001011FBBBCCCCCCAAAAAA.  */
-{ "asrs", 0x280B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asrs", 0x280B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asrs<.f> 0,b,c 00101bbb00001011FBBBCCCCCC111110.  */
-{ "asrs", 0x280B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asrs", 0x280B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asrs<.f><.cc> b,b,c 00101bbb11001011FBBBCCCCCC0QQQQQ.  */
-{ "asrs", 0x28CB0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "asrs", 0x28CB0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* asrs<.f> a,b,u6 00101bbb01001011FBBBuuuuuuAAAAAA.  */
-{ "asrs", 0x284B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrs", 0x284B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrs<.f> 0,b,u6 00101bbb01001011FBBBuuuuuu111110.  */
-{ "asrs", 0x284B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrs", 0x284B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrs<.f><.cc> b,b,u6 00101bbb11001011FBBBuuuuuu1QQQQQ.  */
-{ "asrs", 0x28CB0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "asrs", 0x28CB0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* asrs<.f> b,b,s12 00101bbb10001011FBBBssssssSSSSSS.  */
-{ "asrs", 0x288B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "asrs", 0x288B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asrs<.f> a,limm,c 0010111000001011F111CCCCCCAAAAAA.  */
-{ "asrs", 0x2E0B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "asrs", 0x2E0B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* asrs<.f> a,b,limm 00101bbb00001011FBBB111110AAAAAA.  */
-{ "asrs", 0x280B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asrs", 0x280B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asrs<.f> 0,limm,c 0010111000001011F111CCCCCC111110.  */
-{ "asrs", 0x2E0B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "asrs", 0x2E0B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* asrs<.f> 0,b,limm 00101bbb00001011FBBB111110111110.  */
-{ "asrs", 0x280B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asrs", 0x280B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asrs<.f><.cc> b,b,limm 00101bbb11001011FBBB1111100QQQQQ.  */
-{ "asrs", 0x28CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "asrs", 0x28CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* asrs<.f><.cc> 0,limm,c 0010111011001011F111CCCCCC0QQQQQ.  */
-{ "asrs", 0x2ECB7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "asrs", 0x2ECB7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* asrs<.f> a,limm,u6 0010111001001011F111uuuuuuAAAAAA.  */
-{ "asrs", 0x2E4B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrs", 0x2E4B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrs<.f> 0,limm,u6 0010111001001011F111uuuuuu111110.  */
-{ "asrs", 0x2E4B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrs", 0x2E4B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrs<.f><.cc> 0,limm,u6 0010111011001011F111uuuuuu1QQQQQ.  */
-{ "asrs", 0x2ECB7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "asrs", 0x2ECB7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* asrs<.f> 0,limm,s12 0010111010001011F111ssssssSSSSSS.  */
-{ "asrs", 0x2E8B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "asrs", 0x2E8B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asrs<.f> a,limm,limm 0010111000001011F111111110AAAAAA.  */
-{ "asrs", 0x2E0B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "asrs", 0x2E0B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* asrs<.f> 0,limm,limm 0010111000001011F111111110111110.  */
-{ "asrs", 0x2E0B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "asrs", 0x2E0B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* asrs<.f><.cc> 0,limm,limm 0010111011001011F1111111100QQQQQ.  */
-{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* asrsdw<.f> a,b,c 00101bbb00100101FBBBCCCCCCAAAAAA.  */
-{ "asrsdw", 0x28250000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asrsdw", 0x28250000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asrsdw<.f> 0,b,c 00101bbb00100101FBBBCCCCCC111110.  */
-{ "asrsdw", 0x2825003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "asrsdw", 0x2825003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* asrsdw<.f><.cc> b,b,c 00101bbb11100101FBBBCCCCCC0QQQQQ.  */
-{ "asrsdw", 0x28E50000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "asrsdw", 0x28E50000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* asrsdw<.f> a,b,u6 00101bbb01100101FBBBuuuuuuAAAAAA.  */
-{ "asrsdw", 0x28650000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrsdw", 0x28650000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrsdw<.f> 0,b,u6 00101bbb01100101FBBBuuuuuu111110.  */
-{ "asrsdw", 0x2865003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrsdw", 0x2865003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrsdw<.f><.cc> b,b,u6 00101bbb11100101FBBBuuuuuu1QQQQQ.  */
-{ "asrsdw", 0x28E50020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "asrsdw", 0x28E50020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* asrsdw<.f> b,b,s12 00101bbb10100101FBBBssssssSSSSSS.  */
-{ "asrsdw", 0x28A50000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "asrsdw", 0x28A50000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asrsdw<.f> a,limm,c 0010111000100101F111CCCCCCAAAAAA.  */
-{ "asrsdw", 0x2E257000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "asrsdw", 0x2E257000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* asrsdw<.f> a,b,limm 00101bbb00100101FBBB111110AAAAAA.  */
-{ "asrsdw", 0x28250F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asrsdw", 0x28250F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asrsdw<.f> 0,limm,c 0010111000100101F111CCCCCC111110.  */
-{ "asrsdw", 0x2E25703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "asrsdw", 0x2E25703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* asrsdw<.f> 0,b,limm 00101bbb00100101FBBB111110111110.  */
-{ "asrsdw", 0x28250FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "asrsdw", 0x28250FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* asrsdw<.f><.cc> 0,limm,c 0010111011100101F111CCCCCC0QQQQQ.  */
-{ "asrsdw", 0x2EE57000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "asrsdw", 0x2EE57000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* asrsdw<.f><.cc> b,b,limm 00101bbb11100101FBBB1111100QQQQQ.  */
-{ "asrsdw", 0x28E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "asrsdw", 0x28E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* asrsdw<.f> a,limm,u6 0010111001100101F111uuuuuuAAAAAA.  */
-{ "asrsdw", 0x2E657000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrsdw", 0x2E657000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrsdw<.f> 0,limm,u6 0010111001100101F111uuuuuu111110.  */
-{ "asrsdw", 0x2E65703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "asrsdw", 0x2E65703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* asrsdw<.f><.cc> 0,limm,u6 0010111011100101F111uuuuuu1QQQQQ.  */
-{ "asrsdw", 0x2EE57020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "asrsdw", 0x2EE57020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* asrsdw<.f> 0,limm,s12 0010111010100101F111ssssssSSSSSS.  */
-{ "asrsdw", 0x2EA57000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "asrsdw", 0x2EA57000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* asrsdw<.f> a,limm,limm 0010111000100101F111111110AAAAAA.  */
-{ "asrsdw", 0x2E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "asrsdw", 0x2E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* asrsdw<.f> 0,limm,limm 0010111000100101F111111110111110.  */
-{ "asrsdw", 0x2E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "asrsdw", 0x2E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* asrsdw<.f><.cc> 0,limm,limm 0010111011100101F1111111100QQQQQ.  */
-{ "asrsdw", 0x2EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "asrsdw", 0x2EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* asr_s b,c 01111bbbccc11100.  */
-{ "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* asr_s b,b,c 01111bbbccc11010.  */
 { "asr_s", 0x0000781A, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
@@ -1141,34 +1141,34 @@
 { "asr_s", 0x0000B840, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
 
 /* avgqb<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA.  */
-{ "avgqb", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "avgqb", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* avgqb<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ.  */
-{ "avgqb", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "avgqb", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* avgqb<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA.  */
-{ "avgqb", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "avgqb", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* avgqb<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ.  */
-{ "avgqb", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "avgqb", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* avgqb<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS.  */
-{ "avgqb", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "avgqb", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* avgqb<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA.  */
-{ "avgqb", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "avgqb", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* avgqb<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA.  */
-{ "avgqb", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "avgqb", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* avgqb<.f><.cc> b,b,limm 00110bbb11100011FBBB1111100QQQQQ.  */
-{ "avgqb", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "avgqb", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt.  */
-{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM25_A16_5 }, { C_D }},
+{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM25_A16_5 }, { C_D }},
 
 /* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ.  */
-{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM21_A16_5 }, { C_CC, C_D }},
+{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM21_A16_5 }, { C_CC, C_D }},
 
 /* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110.  */
 { "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }},
@@ -1243,67 +1243,67 @@
 { "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T }},
 
 /* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA.  */
-{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bclr<.f> 0,b,c 00100bbb00010000FBBBCCCCCC111110.  */
-{ "bclr", 0x2010003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bclr", 0x2010003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bclr<.f><.cc> b,b,c 00100bbb11010000FBBBCCCCCC0QQQQQ.  */
-{ "bclr", 0x20D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "bclr", 0x20D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* bclr<.f> a,b,u6 00100bbb01010000FBBBuuuuuuAAAAAA.  */
-{ "bclr", 0x20500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bclr", 0x20500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bclr<.f> 0,b,u6 00100bbb01010000FBBBuuuuuu111110.  */
-{ "bclr", 0x2050003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bclr", 0x2050003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bclr<.f><.cc> b,b,u6 00100bbb11010000FBBBuuuuuu1QQQQQ.  */
-{ "bclr", 0x20D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bclr", 0x20D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bclr<.f> b,b,s12 00100bbb10010000FBBBssssssSSSSSS.  */
-{ "bclr", 0x20900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "bclr", 0x20900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bclr<.f> a,limm,c 0010011000010000F111CCCCCCAAAAAA.  */
-{ "bclr", 0x26107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bclr", 0x26107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bclr<.f> a,b,limm 00100bbb00010000FBBB111110AAAAAA.  */
-{ "bclr", 0x20100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bclr", 0x20100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bclr<.f> 0,limm,c 0010011000010000F111CCCCCC111110.  */
-{ "bclr", 0x2610703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bclr", 0x2610703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bclr<.f> 0,b,limm 00100bbb00010000FBBB111110111110.  */
-{ "bclr", 0x20100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bclr", 0x20100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bclr<.f><.cc> b,b,limm 00100bbb11010000FBBB1111100QQQQQ.  */
-{ "bclr", 0x20D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "bclr", 0x20D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* bclr<.f><.cc> 0,limm,c 0010011011010000F111CCCCCC0QQQQQ.  */
-{ "bclr", 0x26D07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "bclr", 0x26D07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* bclr<.f> a,limm,u6 0010011001010000F111uuuuuuAAAAAA.  */
-{ "bclr", 0x26507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bclr", 0x26507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bclr<.f> 0,limm,u6 0010011001010000F111uuuuuu111110.  */
-{ "bclr", 0x2650703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bclr", 0x2650703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bclr<.f><.cc> 0,limm,u6 0010011011010000F111uuuuuu1QQQQQ.  */
-{ "bclr", 0x26D07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bclr", 0x26D07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bclr<.f> 0,limm,s12 0010011010010000F111ssssssSSSSSS.  */
-{ "bclr", 0x26907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "bclr", 0x26907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bclr<.f> a,limm,limm 0010011000010000F111111110AAAAAA.  */
-{ "bclr", 0x26107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bclr", 0x26107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bclr<.f> 0,limm,limm 0010011000010000F111111110111110.  */
-{ "bclr", 0x26107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bclr", 0x26107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bclr<.f><.cc> 0,limm,limm 0010011011010000F1111111100QQQQQ.  */
-{ "bclr", 0x26D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "bclr", 0x26D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* bclr_s b,b,u5 10111bbb101uuuuu.  */
-{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
+{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
 
 /* beq_s s10 1111001sssssssss.  */
 { "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM10_A16_7_S }, { C_CC_EQ }},
@@ -1327,67 +1327,67 @@
 { "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BI, CD1, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA.  */
-{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bic<.f> 0,b,c 00100bbb00000110FBBBCCCCCC111110.  */
-{ "bic", 0x2006003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bic", 0x2006003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bic<.f><.cc> b,b,c 00100bbb11000110FBBBCCCCCC0QQQQQ.  */
-{ "bic", 0x20C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "bic", 0x20C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* bic<.f> a,b,u6 00100bbb01000110FBBBuuuuuuAAAAAA.  */
-{ "bic", 0x20460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bic", 0x20460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bic<.f> 0,b,u6 00100bbb01000110FBBBuuuuuu111110.  */
-{ "bic", 0x2046003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bic", 0x2046003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bic<.f><.cc> b,b,u6 00100bbb11000110FBBBuuuuuu1QQQQQ.  */
-{ "bic", 0x20C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bic", 0x20C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bic<.f> b,b,s12 00100bbb10000110FBBBssssssSSSSSS.  */
-{ "bic", 0x20860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "bic", 0x20860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bic<.f> a,limm,c 0010011000000110F111CCCCCCAAAAAA.  */
-{ "bic", 0x26067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bic", 0x26067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bic<.f> a,b,limm 00100bbb00000110FBBB111110AAAAAA.  */
-{ "bic", 0x20060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bic", 0x20060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bic<.f> 0,limm,c 0010011000000110F111CCCCCC111110.  */
-{ "bic", 0x2606703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bic", 0x2606703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bic<.f> 0,b,limm 00100bbb00000110FBBB111110111110.  */
-{ "bic", 0x20060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bic", 0x20060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bic<.f><.cc> b,b,limm 00100bbb11000110FBBB1111100QQQQQ.  */
-{ "bic", 0x20C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "bic", 0x20C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* bic<.f><.cc> 0,limm,c 0010011011000110F111CCCCCC0QQQQQ.  */
-{ "bic", 0x26C67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "bic", 0x26C67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* bic<.f> a,limm,u6 0010011001000110F111uuuuuuAAAAAA.  */
-{ "bic", 0x26467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bic", 0x26467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bic<.f> 0,limm,u6 0010011001000110F111uuuuuu111110.  */
-{ "bic", 0x2646703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bic", 0x2646703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bic<.f><.cc> 0,limm,u6 0010011011000110F111uuuuuu1QQQQQ.  */
-{ "bic", 0x26C67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bic", 0x26C67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bic<.f> 0,limm,s12 0010011010000110F111ssssssSSSSSS.  */
-{ "bic", 0x26867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "bic", 0x26867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bic<.f> a,limm,limm 0010011000000110F111111110AAAAAA.  */
-{ "bic", 0x26067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bic", 0x26067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bic<.f> 0,limm,limm 0010011000000110F111111110111110.  */
-{ "bic", 0x26067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bic", 0x26067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bic<.f><.cc> 0,limm,limm 0010011011000110F1111111100QQQQQ.  */
-{ "bic", 0x26C67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "bic", 0x26C67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* bic_s b,b,c 01111bbbccc00110.  */
-{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
+{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* bih c 00100RRR001001010RRRCCCCCCRRRRRR.  */
 { "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BIH, CD1, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
@@ -1396,10 +1396,10 @@
 { "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BIH, CD1, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt.  */
-{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM25_A32_5 }, { C_D }},
+{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM25_A32_5 }, { C_D }},
 
 /* bl<.cc><.d> s21 00001sssssssss00SSSSSSSSSSNQQQQQ.  */
-{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM21_A32_5 }, { C_CC, C_D }},
+{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM21_A32_5 }, { C_CC, C_D }},
 
 /* ble_s s7 1111011011ssssss.  */
 { "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LE }},
@@ -1414,130 +1414,130 @@
 { "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LT }},
 
 /* bl_s s13 11111sssssssssss.  */
-{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM13_A32_5_S }, { 0 }},
+{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM13_A32_5_S }, { 0 }},
 
 /* bmsk<.f> a,b,c 00100bbb00010011FBBBCCCCCCAAAAAA.  */
-{ "bmsk", 0x20130000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bmsk", 0x20130000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bmsk<.f> 0,b,c 00100bbb00010011FBBBCCCCCC111110.  */
-{ "bmsk", 0x2013003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bmsk", 0x2013003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bmsk<.f><.cc> b,b,c 00100bbb11010011FBBBCCCCCC0QQQQQ.  */
-{ "bmsk", 0x20D30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "bmsk", 0x20D30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* bmsk<.f> a,b,u6 00100bbb01010011FBBBuuuuuuAAAAAA.  */
-{ "bmsk", 0x20530000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bmsk", 0x20530000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bmsk<.f> 0,b,u6 00100bbb01010011FBBBuuuuuu111110.  */
-{ "bmsk", 0x2053003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bmsk", 0x2053003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bmsk<.f><.cc> b,b,u6 00100bbb11010011FBBBuuuuuu1QQQQQ.  */
-{ "bmsk", 0x20D30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bmsk", 0x20D30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bmsk<.f> b,b,s12 00100bbb10010011FBBBssssssSSSSSS.  */
-{ "bmsk", 0x20930000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "bmsk", 0x20930000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bmsk<.f> a,limm,c 0010011000010011F111CCCCCCAAAAAA.  */
-{ "bmsk", 0x26137000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bmsk", 0x26137000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bmsk<.f> a,b,limm 00100bbb00010011FBBB111110AAAAAA.  */
-{ "bmsk", 0x20130F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bmsk", 0x20130F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bmsk<.f> 0,limm,c 0010011000010011F111CCCCCC111110.  */
-{ "bmsk", 0x2613703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bmsk", 0x2613703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bmsk<.f> 0,b,limm 00100bbb00010011FBBB111110111110.  */
-{ "bmsk", 0x20130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bmsk", 0x20130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bmsk<.f><.cc> b,b,limm 00100bbb11010011FBBB1111100QQQQQ.  */
-{ "bmsk", 0x20D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "bmsk", 0x20D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* bmsk<.f><.cc> 0,limm,c 0010011011010011F111CCCCCC0QQQQQ.  */
-{ "bmsk", 0x26D37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "bmsk", 0x26D37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* bmsk<.f> a,limm,u6 0010011001010011F111uuuuuuAAAAAA.  */
-{ "bmsk", 0x26537000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bmsk", 0x26537000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bmsk<.f> 0,limm,u6 0010011001010011F111uuuuuu111110.  */
-{ "bmsk", 0x2653703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bmsk", 0x2653703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bmsk<.f><.cc> 0,limm,u6 0010011011010011F111uuuuuu1QQQQQ.  */
-{ "bmsk", 0x26D37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bmsk", 0x26D37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bmsk<.f> 0,limm,s12 0010011010010011F111ssssssSSSSSS.  */
-{ "bmsk", 0x26937000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "bmsk", 0x26937000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bmsk<.f> a,limm,limm 0010011000010011F111111110AAAAAA.  */
-{ "bmsk", 0x26137F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bmsk", 0x26137F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bmsk<.f> 0,limm,limm 0010011000010011F111111110111110.  */
-{ "bmsk", 0x26137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bmsk", 0x26137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bmsk<.f><.cc> 0,limm,limm 0010011011010011F1111111100QQQQQ.  */
-{ "bmsk", 0x26D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "bmsk", 0x26D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* bmskn<.f> a,b,c 00100bbb00101100FBBBCCCCCCAAAAAA.  */
-{ "bmskn", 0x202C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bmskn", 0x202C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bmskn<.f> 0,b,c 00100bbb00101100FBBBCCCCCC111110.  */
-{ "bmskn", 0x202C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bmskn", 0x202C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bmskn<.f><.cc> b,b,c 00100bbb11101100FBBBCCCCCC0QQQQQ.  */
-{ "bmskn", 0x20EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "bmskn", 0x20EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* bmskn<.f> a,b,u6 00100bbb01101100FBBBuuuuuuAAAAAA.  */
-{ "bmskn", 0x206C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bmskn", 0x206C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bmskn<.f> 0,b,u6 00100bbb01101100FBBBuuuuuu111110.  */
-{ "bmskn", 0x206C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bmskn", 0x206C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bmskn<.f><.cc> b,b,u6 00100bbb11101100FBBBuuuuuu1QQQQQ.  */
-{ "bmskn", 0x20EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bmskn", 0x20EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bmskn<.f> b,b,s12 00100bbb10101100FBBBssssssSSSSSS.  */
-{ "bmskn", 0x20AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "bmskn", 0x20AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bmskn<.f> a,limm,c 0010011000101100F111CCCCCCAAAAAA.  */
-{ "bmskn", 0x262C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bmskn", 0x262C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bmskn<.f> a,b,limm 00100bbb00101100FBBB111110AAAAAA.  */
-{ "bmskn", 0x202C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bmskn", 0x202C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bmskn<.f> 0,limm,c 0010011000101100F111CCCCCC111110.  */
-{ "bmskn", 0x262C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bmskn", 0x262C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bmskn<.f> 0,b,limm 00100bbb00101100FBBB111110111110.  */
-{ "bmskn", 0x202C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bmskn", 0x202C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bmskn<.f><.cc> b,b,limm 00100bbb11101100FBBB1111100QQQQQ.  */
-{ "bmskn", 0x20EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "bmskn", 0x20EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* bmskn<.f><.cc> 0,limm,c 0010011011101100F111CCCCCC0QQQQQ.  */
-{ "bmskn", 0x26EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "bmskn", 0x26EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* bmskn<.f> a,limm,u6 0010011001101100F111uuuuuuAAAAAA.  */
-{ "bmskn", 0x266C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bmskn", 0x266C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bmskn<.f> 0,limm,u6 0010011001101100F111uuuuuu111110.  */
-{ "bmskn", 0x266C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bmskn", 0x266C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bmskn<.f><.cc> 0,limm,u6 0010011011101100F111uuuuuu1QQQQQ.  */
-{ "bmskn", 0x26EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bmskn", 0x26EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bmskn<.f> 0,limm,s12 0010011010101100F111ssssssSSSSSS.  */
-{ "bmskn", 0x26AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "bmskn", 0x26AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bmskn<.f> a,limm,limm 0010011000101100F111111110AAAAAA.  */
-{ "bmskn", 0x262C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bmskn", 0x262C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bmskn<.f> 0,limm,limm 0010011000101100F111111110111110.  */
-{ "bmskn", 0x262C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bmskn", 0x262C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bmskn<.f><.cc> 0,limm,limm 0010011011101100F1111111100QQQQQ.  */
-{ "bmskn", 0x26EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "bmskn", 0x26EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* bmsk_s b,b,u5 10111bbb110uuuuu.  */
-{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
+{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
 
 /* bne_s s10 1111010sssssssss.  */
 { "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM10_A16_7_S }, { C_CC_NE }},
@@ -1645,10 +1645,10 @@
 { "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS  }},
 
 /* brk  00100101011011110000000000111111.  */
-{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { C_CC_HS  }},
+{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { 0 }, { C_CC_HS  }},
 
 /* brk_s  0111111111111111.  */
-{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
+{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100.  */
 { "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LO }},
@@ -1753,427 +1753,427 @@
 { "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB_S, OPERAND_ZB_S, OPERAND_SIMM8_A16_9_S }, { C_CC_NE }},
 
 /* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA.  */
-{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bset<.f> 0,b,c 00100bbb00001111FBBBCCCCCC111110.  */
-{ "bset", 0x200F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bset", 0x200F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bset<.f><.cc> b,b,c 00100bbb11001111FBBBCCCCCC0QQQQQ.  */
-{ "bset", 0x20CF0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "bset", 0x20CF0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* bset<.f> a,b,u6 00100bbb01001111FBBBuuuuuuAAAAAA.  */
-{ "bset", 0x204F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bset", 0x204F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bset<.f> 0,b,u6 00100bbb01001111FBBBuuuuuu111110.  */
-{ "bset", 0x204F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bset", 0x204F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bset<.f><.cc> b,b,u6 00100bbb11001111FBBBuuuuuu1QQQQQ.  */
-{ "bset", 0x20CF0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bset", 0x20CF0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bset<.f> b,b,s12 00100bbb10001111FBBBssssssSSSSSS.  */
-{ "bset", 0x208F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "bset", 0x208F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bset<.f> a,limm,c 0010011000001111F111CCCCCCAAAAAA.  */
-{ "bset", 0x260F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bset", 0x260F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bset<.f> a,b,limm 00100bbb00001111FBBB111110AAAAAA.  */
-{ "bset", 0x200F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bset", 0x200F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bset<.f> 0,limm,c 0010011000001111F111CCCCCC111110.  */
-{ "bset", 0x260F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bset", 0x260F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bset<.f> 0,b,limm 00100bbb00001111FBBB111110111110.  */
-{ "bset", 0x200F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bset", 0x200F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bset<.f><.cc> b,b,limm 00100bbb11001111FBBB1111100QQQQQ.  */
-{ "bset", 0x20CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "bset", 0x20CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* bset<.f><.cc> 0,limm,c 0010011011001111F111CCCCCC0QQQQQ.  */
-{ "bset", 0x26CF7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "bset", 0x26CF7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* bset<.f> a,limm,u6 0010011001001111F111uuuuuuAAAAAA.  */
-{ "bset", 0x264F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bset", 0x264F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bset<.f> 0,limm,u6 0010011001001111F111uuuuuu111110.  */
-{ "bset", 0x264F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bset", 0x264F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bset<.f><.cc> 0,limm,u6 0010011011001111F111uuuuuu1QQQQQ.  */
-{ "bset", 0x26CF7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bset", 0x26CF7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bset<.f> 0,limm,s12 0010011010001111F111ssssssSSSSSS.  */
-{ "bset", 0x268F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "bset", 0x268F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bset<.f> a,limm,limm 0010011000001111F111111110AAAAAA.  */
-{ "bset", 0x260F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bset", 0x260F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bset<.f> 0,limm,limm 0010011000001111F111111110111110.  */
-{ "bset", 0x260F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bset", 0x260F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bset<.f><.cc> 0,limm,limm 0010011011001111F1111111100QQQQQ.  */
-{ "bset", 0x26CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "bset", 0x26CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* bset_s b,b,u5 10111bbb100uuuuu.  */
-{ "bset_s", 0x0000B880, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
+{ "bset_s", 0x0000B880, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
 
 /* btst b,c 00100bbb000100011BBBCCCCCCRRRRRR.  */
-{ "btst", 0x20118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "btst", 0x20118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* btst b,c 00100bbb000100011BBBCCCCCC000000.  */
-{ "btst", 0x20118000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "btst", 0x20118000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* btst<.cc> b,c 00100bbb110100011BBBCCCCCC0QQQQQ.  */
-{ "btst", 0x20D18000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
+{ "btst", 0x20D18000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
 
 /* btst b,u6 00100bbb010100011BBBuuuuuuRRRRRR.  */
-{ "btst", 0x20518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "btst", 0x20518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* btst b,u6 00100bbb010100011BBBuuuuuu000000.  */
-{ "btst", 0x20518000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "btst", 0x20518000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* btst<.cc> b,u6 00100bbb110100011BBBuuuuuu1QQQQQ.  */
-{ "btst", 0x20D18020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
+{ "btst", 0x20D18020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* btst b,s12 00100bbb100100011BBBssssssSSSSSS.  */
-{ "btst", 0x20918000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
+{ "btst", 0x20918000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
 
 /* btst limm,c 00100110000100011111CCCCCCRRRRRR.  */
-{ "btst", 0x2611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "btst", 0x2611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* btst b,limm 00100bbb000100011BBB111110RRRRRR.  */
-{ "btst", 0x20118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "btst", 0x20118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* btst limm,c 00100110000100011111CCCCCC000000.  */
-{ "btst", 0x2611F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "btst", 0x2611F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* btst b,limm 00100bbb000100011BBB111110000000.  */
-{ "btst", 0x20118F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "btst", 0x20118F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* btst<.cc> b,limm 00100bbb110100011BBB1111100QQQQQ.  */
-{ "btst", 0x20D18F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
+{ "btst", 0x20D18F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
 
 /* btst<.cc> limm,c 00100110110100011111CCCCCC0QQQQQ.  */
-{ "btst", 0x26D1F000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "btst", 0x26D1F000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* btst limm,u6 00100110010100011111uuuuuuRRRRRR.  */
-{ "btst", 0x2651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "btst", 0x2651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* btst limm,u6 00100110010100011111uuuuuu000000.  */
-{ "btst", 0x2651F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "btst", 0x2651F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* btst<.cc> limm,u6 00100110110100011111uuuuuu1QQQQQ.  */
-{ "btst", 0x26D1F020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "btst", 0x26D1F020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* btst limm,s12 00100110100100011111ssssssSSSSSS.  */
-{ "btst", 0x2691F000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "btst", 0x2691F000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* btst limm,limm 00100110000100011111111110RRRRRR.  */
-{ "btst", 0x2611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "btst", 0x2611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* btst limm,limm 00100110000100011111111110000000.  */
-{ "btst", 0x2611FF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "btst", 0x2611FF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* btst<.cc> limm,limm 001001101101000111111111100QQQQQ.  */
-{ "btst", 0x26D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "btst", 0x26D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* btst_s b,u5 10111bbb111uuuuu.  */
-{ "btst_s", 0x0000B8E0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_UIMM5_11_S }, { 0 }},
+{ "btst_s", 0x0000B8E0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_UIMM5_11_S }, { 0 }},
 
 /* bxor<.f> a,b,c 00100bbb00010010FBBBCCCCCCAAAAAA.  */
-{ "bxor", 0x20120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bxor", 0x20120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bxor<.f> 0,b,c 00100bbb00010010FBBBCCCCCC111110.  */
-{ "bxor", 0x2012003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "bxor", 0x2012003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* bxor<.f><.cc> b,b,c 00100bbb11010010FBBBCCCCCC0QQQQQ.  */
-{ "bxor", 0x20D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "bxor", 0x20D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* bxor<.f> a,b,u6 00100bbb01010010FBBBuuuuuuAAAAAA.  */
-{ "bxor", 0x20520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bxor", 0x20520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bxor<.f> 0,b,u6 00100bbb01010010FBBBuuuuuu111110.  */
-{ "bxor", 0x2052003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "bxor", 0x2052003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bxor<.f><.cc> b,b,u6 00100bbb11010010FBBBuuuuuu1QQQQQ.  */
-{ "bxor", 0x20D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bxor", 0x20D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bxor<.f> b,b,s12 00100bbb10010010FBBBssssssSSSSSS.  */
-{ "bxor", 0x20920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "bxor", 0x20920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bxor<.f> a,limm,c 0010011000010010F111CCCCCCAAAAAA.  */
-{ "bxor", 0x26127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bxor", 0x26127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bxor<.f> a,b,limm 00100bbb00010010FBBB111110AAAAAA.  */
-{ "bxor", 0x20120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bxor", 0x20120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bxor<.f> 0,limm,c 0010011000010010F111CCCCCC111110.  */
-{ "bxor", 0x2612703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "bxor", 0x2612703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* bxor<.f> 0,b,limm 00100bbb00010010FBBB111110111110.  */
-{ "bxor", 0x20120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "bxor", 0x20120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* bxor<.f><.cc> b,b,limm 00100bbb11010010FBBB1111100QQQQQ.  */
-{ "bxor", 0x20D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "bxor", 0x20D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* bxor<.f><.cc> 0,limm,c 0010011011010010F111CCCCCC0QQQQQ.  */
-{ "bxor", 0x26D27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "bxor", 0x26D27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* bxor<.f> a,limm,u6 0010011001010010F111uuuuuuAAAAAA.  */
-{ "bxor", 0x26527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bxor", 0x26527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bxor<.f> 0,limm,u6 0010011001010010F111uuuuuu111110.  */
-{ "bxor", 0x2652703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "bxor", 0x2652703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* bxor<.f><.cc> 0,limm,u6 0010011011010010F111uuuuuu1QQQQQ.  */
-{ "bxor", 0x26D27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "bxor", 0x26D27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* bxor<.f> 0,limm,s12 0010011010010010F111ssssssSSSSSS.  */
-{ "bxor", 0x26927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "bxor", 0x26927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* bxor<.f> a,limm,limm 0010011000010010F111111110AAAAAA.  */
-{ "bxor", 0x26127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bxor", 0x26127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bxor<.f> 0,limm,limm 0010011000010010F111111110111110.  */
-{ "bxor", 0x26127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "bxor", 0x26127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* bxor<.f><.cc> 0,limm,limm 0010011011010010F1111111100QQQQQ.  */
-{ "bxor", 0x26D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "bxor", 0x26D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* b_s s10 1111000sssssssss.  */
-{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM10_A16_7_S }, { 0 }},
+{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM10_A16_7_S }, { 0 }},
 
 /* clamp<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA.  */
-{ "clamp", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "clamp", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* clamp<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ.  */
-{ "clamp", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "clamp", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* clamp<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA.  */
-{ "clamp", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "clamp", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* clamp<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ.  */
-{ "clamp", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "clamp", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* clamp<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS.  */
-{ "clamp", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "clamp", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* clamp<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA.  */
-{ "clamp", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "clamp", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* clamp<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA.  */
-{ "clamp", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "clamp", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* clamp<.f><.cc> b,b,limm 00110bbb11101010FBBB1111100QQQQQ.  */
-{ "clamp", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "clamp", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* clri c 00100111001011110000CCCCCC111111.  */
-{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }},
+{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* clri u6 00100111011011110000uuuuuu111111.  */
-{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* clri 00100111011011110000uuuuuu111111.  */
-{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* cmacrdw<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA.  */
-{ "cmacrdw", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "cmacrdw", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* cmacrdw<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110.  */
-{ "cmacrdw", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "cmacrdw", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* cmacrdw<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ.  */
-{ "cmacrdw", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "cmacrdw", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* cmacrdw<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA.  */
-{ "cmacrdw", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "cmacrdw", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* cmacrdw<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110.  */
-{ "cmacrdw", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "cmacrdw", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* cmacrdw<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ.  */
-{ "cmacrdw", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "cmacrdw", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* cmacrdw<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS.  */
-{ "cmacrdw", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "cmacrdw", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* cmacrdw<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA.  */
-{ "cmacrdw", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "cmacrdw", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* cmacrdw<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA.  */
-{ "cmacrdw", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "cmacrdw", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* cmacrdw<.f> 0,limm,c 0010111000100110F111CCCCCC111110.  */
-{ "cmacrdw", 0x2E26703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "cmacrdw", 0x2E26703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* cmacrdw<.f> 0,b,limm 00101bbb00100110FBBB111110111110.  */
-{ "cmacrdw", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "cmacrdw", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* cmacrdw<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ.  */
-{ "cmacrdw", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "cmacrdw", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* cmacrdw<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ.  */
-{ "cmacrdw", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "cmacrdw", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* cmacrdw<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA.  */
-{ "cmacrdw", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "cmacrdw", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* cmacrdw<.f> 0,limm,u6 0010111001100110F111uuuuuu111110.  */
-{ "cmacrdw", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "cmacrdw", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* cmacrdw<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ.  */
-{ "cmacrdw", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "cmacrdw", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* cmacrdw<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS.  */
-{ "cmacrdw", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "cmacrdw", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* cmacrdw<.f> a,limm,limm 0010111000100110F111111110AAAAAA.  */
-{ "cmacrdw", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "cmacrdw", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* cmacrdw<.f> 0,limm,limm 0010111000100110F111111110111110.  */
-{ "cmacrdw", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "cmacrdw", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* cmacrdw<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ.  */
-{ "cmacrdw", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "cmacrdw", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* cmp b,c 00100bbb000011001BBBCCCCCCRRRRRR.  */
-{ "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* cmp b,c 00100bbb000011001BBBCCCCCC000000.  */
-{ "cmp", 0x200C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "cmp", 0x200C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* cmp<.cc> b,c 00100bbb110011001BBBCCCCCC0QQQQQ.  */
-{ "cmp", 0x20CC8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
+{ "cmp", 0x20CC8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
 
 /* cmp b,u6 00100bbb010011001BBBuuuuuuRRRRRR.  */
-{ "cmp", 0x204C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "cmp", 0x204C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* cmp b,u6 00100bbb010011001BBBuuuuuu000000.  */
-{ "cmp", 0x204C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "cmp", 0x204C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* cmp<.cc> b,u6 00100bbb110011001BBBuuuuuu1QQQQQ.  */
-{ "cmp", 0x20CC8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
+{ "cmp", 0x20CC8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* cmp b,s12 00100bbb100011001BBBssssssSSSSSS.  */
-{ "cmp", 0x208C8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
+{ "cmp", 0x208C8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
 
 /* cmp limm,c 00100110000011001111CCCCCCRRRRRR.  */
-{ "cmp", 0x260CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "cmp", 0x260CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* cmp b,limm 00100bbb000011001BBB111110RRRRRR.  */
-{ "cmp", 0x200C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "cmp", 0x200C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* cmp limm,c 00100110000011001111CCCCCC000000.  */
-{ "cmp", 0x260CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "cmp", 0x260CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* cmp b,limm 00100bbb000011001BBB111110000000.  */
-{ "cmp", 0x200C8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "cmp", 0x200C8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* cmp<.cc> b,limm 00100bbb110011001BBB1111100QQQQQ.  */
-{ "cmp", 0x20CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
+{ "cmp", 0x20CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
 
 /* cmp<.cc> limm,c 00100110110011001111CCCCCC0QQQQQ.  */
-{ "cmp", 0x26CCF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "cmp", 0x26CCF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* cmp limm,u6 00100110010011001111uuuuuuRRRRRR.  */
-{ "cmp", 0x264CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "cmp", 0x264CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* cmp limm,u6 00100110010011001111uuuuuu000000.  */
-{ "cmp", 0x264CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "cmp", 0x264CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* cmp<.cc> limm,u6 00100110110011001111uuuuuu1QQQQQ.  */
-{ "cmp", 0x26CCF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "cmp", 0x26CCF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* cmp limm,s12 00100110100011001111ssssssSSSSSS.  */
-{ "cmp", 0x268CF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "cmp", 0x268CF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* cmp limm,limm 00100110000011001111111110RRRRRR.  */
-{ "cmp", 0x260CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "cmp", 0x260CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* cmp limm,limm 00100110000011001111111110000000.  */
-{ "cmp", 0x260CFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "cmp", 0x260CFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* cmp<.cc> limm,limm 001001101100110011111111100QQQQQ.  */
-{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* cmp_s b,h 01110bbbhhh10HHH.  */
-{ "cmp_s", 0x00007010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_R6H }, { 0 }},
+{ "cmp_s", 0x00007010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_R6H }, { 0 }},
 
 /* cmp_s b,h 01110bbbhhh100HH.  */
-{ "cmp_s", 0x00007010, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { 0 }},
+{ "cmp_s", 0x00007010, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RH_S }, { 0 }},
 
 /* cmp_s h,s3 01110ssshhh101HH.  */
-{ "cmp_s", 0x00007014, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }},
+{ "cmp_s", 0x00007014, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }},
 
 /* cmp_s b,u7 11100bbb1uuuuuuu.  */
-{ "cmp_s", 0x0000E080, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_UIMM7_9_S }, { 0 }},
+{ "cmp_s", 0x0000E080, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_UIMM7_9_S }, { 0 }},
 
 /* cmp_s b,limm 01110bbb11010111.  */
-{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }},
+{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }},
 
 /* cmp_s b,limm 01110bbb11010011.  */
-{ "cmp_s", 0x000070D3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }},
+{ "cmp_s", 0x000070D3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }},
 
 /* cmp_s limm,s3 01110sss11010111.  */
-{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }},
+{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }},
 
 /* crc<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA.  */
-{ "crc", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "crc", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* crc<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110.  */
-{ "crc", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "crc", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* crc<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ.  */
-{ "crc", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "crc", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* crc<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA.  */
-{ "crc", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "crc", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* crc<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110.  */
-{ "crc", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "crc", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* crc<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ.  */
-{ "crc", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "crc", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* crc<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS.  */
-{ "crc", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "crc", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* crc<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA.  */
-{ "crc", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "crc", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* crc<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA.  */
-{ "crc", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "crc", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* crc<.f> 0,limm,c 0010111000101100F111CCCCCC111110.  */
-{ "crc", 0x2E2C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "crc", 0x2E2C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* crc<.f> 0,b,limm 00101bbb00101100FBBB111110111110.  */
-{ "crc", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "crc", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* crc<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ.  */
-{ "crc", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "crc", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* crc<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ.  */
-{ "crc", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "crc", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* crc<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA.  */
-{ "crc", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "crc", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* crc<.f> 0,limm,u6 0010111001101100F111uuuuuu111110.  */
-{ "crc", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "crc", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* crc<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ.  */
-{ "crc", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "crc", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* crc<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS.  */
-{ "crc", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "crc", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* crc<.f> a,limm,limm 0010111000101100F111111110AAAAAA.  */
-{ "crc", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "crc", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* crc<.f> 0,limm,limm 0010111000101100F111111110111110.  */
-{ "crc", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "crc", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* crc<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ.  */
-{ "crc", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "crc", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* daddh11<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA.  */
 { "daddh11", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -2656,7 +2656,7 @@
 { "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS.  */
-{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_RB, OPERAND_SIMM13_A16_20}, { C_DNZ_D }},
+{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM13_A16_20}, { C_DNZ_D }},
 
 /* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA.  */
 { "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -2959,70 +2959,70 @@
 { "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* divacc c 00101011001011110000CCCCCC111111.  */
-{ "divacc", 0x2B2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RC }, { 0 }},
+{ "divacc", 0x2B2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* divacc u6 00101011011011110000uuuuuu111111.  */
-{ "divacc", 0x2B6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "divacc", 0x2B6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* divaw<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA.  */
-{ "divaw", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "divaw", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* divaw<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110.  */
-{ "divaw", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "divaw", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* divaw<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ.  */
-{ "divaw", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "divaw", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* divaw<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA.  */
-{ "divaw", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "divaw", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* divaw<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110.  */
-{ "divaw", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "divaw", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* divaw<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ.  */
-{ "divaw", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "divaw", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* divaw<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS.  */
-{ "divaw", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "divaw", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* divaw<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA.  */
-{ "divaw", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "divaw", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* divaw<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA.  */
-{ "divaw", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "divaw", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* divaw<.f> 0,limm,c 0010111000001000F111CCCCCC111110.  */
-{ "divaw", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "divaw", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* divaw<.f> 0,b,limm 00101bbb00001000FBBB111110111110.  */
-{ "divaw", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "divaw", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* divaw<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ.  */
-{ "divaw", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "divaw", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* divaw<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ.  */
-{ "divaw", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "divaw", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* divaw<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA.  */
-{ "divaw", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "divaw", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* divaw<.f> 0,limm,u6 0010111001001000F111uuuuuu111110.  */
-{ "divaw", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "divaw", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* divaw<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ.  */
-{ "divaw", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "divaw", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* divaw<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS.  */
-{ "divaw", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "divaw", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* divaw<.f> a,limm,limm 0010111000001000F111111110AAAAAA.  */
-{ "divaw", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "divaw", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* divaw<.f> 0,limm,limm 0010111000001000F111111110111110.  */
-{ "divaw", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "divaw", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* divaw<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ.  */
-{ "divaw", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "divaw", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA.  */
 { "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -3205,19 +3205,19 @@
 { "dmachu", 0x2ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* dmacpf<.f> a,b,c 00101bbb00111011FBBBCCCCCCAAAAAA.  */
-{ "dmacpf", 0x283B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "dmacpf", 0x283B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* dmacpf<.f><.cc> b,b,c 00101bbb11111011FBBBCCCCCC0QQQQQ.  */
-{ "dmacpf", 0x28FB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "dmacpf", 0x28FB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* dmacpf<.f> 0,b,c 00101bbb00111011FBBBCCCCCC111110.  */
-{ "dmacpf", 0x283B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "dmacpf", 0x283B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* dmacpf<.f> a,b,limm 00101bbb00111011FBBB111110AAAAAA.  */
-{ "dmacpf", 0x283B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "dmacpf", 0x283B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* dmacpf<.f><.cc> b,b,limm 00101bbb11111011FBBB1111100QQQQQ.  */
-{ "dmacpf", 0x28FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "dmacpf", 0x28FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* dmacwh<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA.  */
 { "dmacwh", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -3340,10 +3340,10 @@
 { "dmacwhu", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* dmb u3 00100011011011110001RRRuuu111111.  */
-{ "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM3_23 }, { 0 }},
+{ "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM3_23 }, { 0 }},
 
 /* dmb    00100011011011110001RRR000111111.  */
-{ "dmb", 0x236F103F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+{ "dmb", 0x236F103F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA.  */
 { "dmpyh", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -4066,19 +4066,19 @@
 { "dmulh22", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* dmulpf<.f> a,b,c 00101bbb00111010FBBBCCCCCCAAAAAA.  */
-{ "dmulpf", 0x283A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "dmulpf", 0x283A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* dmulpf<.f><.cc> b,b,c 00101bbb11111010FBBBCCCCCC0QQQQQ.  */
-{ "dmulpf", 0x28FA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "dmulpf", 0x28FA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* dmulpf<.f> 0,b,c 00101bbb00111010FBBBCCCCCC111110.  */
-{ "dmulpf", 0x283A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "dmulpf", 0x283A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* dmulpf<.f> a,b,limm 00101bbb00111010FBBB111110AAAAAA.  */
-{ "dmulpf", 0x283A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "dmulpf", 0x283A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* dmulpf<.f><.cc> b,b,limm 00101bbb11111010FBBB1111100QQQQQ.  */
-{ "dmulpf", 0x28FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "dmulpf", 0x28FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* drsubh11<.f> a,b,c 00110bbb00010100FBBBCCCCCCAAAAAA.  */
 { "drsubh11", 0x30140000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -4801,7 +4801,7 @@
 { "dsubh22", 0x36FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* dsync  00100010011011110001RRRRRR111111.  */
-{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* ei_s u10 010111uuuuuuuuuu.  */
 { "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, EI, CD2, { OPERAND_UIMM10_6_S }, { 0 }},
@@ -4810,85 +4810,85 @@
 { "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { OPERAND_UIMM6_11_S }, { 0 }},
 
 /* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100.  */
-{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* ex<.di> b,u6 00100bbb01101111DBBBuuuuuu001100.  */
-{ "ex", 0x206F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "ex", 0x206F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* ex<.di> b,limm 00100bbb00101111DBBB111110001100.  */
-{ "ex", 0x202F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "ex", 0x202F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* ex<.di> limm,c 0010011000101111D111CCCCCC001100.  */
-{ "ex", 0x262F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "ex", 0x262F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* ex<.di> limm,u6 0010011001101111D111uuuuuu001100.  */
-{ "ex", 0x266F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "ex", 0x266F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* ex<.di> limm,limm 0010011000101111D111111110001100.  */
-{ "ex", 0x262F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "ex", 0x262F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* extb<.f> b,c 00100bbb00101111FBBBCCCCCC000111.  */
-{ "extb", 0x202F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "extb", 0x202F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* extb<.f> 0,c 0010011000101111F111CCCCCC000111.  */
-{ "extb", 0x262F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "extb", 0x262F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* extb<.f> b,u6 00100bbb01101111FBBBuuuuuu000111.  */
-{ "extb", 0x206F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "extb", 0x206F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* extb<.f> 0,u6 0010011001101111F111uuuuuu000111.  */
-{ "extb", 0x266F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "extb", 0x266F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* extb<.f> b,limm 00100bbb00101111FBBB111110000111.  */
-{ "extb", 0x202F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "extb", 0x202F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* extb<.f> 0,limm 0010011000101111F111111110000111.  */
-{ "extb", 0x262F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "extb", 0x262F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* extb_s b,c 01111bbbccc01111.  */
-{ "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* exth<.f> b,c 00100bbb00101111FBBBCCCCCC001000.  */
-{ "exth", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "exth", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* exth<.f> 0,c 0010011000101111F111CCCCCC001000.  */
-{ "exth", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "exth", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* exth<.f> b,u6 00100bbb01101111FBBBuuuuuu001000.  */
-{ "exth", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "exth", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* exth<.f> 0,u6 0010011001101111F111uuuuuu001000.  */
-{ "exth", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "exth", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* exth<.f> b,limm 00100bbb00101111FBBB111110001000.  */
-{ "exth", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "exth", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* exth<.f> 0,limm 0010011000101111F111111110001000.  */
-{ "exth", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "exth", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* exth_s b,c 01111bbbccc10000.  */
-{ "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* extw<.f> b,c 00100bbb00101111FBBBCCCCCC001000.  */
-{ "extw", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "extw", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* extw<.f> 0,c 0010011000101111F111CCCCCC001000.  */
-{ "extw", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "extw", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* extw<.f> b,u6 00100bbb01101111FBBBuuuuuu001000.  */
-{ "extw", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "extw", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* extw<.f> 0,u6 0010011001101111F111uuuuuu001000.  */
-{ "extw", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "extw", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* extw<.f> b,limm 00100bbb00101111FBBB111110001000.  */
-{ "extw", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "extw", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* extw<.f> 0,limm 0010011000101111F111111110001000.  */
-{ "extw", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "extw", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* extw_s b,c 01111bbbccc10000.  */
-{ "extw_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "extw_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* fadd<.f> a,b,c 00110bbb00000001FBBBCCCCCCAAAAAA.  */
 { "fadd", 0x30010000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -4951,22 +4951,22 @@
 { "fadd", 0x36C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* fbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001011.  */
-{ "fbfdw", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }},
+{ "fbfdw", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }},
 
 /* fbfdw<.f> 0,c 0010111000101111F111CCCCCC001011.  */
-{ "fbfdw", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "fbfdw", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* fbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001011.  */
-{ "fbfdw", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }},
+{ "fbfdw", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }},
 
 /* fbfdw<.f> 0,u6 0010111001101111F111uuuuuu001011.  */
-{ "fbfdw", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "fbfdw", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* fbfdw<.f> b,limm 00101bbb00101111FBBB111110001011.  */
-{ "fbfdw", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }},
+{ "fbfdw", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }},
 
 /* fbfdw<.f> 0,limm 0010111000101111F111111110001011.  */
-{ "fbfdw", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "fbfdw", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* fcvt32 a,b,c 00110bbb000010000BBBCCCCCCAAAAAA.  */
 { "fcvt32", 0x30080000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }},
@@ -5689,25 +5689,25 @@
 { "ffs", 0x2E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* flag c 00100RRR001010010RRRCCCCCCRRRRRR.  */
-{ "flag", 0x20290000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }},
+{ "flag", 0x20290000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* flag<.cc> c 00100RRR111010010RRRCCCCCC0QQQQQ.  */
-{ "flag", 0x20E90000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { C_CC }},
+{ "flag", 0x20E90000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { C_CC }},
 
 /* flag u6 00100RRR011010010RRRuuuuuuRRRRRR.  */
-{ "flag", 0x20690000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "flag", 0x20690000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* flag<.cc> u6 00100RRR111010010RRRuuuuuu1QQQQQ.  */
-{ "flag", 0x20E90020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { C_CC }},
+{ "flag", 0x20E90020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC }},
 
 /* flag s12 00100RRR101010010RRRssssssSSSSSS.  */
-{ "flag", 0x20A90000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_SIMM12_20 }, { 0 }},
+{ "flag", 0x20A90000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { 0 }},
 
 /* flag limm 00100RRR001010010RRR111110RRRRRR.  */
-{ "flag", 0x20290F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }},
+{ "flag", 0x20290F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* flag<.cc> limm 00100RRR111010010RRR1111100QQQQQ.  */
-{ "flag", 0x20E90F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { C_CC }},
+{ "flag", 0x20E90F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { C_CC }},
 
 /* fls<.f> b,c 00101bbb00101111FBBBCCCCCC010011.  */
 { "fls", 0x282F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -6310,160 +6310,160 @@
 { "fsub", 0x36C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* fxtr<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA.  */
-{ "fxtr", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "fxtr", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* fxtr<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ.  */
-{ "fxtr", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "fxtr", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* fxtr<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA.  */
-{ "fxtr", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "fxtr", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* fxtr<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ.  */
-{ "fxtr", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "fxtr", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* fxtr<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS.  */
-{ "fxtr", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "fxtr", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* fxtr<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA.  */
-{ "fxtr", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "fxtr", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* fxtr<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA.  */
-{ "fxtr", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "fxtr", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* fxtr<.f><.cc> b,b,limm 00110bbb11100110FBBB1111100QQQQQ.  */
-{ "fxtr", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "fxtr", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* iaddr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA.  */
-{ "iaddr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "iaddr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* iaddr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ.  */
-{ "iaddr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "iaddr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* iaddr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA.  */
-{ "iaddr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "iaddr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* iaddr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ.  */
-{ "iaddr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "iaddr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* iaddr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS.  */
-{ "iaddr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "iaddr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* iaddr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA.  */
-{ "iaddr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "iaddr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* iaddr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA.  */
-{ "iaddr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "iaddr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* iaddr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ.  */
-{ "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* j c 00100RRR001000000RRRCCCCCCRRRRRR.  */
-{ "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* j OPERAND_BLINK 00100RRR001000000RRR011111RRRRRR.  */
-{ "j", 0x202007C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }},
+{ "j", 0x202007C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }},
 
 /* j.F OPERAND_ILINK1 00100RRR001000001RRR011101RRRRRR.  */
-{ "j", 0x20208740, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK1, OPERAND_BRAKETdup }, { C_FHARD }},
+{ "j", 0x20208740, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_ILINK1, OPERAND_BRAKETdup }, { C_FHARD }},
 
 /* j.F OPERAND_ILINK2 00100RRR001000001RRR011110RRRRRR.  */
-{ "j", 0x20208780, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK2, OPERAND_BRAKETdup }, { C_FHARD }},
+{ "j", 0x20208780, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_ILINK2, OPERAND_BRAKETdup }, { C_FHARD }},
 
 /* jcc c 00100RRR111000000RRRCCCCCC0QQQQQ.  */
-{ "j", 0x20E00000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
+{ "j", 0x20E00000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
 
 /* jcc OPERAND_BLINK 00100RRR111000000RRR0111110QQQQQ.  */
-{ "j", 0x20E007C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }},
+{ "j", 0x20E007C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }},
 
 /* j.Fcc OPERAND_ILINK1 00100RRR111000001RRR0111010QQQQQ.  */
-{ "j", 0x20E08740, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK1, OPERAND_BRAKETdup }, { C_FHARD, C_CC }},
+{ "j", 0x20E08740, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_ILINK1, OPERAND_BRAKETdup }, { C_FHARD, C_CC }},
 
 /* j.Fcc OPERAND_ILINK2 00100RRR111000001RRR0111100QQQQQ.  */
-{ "j", 0x20E08780, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK2, OPERAND_BRAKETdup }, { C_FHARD, C_CC }},
+{ "j", 0x20E08780, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_ILINK2, OPERAND_BRAKETdup }, { C_FHARD, C_CC }},
 
 /* j.D c 00100RRR001000010RRRCCCCCCRRRRRR.  */
-{ "j", 0x20210000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "j", 0x20210000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* j.D OPERAND_BLINK 00100RRR001000010RRR011111RRRRRR.  */
-{ "j", 0x202107C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "j", 0x202107C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* jcc.D c 00100RRR111000010RRRCCCCCC0QQQQQ.  */
-{ "j", 0x20E10000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
+{ "j", 0x20E10000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
 
 /* jcc.D OPERAND_BLINK 00100RRR111000010RRR0111110QQQQQ.  */
-{ "j", 0x20E107C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
+{ "j", 0x20E107C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
 
 /* j c 00100RRR00100000RRRRCCCCCCRRRRRR.  */
-{ "j", 0x20200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "j", 0x20200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* j OPERAND_BLINK 00100RRR00100000RRRR011111RRRRRR.  */
-{ "j", 0x202007C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }},
+{ "j", 0x202007C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }},
 
 /* jcc c 00100RRR11100000RRRRCCCCCC0QQQQQ.  */
-{ "j", 0x20E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
+{ "j", 0x20E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
 
 /* jcc OPERAND_BLINK 00100RRR11100000RRRR0111110QQQQQ.  */
-{ "j", 0x20E007C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }},
+{ "j", 0x20E007C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }},
 
 /* j.D c 00100RRR00100001RRRRCCCCCCRRRRRR.  */
-{ "j", 0x20210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "j", 0x20210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* j.D OPERAND_BLINK 00100RRR00100001RRRR011111RRRRRR.  */
-{ "j", 0x202107C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "j", 0x202107C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* jcc.D c 00100RRR11100001RRRRCCCCCC0QQQQQ.  */
-{ "j", 0x20E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
+{ "j", 0x20E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
 
 /* jcc.D OPERAND_BLINK 00100RRR11100001RRRR0111110QQQQQ.  */
-{ "j", 0x20E107C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
+{ "j", 0x20E107C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
 
 /* j s12 00100RRR101000000RRRssssssSSSSSS.  */
-{ "j", 0x20A00000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }},
+{ "j", 0x20A00000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { 0 }},
 
 /* j.D s12 00100RRR101000010RRRssssssSSSSSS.  */
-{ "j", 0x20A10000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }},
+{ "j", 0x20A10000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { C_DHARD }},
 
 /* j s12 00100RRR10100000RRRRssssssSSSSSS.  */
-{ "j", 0x20A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }},
+{ "j", 0x20A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { 0 }},
 
 /* j.D s12 00100RRR10100001RRRRssssssSSSSSS.  */
-{ "j", 0x20A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }},
+{ "j", 0x20A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { C_DHARD }},
 
 /* j u6 00100RRR011000000RRRuuuuuuRRRRRR.  */
-{ "j", 0x20600000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "j", 0x20600000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* jcc u6 00100RRR111000000RRRuuuuuu1QQQQQ.  */
-{ "j", 0x20E00020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }},
+{ "j", 0x20E00020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC }},
 
 /* j.D u6 00100RRR011000010RRRuuuuuuRRRRRR.  */
-{ "j", 0x20610000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }},
+{ "j", 0x20610000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_DHARD }},
 
 /* jcc.D u6 00100RRR111000010RRRuuuuuu1QQQQQ.  */
-{ "j", 0x20E10020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }},
+{ "j", 0x20E10020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }},
 
 /* j u6 00100RRR01100000RRRRuuuuuuRRRRRR.  */
-{ "j", 0x20600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "j", 0x20600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* jcc u6 00100RRR11100000RRRRuuuuuu1QQQQQ.  */
-{ "j", 0x20E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }},
+{ "j", 0x20E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC }},
 
 /* j.D u6 00100RRR01100001RRRRuuuuuuRRRRRR.  */
-{ "j", 0x20610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }},
+{ "j", 0x20610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_DHARD }},
 
 /* jcc.D u6 00100RRR11100001RRRRuuuuuu1QQQQQ.  */
-{ "j", 0x20E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }},
+{ "j", 0x20E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }},
 
 /* j limm 00100RRR001000000RRR111110RRRRRR.  */
-{ "j", 0x20200F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { 0 }},
+{ "j", 0x20200F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* jcc limm 00100RRR111000000RRR1111100QQQQQ.  */
-{ "j", 0x20E00F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { C_CC }},
+{ "j", 0x20E00F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { C_CC }},
 
 /* j limm 00100RRR00100000RRRR111110RRRRRR.  */
-{ "j", 0x20200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { 0 }},
+{ "j", 0x20200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* jcc limm 00100RRR11100000RRRR1111100QQQQQ.  */
-{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { C_CC }},
+{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { C_CC }},
 
 /* jeq_s OPERAND_BLINK 0111110011100000.  */
 { "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_EQ }},
@@ -6472,92 +6472,92 @@
 { "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_EQ }},
 
 /* jl c 00100RRR001000100RRRCCCCCCRRRRRR.  */
-{ "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* jlcc c 00100RRR111000100RRRCCCCCC0QQQQQ.  */
-{ "jl", 0x20E20000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
+{ "jl", 0x20E20000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
 
 /* jl.D c 00100RRR001000110RRRCCCCCCRRRRRR.  */
-{ "jl", 0x20230000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "jl", 0x20230000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* jlcc.D c 00100RRR111000110RRRCCCCCC0QQQQQ.  */
-{ "jl", 0x20E30000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
+{ "jl", 0x20E30000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
 
 /* jl c 00100RRR00100010RRRRCCCCCCRRRRRR.  */
-{ "jl", 0x20220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "jl", 0x20220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* jlcc c 00100RRR11100010RRRRCCCCCC0QQQQQ.  */
-{ "jl", 0x20E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
+{ "jl", 0x20E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }},
 
 /* jl.D c 00100RRR00100011RRRRCCCCCCRRRRRR.  */
-{ "jl", 0x20230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "jl", 0x20230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* jlcc.D c 00100RRR11100011RRRRCCCCCC0QQQQQ.  */
-{ "jl", 0x20E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
+{ "jl", 0x20E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }},
 
 /* jl s12 00100RRR101000100RRRssssssSSSSSS.  */
-{ "jl", 0x20A20000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }},
+{ "jl", 0x20A20000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { 0 }},
 
 /* jl.D s12 00100RRR101000110RRRssssssSSSSSS.  */
-{ "jl", 0x20A30000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }},
+{ "jl", 0x20A30000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { C_DHARD }},
 
 /* jl s12 00100RRR10100010RRRRssssssSSSSSS.  */
-{ "jl", 0x20A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }},
+{ "jl", 0x20A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { 0 }},
 
 /* jl.D s12 00100RRR10100011RRRRssssssSSSSSS.  */
-{ "jl", 0x20A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }},
+{ "jl", 0x20A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { C_DHARD }},
 
 /* jl u6 00100RRR011000100RRRuuuuuuRRRRRR.  */
-{ "jl", 0x20620000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "jl", 0x20620000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* jlcc u6 00100RRR111000100RRRuuuuuu1QQQQQ.  */
-{ "jl", 0x20E20020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }},
+{ "jl", 0x20E20020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC }},
 
 /* jl.D u6 00100RRR011000110RRRuuuuuuRRRRRR.  */
-{ "jl", 0x20630000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }},
+{ "jl", 0x20630000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_DHARD }},
 
 /* jlcc.D u6 00100RRR111000110RRRuuuuuu1QQQQQ.  */
-{ "jl", 0x20E30020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }},
+{ "jl", 0x20E30020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }},
 
 /* jl u6 00100RRR01100010RRRRuuuuuuRRRRRR.  */
-{ "jl", 0x20620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "jl", 0x20620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* jlcc u6 00100RRR11100010RRRRuuuuuu1QQQQQ.  */
-{ "jl", 0x20E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }},
+{ "jl", 0x20E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC }},
 
 /* jl.D u6 00100RRR01100011RRRRuuuuuuRRRRRR.  */
-{ "jl", 0x20630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }},
+{ "jl", 0x20630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_DHARD }},
 
 /* jlcc.D u6 00100RRR11100011RRRRuuuuuu1QQQQQ.  */
-{ "jl", 0x20E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }},
+{ "jl", 0x20E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }},
 
 /* jl limm 00100RRR001000100RRR111110RRRRRR.  */
-{ "jl", 0x20220F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { 0 }},
+{ "jl", 0x20220F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* jlcc limm 00100RRR111000100RRR1111100QQQQQ.  */
-{ "jl", 0x20E20F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { C_CC }},
+{ "jl", 0x20E20F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { C_CC }},
 
 /* jl limm 00100RRR00100010RRRR111110RRRRRR.  */
-{ "jl", 0x20220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { 0 }},
+{ "jl", 0x20220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* jlcc limm 00100RRR11100010RRRR1111100QQQQQ.  */
-{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { C_CC }},
+{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { C_CC }},
 
 /* jli_s u10 010110uuuuuuuuuu.  */
 { "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JLI, CD1, { OPERAND_UIMM10_6_S }, { 0 }},
 { "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JLI, CD1, { OPERAND_UIMM10_6_S_JLIOFF }, { 0 }},
 
 /* jl_s b 01111bbb01000000.  */
-{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }},
+{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* jl_s.D b 01111bbb01100000.  */
-{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* jl_s b 01111bbb01000000.  */
-{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }},
+{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* jl_s.D b 01111bbb01100000.  */
-{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* jne_s OPERAND_BLINK 0111110111100000.  */
 { "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_NE }},
@@ -6566,163 +6566,163 @@
 { "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_NE }},
 
 /* j_s b 01111bbb00000000.  */
-{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }},
+{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* j_s.D b 01111bbb00100000.  */
-{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* j_s OPERAND_BLINK 0111111011100000.  */
-{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }},
+{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* j_s.D OPERAND_BLINK 0111111111100000.  */
-{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* j_s b 01111bbb00000000.  */
-{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }},
+{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* j_s.D b 01111bbb00100000.  */
-{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* j_s OPERAND_BLINK 0111111011100000.  */
-{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }},
+{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* j_s.D OPERAND_BLINK 0111111111100000.  */
-{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }},
+{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }},
 
 /* kflag c 00100RRR001010011RRRCCCCCCRRRRRR.  */
-{ "kflag", 0x20298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }},
+{ "kflag", 0x20298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* kflag<.cc> c 00100RRR111010011RRRCCCCCC0QQQQQ.  */
-{ "kflag", 0x20E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { C_CC }},
+{ "kflag", 0x20E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { C_CC }},
 
 /* kflag u6 00100RRR011010011RRRuuuuuuRRRRRR.  */
-{ "kflag", 0x20698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "kflag", 0x20698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* kflag<.cc> u6 00100RRR111010011RRRuuuuuu1QQQQQ.  */
-{ "kflag", 0x20E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { C_CC }},
+{ "kflag", 0x20E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { C_CC }},
 
 /* kflag s12 00100RRR101010011RRRssssssSSSSSS.  */
-{ "kflag", 0x20A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_SIMM12_20 }, { 0 }},
+{ "kflag", 0x20A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM12_20 }, { 0 }},
 
 /* kflag limm 00100RRR001010011RRR111110RRRRRR.  */
-{ "kflag", 0x20298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }},
+{ "kflag", 0x20298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* kflag<.cc> limm 00100RRR111010011RRR1111100QQQQQ.  */
-{ "kflag", 0x20E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { C_CC }},
+{ "kflag", 0x20E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { C_CC }},
 
 /* ld<.di><.aa><.x><zz> a,b 00010bbb000000000BBBDaaZZXAAAAAA.  */
-{ "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+{ "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
 
 /* ld<.di><.aa><.x><zz> a,b,c 00100bbbaa110ZZXDBBBCCCCCCAAAAAA.  */
-{ "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+{ "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
 /* ld<.di><.aa><.x><zz> 0,b 00010bbb000000000BBBDaaZZX111110.  */
-{ "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+{ "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
 
 /* ld<.di><.aa><.x><zz> 0,b,c 00100bbbaa110ZZXDBBBCCCCCC111110.  */
-{ "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+{ "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
 /* ld<.di><.aa><.x><zz> a,b,s9 00010bbbssssssssSBBBDaaZZXAAAAAA.  */
-{ "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+{ "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
 
 /* ld<.di><.aa><.x><zz> 0,b,s9 00010bbbssssssssSBBBDaaZZX111110.  */
-{ "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+{ "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
 
 /* ld<.di><.x><zz> a,limm 00010110000000000111DRRZZXAAAAAA.  */
-{ "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
+{ "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
 
 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA.  */
-{ "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+{ "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
 /* ld<.di><.aa><.x><zz> a,limm,c 00100110aa110ZZXD111CCCCCCAAAAAA.  */
-{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
 /* ld<.di><.x><zz> 0,limm 00010110000000000111DRRZZX111110.  */
-{ "ld", 0x1600703E, 0xFFFFF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
+{ "ld", 0x1600703E, 0xFFFFF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
 
 /* ld<.di><.aa><.x><zz> 0,b,limm 00100bbbaa110ZZXDBBB111110111110.  */
-{ "ld", 0x20300FBE, 0xF8380FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+{ "ld", 0x20300FBE, 0xF8380FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
 /* ld<.di><.aa><.x><zz> 0,limm,c 00100110aa110ZZXD111CCCCCC111110.  */
-{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
 /* ld<.di><.aa><.x><zz> a,limm,s9 00010110ssssssssS111DaaZZXAAAAAA.  */
-{ "ld", 0x16007000, 0xFF007000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+{ "ld", 0x16007000, 0xFF007000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
 
 /* ld<.di><.aa><.x><zz> 0,limm,s9 00010110ssssssssS111DaaZZX111110.  */
-{ "ld", 0x1600703E, 0xFF00703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+{ "ld", 0x1600703E, 0xFF00703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
 
 /* ld<.di><.aa><.x><zz> a,limm,limm 00100110aa110ZZXD111111110AAAAAA.  */
-{ "ld", 0x26307F80, 0xFF387FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+{ "ld", 0x26307F80, 0xFF387FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
 /* ld<.di><.aa><.x><zz> 0,limm,limm 00100110aa110ZZXD111111110111110.  */
-{ "ld", 0x26307FBE, 0xFF387FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+{ "ld", 0x26307FBE, 0xFF387FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
 /* ldb_s a,b,c 01100bbbccc01aaa.  */
-{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
+{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
 
 /* ldb_s c,b,u5 10001bbbcccuuuuu.  */
-{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
+{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
 
 /* ldb_s b,SP,u7 11000bbb001uuuuu.  */
-{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
+{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
 
 /* ldb_s OPERAND_R0,GP,s9 1100101sssssssss.  */
-{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM9_7_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
+{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM9_7_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
 
 /* ldd<.di><.aa> a,b 00010bbb000000000BBBDaa110AAAAAA.  */
-{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di><.aa> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA.  */
-{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
+{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,b 00010bbb000000000BBBDaa110111110.  */
-{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,b,c 00100bbbaa110110DBBBCCCCCC111110.  */
-{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
+{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
 
 /* ldd<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA.  */
-{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa110111110.  */
-{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di> a,limm 00010110000000000111DRR110AAAAAA.  */
-{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI20, C_ZZ_D }},
+{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI20, C_ZZ_D }},
 
 /* ldd<.di><.aa> a,b,limm 00100bbbaa110110DBBB111110AAAAAA.  */
-{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
+{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
 
 /* ldd<.di> a,limm,c 00100110RR110110D111CCCCCCAAAAAA.  */
-{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_ZZ_D }},
+{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* ldd<.di> 0,limm 00010110000000000111DRR110111110.  */
-{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI20, C_ZZ_D }},
+{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI20, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,b,limm 00100bbbaa110110DBBB111110111110.  */
-{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
+{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
 
 /* ldd<.di> 0,limm,c 00100110RR110110D111CCCCCC111110.  */
-{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_ZZ_D }},
+{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* ldd<.di><.aa> a,limm,s9 00010110ssssssssS111Daa110AAAAAA.  */
-{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa110111110.  */
-{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldh_s a,b,c 01100bbbccc10aaa.  */
-{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
+{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
 
 /* ldh_s c,b,u6 10010bbbcccuuuuu.  */
-{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
+{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
 
 /* ldh_s.X c,b,u6 10011bbbcccuuuuu.  */
-{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_XHARD, C_ZZ_H }},
+{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_XHARD, C_ZZ_H }},
 
 /* ldh_s OPERAND_R0,GP,s10 1100110sssssssss.  */
-{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }},
+{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }},
 
 /* ldi b,c 00100bbb00100110RBBBCCCCCCRRRRRR.  */
 { "ldi", 0x20260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
@@ -6758,31 +6758,31 @@
 { "ldi_s", 0x00005008, 0x0000F808, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_UIMM7_13_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* ldm a,u6,b 00101bbb01001100RBBBRuuuuuAAAAAA.  */
-{ "ldm", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }},
+{ "ldm", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }},
 
 /* ldm 0,u6,b 00101bbb01001100RBBBRuuuuu111110.  */
-{ "ldm", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }},
+{ "ldm", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }},
 
 /* ldm a,u6,limm 0010111001001100R111RuuuuuAAAAAA.  */
-{ "ldm", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }},
+{ "ldm", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }},
 
 /* ldm 0,u6,limm 0010111001001100R111Ruuuuu111110.  */
-{ "ldm", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }},
+{ "ldm", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }},
 
 /* ldw_s a,b,c 01100bbbccc10aaa.  */
-{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
+{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
 
 /* ldw_s c,b,u6 10010bbbcccuuuuu.  */
-{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
+{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
 
 /* ldw_s.X c,b,u6 10011bbbcccuuuuu.  */
-{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_XHARD, C_ZZ_H }},
+{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_XHARD, C_ZZ_H }},
 
 /* ldw_s OPERAND_R0,GP,s10 1100110sssssssss.  */
-{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }},
+{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }},
 
 /* ld_s a,b,c 01100bbbccc00aaa.  */
-{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { 0 }},
+{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* ld_s.AS a,b,c 01001bbbccc00aaa.  */
 { "ld_s", 0x00004800, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_AS }},
@@ -6800,205 +6800,205 @@
 { "ld_s", 0x00004304, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R3_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* ld_s b,SP,u7 11000bbb000uuuuu.  */
-{ "ld_s", 0x0000C000, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
+{ "ld_s", 0x0000C000, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* ld_s c,b,u7 10000bbbcccuuuuu.  */
-{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
+{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* ld_s b,PCL,u10 11010bbbuuuuuuuu.  */
-{ "ld_s", 0x0000D000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_PCL_S, OPERAND_UIMM10_A32_8_S, OPERAND_BRAKETdup }, { 0 }},
+{ "ld_s", 0x0000D000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_PCL_S, OPERAND_UIMM10_A32_8_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* ld_s OPERAND_R0,GP,s11 1100100sssssssss.  */
-{ "ld_s", 0x0000C800, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S, OPERAND_BRAKETdup }, { 0 }},
+{ "ld_s", 0x0000C800, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, ARC_INSN_SUBCLASS_NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* ld_s OPERAND_R1,GP,s11 01010SSSSSS00sss.  */
 { "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R1_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_13_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110.  */
-{ "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }},
+{ "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }},
 
 /* prefetch b 00010bbb000000000BBB0RR000111110.  */
-{ "prefetch", 0x1000003E, 0xF8FF89FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { 0 }},
+{ "prefetch", 0x1000003E, 0xF8FF89FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { 0 }},
 
 /* prefetch<.aa> b,s9 00010bbbssssssssSBBB0aa000111110.  */
-{ "prefetch", 0x1000003E, 0xF80009FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }},
+{ "prefetch", 0x1000003E, 0xF80009FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }},
 
 /* prefetch<.aa> b,limm 00100bbbaa1100000BBB111110111110.  */
-{ "prefetch", 0x20300FBE, 0xF83F8FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }},
+{ "prefetch", 0x20300FBE, 0xF83F8FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }},
 
 /* prefetch<.aa> limm,c 00100110aa1100000111CCCCCC111110.  */
-{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }},
+{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }},
 
 /* prefetch limm 000101100000000001110RR000111110.  */
-{ "prefetch", 0x1600703E, 0xFFFFF9FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "prefetch", 0x1600703E, 0xFFFFF9FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* prefetch<.aa> limm,s9 00010110ssssssssS1110aa000111110.  */
-{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }},
+{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }},
 
 /* prefetch limm,s9 00010110ssssssssS1110RR000111110.  */
-{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }},
+{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }},
 
 /* prefetch<.aa> limm,limm 00100110aa1100000111111110111110.  */
-{ "prefetch", 0x26307FBE, 0xFF3FFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_AA8 }},
+{ "prefetch", 0x26307FBE, 0xFF3FFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_AA8 }},
 
 /* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110.  */
-{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }},
+{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }},
 
 /* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110.  */
-{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }},
+{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }},
 
 /* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110.  */
-{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }},
+{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }},
 
 /* prealloc limm,c 00100110RR1100010111CCCCCC111110.  */
-{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* prealloc limm 000101100000000001110RR001111110.  */
-{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* prealloc limm,s9 00010110ssssssssS1110RR001111110.  */
-{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }},
+{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }},
 
 /* prefetchl2<.aa> b,c 00100bbbaa1100100BBBCCCCCC111110.  */
-{ "prefetchl2", 0x2032003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_RC }, { C_AA8 }},
+{ "prefetchl2", 0x2032003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_AA8 }},
 
 /* prefetchl2<.aa> b,s9 00010bbbssssssssSBBB0aa010111110.  */
-{ "prefetchl2", 0x100000BE, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_SIMM9_8 }, { C_AA21 }},
+{ "prefetchl2", 0x100000BE, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM9_8 }, { C_AA21 }},
 
 /* prefetchl2<.aa> b,limm 00100bbbaa1100100BBB111110111110.  */
-{ "prefetchl2", 0x20320FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_AA8 }},
+{ "prefetchl2", 0x20320FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_AA8 }},
 
 /* prefetchl2 limm,c 00100110RR1100100111CCCCCC111110.  */
-{ "prefetchl2", 0x2632703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "prefetchl2", 0x2632703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* prefetchl2 limm 000101100000000001110RR010111110.  */
-{ "prefetchl2", 0x160070BE, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM }, { 0 }},
+{ "prefetchl2", 0x160070BE, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* prefetchl2 limm,s9 00010110ssssssssS1110RR010111110.  */
-{ "prefetchl2", 0x160070BE, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_SIMM9_8 }, { 0 }},
+{ "prefetchl2", 0x160070BE, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_SIMM9_8 }, { 0 }},
 
 /* prefetchw<.aa> b,c 00100bbbaa1100001BBBCCCCCC111110.  */
-{ "prefetchw", 0x2030803E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }},
+{ "prefetchw", 0x2030803E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }},
 
 /* prefetchw<.aa> b,s9 00010bbbssssssssSBBB1aa000111110.  */
-{ "prefetchw", 0x1000083E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }},
+{ "prefetchw", 0x1000083E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }},
 
 /* prefetchw<.aa> b,limm 00100bbbaa1100001BBB111110111110.  */
-{ "prefetchw", 0x20308FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }},
+{ "prefetchw", 0x20308FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }},
 
 /* prefetchw limm,c 00100110RR1100001111CCCCCC111110.  */
-{ "prefetchw", 0x2630F03E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "prefetchw", 0x2630F03E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* prefetchw limm 000101100000000001111RR000111110.  */
-{ "prefetchw", 0x1600783E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "prefetchw", 0x1600783E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* prefetchw limm,s9 00010110ssssssssS1111RR000111110.  */
-{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }},
+{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }},
 
 /* leave_s u7 11000UUU110uuuu0.  */
 { "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { OPERAND_UIMM7_11_S }, { 0 }},
 
 /* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000.  */
-{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> 0,c 0010011000101111D111CCCCCC010000.  */
-{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000.  */
-{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> 0,u6 0010011001101111D111uuuuuu010000.  */
-{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> b,limm 00100bbb00101111DBBB111110010000.  */
-{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llock<.di> 0,limm 0010011000101111D111111110010000.  */
-{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010.  */
-{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llockd<.di> 0,c 0010011000101111D111CCCCCC010010.  */
-{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llockd<.di> b,u6 00100bbb01101111DBBBuuuuuu010010.  */
-{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llockd<.di> 0,u6 0010011001101111D111uuuuuu010010.  */
-{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llockd<.di> b,limm 00100bbb00101111DBBB111110010010.  */
-{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* llockd<.di> 0,limm 0010011000101111D111111110010010.  */
-{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* lp s13 00100RRR101010000RRRssssssSSSSSS.  */
-{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { OPERAND_SIMM13_A16_20 }, { 0 }},
+{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM13_A16_20 }, { 0 }},
 
 /* lp s13 00100RRR10101000RRRRssssssSSSSSS.  */
-{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_SIMM13_A16_20 }, { 0 }},
+{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, ARC_INSN_SUBCLASS_NONE, { OPERAND_SIMM13_A16_20 }, { 0 }},
 
 /* lp<cc> u7 00100RRR111010000RRRuuuuuu1QQQQQ.  */
-{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { C_CC }},
+{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM7_A16_20 }, { C_CC }},
 
 /* lp u7 00100RRR011010000RRRuuuuuuRRRRRR.  */
-{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { 0 }},
+{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, LOOP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM7_A16_20 }, { 0 }},
 
 /* lp<cc> u7 00100RRR11101000RRRRuuuuuu1QQQQQ.  */
-{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { C_CC }},
+{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM7_A16_20 }, { C_CC }},
 
 /* lp u7 00100RRR01101000RRRRuuuuuuRRRRRR.  */
-{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { 0 }},
+{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM7_A16_20 }, { 0 }},
 
 /* lr b,c 00100bbb001010100BBBCCCCCCRRRRRR.  */
-{ "lr", 0x202A0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x202A0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr 0,c 00100110001010100111CCCCCCRRRRRR.  */
-{ "lr", 0x262A7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x262A7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr b,c 00100bbb00101010RBBBCCCCCCRRRRRR.  */
-{ "lr", 0x202A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x202A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr 0,c 0010011000101010R111CCCCCCRRRRRR.  */
-{ "lr", 0x262A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x262A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr b,u6 00100bbb011010100BBBuuuuuu000000.  */
-{ "lr", 0x206A0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x206A0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr 0,u6 00100110011010100111uuuuuu000000.  */
-{ "lr", 0x266A7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x266A7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr b,u6 00100bbb01101010RBBBuuuuuu000000.  */
-{ "lr", 0x206A0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x206A0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr 0,u6 0010011001101010R111uuuuuu000000.  */
-{ "lr", 0x266A7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x266A7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr b,s12 00100bbb101010100BBBssssssSSSSSS.  */
-{ "lr", 0x20AA0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x20AA0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr 0,s12 00100110101010100111ssssssSSSSSS.  */
-{ "lr", 0x26AA7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x26AA7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr b,s12 00100bbb10101010RBBBssssssSSSSSS.  */
-{ "lr", 0x20AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x20AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr 0,s12 0010011010101010R111ssssssSSSSSS.  */
-{ "lr", 0x26AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x26AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr b,limm 00100bbb001010100BBB111110RRRRRR.  */
-{ "lr", 0x202A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x202A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr 0,limm 00100110001010100111111110RRRRRR.  */
-{ "lr", 0x262A7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x262A7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr b,limm 00100bbb00101010RBBB111110RRRRRR.  */
-{ "lr", 0x202A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x202A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* lr 0,limm 0010011000101010R111111110RRRRRR.  */
-{ "lr", 0x262A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "lr", 0x262A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* lsl16<.f> b,c 00101bbb00101111FBBBCCCCCC001010.  */
 { "lsl16", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -7037,10 +7037,10 @@
 { "lsl8", 0x2E2F7F8F, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* lsr<.f> b,c 00100bbb00101111FBBBCCCCCC000010.  */
-{ "lsr", 0x202F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "lsr", 0x202F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* lsr<.f> 0,c 0010011000101111F111CCCCCC000010.  */
-{ "lsr", 0x262F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "lsr", 0x262F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* lsr<.f> a,b,c 00101bbb00000001FBBBCCCCCCAAAAAA.  */
 { "lsr", 0x28010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -7052,10 +7052,10 @@
 { "lsr", 0x28C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* lsr<.f> b,u6 00100bbb01101111FBBBuuuuuu000010.  */
-{ "lsr", 0x206F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "lsr", 0x206F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* lsr<.f> 0,u6 0010011001101111F111uuuuuu000010.  */
-{ "lsr", 0x266F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "lsr", 0x266F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* lsr<.f> a,b,u6 00101bbb01000001FBBBuuuuuuAAAAAA.  */
 { "lsr", 0x28410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
@@ -7070,10 +7070,10 @@
 { "lsr", 0x28810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* lsr<.f> b,limm 00100bbb00101111FBBB111110000010.  */
-{ "lsr", 0x202F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "lsr", 0x202F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* lsr<.f> 0,limm 0010011000101111F111111110000010.  */
-{ "lsr", 0x262F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "lsr", 0x262F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* lsr<.f> a,limm,c 0010111000000001F111CCCCCCAAAAAA.  */
 { "lsr", 0x2E017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
@@ -7151,67 +7151,67 @@
 { "lsr8", 0x2E2F7F8E, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* lsrdw<.f> a,b,c 00101bbb00100011FBBBCCCCCCAAAAAA.  */
-{ "lsrdw", 0x28230000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "lsrdw", 0x28230000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* lsrdw<.f> 0,b,c 00101bbb00100011FBBBCCCCCC111110.  */
-{ "lsrdw", 0x2823003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "lsrdw", 0x2823003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* lsrdw<.f><.cc> b,b,c 00101bbb11100011FBBBCCCCCC0QQQQQ.  */
-{ "lsrdw", 0x28E30000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "lsrdw", 0x28E30000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* lsrdw<.f> a,b,u6 00101bbb01100011FBBBuuuuuuAAAAAA.  */
-{ "lsrdw", 0x28630000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "lsrdw", 0x28630000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* lsrdw<.f> 0,b,u6 00101bbb01100011FBBBuuuuuu111110.  */
-{ "lsrdw", 0x2863003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "lsrdw", 0x2863003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* lsrdw<.f><.cc> b,b,u6 00101bbb11100011FBBBuuuuuu1QQQQQ.  */
-{ "lsrdw", 0x28E30020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "lsrdw", 0x28E30020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* lsrdw<.f> b,b,s12 00101bbb10100011FBBBssssssSSSSSS.  */
-{ "lsrdw", 0x28A30000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "lsrdw", 0x28A30000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* lsrdw<.f> a,limm,c 0010111000100011F111CCCCCCAAAAAA.  */
-{ "lsrdw", 0x2E237000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "lsrdw", 0x2E237000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* lsrdw<.f> a,b,limm 00101bbb00100011FBBB111110AAAAAA.  */
-{ "lsrdw", 0x28230F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "lsrdw", 0x28230F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* lsrdw<.f> 0,limm,c 0010111000100011F111CCCCCC111110.  */
-{ "lsrdw", 0x2E23703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "lsrdw", 0x2E23703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* lsrdw<.f> 0,b,limm 00101bbb00100011FBBB111110111110.  */
-{ "lsrdw", 0x28230FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "lsrdw", 0x28230FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* lsrdw<.f><.cc> 0,limm,c 0010111011100011F111CCCCCC0QQQQQ.  */
-{ "lsrdw", 0x2EE37000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "lsrdw", 0x2EE37000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* lsrdw<.f><.cc> b,b,limm 00101bbb11100011FBBB1111100QQQQQ.  */
-{ "lsrdw", 0x28E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "lsrdw", 0x28E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* lsrdw<.f> a,limm,u6 0010111001100011F111uuuuuuAAAAAA.  */
-{ "lsrdw", 0x2E637000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "lsrdw", 0x2E637000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* lsrdw<.f> 0,limm,u6 0010111001100011F111uuuuuu111110.  */
-{ "lsrdw", 0x2E63703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "lsrdw", 0x2E63703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* lsrdw<.f><.cc> 0,limm,u6 0010111011100011F111uuuuuu1QQQQQ.  */
-{ "lsrdw", 0x2EE37020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "lsrdw", 0x2EE37020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* lsrdw<.f> 0,limm,s12 0010111010100011F111ssssssSSSSSS.  */
-{ "lsrdw", 0x2EA37000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "lsrdw", 0x2EA37000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* lsrdw<.f> a,limm,limm 0010111000100011F111111110AAAAAA.  */
-{ "lsrdw", 0x2E237F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "lsrdw", 0x2E237F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* lsrdw<.f> 0,limm,limm 0010111000100011F111111110111110.  */
-{ "lsrdw", 0x2E237FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "lsrdw", 0x2E237FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* lsrdw<.f><.cc> 0,limm,limm 0010111011100011F1111111100QQQQQ.  */
-{ "lsrdw", 0x2EE37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "lsrdw", 0x2EE37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* lsr_s b,c 01111bbbccc11101.  */
-{ "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* lsr_s b,b,c 01111bbbccc11001.  */
 { "lsr_s", 0x00007819, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
@@ -7400,544 +7400,544 @@
 { "macdu", 0x2EDB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* macdw<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA.  */
-{ "macdw", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macdw", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macdw<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110.  */
-{ "macdw", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macdw", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macdw<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ.  */
-{ "macdw", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "macdw", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* macdw<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA.  */
-{ "macdw", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macdw", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macdw<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110.  */
-{ "macdw", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macdw", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macdw<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ.  */
-{ "macdw", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macdw", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macdw<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS.  */
-{ "macdw", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "macdw", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macdw<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA.  */
-{ "macdw", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macdw", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macdw<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA.  */
-{ "macdw", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macdw", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macdw<.f> 0,limm,c 0010111000010000F111CCCCCC111110.  */
-{ "macdw", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macdw", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macdw<.f> 0,b,limm 00101bbb00010000FBBB111110111110.  */
-{ "macdw", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macdw", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macdw<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ.  */
-{ "macdw", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "macdw", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* macdw<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ.  */
-{ "macdw", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "macdw", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* macdw<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA.  */
-{ "macdw", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macdw", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macdw<.f> 0,limm,u6 0010111001010000F111uuuuuu111110.  */
-{ "macdw", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macdw", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macdw<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ.  */
-{ "macdw", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macdw", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macdw<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS.  */
-{ "macdw", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "macdw", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macdw<.f> a,limm,limm 0010111000010000F111111110AAAAAA.  */
-{ "macdw", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macdw", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macdw<.f> 0,limm,limm 0010111000010000F111111110111110.  */
-{ "macdw", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macdw", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macdw<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ.  */
-{ "macdw", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "macdw", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* macflw<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA.  */
-{ "macflw", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macflw", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macflw<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110.  */
-{ "macflw", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macflw", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macflw<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ.  */
-{ "macflw", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "macflw", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* macflw<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA.  */
-{ "macflw", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macflw", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macflw<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110.  */
-{ "macflw", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macflw", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macflw<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ.  */
-{ "macflw", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macflw", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macflw<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS.  */
-{ "macflw", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "macflw", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macflw<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA.  */
-{ "macflw", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macflw", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macflw<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA.  */
-{ "macflw", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macflw", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macflw<.f> 0,limm,c 0010111000110100F111CCCCCC111110.  */
-{ "macflw", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macflw", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macflw<.f> 0,b,limm 00101bbb00110100FBBB111110111110.  */
-{ "macflw", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macflw", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macflw<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ.  */
-{ "macflw", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "macflw", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* macflw<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ.  */
-{ "macflw", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "macflw", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* macflw<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA.  */
-{ "macflw", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macflw", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macflw<.f> 0,limm,u6 0010111001110100F111uuuuuu111110.  */
-{ "macflw", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macflw", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macflw<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ.  */
-{ "macflw", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macflw", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macflw<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS.  */
-{ "macflw", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "macflw", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macflw<.f> a,limm,limm 0010111000110100F111111110AAAAAA.  */
-{ "macflw", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macflw", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macflw<.f> 0,limm,limm 0010111000110100F111111110111110.  */
-{ "macflw", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macflw", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macflw<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ.  */
-{ "macflw", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "macflw", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* machflw<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA.  */
-{ "machflw", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "machflw", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* machflw<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110.  */
-{ "machflw", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "machflw", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* machflw<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ.  */
-{ "machflw", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "machflw", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* machflw<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA.  */
-{ "machflw", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "machflw", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machflw<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110.  */
-{ "machflw", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "machflw", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machflw<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ.  */
-{ "machflw", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "machflw", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* machflw<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS.  */
-{ "machflw", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "machflw", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* machflw<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA.  */
-{ "machflw", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "machflw", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* machflw<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA.  */
-{ "machflw", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "machflw", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* machflw<.f> 0,limm,c 0010111000110111F111CCCCCC111110.  */
-{ "machflw", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "machflw", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* machflw<.f> 0,b,limm 00101bbb00110111FBBB111110111110.  */
-{ "machflw", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "machflw", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* machflw<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ.  */
-{ "machflw", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "machflw", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* machflw<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ.  */
-{ "machflw", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "machflw", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* machflw<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA.  */
-{ "machflw", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "machflw", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machflw<.f> 0,limm,u6 0010111001110111F111uuuuuu111110.  */
-{ "machflw", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "machflw", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machflw<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ.  */
-{ "machflw", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "machflw", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* machflw<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS.  */
-{ "machflw", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "machflw", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* machflw<.f> a,limm,limm 0010111000110111F111111110AAAAAA.  */
-{ "machflw", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "machflw", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* machflw<.f> 0,limm,limm 0010111000110111F111111110111110.  */
-{ "machflw", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "machflw", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* machflw<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ.  */
-{ "machflw", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "machflw", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* machlw<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA.  */
-{ "machlw", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "machlw", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* machlw<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110.  */
-{ "machlw", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "machlw", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* machlw<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ.  */
-{ "machlw", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "machlw", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* machlw<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA.  */
-{ "machlw", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "machlw", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machlw<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110.  */
-{ "machlw", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "machlw", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machlw<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ.  */
-{ "machlw", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "machlw", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* machlw<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS.  */
-{ "machlw", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "machlw", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* machlw<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA.  */
-{ "machlw", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "machlw", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* machlw<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA.  */
-{ "machlw", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "machlw", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* machlw<.f> 0,limm,c 0010111000110110F111CCCCCC111110.  */
-{ "machlw", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "machlw", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* machlw<.f> 0,b,limm 00101bbb00110110FBBB111110111110.  */
-{ "machlw", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "machlw", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* machlw<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ.  */
-{ "machlw", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "machlw", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* machlw<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ.  */
-{ "machlw", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "machlw", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* machlw<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA.  */
-{ "machlw", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "machlw", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machlw<.f> 0,limm,u6 0010111001110110F111uuuuuu111110.  */
-{ "machlw", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "machlw", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machlw<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ.  */
-{ "machlw", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "machlw", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* machlw<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS.  */
-{ "machlw", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "machlw", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* machlw<.f> a,limm,limm 0010111000110110F111111110AAAAAA.  */
-{ "machlw", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "machlw", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* machlw<.f> 0,limm,limm 0010111000110110F111111110111110.  */
-{ "machlw", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "machlw", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* machlw<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ.  */
-{ "machlw", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "machlw", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* machulw<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA.  */
-{ "machulw", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "machulw", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* machulw<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110.  */
-{ "machulw", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "machulw", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* machulw<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ.  */
-{ "machulw", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "machulw", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* machulw<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA.  */
-{ "machulw", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "machulw", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machulw<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110.  */
-{ "machulw", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "machulw", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machulw<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ.  */
-{ "machulw", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "machulw", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* machulw<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS.  */
-{ "machulw", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "machulw", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* machulw<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA.  */
-{ "machulw", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "machulw", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* machulw<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA.  */
-{ "machulw", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "machulw", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* machulw<.f> 0,limm,c 0010111000110101F111CCCCCC111110.  */
-{ "machulw", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "machulw", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* machulw<.f> 0,b,limm 00101bbb00110101FBBB111110111110.  */
-{ "machulw", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "machulw", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* machulw<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ.  */
-{ "machulw", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "machulw", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* machulw<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ.  */
-{ "machulw", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "machulw", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* machulw<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA.  */
-{ "machulw", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "machulw", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machulw<.f> 0,limm,u6 0010111001110101F111uuuuuu111110.  */
-{ "machulw", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "machulw", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* machulw<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ.  */
-{ "machulw", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "machulw", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* machulw<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS.  */
-{ "machulw", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "machulw", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* machulw<.f> a,limm,limm 0010111000110101F111111110AAAAAA.  */
-{ "machulw", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "machulw", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* machulw<.f> 0,limm,limm 0010111000110101F111111110111110.  */
-{ "machulw", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "machulw", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* machulw<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ.  */
-{ "machulw", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "machulw", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* maclw<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA.  */
-{ "maclw", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "maclw", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* maclw<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110.  */
-{ "maclw", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "maclw", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* maclw<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ.  */
-{ "maclw", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "maclw", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* maclw<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA.  */
-{ "maclw", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "maclw", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maclw<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110.  */
-{ "maclw", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "maclw", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maclw<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ.  */
-{ "maclw", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "maclw", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* maclw<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS.  */
-{ "maclw", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "maclw", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* maclw<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA.  */
-{ "maclw", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "maclw", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* maclw<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA.  */
-{ "maclw", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "maclw", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* maclw<.f> 0,limm,c 0010111000110011F111CCCCCC111110.  */
-{ "maclw", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "maclw", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* maclw<.f> 0,b,limm 00101bbb00110011FBBB111110111110.  */
-{ "maclw", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "maclw", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* maclw<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ.  */
-{ "maclw", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "maclw", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* maclw<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ.  */
-{ "maclw", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "maclw", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* maclw<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA.  */
-{ "maclw", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "maclw", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maclw<.f> 0,limm,u6 0010111001110011F111uuuuuu111110.  */
-{ "maclw", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "maclw", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maclw<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ.  */
-{ "maclw", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "maclw", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* maclw<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS.  */
-{ "maclw", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "maclw", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* maclw<.f> a,limm,limm 0010111000110011F111111110AAAAAA.  */
-{ "maclw", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "maclw", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* maclw<.f> 0,limm,limm 0010111000110011F111111110111110.  */
-{ "maclw", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "maclw", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* maclw<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ.  */
-{ "maclw", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "maclw", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* macrdw<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA.  */
-{ "macrdw", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macrdw", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macrdw<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110.  */
-{ "macrdw", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macrdw", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macrdw<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ.  */
-{ "macrdw", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "macrdw", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* macrdw<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA.  */
-{ "macrdw", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macrdw", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macrdw<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110.  */
-{ "macrdw", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macrdw", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macrdw<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ.  */
-{ "macrdw", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macrdw", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macrdw<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS.  */
-{ "macrdw", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "macrdw", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macrdw<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA.  */
-{ "macrdw", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macrdw", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macrdw<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA.  */
-{ "macrdw", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macrdw", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macrdw<.f> 0,limm,c 0010111000010010F111CCCCCC111110.  */
-{ "macrdw", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macrdw", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macrdw<.f> 0,b,limm 00101bbb00010010FBBB111110111110.  */
-{ "macrdw", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macrdw", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macrdw<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ.  */
-{ "macrdw", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "macrdw", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* macrdw<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ.  */
-{ "macrdw", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "macrdw", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* macrdw<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA.  */
-{ "macrdw", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macrdw", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macrdw<.f> 0,limm,u6 0010111001010010F111uuuuuu111110.  */
-{ "macrdw", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macrdw", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macrdw<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ.  */
-{ "macrdw", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macrdw", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macrdw<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS.  */
-{ "macrdw", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "macrdw", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macrdw<.f> a,limm,limm 0010111000010010F111111110AAAAAA.  */
-{ "macrdw", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macrdw", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macrdw<.f> 0,limm,limm 0010111000010010F111111110111110.  */
-{ "macrdw", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macrdw", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macrdw<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ.  */
-{ "macrdw", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "macrdw", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* macrt<.f> a,b,c 00101bbb00011110FBBBCCCCCCAAAAAA.  */
-{ "macrt", 0x281E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macrt", 0x281E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macrt<.f> 0,b,c 00101bbb00011110FBBBCCCCCC111110.  */
-{ "macrt", 0x281E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macrt", 0x281E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macrt<.f><.cc> b,b,c 00101bbb11011110FBBBCCCCCC0QQQQQ.  */
-{ "macrt", 0x28DE0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "macrt", 0x28DE0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* macrt<.f> a,b,u6 00101bbb01011110FBBBuuuuuuAAAAAA.  */
-{ "macrt", 0x285E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macrt", 0x285E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macrt<.f> 0,b,u6 00101bbb01011110FBBBuuuuuu111110.  */
-{ "macrt", 0x285E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macrt", 0x285E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macrt<.f><.cc> b,b,u6 00101bbb11011110FBBBuuuuuu1QQQQQ.  */
-{ "macrt", 0x28DE0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macrt", 0x28DE0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macrt<.f> b,b,s12 00101bbb10011110FBBBssssssSSSSSS.  */
-{ "macrt", 0x289E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "macrt", 0x289E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macrt<.f> a,limm,c 0010111000011110F111CCCCCCAAAAAA.  */
-{ "macrt", 0x2E1E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macrt", 0x2E1E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macrt<.f> a,b,limm 00101bbb00011110FBBB111110AAAAAA.  */
-{ "macrt", 0x281E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macrt", 0x281E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macrt<.f> 0,limm,c 0010111000011110F111CCCCCC111110.  */
-{ "macrt", 0x2E1E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macrt", 0x2E1E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macrt<.f> 0,b,limm 00101bbb00011110FBBB111110111110.  */
-{ "macrt", 0x281E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macrt", 0x281E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macrt<.f><.cc> 0,limm,c 0010111011011110F111CCCCCC0QQQQQ.  */
-{ "macrt", 0x2EDE7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "macrt", 0x2EDE7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* macrt<.f><.cc> b,b,limm 00101bbb11011110FBBB1111100QQQQQ.  */
-{ "macrt", 0x28DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "macrt", 0x28DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* macrt<.f> a,limm,u6 0010111001011110F111uuuuuuAAAAAA.  */
-{ "macrt", 0x2E5E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macrt", 0x2E5E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macrt<.f> 0,limm,u6 0010111001011110F111uuuuuu111110.  */
-{ "macrt", 0x2E5E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macrt", 0x2E5E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macrt<.f><.cc> 0,limm,u6 0010111011011110F111uuuuuu1QQQQQ.  */
-{ "macrt", 0x2EDE7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macrt", 0x2EDE7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macrt<.f> 0,limm,s12 0010111010011110F111ssssssSSSSSS.  */
-{ "macrt", 0x2E9E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "macrt", 0x2E9E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macrt<.f> a,limm,limm 0010111000011110F111111110AAAAAA.  */
-{ "macrt", 0x2E1E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macrt", 0x2E1E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macrt<.f> 0,limm,limm 0010111000011110F111111110111110.  */
-{ "macrt", 0x2E1E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macrt", 0x2E1E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macrt<.f><.cc> 0,limm,limm 0010111011011110F1111111100QQQQQ.  */
-{ "macrt", 0x2EDE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "macrt", 0x2EDE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mact<.f> a,b,c 00101bbb00011100FBBBCCCCCCAAAAAA.  */
-{ "mact", 0x281C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mact", 0x281C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mact<.f> 0,b,c 00101bbb00011100FBBBCCCCCC111110.  */
-{ "mact", 0x281C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mact", 0x281C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mact<.f><.cc> b,b,c 00101bbb11011100FBBBCCCCCC0QQQQQ.  */
-{ "mact", 0x28DC0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mact", 0x28DC0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mact<.f> a,b,u6 00101bbb01011100FBBBuuuuuuAAAAAA.  */
-{ "mact", 0x285C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mact", 0x285C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mact<.f> 0,b,u6 00101bbb01011100FBBBuuuuuu111110.  */
-{ "mact", 0x285C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mact", 0x285C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mact<.f><.cc> b,b,u6 00101bbb11011100FBBBuuuuuu1QQQQQ.  */
-{ "mact", 0x28DC0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mact", 0x28DC0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mact<.f> b,b,s12 00101bbb10011100FBBBssssssSSSSSS.  */
-{ "mact", 0x289C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mact", 0x289C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mact<.f> a,limm,c 0010111000011100F111CCCCCCAAAAAA.  */
-{ "mact", 0x2E1C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mact", 0x2E1C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mact<.f> a,b,limm 00101bbb00011100FBBB111110AAAAAA.  */
-{ "mact", 0x281C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mact", 0x281C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mact<.f> 0,limm,c 0010111000011100F111CCCCCC111110.  */
-{ "mact", 0x2E1C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mact", 0x2E1C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mact<.f> 0,b,limm 00101bbb00011100FBBB111110111110.  */
-{ "mact", 0x281C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mact", 0x281C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mact<.f><.cc> 0,limm,c 0010111011011100F111CCCCCC0QQQQQ.  */
-{ "mact", 0x2EDC7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mact", 0x2EDC7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mact<.f><.cc> b,b,limm 00101bbb11011100FBBB1111100QQQQQ.  */
-{ "mact", 0x28DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mact", 0x28DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mact<.f> a,limm,u6 0010111001011100F111uuuuuuAAAAAA.  */
-{ "mact", 0x2E5C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mact", 0x2E5C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mact<.f> 0,limm,u6 0010111001011100F111uuuuuu111110.  */
-{ "mact", 0x2E5C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mact", 0x2E5C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mact<.f><.cc> 0,limm,u6 0010111011011100F111uuuuuu1QQQQQ.  */
-{ "mact", 0x2EDC7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mact", 0x2EDC7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mact<.f> 0,limm,s12 0010111010011100F111ssssssSSSSSS.  */
-{ "mact", 0x2E9C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mact", 0x2E9C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mact<.f> a,limm,limm 0010111000011100F111111110AAAAAA.  */
-{ "mact", 0x2E1C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mact", 0x2E1C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mact<.f> 0,limm,limm 0010111000011100F111111110111110.  */
-{ "mact", 0x2E1C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mact", 0x2E1C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mact<.f><.cc> 0,limm,limm 0010111011011100F1111111100QQQQQ.  */
-{ "mact", 0x2EDC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mact", 0x2EDC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* macu<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA.  */
 { "macu", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -8000,448 +8000,448 @@
 { "macu", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* macudw<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA.  */
-{ "macudw", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macudw", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macudw<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110.  */
-{ "macudw", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "macudw", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* macudw<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ.  */
-{ "macudw", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "macudw", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* macudw<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA.  */
-{ "macudw", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macudw", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macudw<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110.  */
-{ "macudw", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "macudw", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macudw<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ.  */
-{ "macudw", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macudw", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macudw<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS.  */
-{ "macudw", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "macudw", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macudw<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA.  */
-{ "macudw", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macudw", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macudw<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA.  */
-{ "macudw", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macudw", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macudw<.f> 0,limm,c 0010111000010001F111CCCCCC111110.  */
-{ "macudw", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "macudw", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* macudw<.f> 0,b,limm 00101bbb00010001FBBB111110111110.  */
-{ "macudw", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "macudw", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* macudw<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ.  */
-{ "macudw", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "macudw", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* macudw<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ.  */
-{ "macudw", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "macudw", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* macudw<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA.  */
-{ "macudw", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macudw", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macudw<.f> 0,limm,u6 0010111001010001F111uuuuuu111110.  */
-{ "macudw", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "macudw", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* macudw<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ.  */
-{ "macudw", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "macudw", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* macudw<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS.  */
-{ "macudw", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "macudw", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* macudw<.f> a,limm,limm 0010111000010001F111111110AAAAAA.  */
-{ "macudw", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macudw", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macudw<.f> 0,limm,limm 0010111000010001F111111110111110.  */
-{ "macudw", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "macudw", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* macudw<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ.  */
-{ "macudw", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "macudw", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* max<.f> a,b,c 00100bbb00001000FBBBCCCCCCAAAAAA.  */
-{ "max", 0x20080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "max", 0x20080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* max<.f> 0,b,c 00100bbb00001000FBBBCCCCCC111110.  */
-{ "max", 0x2008003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "max", 0x2008003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* max<.f><.cc> b,b,c 00100bbb11001000FBBBCCCCCC0QQQQQ.  */
-{ "max", 0x20C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "max", 0x20C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* max<.f> a,b,u6 00100bbb01001000FBBBuuuuuuAAAAAA.  */
-{ "max", 0x20480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "max", 0x20480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* max<.f> 0,b,u6 00100bbb01001000FBBBuuuuuu111110.  */
-{ "max", 0x2048003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "max", 0x2048003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* max<.f><.cc> b,b,u6 00100bbb11001000FBBBuuuuuu1QQQQQ.  */
-{ "max", 0x20C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "max", 0x20C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* max<.f> b,b,s12 00100bbb10001000FBBBssssssSSSSSS.  */
-{ "max", 0x20880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "max", 0x20880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* max<.f> a,limm,c 0010011000001000F111CCCCCCAAAAAA.  */
-{ "max", 0x26087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "max", 0x26087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* max<.f> a,b,limm 00100bbb00001000FBBB111110AAAAAA.  */
-{ "max", 0x20080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "max", 0x20080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* max<.f> 0,limm,c 0010011000001000F111CCCCCC111110.  */
-{ "max", 0x2608703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "max", 0x2608703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* max<.f> 0,b,limm 00100bbb00001000FBBB111110111110.  */
-{ "max", 0x20080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "max", 0x20080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* max<.f><.cc> b,b,limm 00100bbb11001000FBBB1111100QQQQQ.  */
-{ "max", 0x20C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "max", 0x20C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* max<.f><.cc> 0,limm,c 0010011011001000F111CCCCCC0QQQQQ.  */
-{ "max", 0x26C87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "max", 0x26C87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* max<.f> a,limm,u6 0010011001001000F111uuuuuuAAAAAA.  */
-{ "max", 0x26487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "max", 0x26487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* max<.f> 0,limm,u6 0010011001001000F111uuuuuu111110.  */
-{ "max", 0x2648703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "max", 0x2648703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* max<.f><.cc> 0,limm,u6 0010011011001000F111uuuuuu1QQQQQ.  */
-{ "max", 0x26C87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "max", 0x26C87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* max<.f> 0,limm,s12 0010011010001000F111ssssssSSSSSS.  */
-{ "max", 0x26887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "max", 0x26887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* max<.f> a,limm,limm 0010011000001000F111111110AAAAAA.  */
-{ "max", 0x26087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "max", 0x26087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* max<.f> 0,limm,limm 0010011000001000F111111110111110.  */
-{ "max", 0x26087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "max", 0x26087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* max<.f><.cc> 0,limm,limm 0010011011001000F1111111100QQQQQ.  */
-{ "max", 0x26C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "max", 0x26C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* maxabssdw<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA.  */
-{ "maxabssdw", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "maxabssdw", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* maxabssdw<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110.  */
-{ "maxabssdw", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "maxabssdw", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* maxabssdw<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ.  */
-{ "maxabssdw", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "maxabssdw", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* maxabssdw<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA.  */
-{ "maxabssdw", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "maxabssdw", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maxabssdw<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110.  */
-{ "maxabssdw", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "maxabssdw", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maxabssdw<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ.  */
-{ "maxabssdw", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "maxabssdw", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* maxabssdw<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS.  */
-{ "maxabssdw", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "maxabssdw", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* maxabssdw<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA.  */
-{ "maxabssdw", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "maxabssdw", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* maxabssdw<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA.  */
-{ "maxabssdw", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "maxabssdw", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* maxabssdw<.f> 0,limm,c 0010111000101011F111CCCCCC111110.  */
-{ "maxabssdw", 0x2E2B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "maxabssdw", 0x2E2B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* maxabssdw<.f> 0,b,limm 00101bbb00101011FBBB111110111110.  */
-{ "maxabssdw", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "maxabssdw", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* maxabssdw<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ.  */
-{ "maxabssdw", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "maxabssdw", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* maxabssdw<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ.  */
-{ "maxabssdw", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "maxabssdw", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* maxabssdw<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA.  */
-{ "maxabssdw", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "maxabssdw", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maxabssdw<.f> 0,limm,u6 0010111001101011F111uuuuuu111110.  */
-{ "maxabssdw", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "maxabssdw", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maxabssdw<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ.  */
-{ "maxabssdw", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "maxabssdw", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* maxabssdw<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS.  */
-{ "maxabssdw", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "maxabssdw", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* maxabssdw<.f> a,limm,limm 0010111000101011F111111110AAAAAA.  */
-{ "maxabssdw", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "maxabssdw", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* maxabssdw<.f> 0,limm,limm 0010111000101011F111111110111110.  */
-{ "maxabssdw", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "maxabssdw", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* maxabssdw<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ.  */
-{ "maxabssdw", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "maxabssdw", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* maxidl<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA.  */
-{ "maxidl", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "maxidl", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* maxidl<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110.  */
-{ "maxidl", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "maxidl", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* maxidl<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ.  */
-{ "maxidl", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "maxidl", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* maxidl<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA.  */
-{ "maxidl", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "maxidl", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maxidl<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110.  */
-{ "maxidl", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "maxidl", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maxidl<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ.  */
-{ "maxidl", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "maxidl", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* maxidl<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS.  */
-{ "maxidl", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "maxidl", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* maxidl<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA.  */
-{ "maxidl", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "maxidl", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* maxidl<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA.  */
-{ "maxidl", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "maxidl", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* maxidl<.f> 0,limm,c 0010111000001111F111CCCCCC111110.  */
-{ "maxidl", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "maxidl", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* maxidl<.f> 0,b,limm 00101bbb00001111FBBB111110111110.  */
-{ "maxidl", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "maxidl", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* maxidl<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ.  */
-{ "maxidl", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "maxidl", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* maxidl<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ.  */
-{ "maxidl", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "maxidl", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* maxidl<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA.  */
-{ "maxidl", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "maxidl", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maxidl<.f> 0,limm,u6 0010111001001111F111uuuuuu111110.  */
-{ "maxidl", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "maxidl", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* maxidl<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ.  */
-{ "maxidl", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "maxidl", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* maxidl<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS.  */
-{ "maxidl", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "maxidl", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* maxidl<.f> a,limm,limm 0010111000001111F111111110AAAAAA.  */
-{ "maxidl", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "maxidl", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* maxidl<.f> 0,limm,limm 0010111000001111F111111110111110.  */
-{ "maxidl", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "maxidl", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* maxidl<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ.  */
-{ "maxidl", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "maxidl", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* min<.f> a,b,c 00100bbb00001001FBBBCCCCCCAAAAAA.  */
-{ "min", 0x20090000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "min", 0x20090000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* min<.f> 0,b,c 00100bbb00001001FBBBCCCCCC111110.  */
-{ "min", 0x2009003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "min", 0x2009003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* min<.f><.cc> b,b,c 00100bbb11001001FBBBCCCCCC0QQQQQ.  */
-{ "min", 0x20C90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "min", 0x20C90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* min<.f> a,b,u6 00100bbb01001001FBBBuuuuuuAAAAAA.  */
-{ "min", 0x20490000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "min", 0x20490000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* min<.f> 0,b,u6 00100bbb01001001FBBBuuuuuu111110.  */
-{ "min", 0x2049003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "min", 0x2049003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* min<.f><.cc> b,b,u6 00100bbb11001001FBBBuuuuuu1QQQQQ.  */
-{ "min", 0x20C90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "min", 0x20C90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* min<.f> b,b,s12 00100bbb10001001FBBBssssssSSSSSS.  */
-{ "min", 0x20890000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "min", 0x20890000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* min<.f> a,limm,c 0010011000001001F111CCCCCCAAAAAA.  */
-{ "min", 0x26097000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "min", 0x26097000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* min<.f> a,b,limm 00100bbb00001001FBBB111110AAAAAA.  */
-{ "min", 0x20090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "min", 0x20090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* min<.f> 0,limm,c 0010011000001001F111CCCCCC111110.  */
-{ "min", 0x2609703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "min", 0x2609703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* min<.f> 0,b,limm 00100bbb00001001FBBB111110111110.  */
-{ "min", 0x20090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "min", 0x20090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* min<.f><.cc> b,b,limm 00100bbb11001001FBBB1111100QQQQQ.  */
-{ "min", 0x20C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "min", 0x20C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* min<.f><.cc> 0,limm,c 0010011011001001F111CCCCCC0QQQQQ.  */
-{ "min", 0x26C97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "min", 0x26C97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* min<.f> a,limm,u6 0010011001001001F111uuuuuuAAAAAA.  */
-{ "min", 0x26497000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "min", 0x26497000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* min<.f> 0,limm,u6 0010011001001001F111uuuuuu111110.  */
-{ "min", 0x2649703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "min", 0x2649703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* min<.f><.cc> 0,limm,u6 0010011011001001F111uuuuuu1QQQQQ.  */
-{ "min", 0x26C97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "min", 0x26C97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* min<.f> 0,limm,s12 0010011010001001F111ssssssSSSSSS.  */
-{ "min", 0x26897000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "min", 0x26897000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* min<.f> a,limm,limm 0010011000001001F111111110AAAAAA.  */
-{ "min", 0x26097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "min", 0x26097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* min<.f> 0,limm,limm 0010011000001001F111111110111110.  */
-{ "min", 0x26097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "min", 0x26097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* min<.f><.cc> 0,limm,limm 0010011011001001F1111111100QQQQQ.  */
-{ "min", 0x26C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "min", 0x26C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* minidl<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA.  */
-{ "minidl", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "minidl", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* minidl<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110.  */
-{ "minidl", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "minidl", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* minidl<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ.  */
-{ "minidl", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "minidl", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* minidl<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA.  */
-{ "minidl", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "minidl", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* minidl<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110.  */
-{ "minidl", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "minidl", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* minidl<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ.  */
-{ "minidl", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "minidl", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* minidl<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS.  */
-{ "minidl", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "minidl", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* minidl<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA.  */
-{ "minidl", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "minidl", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* minidl<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA.  */
-{ "minidl", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "minidl", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* minidl<.f> 0,limm,c 0010111000001001F111CCCCCC111110.  */
-{ "minidl", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "minidl", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* minidl<.f> 0,b,limm 00101bbb00001001FBBB111110111110.  */
-{ "minidl", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "minidl", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* minidl<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ.  */
-{ "minidl", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "minidl", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* minidl<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ.  */
-{ "minidl", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "minidl", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* minidl<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA.  */
-{ "minidl", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "minidl", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* minidl<.f> 0,limm,u6 0010111001001001F111uuuuuu111110.  */
-{ "minidl", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "minidl", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* minidl<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ.  */
-{ "minidl", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "minidl", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* minidl<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS.  */
-{ "minidl", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "minidl", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* minidl<.f> a,limm,limm 0010111000001001F111111110AAAAAA.  */
-{ "minidl", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "minidl", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* minidl<.f> 0,limm,limm 0010111000001001F111111110111110.  */
-{ "minidl", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "minidl", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ.  */
-{ "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* nop  00100110010010100111000000000000.  */
-{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR.  */
-{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mov<.f> 0,c 0010011000001010F111CCCCCCRRRRRR.  */
-{ "mov", 0x260A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "mov", 0x260A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* mov<.f><.cc> b,c 00100bbb11001010FBBBCCCCCC0QQQQQ.  */
-{ "mov", 0x20CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_RC }, { C_F, C_CC }},
+{ "mov", 0x20CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F, C_CC }},
 
 /* mov<.f><.cc> 0,c 0010011011001010F111CCCCCC0QQQQQ.  */
-{ "mov", 0x26CA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F, C_CC }},
+{ "mov", 0x26CA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F, C_CC }},
 
 /* mov<.f> b,u6 00100bbb01001010FBBBuuuuuuRRRRRR.  */
-{ "mov", 0x204A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mov", 0x204A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mov<.f> 0,u6 0010011001001010F111uuuuuuRRRRRR.  */
-{ "mov", 0x264A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "mov", 0x264A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.  */
-{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mov<.f><.cc> 0,u6 0010011011001010F111uuuuuu1QQQQQ.  */
-{ "mov", 0x26CA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mov", 0x26CA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS.  */
-{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { C_F }},
+{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mov<.f> 0,s12 0010011010001010F111ssssssSSSSSS.  */
-{ "mov", 0x268A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_SIMM12_20 }, { C_F }},
+{ "mov", 0x268A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR.  */
-{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mov<.f> 0,limm 0010011000001010F111111110RRRRRR.  */
-{ "mov", 0x260A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "mov", 0x260A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ.  */
-{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mov<.f><.cc> 0,limm 0010011011001010F1111111100QQQQQ.  */
-{ "mov", 0x26CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mov", 0x26CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mov_s b,h 01110bbbhhh01HHH.  */
-{ "mov_s", 0x00007008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_RB_S, OPERAND_R6H }, { 0 }},
+{ "mov_s", 0x00007008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_R6H }, { 0 }},
 
 /* mov_s h,b 01110bbbhhh11HHH.  */
-{ "mov_s", 0x00007018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_R6H, OPERAND_RB_S }, { 0 }},
+{ "mov_s", 0x00007018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_R6H, OPERAND_RB_S }, { 0 }},
 
 /* mov_s 0,b 01110bbb1101111H.  */
-{ "mov_s", 0x000070DE, 0x0000F8FE, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RB_S }, { 0 }},
+{ "mov_s", 0x000070DE, 0x0000F8FE, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA_S, OPERAND_RB_S }, { 0 }},
 
 /* mov_s g,h 01000ggghhhGG0HH.  */
-{ "mov_s", 0x00004000, 0x0000F804, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_G_S, OPERAND_RH_S }, { 0 }},
+{ "mov_s", 0x00004000, 0x0000F804, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_G_S, OPERAND_RH_S }, { 0 }},
 
 /* mov_s 0,h 01000110hhh110HH.  */
-{ "mov_s", 0x00004618, 0x0000FF1C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RH_S }, { 0 }},
+{ "mov_s", 0x00004618, 0x0000FF1C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA_S, OPERAND_RH_S }, { 0 }},
 
 /* mov_s h,s3 01110ssshhh011HH.  */
-{ "mov_s", 0x0000700C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }},
+{ "mov_s", 0x0000700C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }},
 
 /* mov_s 0,s3 01110sss11001111.  */
-{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_SIMM3_5_S }, { 0 }},
+{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA_S, OPERAND_SIMM3_5_S }, { 0 }},
 
 /* mov_s b,u8 11011bbbuuuuuuuu.  */
-{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_UIMM8_8_S }, { 0 }},
+{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_UIMM8_8_S }, { 0 }},
 
 /* mov_s b,limm 01110bbb11001111.  */
-{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }},
+{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }},
 
 /* mov_s g,limm 01000ggg110GG011.  */
-{ "mov_s", 0x000040C3, 0x0000F8E7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_G_S, OPERAND_LIMM_S }, { 0 }},
+{ "mov_s", 0x000040C3, 0x0000F8E7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_G_S, OPERAND_LIMM_S }, { 0 }},
 
 /* mov_s 0,limm 0100011011011011.  */
-{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_LIMM_S }, { 0 }},
+{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA_S, OPERAND_LIMM_S }, { 0 }},
 
 /* mov_s.ne b,h 01110bbbhhh111HH.  */
-{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { C_NE, C_CC_NE }},
+{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RH_S }, { C_NE, C_CC_NE }},
 
 /* mov_s.ne b,limm 01110bbb11011111.  */
-{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { C_NE, C_CC_NE }},
+{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { C_NE, C_CC_NE }},
 
 /* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA.  */
 { "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -8624,124 +8624,124 @@
 { "mpydu", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mpyh<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA.  */
-{ "mpyh", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mpyh", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mpyh<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110.  */
-{ "mpyh", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mpyh", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mpyh<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ.  */
-{ "mpyh", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyh", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyh<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA.  */
-{ "mpyh", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyh", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyh<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110.  */
-{ "mpyh", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyh", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyh<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ.  */
-{ "mpyh", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyh", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyh<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS.  */
-{ "mpyh", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyh", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyh<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA.  */
-{ "mpyh", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyh", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyh<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA.  */
-{ "mpyh", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyh", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyh<.f> 0,limm,c 0010011000011011F111CCCCCC111110.  */
-{ "mpyh", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyh", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyh<.f> 0,b,limm 00100bbb00011011FBBB111110111110.  */
-{ "mpyh", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyh", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyh<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ.  */
-{ "mpyh", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mpyh", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mpyh<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ.  */
-{ "mpyh", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyh", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyh<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA.  */
-{ "mpyh", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyh", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyh<.f> 0,limm,u6 0010011001011011F111uuuuuu111110.  */
-{ "mpyh", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyh", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyh<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ.  */
-{ "mpyh", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyh", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyh<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS.  */
-{ "mpyh", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyh", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyh<.f> a,limm,limm 0010011000011011F111111110AAAAAA.  */
-{ "mpyh", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mpyh", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mpyh<.f> 0,limm,limm 0010011000011011F111111110111110.  */
-{ "mpyh", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mpyh", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mpyh<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ.  */
-{ "mpyh", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mpyh", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mpyhu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA.  */
-{ "mpyhu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mpyhu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mpyhu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110.  */
-{ "mpyhu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mpyhu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mpyhu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ.  */
-{ "mpyhu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyhu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyhu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA.  */
-{ "mpyhu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyhu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyhu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110.  */
-{ "mpyhu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyhu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyhu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ.  */
-{ "mpyhu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyhu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyhu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS.  */
-{ "mpyhu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyhu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyhu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA.  */
-{ "mpyhu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyhu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyhu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA.  */
-{ "mpyhu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyhu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyhu<.f> 0,limm,c 0010011000011100F111CCCCCC111110.  */
-{ "mpyhu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyhu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyhu<.f> 0,b,limm 00100bbb00011100FBBB111110111110.  */
-{ "mpyhu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyhu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyhu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ.  */
-{ "mpyhu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mpyhu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mpyhu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ.  */
-{ "mpyhu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyhu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyhu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA.  */
-{ "mpyhu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyhu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyhu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110.  */
-{ "mpyhu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyhu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyhu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ.  */
-{ "mpyhu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyhu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyhu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS.  */
-{ "mpyhu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyhu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyhu<.f> a,limm,limm 0010011000011100F111111110AAAAAA.  */
-{ "mpyhu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mpyhu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mpyhu<.f> 0,limm,limm 0010011000011100F111111110111110.  */
-{ "mpyhu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mpyhu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mpyhu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ.  */
-{ "mpyhu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mpyhu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mpym<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA.  */
 { "mpym", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -8864,25 +8864,25 @@
 { "mpymu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mpyqb<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ.  */
-{ "mpyqb", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyqb", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyqb<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA.  */
-{ "mpyqb", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyqb", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyqb<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ.  */
-{ "mpyqb", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyqb", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyqb<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS.  */
-{ "mpyqb", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyqb", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyqb<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA.  */
-{ "mpyqb", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyqb", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyqb<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA.  */
-{ "mpyqb", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyqb", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyqb<.f><.cc> b,b,limm 00110bbb11100101FBBB1111100QQQQQ.  */
-{ "mpyqb", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mpyqb", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mpyu<.f> a,b,c 00100bbb00011101FBBBCCCCCCAAAAAA.  */
 { "mpyu", 0x201D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -8945,13 +8945,13 @@
 { "mpyu", 0x26DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mpyuw<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA.  */
-{ "mpyuw", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mpyuw", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mpyuw<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110.  */
-{ "mpyuw", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mpyuw", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mpyuw<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ.  */
-{ "mpyuw", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyuw", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyuw<.f> a,b,c 00100bbb00011111FBBBCCCCCCAAAAAA.  */
 { "mpyuw", 0x201F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -8963,13 +8963,13 @@
 { "mpyuw", 0x20DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyuw<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA.  */
-{ "mpyuw", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyuw", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyuw<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110.  */
-{ "mpyuw", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyuw", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyuw<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ.  */
-{ "mpyuw", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyuw", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyuw<.f> a,b,u6 00100bbb01011111FBBBuuuuuuAAAAAA.  */
 { "mpyuw", 0x205F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
@@ -8981,28 +8981,28 @@
 { "mpyuw", 0x20DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyuw<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS.  */
-{ "mpyuw", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyuw", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyuw<.f> b,b,s12 00100bbb10011111FBBBssssssSSSSSS.  */
 { "mpyuw", 0x209F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyuw<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA.  */
-{ "mpyuw", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyuw", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyuw<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA.  */
-{ "mpyuw", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyuw", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyuw<.f> 0,limm,c 0010011000111111F111CCCCCC111110.  */
-{ "mpyuw", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyuw", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyuw<.f> 0,b,limm 00100bbb00111111FBBB111110111110.  */
-{ "mpyuw", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyuw", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyuw<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ.  */
-{ "mpyuw", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mpyuw", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mpyuw<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ.  */
-{ "mpyuw", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyuw", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyuw<.f> a,limm,c 0010011000011111F111CCCCCCAAAAAA.  */
 { "mpyuw", 0x261F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
@@ -9023,13 +9023,13 @@
 { "mpyuw", 0x26DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyuw<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA.  */
-{ "mpyuw", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyuw", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyuw<.f> 0,limm,u6 0010011001111111F111uuuuuu111110.  */
-{ "mpyuw", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyuw", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyuw<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ.  */
-{ "mpyuw", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyuw", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyuw<.f> a,limm,u6 0010011001011111F111uuuuuuAAAAAA.  */
 { "mpyuw", 0x265F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
@@ -9041,19 +9041,19 @@
 { "mpyuw", 0x26DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyuw<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS.  */
-{ "mpyuw", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyuw", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyuw<.f> 0,limm,s12 0010011010011111F111ssssssSSSSSS.  */
 { "mpyuw", 0x269F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyuw<.f> a,limm,limm 0010011000111111F111111110AAAAAA.  */
-{ "mpyuw", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mpyuw", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mpyuw<.f> 0,limm,limm 0010011000111111F111111110111110.  */
-{ "mpyuw", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mpyuw", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mpyuw<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ.  */
-{ "mpyuw", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mpyuw", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mpyuw<.f> a,limm,limm 0010011000011111F111111110AAAAAA.  */
 { "mpyuw", 0x261F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
@@ -9068,13 +9068,13 @@
 { "mpyuw_s", 0x0000780A, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* mpyw<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA.  */
-{ "mpyw", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mpyw", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mpyw<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110.  */
-{ "mpyw", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mpyw", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mpyw<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ.  */
-{ "mpyw", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyw", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyw<.f> a,b,c 00100bbb00011110FBBBCCCCCCAAAAAA.  */
 { "mpyw", 0x201E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -9086,13 +9086,13 @@
 { "mpyw", 0x20DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyw<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA.  */
-{ "mpyw", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyw", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyw<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110.  */
-{ "mpyw", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyw", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyw<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ.  */
-{ "mpyw", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyw", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyw<.f> a,b,u6 00100bbb01011110FBBBuuuuuuAAAAAA.  */
 { "mpyw", 0x205E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
@@ -9104,28 +9104,28 @@
 { "mpyw", 0x20DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyw<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS.  */
-{ "mpyw", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyw", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyw<.f> b,b,s12 00100bbb10011110FBBBssssssSSSSSS.  */
 { "mpyw", 0x209E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyw<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA.  */
-{ "mpyw", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyw", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyw<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA.  */
-{ "mpyw", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyw", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyw<.f> 0,limm,c 0010011000111110F111CCCCCC111110.  */
-{ "mpyw", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mpyw", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mpyw<.f> 0,b,limm 00100bbb00111110FBBB111110111110.  */
-{ "mpyw", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mpyw", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mpyw<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ.  */
-{ "mpyw", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mpyw", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mpyw<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ.  */
-{ "mpyw", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mpyw", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyw<.f> a,limm,c 0010011000011110F111CCCCCCAAAAAA.  */
 { "mpyw", 0x261E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
@@ -9146,13 +9146,13 @@
 { "mpyw", 0x26DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mpyw<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA.  */
-{ "mpyw", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyw", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyw<.f> 0,limm,u6 0010011001111110F111uuuuuu111110.  */
-{ "mpyw", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mpyw", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mpyw<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ.  */
-{ "mpyw", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mpyw", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyw<.f> a,limm,u6 0010011001011110F111uuuuuuAAAAAA.  */
 { "mpyw", 0x265E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
@@ -9164,19 +9164,19 @@
 { "mpyw", 0x26DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mpyw<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS.  */
-{ "mpyw", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mpyw", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyw<.f> 0,limm,s12 0010011010011110F111ssssssSSSSSS.  */
 { "mpyw", 0x269E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mpyw<.f> a,limm,limm 0010011000111110F111111110AAAAAA.  */
-{ "mpyw", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mpyw", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mpyw<.f> 0,limm,limm 0010011000111110F111111110111110.  */
-{ "mpyw", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mpyw", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mpyw<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ.  */
-{ "mpyw", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mpyw", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mpyw<.f> a,limm,limm 0010011000011110F111111110AAAAAA.  */
 { "mpyw", 0x261E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
@@ -9194,997 +9194,997 @@
 { "mpy_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* msubdw<.f> a,b,c 00101bbb00010100FBBBCCCCCCAAAAAA.  */
-{ "msubdw", 0x28140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "msubdw", 0x28140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* msubdw<.f> 0,b,c 00101bbb00010100FBBBCCCCCC111110.  */
-{ "msubdw", 0x2814003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "msubdw", 0x2814003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* msubdw<.f><.cc> b,b,c 00101bbb11010100FBBBCCCCCC0QQQQQ.  */
-{ "msubdw", 0x28D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "msubdw", 0x28D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* msubdw<.f> a,b,u6 00101bbb01010100FBBBuuuuuuAAAAAA.  */
-{ "msubdw", 0x28540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "msubdw", 0x28540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* msubdw<.f> 0,b,u6 00101bbb01010100FBBBuuuuuu111110.  */
-{ "msubdw", 0x2854003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "msubdw", 0x2854003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* msubdw<.f><.cc> b,b,u6 00101bbb11010100FBBBuuuuuu1QQQQQ.  */
-{ "msubdw", 0x28D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "msubdw", 0x28D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* msubdw<.f> b,b,s12 00101bbb10010100FBBBssssssSSSSSS.  */
-{ "msubdw", 0x28940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "msubdw", 0x28940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* msubdw<.f> a,limm,c 0010111000010100F111CCCCCCAAAAAA.  */
-{ "msubdw", 0x2E147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "msubdw", 0x2E147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* msubdw<.f> a,b,limm 00101bbb00010100FBBB111110AAAAAA.  */
-{ "msubdw", 0x28140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "msubdw", 0x28140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* msubdw<.f> 0,limm,c 0010111000010100F111CCCCCC111110.  */
-{ "msubdw", 0x2E14703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "msubdw", 0x2E14703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* msubdw<.f> 0,b,limm 00101bbb00010100FBBB111110111110.  */
-{ "msubdw", 0x28140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "msubdw", 0x28140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* msubdw<.f><.cc> 0,limm,c 0010111011010100F111CCCCCC0QQQQQ.  */
-{ "msubdw", 0x2ED47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "msubdw", 0x2ED47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* msubdw<.f><.cc> b,b,limm 00101bbb11010100FBBB1111100QQQQQ.  */
-{ "msubdw", 0x28D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "msubdw", 0x28D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* msubdw<.f> a,limm,u6 0010111001010100F111uuuuuuAAAAAA.  */
-{ "msubdw", 0x2E547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "msubdw", 0x2E547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* msubdw<.f> 0,limm,u6 0010111001010100F111uuuuuu111110.  */
-{ "msubdw", 0x2E54703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "msubdw", 0x2E54703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* msubdw<.f><.cc> 0,limm,u6 0010111011010100F111uuuuuu1QQQQQ.  */
-{ "msubdw", 0x2ED47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "msubdw", 0x2ED47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* msubdw<.f> 0,limm,s12 0010111010010100F111ssssssSSSSSS.  */
-{ "msubdw", 0x2E947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "msubdw", 0x2E947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* msubdw<.f> a,limm,limm 0010111000010100F111111110AAAAAA.  */
-{ "msubdw", 0x2E147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "msubdw", 0x2E147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* msubdw<.f> 0,limm,limm 0010111000010100F111111110111110.  */
-{ "msubdw", 0x2E147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "msubdw", 0x2E147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* msubdw<.f><.cc> 0,limm,limm 0010111011010100F1111111100QQQQQ.  */
-{ "msubdw", 0x2ED47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "msubdw", 0x2ED47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* msubt<.f> a,b,c 00101bbb00100000FBBBCCCCCCAAAAAA.  */
-{ "msubt", 0x28200000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "msubt", 0x28200000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* msubt<.f> 0,b,c 00101bbb00100000FBBBCCCCCC111110.  */
-{ "msubt", 0x2820003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "msubt", 0x2820003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* msubt<.f><.cc> b,b,c 00101bbb11100000FBBBCCCCCC0QQQQQ.  */
-{ "msubt", 0x28E00000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "msubt", 0x28E00000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* msubt<.f> a,b,u6 00101bbb01100000FBBBuuuuuuAAAAAA.  */
-{ "msubt", 0x28600000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "msubt", 0x28600000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* msubt<.f> 0,b,u6 00101bbb01100000FBBBuuuuuu111110.  */
-{ "msubt", 0x2860003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "msubt", 0x2860003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* msubt<.f><.cc> b,b,u6 00101bbb11100000FBBBuuuuuu1QQQQQ.  */
-{ "msubt", 0x28E00020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "msubt", 0x28E00020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* msubt<.f> b,b,s12 00101bbb10100000FBBBssssssSSSSSS.  */
-{ "msubt", 0x28A00000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "msubt", 0x28A00000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* msubt<.f> a,limm,c 0010111000100000F111CCCCCCAAAAAA.  */
-{ "msubt", 0x2E207000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "msubt", 0x2E207000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* msubt<.f> a,b,limm 00101bbb00100000FBBB111110AAAAAA.  */
-{ "msubt", 0x28200F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "msubt", 0x28200F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* msubt<.f> 0,limm,c 0010111000100000F111CCCCCC111110.  */
-{ "msubt", 0x2E20703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "msubt", 0x2E20703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* msubt<.f> 0,b,limm 00101bbb00100000FBBB111110111110.  */
-{ "msubt", 0x28200FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "msubt", 0x28200FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* msubt<.f><.cc> 0,limm,c 0010111011100000F111CCCCCC0QQQQQ.  */
-{ "msubt", 0x2EE07000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "msubt", 0x2EE07000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* msubt<.f><.cc> b,b,limm 00101bbb11100000FBBB1111100QQQQQ.  */
-{ "msubt", 0x28E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "msubt", 0x28E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* msubt<.f> a,limm,u6 0010111001100000F111uuuuuuAAAAAA.  */
-{ "msubt", 0x2E607000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "msubt", 0x2E607000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* msubt<.f> 0,limm,u6 0010111001100000F111uuuuuu111110.  */
-{ "msubt", 0x2E60703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "msubt", 0x2E60703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* msubt<.f><.cc> 0,limm,u6 0010111011100000F111uuuuuu1QQQQQ.  */
-{ "msubt", 0x2EE07020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "msubt", 0x2EE07020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* msubt<.f> 0,limm,s12 0010111010100000F111ssssssSSSSSS.  */
-{ "msubt", 0x2EA07000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "msubt", 0x2EA07000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* msubt<.f> a,limm,limm 0010111000100000F111111110AAAAAA.  */
-{ "msubt", 0x2E207F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "msubt", 0x2E207F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* msubt<.f> 0,limm,limm 0010111000100000F111111110111110.  */
-{ "msubt", 0x2E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "msubt", 0x2E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* msubt<.f><.cc> 0,limm,limm 0010111011100000F1111111100QQQQQ.  */
-{ "msubt", 0x2EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "msubt", 0x2EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110.  */
-{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ.  */
-{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_CC }},
+{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_CC }},
 
 /* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110.  */
-{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ.  */
-{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
+{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS.  */
-{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
+{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
 
 /* mul64 0,limm,c 00101110000001000111CCCCCC111110.  */
-{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* mul64 0,b,limm 00101bbb000001000BBB111110111110.  */
-{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ.  */
-{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ.  */
-{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_CC }},
+{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_CC }},
 
 /* mul64 0,limm,u6 00101110010001000111uuuuuu111110.  */
-{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ.  */
-{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS.  */
-{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* mul64 0,limm,limm 00101110000001000111111110111110.  */
-{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ.  */
-{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110.  */
-{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ.  */
-{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
+{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
 
 /* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110.  */
-{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ.  */
-{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
+{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS.  */
-{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
+{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
 
 /* mul64 0,limm,c 00101110000001000111CCCCCC111110.  */
-{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* mul64 0,b,limm 00101bbb000001000BBB111110111110.  */
-{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ.  */
-{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ.  */
-{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
+{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
 
 /* mul64 0,limm,u6 00101110010001000111uuuuuu111110.  */
-{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ.  */
-{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS.  */
-{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* mul64 0,limm,limm 00101110000001000111111110111110.  */
-{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ.  */
-{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* mul64_s 0,b,c 01111bbbccc01100.  */
-{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* mul64_s 0,b,c 01111bbbccc01100.  */
-{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* muldw<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA.  */
-{ "muldw", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "muldw", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* muldw<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110.  */
-{ "muldw", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "muldw", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* muldw<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ.  */
-{ "muldw", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "muldw", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* muldw<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA.  */
-{ "muldw", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "muldw", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* muldw<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110.  */
-{ "muldw", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "muldw", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* muldw<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ.  */
-{ "muldw", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "muldw", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* muldw<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS.  */
-{ "muldw", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "muldw", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* muldw<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA.  */
-{ "muldw", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "muldw", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* muldw<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA.  */
-{ "muldw", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "muldw", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* muldw<.f> 0,limm,c 0010111000001100F111CCCCCC111110.  */
-{ "muldw", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "muldw", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* muldw<.f> 0,b,limm 00101bbb00001100FBBB111110111110.  */
-{ "muldw", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "muldw", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* muldw<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ.  */
-{ "muldw", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "muldw", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* muldw<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ.  */
-{ "muldw", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "muldw", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* muldw<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA.  */
-{ "muldw", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "muldw", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* muldw<.f> 0,limm,u6 0010111001001100F111uuuuuu111110.  */
-{ "muldw", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "muldw", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* muldw<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ.  */
-{ "muldw", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "muldw", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* muldw<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS.  */
-{ "muldw", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "muldw", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* muldw<.f> a,limm,limm 0010111000001100F111111110AAAAAA.  */
-{ "muldw", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "muldw", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* muldw<.f> 0,limm,limm 0010111000001100F111111110111110.  */
-{ "muldw", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "muldw", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* muldw<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ.  */
-{ "muldw", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "muldw", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mulflw<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA.  */
-{ "mulflw", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulflw", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulflw<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110.  */
-{ "mulflw", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulflw", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulflw<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ.  */
-{ "mulflw", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mulflw", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulflw<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA.  */
-{ "mulflw", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulflw", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulflw<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110.  */
-{ "mulflw", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulflw", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulflw<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ.  */
-{ "mulflw", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulflw", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulflw<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS.  */
-{ "mulflw", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulflw", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulflw<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA.  */
-{ "mulflw", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulflw", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulflw<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA.  */
-{ "mulflw", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulflw", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulflw<.f> 0,limm,c 0010111000110010F111CCCCCC111110.  */
-{ "mulflw", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulflw", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulflw<.f> 0,b,limm 00101bbb00110010FBBB111110111110.  */
-{ "mulflw", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulflw", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulflw<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ.  */
-{ "mulflw", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mulflw", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulflw<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ.  */
-{ "mulflw", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mulflw", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mulflw<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA.  */
-{ "mulflw", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulflw", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulflw<.f> 0,limm,u6 0010111001110010F111uuuuuu111110.  */
-{ "mulflw", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulflw", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulflw<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ.  */
-{ "mulflw", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulflw", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulflw<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS.  */
-{ "mulflw", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulflw", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulflw<.f> a,limm,limm 0010111000110010F111111110AAAAAA.  */
-{ "mulflw", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulflw", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulflw<.f> 0,limm,limm 0010111000110010F111111110111110.  */
-{ "mulflw", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulflw", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulflw<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ.  */
-{ "mulflw", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mulflw", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mulhflw<.f> a,b,c 00101bbb00111001FBBBCCCCCCAAAAAA.  */
-{ "mulhflw", 0x28390000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulhflw", 0x28390000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulhflw<.f> 0,b,c 00101bbb00111001FBBBCCCCCC111110.  */
-{ "mulhflw", 0x2839003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulhflw", 0x2839003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulhflw<.f><.cc> b,b,c 00101bbb11111001FBBBCCCCCC0QQQQQ.  */
-{ "mulhflw", 0x28F90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mulhflw", 0x28F90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulhflw<.f> a,b,u6 00101bbb01111001FBBBuuuuuuAAAAAA.  */
-{ "mulhflw", 0x28790000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulhflw", 0x28790000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulhflw<.f> 0,b,u6 00101bbb01111001FBBBuuuuuu111110.  */
-{ "mulhflw", 0x2879003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulhflw", 0x2879003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulhflw<.f><.cc> b,b,u6 00101bbb11111001FBBBuuuuuu1QQQQQ.  */
-{ "mulhflw", 0x28F90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulhflw", 0x28F90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulhflw<.f> b,b,s12 00101bbb10111001FBBBssssssSSSSSS.  */
-{ "mulhflw", 0x28B90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulhflw", 0x28B90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulhflw<.f> a,limm,c 0010111000111001F111CCCCCCAAAAAA.  */
-{ "mulhflw", 0x2E397000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulhflw", 0x2E397000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulhflw<.f> a,b,limm 00101bbb00111001FBBB111110AAAAAA.  */
-{ "mulhflw", 0x28390F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulhflw", 0x28390F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulhflw<.f> 0,limm,c 0010111000111001F111CCCCCC111110.  */
-{ "mulhflw", 0x2E39703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulhflw", 0x2E39703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulhflw<.f> 0,b,limm 00101bbb00111001FBBB111110111110.  */
-{ "mulhflw", 0x28390FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulhflw", 0x28390FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulhflw<.f><.cc> 0,limm,c 0010111011111001F111CCCCCC0QQQQQ.  */
-{ "mulhflw", 0x2EF97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mulhflw", 0x2EF97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulhflw<.f><.cc> b,b,limm 00101bbb11111001FBBB1111100QQQQQ.  */
-{ "mulhflw", 0x28F90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mulhflw", 0x28F90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mulhflw<.f> a,limm,u6 0010111001111001F111uuuuuuAAAAAA.  */
-{ "mulhflw", 0x2E797000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulhflw", 0x2E797000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulhflw<.f> 0,limm,u6 0010111001111001F111uuuuuu111110.  */
-{ "mulhflw", 0x2E79703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulhflw", 0x2E79703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulhflw<.f><.cc> 0,limm,u6 0010111011111001F111uuuuuu1QQQQQ.  */
-{ "mulhflw", 0x2EF97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulhflw", 0x2EF97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulhflw<.f> 0,limm,s12 0010111010111001F111ssssssSSSSSS.  */
-{ "mulhflw", 0x2EB97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulhflw", 0x2EB97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulhflw<.f> a,limm,limm 0010111000111001F111111110AAAAAA.  */
-{ "mulhflw", 0x2E397F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulhflw", 0x2E397F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulhflw<.f> 0,limm,limm 0010111000111001F111111110111110.  */
-{ "mulhflw", 0x2E397FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulhflw", 0x2E397FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulhflw<.f><.cc> 0,limm,limm 0010111011111001F1111111100QQQQQ.  */
-{ "mulhflw", 0x2EF97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mulhflw", 0x2EF97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mulhlw<.f> a,b,c 00101bbb00111000FBBBCCCCCCAAAAAA.  */
-{ "mulhlw", 0x28380000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulhlw", 0x28380000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulhlw<.f> 0,b,c 00101bbb00111000FBBBCCCCCC111110.  */
-{ "mulhlw", 0x2838003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulhlw", 0x2838003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulhlw<.f><.cc> b,b,c 00101bbb11111000FBBBCCCCCC0QQQQQ.  */
-{ "mulhlw", 0x28F80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mulhlw", 0x28F80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulhlw<.f> a,b,u6 00101bbb01111000FBBBuuuuuuAAAAAA.  */
-{ "mulhlw", 0x28780000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulhlw", 0x28780000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulhlw<.f> 0,b,u6 00101bbb01111000FBBBuuuuuu111110.  */
-{ "mulhlw", 0x2878003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulhlw", 0x2878003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulhlw<.f><.cc> b,b,u6 00101bbb11111000FBBBuuuuuu1QQQQQ.  */
-{ "mulhlw", 0x28F80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulhlw", 0x28F80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulhlw<.f> b,b,s12 00101bbb10111000FBBBssssssSSSSSS.  */
-{ "mulhlw", 0x28B80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulhlw", 0x28B80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulhlw<.f> a,limm,c 0010111000111000F111CCCCCCAAAAAA.  */
-{ "mulhlw", 0x2E387000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulhlw", 0x2E387000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulhlw<.f> a,b,limm 00101bbb00111000FBBB111110AAAAAA.  */
-{ "mulhlw", 0x28380F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulhlw", 0x28380F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulhlw<.f> 0,limm,c 0010111000111000F111CCCCCC111110.  */
-{ "mulhlw", 0x2E38703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulhlw", 0x2E38703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulhlw<.f> 0,b,limm 00101bbb00111000FBBB111110111110.  */
-{ "mulhlw", 0x28380FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulhlw", 0x28380FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulhlw<.f><.cc> 0,limm,c 0010111011111000F111CCCCCC0QQQQQ.  */
-{ "mulhlw", 0x2EF87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mulhlw", 0x2EF87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulhlw<.f><.cc> b,b,limm 00101bbb11111000FBBB1111100QQQQQ.  */
-{ "mulhlw", 0x28F80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mulhlw", 0x28F80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mulhlw<.f> a,limm,u6 0010111001111000F111uuuuuuAAAAAA.  */
-{ "mulhlw", 0x2E787000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulhlw", 0x2E787000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulhlw<.f> 0,limm,u6 0010111001111000F111uuuuuu111110.  */
-{ "mulhlw", 0x2E78703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulhlw", 0x2E78703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulhlw<.f><.cc> 0,limm,u6 0010111011111000F111uuuuuu1QQQQQ.  */
-{ "mulhlw", 0x2EF87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulhlw", 0x2EF87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulhlw<.f> 0,limm,s12 0010111010111000F111ssssssSSSSSS.  */
-{ "mulhlw", 0x2EB87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulhlw", 0x2EB87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulhlw<.f> a,limm,limm 0010111000111000F111111110AAAAAA.  */
-{ "mulhlw", 0x2E387F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulhlw", 0x2E387F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulhlw<.f> 0,limm,limm 0010111000111000F111111110111110.  */
-{ "mulhlw", 0x2E387FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulhlw", 0x2E387FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulhlw<.f><.cc> 0,limm,limm 0010111011111000F1111111100QQQQQ.  */
-{ "mulhlw", 0x2EF87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mulhlw", 0x2EF87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mullw<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA.  */
-{ "mullw", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mullw", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mullw<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110.  */
-{ "mullw", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mullw", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mullw<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ.  */
-{ "mullw", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mullw", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mullw<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA.  */
-{ "mullw", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mullw", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mullw<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110.  */
-{ "mullw", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mullw", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mullw<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ.  */
-{ "mullw", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mullw", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mullw<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS.  */
-{ "mullw", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mullw", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mullw<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA.  */
-{ "mullw", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mullw", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mullw<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA.  */
-{ "mullw", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mullw", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mullw<.f> 0,limm,c 0010111000110001F111CCCCCC111110.  */
-{ "mullw", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mullw", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mullw<.f> 0,b,limm 00101bbb00110001FBBB111110111110.  */
-{ "mullw", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mullw", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mullw<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ.  */
-{ "mullw", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mullw", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mullw<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ.  */
-{ "mullw", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mullw", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mullw<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA.  */
-{ "mullw", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mullw", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mullw<.f> 0,limm,u6 0010111001110001F111uuuuuu111110.  */
-{ "mullw", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mullw", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mullw<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ.  */
-{ "mullw", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mullw", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mullw<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS.  */
-{ "mullw", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mullw", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mullw<.f> a,limm,limm 0010111000110001F111111110AAAAAA.  */
-{ "mullw", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mullw", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mullw<.f> 0,limm,limm 0010111000110001F111111110111110.  */
-{ "mullw", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mullw", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mullw<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ.  */
-{ "mullw", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mullw", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mulrdw<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA.  */
-{ "mulrdw", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulrdw", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulrdw<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110.  */
-{ "mulrdw", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulrdw", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulrdw<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ.  */
-{ "mulrdw", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mulrdw", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulrdw<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA.  */
-{ "mulrdw", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulrdw", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulrdw<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110.  */
-{ "mulrdw", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulrdw", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulrdw<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ.  */
-{ "mulrdw", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulrdw", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulrdw<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS.  */
-{ "mulrdw", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulrdw", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulrdw<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA.  */
-{ "mulrdw", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulrdw", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulrdw<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA.  */
-{ "mulrdw", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulrdw", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulrdw<.f> 0,limm,c 0010111000001110F111CCCCCC111110.  */
-{ "mulrdw", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulrdw", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulrdw<.f> 0,b,limm 00101bbb00001110FBBB111110111110.  */
-{ "mulrdw", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulrdw", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulrdw<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ.  */
-{ "mulrdw", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mulrdw", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulrdw<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ.  */
-{ "mulrdw", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mulrdw", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mulrdw<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA.  */
-{ "mulrdw", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulrdw", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulrdw<.f> 0,limm,u6 0010111001001110F111uuuuuu111110.  */
-{ "mulrdw", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulrdw", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulrdw<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ.  */
-{ "mulrdw", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulrdw", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulrdw<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS.  */
-{ "mulrdw", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulrdw", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulrdw<.f> a,limm,limm 0010111000001110F111111110AAAAAA.  */
-{ "mulrdw", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulrdw", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulrdw<.f> 0,limm,limm 0010111000001110F111111110111110.  */
-{ "mulrdw", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulrdw", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulrdw<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ.  */
-{ "mulrdw", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mulrdw", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mulrt<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA.  */
-{ "mulrt", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulrt", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulrt<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110.  */
-{ "mulrt", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulrt", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulrt<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ.  */
-{ "mulrt", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mulrt", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulrt<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA.  */
-{ "mulrt", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulrt", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulrt<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110.  */
-{ "mulrt", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulrt", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulrt<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ.  */
-{ "mulrt", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulrt", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulrt<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS.  */
-{ "mulrt", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulrt", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulrt<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA.  */
-{ "mulrt", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulrt", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulrt<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA.  */
-{ "mulrt", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulrt", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulrt<.f> 0,limm,c 0010111000011010F111CCCCCC111110.  */
-{ "mulrt", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulrt", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulrt<.f> 0,b,limm 00101bbb00011010FBBB111110111110.  */
-{ "mulrt", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulrt", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulrt<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ.  */
-{ "mulrt", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mulrt", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulrt<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ.  */
-{ "mulrt", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mulrt", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mulrt<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA.  */
-{ "mulrt", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulrt", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulrt<.f> 0,limm,u6 0010111001011010F111uuuuuu111110.  */
-{ "mulrt", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulrt", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulrt<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ.  */
-{ "mulrt", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulrt", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulrt<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS.  */
-{ "mulrt", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulrt", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulrt<.f> a,limm,limm 0010111000011010F111111110AAAAAA.  */
-{ "mulrt", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulrt", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulrt<.f> 0,limm,limm 0010111000011010F111111110111110.  */
-{ "mulrt", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulrt", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulrt<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ.  */
-{ "mulrt", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mulrt", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mult<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA.  */
-{ "mult", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mult", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mult<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110.  */
-{ "mult", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mult", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mult<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ.  */
-{ "mult", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mult", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mult<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA.  */
-{ "mult", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mult", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mult<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110.  */
-{ "mult", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mult", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mult<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ.  */
-{ "mult", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mult", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mult<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS.  */
-{ "mult", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mult", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mult<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA.  */
-{ "mult", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mult", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mult<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA.  */
-{ "mult", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mult", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mult<.f> 0,limm,c 0010111000011000F111CCCCCC111110.  */
-{ "mult", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mult", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mult<.f> 0,b,limm 00101bbb00011000FBBB111110111110.  */
-{ "mult", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mult", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mult<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ.  */
-{ "mult", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mult", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mult<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ.  */
-{ "mult", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mult", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mult<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA.  */
-{ "mult", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mult", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mult<.f> 0,limm,u6 0010111001011000F111uuuuuu111110.  */
-{ "mult", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mult", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mult<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ.  */
-{ "mult", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mult", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mult<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS.  */
-{ "mult", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mult", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mult<.f> a,limm,limm 0010111000011000F111111110AAAAAA.  */
-{ "mult", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mult", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mult<.f> 0,limm,limm 0010111000011000F111111110111110.  */
-{ "mult", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mult", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mult<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ.  */
-{ "mult", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mult", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110.  */
-{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ.  */
-{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_CC }},
+{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_CC }},
 
 /* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110.  */
-{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ.  */
-{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
+{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS.  */
-{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
+{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
 
 /* mulu64 0,limm,c 00101110000001010111CCCCCC111110.  */
-{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* mulu64 0,b,limm 00101bbb000001010BBB111110111110.  */
-{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ.  */
-{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ.  */
-{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_CC }},
+{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_CC }},
 
 /* mulu64 0,limm,u6 00101110010001010111uuuuuu111110.  */
-{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ.  */
-{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS.  */
-{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* mulu64 0,limm,limm 00101110000001010111111110111110.  */
-{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ.  */
-{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110.  */
-{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ.  */
-{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
+{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
 
 /* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110.  */
-{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ.  */
-{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
+{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS.  */
-{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
+{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
 
 /* mulu64 0,limm,c 00101110000001010111CCCCCC111110.  */
-{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* mulu64 0,b,limm 00101bbb000001010BBB111110111110.  */
-{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ.  */
-{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ.  */
-{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
+{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
 
 /* mulu64 0,limm,u6 00101110010001010111uuuuuu111110.  */
-{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ.  */
-{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS.  */
-{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* mulu64 0,limm,limm 00101110000001010111111110111110.  */
-{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ.  */
-{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* muludw<.f> a,b,c 00101bbb00001101FBBBCCCCCCAAAAAA.  */
-{ "muludw", 0x280D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "muludw", 0x280D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* muludw<.f> 0,b,c 00101bbb00001101FBBBCCCCCC111110.  */
-{ "muludw", 0x280D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "muludw", 0x280D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* muludw<.f><.cc> b,b,c 00101bbb11001101FBBBCCCCCC0QQQQQ.  */
-{ "muludw", 0x28CD0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "muludw", 0x28CD0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* muludw<.f> a,b,u6 00101bbb01001101FBBBuuuuuuAAAAAA.  */
-{ "muludw", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "muludw", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* muludw<.f> 0,b,u6 00101bbb01001101FBBBuuuuuu111110.  */
-{ "muludw", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "muludw", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* muludw<.f><.cc> b,b,u6 00101bbb11001101FBBBuuuuuu1QQQQQ.  */
-{ "muludw", 0x28CD0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "muludw", 0x28CD0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* muludw<.f> b,b,s12 00101bbb10001101FBBBssssssSSSSSS.  */
-{ "muludw", 0x288D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "muludw", 0x288D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* muludw<.f> a,limm,c 0010111000001101F111CCCCCCAAAAAA.  */
-{ "muludw", 0x2E0D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "muludw", 0x2E0D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* muludw<.f> a,b,limm 00101bbb00001101FBBB111110AAAAAA.  */
-{ "muludw", 0x280D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "muludw", 0x280D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* muludw<.f> 0,limm,c 0010111000001101F111CCCCCC111110.  */
-{ "muludw", 0x2E0D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "muludw", 0x2E0D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* muludw<.f> 0,b,limm 00101bbb00001101FBBB111110111110.  */
-{ "muludw", 0x280D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "muludw", 0x280D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* muludw<.f><.cc> 0,limm,c 0010111011001101F111CCCCCC0QQQQQ.  */
-{ "muludw", 0x2ECD7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "muludw", 0x2ECD7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* muludw<.f><.cc> b,b,limm 00101bbb11001101FBBB1111100QQQQQ.  */
-{ "muludw", 0x28CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "muludw", 0x28CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* muludw<.f> a,limm,u6 0010111001001101F111uuuuuuAAAAAA.  */
-{ "muludw", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "muludw", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* muludw<.f> 0,limm,u6 0010111001001101F111uuuuuu111110.  */
-{ "muludw", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "muludw", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* muludw<.f><.cc> 0,limm,u6 0010111011001101F111uuuuuu1QQQQQ.  */
-{ "muludw", 0x2ECD7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "muludw", 0x2ECD7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* muludw<.f> 0,limm,s12 0010111010001101F111ssssssSSSSSS.  */
-{ "muludw", 0x2E8D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "muludw", 0x2E8D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* muludw<.f> a,limm,limm 0010111000001101F111111110AAAAAA.  */
-{ "muludw", 0x2E0D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "muludw", 0x2E0D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* muludw<.f> 0,limm,limm 0010111000001101F111111110111110.  */
-{ "muludw", 0x2E0D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "muludw", 0x2E0D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* muludw<.f><.cc> 0,limm,limm 0010111011001101F1111111100QQQQQ.  */
-{ "muludw", 0x2ECD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "muludw", 0x2ECD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mululw<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA.  */
-{ "mululw", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mululw", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mululw<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110.  */
-{ "mululw", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mululw", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mululw<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ.  */
-{ "mululw", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mululw", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mululw<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA.  */
-{ "mululw", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mululw", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mululw<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110.  */
-{ "mululw", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mululw", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mululw<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ.  */
-{ "mululw", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mululw", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mululw<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS.  */
-{ "mululw", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mululw", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mululw<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA.  */
-{ "mululw", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mululw", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mululw<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA.  */
-{ "mululw", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mululw", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mululw<.f> 0,limm,c 0010111000110000F111CCCCCC111110.  */
-{ "mululw", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mululw", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mululw<.f> 0,b,limm 00101bbb00110000FBBB111110111110.  */
-{ "mululw", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mululw", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mululw<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ.  */
-{ "mululw", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mululw", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mululw<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ.  */
-{ "mululw", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mululw", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mululw<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA.  */
-{ "mululw", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mululw", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mululw<.f> 0,limm,u6 0010111001110000F111uuuuuu111110.  */
-{ "mululw", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mululw", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mululw<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ.  */
-{ "mululw", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mululw", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mululw<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS.  */
-{ "mululw", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mululw", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mululw<.f> a,limm,limm 0010111000110000F111111110AAAAAA.  */
-{ "mululw", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mululw", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mululw<.f> 0,limm,limm 0010111000110000F111111110111110.  */
-{ "mululw", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mululw", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mululw<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ.  */
-{ "mululw", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mululw", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* mulut<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA.  */
-{ "mulut", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulut", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulut<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110.  */
-{ "mulut", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "mulut", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* mulut<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ.  */
-{ "mulut", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "mulut", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulut<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA.  */
-{ "mulut", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulut", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulut<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110.  */
-{ "mulut", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulut", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulut<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ.  */
-{ "mulut", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulut", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulut<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS.  */
-{ "mulut", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulut", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulut<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA.  */
-{ "mulut", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulut", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulut<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA.  */
-{ "mulut", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulut", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulut<.f> 0,limm,c 0010111000011001F111CCCCCC111110.  */
-{ "mulut", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "mulut", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* mulut<.f> 0,b,limm 00101bbb00011001FBBB111110111110.  */
-{ "mulut", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "mulut", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* mulut<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ.  */
-{ "mulut", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "mulut", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* mulut<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ.  */
-{ "mulut", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "mulut", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* mulut<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA.  */
-{ "mulut", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulut", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulut<.f> 0,limm,u6 0010111001011001F111uuuuuu111110.  */
-{ "mulut", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "mulut", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* mulut<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ.  */
-{ "mulut", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "mulut", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* mulut<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS.  */
-{ "mulut", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "mulut", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* mulut<.f> a,limm,limm 0010111000011001F111111110AAAAAA.  */
-{ "mulut", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulut", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulut<.f> 0,limm,limm 0010111000011001F111111110111110.  */
-{ "mulut", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "mulut", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* mulut<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ.  */
-{ "mulut", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "mulut", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA.  */
-{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB }, { C_F }},
+{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB }, { C_F }},
 
 /* neg<.f> 0,b 00100bbb01001110FBBB000000111110.  */
-{ "neg", 0x204E003E, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB }, { C_F }},
+{ "neg", 0x204E003E, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB }, { C_F }},
 
 /* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ.  */
-{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup }, { C_F, C_CC }},
+{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup }, { C_F, C_CC }},
 
 /* neg<.f> a,limm 0010011001001110F111000000AAAAAA.  */
-{ "neg", 0x264E7000, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM }, { C_F }},
+{ "neg", 0x264E7000, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM }, { C_F }},
 
 /* neg<.f><.cc> 0,limm 0010011011001110F1110000001QQQQQ.  */
-{ "neg", 0x26CE7020, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }},
+{ "neg", 0x26CE7020, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* negsw<.f> b,c 00101bbb00101111FBBBCCCCCC000110.  */
-{ "negsw", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "negsw", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* negsw<.f> 0,c 0010111000101111F111CCCCCC000110.  */
-{ "negsw", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "negsw", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* negsw<.f> b,u6 00101bbb01101111FBBBuuuuuu000110.  */
-{ "negsw", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "negsw", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* negsw<.f> 0,u6 0010111001101111F111uuuuuu000110.  */
-{ "negsw", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "negsw", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* negsw<.f> b,limm 00101bbb00101111FBBB111110000110.  */
-{ "negsw", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "negsw", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* negsw<.f> 0,limm 0010111000101111F111111110000110.  */
-{ "negsw", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "negsw", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* neg_s b,c 01111bbbccc10011.  */
-{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* nop_s  0111100011100000.  */
-{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001.  */
 { "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -10241,124 +10241,124 @@
 { "normw", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* not<.f> b,c 00100bbb00101111FBBBCCCCCC001010.  */
-{ "not", 0x202F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "not", 0x202F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* not<.f> 0,c 0010011000101111F111CCCCCC001010.  */
-{ "not", 0x262F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "not", 0x262F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* not<.f> b,u6 00100bbb01101111FBBBuuuuuu001010.  */
-{ "not", 0x206F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "not", 0x206F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* not<.f> 0,u6 0010011001101111F111uuuuuu001010.  */
-{ "not", 0x266F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "not", 0x266F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* not<.f> b,limm 00100bbb00101111FBBB111110001010.  */
-{ "not", 0x202F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "not", 0x202F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* not<.f> 0,limm 0010011000101111F111111110001010.  */
-{ "not", 0x262F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "not", 0x262F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* not_s b,c 01111bbbccc10010.  */
-{ "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* or<.f> a,b,c 00100bbb00000101FBBBCCCCCCAAAAAA.  */
-{ "or", 0x20050000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "or", 0x20050000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* or<.f> 0,b,c 00100bbb00000101FBBBCCCCCC111110.  */
-{ "or", 0x2005003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "or", 0x2005003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* or<.f><.cc> b,b,c 00100bbb11000101FBBBCCCCCC0QQQQQ.  */
-{ "or", 0x20C50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "or", 0x20C50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* or<.f> a,b,u6 00100bbb01000101FBBBuuuuuuAAAAAA.  */
-{ "or", 0x20450000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "or", 0x20450000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* or<.f> 0,b,u6 00100bbb01000101FBBBuuuuuu111110.  */
-{ "or", 0x2045003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "or", 0x2045003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* or<.f><.cc> b,b,u6 00100bbb11000101FBBBuuuuuu1QQQQQ.  */
-{ "or", 0x20C50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "or", 0x20C50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* or<.f> b,b,s12 00100bbb10000101FBBBssssssSSSSSS.  */
-{ "or", 0x20850000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "or", 0x20850000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* or<.f> a,limm,c 0010011000000101F111CCCCCCAAAAAA.  */
-{ "or", 0x26057000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "or", 0x26057000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* or<.f> a,b,limm 00100bbb00000101FBBB111110AAAAAA.  */
-{ "or", 0x20050F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "or", 0x20050F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* or<.f> 0,limm,c 0010011000000101F111CCCCCC111110.  */
-{ "or", 0x2605703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "or", 0x2605703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* or<.f> 0,b,limm 00100bbb00000101FBBB111110111110.  */
-{ "or", 0x20050FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "or", 0x20050FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* or<.f><.cc> b,b,limm 00100bbb11000101FBBB1111100QQQQQ.  */
-{ "or", 0x20C50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "or", 0x20C50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* or<.f><.cc> 0,limm,c 0010011011000101F111CCCCCC0QQQQQ.  */
-{ "or", 0x26C57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "or", 0x26C57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* or<.f> a,limm,u6 0010011001000101F111uuuuuuAAAAAA.  */
-{ "or", 0x26457000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "or", 0x26457000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* or<.f> 0,limm,u6 0010011001000101F111uuuuuu111110.  */
-{ "or", 0x2645703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "or", 0x2645703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* or<.f><.cc> 0,limm,u6 0010011011000101F111uuuuuu1QQQQQ.  */
-{ "or", 0x26C57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "or", 0x26C57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* or<.f> 0,limm,s12 0010011010000101F111ssssssSSSSSS.  */
-{ "or", 0x26857000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "or", 0x26857000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* or<.f> a,limm,limm 0010011000000101F111111110AAAAAA.  */
-{ "or", 0x26057F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "or", 0x26057F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* or<.f> 0,limm,limm 0010011000000101F111111110111110.  */
-{ "or", 0x26057FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "or", 0x26057FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* or<.f><.cc> 0,limm,limm 0010011011000101F1111111100QQQQQ.  */
-{ "or", 0x26C57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "or", 0x26C57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* or_s b,b,c 01111bbbccc00101.  */
-{ "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
+{ "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* pkqb<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA.  */
-{ "pkqb", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "pkqb", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* pkqb<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ.  */
-{ "pkqb", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "pkqb", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* pkqb<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA.  */
-{ "pkqb", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "pkqb", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* pkqb<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ.  */
-{ "pkqb", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "pkqb", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* pkqb<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS.  */
-{ "pkqb", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "pkqb", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* pkqb<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA.  */
-{ "pkqb", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "pkqb", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* pkqb<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA.  */
-{ "pkqb", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "pkqb", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* pkqb<.f><.cc> b,b,limm 00110bbb11100000FBBB1111100QQQQQ.  */
-{ "pkqb", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "pkqb", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* pop_s b 11000bbb11000001.  */
-{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, NONE, { OPERAND_RB_S }, { C_AA_AB }},
+{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S }, { C_AA_AB }},
 
 /* pop_s OPERAND_BLINK 11000RRR11010001.  */
-{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, NONE, { OPERAND_BLINK_S }, { C_AA_AB }},
+{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, ARC_INSN_SUBCLASS_NONE, { OPERAND_BLINK_S }, { C_AA_AB }},
 
 /* push_s b 11000bbb11100001.  */
-{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, NONE, { OPERAND_RB_S }, { C_AA_AW }},
+{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S }, { C_AA_AW }},
 
 /* push_s blink 11000RRR11110001.  */
-{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, NONE, { OPERAND_BLINK_S }, { C_AA_AW }},
+{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, ARC_INSN_SUBCLASS_NONE, { OPERAND_BLINK_S }, { C_AA_AW }},
 
 /* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA.  */
 { "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -10604,64 +10604,64 @@
 { "qmpyhu", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* rcmp b,c 00100bbb000011011BBBCCCCCCRRRRRR.  */
-{ "rcmp", 0x200D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "rcmp", 0x200D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* rcmp b,c 00100bbb000011011BBBCCCCCC000000.  */
-{ "rcmp", 0x200D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "rcmp", 0x200D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* rcmp<.cc> b,c 00100bbb110011011BBBCCCCCC0QQQQQ.  */
-{ "rcmp", 0x20CD8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
+{ "rcmp", 0x20CD8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
 
 /* rcmp b,u6 00100bbb010011011BBBuuuuuuRRRRRR.  */
-{ "rcmp", 0x204D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "rcmp", 0x204D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* rcmp b,u6 00100bbb010011011BBBuuuuuu000000.  */
-{ "rcmp", 0x204D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "rcmp", 0x204D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* rcmp<.cc> b,u6 00100bbb110011011BBBuuuuuu1QQQQQ.  */
-{ "rcmp", 0x20CD8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
+{ "rcmp", 0x20CD8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* rcmp b,s12 00100bbb100011011BBBssssssSSSSSS.  */
-{ "rcmp", 0x208D8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
+{ "rcmp", 0x208D8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
 
 /* rcmp limm,c 00100110000011011111CCCCCCRRRRRR.  */
-{ "rcmp", 0x260DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "rcmp", 0x260DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* rcmp b,limm 00100bbb000011011BBB111110RRRRRR.  */
-{ "rcmp", 0x200D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "rcmp", 0x200D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* rcmp limm,c 00100110000011011111CCCCCC000000.  */
-{ "rcmp", 0x260DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "rcmp", 0x260DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* rcmp b,limm 00100bbb000011011BBB111110000000.  */
-{ "rcmp", 0x200D8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "rcmp", 0x200D8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* rcmp<.cc> limm,c 00100110110011011111CCCCCC0QQQQQ.  */
-{ "rcmp", 0x26CDF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "rcmp", 0x26CDF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* rcmp<.cc> b,limm 00100bbb110011011BBB1111100QQQQQ.  */
-{ "rcmp", 0x20CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
+{ "rcmp", 0x20CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
 
 /* rcmp limm,u6 00100110010011011111uuuuuuRRRRRR.  */
-{ "rcmp", 0x264DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "rcmp", 0x264DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* rcmp limm,u6 00100110010011011111uuuuuu000000.  */
-{ "rcmp", 0x264DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "rcmp", 0x264DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* rcmp<.cc> limm,u6 00100110110011011111uuuuuu1QQQQQ.  */
-{ "rcmp", 0x26CDF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "rcmp", 0x26CDF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* rcmp limm,s12 00100110100011011111ssssssSSSSSS.  */
-{ "rcmp", 0x268DF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "rcmp", 0x268DF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* rcmp limm,limm 00100110000011011111111110RRRRRR.  */
-{ "rcmp", 0x260DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "rcmp", 0x260DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* rcmp limm,limm 00100110000011011111111110000000.  */
-{ "rcmp", 0x260DFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "rcmp", 0x260DFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* rcmp<.cc> limm,limm 001001101100110111111111100QQQQQ.  */
-{ "rcmp", 0x26CDFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "rcmp", 0x26CDFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA.  */
 { "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -10784,58 +10784,58 @@
 { "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* rlc<.f> b,c 00100bbb00101111FBBBCCCCCC001011.  */
-{ "rlc", 0x202F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "rlc", 0x202F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* rlc<.f> 0,c 0010011000101111F111CCCCCC001011.  */
-{ "rlc", 0x262F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "rlc", 0x262F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* rlc<.f> b,u6 00100bbb01101111FBBBuuuuuu001011.  */
-{ "rlc", 0x206F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "rlc", 0x206F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rlc<.f> 0,u6 0010011001101111F111uuuuuu001011.  */
-{ "rlc", 0x266F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "rlc", 0x266F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rlc<.f> b,limm 00100bbb00101111FBBB111110001011.  */
-{ "rlc", 0x202F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "rlc", 0x202F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* rlc<.f> 0,limm 0010011000101111F111111110001011.  */
-{ "rlc", 0x262F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "rlc", 0x262F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* rnd16<.f> b,c 00101bbb00101111FBBBCCCCCC000011.  */
-{ "rnd16", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "rnd16", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* rnd16<.f> 0,c 0010111000101111F111CCCCCC000011.  */
-{ "rnd16", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "rnd16", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* rnd16<.f> b,u6 00101bbb01101111FBBBuuuuuu000011.  */
-{ "rnd16", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "rnd16", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rnd16<.f> 0,u6 0010111001101111F111uuuuuu000011.  */
-{ "rnd16", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "rnd16", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rnd16<.f> b,limm 00101bbb00101111FBBB111110000011.  */
-{ "rnd16", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "rnd16", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* rnd16<.f> 0,limm 0010111000101111F111111110000011.  */
-{ "rnd16", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "rnd16", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* rol<.f> b,c 00100bbb00101111FBBBCCCCCC001101.  */
-{ "rol", 0x202F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "rol", 0x202F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* rol<.f> 0,c 0010011000101111F111CCCCCC001101.  */
-{ "rol", 0x262F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "rol", 0x262F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* rol<.f> b,u6 00100bbb01101111FBBBuuuuuu001101.  */
-{ "rol", 0x206F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "rol", 0x206F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rol<.f> 0,u6 0010011001101111F111uuuuuu001101.  */
-{ "rol", 0x266F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "rol", 0x266F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rol<.f> b,limm 00100bbb00101111FBBB111110001101.  */
-{ "rol", 0x202F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "rol", 0x202F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* rol<.f> 0,limm 0010011000101111F111111110001101.  */
-{ "rol", 0x262F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "rol", 0x262F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* rol8<.f> b,c 00101bbb00101111FBBBCCCCCC010000.  */
 { "rol8", 0x282F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -10856,10 +10856,10 @@
 { "rol8", 0x2E2F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* ror<.f> b,c 00100bbb00101111FBBBCCCCCC000011.  */
-{ "ror", 0x202F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "ror", 0x202F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* ror<.f> 0,c 0010011000101111F111CCCCCC000011.  */
-{ "ror", 0x262F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "ror", 0x262F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* ror<.f> a,b,c 00101bbb00000011FBBBCCCCCCAAAAAA.  */
 { "ror", 0x28030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -10871,10 +10871,10 @@
 { "ror", 0x28C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* ror<.f> b,u6 00100bbb01101111FBBBuuuuuu000011.  */
-{ "ror", 0x206F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "ror", 0x206F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* ror<.f> 0,u6 0010011001101111F111uuuuuu000011.  */
-{ "ror", 0x266F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "ror", 0x266F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* ror<.f> a,b,u6 00101bbb01000011FBBBuuuuuuAAAAAA.  */
 { "ror", 0x28430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
@@ -10889,10 +10889,10 @@
 { "ror", 0x28830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* ror<.f> b,limm 00100bbb00101111FBBB111110000011.  */
-{ "ror", 0x202F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "ror", 0x202F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* ror<.f> 0,limm 0010011000101111F111111110000011.  */
-{ "ror", 0x262F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "ror", 0x262F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* ror<.f> a,limm,c 0010111000000011F111CCCCCCAAAAAA.  */
 { "ror", 0x2E037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
@@ -10952,217 +10952,217 @@
 { "ror8", 0x2E2F7F91, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* rrc<.f> b,c 00100bbb00101111FBBBCCCCCC000100.  */
-{ "rrc", 0x202F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "rrc", 0x202F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* rrc<.f> 0,c 0010011000101111F111CCCCCC000100.  */
-{ "rrc", 0x262F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "rrc", 0x262F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* rrc<.f> b,u6 00100bbb01101111FBBBuuuuuu000100.  */
-{ "rrc", 0x206F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "rrc", 0x206F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rrc<.f> 0,u6 0010011001101111F111uuuuuu000100.  */
-{ "rrc", 0x266F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "rrc", 0x266F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rrc<.f> b,limm 00100bbb00101111FBBB111110000100.  */
-{ "rrc", 0x202F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "rrc", 0x202F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* rrc<.f> 0,limm 0010011000101111F111111110000100.  */
-{ "rrc", 0x262F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "rrc", 0x262F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* rsub<.f> a,b,c 00100bbb00001110FBBBCCCCCCAAAAAA.  */
-{ "rsub", 0x200E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "rsub", 0x200E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* rsub<.f> 0,b,c 00100bbb00001110FBBBCCCCCC111110.  */
-{ "rsub", 0x200E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "rsub", 0x200E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* rsub<.f><.cc> b,b,c 00100bbb11001110FBBBCCCCCC0QQQQQ.  */
-{ "rsub", 0x20CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "rsub", 0x20CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* rsub<.f> a,b,u6 00100bbb01001110FBBBuuuuuuAAAAAA.  */
-{ "rsub", 0x204E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "rsub", 0x204E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rsub<.f> 0,b,u6 00100bbb01001110FBBBuuuuuu111110.  */
-{ "rsub", 0x204E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "rsub", 0x204E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rsub<.f><.cc> b,b,u6 00100bbb11001110FBBBuuuuuu1QQQQQ.  */
-{ "rsub", 0x20CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "rsub", 0x20CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* rsub<.f> b,b,s12 00100bbb10001110FBBBssssssSSSSSS.  */
-{ "rsub", 0x208E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "rsub", 0x208E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* rsub<.f> a,limm,c 0010011000001110F111CCCCCCAAAAAA.  */
-{ "rsub", 0x260E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "rsub", 0x260E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* rsub<.f> a,b,limm 00100bbb00001110FBBB111110AAAAAA.  */
-{ "rsub", 0x200E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "rsub", 0x200E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* rsub<.f> 0,limm,c 0010011000001110F111CCCCCC111110.  */
-{ "rsub", 0x260E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "rsub", 0x260E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* rsub<.f> 0,b,limm 00100bbb00001110FBBB111110111110.  */
-{ "rsub", 0x200E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "rsub", 0x200E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* rsub<.f><.cc> b,b,limm 00100bbb11001110FBBB1111100QQQQQ.  */
-{ "rsub", 0x20CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "rsub", 0x20CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* rsub<.f><.cc> 0,limm,c 0010011011001110F111CCCCCC0QQQQQ.  */
-{ "rsub", 0x26CE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "rsub", 0x26CE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* rsub<.f> a,limm,u6 0010011001001110F111uuuuuuAAAAAA.  */
-{ "rsub", 0x264E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "rsub", 0x264E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rsub<.f> 0,limm,u6 0010011001001110F111uuuuuu111110.  */
-{ "rsub", 0x264E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "rsub", 0x264E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* rsub<.f><.cc> 0,limm,u6 0010011011001110F111uuuuuu1QQQQQ.  */
-{ "rsub", 0x26CE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "rsub", 0x26CE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* rsub<.f> 0,limm,s12 0010011010001110F111ssssssSSSSSS.  */
-{ "rsub", 0x268E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "rsub", 0x268E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* rsub<.f> a,limm,limm 0010011000001110F111111110AAAAAA.  */
-{ "rsub", 0x260E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "rsub", 0x260E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* rsub<.f> 0,limm,limm 0010011000001110F111111110111110.  */
-{ "rsub", 0x260E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "rsub", 0x260E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* rsub<.f><.cc> 0,limm,limm 0010011011001110F1111111100QQQQQ.  */
-{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* rtie  00100100011011110000000000111111.  */
-{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
+{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* rtsc b,0 00110bbb01101111RBBB000000011010.  */
-{ "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_ZB }, { 0 }},
+{ "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_ZB }, { 0 }},
 
 /* rtsc 0,0 0011011001101111R111000000011010.  */
-{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_ZB }, { 0 }},
+{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_ZB }, { 0 }},
 
 /* rtsc b,c 00110bbb00101111RBBBCCCCCC011010.  */
-{ "rtsc", 0x302F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "rtsc", 0x302F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* rtsc 0,c 0011011000101111R111CCCCCC011010.  */
-{ "rtsc", 0x362F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }},
+{ "rtsc", 0x362F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }},
 
 /* rtsc b,u6 00110bbb01101111RBBBuuuuuu011010.  */
-{ "rtsc", 0x306F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "rtsc", 0x306F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* rtsc 0,u6 0011011001101111R111uuuuuu011010.  */
-{ "rtsc", 0x366F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }},
+{ "rtsc", 0x366F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }},
 
 /* rtsc b,limm 00110bbb00101111RBBB111110011010.  */
-{ "rtsc", 0x302F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "rtsc", 0x302F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* rtsc 0,limm 0011011000101111R111111110011010.  */
-{ "rtsc", 0x362F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }},
+{ "rtsc", 0x362F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }},
 
 /* rtsc 0011011001101111R111000000011010.  */
-{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { 0 }, { 0 }},
+{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* sat16<.f> b,c 00101bbb00101111FBBBCCCCCC000010.  */
-{ "sat16", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sat16", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sat16<.f> 0,c 0010111000101111F111CCCCCC000010.  */
-{ "sat16", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "sat16", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* sat16<.f> b,u6 00101bbb01101111FBBBuuuuuu000010.  */
-{ "sat16", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sat16", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sat16<.f> 0,u6 0010111001101111F111uuuuuu000010.  */
-{ "sat16", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "sat16", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sat16<.f> b,limm 00101bbb00101111FBBB111110000010.  */
-{ "sat16", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sat16", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sat16<.f> 0,limm 0010111000101111F111111110000010.  */
-{ "sat16", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "sat16", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* sbc<.f> a,b,c 00100bbb00000011FBBBCCCCCCAAAAAA.  */
-{ "sbc", 0x20030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sbc", 0x20030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sbc<.f> 0,b,c 00100bbb00000011FBBBCCCCCC111110.  */
-{ "sbc", 0x2003003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sbc", 0x2003003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sbc<.f><.cc> b,b,c 00100bbb11000011FBBBCCCCCC0QQQQQ.  */
-{ "sbc", 0x20C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "sbc", 0x20C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* sbc<.f> a,b,u6 00100bbb01000011FBBBuuuuuuAAAAAA.  */
-{ "sbc", 0x20430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sbc", 0x20430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sbc<.f> 0,b,u6 00100bbb01000011FBBBuuuuuu111110.  */
-{ "sbc", 0x2043003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sbc", 0x2043003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sbc<.f><.cc> b,b,u6 00100bbb11000011FBBBuuuuuu1QQQQQ.  */
-{ "sbc", 0x20C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sbc", 0x20C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sbc<.f> b,b,s12 00100bbb10000011FBBBssssssSSSSSS.  */
-{ "sbc", 0x20830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "sbc", 0x20830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sbc<.f> a,limm,c 0010011000000011F111CCCCCCAAAAAA.  */
-{ "sbc", 0x26037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sbc", 0x26037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sbc<.f> a,b,limm 00100bbb00000011FBBB111110AAAAAA.  */
-{ "sbc", 0x20030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sbc", 0x20030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sbc<.f> 0,limm,c 0010011000000011F111CCCCCC111110.  */
-{ "sbc", 0x2603703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sbc", 0x2603703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sbc<.f> 0,b,limm 00100bbb00000011FBBB111110111110.  */
-{ "sbc", 0x20030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sbc", 0x20030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sbc<.f><.cc> b,b,limm 00100bbb11000011FBBB1111100QQQQQ.  */
-{ "sbc", 0x20C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "sbc", 0x20C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* sbc<.f><.cc> 0,limm,c 0010011011000011F111CCCCCC0QQQQQ.  */
-{ "sbc", 0x26C37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "sbc", 0x26C37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* sbc<.f> a,limm,u6 0010011001000011F111uuuuuuAAAAAA.  */
-{ "sbc", 0x26437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sbc", 0x26437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sbc<.f> 0,limm,u6 0010011001000011F111uuuuuu111110.  */
-{ "sbc", 0x2643703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sbc", 0x2643703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sbc<.f><.cc> 0,limm,u6 0010011011000011F111uuuuuu1QQQQQ.  */
-{ "sbc", 0x26C37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sbc", 0x26C37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sbc<.f> 0,limm,s12 0010011010000011F111ssssssSSSSSS.  */
-{ "sbc", 0x26837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "sbc", 0x26837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sbc<.f> a,limm,limm 0010011000000011F111111110AAAAAA.  */
-{ "sbc", 0x26037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sbc", 0x26037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sbc<.f> 0,limm,limm 0010011000000011F111111110111110.  */
-{ "sbc", 0x26037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sbc", 0x26037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sbc<.f><.cc> 0,limm,limm 0010011011000011F1111111100QQQQQ.  */
-{ "sbc", 0x26C37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "sbc", 0x26C37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001.  */
-{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001.  */
-{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> b,limm 00100bbb00101111DBBB111110010001.  */
-{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> limm,c 0010011000101111D111CCCCCC010001.  */
-{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> limm,u6 0010011001101111D111uuuuuu010001.  */
-{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* scond<.di> limm,limm 0010011000101111D111111110010001.  */
-{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011.  */
-{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011.  */
-{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* scondd<.di> b,limm 00100bbb00101111DBBB111110010011.  */
-{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
+{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }},
 
 /* seteq<.f> a,b,c 00100bbb00111000FBBBCCCCCCAAAAAA.  */
 { "seteq", 0x20380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -11405,16 +11405,16 @@
 { "seths", 0x26FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* seti c 00100110001011110000CCCCCC111111.  */
-{ "seti", 0x262F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }},
+{ "seti", 0x262F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* seti u6 00100110011011110000uuuuuu111111.  */
-{ "seti", 0x266F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "seti", 0x266F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* seti limm 00100110001011110000111110111111.  */
-{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }},
+{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* seti 00100110011011110000uuuuuu111111.  */
-{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA.  */
 { "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -11657,589 +11657,589 @@
 { "setne", 0x26F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* sexb<.f> b,c 00100bbb00101111FBBBCCCCCC000101.  */
-{ "sexb", 0x202F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sexb", 0x202F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sexb<.f> 0,c 0010011000101111F111CCCCCC000101.  */
-{ "sexb", 0x262F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "sexb", 0x262F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* sexb<.f> b,u6 00100bbb01101111FBBBuuuuuu000101.  */
-{ "sexb", 0x206F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sexb", 0x206F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sexb<.f> 0,u6 0010011001101111F111uuuuuu000101.  */
-{ "sexb", 0x266F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "sexb", 0x266F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sexb<.f> b,limm 00100bbb00101111FBBB111110000101.  */
-{ "sexb", 0x202F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sexb", 0x202F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sexb<.f> 0,limm 0010011000101111F111111110000101.  */
-{ "sexb", 0x262F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "sexb", 0x262F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* sexb_s b,c 01111bbbccc01101.  */
-{ "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* sexh<.f> b,c 00100bbb00101111FBBBCCCCCC000110.  */
-{ "sexh", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sexh", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sexh<.f> 0,c 0010011000101111F111CCCCCC000110.  */
-{ "sexh", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "sexh", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* sexh<.f> b,u6 00100bbb01101111FBBBuuuuuu000110.  */
-{ "sexh", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sexh", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sexh<.f> 0,u6 0010011001101111F111uuuuuu000110.  */
-{ "sexh", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "sexh", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sexh<.f> b,limm 00100bbb00101111FBBB111110000110.  */
-{ "sexh", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sexh", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sexh<.f> 0,limm 0010011000101111F111111110000110.  */
-{ "sexh", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "sexh", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* sexh_s b,c 01111bbbccc01110.  */
-{ "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* sexw<.f> b,c 00100bbb00101111FBBBCCCCCC000110.  */
-{ "sexw", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sexw", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sexw<.f> 0,c 0010011000101111F111CCCCCC000110.  */
-{ "sexw", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "sexw", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* sexw<.f> b,u6 00100bbb01101111FBBBuuuuuu000110.  */
-{ "sexw", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sexw", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sexw<.f> 0,u6 0010011001101111F111uuuuuu000110.  */
-{ "sexw", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "sexw", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sexw<.f> b,limm 00100bbb00101111FBBB111110000110.  */
-{ "sexw", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sexw", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sexw<.f> 0,limm 0010011000101111F111111110000110.  */
-{ "sexw", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "sexw", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* sexw_s b,c 01111bbbccc01110.  */
-{ "sexw_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "sexw_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* sflag c 00110000001011110000CCCCCC111111 */
-{ "sflag", 0x302F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_RC }, { 0 }},
+{ "sflag", 0x302F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* sflag u6 00110000011011110000uuuuuu111111 */
-{ "sflag", 0x306F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "sflag", 0x306F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* sflag limm 00110000001011110000111110111111 */
-{ "sflag", 0x302F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_LIMM }, { 0 }},
+{ "sflag", 0x302F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, CONTROL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* sfxtr<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA.  */
-{ "sfxtr", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sfxtr", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sfxtr<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ.  */
-{ "sfxtr", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "sfxtr", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* sfxtr<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA.  */
-{ "sfxtr", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sfxtr", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sfxtr<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ.  */
-{ "sfxtr", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sfxtr", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sfxtr<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS.  */
-{ "sfxtr", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "sfxtr", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sfxtr<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA.  */
-{ "sfxtr", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sfxtr", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sfxtr<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA.  */
-{ "sfxtr", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sfxtr", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sfxtr<.f><.cc> b,b,limm 00110bbb11101001FBBB1111100QQQQQ.  */
-{ "sfxtr", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "sfxtr", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* sjli u12 00101RRR101000001RRRuuuuuuUUUUUU.  */
 { "sjli", 0x28A08000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, SJLI, CD1, { OPERAND_UIMM12_20 }, { 0 }},
 
 /* sleep c 00100001001011110000CCCCCC111111.  */
-{ "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }},
+{ "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* sleep u6 00100001011011110000uuuuuu111111.  */
-{ "sleep", 0x216F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "sleep", 0x216F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* sleep limm 00100001001011110000111110111111.  */
-{ "sleep", 0x212F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_LIMM }, { 0 }},
+{ "sleep", 0x212F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM }, { 0 }},
 
 /* sleep 00100001011011110000uuuuuu111111.  */
-{ "sleep", 0x216F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
+{ "sleep", 0x216F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* sqrtacc c 00101010001011110000CCCCCC111111.  */
-{ "sqrtacc", 0x2A2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RC }, { 0 }},
+{ "sqrtacc", 0x2A2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* sqrtacc u6 00101010011011110000uuuuuu111111.  */
-{ "sqrtacc", 0x2A6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "sqrtacc", 0x2A6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* sr b,c 00100bbb001010110BBBCCCCCCRRRRRR.  */
-{ "sr", 0x202B0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x202B0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr b,c 00100bbb00101011RBBBCCCCCCRRRRRR.  */
-{ "sr", 0x202B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x202B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr b,u6 00100bbb011010110BBBuuuuuu000000.  */
-{ "sr", 0x206B0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x206B0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr b,u6 00100bbb01101011RBBBuuuuuu000000.  */
-{ "sr", 0x206B0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x206B0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr b,s12 00100bbb101010110BBBssssssSSSSSS.  */
-{ "sr", 0x20AB0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x20AB0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr b,s12 00100bbb10101011RBBBssssssSSSSSS.  */
-{ "sr", 0x20AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x20AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr limm,c 00100110001010110111CCCCCCRRRRRR.  */
-{ "sr", 0x262B7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x262B7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr b,limm 00100bbb001010110BBB111110RRRRRR.  */
-{ "sr", 0x202B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x202B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr limm,c 0010011000101011R111CCCCCCRRRRRR.  */
-{ "sr", 0x262B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x262B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr b,limm 00100bbb00101011RBBB111110RRRRRR.  */
-{ "sr", 0x202B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x202B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr limm,u6 00100110011010110111uuuuuu000000.  */
-{ "sr", 0x266B7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x266B7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr limm,u6 0010011001101011R111uuuuuu000000.  */
-{ "sr", 0x266B7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x266B7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr limm,s12 00100110101010110111ssssssSSSSSS.  */
-{ "sr", 0x26AB7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x26AB7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr limm,s12 0010011010101011R111ssssssSSSSSS.  */
-{ "sr", 0x26AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x26AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr limm,limm 00100110001010110111111110RRRRRR.  */
-{ "sr", 0x262B7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x262B7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }},
 
 /* sr limm,limm 0010011000101011R111111110RRRRRR.  */
-{ "sr", 0x262B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }},
+{ "sr", 0x262B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }},
 
 /* st<.di><.aa><zz> c,b 00011bbb000000000BBBCCCCCCDaaZZR.  */
-{ "st", 0x18000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> c,b 00011bbb000000000BBBCCCCCCDaaZZ0.  */
-{ "st", 0x18000000, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000000, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> w6,b 00011bbb000000000BBBwwwwwwDaaZZ1.  */
-{ "st", 0x18000001, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000001, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZR.  */
-{ "st", 0x18000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZ0.  */
-{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaaZZ1.  */
-{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><zz> c,limm 00011110000000000111CCCCCCDRRZZR.  */
-{ "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }},
+{ "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }},
 
 /* st<.di><zz> c,limm 00011110000000000111CCCCCCDRRZZ0.  */
-{ "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }},
+{ "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }},
 
 /* st<.di><zz> w6,limm 00011110000000000111wwwwwwDRRZZ1.  */
-{ "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }},
+{ "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }},
 
 /* st<.di><.aa><zz> limm,b,s9 00011bbbssssssssSBBB111110DaaZZR.  */
-{ "st", 0x18000F80, 0xF8000FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000F80, 0xF8000FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> limm,b,s9 00011bbbssssssssSBBB111110DaaZZ0.  */
-{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> w6,limm,s9 00011110ssssssssS111wwwwwwDaaZZ1.  */
-{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> limm,limm,s9 00011110ssssssssS111111110DaaZZR.  */
-{ "st", 0x1E007F80, 0xFF007FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x1E007F80, 0xFF007FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* st<.di><.aa><zz> limm,limm,s9 00011110ssssssssS111111110DaaZZ0.  */
-{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
 
 /* stb_s c,b,u5 10101bbbcccuuuuu.  */
-{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
+{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
 
 /* stb_s b,SP,u7 11000bbb011uuuuu.  */
-{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
+{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }},
 
 /* std<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaa110.  */
-{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaa111.  */
-{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110.  */
-{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111.  */
-{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di> c,limm 00011110000000000111CCCCCCDRR110.  */
-{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI26, C_ZZ_D }},
+{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI26, C_ZZ_D }},
 
 /* std<.di> w6,limm 00011110000000000111wwwwwwDRR111.  */
-{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI26, C_ZZ_D }},
+{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI26, C_ZZ_D }},
 
 /* std<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110Daa110.  */
-{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111.  */
-{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> limm,limm,s9 00011110ssssssssS111111110Daa110.  */
-{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* sth_s c,b,u6 10110bbbcccuuuuu.  */
-{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
+{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
 
 /* stm a,u6,b 00101bbb01001101RBBBRuuuuuAAAAAA.  */
-{ "stm", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }},
+{ "stm", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }},
 
 /* stm 0,u6,b 00101bbb01001101RBBBRuuuuu111110.  */
-{ "stm", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }},
+{ "stm", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }},
 
 /* stm a,u6,limm 0010111001001101R111RuuuuuAAAAAA.  */
-{ "stm", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }},
+{ "stm", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }},
 
 /* stm 0,u6,limm 0010111001001101R111Ruuuuu111110.  */
-{ "stm", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }},
+{ "stm", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }},
 
 /* stw_s c,b,u6 10110bbbcccuuuuu.  */
-{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
+{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }},
 
 /* st_s b,SP,u7 11000bbb010uuuuu.  */
-{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
+{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* st_s c,b,u7 10100bbbcccuuuuu.  */
-{ "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
+{ "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* st_s OPERAND_R0,GP,s11 01010SSSSSS10sss.  */
 { "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, CD2, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_13_S, OPERAND_BRAKETdup }, { 0 }},
 
 /* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA.  */
-{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110.  */
-{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ.  */
-{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.  */
-{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110.  */
-{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ.  */
-{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS.  */
-{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA.  */
-{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA.  */
-{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110.  */
-{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110.  */
-{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ.  */
-{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ.  */
-{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA.  */
-{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110.  */
-{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ.  */
-{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS.  */
-{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA.  */
-{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sub<.f> 0,limm,limm 0010011000000010F111111110111110.  */
-{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ.  */
-{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA.  */
-{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110.  */
-{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ.  */
-{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA.  */
-{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110.  */
-{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ.  */
-{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS.  */
-{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA.  */
-{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA.  */
-{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110.  */
-{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110.  */
-{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ.  */
-{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ.  */
-{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA.  */
-{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110.  */
-{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ.  */
-{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS.  */
-{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA.  */
-{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sub1<.f> 0,limm,limm 0010011000010111F111111110111110.  */
-{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ.  */
-{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA.  */
-{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110.  */
-{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ.  */
-{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA.  */
-{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110.  */
-{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ.  */
-{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS.  */
-{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA.  */
-{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA.  */
-{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110.  */
-{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110.  */
-{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ.  */
-{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ.  */
-{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA.  */
-{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110.  */
-{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ.  */
-{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS.  */
-{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA.  */
-{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sub2<.f> 0,limm,limm 0010011000011000F111111110111110.  */
-{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ.  */
-{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA.  */
-{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110.  */
-{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ.  */
-{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA.  */
-{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110.  */
-{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ.  */
-{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS.  */
-{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA.  */
-{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA.  */
-{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110.  */
-{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110.  */
-{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ.  */
-{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ.  */
-{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA.  */
-{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110.  */
-{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ.  */
-{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS.  */
-{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA.  */
-{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sub3<.f> 0,limm,limm 0010011000011001F111111110111110.  */
-{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ.  */
-{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* subsdw<.f> a,b,c 00101bbb00101001FBBBCCCCCCAAAAAA.  */
-{ "subsdw", 0x28290000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "subsdw", 0x28290000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* subsdw<.f> 0,b,c 00101bbb00101001FBBBCCCCCC111110.  */
-{ "subsdw", 0x2829003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "subsdw", 0x2829003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* subsdw<.f><.cc> b,b,c 00101bbb11101001FBBBCCCCCC0QQQQQ.  */
-{ "subsdw", 0x28E90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "subsdw", 0x28E90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* subsdw<.f> a,b,u6 00101bbb01101001FBBBuuuuuuAAAAAA.  */
-{ "subsdw", 0x28690000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "subsdw", 0x28690000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* subsdw<.f> 0,b,u6 00101bbb01101001FBBBuuuuuu111110.  */
-{ "subsdw", 0x2869003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "subsdw", 0x2869003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* subsdw<.f><.cc> b,b,u6 00101bbb11101001FBBBuuuuuu1QQQQQ.  */
-{ "subsdw", 0x28E90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "subsdw", 0x28E90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* subsdw<.f> b,b,s12 00101bbb10101001FBBBssssssSSSSSS.  */
-{ "subsdw", 0x28A90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "subsdw", 0x28A90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* subsdw<.f> a,limm,c 0010111000101001F111CCCCCCAAAAAA.  */
-{ "subsdw", 0x2E297000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "subsdw", 0x2E297000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* subsdw<.f> a,b,limm 00101bbb00101001FBBB111110AAAAAA.  */
-{ "subsdw", 0x28290F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "subsdw", 0x28290F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* subsdw<.f> 0,limm,c 0010111000101001F111CCCCCC111110.  */
-{ "subsdw", 0x2E29703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "subsdw", 0x2E29703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* subsdw<.f> 0,b,limm 00101bbb00101001FBBB111110111110.  */
-{ "subsdw", 0x28290FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "subsdw", 0x28290FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* subsdw<.f><.cc> b,b,limm 00101bbb11101001FBBB1111100QQQQQ.  */
-{ "subsdw", 0x28E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "subsdw", 0x28E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* subsdw<.f><.cc> 0,limm,c 0010111011101001F111CCCCCC0QQQQQ.  */
-{ "subsdw", 0x2EE97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "subsdw", 0x2EE97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* subsdw<.f> a,limm,u6 0010111001101001F111uuuuuuAAAAAA.  */
-{ "subsdw", 0x2E697000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "subsdw", 0x2E697000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* subsdw<.f> 0,limm,u6 0010111001101001F111uuuuuu111110.  */
-{ "subsdw", 0x2E69703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "subsdw", 0x2E69703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* subsdw<.f><.cc> 0,limm,u6 0010111011101001F111uuuuuu1QQQQQ.  */
-{ "subsdw", 0x2EE97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "subsdw", 0x2EE97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* subsdw<.f> 0,limm,s12 0010111010101001F111ssssssSSSSSS.  */
-{ "subsdw", 0x2EA97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "subsdw", 0x2EA97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* subsdw<.f> a,limm,limm 0010111000101001F111111110AAAAAA.  */
-{ "subsdw", 0x2E297F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "subsdw", 0x2E297F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* subsdw<.f> 0,limm,limm 0010111000101001F111111110111110.  */
-{ "subsdw", 0x2E297FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "subsdw", 0x2E297FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* subsdw<.f><.cc> 0,limm,limm 0010111011101001F1111111100QQQQQ.  */
-{ "subsdw", 0x2EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "subsdw", 0x2EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* sub_s b,b,c 01111bbbccc00010.  */
-{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
+{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* sub_s a,b,c 01001bbbccc10aaa.  */
 { "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, CD2, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* sub_s c,b,u3 01101bbbccc01uuu.  */
-{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }},
+{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }},
 
 /* sub_s b,b,u5 10111bbb011uuuuu.  */
-{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
+{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }},
 
 /* sub_s SP,SP,u7 11000001101uuuuu.  */
-{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM7_A32_11_S }, { 0 }},
+{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM7_A32_11_S }, { 0 }},
 
 /* sub_s.ne b,b,b 01111bbb11000000.  */
-{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RB_Sdup }, { C_NE, C_CC_NE }},
+{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RB_Sdup }, { C_NE, C_CC_NE }},
 
 /* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000.  */
 { "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -12278,109 +12278,109 @@
 { "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* swi  00100010011011110000000000111111.  */
-{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
+{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* swi_s  0111101011100000.  */
-{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
+{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* swi_s u6 01111uuuuuu11111.  */
-{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_5_S }, { 0 }},
+{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_5_S }, { 0 }},
 
 /* sync  00100011011011110000000000111111.  */
-{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* trap0  00100010011011110000000000111111.  */
-{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { 0 }, { 0 }},
+{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* trap_s u6 01111uuuuuu11110.  */
-{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_5_S }, { 0 }},
+{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_5_S }, { 0 }},
 
 /* tst b,c 00100bbb000010111BBBCCCCCCRRRRRR.  */
-{ "tst", 0x200B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "tst", 0x200B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* tst b,c 00100bbb000010111BBBCCCCCC000000.  */
-{ "tst", 0x200B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "tst", 0x200B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* tst<.cc> b,c 00100bbb110010111BBBCCCCCC0QQQQQ.  */
-{ "tst", 0x20CB8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
+{ "tst", 0x20CB8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }},
 
 /* tst b,u6 00100bbb010010111BBBuuuuuuRRRRRR.  */
-{ "tst", 0x204B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "tst", 0x204B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* tst b,u6 00100bbb010010111BBBuuuuuu000000.  */
-{ "tst", 0x204B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "tst", 0x204B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* tst<.cc> b,u6 00100bbb110010111BBBuuuuuu1QQQQQ.  */
-{ "tst", 0x20CB8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
+{ "tst", 0x20CB8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* tst b,s12 00100bbb100010111BBBssssssSSSSSS.  */
-{ "tst", 0x208B8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
+{ "tst", 0x208B8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }},
 
 /* tst limm,c 00100110000010111111CCCCCCRRRRRR.  */
-{ "tst", 0x260BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "tst", 0x260BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* tst b,limm 00100bbb000010111BBB111110RRRRRR.  */
-{ "tst", 0x200B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "tst", 0x200B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* tst limm,c 00100110000010111111CCCCCC000000.  */
-{ "tst", 0x260BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "tst", 0x260BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* tst b,limm 00100bbb000010111BBB111110000000.  */
-{ "tst", 0x200B8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "tst", 0x200B8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* tst<.cc> b,limm 00100bbb110010111BBB1111100QQQQQ.  */
-{ "tst", 0x20CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
+{ "tst", 0x20CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }},
 
 /* tst<.cc> limm,c 00100110110010111111CCCCCC0QQQQQ.  */
-{ "tst", 0x26CBF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "tst", 0x26CBF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* tst limm,u6 00100110010010111111uuuuuuRRRRRR.  */
-{ "tst", 0x264BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "tst", 0x264BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* tst limm,u6 00100110010010111111uuuuuu000000.  */
-{ "tst", 0x264BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "tst", 0x264BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* tst<.cc> limm,u6 00100110110010111111uuuuuu1QQQQQ.  */
-{ "tst", 0x26CBF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "tst", 0x26CBF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* tst limm,s12 00100110100010111111ssssssSSSSSS.  */
-{ "tst", 0x268BF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "tst", 0x268BF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* tst limm,limm 00100110000010111111111110RRRRRR.  */
-{ "tst", 0x260BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "tst", 0x260BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* tst limm,limm 00100110000010111111111110000000.  */
-{ "tst", 0x260BFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "tst", 0x260BFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* tst<.cc> limm,limm 001001101100101111111111100QQQQQ.  */
-{ "tst", 0x26CBFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "tst", 0x26CBFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* tst_s b,c 01111bbbccc01011.  */
-{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
+{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }},
 
 /* unimp_s  0111100111100000.  */
-{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
+{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { 0 }, { 0 }},
 
 /* upkqb<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA.  */
-{ "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* upkqb<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ.  */
-{ "upkqb", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "upkqb", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* upkqb<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA.  */
-{ "upkqb", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "upkqb", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* upkqb<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS.  */
-{ "upkqb", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "upkqb", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* upkqb<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA.  */
-{ "upkqb", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "upkqb", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* upkqb<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA.  */
-{ "upkqb", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "upkqb", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* upkqb<.f><.cc> b,b,limm 00110bbb11100001FBBB1111100QQQQQ.  */
-{ "upkqb", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "upkqb", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA.  */
 { "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
@@ -12743,163 +12743,163 @@
 { "vaddsub4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001010.  */
-{ "vbfdw", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }},
+{ "vbfdw", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }},
 
 /* vbfdw<.f> 0,c 0010111000101111F111CCCCCC001010.  */
-{ "vbfdw", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
+{ "vbfdw", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }},
 
 /* vbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001010.  */
-{ "vbfdw", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }},
+{ "vbfdw", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }},
 
 /* vbfdw<.f> 0,u6 0010111001101111F111uuuuuu001010.  */
-{ "vbfdw", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
+{ "vbfdw", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }},
 
 /* vbfdw<.f> b,limm 00101bbb00101111FBBB111110001010.  */
-{ "vbfdw", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }},
+{ "vbfdw", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }},
 
 /* vbfdw<.f> 0,limm 0010111000101111F111111110001010.  */
-{ "vbfdw", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
+{ "vbfdw", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }},
 
 /* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA.  */
-{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110.  */
-{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ.  */
-{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
+{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
 
 /* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA.  */
-{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20_SPLITH }, { 0 }},
+{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20_SPLITH }, { 0 }},
 
 /* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110.  */
-{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20_SPLITH }, { 0 }},
+{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20_SPLITH }, { 0 }},
 
 /* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ.  */
-{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20_SPLITH }, { C_CC }},
+{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20_SPLITH }, { C_CC }},
 
 /* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS.  */
-{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20_SPLITH }, { 0 }},
+{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20_SPLITH }, { 0 }},
 
 /* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA.  */
-{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA.  */
-{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vmac2h 0,limm,c 00101110000111100111CCCCCC111110.  */
-{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vmac2h 0,b,limm 00101bbb000111100BBB111110111110.  */
-{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ.  */
-{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
+{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
 
 /* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ.  */
-{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA.  */
-{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { 0 }},
+{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { 0 }},
 
 /* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110.  */
-{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { 0 }},
+{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { 0 }},
 
 /* vmac2h<.cc> 0,limm,u6 00101110110111100111uuuuuu1QQQQQ.  */
-{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { C_CC }},
+{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { C_CC }},
 
 /* vmac2h 0,limm,s12 00101110100111100111ssssssSSSSSS.  */
-{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20_SPLITH }, { 0 }},
+{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20_SPLITH }, { 0 }},
 
 /* vmac2h a,limm,limm 00101110000111100111111110AAAAAA.  */
-{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vmac2h 0,limm,limm 00101110000111100111111110111110.  */
-{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vmac2h<.cc> 0,limm,limm 001011101101111001111111100QQQQQ.  */
-{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vmac2hu a,b,c 00101bbb000111110BBBCCCCCCAAAAAA.  */
-{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmac2hu 0,b,c 00101bbb000111110BBBCCCCCC111110.  */
-{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmac2hu<.cc> b,b,c 00101bbb110111110BBBCCCCCC0QQQQQ.  */
-{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
+{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
 
 /* vmac2hu a,b,u6 00101bbb010111110BBBuuuuuuAAAAAA.  */
-{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20_SPLITH }, { 0 }},
+{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20_SPLITH }, { 0 }},
 
 /* vmac2hu 0,b,u6 00101bbb010111110BBBuuuuuu111110.  */
-{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20_SPLITH }, { 0 }},
+{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20_SPLITH }, { 0 }},
 
 /* vmac2hu<.cc> b,b,u6 00101bbb110111110BBBuuuuuu1QQQQQ.  */
-{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20_SPLITH }, { C_CC }},
+{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20_SPLITH }, { C_CC }},
 
 /* vmac2hu b,b,s12 00101bbb100111110BBBssssssSSSSSS.  */
-{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20_SPLITH }, { 0 }},
+{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20_SPLITH }, { 0 }},
 
 /* vmac2hu a,limm,c 00101110000111110111CCCCCCAAAAAA.  */
-{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vmac2hu a,b,limm 00101bbb000111110BBB111110AAAAAA.  */
-{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vmac2hu 0,limm,c 00101110000111110111CCCCCC111110.  */
-{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vmac2hu 0,b,limm 00101bbb000111110BBB111110111110.  */
-{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vmac2hu<.cc> b,b,limm 00101bbb110111110BBB1111100QQQQQ.  */
-{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
+{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
 
 /* vmac2hu<.cc> 0,limm,c 00101110110111110111CCCCCC0QQQQQ.  */
-{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* vmac2hu a,limm,u6 00101110010111110111uuuuuuAAAAAA.  */
-{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { 0 }},
+{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { 0 }},
 
 /* vmac2hu 0,limm,u6 00101110010111110111uuuuuu111110.  */
-{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { 0 }},
+{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { 0 }},
 
 /* vmac2hu<.cc> 0,limm,u6 00101110110111110111uuuuuu1QQQQQ.  */
-{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { C_CC }},
+{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20_SPLITH }, { C_CC }},
 
 /* vmac2hu 0,limm,s12 00101110100111110111ssssssSSSSSS.  */
-{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20_SPLITH }, { 0 }},
+{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20_SPLITH }, { 0 }},
 
 /* vmac2hu a,limm,limm 00101110000111110111111110AAAAAA.  */
-{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vmac2hu 0,limm,limm 00101110000111110111111110111110.  */
-{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vmac2hu<.cc> 0,limm,limm 001011101101111101111111100QQQQQ.  */
-{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA.  */
-{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110.  */
-{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ.  */
-{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
 
 /* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA.  */
 { "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA.  */
-{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110.  */
-{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ.  */
-{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA.  */
 { "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
@@ -12911,28 +12911,28 @@
 { "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS.  */
-{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS.  */
 { "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA.  */
-{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA.  */
-{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110.  */
-{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110.  */
-{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ.  */
-{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
 
 /* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ.  */
-{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA.  */
 { "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
@@ -12953,13 +12953,13 @@
 { "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA.  */
-{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110.  */
-{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ.  */
-{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA.  */
 { "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
@@ -12971,19 +12971,19 @@
 { "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS.  */
-{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS.  */
 { "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA.  */
-{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vmpy2h 0,limm,limm 00101110000111000111111110111110.  */
-{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ.  */
-{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA.  */
 { "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
@@ -12995,13 +12995,13 @@
 { "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA.  */
-{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110.  */
-{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ.  */
-{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
 
 /* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA.  */
 { "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
@@ -13013,13 +13013,13 @@
 { "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
 
 /* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA.  */
-{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110.  */
-{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ.  */
-{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA.  */
 { "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
@@ -13031,28 +13031,28 @@
 { "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS.  */
-{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS.  */
 { "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA.  */
-{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA.  */
-{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110.  */
-{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110.  */
-{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ.  */
-{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
 
 /* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ.  */
-{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA.  */
 { "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }},
@@ -13073,13 +13073,13 @@
 { "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA.  */
-{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110.  */
-{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ.  */
-{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA.  */
 { "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
@@ -13091,19 +13091,19 @@
 { "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS.  */
-{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS.  */
 { "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA.  */
-{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vmpy2hu 0,limm,limm 00101110000111010111111110111110.  */
-{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ.  */
-{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA.  */
 { "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
@@ -13115,124 +13115,124 @@
 { "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vpack2hl 0,b,c 00101bbb001010010BBBCCCCCC111110 */
-{ "vpack2hl", 0x2829003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vpack2hl", 0x2829003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vpack2hl a,b,c 00101bbb001010010BBBCCCCCCAAAAAA */
-{ "vpack2hl", 0x28290000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vpack2hl", 0x28290000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vpack2hl<.cc> b,b,c 00101bbb111010010BBBCCCCCC0QQQQQ */
-{ "vpack2hl", 0x28E90000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
+{ "vpack2hl", 0x28E90000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
 
 /* vpack2hl<.cc> b,b,u6 00101bbb111010010BBBuuuuuu1QQQQQ */
-{ "vpack2hl", 0x28E90020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
+{ "vpack2hl", 0x28E90020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vpack2hl a,b,u6 00101bbb011010010BBBuuuuuuAAAAAA */
-{ "vpack2hl", 0x28690000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "vpack2hl", 0x28690000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vpack2hl 0,b,u6 00101bbb011010010BBBuuuuuu111110 */
-{ "vpack2hl", 0x2869003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "vpack2hl", 0x2869003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vpack2hl b,b,s12 00101bbb101010010BBBssssssSSSSSS */
-{ "vpack2hl", 0x28A90000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
+{ "vpack2hl", 0x28A90000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vpack2hl<.cc> 0,limm,c 00101110111010010111CCCCCC0QQQQQ */
-{ "vpack2hl", 0x2EE97000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "vpack2hl", 0x2EE97000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* vpack2hl 0,limm,c 00101110011010010111CCCCCC111110 */
-{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vpack2hl a,b,limm 00101bbb001010010BBB111110AAAAAA */
-{ "vpack2hl", 0x28290F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vpack2hl", 0x28290F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vpack2hl a,limm,c 00101110001010010111CCCCCCAAAAAA */
-{ "vpack2hl", 0x2E297000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vpack2hl", 0x2E297000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vpack2hl 0,b,limm 00101bbb001010010BBB111110111110 */
-{ "vpack2hl", 0x28290FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vpack2hl", 0x28290FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vpack2hl<.cc> b,b,limm 00101bbb111010010BBB1111100QQQQQ */
-{ "vpack2hl", 0x28E90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
+{ "vpack2hl", 0x28E90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
 
 /* vpack2hl a,limm,u6 00101110011010010111uuuuuuAAAAAA */
-{ "vpack2hl", 0x2E697000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "vpack2hl", 0x2E697000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vpack2hl 0,limm,u6 00101110011010010111uuuuuu111110 */
-{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vpack2hl<.cc> 0,limm,u6 00101110111010010111uuuuuu1QQQQQ */
-{ "vpack2hl", 0x2EE97020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "vpack2hl", 0x2EE97020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vpack2hl 0,limm,s12 00101110101010010111ssssssSSSSSS */
-{ "vpack2hl", 0x2EA97000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "vpack2hl", 0x2EA97000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vpack2hl<.cc> 0,limm,limm 001011101110100101111111100QQQQQ */
-{ "vpack2hl", 0x2EE97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "vpack2hl", 0x2EE97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vpack2hl a,limm,limm 00101110001010010111111110AAAAAA */
-{ "vpack2hl", 0x2E297F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vpack2hl", 0x2E297F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vpack2hl 0,limm,limm 00101110001010010111111110111110 */
-{ "vpack2hl", 0x2E297FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vpack2hl", 0x2E297FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vpack2hm a,b,c 00101bbb001010011BBBCCCCCCAAAAAA */
-{ "vpack2hm", 0x28298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vpack2hm", 0x28298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vpack2hm<.cc> b,b,c 00101bbb111010011BBBCCCCCC0QQQQQ */
-{ "vpack2hm", 0x28E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
+{ "vpack2hm", 0x28E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }},
 
 /* vpack2hm 0,b,c 00101bbb001010011BBBCCCCCC111110 */
-{ "vpack2hm", 0x2829803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
+{ "vpack2hm", 0x2829803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }},
 
 /* vpack2hm a,b,u6 00101bbb011010011BBBuuuuuuAAAAAA */
-{ "vpack2hm", 0x28698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "vpack2hm", 0x28698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vpack2hm 0,b,u6 00101bbb011010011BBBuuuuuu111110 */
-{ "vpack2hm", 0x2869803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
+{ "vpack2hm", 0x2869803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vpack2hm<.cc> b,b,u6 00101bbb111010011BBBuuuuuu1QQQQQ */
-{ "vpack2hm", 0x28E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
+{ "vpack2hm", 0x28E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vpack2hm b,b,s12 00101bbb101010011BBBssssssSSSSSS */
-{ "vpack2hm", 0x28A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
+{ "vpack2hm", 0x28A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vpack2hm a,b,limm 00101bbb001010011BBB111110AAAAAA */
-{ "vpack2hm", 0x28298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vpack2hm", 0x28298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vpack2hm 0,b,limm 00101bbb001010011BBB111110111110 */
-{ "vpack2hm", 0x28298FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
+{ "vpack2hm", 0x28298FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }},
 
 /* vpack2hm<.cc> 0,limm,c 00101110111010011111CCCCCC0QQQQQ */
-{ "vpack2hm", 0x2EE9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
+{ "vpack2hm", 0x2EE9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }},
 
 /* vpack2hm<.cc> b,b,limm 00101bbb111010011BBB1111100QQQQQ */
-{ "vpack2hm", 0x28E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
+{ "vpack2hm", 0x28E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }},
 
 /* vpack2hm a,limm,c 00101110001010011111CCCCCCAAAAAA */
-{ "vpack2hm", 0x2E29F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vpack2hm", 0x2E29F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vpack2hm 0,limm,c 00101110011010011111CCCCCC111110 */
-{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
+{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }},
 
 /* vpack2hm a,limm,u6 00101110011010011111uuuuuuAAAAAA */
-{ "vpack2hm", 0x2E69F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "vpack2hm", 0x2E69F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vpack2hm 0,limm,u6 00101110011010011111uuuuuu111110 */
-{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
+{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }},
 
 /* vpack2hm<.cc> 0,limm,u6 00101110111010011111uuuuuu1QQQQQ */
-{ "vpack2hm", 0x2EE9F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
+{ "vpack2hm", 0x2EE9F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }},
 
 /* vpack2hm 0,limm,s12 00101110101010011111ssssssSSSSSS */
-{ "vpack2hm", 0x2EA9F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
+{ "vpack2hm", 0x2EA9F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }},
 
 /* vpack2hm a,limm,limm 00101110001010011111111110AAAAAA */
-{ "vpack2hm", 0x2E29FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vpack2hm", 0x2E29FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vpack2hm 0,limm,limm 00101110001010011111111110111110 */
-{ "vpack2hm", 0x2E29FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
+{ "vpack2hm", 0x2E29FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }},
 
 /* vpack2hm<.cc> 0,limm,limm 001011101110100111111111100QQQQQ */
-{ "vpack2hm", 0x2EE9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
+{ "vpack2hm", 0x2EE9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* vsub2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA.  */
 { "vsub2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }},
@@ -13595,16 +13595,16 @@
 { "vsubadd4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }},
 
 /* wevt c 00100000001011110001CCCCCC111111.  */
-{ "wevt", 0x202F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }},
+{ "wevt", 0x202F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* wevt u6 00100000011011110001uuuuuu111111.  */
-{ "wevt", 0x206F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "wevt", 0x206F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* wlfc c 00100001001011110001CCCCCC111111.  */
-{ "wlfc", 0x212F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }},
+{ "wlfc", 0x212F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RC }, { 0 }},
 
 /* wlfc u6 00100001011011110001uuuuuu111111.  */
-{ "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }},
+{ "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, ARC_INSN_SUBCLASS_NONE, { OPERAND_UIMM6_20 }, { 0 }},
 
 /* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA.  */
 { "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
@@ -13667,89 +13667,89 @@
 { "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA.  */
-{ "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* xor<.f> 0,b,c 00100bbb00000111FBBBCCCCCC111110.  */
-{ "xor", 0x2007003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "xor", 0x2007003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* xor<.f><.cc> b,b,c 00100bbb11000111FBBBCCCCCC0QQQQQ.  */
-{ "xor", 0x20C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "xor", 0x20C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* xor<.f> a,b,u6 00100bbb01000111FBBBuuuuuuAAAAAA.  */
-{ "xor", 0x20470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "xor", 0x20470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* xor<.f> 0,b,u6 00100bbb01000111FBBBuuuuuu111110.  */
-{ "xor", 0x2047003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "xor", 0x2047003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* xor<.f><.cc> b,b,u6 00100bbb11000111FBBBuuuuuu1QQQQQ.  */
-{ "xor", 0x20C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "xor", 0x20C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* xor<.f> b,b,s12 00100bbb10000111FBBBssssssSSSSSS.  */
-{ "xor", 0x20870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "xor", 0x20870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* xor<.f> a,limm,c 0010011000000111F111CCCCCCAAAAAA.  */
-{ "xor", 0x26077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "xor", 0x26077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* xor<.f> a,b,limm 00100bbb00000111FBBB111110AAAAAA.  */
-{ "xor", 0x20070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "xor", 0x20070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* xor<.f> 0,limm,c 0010011000000111F111CCCCCC111110.  */
-{ "xor", 0x2607703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "xor", 0x2607703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* xor<.f> 0,b,limm 00100bbb00000111FBBB111110111110.  */
-{ "xor", 0x20070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "xor", 0x20070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* xor<.f><.cc> 0,limm,c 0010011011000111F111CCCCCC0QQQQQ.  */
-{ "xor", 0x26C77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
+{ "xor", 0x26C77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }},
 
 /* xor<.f><.cc> b,b,limm 00100bbb11000111FBBB1111100QQQQQ.  */
-{ "xor", 0x20C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "xor", 0x20C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
 
 /* xor<.f> a,limm,u6 0010011001000111F111uuuuuuAAAAAA.  */
-{ "xor", 0x26477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "xor", 0x26477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* xor<.f> 0,limm,u6 0010011001000111F111uuuuuu111110.  */
-{ "xor", 0x2647703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
+{ "xor", 0x2647703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }},
 
 /* xor<.f><.cc> 0,limm,u6 0010011011000111F111uuuuuu1QQQQQ.  */
-{ "xor", 0x26C77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "xor", 0x26C77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* xor<.f> 0,limm,s12 0010011010000111F111ssssssSSSSSS.  */
-{ "xor", 0x26877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
+{ "xor", 0x26877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }},
 
 /* xor<.f> a,limm,limm 0010011000000111F111111110AAAAAA.  */
-{ "xor", 0x26077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "xor", 0x26077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* xor<.f> 0,limm,limm 0010011000000111F111111110111110.  */
-{ "xor", 0x26077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
+{ "xor", 0x26077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }},
 
 /* xor<.f><.cc> 0,limm,limm 0010011011000111F1111111100QQQQQ.  */
-{ "xor", 0x26C77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
+{ "xor", 0x26C77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }},
 
 /* xor_s b,b,c 01111bbbccc00111.  */
-{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
+{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }},
 
 /* xpkqb<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA.  */
-{ "xpkqb", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
+{ "xpkqb", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }},
 
 /* xpkqb<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ.  */
-{ "xpkqb", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
+{ "xpkqb", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }},
 
 /* xpkqb<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA.  */
-{ "xpkqb", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
+{ "xpkqb", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }},
 
 /* xpkqb<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ.  */
-{ "xpkqb", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
+{ "xpkqb", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }},
 
 /* xpkqb<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS.  */
 
-{ "xpkqb", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
+{ "xpkqb", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }},
 
 /* xpkqb<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA.  */
-{ "xpkqb", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
+{ "xpkqb", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }},
 
 /* xpkqb<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA.  */
-{ "xpkqb", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
+{ "xpkqb", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }},
 
 /* xpkqb<.f><.cc> b,b,limm 00110bbb11100010FBBB1111100QQQQQ.  */
-{ "xpkqb", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
+{ "xpkqb", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, ARC_INSN_SUBCLASS_NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }},
diff --git a/target/arc/decoder_fragments/arc64-tbl.h b/target/arc/decoder_fragments/arc64-tbl.h
index 7b32488a634..2109d221a37 100644
--- a/target/arc/decoder_fragments/arc64-tbl.h
+++ b/target/arc/decoder_fragments/arc64-tbl.h
@@ -1,962 +1,962 @@
 /* stl<.aa> RC,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxx0xx111 */
-{ "stl", 0x18000007, 0xf8000027, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
+{ "stl", 0x18000007, 0xf8000027, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
 
 /* stl<.aa> W6,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxx1xx111 */
-{ "stl", 0x18000027, 0xf8000027, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
+{ "stl", 0x18000027, 0xf8000027, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
 
 /* stl RC,BRAKET,XIMM,BRAKETdup 00011100000000000111xxxxxx000111 */
-{ "stl", 0x1c007007, 0xfffff03f, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
+{ "stl", 0x1c007007, 0xfffff03f, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { RC, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
 
 /* stl W6,BRAKET,XIMM,BRAKETdup 00011100000000000111xxxxxx100111 */
-{ "stl", 0x1c007027, 0xfffff03f, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
+{ "stl", 0x1c007027, 0xfffff03f, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
 
 /* stl RC,BRAKET,LIMM,BRAKETdup 00011110000000000111xxxxxx000111 */
-{ "stl", 0x1e007007, 0xfffff03f, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
+{ "stl", 0x1e007007, 0xfffff03f, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
 
 /* stl W6,BRAKET,LIMM,BRAKETdup 00011110000000000111xxxxxx100111 */
-{ "stl", 0x1e007027, 0xfffff03f, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
+{ "stl", 0x1e007027, 0xfffff03f, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
 
 /* stl<.aa> XIMM,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxx111100xxx111 */
-{ "stl", 0x18000f07, 0xf8000fc7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
+{ "stl", 0x18000f07, 0xf8000fc7, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
 
 /* stl<.aa> LIMM,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxx111110xxx111 */
-{ "stl", 0x18000f87, 0xf8000fc7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
+{ "stl", 0x18000f87, 0xf8000fc7, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
 
 /* stdl<.aa> RCD,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxx1xx110 */
-{ "stdl", 0x18000026, 0xf8000027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
+{ "stdl", 0x18000026, 0xf8000027, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
 
 /* stdl<.aa> W6,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxx1xx101 */
-{ "stdl", 0x18000025, 0xf8000027, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
+{ "stdl", 0x18000025, 0xf8000027, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
 
 /* stdl RCD,BRAKET,XIMM,BRAKETdup 00011100xxxxxxxxx111xxxxxx1xx110 */
-{ "stdl", 0x1c007026, 0xff007027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
+{ "stdl", 0x1c007026, 0xff007027, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { RCD, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
 
 /* stdl W6,BRAKET,XIMM,BRAKETdup 00011100xxxxxxxxx111xxxxxx1xx101 */
-{ "stdl", 0x1c007025, 0xff007027, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
+{ "stdl", 0x1c007025, 0xff007027, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
 
 /* stdl RCD,BRAKET,LIMM,BRAKETdup 00011110xxxxxxxxx111xxxxxx1xx110 */
-{ "stdl", 0x1e007026, 0xff007027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
+{ "stdl", 0x1e007026, 0xff007027, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
 
 /* stdl W6,BRAKET,LIMM,BRAKETdup 00011110xxxxxxxxx111xxxxxx1xx101 */
-{ "stdl", 0x1e007025, 0xff007027, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
+{ "stdl", 0x1e007025, 0xff007027, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L, C_AS27 } }
 
 /* stdl<.aa> XIMM,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxx111100xxx110 */
-{ "stdl", 0x18000f26, 0xf8000fe7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
+{ "stdl", 0x18000f26, 0xf8000fe7, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
 
 /* stdl<.aa> LIMM,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxx111110xxx110 */
-{ "stdl", 0x18000fa6, 0xf8000fe7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
+{ "stdl", 0x18000fa6, 0xf8000fe7, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 } }
 
 /* abs<.f> RB,RC 00100xxx00101111xxxxxxxxxx001001 */
-{ "abs", 0x202f0009, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "abs", 0x202f0009, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* abs<.f> ZA,RC 0010011000101111x111xxxxxx001001 */
-{ "abs", 0x262f7009, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "abs", 0x262f7009, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* abs<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx001001 */
-{ "abs", 0x206f0009, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "abs", 0x206f0009, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* abs<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx001001 */
-{ "abs", 0x266f7009, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "abs", 0x266f7009, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* abs<.f> RB,LIMM 00100xxx00101111xxxx111110001001 */
-{ "abs", 0x202f0f89, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "abs", 0x202f0f89, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* abs<.f> ZA,LIMM 0010011000101111x111111110001001 */
-{ "abs", 0x262f7f89, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "abs", 0x262f7f89, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* absl<.f> RB,RC 01011xxx00101111xxxxxxxxxx001001 */
-{ "absl", 0x582f0009, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "absl", 0x582f0009, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* absl<.f> ZA,RC 0101111000101111x111xxxxxx001001 */
-{ "absl", 0x5e2f7009, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "absl", 0x5e2f7009, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* absl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx001001 */
-{ "absl", 0x586f0009, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "absl", 0x586f0009, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* absl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx001001 */
-{ "absl", 0x5e6f7009, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "absl", 0x5e6f7009, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* absl<.f> RB,XIMM 01011xxx00101111xxxx111100001001 */
-{ "absl", 0x582f0f09, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "absl", 0x582f0f09, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* absl<.f> ZA,XIMM 0101111000101111x111111100001001 */
-{ "absl", 0x5e2f7f09, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "absl", 0x5e2f7f09, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* absl<.f> RB,LIMM 01011xxx00101111xxxx111110001001 */
-{ "absl", 0x582f0f89, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "absl", 0x582f0f89, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* absl<.f> ZA,LIMM 0101111000101111x111111110001001 */
-{ "absl", 0x5e2f7f89, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "absl", 0x5e2f7f89, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* abs_s RB_S,RC_S 01111xxxxxx10001 */
-{ "abs_s", 0x00007811, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RC_S }, { 0 } }
+{ "abs_s", 0x00007811, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* adc<.f> RA,RB,RC 00100xxx00000001xxxxxxxxxxxxxxxx */
-{ "adc", 0x20010000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "adc", 0x20010000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* adc<.f> ZA,RB,RC 00100xxx00000001xxxxxxxxxx111110 */
-{ "adc", 0x2001003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "adc", 0x2001003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* adc<.f><.cc> RB,RBdup,RC 00100xxx11000001xxxxxxxxxx0xxxxx */
-{ "adc", 0x20c10000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "adc", 0x20c10000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* adc<.f> RA,RB,UIMM6_20 00100xxx01000001xxxxxxxxxxxxxxxx */
-{ "adc", 0x20410000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "adc", 0x20410000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* adc<.f> ZA,RB,UIMM6_20 00100xxx01000001xxxxxxxxxx111110 */
-{ "adc", 0x2041003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "adc", 0x2041003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* adc<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11000001xxxxxxxxxx1xxxxx */
-{ "adc", 0x20c10020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "adc", 0x20c10020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* adc<.f> RB,RBdup,SIMM12_20 00100xxx10000001xxxxxxxxxxxxxxxx */
-{ "adc", 0x20810000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "adc", 0x20810000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* adc<.f> RA,LIMM,RC 0010011000000001x111xxxxxxxxxxxx */
-{ "adc", 0x26017000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "adc", 0x26017000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* adc<.f> RA,RB,LIMM 00100xxx00000001xxxx111110xxxxxx */
-{ "adc", 0x20010f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "adc", 0x20010f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* adc<.f> ZA,LIMM,RC 0010011000000001x111xxxxxx111110 */
-{ "adc", 0x2601703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "adc", 0x2601703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* adc<.f> ZA,RB,LIMM 00100xxx00000001xxxx111110111110 */
-{ "adc", 0x20010fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "adc", 0x20010fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* adc<.f><.cc> RB,RBdup,LIMM 00100xxx11000001xxxx1111100xxxxx */
-{ "adc", 0x20c10f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "adc", 0x20c10f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* adc<.f><.cc> ZA,LIMM,RC 0010011011000001x111xxxxxx0xxxxx */
-{ "adc", 0x26c17000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "adc", 0x26c17000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* adc<.f> RA,LIMM,UIMM6_20 0010011001000001x111xxxxxxxxxxxx */
-{ "adc", 0x26417000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "adc", 0x26417000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* adc<.f> ZA,LIMM,UIMM6_20 0010011001000001x111xxxxxx111110 */
-{ "adc", 0x2641703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "adc", 0x2641703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* adc<.f><.cc> ZA,LIMM,UIMM6_20 0010011011000001x111xxxxxx1xxxxx */
-{ "adc", 0x26c17020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "adc", 0x26c17020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* adc<.f> ZA,LIMM,SIMM12_20 0010011010000001x111xxxxxxxxxxxx */
-{ "adc", 0x26817000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "adc", 0x26817000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* adc<.f> RA,LIMM,LIMMdup 0010011000000001x111111110xxxxxx */
-{ "adc", 0x26017f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "adc", 0x26017f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* adc<.f> ZA,LIMM,LIMMdup 0010011000000001x111111110111110 */
-{ "adc", 0x26017fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "adc", 0x26017fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* adc<.f><.cc> ZA,LIMM,LIMMdup 0010011011000001x1111111100xxxxx */
-{ "adc", 0x26c17f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "adc", 0x26c17f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* adcl<.f> RA,RB,RC 01011xxx00000001xxxxxxxxxxxxxxxx */
-{ "adcl", 0x58010000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "adcl", 0x58010000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* adcl<.f> ZA,RB,RC 01011xxx00000001xxxxxxxxxx111110 */
-{ "adcl", 0x5801003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "adcl", 0x5801003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* adcl<.f><.cc> RB,RBdup,RC 01011xxx11000001xxxxxxxxxx0xxxxx */
-{ "adcl", 0x58c10000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "adcl", 0x58c10000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* adcl<.f> RA,RB,UIMM6_20 01011xxx01000001xxxxxxxxxxxxxxxx */
-{ "adcl", 0x58410000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "adcl", 0x58410000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* adcl<.f> ZA,RB,UIMM6_20 01011xxx01000001xxxxxxxxxx111110 */
-{ "adcl", 0x5841003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "adcl", 0x5841003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* adcl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11000001xxxxxxxxxx1xxxxx */
-{ "adcl", 0x58c10020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "adcl", 0x58c10020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* adcl<.f> RB,RBdup,SIMM12_20 01011xxx10000001xxxxxxxxxxxxxxxx */
-{ "adcl", 0x58810000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "adcl", 0x58810000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* adcl<.f> RA,XIMM,RC 0101110000000001x111xxxxxxxxxxxx */
-{ "adcl", 0x5c017000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "adcl", 0x5c017000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* adcl<.f> RA,RB,XIMM 01011xxx00000001xxxx111100xxxxxx */
-{ "adcl", 0x58010f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "adcl", 0x58010f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* adcl<.f> ZA,XIMM,RC 0101110000000001x111xxxxxx111110 */
-{ "adcl", 0x5c01703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "adcl", 0x5c01703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* adcl<.f> ZA,RB,XIMM 01011xxx00000001xxxx111100111110 */
-{ "adcl", 0x58010f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "adcl", 0x58010f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* adcl<.f><.cc> ZA,XIMM,RC 0101110011000001x111xxxxxx0xxxxx */
-{ "adcl", 0x5cc17000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "adcl", 0x5cc17000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* adcl<.f><.cc> RB,RBdup,XIMM 01011xxx11000001xxxx1111000xxxxx */
-{ "adcl", 0x58c10f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "adcl", 0x58c10f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* adcl<.f> RA,XIMM,UIMM6_20 0101110001000001x111xxxxxxxxxxxx */
-{ "adcl", 0x5c417000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "adcl", 0x5c417000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* adcl<.f> ZA,XIMM,UIMM6_20 0101110001000001x111xxxxxx111110 */
-{ "adcl", 0x5c41703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "adcl", 0x5c41703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* adcl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011000001x111xxxxxx1xxxxx */
-{ "adcl", 0x5cc17020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "adcl", 0x5cc17020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* adcl<.f> RA,LIMM,RC 0101111000000001x111xxxxxxxxxxxx */
-{ "adcl", 0x5e017000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "adcl", 0x5e017000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* adcl<.f> RA,RB,LIMM 01011xxx00000001xxxx111110xxxxxx */
-{ "adcl", 0x58010f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "adcl", 0x58010f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* adcl<.f> ZA,LIMM,RC 0101111000000001x111xxxxxx111110 */
-{ "adcl", 0x5e01703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "adcl", 0x5e01703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* adcl<.f> ZA,RB,LIMM 01011xxx00000001xxxx111110111110 */
-{ "adcl", 0x58010fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "adcl", 0x58010fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* adcl<.f><.cc> ZA,LIMM,RC 0101111011000001x111xxxxxx0xxxxx */
-{ "adcl", 0x5ec17000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "adcl", 0x5ec17000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* adcl<.f><.cc> RB,RBdup,LIMM 01011xxx11000001xxxx1111100xxxxx */
-{ "adcl", 0x58c10f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "adcl", 0x58c10f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* adcl<.f> RA,LIMM,UIMM6_20 0101111001000001x111xxxxxxxxxxxx */
-{ "adcl", 0x5e417000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "adcl", 0x5e417000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* adcl<.f> ZA,LIMM,UIMM6_20 0101111001000001x111xxxxxx111110 */
-{ "adcl", 0x5e41703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "adcl", 0x5e41703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* adcl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011000001x111xxxxxx1xxxxx */
-{ "adcl", 0x5ec17020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "adcl", 0x5ec17020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* adcl<.f> ZA,XIMM,SIMM12_20 0101110010000001x111xxxxxxxxxxxx */
-{ "adcl", 0x5c817000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "adcl", 0x5c817000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* adcl<.f> ZA,LIMM,SIMM12_20 0101111010000001x111xxxxxxxxxxxx */
-{ "adcl", 0x5e817000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "adcl", 0x5e817000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* adcl<.f> RA,XIMM,XIMMdup 0101110000000001x111111100xxxxxx */
-{ "adcl", 0x5c017f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "adcl", 0x5c017f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* adcl<.f> ZA,XIMM,XIMMdup 0101110000000001x111111100111110 */
-{ "adcl", 0x5c017f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "adcl", 0x5c017f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* adcl<.f><.cc> ZA,XIMM,XIMMdup 0101110011000001x1111111000xxxxx */
-{ "adcl", 0x5cc17f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "adcl", 0x5cc17f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* adcl<.f> RA,LIMM,LIMMdup 0101111000000001x111111110xxxxxx */
-{ "adcl", 0x5e017f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "adcl", 0x5e017f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* adcl<.f> ZA,LIMM,LIMMdup 0101111000000001x111111110111110 */
-{ "adcl", 0x5e017fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "adcl", 0x5e017fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* adcl<.f><.cc> ZA,LIMM,LIMMdup 0101111011000001x1111111100xxxxx */
-{ "adcl", 0x5ec17f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "adcl", 0x5ec17f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* add<.f> RA,RB,RC 00100xxx00000000xxxxxxxxxxxxxxxx */
-{ "add", 0x20000000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "add", 0x20000000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* add<.f> ZA,RB,RC 00100xxx00000000xxxxxxxxxx111110 */
-{ "add", 0x2000003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "add", 0x2000003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* add<.f><.cc> RB,RBdup,RC 00100xxx11000000xxxxxxxxxx0xxxxx */
-{ "add", 0x20c00000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "add", 0x20c00000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* add<.f> RA,RB,UIMM6_20 00100xxx01000000xxxxxxxxxxxxxxxx */
-{ "add", 0x20400000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "add", 0x20400000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* add<.f> ZA,RB,UIMM6_20 00100xxx01000000xxxxxxxxxx111110 */
-{ "add", 0x2040003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "add", 0x2040003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* add<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11000000xxxxxxxxxx1xxxxx */
-{ "add", 0x20c00020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "add", 0x20c00020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* add<.f> RB,RBdup,SIMM12_20 00100xxx10000000xxxxxxxxxxxxxxxx */
-{ "add", 0x20800000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "add", 0x20800000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* add<.f> RA,LIMM,RC 0010011000000000x111xxxxxxxxxxxx */
-{ "add", 0x26007000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "add", 0x26007000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* add<.f> RA,RB,LIMM 00100xxx00000000xxxx111110xxxxxx */
-{ "add", 0x20000f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "add", 0x20000f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* add<.f> ZA,LIMM,RC 0010011000000000x111xxxxxx111110 */
-{ "add", 0x2600703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "add", 0x2600703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* add<.f> ZA,RB,LIMM 00100xxx00000000xxxx111110111110 */
-{ "add", 0x20000fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "add", 0x20000fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* add<.f><.cc> RB,RBdup,LIMM 00100xxx11000000xxxx1111100xxxxx */
-{ "add", 0x20c00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "add", 0x20c00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* add<.f><.cc> ZA,LIMM,RC 0010011011000000x111xxxxxx0xxxxx */
-{ "add", 0x26c07000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "add", 0x26c07000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* add<.f> RA,LIMM,UIMM6_20 0010011001000000x111xxxxxxxxxxxx */
-{ "add", 0x26407000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "add", 0x26407000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add<.f> ZA,LIMM,UIMM6_20 0010011001000000x111xxxxxx111110 */
-{ "add", 0x2640703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "add", 0x2640703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add<.f><.cc> ZA,LIMM,UIMM6_20 0010011011000000x111xxxxxx1xxxxx */
-{ "add", 0x26c07020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add", 0x26c07020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add<.f> ZA,LIMM,SIMM12_20 0010011010000000x111xxxxxxxxxxxx */
-{ "add", 0x26807000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "add", 0x26807000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* add<.f> RA,LIMM,LIMMdup 0010011000000000x111111110xxxxxx */
-{ "add", 0x26007f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "add", 0x26007f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* add<.f> ZA,LIMM,LIMMdup 0010011000000000x111111110111110 */
-{ "add", 0x26007fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "add", 0x26007fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* add<.f><.cc> ZA,LIMM,LIMMdup 0010011011000000x1111111100xxxxx */
-{ "add", 0x26c07f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "add", 0x26c07f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* add1<.f> RA,RB,RC 00100xxx00010100xxxxxxxxxxxxxxxx */
-{ "add1", 0x20140000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "add1", 0x20140000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* add1<.f> ZA,RB,RC 00100xxx00010100xxxxxxxxxx111110 */
-{ "add1", 0x2014003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "add1", 0x2014003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* add1<.f><.cc> RB,RBdup,RC 00100xxx11010100xxxxxxxxxx0xxxxx */
-{ "add1", 0x20d40000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "add1", 0x20d40000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* add1<.f> RA,RB,UIMM6_20 00100xxx01010100xxxxxxxxxxxxxxxx */
-{ "add1", 0x20540000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "add1", 0x20540000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* add1<.f> ZA,RB,UIMM6_20 00100xxx01010100xxxxxxxxxx111110 */
-{ "add1", 0x2054003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "add1", 0x2054003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* add1<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11010100xxxxxxxxxx1xxxxx */
-{ "add1", 0x20d40020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "add1", 0x20d40020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* add1<.f> RB,RBdup,SIMM12_20 00100xxx10010100xxxxxxxxxxxxxxxx */
-{ "add1", 0x20940000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "add1", 0x20940000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* add1<.f> RA,LIMM,RC 0010011000010100x111xxxxxxxxxxxx */
-{ "add1", 0x26147000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "add1", 0x26147000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* add1<.f> RA,RB,LIMM 00100xxx00010100xxxx111110xxxxxx */
-{ "add1", 0x20140f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "add1", 0x20140f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* add1<.f> ZA,LIMM,RC 0010011000010100x111xxxxxx111110 */
-{ "add1", 0x2614703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "add1", 0x2614703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* add1<.f> ZA,RB,LIMM 00100xxx00010100xxxx111110111110 */
-{ "add1", 0x20140fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "add1", 0x20140fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* add1<.f><.cc> RB,RBdup,LIMM 00100xxx11010100xxxx1111100xxxxx */
-{ "add1", 0x20d40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "add1", 0x20d40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* add1<.f><.cc> ZA,LIMM,RC 0010011011010100x111xxxxxx0xxxxx */
-{ "add1", 0x26d47000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "add1", 0x26d47000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* add1<.f> RA,LIMM,UIMM6_20 0010011001010100x111xxxxxxxxxxxx */
-{ "add1", 0x26547000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "add1", 0x26547000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add1<.f> ZA,LIMM,UIMM6_20 0010011001010100x111xxxxxx111110 */
-{ "add1", 0x2654703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "add1", 0x2654703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add1<.f><.cc> ZA,LIMM,UIMM6_20 0010011011010100x111xxxxxx1xxxxx */
-{ "add1", 0x26d47020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add1", 0x26d47020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add1<.f> ZA,LIMM,SIMM12_20 0010011010010100x111xxxxxxxxxxxx */
-{ "add1", 0x26947000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "add1", 0x26947000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* add1<.f> RA,LIMM,LIMMdup 0010011000010100x111111110xxxxxx */
-{ "add1", 0x26147f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "add1", 0x26147f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* add1<.f> ZA,LIMM,LIMMdup 0010011000010100x111111110111110 */
-{ "add1", 0x26147fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "add1", 0x26147fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* add1<.f><.cc> ZA,LIMM,LIMMdup 0010011011010100x1111111100xxxxx */
-{ "add1", 0x26d47f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "add1", 0x26d47f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* add1l<.f> RA,RB,RC 01011xxx00010100xxxxxxxxxxxxxxxx */
-{ "add1l", 0x58140000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "add1l", 0x58140000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* add1l<.f> ZA,RB,RC 01011xxx00010100xxxxxxxxxx111110 */
-{ "add1l", 0x5814003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "add1l", 0x5814003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* add1l<.f><.cc> RB,RBdup,RC 01011xxx11010100xxxxxxxxxx0xxxxx */
-{ "add1l", 0x58d40000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "add1l", 0x58d40000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* add1l<.f> RA,RB,UIMM6_20 01011xxx01010100xxxxxxxxxxxxxxxx */
-{ "add1l", 0x58540000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "add1l", 0x58540000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* add1l<.f> ZA,RB,UIMM6_20 01011xxx01010100xxxxxxxxxx111110 */
-{ "add1l", 0x5854003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "add1l", 0x5854003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* add1l<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11010100xxxxxxxxxx1xxxxx */
-{ "add1l", 0x58d40020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "add1l", 0x58d40020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* add1l<.f> RB,RBdup,SIMM12_20 01011xxx10010100xxxxxxxxxxxxxxxx */
-{ "add1l", 0x58940000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "add1l", 0x58940000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* add1l<.f> RA,XIMM,RC 0101110000010100x111xxxxxxxxxxxx */
-{ "add1l", 0x5c147000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "add1l", 0x5c147000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* add1l<.f> RA,RB,XIMM 01011xxx00010100xxxx111100xxxxxx */
-{ "add1l", 0x58140f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "add1l", 0x58140f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* add1l<.f> ZA,XIMM,RC 0101110000010100x111xxxxxx111110 */
-{ "add1l", 0x5c14703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "add1l", 0x5c14703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* add1l<.f> ZA,RB,XIMM 01011xxx00010100xxxx111100111110 */
-{ "add1l", 0x58140f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "add1l", 0x58140f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* add1l<.f><.cc> ZA,XIMM,RC 0101110011010100x111xxxxxx0xxxxx */
-{ "add1l", 0x5cd47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "add1l", 0x5cd47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* add1l<.f><.cc> RB,RBdup,XIMM 01011xxx11010100xxxx1111000xxxxx */
-{ "add1l", 0x58d40f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "add1l", 0x58d40f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* add1l<.f> RA,XIMM,UIMM6_20 0101110001010100x111xxxxxxxxxxxx */
-{ "add1l", 0x5c547000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "add1l", 0x5c547000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* add1l<.f> ZA,XIMM,UIMM6_20 0101110001010100x111xxxxxx111110 */
-{ "add1l", 0x5c54703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "add1l", 0x5c54703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* add1l<.f><.cc> ZA,XIMM,UIMM6_20 0101110011010100x111xxxxxx1xxxxx */
-{ "add1l", 0x5cd47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add1l", 0x5cd47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add1l<.f> RA,LIMM,RC 0101111000010100x111xxxxxxxxxxxx */
-{ "add1l", 0x5e147000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "add1l", 0x5e147000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* add1l<.f> RA,RB,LIMM 01011xxx00010100xxxx111110xxxxxx */
-{ "add1l", 0x58140f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "add1l", 0x58140f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* add1l<.f> ZA,LIMM,RC 0101111000010100x111xxxxxx111110 */
-{ "add1l", 0x5e14703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "add1l", 0x5e14703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* add1l<.f> ZA,RB,LIMM 01011xxx00010100xxxx111110111110 */
-{ "add1l", 0x58140fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "add1l", 0x58140fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* add1l<.f><.cc> ZA,LIMM,RC 0101111011010100x111xxxxxx0xxxxx */
-{ "add1l", 0x5ed47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "add1l", 0x5ed47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* add1l<.f><.cc> RB,RBdup,LIMM 01011xxx11010100xxxx1111100xxxxx */
-{ "add1l", 0x58d40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "add1l", 0x58d40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* add1l<.f> RA,LIMM,UIMM6_20 0101111001010100x111xxxxxxxxxxxx */
-{ "add1l", 0x5e547000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "add1l", 0x5e547000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add1l<.f> ZA,LIMM,UIMM6_20 0101111001010100x111xxxxxx111110 */
-{ "add1l", 0x5e54703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "add1l", 0x5e54703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add1l<.f><.cc> ZA,LIMM,UIMM6_20 0101111011010100x111xxxxxx1xxxxx */
-{ "add1l", 0x5ed47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add1l", 0x5ed47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add1l<.f> ZA,XIMM,SIMM12_20 0101110010010100x111xxxxxxxxxxxx */
-{ "add1l", 0x5c947000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "add1l", 0x5c947000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* add1l<.f> ZA,LIMM,SIMM12_20 0101111010010100x111xxxxxxxxxxxx */
-{ "add1l", 0x5e947000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "add1l", 0x5e947000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* add1l<.f> RA,XIMM,XIMMdup 0101110000010100x111111100xxxxxx */
-{ "add1l", 0x5c147f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "add1l", 0x5c147f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* add1l<.f> ZA,XIMM,XIMMdup 0101110000010100x111111100111110 */
-{ "add1l", 0x5c147f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "add1l", 0x5c147f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* add1l<.f><.cc> ZA,XIMM,XIMMdup 0101110011010100x1111111000xxxxx */
-{ "add1l", 0x5cd47f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "add1l", 0x5cd47f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* add1l<.f> RA,LIMM,LIMMdup 0101111000010100x111111110xxxxxx */
-{ "add1l", 0x5e147f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "add1l", 0x5e147f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* add1l<.f> ZA,LIMM,LIMMdup 0101111000010100x111111110111110 */
-{ "add1l", 0x5e147fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "add1l", 0x5e147fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* add1l<.f><.cc> ZA,LIMM,LIMMdup 0101111011010100x1111111100xxxxx */
-{ "add1l", 0x5ed47f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "add1l", 0x5ed47f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* add1_s RB_S,RB_Sdup,RC_S 01111xxxxxx10100 */
-{ "add1_s", 0x00007814, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "add1_s", 0x00007814, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* add2<.f> RA,RB,RC 00100xxx00010101xxxxxxxxxxxxxxxx */
-{ "add2", 0x20150000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "add2", 0x20150000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* add2<.f> ZA,RB,RC 00100xxx00010101xxxxxxxxxx111110 */
-{ "add2", 0x2015003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "add2", 0x2015003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* add2<.f><.cc> RB,RBdup,RC 00100xxx11010101xxxxxxxxxx0xxxxx */
-{ "add2", 0x20d50000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "add2", 0x20d50000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* add2<.f> RA,RB,UIMM6_20 00100xxx01010101xxxxxxxxxxxxxxxx */
-{ "add2", 0x20550000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "add2", 0x20550000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* add2<.f> ZA,RB,UIMM6_20 00100xxx01010101xxxxxxxxxx111110 */
-{ "add2", 0x2055003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "add2", 0x2055003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* add2<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11010101xxxxxxxxxx1xxxxx */
-{ "add2", 0x20d50020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "add2", 0x20d50020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* add2<.f> RB,RBdup,SIMM12_20 00100xxx10010101xxxxxxxxxxxxxxxx */
-{ "add2", 0x20950000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "add2", 0x20950000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* add2<.f> RA,LIMM,RC 0010011000010101x111xxxxxxxxxxxx */
-{ "add2", 0x26157000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "add2", 0x26157000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* add2<.f> RA,RB,LIMM 00100xxx00010101xxxx111110xxxxxx */
-{ "add2", 0x20150f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "add2", 0x20150f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* add2<.f> ZA,LIMM,RC 0010011000010101x111xxxxxx111110 */
-{ "add2", 0x2615703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "add2", 0x2615703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* add2<.f> ZA,RB,LIMM 00100xxx00010101xxxx111110111110 */
-{ "add2", 0x20150fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "add2", 0x20150fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* add2<.f><.cc> RB,RBdup,LIMM 00100xxx11010101xxxx1111100xxxxx */
-{ "add2", 0x20d50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "add2", 0x20d50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* add2<.f><.cc> ZA,LIMM,RC 0010011011010101x111xxxxxx0xxxxx */
-{ "add2", 0x26d57000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "add2", 0x26d57000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* add2<.f> RA,LIMM,UIMM6_20 0010011001010101x111xxxxxxxxxxxx */
-{ "add2", 0x26557000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "add2", 0x26557000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add2<.f> ZA,LIMM,UIMM6_20 0010011001010101x111xxxxxx111110 */
-{ "add2", 0x2655703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "add2", 0x2655703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add2<.f><.cc> ZA,LIMM,UIMM6_20 0010011011010101x111xxxxxx1xxxxx */
-{ "add2", 0x26d57020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add2", 0x26d57020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add2<.f> ZA,LIMM,SIMM12_20 0010011010010101x111xxxxxxxxxxxx */
-{ "add2", 0x26957000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "add2", 0x26957000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* add2<.f> RA,LIMM,LIMMdup 0010011000010101x111111110xxxxxx */
-{ "add2", 0x26157f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "add2", 0x26157f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* add2<.f> ZA,LIMM,LIMMdup 0010011000010101x111111110111110 */
-{ "add2", 0x26157fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "add2", 0x26157fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* add2<.f><.cc> ZA,LIMM,LIMMdup 0010011011010101x1111111100xxxxx */
-{ "add2", 0x26d57f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "add2", 0x26d57f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* add2l<.f> RA,RB,RC 01011xxx00010101xxxxxxxxxxxxxxxx */
-{ "add2l", 0x58150000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "add2l", 0x58150000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* add2l<.f> ZA,RB,RC 01011xxx00010101xxxxxxxxxx111110 */
-{ "add2l", 0x5815003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "add2l", 0x5815003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* add2l<.f><.cc> RB,RBdup,RC 01011xxx11010101xxxxxxxxxx0xxxxx */
-{ "add2l", 0x58d50000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "add2l", 0x58d50000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* add2l<.f> RA,RB,UIMM6_20 01011xxx01010101xxxxxxxxxxxxxxxx */
-{ "add2l", 0x58550000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "add2l", 0x58550000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* add2l<.f> ZA,RB,UIMM6_20 01011xxx01010101xxxxxxxxxx111110 */
-{ "add2l", 0x5855003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "add2l", 0x5855003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* add2l<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11010101xxxxxxxxxx1xxxxx */
-{ "add2l", 0x58d50020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "add2l", 0x58d50020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* add2l<.f> RB,RBdup,SIMM12_20 01011xxx10010101xxxxxxxxxxxxxxxx */
-{ "add2l", 0x58950000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "add2l", 0x58950000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* add2l<.f> RA,XIMM,RC 0101110000010101x111xxxxxxxxxxxx */
-{ "add2l", 0x5c157000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "add2l", 0x5c157000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* add2l<.f> RA,RB,XIMM 01011xxx00010101xxxx111100xxxxxx */
-{ "add2l", 0x58150f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "add2l", 0x58150f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* add2l<.f> ZA,XIMM,RC 0101110000010101x111xxxxxx111110 */
-{ "add2l", 0x5c15703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "add2l", 0x5c15703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* add2l<.f> ZA,RB,XIMM 01011xxx00010101xxxx111100111110 */
-{ "add2l", 0x58150f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "add2l", 0x58150f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* add2l<.f><.cc> ZA,XIMM,RC 0101110011010101x111xxxxxx0xxxxx */
-{ "add2l", 0x5cd57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "add2l", 0x5cd57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* add2l<.f><.cc> RB,RBdup,XIMM 01011xxx11010101xxxx1111000xxxxx */
-{ "add2l", 0x58d50f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "add2l", 0x58d50f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* add2l<.f> RA,XIMM,UIMM6_20 0101110001010101x111xxxxxxxxxxxx */
-{ "add2l", 0x5c557000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "add2l", 0x5c557000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* add2l<.f> ZA,XIMM,UIMM6_20 0101110001010101x111xxxxxx111110 */
-{ "add2l", 0x5c55703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "add2l", 0x5c55703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* add2l<.f><.cc> ZA,XIMM,UIMM6_20 0101110011010101x111xxxxxx1xxxxx */
-{ "add2l", 0x5cd57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add2l", 0x5cd57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add2l<.f> RA,LIMM,RC 0101111000010101x111xxxxxxxxxxxx */
-{ "add2l", 0x5e157000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "add2l", 0x5e157000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* add2l<.f> RA,RB,LIMM 01011xxx00010101xxxx111110xxxxxx */
-{ "add2l", 0x58150f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "add2l", 0x58150f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* add2l<.f> ZA,LIMM,RC 0101111000010101x111xxxxxx111110 */
-{ "add2l", 0x5e15703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "add2l", 0x5e15703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* add2l<.f> ZA,RB,LIMM 01011xxx00010101xxxx111110111110 */
-{ "add2l", 0x58150fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "add2l", 0x58150fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* add2l<.f><.cc> ZA,LIMM,RC 0101111011010101x111xxxxxx0xxxxx */
-{ "add2l", 0x5ed57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "add2l", 0x5ed57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* add2l<.f><.cc> RB,RBdup,LIMM 01011xxx11010101xxxx1111100xxxxx */
-{ "add2l", 0x58d50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "add2l", 0x58d50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* add2l<.f> RA,LIMM,UIMM6_20 0101111001010101x111xxxxxxxxxxxx */
-{ "add2l", 0x5e557000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "add2l", 0x5e557000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add2l<.f> ZA,LIMM,UIMM6_20 0101111001010101x111xxxxxx111110 */
-{ "add2l", 0x5e55703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "add2l", 0x5e55703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add2l<.f><.cc> ZA,LIMM,UIMM6_20 0101111011010101x111xxxxxx1xxxxx */
-{ "add2l", 0x5ed57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add2l", 0x5ed57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add2l<.f> ZA,XIMM,SIMM12_20 0101110010010101x111xxxxxxxxxxxx */
-{ "add2l", 0x5c957000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "add2l", 0x5c957000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* add2l<.f> ZA,LIMM,SIMM12_20 0101111010010101x111xxxxxxxxxxxx */
-{ "add2l", 0x5e957000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "add2l", 0x5e957000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* add2l<.f> RA,XIMM,XIMMdup 0101110000010101x111111100xxxxxx */
-{ "add2l", 0x5c157f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "add2l", 0x5c157f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* add2l<.f> ZA,XIMM,XIMMdup 0101110000010101x111111100111110 */
-{ "add2l", 0x5c157f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "add2l", 0x5c157f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* add2l<.f><.cc> ZA,XIMM,XIMMdup 0101110011010101x1111111000xxxxx */
-{ "add2l", 0x5cd57f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "add2l", 0x5cd57f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* add2l<.f> RA,LIMM,LIMMdup 0101111000010101x111111110xxxxxx */
-{ "add2l", 0x5e157f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "add2l", 0x5e157f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* add2l<.f> ZA,LIMM,LIMMdup 0101111000010101x111111110111110 */
-{ "add2l", 0x5e157fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "add2l", 0x5e157fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* add2l<.f><.cc> ZA,LIMM,LIMMdup 0101111011010101x1111111100xxxxx */
-{ "add2l", 0x5ed57f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "add2l", 0x5ed57f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* add2_s RB_S,RB_Sdup,RC_S 01111xxxxxx10101 */
-{ "add2_s", 0x00007815, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "add2_s", 0x00007815, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* add3<.f> RA,RB,RC 00100xxx00010110xxxxxxxxxxxxxxxx */
-{ "add3", 0x20160000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "add3", 0x20160000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* add3<.f> ZA,RB,RC 00100xxx00010110xxxxxxxxxx111110 */
-{ "add3", 0x2016003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "add3", 0x2016003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* add3<.f><.cc> RB,RBdup,RC 00100xxx11010110xxxxxxxxxx0xxxxx */
-{ "add3", 0x20d60000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "add3", 0x20d60000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* add3<.f> RA,RB,UIMM6_20 00100xxx01010110xxxxxxxxxxxxxxxx */
-{ "add3", 0x20560000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "add3", 0x20560000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* add3<.f> ZA,RB,UIMM6_20 00100xxx01010110xxxxxxxxxx111110 */
-{ "add3", 0x2056003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "add3", 0x2056003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* add3<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11010110xxxxxxxxxx1xxxxx */
-{ "add3", 0x20d60020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "add3", 0x20d60020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* add3<.f> RB,RBdup,SIMM12_20 00100xxx10010110xxxxxxxxxxxxxxxx */
-{ "add3", 0x20960000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "add3", 0x20960000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* add3<.f> RA,LIMM,RC 0010011000010110x111xxxxxxxxxxxx */
-{ "add3", 0x26167000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "add3", 0x26167000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* add3<.f> RA,RB,LIMM 00100xxx00010110xxxx111110xxxxxx */
-{ "add3", 0x20160f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "add3", 0x20160f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* add3<.f> ZA,LIMM,RC 0010011000010110x111xxxxxx111110 */
-{ "add3", 0x2616703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "add3", 0x2616703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* add3<.f> ZA,RB,LIMM 00100xxx00010110xxxx111110111110 */
-{ "add3", 0x20160fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "add3", 0x20160fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* add3<.f><.cc> RB,RBdup,LIMM 00100xxx11010110xxxx1111100xxxxx */
-{ "add3", 0x20d60f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "add3", 0x20d60f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* add3<.f><.cc> ZA,LIMM,RC 0010011011010110x111xxxxxx0xxxxx */
-{ "add3", 0x26d67000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "add3", 0x26d67000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* add3<.f> RA,LIMM,UIMM6_20 0010011001010110x111xxxxxxxxxxxx */
-{ "add3", 0x26567000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "add3", 0x26567000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add3<.f> ZA,LIMM,UIMM6_20 0010011001010110x111xxxxxx111110 */
-{ "add3", 0x2656703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "add3", 0x2656703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add3<.f><.cc> ZA,LIMM,UIMM6_20 0010011011010110x111xxxxxx1xxxxx */
-{ "add3", 0x26d67020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add3", 0x26d67020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add3<.f> ZA,LIMM,SIMM12_20 0010011010010110x111xxxxxxxxxxxx */
-{ "add3", 0x26967000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "add3", 0x26967000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* add3<.f> RA,LIMM,LIMMdup 0010011000010110x111111110xxxxxx */
-{ "add3", 0x26167f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "add3", 0x26167f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* add3<.f> ZA,LIMM,LIMMdup 0010011000010110x111111110111110 */
-{ "add3", 0x26167fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "add3", 0x26167fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* add3<.f><.cc> ZA,LIMM,LIMMdup 0010011011010110x1111111100xxxxx */
-{ "add3", 0x26d67f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "add3", 0x26d67f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* add3l<.f> RA,RB,RC 01011xxx00010110xxxxxxxxxxxxxxxx */
-{ "add3l", 0x58160000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "add3l", 0x58160000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* add3l<.f> ZA,RB,RC 01011xxx00010110xxxxxxxxxx111110 */
-{ "add3l", 0x5816003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "add3l", 0x5816003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* add3l<.f><.cc> RB,RBdup,RC 01011xxx11010110xxxxxxxxxx0xxxxx */
-{ "add3l", 0x58d60000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "add3l", 0x58d60000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* add3l<.f> RA,RB,UIMM6_20 01011xxx01010110xxxxxxxxxxxxxxxx */
-{ "add3l", 0x58560000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "add3l", 0x58560000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* add3l<.f> ZA,RB,UIMM6_20 01011xxx01010110xxxxxxxxxx111110 */
-{ "add3l", 0x5856003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "add3l", 0x5856003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* add3l<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11010110xxxxxxxxxx1xxxxx */
-{ "add3l", 0x58d60020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "add3l", 0x58d60020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* add3l<.f> RB,RBdup,SIMM12_20 01011xxx10010110xxxxxxxxxxxxxxxx */
-{ "add3l", 0x58960000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "add3l", 0x58960000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* add3l<.f> RA,XIMM,RC 0101110000010110x111xxxxxxxxxxxx */
-{ "add3l", 0x5c167000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "add3l", 0x5c167000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* add3l<.f> RA,RB,XIMM 01011xxx00010110xxxx111100xxxxxx */
-{ "add3l", 0x58160f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "add3l", 0x58160f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* add3l<.f> ZA,XIMM,RC 0101110000010110x111xxxxxx111110 */
-{ "add3l", 0x5c16703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "add3l", 0x5c16703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* add3l<.f> ZA,RB,XIMM 01011xxx00010110xxxx111100111110 */
-{ "add3l", 0x58160f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "add3l", 0x58160f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* add3l<.f><.cc> ZA,XIMM,RC 0101110011010110x111xxxxxx0xxxxx */
-{ "add3l", 0x5cd67000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "add3l", 0x5cd67000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* add3l<.f><.cc> RB,RBdup,XIMM 01011xxx11010110xxxx1111000xxxxx */
-{ "add3l", 0x58d60f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "add3l", 0x58d60f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* add3l<.f> RA,XIMM,UIMM6_20 0101110001010110x111xxxxxxxxxxxx */
-{ "add3l", 0x5c567000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "add3l", 0x5c567000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* add3l<.f> ZA,XIMM,UIMM6_20 0101110001010110x111xxxxxx111110 */
-{ "add3l", 0x5c56703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "add3l", 0x5c56703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* add3l<.f><.cc> ZA,XIMM,UIMM6_20 0101110011010110x111xxxxxx1xxxxx */
-{ "add3l", 0x5cd67020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add3l", 0x5cd67020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add3l<.f> RA,LIMM,RC 0101111000010110x111xxxxxxxxxxxx */
-{ "add3l", 0x5e167000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "add3l", 0x5e167000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* add3l<.f> RA,RB,LIMM 01011xxx00010110xxxx111110xxxxxx */
-{ "add3l", 0x58160f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "add3l", 0x58160f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* add3l<.f> ZA,LIMM,RC 0101111000010110x111xxxxxx111110 */
-{ "add3l", 0x5e16703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "add3l", 0x5e16703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* add3l<.f> ZA,RB,LIMM 01011xxx00010110xxxx111110111110 */
-{ "add3l", 0x58160fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "add3l", 0x58160fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* add3l<.f><.cc> ZA,LIMM,RC 0101111011010110x111xxxxxx0xxxxx */
-{ "add3l", 0x5ed67000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "add3l", 0x5ed67000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* add3l<.f><.cc> RB,RBdup,LIMM 01011xxx11010110xxxx1111100xxxxx */
-{ "add3l", 0x58d60f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "add3l", 0x58d60f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* add3l<.f> RA,LIMM,UIMM6_20 0101111001010110x111xxxxxxxxxxxx */
-{ "add3l", 0x5e567000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "add3l", 0x5e567000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add3l<.f> ZA,LIMM,UIMM6_20 0101111001010110x111xxxxxx111110 */
-{ "add3l", 0x5e56703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "add3l", 0x5e56703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* add3l<.f><.cc> ZA,LIMM,UIMM6_20 0101111011010110x111xxxxxx1xxxxx */
-{ "add3l", 0x5ed67020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "add3l", 0x5ed67020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* add3l<.f> ZA,XIMM,SIMM12_20 0101110010010110x111xxxxxxxxxxxx */
-{ "add3l", 0x5c967000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "add3l", 0x5c967000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* add3l<.f> ZA,LIMM,SIMM12_20 0101111010010110x111xxxxxxxxxxxx */
-{ "add3l", 0x5e967000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "add3l", 0x5e967000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* add3l<.f> RA,XIMM,XIMMdup 0101110000010110x111111100xxxxxx */
-{ "add3l", 0x5c167f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "add3l", 0x5c167f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* add3l<.f> ZA,XIMM,XIMMdup 0101110000010110x111111100111110 */
-{ "add3l", 0x5c167f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "add3l", 0x5c167f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* add3l<.f><.cc> ZA,XIMM,XIMMdup 0101110011010110x1111111000xxxxx */
-{ "add3l", 0x5cd67f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "add3l", 0x5cd67f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* add3l<.f> RA,LIMM,LIMMdup 0101111000010110x111111110xxxxxx */
-{ "add3l", 0x5e167f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "add3l", 0x5e167f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* add3l<.f> ZA,LIMM,LIMMdup 0101111000010110x111111110111110 */
-{ "add3l", 0x5e167fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "add3l", 0x5e167fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* add3l<.f><.cc> ZA,LIMM,LIMMdup 0101111011010110x1111111100xxxxx */
-{ "add3l", 0x5ed67f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "add3l", 0x5ed67f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* add3_s RB_S,RB_Sdup,RC_S 01111xxxxxx10110 */
-{ "add3_s", 0x00007816, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "add3_s", 0x00007816, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* addhl RA,RB,RC 01011xxx001011100xxxxxxxxxxxxxxx */
-{ "addhl", 0x582e0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 } }
+{ "addhl", 0x582e0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* addhl ZA,RB,RC 01011xxx001011100xxxxxxxxx111110 */
-{ "addhl", 0x582e003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 } }
+{ "addhl", 0x582e003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* addhl<.cc> RB,RBdup,RC 01011xxx111011100xxxxxxxxx0xxxxx */
-{ "addhl", 0x58ee0000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "addhl", 0x58ee0000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* addhl RA,RB,UIMM6_20 01011xxx011011100xxxxxxxxxxxxxxx */
-{ "addhl", 0x586e0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "addhl", 0x586e0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* addhl ZA,RB,UIMM6_20 01011xxx011011100xxxxxxxxx111110 */
-{ "addhl", 0x586e003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "addhl", 0x586e003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* addhl<.cc> RB,RBdup,UIMM6_20 01011xxx111011100xxxxxxxxx1xxxxx */
-{ "addhl", 0x58ee0020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "addhl", 0x58ee0020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* addhl RB,RBdup,SIMM12_20 01011xxx101011100xxxxxxxxxxxxxxx */
-{ "addhl", 0x58ae0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "addhl", 0x58ae0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* addhl RA,HI32,RC 01011110001011100111xxxxxxxxxxxx */
-{ "addhl", 0x5e2e7000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, HI32, RC }, { 0 } }
+{ "addhl", 0x5e2e7000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, HI32, RC }, { 0 } }
 
 /* addhl RA,RB,HI32 01011xxx001011100xxx111110xxxxxx */
-{ "addhl", 0x582e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, HI32 }, { 0 } }
+{ "addhl", 0x582e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, HI32 }, { 0 } }
 
 /* addhl<.cc> RB,RBdup,HI32 01011xxx111011100xxx1111100xxxxx */
-{ "addhl", 0x58ee0f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, HI32 }, { C_CC } }
+{ "addhl", 0x58ee0f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, HI32 }, { C_CC } }
 
 /* addhl_s RH_S,PCL_S,XIMM_S 01110011xxx010xx */
-{ "addhl_s", 0x00007308, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, XIMM_S }, { 0 } }
+{ "addhl_s", 0x00007308, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, PCL_S, XIMM_S }, { 0 } }
 
 /* addhl_s RH_S,RH_Sdup,HI32 01110001xxx010xx */
-{ "addhl_s", 0x00007108, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, HI32 }, { 0 } }
+{ "addhl_s", 0x00007108, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, RH_Sdup, HI32 }, { 0 } }
 
 /* addl<.f> RA,RB,RC 01011xxx00000000xxxxxxxxxxxxxxxx */
-{ "addl", 0x58000000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "addl", 0x58000000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* addl<.f> ZA,RB,RC 01011xxx00000000xxxxxxxxxx111110 */
-{ "addl", 0x5800003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "addl", 0x5800003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* addl<.f><.cc> RB,RBdup,RC 01011xxx11000000xxxxxxxxxx0xxxxx */
-{ "addl", 0x58c00000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "addl", 0x58c00000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* addl<.f> RA,RB,UIMM6_20 01011xxx01000000xxxxxxxxxxxxxxxx */
-{ "addl", 0x58400000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "addl", 0x58400000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* addl<.f> ZA,RB,UIMM6_20 01011xxx01000000xxxxxxxxxx111110 */
-{ "addl", 0x5840003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "addl", 0x5840003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* addl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11000000xxxxxxxxxx1xxxxx */
-{ "addl", 0x58c00020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "addl", 0x58c00020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* addl<.f> RB,RBdup,SIMM12_20 01011xxx10000000xxxxxxxxxxxxxxxx */
-{ "addl", 0x58800000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "addl", 0x58800000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* addl<.f> RA,XIMM,RC 0101110000000000x111xxxxxxxxxxxx */
-{ "addl", 0x5c007000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "addl", 0x5c007000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* addl<.f> RA,RB,XIMM 01011xxx00000000xxxx111100xxxxxx */
-{ "addl", 0x58000f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "addl", 0x58000f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* addl<.f> ZA,XIMM,RC 0101110000000000x111xxxxxx111110 */
-{ "addl", 0x5c00703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "addl", 0x5c00703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* addl<.f> ZA,RB,XIMM 01011xxx00000000xxxx111100111110 */
-{ "addl", 0x58000f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "addl", 0x58000f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* addl<.f><.cc> ZA,XIMM,RC 0101110011000000x111xxxxxx0xxxxx */
-{ "addl", 0x5cc07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "addl", 0x5cc07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* addl<.f><.cc> RB,RBdup,XIMM 01011xxx11000000xxxx1111000xxxxx */
-{ "addl", 0x58c00f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "addl", 0x58c00f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* addl<.f> RA,XIMM,UIMM6_20 0101110001000000x111xxxxxxxxxxxx */
-{ "addl", 0x5c407000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "addl", 0x5c407000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* addl<.f> ZA,XIMM,UIMM6_20 0101110001000000x111xxxxxx111110 */
-{ "addl", 0x5c40703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "addl", 0x5c40703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* addl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011000000x111xxxxxx1xxxxx */
-{ "addl", 0x5cc07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "addl", 0x5cc07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* addl<.f> RA,LIMM,RC 0101111000000000x111xxxxxxxxxxxx */
-{ "addl", 0x5e007000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "addl", 0x5e007000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* addl<.f> RA,RB,LIMM 01011xxx00000000xxxx111110xxxxxx */
-{ "addl", 0x58000f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "addl", 0x58000f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* addl<.f> ZA,LIMM,RC 0101111000000000x111xxxxxx111110 */
-{ "addl", 0x5e00703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "addl", 0x5e00703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* addl<.f> ZA,RB,LIMM 01011xxx00000000xxxx111110111110 */
-{ "addl", 0x58000fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "addl", 0x58000fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* addl<.f><.cc> ZA,LIMM,RC 0101111011000000x111xxxxxx0xxxxx */
-{ "addl", 0x5ec07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "addl", 0x5ec07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* addl<.f><.cc> RB,RBdup,LIMM 01011xxx11000000xxxx1111100xxxxx */
-{ "addl", 0x58c00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "addl", 0x58c00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* addl<.f> RA,LIMM,UIMM6_20 0101111001000000x111xxxxxxxxxxxx */
-{ "addl", 0x5e407000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "addl", 0x5e407000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* addl<.f> ZA,LIMM,UIMM6_20 0101111001000000x111xxxxxx111110 */
-{ "addl", 0x5e40703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "addl", 0x5e40703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* addl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011000000x111xxxxxx1xxxxx */
-{ "addl", 0x5ec07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "addl", 0x5ec07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* addl<.f> ZA,XIMM,SIMM12_20 0101110010000000x111xxxxxxxxxxxx */
-{ "addl", 0x5c807000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "addl", 0x5c807000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* addl<.f> ZA,LIMM,SIMM12_20 0101111010000000x111xxxxxxxxxxxx */
-{ "addl", 0x5e807000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "addl", 0x5e807000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* addl<.f> RA,XIMM,XIMMdup 0101110000000000x111111100xxxxxx */
-{ "addl", 0x5c007f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "addl", 0x5c007f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* addl<.f> ZA,XIMM,XIMMdup 0101110000000000x111111100111110 */
-{ "addl", 0x5c007f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "addl", 0x5c007f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* addl<.f><.cc> ZA,XIMM,XIMMdup 0101110011000000x1111111000xxxxx */
-{ "addl", 0x5cc07f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "addl", 0x5cc07f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* addl<.f> RA,LIMM,LIMMdup 0101111000000000x111111110xxxxxx */
-{ "addl", 0x5e007f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "addl", 0x5e007f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* addl<.f> ZA,LIMM,LIMMdup 0101111000000000x111111110111110 */
-{ "addl", 0x5e007fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "addl", 0x5e007fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* addl<.f><.cc> ZA,LIMM,LIMMdup 0101111011000000x1111111100xxxxx */
-{ "addl", 0x5ec07f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "addl", 0x5ec07f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* addl_s SP_S,SP_Sdup,UIMM9_A32_11_S 11000xx0101xxxxx */
-{ "addl_s", 0x0000c0a0, 0x0000f9e0, ARC_OPCODE_ARC64, ARITH, NONE, { SP_S, SP_Sdup, UIMM9_A32_11_S }, { 0 } }
+{ "addl_s", 0x0000c0a0, 0x0000f9e0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { SP_S, SP_Sdup, UIMM9_A32_11_S }, { 0 } }
 
 /* addl_s RB_S,RB_Sdup,RC_S 01111xxxxxx00001 */
-{ "addl_s", 0x00007801, 0x0000f81f, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "addl_s", 0x00007801, 0x0000f81f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* addl_s RB_S,SP_S,UIMM7_A32_11_S 11000xxx100xxxxx */
-{ "addl_s", 0x0000c080, 0x0000f8e0, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 } }
+{ "addl_s", 0x0000c080, 0x0000f8e0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 } }
 
 /* addl_s R0_S,GP_S,SIMM11_A32_7_S 1100111xxxxxxxxx */
-{ "addl_s", 0x0000ce00, 0x0000fe00, ARC_OPCODE_ARC64, ARITH, NONE, { R0_S, GP_S, SIMM11_A32_7_S }, { 0 } }
+{ "addl_s", 0x0000ce00, 0x0000fe00, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { R0_S, GP_S, SIMM11_A32_7_S }, { 0 } }
 
 /* addl_s RH_S,RH_Sdup,LO32 01110001xxx110xx */
-{ "addl_s", 0x00007118, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, LO32 }, { 0 } }
+{ "addl_s", 0x00007118, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, RH_Sdup, LO32 }, { 0 } }
 
 /* addl_s RH_S,PCL_S,LO32 01110011xxx110xx */
-{ "addl_s", 0x00007318, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, LO32 }, { 0 } }
+{ "addl_s", 0x00007318, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, PCL_S, LO32 }, { 0 } }
 
 /* add_s RA_S,RB_S,RC_S 01100xxxxxx11xxx */
-{ "add_s", 0x00006018, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA_S, RB_S, RC_S }, { 0 } }
+{ "add_s", 0x00006018, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA_S, RB_S, RC_S }, { 0 } }
 
 /* add_s RB_S,RB_Sdup,RH_S 01110xxxxxx000xx */
-{ "add_s", 0x00007000, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RB_Sdup, RH_S }, { 0 } }
+{ "add_s", 0x00007000, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RH_S }, { 0 } }
 
 /* add_s RH_S,RH_Sdup,SIMM3_5_S 01110xxxxxx001xx */
-{ "add_s", 0x00007004, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RH_S, RH_Sdup, SIMM3_5_S }, { 0 } }
+{ "add_s", 0x00007004, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, RH_Sdup, SIMM3_5_S }, { 0 } }
 
 /* add_s R0_S,RB_S,UIMM6_13_S 01001xxx0xxx1xxx */
 { "add_s", 0x00004808, 0x0000f888, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, CD, { R0_S, RB_S, UIMM6_13_S }, { 0 } }
@@ -965,256 +965,256 @@
 { "add_s", 0x00004888, 0x0000f888, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, CD, { R1_S, RB_S, UIMM6_13_S }, { 0 } }
 
 /* add_s RB_S,RB_Sdup,LIMM_S 01110xxx11000011 */
-{ "add_s", 0x000070c3, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RB_Sdup, LIMM_S }, { 0 } }
+{ "add_s", 0x000070c3, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, LIMM_S }, { 0 } }
 
 /* add_s ZA_S,LIMM_S,SIMM3_5_S 01110xxx11000111 */
-{ "add_s", 0x000070c7, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA_S, LIMM_S, SIMM3_5_S }, { 0 } }
+{ "add_s", 0x000070c7, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA_S, LIMM_S, SIMM3_5_S }, { 0 } }
 
 /* add_s b,sp,u7 11000bbb100uuuuu.  */
-{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 }},
+{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 }},
 
 /* add_s SP,SP,u7 11000000101uuuuu.  */
-{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC32, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
+{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
 
 /* aex RB_CHK,BRAKET,RC,BRAKETdup 00100xxx00100111xxxxxxxxxxxxxxxx */
-{ "aex", 0x20270000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "aex", 0x20270000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* aex<.cc> RB_CHK,BRAKET,RC,BRAKETdup 00100xxx11100111xxxxxxxxxx0xxxxx */
-{ "aex", 0x20e70000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_CC } }
+{ "aex", 0x20e70000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_CC } }
 
 /* aex RB_CHK,BRAKET,UIMM6_20,BRAKETdup 00100xxx01100111xxxxxxxxxxxxxxxx */
-{ "aex", 0x20670000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "aex", 0x20670000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* aex<.cc> RB_CHK,BRAKET,UIMM6_20,BRAKETdup 00100xxx11100111xxxxxxxxxx1xxxxx */
-{ "aex", 0x20e70020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { C_CC } }
+{ "aex", 0x20e70020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { C_CC } }
 
 /* aex RB_CHK,BRAKET,SIMM12_20,BRAKETdup 00100xxx10100111xxxxxxxxxxxxxxxx */
-{ "aex", 0x20a70000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "aex", 0x20a70000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* aex LIMM,BRAKET,RC,BRAKETdup 0010011000100111x111xxxxxxxxxxxx */
-{ "aex", 0x26277000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "aex", 0x26277000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* aex RB_CHK,BRAKET,LIMM,BRAKETdup 00100xxx00100111xxxx111110xxxxxx */
-{ "aex", 0x20270f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "aex", 0x20270f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* aex<.cc> LIMM,BRAKET,RC,BRAKETdup 0010011011100111x111xxxxxx0xxxxx */
-{ "aex", 0x26e77000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_CC } }
+{ "aex", 0x26e77000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_CC } }
 
 /* aex<.cc> RB_CHK,BRAKET,LIMM,BRAKETdup 00100xxx11100111xxxx1111100xxxxx */
-{ "aex", 0x20e70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_CC } }
+{ "aex", 0x20e70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_CC } }
 
 /* aex LIMM,BRAKET,UIMM6_20,BRAKETdup 0010011001100111x111xxxxxxxxxxxx */
-{ "aex", 0x26677000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "aex", 0x26677000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* aex<.cc> LIMM,BRAKET,UIMM6_20,BRAKETdup 0010011011100111x111xxxxxx1xxxxx */
-{ "aex", 0x26e77020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_CC } }
+{ "aex", 0x26e77020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_CC } }
 
 /* aex LIMM,BRAKET,SIMM12_20,BRAKETdup 0010011010100111x111xxxxxxxxxxxx */
-{ "aex", 0x26a77000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "aex", 0x26a77000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* aex LIMM,BRAKET,LIMMdup,BRAKETdup 0010011000100111x111111110xxxxxx */
-{ "aex", 0x26277f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 } }
+{ "aex", 0x26277f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 } }
 
 /* aex<.cc> LIMM,BRAKET,LIMMdup,BRAKETdup 0010011011100111x1111111100xxxxx */
-{ "aex", 0x26e77f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_CC } }
+{ "aex", 0x26e77f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_CC } }
 
 /* aexl RB,BRAKET,RC,BRAKETdup 01011xxx001001110xxxxxxxxxxxxxxx */
-{ "aexl", 0x58270000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "aexl", 0x58270000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* aexl<.cc> RB,BRAKET,RC,BRAKETdup 01011xxx111001110xxxxxxxxx0xxxxx */
-{ "aexl", 0x58e70000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_CC } }
+{ "aexl", 0x58e70000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_CC } }
 
 /* aexl RB,BRAKET,UIMM6_20,BRAKETdup 01011xxx011001110xxxxxxxxxxxxxxx */
-{ "aexl", 0x58670000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "aexl", 0x58670000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* aexl<.cc> RB,BRAKET,UIMM6_20,BRAKETdup 01011xxx111001110xxxxxxxxx1xxxxx */
-{ "aexl", 0x58e70020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC } }
+{ "aexl", 0x58e70020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC } }
 
 /* aexl RB,BRAKET,SIMM12_20,BRAKETdup 01011xxx101001110xxxxxxxxxxxxxxx */
-{ "aexl", 0x58a70000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "aexl", 0x58a70000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* aexl RB,BRAKET,XIMM,BRAKETdup 01011xxx001001110xxx111100xxxxxx */
-{ "aexl", 0x58270f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, XIMM, BRAKETdup }, { 0 } }
+{ "aexl", 0x58270f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, XIMM, BRAKETdup }, { 0 } }
 
 /* aexl<.cc> RB,BRAKET,XIMM,BRAKETdup 01011xxx111001110xxx1111000xxxxx */
-{ "aexl", 0x58e70f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, XIMM, BRAKETdup }, { C_CC } }
+{ "aexl", 0x58e70f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, XIMM, BRAKETdup }, { C_CC } }
 
 /* aexl RB,BRAKET,LIMM,BRAKETdup 01011xxx001001110xxx111110xxxxxx */
-{ "aexl", 0x58270f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "aexl", 0x58270f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* aexl<.cc> RB,BRAKET,LIMM,BRAKETdup 01011xxx111001110xxx1111100xxxxx */
-{ "aexl", 0x58e70f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_CC } }
+{ "aexl", 0x58e70f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_CC } }
 
 /* and<.f> RA,RB,RC 00100xxx00000100xxxxxxxxxxxxxxxx */
-{ "and", 0x20040000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "and", 0x20040000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* and<.f> ZA,RB,RC 00100xxx00000100xxxxxxxxxx111110 */
-{ "and", 0x2004003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "and", 0x2004003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* and<.f><.cc> RB,RBdup,RC 00100xxx11000100xxxxxxxxxx0xxxxx */
-{ "and", 0x20c40000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "and", 0x20c40000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* and<.f> RA,RB,UIMM6_20 00100xxx01000100xxxxxxxxxxxxxxxx */
-{ "and", 0x20440000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "and", 0x20440000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* and<.f> ZA,RB,UIMM6_20 00100xxx01000100xxxxxxxxxx111110 */
-{ "and", 0x2044003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "and", 0x2044003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* and<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11000100xxxxxxxxxx1xxxxx */
-{ "and", 0x20c40020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "and", 0x20c40020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* and<.f> RB,RBdup,SIMM12_20 00100xxx10000100xxxxxxxxxxxxxxxx */
-{ "and", 0x20840000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "and", 0x20840000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* and<.f> RA,LIMM,RC 0010011000000100x111xxxxxxxxxxxx */
-{ "and", 0x26047000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "and", 0x26047000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* and<.f> RA,RB,LIMM 00100xxx00000100xxxx111110xxxxxx */
-{ "and", 0x20040f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "and", 0x20040f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* and<.f> ZA,LIMM,RC 0010011000000100x111xxxxxx111110 */
-{ "and", 0x2604703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "and", 0x2604703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* and<.f> ZA,RB,LIMM 00100xxx00000100xxxx111110111110 */
-{ "and", 0x20040fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "and", 0x20040fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* and<.f><.cc> RB,RBdup,LIMM 00100xxx11000100xxxx1111100xxxxx */
-{ "and", 0x20c40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "and", 0x20c40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* and<.f><.cc> ZA,LIMM,RC 0010011011000100x111xxxxxx0xxxxx */
-{ "and", 0x26c47000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "and", 0x26c47000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* and<.f> RA,LIMM,UIMM6_20 0010011001000100x111xxxxxxxxxxxx */
-{ "and", 0x26447000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "and", 0x26447000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* and<.f> ZA,LIMM,UIMM6_20 0010011001000100x111xxxxxx111110 */
-{ "and", 0x2644703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "and", 0x2644703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* and<.f><.cc> ZA,LIMM,UIMM6_20 0010011011000100x111xxxxxx1xxxxx */
-{ "and", 0x26c47020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "and", 0x26c47020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* and<.f> ZA,LIMM,SIMM12_20 0010011010000100x111xxxxxxxxxxxx */
-{ "and", 0x26847000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "and", 0x26847000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* and<.f> RA,LIMM,LIMMdup 0010011000000100x111111110xxxxxx */
-{ "and", 0x26047f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "and", 0x26047f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* and<.f> ZA,LIMM,LIMMdup 0010011000000100x111111110111110 */
-{ "and", 0x26047fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "and", 0x26047fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* and<.f><.cc> ZA,LIMM,LIMMdup 0010011011000100x1111111100xxxxx */
-{ "and", 0x26c47f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "and", 0x26c47f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* andl<.f> RA,RB,RC 01011xxx00000100xxxxxxxxxxxxxxxx */
-{ "andl", 0x58040000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "andl", 0x58040000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* andl<.f> ZA,RB,RC 01011xxx00000100xxxxxxxxxx111110 */
-{ "andl", 0x5804003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "andl", 0x5804003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* andl<.f><.cc> RB,RBdup,RC 01011xxx11000100xxxxxxxxxx0xxxxx */
-{ "andl", 0x58c40000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "andl", 0x58c40000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* andl<.f> RA,RB,UIMM6_20 01011xxx01000100xxxxxxxxxxxxxxxx */
-{ "andl", 0x58440000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "andl", 0x58440000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* andl<.f> ZA,RB,UIMM6_20 01011xxx01000100xxxxxxxxxx111110 */
-{ "andl", 0x5844003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "andl", 0x5844003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* andl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11000100xxxxxxxxxx1xxxxx */
-{ "andl", 0x58c40020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "andl", 0x58c40020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* andl<.f> RB,RBdup,SIMM12_20 01011xxx10000100xxxxxxxxxxxxxxxx */
-{ "andl", 0x58840000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "andl", 0x58840000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* andl<.f> RA,XIMM,RC 0101110000000100x111xxxxxxxxxxxx */
-{ "andl", 0x5c047000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "andl", 0x5c047000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* andl<.f> RA,RB,XIMM 01011xxx00000100xxxx111100xxxxxx */
-{ "andl", 0x58040f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "andl", 0x58040f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* andl<.f> ZA,XIMM,RC 0101110000000100x111xxxxxx111110 */
-{ "andl", 0x5c04703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "andl", 0x5c04703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* andl<.f> ZA,RB,XIMM 01011xxx00000100xxxx111100111110 */
-{ "andl", 0x58040f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "andl", 0x58040f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* andl<.f><.cc> ZA,XIMM,RC 0101110011000100x111xxxxxx0xxxxx */
-{ "andl", 0x5cc47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "andl", 0x5cc47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* andl<.f><.cc> RB,RBdup,XIMM 01011xxx11000100xxxx1111000xxxxx */
-{ "andl", 0x58c40f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "andl", 0x58c40f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* andl<.f> RA,XIMM,UIMM6_20 0101110001000100x111xxxxxxxxxxxx */
-{ "andl", 0x5c447000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "andl", 0x5c447000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* andl<.f> ZA,XIMM,UIMM6_20 0101110001000100x111xxxxxx111110 */
-{ "andl", 0x5c44703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "andl", 0x5c44703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* andl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011000100x111xxxxxx1xxxxx */
-{ "andl", 0x5cc47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "andl", 0x5cc47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* andl<.f> RA,LIMM,RC 0101111000000100x111xxxxxxxxxxxx */
-{ "andl", 0x5e047000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "andl", 0x5e047000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* andl<.f> RA,RB,LIMM 01011xxx00000100xxxx111110xxxxxx */
-{ "andl", 0x58040f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "andl", 0x58040f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* andl<.f> ZA,LIMM,RC 0101111000000100x111xxxxxx111110 */
-{ "andl", 0x5e04703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "andl", 0x5e04703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* andl<.f> ZA,RB,LIMM 01011xxx00000100xxxx111110111110 */
-{ "andl", 0x58040fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "andl", 0x58040fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* andl<.f><.cc> ZA,LIMM,RC 0101111011000100x111xxxxxx0xxxxx */
-{ "andl", 0x5ec47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "andl", 0x5ec47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* andl<.f><.cc> RB,RBdup,LIMM 01011xxx11000100xxxx1111100xxxxx */
-{ "andl", 0x58c40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "andl", 0x58c40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* andl<.f> RA,LIMM,UIMM6_20 0101111001000100x111xxxxxxxxxxxx */
-{ "andl", 0x5e447000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "andl", 0x5e447000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* andl<.f> ZA,LIMM,UIMM6_20 0101111001000100x111xxxxxx111110 */
-{ "andl", 0x5e44703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "andl", 0x5e44703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* andl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011000100x111xxxxxx1xxxxx */
-{ "andl", 0x5ec47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "andl", 0x5ec47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* andl<.f> ZA,XIMM,SIMM12_20 0101110010000100x111xxxxxxxxxxxx */
-{ "andl", 0x5c847000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "andl", 0x5c847000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* andl<.f> ZA,LIMM,SIMM12_20 0101111010000100x111xxxxxxxxxxxx */
-{ "andl", 0x5e847000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "andl", 0x5e847000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* andl<.f> RA,XIMM,XIMMdup 0101110000000100x111111100xxxxxx */
-{ "andl", 0x5c047f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "andl", 0x5c047f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* andl<.f> ZA,XIMM,XIMMdup 0101110000000100x111111100111110 */
-{ "andl", 0x5c047f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "andl", 0x5c047f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* andl<.f><.cc> ZA,XIMM,XIMMdup 0101110011000100x1111111000xxxxx */
-{ "andl", 0x5cc47f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "andl", 0x5cc47f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* andl<.f> RA,LIMM,LIMMdup 0101111000000100x111111110xxxxxx */
-{ "andl", 0x5e047f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "andl", 0x5e047f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* andl<.f> ZA,LIMM,LIMMdup 0101111000000100x111111110111110 */
-{ "andl", 0x5e047fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "andl", 0x5e047fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* andl<.f><.cc> ZA,LIMM,LIMMdup 0101111011000100x1111111100xxxxx */
-{ "andl", 0x5ec47f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "andl", 0x5ec47f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* andl_s RB_S,RB_Sdup,RC_S 01111xxxxxx01000 */
-{ "andl_s", 0x00007808, 0x0000f81f, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "andl_s", 0x00007808, 0x0000f81f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* and_s RB_S,RB_Sdup,RC_S 01111xxxxxx00100 */
-{ "and_s", 0x00007804, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "and_s", 0x00007804, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* asl<.f> RB,RC 00100xxx00101111xxxxxxxxxx000000 */
-{ "asl", 0x202f0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_F } }
+{ "asl", 0x202f0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* asl<.f> ZA,RC 0010011000101111x111xxxxxx000000 */
-{ "asl", 0x262f7000, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RC }, { C_F } }
+{ "asl", 0x262f7000, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* asl<.f> RA,RB,RC 00101xxx00000000xxxxxxxxxxxxxxxx */
 { "asl", 0x28000000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, RB, RC }, { C_F } }
@@ -1226,10 +1226,10 @@
 { "asl", 0x28c00000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* asl<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx000000 */
-{ "asl", 0x206f0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "asl", 0x206f0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* asl<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx000000 */
-{ "asl", 0x266f7000, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "asl", 0x266f7000, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* asl<.f> RA,RB,UIMM6_20 00101xxx01000000xxxxxxxxxxxxxxxx */
 { "asl", 0x28400000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F } }
@@ -1244,10 +1244,10 @@
 { "asl", 0x28800000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* asl<.f> RB,LIMM 00100xxx00101111xxxx111110000000 */
-{ "asl", 0x202f0f80, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_F } }
+{ "asl", 0x202f0f80, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* asl<.f> ZA,LIMM 0010011000101111x111111110000000 */
-{ "asl", 0x262f7f80, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM }, { C_F } }
+{ "asl", 0x262f7f80, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* asl<.f> RA,LIMM,RC 0010111000000000x111xxxxxxxxxxxx */
 { "asl", 0x2e007000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F } }
@@ -1289,130 +1289,130 @@
 { "asl", 0x2ec07f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* asll<.f> RA,RB,RC 01011xxx00100000xxxxxxxxxxxxxxxx */
-{ "asll", 0x58200000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "asll", 0x58200000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* asll<.f> ZA,RB,RC 01011xxx00100000xxxxxxxxxx111110 */
-{ "asll", 0x5820003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "asll", 0x5820003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* asll<.f><.cc> RB,RBdup,RC 01011xxx11100000xxxxxxxxxx0xxxxx */
-{ "asll", 0x58e00000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "asll", 0x58e00000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* asll<.f> RB,RC 01011xxx00101111xxxxxxxxxx000000 */
-{ "asll", 0x582f0000, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "asll", 0x582f0000, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* asll<.f> ZA,RC 0101111000101111x111xxxxxx000000 */
-{ "asll", 0x5e2f7000, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "asll", 0x5e2f7000, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* asll<.f> RA,RB,UIMM6_20 01011xxx01100000xxxxxxxxxxxxxxxx */
-{ "asll", 0x58600000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "asll", 0x58600000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* asll<.f> ZA,RB,UIMM6_20 01011xxx01100000xxxxxxxxxx111110 */
-{ "asll", 0x5860003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "asll", 0x5860003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* asll<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11100000xxxxxxxxxx1xxxxx */
-{ "asll", 0x58e00020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "asll", 0x58e00020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* asll<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx000000 */
-{ "asll", 0x586f0000, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "asll", 0x586f0000, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* asll<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx000000 */
-{ "asll", 0x5e6f7000, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "asll", 0x5e6f7000, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* asll<.f> RB,RBdup,SIMM12_20 01011xxx10100000xxxxxxxxxxxxxxxx */
-{ "asll", 0x58a00000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "asll", 0x58a00000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* asll<.f> RA,XIMM,RC 0101110000100000x111xxxxxxxxxxxx */
-{ "asll", 0x5c207000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "asll", 0x5c207000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* asll<.f> RA,RB,XIMM 01011xxx00100000xxxx111100xxxxxx */
-{ "asll", 0x58200f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "asll", 0x58200f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* asll<.f> ZA,XIMM,RC 0101110000100000x111xxxxxx111110 */
-{ "asll", 0x5c20703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "asll", 0x5c20703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* asll<.f> ZA,RB,XIMM 01011xxx00100000xxxx111100111110 */
-{ "asll", 0x58200f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "asll", 0x58200f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* asll<.f><.cc> ZA,XIMM,RC 0101110011100000x111xxxxxx0xxxxx */
-{ "asll", 0x5ce07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "asll", 0x5ce07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* asll<.f><.cc> RB,RBdup,XIMM 01011xxx11100000xxxx1111000xxxxx */
-{ "asll", 0x58e00f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "asll", 0x58e00f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* asll<.f> RB,XIMM 01011xxx00101111xxxx111100000000 */
-{ "asll", 0x582f0f00, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "asll", 0x582f0f00, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* asll<.f> ZA,XIMM 0101111000101111x111111100000000 */
-{ "asll", 0x5e2f7f00, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "asll", 0x5e2f7f00, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* asll<.f> RA,XIMM,UIMM6_20 0101110001100000x111xxxxxxxxxxxx */
-{ "asll", 0x5c607000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "asll", 0x5c607000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* asll<.f> ZA,XIMM,UIMM6_20 0101110001100000x111xxxxxx111110 */
-{ "asll", 0x5c60703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "asll", 0x5c60703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* asll<.f><.cc> ZA,XIMM,UIMM6_20 0101110011100000x111xxxxxx1xxxxx */
-{ "asll", 0x5ce07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "asll", 0x5ce07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* asll<.f> RA,LIMM,RC 0101111000100000x111xxxxxxxxxxxx */
-{ "asll", 0x5e207000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "asll", 0x5e207000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* asll<.f> RA,RB,LIMM 01011xxx00100000xxxx111110xxxxxx */
-{ "asll", 0x58200f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "asll", 0x58200f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* asll<.f> ZA,LIMM,RC 0101111000100000x111xxxxxx111110 */
-{ "asll", 0x5e20703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "asll", 0x5e20703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* asll<.f> ZA,RB,LIMM 01011xxx00100000xxxx111110111110 */
-{ "asll", 0x58200fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "asll", 0x58200fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* asll<.f><.cc> ZA,LIMM,RC 0101111011100000x111xxxxxx0xxxxx */
-{ "asll", 0x5ee07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "asll", 0x5ee07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* asll<.f><.cc> RB,RBdup,LIMM 01011xxx11100000xxxx1111100xxxxx */
-{ "asll", 0x58e00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "asll", 0x58e00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* asll<.f> RB,LIMM 01011xxx00101111xxxx111110000000 */
-{ "asll", 0x582f0f80, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "asll", 0x582f0f80, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* asll<.f> ZA,LIMM 0101111000101111x111111110000000 */
-{ "asll", 0x5e2f7f80, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "asll", 0x5e2f7f80, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* asll<.f> RA,LIMM,UIMM6_20 0101111001100000x111xxxxxxxxxxxx */
-{ "asll", 0x5e607000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "asll", 0x5e607000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* asll<.f> ZA,LIMM,UIMM6_20 0101111001100000x111xxxxxx111110 */
-{ "asll", 0x5e60703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "asll", 0x5e60703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* asll<.f><.cc> ZA,LIMM,UIMM6_20 0101111011100000x111xxxxxx1xxxxx */
-{ "asll", 0x5ee07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "asll", 0x5ee07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* asll<.f> ZA,XIMM,SIMM12_20 0101110010100000x111xxxxxxxxxxxx */
-{ "asll", 0x5ca07000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "asll", 0x5ca07000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* asll<.f> ZA,LIMM,SIMM12_20 0101111010100000x111xxxxxxxxxxxx */
-{ "asll", 0x5ea07000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "asll", 0x5ea07000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* asll<.f> RA,XIMM,XIMMdup 0101110000100000x111111100xxxxxx */
-{ "asll", 0x5c207f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "asll", 0x5c207f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* asll<.f> ZA,XIMM,XIMMdup 0101110000100000x111111100111110 */
-{ "asll", 0x5c207f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "asll", 0x5c207f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* asll<.f><.cc> ZA,XIMM,XIMMdup 0101110011100000x1111111000xxxxx */
-{ "asll", 0x5ce07f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "asll", 0x5ce07f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* asll<.f> RA,LIMM,LIMMdup 0101111000100000x111111110xxxxxx */
-{ "asll", 0x5e207f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "asll", 0x5e207f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* asll<.f> ZA,LIMM,LIMMdup 0101111000100000x111111110111110 */
-{ "asll", 0x5e207fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "asll", 0x5e207fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* asll<.f><.cc> ZA,LIMM,LIMMdup 0101111011100000x1111111100xxxxx */
-{ "asll", 0x5ee07f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "asll", 0x5ee07f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* asl_s RB_S,RC_S 01111xxxxxx11011 */
-{ "asl_s", 0x0000781b, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RC_S }, { 0 } }
+{ "asl_s", 0x0000781b, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* asl_s RB_S,RB_Sdup,RC_S 01111xxxxxx11000 */
 { "asl_s", 0x00007818, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 } }
@@ -1421,10 +1421,10 @@
 { "asl_s", 0x0000b800, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
 
 /* asr<.f> RB,RC 00100xxx00101111xxxxxxxxxx000001 */
-{ "asr", 0x202f0001, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_F } }
+{ "asr", 0x202f0001, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* asr<.f> ZA,RC 0010011000101111x111xxxxxx000001 */
-{ "asr", 0x262f7001, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RC }, { C_F } }
+{ "asr", 0x262f7001, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* asr<.f> RA,RB,RC 00101xxx00000010xxxxxxxxxxxxxxxx */
 { "asr", 0x28020000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, RB, RC }, { C_F } }
@@ -1436,10 +1436,10 @@
 { "asr", 0x28c20000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* asr<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx000001 */
-{ "asr", 0x206f0001, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "asr", 0x206f0001, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* asr<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx000001 */
-{ "asr", 0x266f7001, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "asr", 0x266f7001, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* asr<.f> RA,RB,UIMM6_20 00101xxx01000010xxxxxxxxxxxxxxxx */
 { "asr", 0x28420000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F } }
@@ -1454,10 +1454,10 @@
 { "asr", 0x28820000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* asr<.f> RB,LIMM 00100xxx00101111xxxx111110000001 */
-{ "asr", 0x202f0f81, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_F } }
+{ "asr", 0x202f0f81, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* asr<.f> ZA,LIMM 0010011000101111x111111110000001 */
-{ "asr", 0x262f7f81, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM }, { C_F } }
+{ "asr", 0x262f7f81, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* asr<.f> RA,LIMM,RC 0010111000000010x111xxxxxxxxxxxx */
 { "asr", 0x2e027000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F } }
@@ -1535,130 +1535,130 @@
 { "asr8", 0x2e2f7f8d, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, SHFT1, { ZA, LIMM }, { C_F } }
 
 /* asrl<.f> RA,RB,RC 01011xxx00100010xxxxxxxxxxxxxxxx */
-{ "asrl", 0x58220000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "asrl", 0x58220000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* asrl<.f> ZA,RB,RC 01011xxx00100010xxxxxxxxxx111110 */
-{ "asrl", 0x5822003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "asrl", 0x5822003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* asrl<.f><.cc> RB,RBdup,RC 01011xxx11100010xxxxxxxxxx0xxxxx */
-{ "asrl", 0x58e20000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "asrl", 0x58e20000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* asrl<.f> RB,RC 01011xxx00101111xxxxxxxxxx000001 */
-{ "asrl", 0x582f0001, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "asrl", 0x582f0001, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* asrl<.f> ZA,RC 0101111000101111x111xxxxxx000001 */
-{ "asrl", 0x5e2f7001, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "asrl", 0x5e2f7001, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* asrl<.f> RA,RB,UIMM6_20 01011xxx01100010xxxxxxxxxxxxxxxx */
-{ "asrl", 0x58620000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "asrl", 0x58620000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* asrl<.f> ZA,RB,UIMM6_20 01011xxx01100010xxxxxxxxxx111110 */
-{ "asrl", 0x5862003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "asrl", 0x5862003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* asrl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11100010xxxxxxxxxx1xxxxx */
-{ "asrl", 0x58e20020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "asrl", 0x58e20020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* asrl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx000001 */
-{ "asrl", 0x586f0001, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "asrl", 0x586f0001, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* asrl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx000001 */
-{ "asrl", 0x5e6f7001, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "asrl", 0x5e6f7001, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* asrl<.f> RB,RBdup,SIMM12_20 01011xxx10100010xxxxxxxxxxxxxxxx */
-{ "asrl", 0x58a20000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "asrl", 0x58a20000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* asrl<.f> RA,XIMM,RC 0101110000100010x111xxxxxxxxxxxx */
-{ "asrl", 0x5c227000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "asrl", 0x5c227000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* asrl<.f> RA,RB,XIMM 01011xxx00100010xxxx111100xxxxxx */
-{ "asrl", 0x58220f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "asrl", 0x58220f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* asrl<.f> ZA,XIMM,RC 0101110000100010x111xxxxxx111110 */
-{ "asrl", 0x5c22703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "asrl", 0x5c22703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* asrl<.f> ZA,RB,XIMM 01011xxx00100010xxxx111100111110 */
-{ "asrl", 0x58220f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "asrl", 0x58220f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* asrl<.f><.cc> ZA,XIMM,RC 0101110011100010x111xxxxxx0xxxxx */
-{ "asrl", 0x5ce27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "asrl", 0x5ce27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* asrl<.f><.cc> RB,RBdup,XIMM 01011xxx11100010xxxx1111000xxxxx */
-{ "asrl", 0x58e20f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "asrl", 0x58e20f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* asrl<.f> RB,XIMM 01011xxx00101111xxxx111100000001 */
-{ "asrl", 0x582f0f01, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "asrl", 0x582f0f01, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* asrl<.f> ZA,XIMM 0101111000101111x111111100000001 */
-{ "asrl", 0x5e2f7f01, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "asrl", 0x5e2f7f01, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* asrl<.f> RA,XIMM,UIMM6_20 0101110001100010x111xxxxxxxxxxxx */
-{ "asrl", 0x5c627000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "asrl", 0x5c627000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* asrl<.f> ZA,XIMM,UIMM6_20 0101110001100010x111xxxxxx111110 */
-{ "asrl", 0x5c62703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "asrl", 0x5c62703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* asrl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011100010x111xxxxxx1xxxxx */
-{ "asrl", 0x5ce27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "asrl", 0x5ce27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* asrl<.f> RA,LIMM,RC 0101111000100010x111xxxxxxxxxxxx */
-{ "asrl", 0x5e227000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "asrl", 0x5e227000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* asrl<.f> RA,RB,LIMM 01011xxx00100010xxxx111110xxxxxx */
-{ "asrl", 0x58220f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "asrl", 0x58220f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* asrl<.f> ZA,LIMM,RC 0101111000100010x111xxxxxx111110 */
-{ "asrl", 0x5e22703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "asrl", 0x5e22703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* asrl<.f> ZA,RB,LIMM 01011xxx00100010xxxx111110111110 */
-{ "asrl", 0x58220fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "asrl", 0x58220fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* asrl<.f><.cc> ZA,LIMM,RC 0101111011100010x111xxxxxx0xxxxx */
-{ "asrl", 0x5ee27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "asrl", 0x5ee27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* asrl<.f><.cc> RB,RBdup,LIMM 01011xxx11100010xxxx1111100xxxxx */
-{ "asrl", 0x58e20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "asrl", 0x58e20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* asrl<.f> RB,LIMM 01011xxx00101111xxxx111110000001 */
-{ "asrl", 0x582f0f81, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "asrl", 0x582f0f81, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* asrl<.f> ZA,LIMM 0101111000101111x111111110000001 */
-{ "asrl", 0x5e2f7f81, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "asrl", 0x5e2f7f81, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* asrl<.f> RA,LIMM,UIMM6_20 0101111001100010x111xxxxxxxxxxxx */
-{ "asrl", 0x5e627000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "asrl", 0x5e627000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* asrl<.f> ZA,LIMM,UIMM6_20 0101111001100010x111xxxxxx111110 */
-{ "asrl", 0x5e62703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "asrl", 0x5e62703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* asrl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011100010x111xxxxxx1xxxxx */
-{ "asrl", 0x5ee27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "asrl", 0x5ee27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* asrl<.f> ZA,XIMM,SIMM12_20 0101110010100010x111xxxxxxxxxxxx */
-{ "asrl", 0x5ca27000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "asrl", 0x5ca27000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* asrl<.f> ZA,LIMM,SIMM12_20 0101111010100010x111xxxxxxxxxxxx */
-{ "asrl", 0x5ea27000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "asrl", 0x5ea27000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* asrl<.f> RA,XIMM,XIMMdup 0101110000100010x111111100xxxxxx */
-{ "asrl", 0x5c227f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "asrl", 0x5c227f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* asrl<.f> ZA,XIMM,XIMMdup 0101110000100010x111111100111110 */
-{ "asrl", 0x5c227f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "asrl", 0x5c227f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* asrl<.f><.cc> ZA,XIMM,XIMMdup 0101110011100010x1111111000xxxxx */
-{ "asrl", 0x5ce27f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "asrl", 0x5ce27f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* asrl<.f> RA,LIMM,LIMMdup 0101111000100010x111111110xxxxxx */
-{ "asrl", 0x5e227f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "asrl", 0x5e227f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* asrl<.f> ZA,LIMM,LIMMdup 0101111000100010x111111110111110 */
-{ "asrl", 0x5e227fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "asrl", 0x5e227fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* asrl<.f><.cc> ZA,LIMM,LIMMdup 0101111011100010x1111111100xxxxx */
-{ "asrl", 0x5ee27f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "asrl", 0x5ee27f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* asr_s RB_S,RC_S 01111xxxxxx11100 */
-{ "asr_s", 0x0000781c, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RC_S }, { 0 } }
+{ "asr_s", 0x0000781c, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* asr_s RB_S,RB_Sdup,RC_S 01111xxxxxx11010 */
 { "asr_s", 0x0000781a, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 } }
@@ -1667,250 +1667,250 @@
 { "asr_s", 0x0000b840, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
 
 /* atld<.op><.aq> RB,BRAKET,RC,BRAKETdup 00100xxx00101111xxxxxxxxxx110xxx */
-{ "atld", 0x202f0030, 0xf8ff0038, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_ATOP, C_AQ, C_RL } }
+{ "atld", 0x202f0030, 0xf8ff0038, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_ATOP, C_AQ, C_RL } }
 
 /* atldl<.op><.aq> RB,BRAKET,RC,BRAKETdup 01011xxx00101111xxxxxxxxxx110xxx */
-{ "atldl", 0x582f0030, 0xf8ff0038, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_ATOP, C_AQ, C_RL } }
+{ "atldl", 0x582f0030, 0xf8ff0038, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_ATOP, C_AQ, C_RL } }
 
 /* b<.d> SIMM25_A16_5 00000xxxxxxxxxx1xxxxxxxxxxxxxxxx */
-{ "b", 0x00010000, 0xf8010000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, NONE, { SIMM25_A16_5 }, { C_D } }
+{ "b", 0x00010000, 0xf8010000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, ARC_INSN_SUBCLASS_NONE, { SIMM25_A16_5 }, { C_D } }
 
 /* b<.cc><.d> SIMM21_A16_5 00000xxxxxxxxxx0xxxxxxxxxxxxxxxx */
-{ "b", 0x00000000, 0xf8010000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D } }
+{ "b", 0x00000000, 0xf8010000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, ARC_INSN_SUBCLASS_NONE, { SIMM21_A16_5 }, { C_CC, C_D } }
 
 /* bbit0<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx00110 */
-{ "bbit0", 0x08010006, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "bbit0", 0x08010006, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* bbit0<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx10110 */
-{ "bbit0", 0x08010016, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "bbit0", 0x08010016, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* bbit0 RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110000110 */
-{ "bbit0", 0x08010f86, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "bbit0", 0x08010f86, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* bbit0 LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx000110 */
-{ "bbit0", 0x0e017006, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "bbit0", 0x0e017006, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* bbit0 LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx010110 */
-{ "bbit0", 0x0e017016, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "bbit0", 0x0e017016, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* bbit0 LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110000110 */
-{ "bbit0", 0x0e017f86, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 } }
+{ "bbit0", 0x0e017f86, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT0, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 } }
 
 /* bbit0l<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx01110 */
-{ "bbit0l", 0x0801000e, 0xf801001f, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "bbit0l", 0x0801000e, 0xf801001f, ARC_OPCODE_ARC64, BBIT0, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* bbit0l<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx11110 */
-{ "bbit0l", 0x0801001e, 0xf801001f, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "bbit0l", 0x0801001e, 0xf801001f, ARC_OPCODE_ARC64, BBIT0, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* bbit0l RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110001110 */
-{ "bbit0l", 0x08010f8e, 0xf8010fff, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "bbit0l", 0x08010f8e, 0xf8010fff, ARC_OPCODE_ARC64, BBIT0, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* bbit0l LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx001110 */
-{ "bbit0l", 0x0e01700e, 0xff01703f, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "bbit0l", 0x0e01700e, 0xff01703f, ARC_OPCODE_ARC64, BBIT0, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* bbit0l LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx011110 */
-{ "bbit0l", 0x0e01701e, 0xff01703f, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "bbit0l", 0x0e01701e, 0xff01703f, ARC_OPCODE_ARC64, BBIT0, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* bbit0l LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110001110 */
-{ "bbit0l", 0x0e017f8e, 0xff017fff, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 } }
+{ "bbit0l", 0x0e017f8e, 0xff017fff, ARC_OPCODE_ARC64, BBIT0, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 } }
 
 /* bbit1<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx00111 */
-{ "bbit1", 0x08010007, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "bbit1", 0x08010007, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* bbit1<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx10111 */
-{ "bbit1", 0x08010017, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "bbit1", 0x08010017, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* bbit1 RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110000111 */
-{ "bbit1", 0x08010f87, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "bbit1", 0x08010f87, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* bbit1 LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx000111 */
-{ "bbit1", 0x0e017007, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "bbit1", 0x0e017007, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* bbit1 LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx010111 */
-{ "bbit1", 0x0e017017, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "bbit1", 0x0e017017, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* bbit1 LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110000111 */
-{ "bbit1", 0x0e017f87, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 } }
+{ "bbit1", 0x0e017f87, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BBIT1, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 } }
 
 /* bbit1l<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx01111 */
-{ "bbit1l", 0x0801000f, 0xf801001f, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "bbit1l", 0x0801000f, 0xf801001f, ARC_OPCODE_ARC64, BBIT1, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* bbit1l<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx11111 */
-{ "bbit1l", 0x0801001f, 0xf801001f, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "bbit1l", 0x0801001f, 0xf801001f, ARC_OPCODE_ARC64, BBIT1, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* bbit1l RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110001111 */
-{ "bbit1l", 0x08010f8f, 0xf8010fff, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "bbit1l", 0x08010f8f, 0xf8010fff, ARC_OPCODE_ARC64, BBIT1, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* bbit1l LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx001111 */
-{ "bbit1l", 0x0e01700f, 0xff01703f, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "bbit1l", 0x0e01700f, 0xff01703f, ARC_OPCODE_ARC64, BBIT1, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* bbit1l LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx011111 */
-{ "bbit1l", 0x0e01701f, 0xff01703f, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "bbit1l", 0x0e01701f, 0xff01703f, ARC_OPCODE_ARC64, BBIT1, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* bbit1l LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110001111 */
-{ "bbit1l", 0x0e017f8f, 0xff017fff, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 } }
+{ "bbit1l", 0x0e017f8f, 0xff017fff, ARC_OPCODE_ARC64, BBIT1, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 } }
 
 /* bclr<.f> RA,RB,RC 00100xxx00010000xxxxxxxxxxxxxxxx */
-{ "bclr", 0x20100000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "bclr", 0x20100000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bclr<.f> ZA,RB,RC 00100xxx00010000xxxxxxxxxx111110 */
-{ "bclr", 0x2010003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "bclr", 0x2010003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bclr<.f><.cc> RB,RBdup,RC 00100xxx11010000xxxxxxxxxx0xxxxx */
-{ "bclr", 0x20d00000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bclr", 0x20d00000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bclr<.f> RA,RB,UIMM6_20 00100xxx01010000xxxxxxxxxxxxxxxx */
-{ "bclr", 0x20500000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bclr", 0x20500000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bclr<.f> ZA,RB,UIMM6_20 00100xxx01010000xxxxxxxxxx111110 */
-{ "bclr", 0x2050003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bclr", 0x2050003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bclr<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11010000xxxxxxxxxx1xxxxx */
-{ "bclr", 0x20d00020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bclr", 0x20d00020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bclr<.f> RB,RBdup,SIMM12_20 00100xxx10010000xxxxxxxxxxxxxxxx */
-{ "bclr", 0x20900000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bclr", 0x20900000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bclr<.f> RA,LIMM,RC 0010011000010000x111xxxxxxxxxxxx */
-{ "bclr", 0x26107000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bclr", 0x26107000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bclr<.f> RA,RB,LIMM 00100xxx00010000xxxx111110xxxxxx */
-{ "bclr", 0x20100f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bclr", 0x20100f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bclr<.f> ZA,LIMM,RC 0010011000010000x111xxxxxx111110 */
-{ "bclr", 0x2610703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bclr", 0x2610703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bclr<.f> ZA,RB,LIMM 00100xxx00010000xxxx111110111110 */
-{ "bclr", 0x20100fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bclr", 0x20100fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bclr<.f><.cc> RB,RBdup,LIMM 00100xxx11010000xxxx1111100xxxxx */
-{ "bclr", 0x20d00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bclr", 0x20d00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bclr<.f><.cc> ZA,LIMM,RC 0010011011010000x111xxxxxx0xxxxx */
-{ "bclr", 0x26d07000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bclr", 0x26d07000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bclr<.f> RA,LIMM,UIMM6_20 0010011001010000x111xxxxxxxxxxxx */
-{ "bclr", 0x26507000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bclr", 0x26507000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bclr<.f> ZA,LIMM,UIMM6_20 0010011001010000x111xxxxxx111110 */
-{ "bclr", 0x2650703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bclr", 0x2650703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bclr<.f><.cc> ZA,LIMM,UIMM6_20 0010011011010000x111xxxxxx1xxxxx */
-{ "bclr", 0x26d07020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bclr", 0x26d07020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bclr<.f> ZA,LIMM,SIMM12_20 0010011010010000x111xxxxxxxxxxxx */
-{ "bclr", 0x26907000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bclr", 0x26907000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bclr<.f> RA,LIMM,LIMMdup 0010011000010000x111111110xxxxxx */
-{ "bclr", 0x26107f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bclr", 0x26107f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bclr<.f> ZA,LIMM,LIMMdup 0010011000010000x111111110111110 */
-{ "bclr", 0x26107fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bclr", 0x26107fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bclr<.f><.cc> ZA,LIMM,LIMMdup 0010011011010000x1111111100xxxxx */
-{ "bclr", 0x26d07f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bclr", 0x26d07f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bclrl<.f> RA,RB,RC 01011xxx00010000xxxxxxxxxxxxxxxx */
-{ "bclrl", 0x58100000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "bclrl", 0x58100000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bclrl<.f> ZA,RB,RC 01011xxx00010000xxxxxxxxxx111110 */
-{ "bclrl", 0x5810003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "bclrl", 0x5810003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bclrl<.f><.cc> RB,RBdup,RC 01011xxx11010000xxxxxxxxxx0xxxxx */
-{ "bclrl", 0x58d00000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bclrl", 0x58d00000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bclrl<.f> RA,RB,UIMM6_20 01011xxx01010000xxxxxxxxxxxxxxxx */
-{ "bclrl", 0x58500000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bclrl", 0x58500000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bclrl<.f> ZA,RB,UIMM6_20 01011xxx01010000xxxxxxxxxx111110 */
-{ "bclrl", 0x5850003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bclrl", 0x5850003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bclrl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11010000xxxxxxxxxx1xxxxx */
-{ "bclrl", 0x58d00020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bclrl", 0x58d00020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bclrl<.f> RB,RBdup,SIMM12_20 01011xxx10010000xxxxxxxxxxxxxxxx */
-{ "bclrl", 0x58900000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bclrl", 0x58900000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bclrl<.f> RA,XIMM,RC 0101110000010000x111xxxxxxxxxxxx */
-{ "bclrl", 0x5c107000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "bclrl", 0x5c107000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* bclrl<.f> RA,RB,XIMM 01011xxx00010000xxxx111100xxxxxx */
-{ "bclrl", 0x58100f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "bclrl", 0x58100f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* bclrl<.f> ZA,XIMM,RC 0101110000010000x111xxxxxx111110 */
-{ "bclrl", 0x5c10703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "bclrl", 0x5c10703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* bclrl<.f> ZA,RB,XIMM 01011xxx00010000xxxx111100111110 */
-{ "bclrl", 0x58100f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "bclrl", 0x58100f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* bclrl<.f><.cc> ZA,XIMM,RC 0101110011010000x111xxxxxx0xxxxx */
-{ "bclrl", 0x5cd07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "bclrl", 0x5cd07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* bclrl<.f><.cc> RB,RBdup,XIMM 01011xxx11010000xxxx1111000xxxxx */
-{ "bclrl", 0x58d00f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "bclrl", 0x58d00f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* bclrl<.f> RA,XIMM,UIMM6_20 0101110001010000x111xxxxxxxxxxxx */
-{ "bclrl", 0x5c507000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "bclrl", 0x5c507000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bclrl<.f> ZA,XIMM,UIMM6_20 0101110001010000x111xxxxxx111110 */
-{ "bclrl", 0x5c50703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "bclrl", 0x5c50703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bclrl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011010000x111xxxxxx1xxxxx */
-{ "bclrl", 0x5cd07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bclrl", 0x5cd07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bclrl<.f> RA,LIMM,RC 0101111000010000x111xxxxxxxxxxxx */
-{ "bclrl", 0x5e107000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bclrl", 0x5e107000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bclrl<.f> RA,RB,LIMM 01011xxx00010000xxxx111110xxxxxx */
-{ "bclrl", 0x58100f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bclrl", 0x58100f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bclrl<.f> ZA,LIMM,RC 0101111000010000x111xxxxxx111110 */
-{ "bclrl", 0x5e10703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bclrl", 0x5e10703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bclrl<.f> ZA,RB,LIMM 01011xxx00010000xxxx111110111110 */
-{ "bclrl", 0x58100fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bclrl", 0x58100fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bclrl<.f><.cc> ZA,LIMM,RC 0101111011010000x111xxxxxx0xxxxx */
-{ "bclrl", 0x5ed07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bclrl", 0x5ed07000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bclrl<.f><.cc> RB,RBdup,LIMM 01011xxx11010000xxxx1111100xxxxx */
-{ "bclrl", 0x58d00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bclrl", 0x58d00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bclrl<.f> RA,LIMM,UIMM6_20 0101111001010000x111xxxxxxxxxxxx */
-{ "bclrl", 0x5e507000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bclrl", 0x5e507000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bclrl<.f> ZA,LIMM,UIMM6_20 0101111001010000x111xxxxxx111110 */
-{ "bclrl", 0x5e50703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bclrl", 0x5e50703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bclrl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011010000x111xxxxxx1xxxxx */
-{ "bclrl", 0x5ed07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bclrl", 0x5ed07020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bclrl<.f> ZA,XIMM,SIMM12_20 0101110010010000x111xxxxxxxxxxxx */
-{ "bclrl", 0x5c907000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "bclrl", 0x5c907000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* bclrl<.f> ZA,LIMM,SIMM12_20 0101111010010000x111xxxxxxxxxxxx */
-{ "bclrl", 0x5e907000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bclrl", 0x5e907000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bclrl<.f> RA,XIMM,XIMMdup 0101110000010000x111111100xxxxxx */
-{ "bclrl", 0x5c107f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "bclrl", 0x5c107f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* bclrl<.f> ZA,XIMM,XIMMdup 0101110000010000x111111100111110 */
-{ "bclrl", 0x5c107f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "bclrl", 0x5c107f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* bclrl<.f><.cc> ZA,XIMM,XIMMdup 0101110011010000x1111111000xxxxx */
-{ "bclrl", 0x5cd07f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "bclrl", 0x5cd07f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* bclrl<.f> RA,LIMM,LIMMdup 0101111000010000x111111110xxxxxx */
-{ "bclrl", 0x5e107f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bclrl", 0x5e107f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bclrl<.f> ZA,LIMM,LIMMdup 0101111000010000x111111110111110 */
-{ "bclrl", 0x5e107fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bclrl", 0x5e107fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bclrl<.f><.cc> ZA,LIMM,LIMMdup 0101111011010000x1111111100xxxxx */
-{ "bclrl", 0x5ed07f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bclrl", 0x5ed07f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bclr_s RB_S,RB_Sdup,UIMM5_11_S 10111xxx101xxxxx */
-{ "bclr_s", 0x0000b8a0, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
+{ "bclr_s", 0x0000b8a0, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
 
 /* beq_s SIMM10_A16_7_S 1111001xxxxxxxxx */
 { "beq_s", 0x0000f200, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_EQ } }
@@ -1928,184 +1928,184 @@
 { "bhs_s", 0x0000f740, 0x0000ffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HS } }
 
 /* bi BRAKET,RC,BRAKETdup 00100xxx001001000xxxxxxxxxxxxxxx */
-{ "bi", 0x20240000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BI, NONE, { BRAKET, RC, BRAKETdup }, { 0 } }
+{ "bi", 0x20240000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BI, ARC_INSN_SUBCLASS_NONE, { BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* bi BRAKET,LIMM,BRAKETdup 00100xxx001001000xxx111110xxxxxx */
-{ "bi", 0x20240f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BI, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "bi", 0x20240f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BI, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* bic<.f> RA,RB,RC 00100xxx00000110xxxxxxxxxxxxxxxx */
-{ "bic", 0x20060000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "bic", 0x20060000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bic<.f> ZA,RB,RC 00100xxx00000110xxxxxxxxxx111110 */
-{ "bic", 0x2006003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "bic", 0x2006003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bic<.f><.cc> RB,RBdup,RC 00100xxx11000110xxxxxxxxxx0xxxxx */
-{ "bic", 0x20c60000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bic", 0x20c60000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bic<.f> RA,RB,UIMM6_20 00100xxx01000110xxxxxxxxxxxxxxxx */
-{ "bic", 0x20460000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bic", 0x20460000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bic<.f> ZA,RB,UIMM6_20 00100xxx01000110xxxxxxxxxx111110 */
-{ "bic", 0x2046003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bic", 0x2046003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bic<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11000110xxxxxxxxxx1xxxxx */
-{ "bic", 0x20c60020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bic", 0x20c60020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bic<.f> RB,RBdup,SIMM12_20 00100xxx10000110xxxxxxxxxxxxxxxx */
-{ "bic", 0x20860000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bic", 0x20860000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bic<.f> RA,LIMM,RC 0010011000000110x111xxxxxxxxxxxx */
-{ "bic", 0x26067000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bic", 0x26067000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bic<.f> RA,RB,LIMM 00100xxx00000110xxxx111110xxxxxx */
-{ "bic", 0x20060f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bic", 0x20060f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bic<.f> ZA,LIMM,RC 0010011000000110x111xxxxxx111110 */
-{ "bic", 0x2606703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bic", 0x2606703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bic<.f> ZA,RB,LIMM 00100xxx00000110xxxx111110111110 */
-{ "bic", 0x20060fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bic", 0x20060fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bic<.f><.cc> RB,RBdup,LIMM 00100xxx11000110xxxx1111100xxxxx */
-{ "bic", 0x20c60f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bic", 0x20c60f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bic<.f><.cc> ZA,LIMM,RC 0010011011000110x111xxxxxx0xxxxx */
-{ "bic", 0x26c67000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bic", 0x26c67000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bic<.f> RA,LIMM,UIMM6_20 0010011001000110x111xxxxxxxxxxxx */
-{ "bic", 0x26467000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bic", 0x26467000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bic<.f> ZA,LIMM,UIMM6_20 0010011001000110x111xxxxxx111110 */
-{ "bic", 0x2646703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bic", 0x2646703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bic<.f><.cc> ZA,LIMM,UIMM6_20 0010011011000110x111xxxxxx1xxxxx */
-{ "bic", 0x26c67020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bic", 0x26c67020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bic<.f> ZA,LIMM,SIMM12_20 0010011010000110x111xxxxxxxxxxxx */
-{ "bic", 0x26867000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bic", 0x26867000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bic<.f> RA,LIMM,LIMMdup 0010011000000110x111111110xxxxxx */
-{ "bic", 0x26067f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bic", 0x26067f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bic<.f> ZA,LIMM,LIMMdup 0010011000000110x111111110111110 */
-{ "bic", 0x26067fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bic", 0x26067fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bic<.f><.cc> ZA,LIMM,LIMMdup 0010011011000110x1111111100xxxxx */
-{ "bic", 0x26c67f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bic", 0x26c67f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bicl<.f> RA,RB,RC 01011xxx00000110xxxxxxxxxxxxxxxx */
-{ "bicl", 0x58060000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "bicl", 0x58060000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bicl<.f> ZA,RB,RC 01011xxx00000110xxxxxxxxxx111110 */
-{ "bicl", 0x5806003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "bicl", 0x5806003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bicl<.f><.cc> RB,RBdup,RC 01011xxx11000110xxxxxxxxxx0xxxxx */
-{ "bicl", 0x58c60000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bicl", 0x58c60000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bicl<.f> RA,RB,UIMM6_20 01011xxx01000110xxxxxxxxxxxxxxxx */
-{ "bicl", 0x58460000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bicl", 0x58460000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bicl<.f> ZA,RB,UIMM6_20 01011xxx01000110xxxxxxxxxx111110 */
-{ "bicl", 0x5846003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bicl", 0x5846003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bicl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11000110xxxxxxxxxx1xxxxx */
-{ "bicl", 0x58c60020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bicl", 0x58c60020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bicl<.f> RB,RBdup,SIMM12_20 01011xxx10000110xxxxxxxxxxxxxxxx */
-{ "bicl", 0x58860000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bicl", 0x58860000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bicl<.f> RA,XIMM,RC 0101110000000110x111xxxxxxxxxxxx */
-{ "bicl", 0x5c067000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "bicl", 0x5c067000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* bicl<.f> RA,RB,XIMM 01011xxx00000110xxxx111100xxxxxx */
-{ "bicl", 0x58060f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "bicl", 0x58060f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* bicl<.f> ZA,XIMM,RC 0101110000000110x111xxxxxx111110 */
-{ "bicl", 0x5c06703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "bicl", 0x5c06703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* bicl<.f> ZA,RB,XIMM 01011xxx00000110xxxx111100111110 */
-{ "bicl", 0x58060f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "bicl", 0x58060f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* bicl<.f><.cc> ZA,XIMM,RC 0101110011000110x111xxxxxx0xxxxx */
-{ "bicl", 0x5cc67000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "bicl", 0x5cc67000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* bicl<.f><.cc> RB,RBdup,XIMM 01011xxx11000110xxxx1111000xxxxx */
-{ "bicl", 0x58c60f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "bicl", 0x58c60f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* bicl<.f> RA,XIMM,UIMM6_20 0101110001000110x111xxxxxxxxxxxx */
-{ "bicl", 0x5c467000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "bicl", 0x5c467000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bicl<.f> ZA,XIMM,UIMM6_20 0101110001000110x111xxxxxx111110 */
-{ "bicl", 0x5c46703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "bicl", 0x5c46703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bicl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011000110x111xxxxxx1xxxxx */
-{ "bicl", 0x5cc67020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bicl", 0x5cc67020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bicl<.f> RA,LIMM,RC 0101111000000110x111xxxxxxxxxxxx */
-{ "bicl", 0x5e067000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bicl", 0x5e067000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bicl<.f> RA,RB,LIMM 01011xxx00000110xxxx111110xxxxxx */
-{ "bicl", 0x58060f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bicl", 0x58060f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bicl<.f> ZA,LIMM,RC 0101111000000110x111xxxxxx111110 */
-{ "bicl", 0x5e06703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bicl", 0x5e06703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bicl<.f> ZA,RB,LIMM 01011xxx00000110xxxx111110111110 */
-{ "bicl", 0x58060fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bicl", 0x58060fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bicl<.f><.cc> ZA,LIMM,RC 0101111011000110x111xxxxxx0xxxxx */
-{ "bicl", 0x5ec67000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bicl", 0x5ec67000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bicl<.f><.cc> RB,RBdup,LIMM 01011xxx11000110xxxx1111100xxxxx */
-{ "bicl", 0x58c60f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bicl", 0x58c60f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bicl<.f> RA,LIMM,UIMM6_20 0101111001000110x111xxxxxxxxxxxx */
-{ "bicl", 0x5e467000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bicl", 0x5e467000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bicl<.f> ZA,LIMM,UIMM6_20 0101111001000110x111xxxxxx111110 */
-{ "bicl", 0x5e46703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bicl", 0x5e46703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bicl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011000110x111xxxxxx1xxxxx */
-{ "bicl", 0x5ec67020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bicl", 0x5ec67020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bicl<.f> ZA,XIMM,SIMM12_20 0101110010000110x111xxxxxxxxxxxx */
-{ "bicl", 0x5c867000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "bicl", 0x5c867000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* bicl<.f> ZA,LIMM,SIMM12_20 0101111010000110x111xxxxxxxxxxxx */
-{ "bicl", 0x5e867000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bicl", 0x5e867000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bicl<.f> RA,XIMM,XIMMdup 0101110000000110x111111100xxxxxx */
-{ "bicl", 0x5c067f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "bicl", 0x5c067f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* bicl<.f> ZA,XIMM,XIMMdup 0101110000000110x111111100111110 */
-{ "bicl", 0x5c067f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "bicl", 0x5c067f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* bicl<.f><.cc> ZA,XIMM,XIMMdup 0101110011000110x1111111000xxxxx */
-{ "bicl", 0x5cc67f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "bicl", 0x5cc67f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* bicl<.f> RA,LIMM,LIMMdup 0101111000000110x111111110xxxxxx */
-{ "bicl", 0x5e067f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bicl", 0x5e067f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bicl<.f> ZA,LIMM,LIMMdup 0101111000000110x111111110111110 */
-{ "bicl", 0x5e067fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bicl", 0x5e067fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bicl<.f><.cc> ZA,LIMM,LIMMdup 0101111011000110x1111111100xxxxx */
-{ "bicl", 0x5ec67f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bicl", 0x5ec67f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bic_s RB_S,RB_Sdup,RC_S 01111xxxxxx00110 */
-{ "bic_s", 0x00007806, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "bic_s", 0x00007806, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* bih BRAKET,RC,BRAKETdup 00100xxx001001010xxxxxxxxxxxxxxx */
-{ "bih", 0x20250000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BIH, NONE, { BRAKET, RC, BRAKETdup }, { 0 } }
+{ "bih", 0x20250000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BIH, ARC_INSN_SUBCLASS_NONE, { BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* bih BRAKET,LIMM,BRAKETdup 00100xxx001001010xxx111110xxxxxx */
-{ "bih", 0x20250f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BIH, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "bih", 0x20250f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BIH, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* bl<.d> SIMM25_A32_5 00001xxxxxxxxx10xxxxxxxxxxxxxxxx */
-{ "bl", 0x08020000, 0xf8030000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, NONE, { SIMM25_A32_5 }, { C_D } }
+{ "bl", 0x08020000, 0xf8030000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, ARC_INSN_SUBCLASS_NONE, { SIMM25_A32_5 }, { C_D } }
 
 /* bl<.cc><.d> SIMM21_A32_5 00001xxxxxxxxx00xxxxxxxxxxxxxxxx */
-{ "bl", 0x08000000, 0xf8030000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, NONE, { SIMM21_A32_5 }, { C_CC, C_D } }
+{ "bl", 0x08000000, 0xf8030000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, ARC_INSN_SUBCLASS_NONE, { SIMM21_A32_5 }, { C_CC, C_D } }
 
 /* ble_s SIMM7_A16_10_S 1111011011xxxxxx */
 { "ble_s", 0x0000f6c0, 0x0000ffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LE } }
@@ -2120,1105 +2120,1105 @@
 { "blt_s", 0x0000f680, 0x0000ffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LT } }
 
 /* bl_s SIMM13_A32_5_S 11111xxxxxxxxxxx */
-{ "bl_s", 0x0000f800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, NONE, { SIMM13_A32_5_S }, { 0 } }
+{ "bl_s", 0x0000f800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, ARC_INSN_SUBCLASS_NONE, { SIMM13_A32_5_S }, { 0 } }
 
 /* bl_s LIMM34 0111101111100000 */
-{ "bl_s", 0x00007be0, 0x0000ffff, ARC_OPCODE_ARC64, BRANCH, NONE, { LIMM34 }, { 0 } }
+{ "bl_s", 0x00007be0, 0x0000ffff, ARC_OPCODE_ARC64, BRANCH, ARC_INSN_SUBCLASS_NONE, { LIMM34 }, { 0 } }
 
 /* bmsk<.f> RA,RB,RC 00100xxx00010011xxxxxxxxxxxxxxxx */
-{ "bmsk", 0x20130000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "bmsk", 0x20130000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bmsk<.f> ZA,RB,RC 00100xxx00010011xxxxxxxxxx111110 */
-{ "bmsk", 0x2013003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "bmsk", 0x2013003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bmsk<.f><.cc> RB,RBdup,RC 00100xxx11010011xxxxxxxxxx0xxxxx */
-{ "bmsk", 0x20d30000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bmsk", 0x20d30000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bmsk<.f> RA,RB,UIMM6_20 00100xxx01010011xxxxxxxxxxxxxxxx */
-{ "bmsk", 0x20530000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bmsk", 0x20530000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bmsk<.f> ZA,RB,UIMM6_20 00100xxx01010011xxxxxxxxxx111110 */
-{ "bmsk", 0x2053003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bmsk", 0x2053003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bmsk<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11010011xxxxxxxxxx1xxxxx */
-{ "bmsk", 0x20d30020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bmsk", 0x20d30020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmsk<.f> RB,RBdup,SIMM12_20 00100xxx10010011xxxxxxxxxxxxxxxx */
-{ "bmsk", 0x20930000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bmsk", 0x20930000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bmsk<.f> RA,LIMM,RC 0010011000010011x111xxxxxxxxxxxx */
-{ "bmsk", 0x26137000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bmsk", 0x26137000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bmsk<.f> RA,RB,LIMM 00100xxx00010011xxxx111110xxxxxx */
-{ "bmsk", 0x20130f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bmsk", 0x20130f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bmsk<.f> ZA,LIMM,RC 0010011000010011x111xxxxxx111110 */
-{ "bmsk", 0x2613703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bmsk", 0x2613703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bmsk<.f> ZA,RB,LIMM 00100xxx00010011xxxx111110111110 */
-{ "bmsk", 0x20130fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bmsk", 0x20130fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bmsk<.f><.cc> RB,RBdup,LIMM 00100xxx11010011xxxx1111100xxxxx */
-{ "bmsk", 0x20d30f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bmsk", 0x20d30f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bmsk<.f><.cc> ZA,LIMM,RC 0010011011010011x111xxxxxx0xxxxx */
-{ "bmsk", 0x26d37000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bmsk", 0x26d37000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bmsk<.f> RA,LIMM,UIMM6_20 0010011001010011x111xxxxxxxxxxxx */
-{ "bmsk", 0x26537000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bmsk", 0x26537000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bmsk<.f> ZA,LIMM,UIMM6_20 0010011001010011x111xxxxxx111110 */
-{ "bmsk", 0x2653703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bmsk", 0x2653703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bmsk<.f><.cc> ZA,LIMM,UIMM6_20 0010011011010011x111xxxxxx1xxxxx */
-{ "bmsk", 0x26d37020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bmsk", 0x26d37020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmsk<.f> ZA,LIMM,SIMM12_20 0010011010010011x111xxxxxxxxxxxx */
-{ "bmsk", 0x26937000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bmsk", 0x26937000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bmsk<.f> RA,LIMM,LIMMdup 0010011000010011x111111110xxxxxx */
-{ "bmsk", 0x26137f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bmsk", 0x26137f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bmsk<.f> ZA,LIMM,LIMMdup 0010011000010011x111111110111110 */
-{ "bmsk", 0x26137fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bmsk", 0x26137fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bmsk<.f><.cc> ZA,LIMM,LIMMdup 0010011011010011x1111111100xxxxx */
-{ "bmsk", 0x26d37f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bmsk", 0x26d37f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bmskl<.f> RA,RB,RC 01011xxx00010011xxxxxxxxxxxxxxxx */
-{ "bmskl", 0x58130000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "bmskl", 0x58130000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bmskl<.f> ZA,RB,RC 01011xxx00010011xxxxxxxxxx111110 */
-{ "bmskl", 0x5813003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "bmskl", 0x5813003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bmskl<.f><.cc> RB,RBdup,RC 01011xxx11010011xxxxxxxxxx0xxxxx */
-{ "bmskl", 0x58d30000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bmskl", 0x58d30000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bmskl<.f> RA,RB,UIMM6_20 01011xxx01010011xxxxxxxxxxxxxxxx */
-{ "bmskl", 0x58530000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bmskl", 0x58530000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bmskl<.f> ZA,RB,UIMM6_20 01011xxx01010011xxxxxxxxxx111110 */
-{ "bmskl", 0x5853003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bmskl", 0x5853003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bmskl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11010011xxxxxxxxxx1xxxxx */
-{ "bmskl", 0x58d30020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bmskl", 0x58d30020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmskl<.f> RB,RBdup,SIMM12_20 01011xxx10010011xxxxxxxxxxxxxxxx */
-{ "bmskl", 0x58930000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bmskl", 0x58930000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bmskl<.f> RA,XIMM,RC 0101110000010011x111xxxxxxxxxxxx */
-{ "bmskl", 0x5c137000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "bmskl", 0x5c137000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* bmskl<.f> RA,RB,XIMM 01011xxx00010011xxxx111100xxxxxx */
-{ "bmskl", 0x58130f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "bmskl", 0x58130f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* bmskl<.f> ZA,XIMM,RC 0101110000010011x111xxxxxx111110 */
-{ "bmskl", 0x5c13703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "bmskl", 0x5c13703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* bmskl<.f> ZA,RB,XIMM 01011xxx00010011xxxx111100111110 */
-{ "bmskl", 0x58130f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "bmskl", 0x58130f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* bmskl<.f><.cc> ZA,XIMM,RC 0101110011010011x111xxxxxx0xxxxx */
-{ "bmskl", 0x5cd37000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "bmskl", 0x5cd37000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* bmskl<.f><.cc> RB,RBdup,XIMM 01011xxx11010011xxxx1111000xxxxx */
-{ "bmskl", 0x58d30f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "bmskl", 0x58d30f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* bmskl<.f> RA,XIMM,UIMM6_20 0101110001010011x111xxxxxxxxxxxx */
-{ "bmskl", 0x5c537000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "bmskl", 0x5c537000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bmskl<.f> ZA,XIMM,UIMM6_20 0101110001010011x111xxxxxx111110 */
-{ "bmskl", 0x5c53703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "bmskl", 0x5c53703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bmskl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011010011x111xxxxxx1xxxxx */
-{ "bmskl", 0x5cd37020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bmskl", 0x5cd37020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmskl<.f> RA,LIMM,RC 0101111000010011x111xxxxxxxxxxxx */
-{ "bmskl", 0x5e137000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bmskl", 0x5e137000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bmskl<.f> RA,RB,LIMM 01011xxx00010011xxxx111110xxxxxx */
-{ "bmskl", 0x58130f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bmskl", 0x58130f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bmskl<.f> ZA,LIMM,RC 0101111000010011x111xxxxxx111110 */
-{ "bmskl", 0x5e13703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bmskl", 0x5e13703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bmskl<.f> ZA,RB,LIMM 01011xxx00010011xxxx111110111110 */
-{ "bmskl", 0x58130fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bmskl", 0x58130fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bmskl<.f><.cc> ZA,LIMM,RC 0101111011010011x111xxxxxx0xxxxx */
-{ "bmskl", 0x5ed37000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bmskl", 0x5ed37000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bmskl<.f><.cc> RB,RBdup,LIMM 01011xxx11010011xxxx1111100xxxxx */
-{ "bmskl", 0x58d30f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bmskl", 0x58d30f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bmskl<.f> RA,LIMM,UIMM6_20 0101111001010011x111xxxxxxxxxxxx */
-{ "bmskl", 0x5e537000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bmskl", 0x5e537000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bmskl<.f> ZA,LIMM,UIMM6_20 0101111001010011x111xxxxxx111110 */
-{ "bmskl", 0x5e53703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bmskl", 0x5e53703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bmskl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011010011x111xxxxxx1xxxxx */
-{ "bmskl", 0x5ed37020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bmskl", 0x5ed37020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmskl<.f> ZA,XIMM,SIMM12_20 0101110010010011x111xxxxxxxxxxxx */
-{ "bmskl", 0x5c937000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "bmskl", 0x5c937000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* bmskl<.f> ZA,LIMM,SIMM12_20 0101111010010011x111xxxxxxxxxxxx */
-{ "bmskl", 0x5e937000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bmskl", 0x5e937000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bmskl<.f> RA,XIMM,XIMMdup 0101110000010011x111111100xxxxxx */
-{ "bmskl", 0x5c137f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "bmskl", 0x5c137f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* bmskl<.f> ZA,XIMM,XIMMdup 0101110000010011x111111100111110 */
-{ "bmskl", 0x5c137f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "bmskl", 0x5c137f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* bmskl<.f><.cc> ZA,XIMM,XIMMdup 0101110011010011x1111111000xxxxx */
-{ "bmskl", 0x5cd37f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "bmskl", 0x5cd37f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* bmskl<.f> RA,LIMM,LIMMdup 0101111000010011x111111110xxxxxx */
-{ "bmskl", 0x5e137f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bmskl", 0x5e137f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bmskl<.f> ZA,LIMM,LIMMdup 0101111000010011x111111110111110 */
-{ "bmskl", 0x5e137fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bmskl", 0x5e137fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bmskl<.f><.cc> ZA,LIMM,LIMMdup 0101111011010011x1111111100xxxxx */
-{ "bmskl", 0x5ed37f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bmskl", 0x5ed37f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bmskn<.f> RA,RB,RC 00100xxx00101100xxxxxxxxxxxxxxxx */
-{ "bmskn", 0x202c0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "bmskn", 0x202c0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bmskn<.f> ZA,RB,RC 00100xxx00101100xxxxxxxxxx111110 */
-{ "bmskn", 0x202c003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "bmskn", 0x202c003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bmskn<.f><.cc> RB,RBdup,RC 00100xxx11101100xxxxxxxxxx0xxxxx */
-{ "bmskn", 0x20ec0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bmskn", 0x20ec0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bmskn<.f> RA,RB,UIMM6_20 00100xxx01101100xxxxxxxxxxxxxxxx */
-{ "bmskn", 0x206c0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bmskn", 0x206c0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bmskn<.f> ZA,RB,UIMM6_20 00100xxx01101100xxxxxxxxxx111110 */
-{ "bmskn", 0x206c003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bmskn", 0x206c003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bmskn<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11101100xxxxxxxxxx1xxxxx */
-{ "bmskn", 0x20ec0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bmskn", 0x20ec0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmskn<.f> RB,RBdup,SIMM12_20 00100xxx10101100xxxxxxxxxxxxxxxx */
-{ "bmskn", 0x20ac0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bmskn", 0x20ac0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bmskn<.f> RA,LIMM,RC 0010011000101100x111xxxxxxxxxxxx */
-{ "bmskn", 0x262c7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bmskn", 0x262c7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bmskn<.f> RA,RB,LIMM 00100xxx00101100xxxx111110xxxxxx */
-{ "bmskn", 0x202c0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bmskn", 0x202c0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bmskn<.f> ZA,LIMM,RC 0010011000101100x111xxxxxx111110 */
-{ "bmskn", 0x262c703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bmskn", 0x262c703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bmskn<.f> ZA,RB,LIMM 00100xxx00101100xxxx111110111110 */
-{ "bmskn", 0x202c0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bmskn", 0x202c0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bmskn<.f><.cc> RB,RBdup,LIMM 00100xxx11101100xxxx1111100xxxxx */
-{ "bmskn", 0x20ec0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bmskn", 0x20ec0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bmskn<.f><.cc> ZA,LIMM,RC 0010011011101100x111xxxxxx0xxxxx */
-{ "bmskn", 0x26ec7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bmskn", 0x26ec7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bmskn<.f> RA,LIMM,UIMM6_20 0010011001101100x111xxxxxxxxxxxx */
-{ "bmskn", 0x266c7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bmskn", 0x266c7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bmskn<.f> ZA,LIMM,UIMM6_20 0010011001101100x111xxxxxx111110 */
-{ "bmskn", 0x266c703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bmskn", 0x266c703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bmskn<.f><.cc> ZA,LIMM,UIMM6_20 0010011011101100x111xxxxxx1xxxxx */
-{ "bmskn", 0x26ec7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bmskn", 0x26ec7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmskn<.f> ZA,LIMM,SIMM12_20 0010011010101100x111xxxxxxxxxxxx */
-{ "bmskn", 0x26ac7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bmskn", 0x26ac7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bmskn<.f> RA,LIMM,LIMMdup 0010011000101100x111111110xxxxxx */
-{ "bmskn", 0x262c7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bmskn", 0x262c7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bmskn<.f> ZA,LIMM,LIMMdup 0010011000101100x111111110111110 */
-{ "bmskn", 0x262c7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bmskn", 0x262c7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bmskn<.f><.cc> ZA,LIMM,LIMMdup 0010011011101100x1111111100xxxxx */
-{ "bmskn", 0x26ec7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bmskn", 0x26ec7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bmsknl<.f> RA,RB,RC 01011xxx00101100xxxxxxxxxxxxxxxx */
-{ "bmsknl", 0x582c0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "bmsknl", 0x582c0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bmsknl<.f> ZA,RB,RC 01011xxx00101100xxxxxxxxxx111110 */
-{ "bmsknl", 0x582c003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "bmsknl", 0x582c003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bmsknl<.f><.cc> RB,RBdup,RC 01011xxx11101100xxxxxxxxxx0xxxxx */
-{ "bmsknl", 0x58ec0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bmsknl", 0x58ec0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bmsknl<.f> RA,RB,UIMM6_20 01011xxx01101100xxxxxxxxxxxxxxxx */
-{ "bmsknl", 0x586c0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bmsknl", 0x586c0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bmsknl<.f> ZA,RB,UIMM6_20 01011xxx01101100xxxxxxxxxx111110 */
-{ "bmsknl", 0x586c003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bmsknl", 0x586c003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bmsknl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11101100xxxxxxxxxx1xxxxx */
-{ "bmsknl", 0x58ec0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bmsknl", 0x58ec0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmsknl<.f> RB,RBdup,SIMM12_20 01011xxx10101100xxxxxxxxxxxxxxxx */
-{ "bmsknl", 0x58ac0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bmsknl", 0x58ac0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bmsknl<.f> RA,XIMM,RC 0101110000101100x111xxxxxxxxxxxx */
-{ "bmsknl", 0x5c2c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "bmsknl", 0x5c2c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* bmsknl<.f> RA,RB,XIMM 01011xxx00101100xxxx111100xxxxxx */
-{ "bmsknl", 0x582c0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "bmsknl", 0x582c0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* bmsknl<.f> ZA,XIMM,RC 0101110000101100x111xxxxxx111110 */
-{ "bmsknl", 0x5c2c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "bmsknl", 0x5c2c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* bmsknl<.f> ZA,RB,XIMM 01011xxx00101100xxxx111100111110 */
-{ "bmsknl", 0x582c0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "bmsknl", 0x582c0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* bmsknl<.f><.cc> ZA,XIMM,RC 0101110011101100x111xxxxxx0xxxxx */
-{ "bmsknl", 0x5cec7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "bmsknl", 0x5cec7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* bmsknl<.f><.cc> RB,RBdup,XIMM 01011xxx11101100xxxx1111000xxxxx */
-{ "bmsknl", 0x58ec0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "bmsknl", 0x58ec0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* bmsknl<.f> RA,XIMM,UIMM6_20 0101110001101100x111xxxxxxxxxxxx */
-{ "bmsknl", 0x5c6c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "bmsknl", 0x5c6c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bmsknl<.f> ZA,XIMM,UIMM6_20 0101110001101100x111xxxxxx111110 */
-{ "bmsknl", 0x5c6c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "bmsknl", 0x5c6c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bmsknl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011101100x111xxxxxx1xxxxx */
-{ "bmsknl", 0x5cec7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bmsknl", 0x5cec7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmsknl<.f> RA,LIMM,RC 0101111000101100x111xxxxxxxxxxxx */
-{ "bmsknl", 0x5e2c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bmsknl", 0x5e2c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bmsknl<.f> RA,RB,LIMM 01011xxx00101100xxxx111110xxxxxx */
-{ "bmsknl", 0x582c0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bmsknl", 0x582c0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bmsknl<.f> ZA,LIMM,RC 0101111000101100x111xxxxxx111110 */
-{ "bmsknl", 0x5e2c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bmsknl", 0x5e2c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bmsknl<.f> ZA,RB,LIMM 01011xxx00101100xxxx111110111110 */
-{ "bmsknl", 0x582c0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bmsknl", 0x582c0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bmsknl<.f><.cc> ZA,LIMM,RC 0101111011101100x111xxxxxx0xxxxx */
-{ "bmsknl", 0x5eec7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bmsknl", 0x5eec7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bmsknl<.f><.cc> RB,RBdup,LIMM 01011xxx11101100xxxx1111100xxxxx */
-{ "bmsknl", 0x58ec0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bmsknl", 0x58ec0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bmsknl<.f> RA,LIMM,UIMM6_20 0101111001101100x111xxxxxxxxxxxx */
-{ "bmsknl", 0x5e6c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bmsknl", 0x5e6c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bmsknl<.f> ZA,LIMM,UIMM6_20 0101111001101100x111xxxxxx111110 */
-{ "bmsknl", 0x5e6c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bmsknl", 0x5e6c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bmsknl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011101100x111xxxxxx1xxxxx */
-{ "bmsknl", 0x5eec7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bmsknl", 0x5eec7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bmsknl<.f> ZA,XIMM,SIMM12_20 0101110010101100x111xxxxxxxxxxxx */
-{ "bmsknl", 0x5cac7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "bmsknl", 0x5cac7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* bmsknl<.f> ZA,LIMM,SIMM12_20 0101111010101100x111xxxxxxxxxxxx */
-{ "bmsknl", 0x5eac7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bmsknl", 0x5eac7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bmsknl<.f> RA,XIMM,XIMMdup 0101110000101100x111111100xxxxxx */
-{ "bmsknl", 0x5c2c7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "bmsknl", 0x5c2c7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* bmsknl<.f> ZA,XIMM,XIMMdup 0101110000101100x111111100111110 */
-{ "bmsknl", 0x5c2c7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "bmsknl", 0x5c2c7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* bmsknl<.f><.cc> ZA,XIMM,XIMMdup 0101110011101100x1111111000xxxxx */
-{ "bmsknl", 0x5cec7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "bmsknl", 0x5cec7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* bmsknl<.f> RA,LIMM,LIMMdup 0101111000101100x111111110xxxxxx */
-{ "bmsknl", 0x5e2c7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bmsknl", 0x5e2c7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bmsknl<.f> ZA,LIMM,LIMMdup 0101111000101100x111111110111110 */
-{ "bmsknl", 0x5e2c7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bmsknl", 0x5e2c7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bmsknl<.f><.cc> ZA,LIMM,LIMMdup 0101111011101100x1111111100xxxxx */
-{ "bmsknl", 0x5eec7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bmsknl", 0x5eec7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bmsk_s RB_S,RB_Sdup,UIMM5_11_S 10111xxx110xxxxx */
-{ "bmsk_s", 0x0000b8c0, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
+{ "bmsk_s", 0x0000b8c0, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
 
 /* bne_s SIMM10_A16_7_S 1111010xxxxxxxxx */
 { "bne_s", 0x0000f400, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_NE } }
 
 /* breq<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx00000 */
-{ "breq", 0x08010000, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_EQ } }
+{ "breq", 0x08010000, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_EQ } }
 
 /* breq<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx10000 */
-{ "breq", 0x08010010, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_EQ } }
+{ "breq", 0x08010010, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_EQ } }
 
 /* breq RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110000000 */
-{ "breq", 0x08010f80, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_EQ } }
+{ "breq", 0x08010f80, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_EQ } }
 
 /* breq LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx000000 */
-{ "breq", 0x0e017000, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_EQ } }
+{ "breq", 0x0e017000, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_EQ } }
 
 /* breq LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx010000 */
-{ "breq", 0x0e017010, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_EQ } }
+{ "breq", 0x0e017010, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_EQ } }
 
 /* breq LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110000000 */
-{ "breq", 0x0e017f80, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_EQ } }
+{ "breq", 0x0e017f80, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_EQ } }
 
 /* breql<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx01000 */
-{ "breql", 0x08010008, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "breql", 0x08010008, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* breql<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx11000 */
-{ "breql", 0x08010018, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "breql", 0x08010018, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* breql RB,XIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111100001000 */
-{ "breql", 0x08010f08, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
+{ "breql", 0x08010f08, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
 
 /* breql XIMM,RC,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx001000 */
-{ "breql", 0x0c017008, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "breql", 0x0c017008, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* breql XIMM,UIMM6_8,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx011000 */
-{ "breql", 0x0c017018, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "breql", 0x0c017018, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* breql RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110001000 */
-{ "breql", 0x08010f88, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "breql", 0x08010f88, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* breql LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx001000 */
-{ "breql", 0x0e017008, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "breql", 0x0e017008, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* breql LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx011000 */
-{ "breql", 0x0e017018, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "breql", 0x0e017018, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* breql_s RB_S,ZB_S,SIMM8_A16_9_S 11101xxx0xxxxxxx */
-{ "breql_s", 0x0000e800, 0x0000f880, ARC_OPCODE_ARC64, BRCC, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 } }
+{ "breql_s", 0x0000e800, 0x0000f880, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 } }
 
 /* breq_s RB_S,ZB_S,SIMM8_A16_9_S 11101xxx0xxxxxxx */
-{ "breq_s", 0x0000e800, 0x0000f880, ARC_OPCODE_ARC32, BRCC, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 } }
+{ "breq_s", 0x0000e800, 0x0000f880, ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 } }
 
 /* brge<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx00011 */
-{ "brge", 0x08010003, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_GE } }
+{ "brge", 0x08010003, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_GE } }
 
 /* brge<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx10011 */
-{ "brge", 0x08010013, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_GE } }
+{ "brge", 0x08010013, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_GE } }
 
 /* brge RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110000011 */
-{ "brge", 0x08010f83, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_GE } }
+{ "brge", 0x08010f83, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_GE } }
 
 /* brge LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx000011 */
-{ "brge", 0x0e017003, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_GE } }
+{ "brge", 0x0e017003, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_GE } }
 
 /* brge LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx010011 */
-{ "brge", 0x0e017013, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_GE } }
+{ "brge", 0x0e017013, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_GE } }
 
 /* brge LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110000011 */
-{ "brge", 0x0e017f83, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_GE } }
+{ "brge", 0x0e017f83, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_GE } }
 
 /* brgel<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx01011 */
-{ "brgel", 0x0801000b, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "brgel", 0x0801000b, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* brgel<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx11011 */
-{ "brgel", 0x0801001b, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "brgel", 0x0801001b, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* brgel RB,XIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111100001011 */
-{ "brgel", 0x08010f0b, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
+{ "brgel", 0x08010f0b, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brgel XIMM,RC,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx001011 */
-{ "brgel", 0x0c01700b, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brgel", 0x0c01700b, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brgel XIMM,UIMM6_8,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx011011 */
-{ "brgel", 0x0c01701b, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brgel", 0x0c01701b, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brgel RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110001011 */
-{ "brgel", 0x08010f8b, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "brgel", 0x08010f8b, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brgel LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx001011 */
-{ "brgel", 0x0e01700b, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brgel", 0x0e01700b, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brgel LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx011011 */
-{ "brgel", 0x0e01701b, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brgel", 0x0e01701b, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brhs<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx00101 */
-{ "brhs", 0x08010005, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_HS } }
+{ "brhs", 0x08010005, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_HS } }
 
 /* brhs<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx10101 */
-{ "brhs", 0x08010015, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_HS } }
+{ "brhs", 0x08010015, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_HS } }
 
 /* brhs RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110000101 */
-{ "brhs", 0x08010f85, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_HS } }
+{ "brhs", 0x08010f85, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_HS } }
 
 /* brhs LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx000101 */
-{ "brhs", 0x0e017005, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_HS } }
+{ "brhs", 0x0e017005, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_HS } }
 
 /* brhs LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx010101 */
-{ "brhs", 0x0e017015, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_HS } }
+{ "brhs", 0x0e017015, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_HS } }
 
 /* brhs LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110000101 */
-{ "brhs", 0x0e017f85, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_HS } }
+{ "brhs", 0x0e017f85, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_HS } }
 
 /* brhsl<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx01101 */
-{ "brhsl", 0x0801000d, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "brhsl", 0x0801000d, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* brhsl<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx11101 */
-{ "brhsl", 0x0801001d, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "brhsl", 0x0801001d, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* brhsl RB,XIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111100001101 */
-{ "brhsl", 0x08010f0d, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
+{ "brhsl", 0x08010f0d, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brhsl XIMM,RC,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx001101 */
-{ "brhsl", 0x0c01700d, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brhsl", 0x0c01700d, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brhsl XIMM,UIMM6_8,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx011101 */
-{ "brhsl", 0x0c01701d, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brhsl", 0x0c01701d, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brhsl RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110001101 */
-{ "brhsl", 0x08010f8d, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "brhsl", 0x08010f8d, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brhsl LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx001101 */
-{ "brhsl", 0x0e01700d, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brhsl", 0x0e01700d, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brhsl LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx011101 */
-{ "brhsl", 0x0e01701d, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brhsl", 0x0e01701d, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brk  00100101011011110000000000111111 */
-{ "brk", 0x256f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, {  }, { 0 } }
+{ "brk", 0x256f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* brk_s  0111111111111111 */
-{ "brk_s", 0x00007fff, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, {  }, { 0 } }
+{ "brk_s", 0x00007fff, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* brlo<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx00100 */
-{ "brlo", 0x08010004, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LO } }
+{ "brlo", 0x08010004, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LO } }
 
 /* brlo<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx10100 */
-{ "brlo", 0x08010014, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LO } }
+{ "brlo", 0x08010014, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LO } }
 
 /* brlo RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110000100 */
-{ "brlo", 0x08010f84, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LO } }
+{ "brlo", 0x08010f84, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LO } }
 
 /* brlo LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx000100 */
-{ "brlo", 0x0e017004, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LO } }
+{ "brlo", 0x0e017004, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LO } }
 
 /* brlo LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx010100 */
-{ "brlo", 0x0e017014, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LO } }
+{ "brlo", 0x0e017014, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LO } }
 
 /* brlo LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110000100 */
-{ "brlo", 0x0e017f84, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_LO } }
+{ "brlo", 0x0e017f84, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_LO } }
 
 /* brlol<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx01100 */
-{ "brlol", 0x0801000c, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "brlol", 0x0801000c, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* brlol<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx11100 */
-{ "brlol", 0x0801001c, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "brlol", 0x0801001c, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* brlol RB,XIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111100001100 */
-{ "brlol", 0x08010f0c, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
+{ "brlol", 0x08010f0c, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brlol XIMM,RC,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx001100 */
-{ "brlol", 0x0c01700c, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brlol", 0x0c01700c, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brlol XIMM,UIMM6_8,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx011100 */
-{ "brlol", 0x0c01701c, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brlol", 0x0c01701c, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brlol RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110001100 */
-{ "brlol", 0x08010f8c, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "brlol", 0x08010f8c, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brlol LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx001100 */
-{ "brlol", 0x0e01700c, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brlol", 0x0e01700c, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brlol LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx011100 */
-{ "brlol", 0x0e01701c, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brlol", 0x0e01701c, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brlt<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx00010 */
-{ "brlt", 0x08010002, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LT } }
+{ "brlt", 0x08010002, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LT } }
 
 /* brlt<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx10010 */
-{ "brlt", 0x08010012, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LT } }
+{ "brlt", 0x08010012, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LT } }
 
 /* brlt RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110000010 */
-{ "brlt", 0x08010f82, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LT } }
+{ "brlt", 0x08010f82, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LT } }
 
 /* brlt LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx000010 */
-{ "brlt", 0x0e017002, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LT } }
+{ "brlt", 0x0e017002, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LT } }
 
 /* brlt LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx010010 */
-{ "brlt", 0x0e017012, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LT } }
+{ "brlt", 0x0e017012, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LT } }
 
 /* brlt LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110000010 */
-{ "brlt", 0x0e017f82, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_LT } }
+{ "brlt", 0x0e017f82, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_LT } }
 
 /* brltl<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx01010 */
-{ "brltl", 0x0801000a, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "brltl", 0x0801000a, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* brltl<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx11010 */
-{ "brltl", 0x0801001a, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "brltl", 0x0801001a, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* brltl RB,XIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111100001010 */
-{ "brltl", 0x08010f0a, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
+{ "brltl", 0x08010f0a, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brltl XIMM,RC,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx001010 */
-{ "brltl", 0x0c01700a, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brltl", 0x0c01700a, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brltl XIMM,UIMM6_8,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx011010 */
-{ "brltl", 0x0c01701a, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brltl", 0x0c01701a, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brltl RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110001010 */
-{ "brltl", 0x08010f8a, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "brltl", 0x08010f8a, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brltl LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx001010 */
-{ "brltl", 0x0e01700a, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brltl", 0x0e01700a, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brltl LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx011010 */
-{ "brltl", 0x0e01701a, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brltl", 0x0e01701a, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brne<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx00001 */
-{ "brne", 0x08010001, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_NE } }
+{ "brne", 0x08010001, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_NE } }
 
 /* brne<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx10001 */
-{ "brne", 0x08010011, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_NE } }
+{ "brne", 0x08010011, 0xf801001f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_NE } }
 
 /* brne RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110000001 */
-{ "brne", 0x08010f81, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_NE } }
+{ "brne", 0x08010f81, 0xf8010fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_NE } }
 
 /* brne LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx000001 */
-{ "brne", 0x0e017001, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_NE } }
+{ "brne", 0x0e017001, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_NE } }
 
 /* brne LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx010001 */
-{ "brne", 0x0e017011, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_NE } }
+{ "brne", 0x0e017011, 0xff01703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_NE } }
 
 /* brne LIMM,LIMMdup,SIMM9_A16_8 00001110xxxxxxx1x111111110000001 */
-{ "brne", 0x0e017f81, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_NE } }
+{ "brne", 0x0e017f81, 0xff017fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_NE } }
 
 /* brnel<.d> RB,RC,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx01001 */
-{ "brnel", 0x08010009, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
+{ "brnel", 0x08010009, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, RC, SIMM9_A16_8 }, { C_D } }
 
 /* brnel<.d> RB,UIMM6_8,SIMM9_A16_8 00001xxxxxxxxxx1xxxxxxxxxxx11001 */
-{ "brnel", 0x08010019, 0xf801001f, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
+{ "brnel", 0x08010019, 0xf801001f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D } }
 
 /* brnel RB,XIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111100001001 */
-{ "brnel", 0x08010f09, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
+{ "brnel", 0x08010f09, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brnel XIMM,RC,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx001001 */
-{ "brnel", 0x0c017009, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brnel", 0x0c017009, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brnel XIMM,UIMM6_8,SIMM9_A16_8 00001100xxxxxxx1x111xxxxxx011001 */
-{ "brnel", 0x0c017019, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brnel", 0x0c017019, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brnel RB,LIMM,SIMM9_A16_8 00001xxxxxxxxxx1xxxx111110001001 */
-{ "brnel", 0x08010f89, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
+{ "brnel", 0x08010f89, 0xf8010fff, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 } }
 
 /* brnel LIMM,RC,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx001001 */
-{ "brnel", 0x0e017009, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
+{ "brnel", 0x0e017009, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 } }
 
 /* brnel LIMM,UIMM6_8,SIMM9_A16_8 00001110xxxxxxx1x111xxxxxx011001 */
-{ "brnel", 0x0e017019, 0xff01703f, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
+{ "brnel", 0x0e017019, 0xff01703f, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 } }
 
 /* brnel_s RB_S,ZB_S,SIMM8_A16_9_S 11101xxx1xxxxxxx */
-{ "brnel_s", 0x0000e880, 0x0000f880, ARC_OPCODE_ARC64, BRCC, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 } }
+{ "brnel_s", 0x0000e880, 0x0000f880, ARC_OPCODE_ARC64, BRCC, ARC_INSN_SUBCLASS_NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 } }
 
 /* brne_s RB_S,ZB_S,SIMM8_A16_9_S 11101xxx1xxxxxxx */
-{ "brne_s", 0x0000e880, 0x0000f880, ARC_OPCODE_ARC32, BRCC, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 } }
+{ "brne_s", 0x0000e880, 0x0000f880, ARC_OPCODE_ARC32, BRCC, ARC_INSN_SUBCLASS_NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 } }
 
 /* bset<.f> RA,RB,RC 00100xxx00001111xxxxxxxxxxxxxxxx */
-{ "bset", 0x200f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "bset", 0x200f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bset<.f> ZA,RB,RC 00100xxx00001111xxxxxxxxxx111110 */
-{ "bset", 0x200f003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "bset", 0x200f003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bset<.f><.cc> RB,RBdup,RC 00100xxx11001111xxxxxxxxxx0xxxxx */
-{ "bset", 0x20cf0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bset", 0x20cf0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bset<.f> RA,RB,UIMM6_20 00100xxx01001111xxxxxxxxxxxxxxxx */
-{ "bset", 0x204f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bset", 0x204f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bset<.f> ZA,RB,UIMM6_20 00100xxx01001111xxxxxxxxxx111110 */
-{ "bset", 0x204f003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bset", 0x204f003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bset<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11001111xxxxxxxxxx1xxxxx */
-{ "bset", 0x20cf0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bset", 0x20cf0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bset<.f> RB,RBdup,SIMM12_20 00100xxx10001111xxxxxxxxxxxxxxxx */
-{ "bset", 0x208f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bset", 0x208f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bset<.f> RA,LIMM,RC 0010011000001111x111xxxxxxxxxxxx */
-{ "bset", 0x260f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bset", 0x260f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bset<.f> RA,RB,LIMM 00100xxx00001111xxxx111110xxxxxx */
-{ "bset", 0x200f0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bset", 0x200f0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bset<.f> ZA,LIMM,RC 0010011000001111x111xxxxxx111110 */
-{ "bset", 0x260f703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bset", 0x260f703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bset<.f> ZA,RB,LIMM 00100xxx00001111xxxx111110111110 */
-{ "bset", 0x200f0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bset", 0x200f0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bset<.f><.cc> RB,RBdup,LIMM 00100xxx11001111xxxx1111100xxxxx */
-{ "bset", 0x20cf0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bset", 0x20cf0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bset<.f><.cc> ZA,LIMM,RC 0010011011001111x111xxxxxx0xxxxx */
-{ "bset", 0x26cf7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bset", 0x26cf7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bset<.f> RA,LIMM,UIMM6_20 0010011001001111x111xxxxxxxxxxxx */
-{ "bset", 0x264f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bset", 0x264f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bset<.f> ZA,LIMM,UIMM6_20 0010011001001111x111xxxxxx111110 */
-{ "bset", 0x264f703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bset", 0x264f703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bset<.f><.cc> ZA,LIMM,UIMM6_20 0010011011001111x111xxxxxx1xxxxx */
-{ "bset", 0x26cf7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bset", 0x26cf7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bset<.f> ZA,LIMM,SIMM12_20 0010011010001111x111xxxxxxxxxxxx */
-{ "bset", 0x268f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bset", 0x268f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bset<.f> RA,LIMM,LIMMdup 0010011000001111x111111110xxxxxx */
-{ "bset", 0x260f7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bset", 0x260f7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bset<.f> ZA,LIMM,LIMMdup 0010011000001111x111111110111110 */
-{ "bset", 0x260f7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bset", 0x260f7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bset<.f><.cc> ZA,LIMM,LIMMdup 0010011011001111x1111111100xxxxx */
-{ "bset", 0x26cf7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bset", 0x26cf7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bsetl<.f> RA,RB,RC 01011xxx00001111xxxxxxxxxxxxxxxx */
-{ "bsetl", 0x580f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "bsetl", 0x580f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bsetl<.f> ZA,RB,RC 01011xxx00001111xxxxxxxxxx111110 */
-{ "bsetl", 0x580f003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "bsetl", 0x580f003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bsetl<.f><.cc> RB,RBdup,RC 01011xxx11001111xxxxxxxxxx0xxxxx */
-{ "bsetl", 0x58cf0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bsetl", 0x58cf0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bsetl<.f> RA,RB,UIMM6_20 01011xxx01001111xxxxxxxxxxxxxxxx */
-{ "bsetl", 0x584f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bsetl", 0x584f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bsetl<.f> ZA,RB,UIMM6_20 01011xxx01001111xxxxxxxxxx111110 */
-{ "bsetl", 0x584f003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bsetl", 0x584f003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bsetl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11001111xxxxxxxxxx1xxxxx */
-{ "bsetl", 0x58cf0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bsetl", 0x58cf0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bsetl<.f> RB,RBdup,SIMM12_20 01011xxx10001111xxxxxxxxxxxxxxxx */
-{ "bsetl", 0x588f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bsetl", 0x588f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bsetl<.f> RA,XIMM,RC 0101110000001111x111xxxxxxxxxxxx */
-{ "bsetl", 0x5c0f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "bsetl", 0x5c0f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* bsetl<.f> RA,RB,XIMM 01011xxx00001111xxxx111100xxxxxx */
-{ "bsetl", 0x580f0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "bsetl", 0x580f0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* bsetl<.f> ZA,XIMM,RC 0101110000001111x111xxxxxx111110 */
-{ "bsetl", 0x5c0f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "bsetl", 0x5c0f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* bsetl<.f> ZA,RB,XIMM 01011xxx00001111xxxx111100111110 */
-{ "bsetl", 0x580f0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "bsetl", 0x580f0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* bsetl<.f><.cc> ZA,XIMM,RC 0101110011001111x111xxxxxx0xxxxx */
-{ "bsetl", 0x5ccf7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "bsetl", 0x5ccf7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* bsetl<.f><.cc> RB,RBdup,XIMM 01011xxx11001111xxxx1111000xxxxx */
-{ "bsetl", 0x58cf0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "bsetl", 0x58cf0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* bsetl<.f> RA,XIMM,UIMM6_20 0101110001001111x111xxxxxxxxxxxx */
-{ "bsetl", 0x5c4f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "bsetl", 0x5c4f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bsetl<.f> ZA,XIMM,UIMM6_20 0101110001001111x111xxxxxx111110 */
-{ "bsetl", 0x5c4f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "bsetl", 0x5c4f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bsetl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011001111x111xxxxxx1xxxxx */
-{ "bsetl", 0x5ccf7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bsetl", 0x5ccf7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bsetl<.f> RA,LIMM,RC 0101111000001111x111xxxxxxxxxxxx */
-{ "bsetl", 0x5e0f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bsetl", 0x5e0f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bsetl<.f> RA,RB,LIMM 01011xxx00001111xxxx111110xxxxxx */
-{ "bsetl", 0x580f0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bsetl", 0x580f0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bsetl<.f> ZA,LIMM,RC 0101111000001111x111xxxxxx111110 */
-{ "bsetl", 0x5e0f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bsetl", 0x5e0f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bsetl<.f> ZA,RB,LIMM 01011xxx00001111xxxx111110111110 */
-{ "bsetl", 0x580f0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bsetl", 0x580f0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bsetl<.f><.cc> ZA,LIMM,RC 0101111011001111x111xxxxxx0xxxxx */
-{ "bsetl", 0x5ecf7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bsetl", 0x5ecf7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bsetl<.f><.cc> RB,RBdup,LIMM 01011xxx11001111xxxx1111100xxxxx */
-{ "bsetl", 0x58cf0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bsetl", 0x58cf0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bsetl<.f> RA,LIMM,UIMM6_20 0101111001001111x111xxxxxxxxxxxx */
-{ "bsetl", 0x5e4f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bsetl", 0x5e4f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bsetl<.f> ZA,LIMM,UIMM6_20 0101111001001111x111xxxxxx111110 */
-{ "bsetl", 0x5e4f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bsetl", 0x5e4f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bsetl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011001111x111xxxxxx1xxxxx */
-{ "bsetl", 0x5ecf7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bsetl", 0x5ecf7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bsetl<.f> ZA,XIMM,SIMM12_20 0101110010001111x111xxxxxxxxxxxx */
-{ "bsetl", 0x5c8f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "bsetl", 0x5c8f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* bsetl<.f> ZA,LIMM,SIMM12_20 0101111010001111x111xxxxxxxxxxxx */
-{ "bsetl", 0x5e8f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bsetl", 0x5e8f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bsetl<.f> RA,XIMM,XIMMdup 0101110000001111x111111100xxxxxx */
-{ "bsetl", 0x5c0f7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "bsetl", 0x5c0f7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* bsetl<.f> ZA,XIMM,XIMMdup 0101110000001111x111111100111110 */
-{ "bsetl", 0x5c0f7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "bsetl", 0x5c0f7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* bsetl<.f><.cc> ZA,XIMM,XIMMdup 0101110011001111x1111111000xxxxx */
-{ "bsetl", 0x5ccf7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "bsetl", 0x5ccf7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* bsetl<.f> RA,LIMM,LIMMdup 0101111000001111x111111110xxxxxx */
-{ "bsetl", 0x5e0f7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bsetl", 0x5e0f7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bsetl<.f> ZA,LIMM,LIMMdup 0101111000001111x111111110111110 */
-{ "bsetl", 0x5e0f7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bsetl", 0x5e0f7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bsetl<.f><.cc> ZA,LIMM,LIMMdup 0101111011001111x1111111100xxxxx */
-{ "bsetl", 0x5ecf7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bsetl", 0x5ecf7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bset_s RB_S,RB_Sdup,UIMM5_11_S 10111xxx100xxxxx */
-{ "bset_s", 0x0000b880, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
+{ "bset_s", 0x0000b880, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
 
 /* btst RB,RC 00100xxx000100011xxxxxxxxxxxxxxx */
-{ "btst", 0x20118000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { 0 } }
+{ "btst", 0x20118000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* btst<.cc> RB,RC 00100xxx110100011xxxxxxxxx0xxxxx */
-{ "btst", 0x20d18000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_CC } }
+{ "btst", 0x20d18000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* btst RB,UIMM6_20 00100xxx010100011xxxxxxxxxxxxxxx */
-{ "btst", 0x20518000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "btst", 0x20518000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* btst<.cc> RB,UIMM6_20 00100xxx110100011xxxxxxxxx1xxxxx */
-{ "btst", 0x20d18020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "btst", 0x20d18020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* btst RB,SIMM12_20 00100xxx100100011xxxxxxxxxxxxxxx */
-{ "btst", 0x20918000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "btst", 0x20918000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* btst LIMM,RC 00100110000100011111xxxxxxxxxxxx */
-{ "btst", 0x2611f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, RC }, { 0 } }
+{ "btst", 0x2611f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { 0 } }
 
 /* btst RB,LIMM 00100xxx000100011xxx111110xxxxxx */
-{ "btst", 0x20118f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { 0 } }
+{ "btst", 0x20118f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { 0 } }
 
 /* btst<.cc> RB,LIMM 00100xxx110100011xxx1111100xxxxx */
-{ "btst", 0x20d18f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_CC } }
+{ "btst", 0x20d18f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_CC } }
 
 /* btst<.cc> LIMM,RC 00100110110100011111xxxxxx0xxxxx */
-{ "btst", 0x26d1f000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, RC }, { C_CC } }
+{ "btst", 0x26d1f000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { C_CC } }
 
 /* btst LIMM,UIMM6_20 00100110010100011111xxxxxxxxxxxx */
-{ "btst", 0x2651f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 } }
+{ "btst", 0x2651f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { 0 } }
 
 /* btst<.cc> LIMM,UIMM6_20 00100110110100011111xxxxxx1xxxxx */
-{ "btst", 0x26d1f020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC } }
+{ "btst", 0x26d1f020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { C_CC } }
 
 /* btst LIMM,SIMM12_20 00100110100100011111xxxxxxxxxxxx */
-{ "btst", 0x2691f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 } }
+{ "btst", 0x2691f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, SIMM12_20 }, { 0 } }
 
 /* btst LIMM,LIMMdup 00100110000100011111111110xxxxxx */
-{ "btst", 0x2611ff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 } }
+{ "btst", 0x2611ff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup }, { 0 } }
 
 /* btst<.cc> LIMM,LIMMdup 001001101101000111111111100xxxxx */
-{ "btst", 0x26d1ff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC } }
+{ "btst", 0x26d1ff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup }, { C_CC } }
 
 /* btstl RB,RC 01011xxx000100011xxxxxxxxxxxxxxx */
-{ "btstl", 0x58118000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 } }
+{ "btstl", 0x58118000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* btstl<.cc> RB,RC 01011xxx110100011xxxxxxxxx0xxxxx */
-{ "btstl", 0x58d18000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC } }
+{ "btstl", 0x58d18000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* btstl RB,UIMM6_20 01011xxx010100011xxxxxxxxxxxxxxx */
-{ "btstl", 0x58518000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "btstl", 0x58518000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* btstl<.cc> RB,UIMM6_20 01011xxx110100011xxxxxxxxx1xxxxx */
-{ "btstl", 0x58d18020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "btstl", 0x58d18020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* btstl RB,SIMM12_20 01011xxx100100011xxxxxxxxxxxxxxx */
-{ "btstl", 0x58918000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "btstl", 0x58918000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* btstl XIMM,RC 01011100000100011111xxxxxxxxxxxx */
-{ "btstl", 0x5c11f000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 } }
+{ "btstl", 0x5c11f000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { XIMM, RC }, { 0 } }
 
 /* btstl RB,XIMM 01011xxx000100011xxx111100xxxxxx */
-{ "btstl", 0x58118f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 } }
+{ "btstl", 0x58118f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { 0 } }
 
 /* btstl<.cc> RB,XIMM 01011xxx110100011xxx1111000xxxxx */
-{ "btstl", 0x58d18f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC } }
+{ "btstl", 0x58d18f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_CC } }
 
 /* btstl LIMM,RC 01011110000100011111xxxxxxxxxxxx */
-{ "btstl", 0x5e11f000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 } }
+{ "btstl", 0x5e11f000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { 0 } }
 
 /* btstl RB,LIMM 01011xxx000100011xxx111110xxxxxx */
-{ "btstl", 0x58118f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 } }
+{ "btstl", 0x58118f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { 0 } }
 
 /* btstl<.cc> RB,LIMM 01011xxx110100011xxx1111100xxxxx */
-{ "btstl", 0x58d18f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC } }
+{ "btstl", 0x58d18f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_CC } }
 
 /* btst_s RB_S,UIMM5_11_S 10111xxx111xxxxx */
-{ "btst_s", 0x0000b8e0, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, UIMM5_11_S }, { 0 } }
+{ "btst_s", 0x0000b8e0, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, UIMM5_11_S }, { 0 } }
 
 /* bxor<.f> RA,RB,RC 00100xxx00010010xxxxxxxxxxxxxxxx */
-{ "bxor", 0x20120000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "bxor", 0x20120000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bxor<.f> ZA,RB,RC 00100xxx00010010xxxxxxxxxx111110 */
-{ "bxor", 0x2012003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "bxor", 0x2012003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bxor<.f><.cc> RB,RBdup,RC 00100xxx11010010xxxxxxxxxx0xxxxx */
-{ "bxor", 0x20d20000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bxor", 0x20d20000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bxor<.f> RA,RB,UIMM6_20 00100xxx01010010xxxxxxxxxxxxxxxx */
-{ "bxor", 0x20520000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bxor", 0x20520000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bxor<.f> ZA,RB,UIMM6_20 00100xxx01010010xxxxxxxxxx111110 */
-{ "bxor", 0x2052003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bxor", 0x2052003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bxor<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11010010xxxxxxxxxx1xxxxx */
-{ "bxor", 0x20d20020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bxor", 0x20d20020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bxor<.f> RB,RBdup,SIMM12_20 00100xxx10010010xxxxxxxxxxxxxxxx */
-{ "bxor", 0x20920000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bxor", 0x20920000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bxor<.f> RA,LIMM,RC 0010011000010010x111xxxxxxxxxxxx */
-{ "bxor", 0x26127000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bxor", 0x26127000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bxor<.f> RA,RB,LIMM 00100xxx00010010xxxx111110xxxxxx */
-{ "bxor", 0x20120f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bxor", 0x20120f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bxor<.f> ZA,LIMM,RC 0010011000010010x111xxxxxx111110 */
-{ "bxor", 0x2612703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bxor", 0x2612703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bxor<.f> ZA,RB,LIMM 00100xxx00010010xxxx111110111110 */
-{ "bxor", 0x20120fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bxor", 0x20120fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bxor<.f><.cc> RB,RBdup,LIMM 00100xxx11010010xxxx1111100xxxxx */
-{ "bxor", 0x20d20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bxor", 0x20d20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bxor<.f><.cc> ZA,LIMM,RC 0010011011010010x111xxxxxx0xxxxx */
-{ "bxor", 0x26d27000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bxor", 0x26d27000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bxor<.f> RA,LIMM,UIMM6_20 0010011001010010x111xxxxxxxxxxxx */
-{ "bxor", 0x26527000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bxor", 0x26527000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bxor<.f> ZA,LIMM,UIMM6_20 0010011001010010x111xxxxxx111110 */
-{ "bxor", 0x2652703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bxor", 0x2652703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bxor<.f><.cc> ZA,LIMM,UIMM6_20 0010011011010010x111xxxxxx1xxxxx */
-{ "bxor", 0x26d27020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bxor", 0x26d27020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bxor<.f> ZA,LIMM,SIMM12_20 0010011010010010x111xxxxxxxxxxxx */
-{ "bxor", 0x26927000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bxor", 0x26927000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bxor<.f> RA,LIMM,LIMMdup 0010011000010010x111111110xxxxxx */
-{ "bxor", 0x26127f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bxor", 0x26127f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bxor<.f> ZA,LIMM,LIMMdup 0010011000010010x111111110111110 */
-{ "bxor", 0x26127fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bxor", 0x26127fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bxor<.f><.cc> ZA,LIMM,LIMMdup 0010011011010010x1111111100xxxxx */
-{ "bxor", 0x26d27f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bxor", 0x26d27f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* bxorl<.f> RA,RB,RC 01011xxx00010010xxxxxxxxxxxxxxxx */
-{ "bxorl", 0x58120000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "bxorl", 0x58120000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* bxorl<.f> ZA,RB,RC 01011xxx00010010xxxxxxxxxx111110 */
-{ "bxorl", 0x5812003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "bxorl", 0x5812003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* bxorl<.f><.cc> RB,RBdup,RC 01011xxx11010010xxxxxxxxxx0xxxxx */
-{ "bxorl", 0x58d20000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "bxorl", 0x58d20000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* bxorl<.f> RA,RB,UIMM6_20 01011xxx01010010xxxxxxxxxxxxxxxx */
-{ "bxorl", 0x58520000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "bxorl", 0x58520000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* bxorl<.f> ZA,RB,UIMM6_20 01011xxx01010010xxxxxxxxxx111110 */
-{ "bxorl", 0x5852003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "bxorl", 0x5852003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* bxorl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11010010xxxxxxxxxx1xxxxx */
-{ "bxorl", 0x58d20020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "bxorl", 0x58d20020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* bxorl<.f> RB,RBdup,SIMM12_20 01011xxx10010010xxxxxxxxxxxxxxxx */
-{ "bxorl", 0x58920000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "bxorl", 0x58920000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* bxorl<.f> RA,XIMM,RC 0101110000010010x111xxxxxxxxxxxx */
-{ "bxorl", 0x5c127000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "bxorl", 0x5c127000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* bxorl<.f> RA,RB,XIMM 01011xxx00010010xxxx111100xxxxxx */
-{ "bxorl", 0x58120f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "bxorl", 0x58120f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* bxorl<.f> ZA,XIMM,RC 0101110000010010x111xxxxxx111110 */
-{ "bxorl", 0x5c12703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "bxorl", 0x5c12703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* bxorl<.f> ZA,RB,XIMM 01011xxx00010010xxxx111100111110 */
-{ "bxorl", 0x58120f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "bxorl", 0x58120f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* bxorl<.f><.cc> ZA,XIMM,RC 0101110011010010x111xxxxxx0xxxxx */
-{ "bxorl", 0x5cd27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "bxorl", 0x5cd27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* bxorl<.f><.cc> RB,RBdup,XIMM 01011xxx11010010xxxx1111000xxxxx */
-{ "bxorl", 0x58d20f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "bxorl", 0x58d20f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* bxorl<.f> RA,XIMM,UIMM6_20 0101110001010010x111xxxxxxxxxxxx */
-{ "bxorl", 0x5c527000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "bxorl", 0x5c527000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bxorl<.f> ZA,XIMM,UIMM6_20 0101110001010010x111xxxxxx111110 */
-{ "bxorl", 0x5c52703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "bxorl", 0x5c52703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* bxorl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011010010x111xxxxxx1xxxxx */
-{ "bxorl", 0x5cd27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bxorl", 0x5cd27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bxorl<.f> RA,LIMM,RC 0101111000010010x111xxxxxxxxxxxx */
-{ "bxorl", 0x5e127000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "bxorl", 0x5e127000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* bxorl<.f> RA,RB,LIMM 01011xxx00010010xxxx111110xxxxxx */
-{ "bxorl", 0x58120f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "bxorl", 0x58120f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* bxorl<.f> ZA,LIMM,RC 0101111000010010x111xxxxxx111110 */
-{ "bxorl", 0x5e12703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "bxorl", 0x5e12703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* bxorl<.f> ZA,RB,LIMM 01011xxx00010010xxxx111110111110 */
-{ "bxorl", 0x58120fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "bxorl", 0x58120fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* bxorl<.f><.cc> ZA,LIMM,RC 0101111011010010x111xxxxxx0xxxxx */
-{ "bxorl", 0x5ed27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "bxorl", 0x5ed27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* bxorl<.f><.cc> RB,RBdup,LIMM 01011xxx11010010xxxx1111100xxxxx */
-{ "bxorl", 0x58d20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "bxorl", 0x58d20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* bxorl<.f> RA,LIMM,UIMM6_20 0101111001010010x111xxxxxxxxxxxx */
-{ "bxorl", 0x5e527000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "bxorl", 0x5e527000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bxorl<.f> ZA,LIMM,UIMM6_20 0101111001010010x111xxxxxx111110 */
-{ "bxorl", 0x5e52703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "bxorl", 0x5e52703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* bxorl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011010010x111xxxxxx1xxxxx */
-{ "bxorl", 0x5ed27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "bxorl", 0x5ed27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* bxorl<.f> ZA,XIMM,SIMM12_20 0101110010010010x111xxxxxxxxxxxx */
-{ "bxorl", 0x5c927000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "bxorl", 0x5c927000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* bxorl<.f> ZA,LIMM,SIMM12_20 0101111010010010x111xxxxxxxxxxxx */
-{ "bxorl", 0x5e927000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "bxorl", 0x5e927000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* bxorl<.f> RA,XIMM,XIMMdup 0101110000010010x111111100xxxxxx */
-{ "bxorl", 0x5c127f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "bxorl", 0x5c127f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* bxorl<.f> ZA,XIMM,XIMMdup 0101110000010010x111111100111110 */
-{ "bxorl", 0x5c127f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "bxorl", 0x5c127f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* bxorl<.f><.cc> ZA,XIMM,XIMMdup 0101110011010010x1111111000xxxxx */
-{ "bxorl", 0x5cd27f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "bxorl", 0x5cd27f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* bxorl<.f> RA,LIMM,LIMMdup 0101111000010010x111111110xxxxxx */
-{ "bxorl", 0x5e127f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "bxorl", 0x5e127f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* bxorl<.f> ZA,LIMM,LIMMdup 0101111000010010x111111110111110 */
-{ "bxorl", 0x5e127fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "bxorl", 0x5e127fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* bxorl<.f><.cc> ZA,LIMM,LIMMdup 0101111011010010x1111111100xxxxx */
-{ "bxorl", 0x5ed27f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "bxorl", 0x5ed27f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* b_s SIMM10_A16_7_S 1111000xxxxxxxxx */
-{ "b_s", 0x0000f000, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 } }
+{ "b_s", 0x0000f000, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, ARC_INSN_SUBCLASS_NONE, { SIMM10_A16_7_S }, { 0 } }
 
 /* clri RC 00100111001011110000xxxxxx111111 */
-{ "clri", 0x272f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { RC }, { 0 } }
+{ "clri", 0x272f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { RC }, { 0 } }
 
 /* clri UIMM6_20 00100111011011110000xxxxxx111111 */
-{ "clri", 0x276f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { UIMM6_20 }, { 0 } }
+{ "clri", 0x276f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* clri  00100111011011110000000000111111 */
-{ "clri", 0x276f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, {  }, { 0 } }
+{ "clri", 0x276f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* cmp RB,RC 00100xxx000011001xxxxxxxxxxxxxxx */
-{ "cmp", 0x200c8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { 0 } }
+{ "cmp", 0x200c8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* cmp<.cc> RB,RC 00100xxx110011001xxxxxxxxx0xxxxx */
-{ "cmp", 0x20cc8000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_CC } }
+{ "cmp", 0x20cc8000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* cmp RB,UIMM6_20 00100xxx010011001xxxxxxxxxxxxxxx */
-{ "cmp", 0x204c8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "cmp", 0x204c8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* cmp<.cc> RB,UIMM6_20 00100xxx110011001xxxxxxxxx1xxxxx */
-{ "cmp", 0x20cc8020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "cmp", 0x20cc8020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* cmp RB,SIMM12_20 00100xxx100011001xxxxxxxxxxxxxxx */
-{ "cmp", 0x208c8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "cmp", 0x208c8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* cmp LIMM,RC 00100110000011001111xxxxxxxxxxxx */
-{ "cmp", 0x260cf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, RC }, { 0 } }
+{ "cmp", 0x260cf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { 0 } }
 
 /* cmp RB,LIMM 00100xxx000011001xxx111110xxxxxx */
-{ "cmp", 0x200c8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { 0 } }
+{ "cmp", 0x200c8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { 0 } }
 
 /* cmp<.cc> RB,LIMM 00100xxx110011001xxx1111100xxxxx */
-{ "cmp", 0x20cc8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_CC } }
+{ "cmp", 0x20cc8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_CC } }
 
 /* cmp<.cc> LIMM,RC 00100110110011001111xxxxxx0xxxxx */
-{ "cmp", 0x26ccf000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, RC }, { C_CC } }
+{ "cmp", 0x26ccf000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { C_CC } }
 
 /* cmp LIMM,UIMM6_20 00100110010011001111xxxxxxxxxxxx */
-{ "cmp", 0x264cf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 } }
+{ "cmp", 0x264cf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { 0 } }
 
 /* cmp<.cc> LIMM,UIMM6_20 00100110110011001111xxxxxx1xxxxx */
-{ "cmp", 0x26ccf020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC } }
+{ "cmp", 0x26ccf020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { C_CC } }
 
 /* cmp LIMM,SIMM12_20 00100110100011001111xxxxxxxxxxxx */
-{ "cmp", 0x268cf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 } }
+{ "cmp", 0x268cf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, SIMM12_20 }, { 0 } }
 
 /* cmp LIMM,LIMMdup 00100110000011001111111110xxxxxx */
-{ "cmp", 0x260cff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, LIMMdup }, { 0 } }
+{ "cmp", 0x260cff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup }, { 0 } }
 
 /* cmp<.cc> LIMM,LIMMdup 001001101100110011111111100xxxxx */
-{ "cmp", 0x26ccff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, LIMMdup }, { C_CC } }
+{ "cmp", 0x26ccff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup }, { C_CC } }
 
 /* cmpl RB,RC 01011xxx000011001xxxxxxxxxxxxxxx */
-{ "cmpl", 0x580c8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 } }
+{ "cmpl", 0x580c8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* cmpl<.cc> RB,RC 01011xxx110011001xxxxxxxxx0xxxxx */
-{ "cmpl", 0x58cc8000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC } }
+{ "cmpl", 0x58cc8000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* cmpl RB,UIMM6_20 01011xxx010011001xxxxxxxxxxxxxxx */
-{ "cmpl", 0x584c8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "cmpl", 0x584c8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* cmpl<.cc> RB,UIMM6_20 01011xxx110011001xxxxxxxxx1xxxxx */
-{ "cmpl", 0x58cc8020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "cmpl", 0x58cc8020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* cmpl RB,SIMM12_20 01011xxx100011001xxxxxxxxxxxxxxx */
-{ "cmpl", 0x588c8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "cmpl", 0x588c8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* cmpl XIMM,RC 01011100000011001111xxxxxxxxxxxx */
-{ "cmpl", 0x5c0cf000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 } }
+{ "cmpl", 0x5c0cf000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { XIMM, RC }, { 0 } }
 
 /* cmpl RB,XIMM 01011xxx000011001xxx111100xxxxxx */
-{ "cmpl", 0x580c8f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 } }
+{ "cmpl", 0x580c8f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { 0 } }
 
 /* cmpl<.cc> RB,XIMM 01011xxx110011001xxx1111000xxxxx */
-{ "cmpl", 0x58cc8f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC } }
+{ "cmpl", 0x58cc8f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_CC } }
 
 /* cmpl LIMM,RC 01011110000011001111xxxxxxxxxxxx */
-{ "cmpl", 0x5e0cf000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 } }
+{ "cmpl", 0x5e0cf000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { 0 } }
 
 /* cmpl RB,LIMM 01011xxx000011001xxx111110xxxxxx */
-{ "cmpl", 0x580c8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 } }
+{ "cmpl", 0x580c8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { 0 } }
 
 /* cmpl<.cc> RB,LIMM 01011xxx110011001xxx1111100xxxxx */
-{ "cmpl", 0x58cc8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC } }
+{ "cmpl", 0x58cc8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_CC } }
 
 /* cmp_s RB_S,RH_S 01110xxxxxx100xx */
-{ "cmp_s", 0x00007010, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RH_S }, { 0 } }
+{ "cmp_s", 0x00007010, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RH_S }, { 0 } }
 
 /* cmp_s RH_S,SIMM3_5_S 01110xxxxxx101xx */
-{ "cmp_s", 0x00007014, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RH_S, SIMM3_5_S }, { 0 } }
+{ "cmp_s", 0x00007014, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, SIMM3_5_S }, { 0 } }
 
 /* cmp_s RB_S,LIMM_S 01110xxx11010011 */
-{ "cmp_s", 0x000070d3, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, LIMM_S }, { 0 } }
+{ "cmp_s", 0x000070d3, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, LIMM_S }, { 0 } }
 
 /* cmp_s LIMM_S,SIMM3_5_S 01110xxx11010111 */
-{ "cmp_s", 0x000070d7, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM_S, SIMM3_5_S }, { 0 } }
+{ "cmp_s", 0x000070d7, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM_S, SIMM3_5_S }, { 0 } }
 
 /* dbnz RB,SIMM13_A16_20 00100xxx1000110x0xxxxxxxxxxxxxxx */
-{ "dbnz", 0x208c0000, 0xf8fe8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, NONE, { RB, SIMM13_A16_20 }, { C_DNZ_D } }
+{ "dbnz", 0x208c0000, 0xf8fe8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, BRANCH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM13_A16_20 }, { C_DNZ_D } }
 
 /* div<.f> RA_CHK,RB,RC 00101xxx00000100xxxxxxxxxxxxxxxx */
 { "div", 0x28040000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F } }
@@ -3281,103 +3281,103 @@
 { "div", 0x2ec47f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* divl<.f> RA,RB,RC 01011xxx00100100xxxxxxxxxxxxxxxx */
-{ "divl", 0x58240000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "divl", 0x58240000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* divl<.f> ZA,RB,RC 01011xxx00100100xxxxxxxxxx111110 */
-{ "divl", 0x5824003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "divl", 0x5824003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* divl<.f><.cc> RB,RBdup,RC 01011xxx11100100xxxxxxxxxx0xxxxx */
-{ "divl", 0x58e40000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "divl", 0x58e40000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* divl<.f> RA,RB,UIMM6_20 01011xxx01100100xxxxxxxxxxxxxxxx */
-{ "divl", 0x58640000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "divl", 0x58640000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* divl<.f> ZA,RB,UIMM6_20 01011xxx01100100xxxxxxxxxx111110 */
-{ "divl", 0x5864003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "divl", 0x5864003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* divl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11100100xxxxxxxxxx1xxxxx */
-{ "divl", 0x58e40020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "divl", 0x58e40020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* divl<.f> RB,RBdup,SIMM12_20 01011xxx10100100xxxxxxxxxxxxxxxx */
-{ "divl", 0x58a40000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "divl", 0x58a40000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* divl<.f> RA,XIMM,RC 0101110000100100x111xxxxxxxxxxxx */
-{ "divl", 0x5c247000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "divl", 0x5c247000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* divl<.f> RA,RB,XIMM 01011xxx00100100xxxx111100xxxxxx */
-{ "divl", 0x58240f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "divl", 0x58240f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* divl<.f> ZA,XIMM,RC 0101110000100100x111xxxxxx111110 */
-{ "divl", 0x5c24703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "divl", 0x5c24703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* divl<.f> ZA,RB,XIMM 01011xxx00100100xxxx111100111110 */
-{ "divl", 0x58240f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "divl", 0x58240f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* divl<.f><.cc> ZA,XIMM,RC 0101110011100100x111xxxxxx0xxxxx */
-{ "divl", 0x5ce47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "divl", 0x5ce47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* divl<.f><.cc> RB,RBdup,XIMM 01011xxx11100100xxxx1111000xxxxx */
-{ "divl", 0x58e40f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "divl", 0x58e40f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* divl<.f> RA,XIMM,UIMM6_20 0101110001100100x111xxxxxxxxxxxx */
-{ "divl", 0x5c647000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "divl", 0x5c647000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* divl<.f> ZA,XIMM,UIMM6_20 0101110001100100x111xxxxxx111110 */
-{ "divl", 0x5c64703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "divl", 0x5c64703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* divl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011100100x111xxxxxx1xxxxx */
-{ "divl", 0x5ce47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "divl", 0x5ce47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* divl<.f> RA,LIMM,RC 0101111000100100x111xxxxxxxxxxxx */
-{ "divl", 0x5e247000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "divl", 0x5e247000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* divl<.f> RA,RB,LIMM 01011xxx00100100xxxx111110xxxxxx */
-{ "divl", 0x58240f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "divl", 0x58240f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* divl<.f> ZA,LIMM,RC 0101111000100100x111xxxxxx111110 */
-{ "divl", 0x5e24703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "divl", 0x5e24703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* divl<.f> ZA,RB,LIMM 01011xxx00100100xxxx111110111110 */
-{ "divl", 0x58240fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "divl", 0x58240fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* divl<.f><.cc> ZA,LIMM,RC 0101111011100100x111xxxxxx0xxxxx */
-{ "divl", 0x5ee47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "divl", 0x5ee47000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* divl<.f><.cc> RB,RBdup,LIMM 01011xxx11100100xxxx1111100xxxxx */
-{ "divl", 0x58e40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "divl", 0x58e40f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* divl<.f> RA,LIMM,UIMM6_20 0101111001100100x111xxxxxxxxxxxx */
-{ "divl", 0x5e647000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "divl", 0x5e647000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* divl<.f> ZA,LIMM,UIMM6_20 0101111001100100x111xxxxxx111110 */
-{ "divl", 0x5e64703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "divl", 0x5e64703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* divl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011100100x111xxxxxx1xxxxx */
-{ "divl", 0x5ee47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "divl", 0x5ee47020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* divl<.f> ZA,XIMM,SIMM12_20 0101110010100100x111xxxxxxxxxxxx */
-{ "divl", 0x5ca47000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "divl", 0x5ca47000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* divl<.f> ZA,LIMM,SIMM12_20 0101111010100100x111xxxxxxxxxxxx */
-{ "divl", 0x5ea47000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "divl", 0x5ea47000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* divl<.f> RA,XIMM,XIMMdup 0101110000100100x111111100xxxxxx */
-{ "divl", 0x5c247f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "divl", 0x5c247f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* divl<.f> ZA,XIMM,XIMMdup 0101110000100100x111111100111110 */
-{ "divl", 0x5c247f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "divl", 0x5c247f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* divl<.f><.cc> ZA,XIMM,XIMMdup 0101110011100100x1111111000xxxxx */
-{ "divl", 0x5ce47f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "divl", 0x5ce47f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* divl<.f> RA,LIMM,LIMMdup 0101111000100100x111111110xxxxxx */
-{ "divl", 0x5e247f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "divl", 0x5e247f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* divl<.f> ZA,LIMM,LIMMdup 0101111000100100x111111110111110 */
-{ "divl", 0x5e247fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "divl", 0x5e247fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* divl<.f><.cc> ZA,LIMM,LIMMdup 0101111011100100x1111111100xxxxx */
-{ "divl", 0x5ee47f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "divl", 0x5ee47f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* divu<.f> RA_CHK,RB,RC 00101xxx00000101xxxxxxxxxxxxxxxx */
 { "divu", 0x28050000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F } }
@@ -3440,103 +3440,103 @@
 { "divu", 0x2ec57f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* divul<.f> RA,RB,RC 01011xxx00100101xxxxxxxxxxxxxxxx */
-{ "divul", 0x58250000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "divul", 0x58250000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* divul<.f> ZA,RB,RC 01011xxx00100101xxxxxxxxxx111110 */
-{ "divul", 0x5825003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "divul", 0x5825003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* divul<.f><.cc> RB,RBdup,RC 01011xxx11100101xxxxxxxxxx0xxxxx */
-{ "divul", 0x58e50000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "divul", 0x58e50000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* divul<.f> RA,RB,UIMM6_20 01011xxx01100101xxxxxxxxxxxxxxxx */
-{ "divul", 0x58650000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "divul", 0x58650000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* divul<.f> ZA,RB,UIMM6_20 01011xxx01100101xxxxxxxxxx111110 */
-{ "divul", 0x5865003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "divul", 0x5865003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* divul<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11100101xxxxxxxxxx1xxxxx */
-{ "divul", 0x58e50020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "divul", 0x58e50020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* divul<.f> RB,RBdup,SIMM12_20 01011xxx10100101xxxxxxxxxxxxxxxx */
-{ "divul", 0x58a50000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "divul", 0x58a50000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* divul<.f> RA,XIMM,RC 0101110000100101x111xxxxxxxxxxxx */
-{ "divul", 0x5c257000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "divul", 0x5c257000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* divul<.f> RA,RB,XIMM 01011xxx00100101xxxx111100xxxxxx */
-{ "divul", 0x58250f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "divul", 0x58250f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* divul<.f> ZA,XIMM,RC 0101110000100101x111xxxxxx111110 */
-{ "divul", 0x5c25703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "divul", 0x5c25703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* divul<.f> ZA,RB,XIMM 01011xxx00100101xxxx111100111110 */
-{ "divul", 0x58250f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "divul", 0x58250f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* divul<.f><.cc> ZA,XIMM,RC 0101110011100101x111xxxxxx0xxxxx */
-{ "divul", 0x5ce57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "divul", 0x5ce57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* divul<.f><.cc> RB,RBdup,XIMM 01011xxx11100101xxxx1111000xxxxx */
-{ "divul", 0x58e50f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "divul", 0x58e50f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* divul<.f> RA,XIMM,UIMM6_20 0101110001100101x111xxxxxxxxxxxx */
-{ "divul", 0x5c657000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "divul", 0x5c657000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* divul<.f> ZA,XIMM,UIMM6_20 0101110001100101x111xxxxxx111110 */
-{ "divul", 0x5c65703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "divul", 0x5c65703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* divul<.f><.cc> ZA,XIMM,UIMM6_20 0101110011100101x111xxxxxx1xxxxx */
-{ "divul", 0x5ce57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "divul", 0x5ce57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* divul<.f> RA,LIMM,RC 0101111000100101x111xxxxxxxxxxxx */
-{ "divul", 0x5e257000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "divul", 0x5e257000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* divul<.f> RA,RB,LIMM 01011xxx00100101xxxx111110xxxxxx */
-{ "divul", 0x58250f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "divul", 0x58250f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* divul<.f> ZA,LIMM,RC 0101111000100101x111xxxxxx111110 */
-{ "divul", 0x5e25703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "divul", 0x5e25703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* divul<.f> ZA,RB,LIMM 01011xxx00100101xxxx111110111110 */
-{ "divul", 0x58250fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "divul", 0x58250fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* divul<.f><.cc> ZA,LIMM,RC 0101111011100101x111xxxxxx0xxxxx */
-{ "divul", 0x5ee57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "divul", 0x5ee57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* divul<.f><.cc> RB,RBdup,LIMM 01011xxx11100101xxxx1111100xxxxx */
-{ "divul", 0x58e50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "divul", 0x58e50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* divul<.f> RA,LIMM,UIMM6_20 0101111001100101x111xxxxxxxxxxxx */
-{ "divul", 0x5e657000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "divul", 0x5e657000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* divul<.f> ZA,LIMM,UIMM6_20 0101111001100101x111xxxxxx111110 */
-{ "divul", 0x5e65703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "divul", 0x5e65703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* divul<.f><.cc> ZA,LIMM,UIMM6_20 0101111011100101x111xxxxxx1xxxxx */
-{ "divul", 0x5ee57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "divul", 0x5ee57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* divul<.f> ZA,XIMM,SIMM12_20 0101110010100101x111xxxxxxxxxxxx */
-{ "divul", 0x5ca57000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "divul", 0x5ca57000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* divul<.f> ZA,LIMM,SIMM12_20 0101111010100101x111xxxxxxxxxxxx */
-{ "divul", 0x5ea57000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "divul", 0x5ea57000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* divul<.f> RA,XIMM,XIMMdup 0101110000100101x111111100xxxxxx */
-{ "divul", 0x5c257f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "divul", 0x5c257f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* divul<.f> ZA,XIMM,XIMMdup 0101110000100101x111111100111110 */
-{ "divul", 0x5c257f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "divul", 0x5c257f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* divul<.f><.cc> ZA,XIMM,XIMMdup 0101110011100101x1111111000xxxxx */
-{ "divul", 0x5ce57f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "divul", 0x5ce57f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* divul<.f> RA,LIMM,LIMMdup 0101111000100101x111111110xxxxxx */
-{ "divul", 0x5e257f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "divul", 0x5e257f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* divul<.f> ZA,LIMM,LIMMdup 0101111000100101x111111110111110 */
-{ "divul", 0x5e257fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "divul", 0x5e257fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* divul<.f><.cc> ZA,LIMM,LIMMdup 0101111011100101x1111111100xxxxx */
-{ "divul", 0x5ee57f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "divul", 0x5ee57f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* dmach<.f> RA_CHK,RB,RC 00101xxx00010010xxxxxxxxxxxxxxxx */
 { "dmach", 0x28120000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F } }
@@ -3779,10 +3779,10 @@
 { "dmacwhu", 0x2ef77f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* dmb  00100011011011110001xxx000111111 */
-{ "dmb", 0x236f103f, 0xfffff1ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, {  }, { 0 } }
+{ "dmb", 0x236f103f, 0xfffff1ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* dmb UIMM3_23 00100011011011110001xxxxxx111111 */
-{ "dmb", 0x236f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { UIMM3_23 }, { 0 } }
+{ "dmb", 0x236f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { UIMM3_23 }, { 0 } }
 
 /* dmpyh<.f> RA_CHK,RB,RC 00101xxx00010000xxxxxxxxxxxxxxxx */
 { "dmpyh", 0x28100000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F } }
@@ -4025,181 +4025,181 @@
 { "dmpywhu", 0x2ef37f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* dsync  00100010011011110001xxxxxx111111 */
-{ "dsync", 0x226f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, {  }, { 0 } }
+{ "dsync", 0x226f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* ex<.di> RB,BRAKET,RC,BRAKETdup 00100xxx00101111xxxxxxxxxx001100 */
-{ "ex", 0x202f000c, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 } }
+{ "ex", 0x202f000c, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 } }
 
 /* ex<.di> RB,BRAKET,UIMM6_20,BRAKETdup 00100xxx01101111xxxxxxxxxx001100 */
-{ "ex", 0x206f000c, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
+{ "ex", 0x206f000c, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
 
 /* ex<.di> RB,BRAKET,LIMM,BRAKETdup 00100xxx00101111xxxx111110001100 */
-{ "ex", 0x202f0f8c, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 } }
+{ "ex", 0x202f0f8c, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 } }
 
 /* ex<.di> LIMM,BRAKET,RC,BRAKETdup 0010011000101111x111xxxxxx001100 */
-{ "ex", 0x262f700c, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 } }
+{ "ex", 0x262f700c, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 } }
 
 /* ex<.di> LIMM,BRAKET,UIMM6_20,BRAKETdup 0010011001101111x111xxxxxx001100 */
-{ "ex", 0x266f700c, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
+{ "ex", 0x266f700c, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
 
 /* ex<.di> LIMM,BRAKET,LIMMdup,BRAKETdup 0010011000101111x111111110001100 */
-{ "ex", 0x262f7f8c, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 } }
+{ "ex", 0x262f7f8c, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 } }
 
 /* exl<.aq> RB,BRAKET,RC,BRAKETdup 01011xxx00101111xxxxxxxxxx001100 */
-{ "exl", 0x582f000c, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ, C_RL } }
+{ "exl", 0x582f000c, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ, C_RL } }
 
 /* extb<.f> RB,RC 00100xxx00101111xxxxxxxxxx000111 */
-{ "extb", 0x202f0007, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "extb", 0x202f0007, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* extb<.f> ZA,RC 0010011000101111x111xxxxxx000111 */
-{ "extb", 0x262f7007, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "extb", 0x262f7007, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* extb<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx000111 */
-{ "extb", 0x206f0007, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "extb", 0x206f0007, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* extb<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx000111 */
-{ "extb", 0x266f7007, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "extb", 0x266f7007, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* extb<.f> RB,LIMM 00100xxx00101111xxxx111110000111 */
-{ "extb", 0x202f0f87, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "extb", 0x202f0f87, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* extb<.f> ZA,LIMM 0010011000101111x111111110000111 */
-{ "extb", 0x262f7f87, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "extb", 0x262f7f87, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* extb_s RB_S,RC_S 01111xxxxxx01111 */
-{ "extb_s", 0x0000780f, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RC_S }, { 0 } }
+{ "extb_s", 0x0000780f, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* exth<.f> RB,RC 00100xxx00101111xxxxxxxxxx001000 */
-{ "exth", 0x202f0008, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "exth", 0x202f0008, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* exth<.f> ZA,RC 0010011000101111x111xxxxxx001000 */
-{ "exth", 0x262f7008, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "exth", 0x262f7008, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* exth<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx001000 */
-{ "exth", 0x206f0008, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "exth", 0x206f0008, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* exth<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx001000 */
-{ "exth", 0x266f7008, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "exth", 0x266f7008, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* exth<.f> RB,LIMM 00100xxx00101111xxxx111110001000 */
-{ "exth", 0x202f0f88, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "exth", 0x202f0f88, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* exth<.f> ZA,LIMM 0010011000101111x111111110001000 */
-{ "exth", 0x262f7f88, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "exth", 0x262f7f88, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* exth_s RB_S,RC_S 01111xxxxxx10000 */
-{ "exth_s", 0x00007810, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RC_S }, { 0 } }
+{ "exth_s", 0x00007810, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* ffs<.f> RB,RC 00101xxx00101111xxxxxxxxxx010010 */
-{ "ffs", 0x282f0012, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "ffs", 0x282f0012, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* ffs<.f> ZA,RC 0010111000101111x111xxxxxx010010 */
-{ "ffs", 0x2e2f7012, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "ffs", 0x2e2f7012, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* ffs<.f> RB,UIMM6_20 00101xxx01101111xxxxxxxxxx010010 */
-{ "ffs", 0x286f0012, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "ffs", 0x286f0012, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* ffs<.f> ZA,UIMM6_20 0010111001101111x111xxxxxx010010 */
-{ "ffs", 0x2e6f7012, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "ffs", 0x2e6f7012, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* ffs<.f> RB,LIMM 00101xxx00101111xxxx111110010010 */
-{ "ffs", 0x282f0f92, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "ffs", 0x282f0f92, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* ffs<.f> ZA,LIMM 0010111000101111x111111110010010 */
-{ "ffs", 0x2e2f7f92, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "ffs", 0x2e2f7f92, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* ffsl<.f> RB,RC 01011xxx00101111xxxxxxxxxx010010 */
-{ "ffsl", 0x582f0012, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "ffsl", 0x582f0012, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* ffsl<.f> ZA,RC 0101111000101111x111xxxxxx010010 */
-{ "ffsl", 0x5e2f7012, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "ffsl", 0x5e2f7012, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* ffsl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx010010 */
-{ "ffsl", 0x586f0012, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "ffsl", 0x586f0012, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* ffsl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx010010 */
-{ "ffsl", 0x5e6f7012, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "ffsl", 0x5e6f7012, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* ffsl<.f> RB,XIMM 01011xxx00101111xxxx111100010010 */
-{ "ffsl", 0x582f0f12, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "ffsl", 0x582f0f12, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* ffsl<.f> ZA,XIMM 0101111000101111x111111100010010 */
-{ "ffsl", 0x5e2f7f12, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "ffsl", 0x5e2f7f12, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* ffsl<.f> RB,LIMM 01011xxx00101111xxxx111110010010 */
-{ "ffsl", 0x582f0f92, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "ffsl", 0x582f0f92, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* ffsl<.f> ZA,LIMM 0101111000101111x111111110010010 */
-{ "ffsl", 0x5e2f7f92, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "ffsl", 0x5e2f7f92, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* flag RC 00100xxx001010010xxxxxxxxxxxxxxx */
-{ "flag", 0x20290000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { RC }, { 0 } }
+{ "flag", 0x20290000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { RC }, { 0 } }
 
 /* flag<.cc> RC 00100xxx111010010xxxxxxxxx0xxxxx */
-{ "flag", 0x20e90000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { RC }, { C_CC } }
+{ "flag", 0x20e90000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { RC }, { C_CC } }
 
 /* flag UIMM6_20 00100xxx011010010xxxxxxxxxxxxxxx */
-{ "flag", 0x20690000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { UIMM6_20 }, { 0 } }
+{ "flag", 0x20690000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* flag<.cc> UIMM6_20 00100xxx111010010xxxxxxxxx1xxxxx */
-{ "flag", 0x20e90020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { UIMM6_20 }, { C_CC } }
+{ "flag", 0x20e90020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { C_CC } }
 
 /* flag SIMM12_20 00100xxx101010010xxxxxxxxxxxxxxx */
-{ "flag", 0x20a90000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { SIMM12_20 }, { 0 } }
+{ "flag", 0x20a90000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { SIMM12_20 }, { 0 } }
 
 /* flag LIMM 00100xxx001010010xxx111110xxxxxx */
-{ "flag", 0x20290f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { LIMM }, { 0 } }
+{ "flag", 0x20290f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { LIMM }, { 0 } }
 
 /* flag<.cc> LIMM 00100xxx111010010xxx1111100xxxxx */
-{ "flag", 0x20e90f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { LIMM }, { C_CC } }
+{ "flag", 0x20e90f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { LIMM }, { C_CC } }
 
 /* fls<.f> RB,RC 00101xxx00101111xxxxxxxxxx010011 */
-{ "fls", 0x282f0013, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "fls", 0x282f0013, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* fls<.f> ZA,RC 0010111000101111x111xxxxxx010011 */
-{ "fls", 0x2e2f7013, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "fls", 0x2e2f7013, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* fls<.f> RB,UIMM6_20 00101xxx01101111xxxxxxxxxx010011 */
-{ "fls", 0x286f0013, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "fls", 0x286f0013, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* fls<.f> ZA,UIMM6_20 0010111001101111x111xxxxxx010011 */
-{ "fls", 0x2e6f7013, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "fls", 0x2e6f7013, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* fls<.f> RB,LIMM 00101xxx00101111xxxx111110010011 */
-{ "fls", 0x282f0f93, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "fls", 0x282f0f93, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* fls<.f> ZA,LIMM 0010111000101111x111111110010011 */
-{ "fls", 0x2e2f7f93, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "fls", 0x2e2f7f93, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* flsl<.f> RB,RC 01011xxx00101111xxxxxxxxxx010011 */
-{ "flsl", 0x582f0013, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "flsl", 0x582f0013, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* flsl<.f> ZA,RC 0101111000101111x111xxxxxx010011 */
-{ "flsl", 0x5e2f7013, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "flsl", 0x5e2f7013, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* flsl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx010011 */
-{ "flsl", 0x586f0013, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "flsl", 0x586f0013, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* flsl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx010011 */
-{ "flsl", 0x5e6f7013, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "flsl", 0x5e6f7013, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* flsl<.f> RB,XIMM 01011xxx00101111xxxx111100010011 */
-{ "flsl", 0x582f0f13, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "flsl", 0x582f0f13, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* flsl<.f> ZA,XIMM 0101111000101111x111111100010011 */
-{ "flsl", 0x5e2f7f13, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "flsl", 0x5e2f7f13, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* flsl<.f> RB,LIMM 01011xxx00101111xxxx111110010011 */
-{ "flsl", 0x582f0f93, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "flsl", 0x582f0f93, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* flsl<.f> ZA,LIMM 0101111000101111x111111110010011 */
-{ "flsl", 0x5e2f7f93, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "flsl", 0x5e2f7f93, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* j BRAKET,RC,BRAKETdup 00100xxx00100000xxxxxxxxxxxxxxxx */
-{ "j", 0x20200000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 } }
+{ "j", 0x20200000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* j BRAKET,BLINK,BRAKETdup 00100xxx00100000xxxx011111xxxxxx */
-{ "j", 0x202007c0, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { 0 } }
+{ "j", 0x202007c0, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, BLINK, BRAKETdup }, { 0 } }
 
 /* j<.cc> BRAKET,RC,BRAKETdup 00100xxx11100000xxxxxxxxxx0xxxxx */
 { "j", 0x20e00000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { BRAKET, RC, BRAKETdup }, { C_CC } }
@@ -4208,10 +4208,10 @@
 { "j", 0x20e007c0, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { BRAKET, BLINK, BRAKETdup }, { C_CC } }
 
 /* j BRAKET,RC,BRAKETdup 00100xxx00100001xxxxxxxxxxxxxxxx */
-{ "j", 0x20210000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD } }
+{ "j", 0x20210000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD } }
 
 /* j BRAKET,BLINK,BRAKETdup 00100xxx00100001xxxx011111xxxxxx */
-{ "j", 0x202107c0, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_DHARD } }
+{ "j", 0x202107c0, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, BLINK, BRAKETdup }, { C_DHARD } }
 
 /* j<.cc> BRAKET,RC,BRAKETdup 00100xxx11100001xxxxxxxxxx0xxxxx */
 { "j", 0x20e10000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD } }
@@ -4220,25 +4220,25 @@
 { "j", 0x20e107c0, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { BRAKET, BLINK, BRAKETdup }, { C_CC, C_DHARD } }
 
 /* j SIMM12_20 00100xxx10100000xxxxxxxxxxxxxxxx */
-{ "j", 0x20a00000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { SIMM12_20 }, { 0 } }
+{ "j", 0x20a00000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { SIMM12_20 }, { 0 } }
 
 /* j SIMM12_20 00100xxx10100001xxxxxxxxxxxxxxxx */
-{ "j", 0x20a10000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { SIMM12_20 }, { C_DHARD } }
+{ "j", 0x20a10000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { SIMM12_20 }, { C_DHARD } }
 
 /* j UIMM6_20 00100xxx01100000xxxxxxxxxxxxxxxx */
-{ "j", 0x20600000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { UIMM6_20 }, { 0 } }
+{ "j", 0x20600000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* j<.cc> UIMM6_20 00100xxx11100000xxxxxxxxxx1xxxxx */
 { "j", 0x20e00020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { UIMM6_20 }, { C_CC } }
 
 /* j UIMM6_20 00100xxx01100001xxxxxxxxxxxxxxxx */
-{ "j", 0x20610000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { UIMM6_20 }, { C_DHARD } }
+{ "j", 0x20610000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { C_DHARD } }
 
 /* j<.cc> UIMM6_20 00100xxx11100001xxxxxxxxxx1xxxxx */
 { "j", 0x20e10020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { UIMM6_20 }, { C_CC, C_DHARD } }
 
 /* j LIMM 00100xxx00100000xxxx111110xxxxxx */
-{ "j", 0x20200f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { LIMM }, { 0 } }
+{ "j", 0x20200f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { LIMM }, { 0 } }
 
 /* j<.cc> LIMM 00100xxx11100000xxxx1111100xxxxx */
 { "j", 0x20e00f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { LIMM }, { C_CC } }
@@ -4247,520 +4247,520 @@
 { "jeq_s", 0x00007ce0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_EQ } }
 
 /* jl BRAKET,RC,BRAKETdup 00100xxx00100010xxxxxxxxxxxxxxxx */
-{ "jl", 0x20220000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 } }
+{ "jl", 0x20220000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* jl<.cc> BRAKET,RC,BRAKETdup 00100xxx11100010xxxxxxxxxx0xxxxx */
-{ "jl", 0x20e20000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC } }
+{ "jl", 0x20e20000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RC, BRAKETdup }, { C_CC } }
 
 /* jl BRAKET,RC,BRAKETdup 00100xxx00100011xxxxxxxxxxxxxxxx */
-{ "jl", 0x20230000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD } }
+{ "jl", 0x20230000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD } }
 
 /* jl<.cc> BRAKET,RC,BRAKETdup 00100xxx11100011xxxxxxxxxx0xxxxx */
-{ "jl", 0x20e30000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD } }
+{ "jl", 0x20e30000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD } }
 
 /* jl SIMM12_20 00100xxx10100010xxxxxxxxxxxxxxxx */
-{ "jl", 0x20a20000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { SIMM12_20 }, { 0 } }
+{ "jl", 0x20a20000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { SIMM12_20 }, { 0 } }
 
 /* jl SIMM12_20 00100xxx10100011xxxxxxxxxxxxxxxx */
-{ "jl", 0x20a30000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { SIMM12_20 }, { C_DHARD } }
+{ "jl", 0x20a30000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { SIMM12_20 }, { C_DHARD } }
 
 /* jl UIMM6_20 00100xxx01100010xxxxxxxxxxxxxxxx */
-{ "jl", 0x20620000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { UIMM6_20 }, { 0 } }
+{ "jl", 0x20620000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* jl<.cc> UIMM6_20 00100xxx11100010xxxxxxxxxx1xxxxx */
-{ "jl", 0x20e20020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { UIMM6_20 }, { C_CC } }
+{ "jl", 0x20e20020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { C_CC } }
 
 /* jl UIMM6_20 00100xxx01100011xxxxxxxxxxxxxxxx */
-{ "jl", 0x20630000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { UIMM6_20 }, { C_DHARD } }
+{ "jl", 0x20630000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { C_DHARD } }
 
 /* jl<.cc> UIMM6_20 00100xxx11100011xxxxxxxxxx1xxxxx */
-{ "jl", 0x20e30020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD } }
+{ "jl", 0x20e30020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { C_CC, C_DHARD } }
 
 /* jl LIMM 00100xxx00100010xxxx111110xxxxxx */
-{ "jl", 0x20220f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { LIMM }, { 0 } }
+{ "jl", 0x20220f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { LIMM }, { 0 } }
 
 /* jl<.cc> LIMM 00100xxx11100010xxxx1111100xxxxx */
-{ "jl", 0x20e20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { LIMM }, { C_CC } }
+{ "jl", 0x20e20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { LIMM }, { C_CC } }
 
 /* jli_s UIMM10_13_S 01010xxxxxxx1xxx */
-{ "jli_s", 0x00005008, 0x0000f808, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JLI, NONE, { UIMM10_13_S }, { 0 } }
+{ "jli_s", 0x00005008, 0x0000f808, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JLI, ARC_INSN_SUBCLASS_NONE, { UIMM10_13_S }, { 0 } }
 
 /* jl_s BRAKET,RB_S,BRAKETdup 01111xxx01000000 */
-{ "jl_s", 0x00007840, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 } }
+{ "jl_s", 0x00007840, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB_S, BRAKETdup }, { 0 } }
 
 /* jl_s BRAKET,RB_S,BRAKETdup 01111xxx01100000 */
-{ "jl_s", 0x00007860, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD } }
+{ "jl_s", 0x00007860, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD } }
 
 /* jne_s BRAKET,BLINK_S,BRAKETdup 0111110111100000 */
 { "jne_s", 0x00007de0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_NE } }
 
 /* j_s BRAKET,RB_S,BRAKETdup 01111xxx00000000 */
-{ "j_s", 0x00007800, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 } }
+{ "j_s", 0x00007800, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB_S, BRAKETdup }, { 0 } }
 
 /* j_s BRAKET,RB_S,BRAKETdup 01111xxx00100000 */
-{ "j_s", 0x00007820, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD } }
+{ "j_s", 0x00007820, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD } }
 
 /* j_s BRAKET,BLINK_S,BRAKETdup 0111111011100000 */
-{ "j_s", 0x00007ee0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 } }
+{ "j_s", 0x00007ee0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 } }
 
 /* j_s BRAKET,BLINK_S,BRAKETdup 0111111111100000 */
-{ "j_s", 0x00007fe0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { C_DHARD } }
+{ "j_s", 0x00007fe0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, JUMP, ARC_INSN_SUBCLASS_NONE, { BRAKET, BLINK_S, BRAKETdup }, { C_DHARD } }
 
 /* kflag RC 00100xxx001010011xxxxxxxxxxxxxxx */
-{ "kflag", 0x20298000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { RC }, { 0 } }
+{ "kflag", 0x20298000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { RC }, { 0 } }
 
 /* kflag<.cc> RC 00100xxx111010011xxxxxxxxx0xxxxx */
-{ "kflag", 0x20e98000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { RC }, { C_CC } }
+{ "kflag", 0x20e98000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { RC }, { C_CC } }
 
 /* kflag UIMM6_20 00100xxx011010011xxxxxxxxxxxxxxx */
-{ "kflag", 0x20698000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { UIMM6_20 }, { 0 } }
+{ "kflag", 0x20698000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* kflag<.cc> UIMM6_20 00100xxx111010011xxxxxxxxx1xxxxx */
-{ "kflag", 0x20e98020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { UIMM6_20 }, { C_CC } }
+{ "kflag", 0x20e98020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { C_CC } }
 
 /* kflag SIMM12_20 00100xxx101010011xxxxxxxxxxxxxxx */
-{ "kflag", 0x20a98000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { SIMM12_20 }, { 0 } }
+{ "kflag", 0x20a98000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { SIMM12_20 }, { 0 } }
 
 /* kflag LIMM 00100xxx001010011xxx111110xxxxxx */
-{ "kflag", 0x20298f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { LIMM }, { 0 } }
+{ "kflag", 0x20298f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { LIMM }, { 0 } }
 
 /* kflag<.cc> LIMM 00100xxx111010011xxx1111100xxxxx */
-{ "kflag", 0x20e98f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { LIMM }, { C_CC } }
+{ "kflag", 0x20e98f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { LIMM }, { C_CC } }
 
 /* ld<.di><.aa> RA_CHK,BRAKET,RB,BRAKETdup 00010xxx000000000xxxxxx000xxxxxx */
-{ "ld", 0x10000000, 0xf8ff81c0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
+{ "ld", 0x10000000, 0xf8ff81c0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
 
 /* ld<.di><.aa> RA_CHK,BRAKET,RB,RC,BRAKETdup 00100xxxxx110000xxxxxxxxxxxxxxxx */
-{ "ld", 0x20300000, 0xf83f0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
+{ "ld", 0x20300000, 0xf83f0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
 
 /* ld<.di><.aa> ZA,BRAKET,RB,RC,BRAKETdup 00100xxxxx110000xxxxxxxxxx111110 */
-{ "ld", 0x2030003e, 0xf83f003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
+{ "ld", 0x2030003e, 0xf83f003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
 
 /* ld<.aa><.x> RA_CHK,BRAKET,RB,BRAKETdup 00010xxx000000000xxx0xx00xxxxxxx */
-{ "ld", 0x10000000, 0xf8ff8980, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
+{ "ld", 0x10000000, 0xf8ff8980, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
 
 /* ld<.aa><.x> RA_CHK,BRAKET,RB,RC,BRAKETdup 00100xxxxx11000x0xxxxxxxxxxxxxxx */
-{ "ld", 0x20300000, 0xf83e8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
+{ "ld", 0x20300000, 0xf83e8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
 
 /* ld<.aa><.x> ZA,BRAKET,RB,RC,BRAKETdup 00100xxxxx11000x0xxxxxxxxx111110 */
-{ "ld", 0x2030003e, 0xf83e803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
+{ "ld", 0x2030003e, 0xf83e803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
 
 /* ld<.di><.aa> RA_CHK,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx000xxxxxx */
-{ "ld", 0x10000000, 0xf80001c0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
+{ "ld", 0x10000000, 0xf80001c0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
 
 /* ld<.di><.aa> ZA,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx000111110 */
-{ "ld", 0x1000003e, 0xf80001ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
+{ "ld", 0x1000003e, 0xf80001ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
 
 /* ld<.aa><.x> RA_CHK,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxx0xx00xxxxxxx */
-{ "ld", 0x10000000, 0xf8000980, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
+{ "ld", 0x10000000, 0xf8000980, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
 
 /* ld<.aa><.x> ZA,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxx0xx00x111110 */
-{ "ld", 0x1000003e, 0xf80009bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
+{ "ld", 0x1000003e, 0xf80009bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
 
 /* ld<.di> RA_CHK,BRAKET,LIMM,BRAKETdup 00010110000000000111x00000xxxxxx */
-{ "ld", 0x16007000, 0xfffff7c0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_DI20 } }
+{ "ld", 0x16007000, 0xfffff7c0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_DI20 } }
 
 /* ld<.di> ZA,BRAKET,LIMM,BRAKETdup 00010110000000000111x00000111110 */
-{ "ld", 0x1600703e, 0xfffff7ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_DI20 } }
+{ "ld", 0x1600703e, 0xfffff7ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_DI20 } }
 
 /* ld<.di><.aa> RA_CHK,BRAKET,RB,XIMM,BRAKETdup 00100xxxxx110000xxxx111100xxxxxx */
-{ "ld", 0x20300f00, 0xf83f0fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
+{ "ld", 0x20300f00, 0xf83f0fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
 
 /* ld<.di><.aa> RA_CHK,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx110000xxxx111110xxxxxx */
-{ "ld", 0x20300f80, 0xf83f0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
+{ "ld", 0x20300f80, 0xf83f0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
 
 /* ld<.di><.aa> RA_CHK,BRAKET,XIMM,RC,BRAKETdup 00100100xx110000x111xxxxxxxxxxxx */
-{ "ld", 0x24307000, 0xff3f7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
+{ "ld", 0x24307000, 0xff3f7000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
 
 /* ld<.di><.aa> RA_CHK,BRAKET,LIMM,RC,BRAKETdup 00100110xx110000x111xxxxxxxxxxxx */
-{ "ld", 0x26307000, 0xff3f7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
+{ "ld", 0x26307000, 0xff3f7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
 
 /* ld<.di><.aa> ZA,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx110000xxxx111110111110 */
-{ "ld", 0x20300fbe, 0xf83f0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
+{ "ld", 0x20300fbe, 0xf83f0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
 
 /* ld<.di><.aa> ZA,BRAKET,LIMM,RC,BRAKETdup 00100110xx110000x111xxxxxx111110 */
-{ "ld", 0x2630703e, 0xff3f703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
+{ "ld", 0x2630703e, 0xff3f703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 } }
 
 /* ld<.x> RA_CHK,BRAKET,LIMM,BRAKETdup 0001011000000000011100000xxxxxxx */
-{ "ld", 0x16007000, 0xffffff80, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_X25 } }
+{ "ld", 0x16007000, 0xffffff80, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_X25 } }
 
 /* ld<.x> ZA,BRAKET,LIMM,BRAKETdup 0001011000000000011100000x111110 */
-{ "ld", 0x1600703e, 0xffffffbf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_X25 } }
+{ "ld", 0x1600703e, 0xffffffbf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_X25 } }
 
 /* ld<.aa><.x> RA_CHK,BRAKET,RB,XIMM,BRAKETdup 00100xxxxx11000x0xxx111100xxxxxx */
-{ "ld", 0x20300f00, 0xf83e8fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
+{ "ld", 0x20300f00, 0xf83e8fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
 
 /* ld<.aa><.x> RA_CHK,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx11000x0xxx111110xxxxxx */
-{ "ld", 0x20300f80, 0xf83e8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
+{ "ld", 0x20300f80, 0xf83e8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
 
 /* ld<.aa><.x> RA_CHK,BRAKET,XIMM,RC,BRAKETdup 00100100xx11000x0111xxxxxxxxxxxx */
-{ "ld", 0x24307000, 0xff3ef000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
+{ "ld", 0x24307000, 0xff3ef000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
 
 /* ld<.aa><.x> RA_CHK,BRAKET,LIMM,RC,BRAKETdup 00100110xx11000x0111xxxxxxxxxxxx */
-{ "ld", 0x26307000, 0xff3ef000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
+{ "ld", 0x26307000, 0xff3ef000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
 
 /* ld<.aa><.x> ZA,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx11000x0xxx111110111110 */
-{ "ld", 0x20300fbe, 0xf83e8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
+{ "ld", 0x20300fbe, 0xf83e8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 } }
 
 /* ld<.di><.aa> RA_CHK,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx111xxx000xxxxxx */
-{ "ld", 0x16007000, 0xff0071c0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
+{ "ld", 0x16007000, 0xff0071c0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
 
 /* ld<.di><.aa> ZA,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx111xxx000111110 */
-{ "ld", 0x1600703e, 0xff0071ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
+{ "ld", 0x1600703e, 0xff0071ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 } }
 
 /* ld<.aa><.x> RA_CHK,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx1110xx00xxxxxxx */
-{ "ld", 0x16007000, 0xff007980, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
+{ "ld", 0x16007000, 0xff007980, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
 
 /* ld<.aa><.x> ZA,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx1110xx00x111110 */
-{ "ld", 0x1600703e, 0xff0079bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
+{ "ld", 0x1600703e, 0xff0079bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 } }
 
 /* ld<.aa><.x> ZA,LIMM,RC 00100110xx11000x0111xxxxxx111110 */
-{ "ld", 0x2630703e, 0xff3ef03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, LIMM, RC }, { C_ZZ_W, C_AA8, C_X15 } }
+{ "ld", 0x2630703e, 0xff3ef03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_ZZ_W, C_AA8, C_X15 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,RB,BRAKETdup 00010xxx000000000xxxxxx01xxxxxxx */
-{ "ldb", 0x10000080, 0xf8ff8180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
+{ "ldb", 0x10000080, 0xf8ff8180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,RB,RC,BRAKETdup 00100xxxxx11001xxxxxxxxxxxxxxxxx */
-{ "ldb", 0x20320000, 0xf83e0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
+{ "ldb", 0x20320000, 0xf83e0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
 
 /* ldb<.di><.aa><.x> ZA,BRAKET,RB,RC,BRAKETdup 00100xxxxx11001xxxxxxxxxxx111110 */
-{ "ldb", 0x2032003e, 0xf83e003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
+{ "ldb", 0x2032003e, 0xf83e003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx01xxxxxxx */
-{ "ldb", 0x10000080, 0xf8000180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
+{ "ldb", 0x10000080, 0xf8000180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
 
 /* ldb<.di><.aa><.x> ZA,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx01x111110 */
-{ "ldb", 0x100000be, 0xf80001bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
+{ "ldb", 0x100000be, 0xf80001bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
 
 /* ldb<.di><.x> RA_CHK,BRAKET,XIMM,BRAKETdup 00010100000000000111x0001xxxxxxx */
-{ "ldb", 0x14007080, 0xfffff780, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 } }
+{ "ldb", 0x14007080, 0xfffff780, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, XIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 } }
 
 /* ldb<.di><.x> RA_CHK,BRAKET,LIMM,BRAKETdup 00010110000000000111x0001xxxxxxx */
-{ "ldb", 0x16007080, 0xfffff780, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 } }
+{ "ldb", 0x16007080, 0xfffff780, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 } }
 
 /* ldb<.di><.x> ZA,BRAKET,LIMM,BRAKETdup 00010110000000000111x0001x111110 */
-{ "ldb", 0x160070be, 0xfffff7bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 } }
+{ "ldb", 0x160070be, 0xfffff7bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,RB,XIMM,BRAKETdup 00100xxxxx11001xxxxx111100xxxxxx */
-{ "ldb", 0x20320f00, 0xf83e0fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
+{ "ldb", 0x20320f00, 0xf83e0fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx11001xxxxx111110xxxxxx */
-{ "ldb", 0x20320f80, 0xf83e0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
+{ "ldb", 0x20320f80, 0xf83e0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,XIMM,RC,BRAKETdup 00100100xx11001xx111xxxxxxxxxxxx */
-{ "ldb", 0x24327000, 0xff3e7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
+{ "ldb", 0x24327000, 0xff3e7000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,LIMM,RC,BRAKETdup 00100110xx11001xx111xxxxxxxxxxxx */
-{ "ldb", 0x26327000, 0xff3e7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
+{ "ldb", 0x26327000, 0xff3e7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
 
 /* ldb<.di><.aa><.x> ZA,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx11001xxxxx111110111110 */
-{ "ldb", 0x20320fbe, 0xf83e0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
+{ "ldb", 0x20320fbe, 0xf83e0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
 
 /* ldb<.di><.aa><.x> ZA,BRAKET,LIMM,RC,BRAKETdup 00100110xx11001xx111xxxxxx111110 */
-{ "ldb", 0x2632703e, 0xff3e703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
+{ "ldb", 0x2632703e, 0xff3e703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,XIMM,SIMM9_8,BRAKETdup 00010100xxxxxxxxx111xxx01xxxxxxx */
-{ "ldb", 0x14007080, 0xff007180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
+{ "ldb", 0x14007080, 0xff007180, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, XIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
 
 /* ldb<.di><.aa><.x> RA_CHK,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx111xxx01xxxxxxx */
-{ "ldb", 0x16007080, 0xff007180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
+{ "ldb", 0x16007080, 0xff007180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
 
 /* ldb<.di><.aa><.x> ZA,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx111xxx01x111110 */
-{ "ldb", 0x160070be, 0xff0071bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
+{ "ldb", 0x160070be, 0xff0071bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 } }
 
 /* ldh<.di><.aa><.x> RA_CHK,BRAKET,RB,BRAKETdup 00010xxx000000000xxxxxx10xxxxxxx */
-{ "ldh", 0x10000100, 0xf8ff8180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldh", 0x10000100, 0xf8ff8180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldh<.di><.aa><.x> RA_CHK,BRAKET,RB,RC,BRAKETdup 00100xxxxx11010xxxxxxxxxxxxxxxxx */
-{ "ldh", 0x20340000, 0xf83e0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldh", 0x20340000, 0xf83e0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldh<.di><.aa><.x> ZA,BRAKET,RB,RC,BRAKETdup 00100xxxxx11010xxxxxxxxxxx111110 */
-{ "ldh", 0x2034003e, 0xf83e003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldh", 0x2034003e, 0xf83e003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldh<.di><.aa><.x> RA_CHK,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx10xxxxxxx */
-{ "ldh", 0x10000100, 0xf8000180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldh", 0x10000100, 0xf8000180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldh<.di><.aa><.x> ZA,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx10x111110 */
-{ "ldh", 0x1000013e, 0xf80001bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldh", 0x1000013e, 0xf80001bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldh<.di><.x> RA_CHK,BRAKET,LIMM,BRAKETdup 00010110000000000111x0010xxxxxxx */
-{ "ldh", 0x16007100, 0xfffff780, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 } }
+{ "ldh", 0x16007100, 0xfffff780, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 } }
 
 /* ldh<.di><.x> ZA,BRAKET,LIMM,BRAKETdup 00010110000000000111x0010x111110 */
-{ "ldh", 0x1600713e, 0xfffff7bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 } }
+{ "ldh", 0x1600713e, 0xfffff7bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 } }
 
 /* ldh<.di><.aa><.x> RA_CHK,BRAKET,RB,XIMM,BRAKETdup 00100xxxxx11010xxxxx111100xxxxxx */
-{ "ldh", 0x20340f00, 0xf83e0fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldh", 0x20340f00, 0xf83e0fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldh<.di><.aa><.x> RA_CHK,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx11010xxxxx111110xxxxxx */
-{ "ldh", 0x20340f80, 0xf83e0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldh", 0x20340f80, 0xf83e0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldh<.di><.aa><.x> RA_CHK,BRAKET,XIMM,RC,BRAKETdup 00100100xx11010xx111xxxxxxxxxxxx */
-{ "ldh", 0x24347000, 0xff3e7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldh", 0x24347000, 0xff3e7000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldh<.di><.aa><.x> RA_CHK,BRAKET,LIMM,RC,BRAKETdup 00100110xx11010xx111xxxxxxxxxxxx */
-{ "ldh", 0x26347000, 0xff3e7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldh", 0x26347000, 0xff3e7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldh<.di><.aa><.x> ZA,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx11010xxxxx111110111110 */
-{ "ldh", 0x20340fbe, 0xf83e0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldh", 0x20340fbe, 0xf83e0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldh<.di><.aa><.x> ZA,BRAKET,LIMM,RC,BRAKETdup 00100110xx11010xx111xxxxxx111110 */
-{ "ldh", 0x2634703e, 0xff3e703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldh", 0x2634703e, 0xff3e703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldh<.di><.aa><.x> RA_CHK,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx111xxx10xxxxxxx */
-{ "ldh", 0x16007100, 0xff007180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldh", 0x16007100, 0xff007180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldh<.di><.aa><.x> ZA,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx111xxx10x111110 */
-{ "ldh", 0x1600713e, 0xff0071bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldh", 0x1600713e, 0xff0071bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldw<.di><.aa><.x> RA_CHK,BRAKET,RB,BRAKETdup 00010xxx000000000xxxxxx10xxxxxxx */
-{ "ldw", 0x10000100, 0xf8ff8180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldw", 0x10000100, 0xf8ff8180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldw<.di><.aa><.x> RA_CHK,BRAKET,RB,RC,BRAKETdup 00100xxxxx11010xxxxxxxxxxxxxxxxx */
-{ "ldw", 0x20340000, 0xf83e0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldw", 0x20340000, 0xf83e0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldw<.di><.aa><.x> ZA,BRAKET,RB,RC,BRAKETdup 00100xxxxx11010xxxxxxxxxxx111110 */
-{ "ldw", 0x2034003e, 0xf83e003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldw", 0x2034003e, 0xf83e003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldw<.di><.aa><.x> RA_CHK,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx10xxxxxxx */
-{ "ldw", 0x10000100, 0xf8000180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldw", 0x10000100, 0xf8000180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldw<.di><.aa><.x> ZA,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx10x111110 */
-{ "ldw", 0x1000013e, 0xf80001bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldw", 0x1000013e, 0xf80001bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldw<.di><.x> RA_CHK,BRAKET,LIMM,BRAKETdup 00010110000000000111x0010xxxxxxx */
-{ "ldw", 0x16007100, 0xfffff780, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 } }
+{ "ldw", 0x16007100, 0xfffff780, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 } }
 
 /* ldw<.di><.x> ZA,BRAKET,LIMM,BRAKETdup 00010110000000000111x0010x111110 */
-{ "ldw", 0x1600713e, 0xfffff7bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 } }
+{ "ldw", 0x1600713e, 0xfffff7bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 } }
 
 /* ldw<.di><.aa><.x> RA_CHK,BRAKET,RB,XIMM,BRAKETdup 00100xxxxx11010xxxxx111100xxxxxx */
-{ "ldw", 0x20340f00, 0xf83e0fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldw", 0x20340f00, 0xf83e0fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldw<.di><.aa><.x> RA_CHK,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx11010xxxxx111110xxxxxx */
-{ "ldw", 0x20340f80, 0xf83e0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldw", 0x20340f80, 0xf83e0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldw<.di><.aa><.x> RA_CHK,BRAKET,XIMM,RC,BRAKETdup 00100100xx11010xx111xxxxxxxxxxxx */
-{ "ldw", 0x24347000, 0xff3e7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldw", 0x24347000, 0xff3e7000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldw<.di><.aa><.x> RA_CHK,BRAKET,LIMM,RC,BRAKETdup 00100110xx11010xx111xxxxxxxxxxxx */
-{ "ldw", 0x26347000, 0xff3e7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldw", 0x26347000, 0xff3e7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldw<.di><.aa><.x> ZA,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx11010xxxxx111110111110 */
-{ "ldw", 0x20340fbe, 0xf83e0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldw", 0x20340fbe, 0xf83e0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldw<.di><.aa><.x> ZA,BRAKET,LIMM,RC,BRAKETdup 00100110xx11010xx111xxxxxx111110 */
-{ "ldw", 0x2634703e, 0xff3e703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
+{ "ldw", 0x2634703e, 0xff3e703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 } }
 
 /* ldw<.di><.aa><.x> RA_CHK,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx111xxx10xxxxxxx */
-{ "ldw", 0x16007100, 0xff007180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldw", 0x16007100, 0xff007180, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldw<.di><.aa><.x> ZA,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx111xxx10x111110 */
-{ "ldw", 0x1600713e, 0xff0071bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
+{ "ldw", 0x1600713e, 0xff0071bf, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 } }
 
 /* ldd<.di><.aa> RAD,BRAKET,RB,BRAKETdup 00010xxx000000000xxxxxx110xxxxxx */
-{ "ldd", 0x10000180, 0xf8ff81c0, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 } }
+{ "ldd", 0x10000180, 0xf8ff81c0, ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 } }
 
 /* ldd<.di><.aa> RAD,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxxxx110xxxxxx */
-{ "ldd", 0x10000180, 0xf80001c0, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 } }
+{ "ldd", 0x10000180, 0xf80001c0, ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 } }
 
 /* ldd<.di><.aa> RAD,BRAKET,LIMM,BRAKETdup 00010110000000000111xxx110xxxxxx */
-{ "ldd", 0x16007180, 0xfffff1c0, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_AA21 } }
+{ "ldd", 0x16007180, 0xfffff1c0, ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_AA21 } }
 
 /* ldd<.di><.aa> RAD,BRAKET,RB,RC,BRAKETdup 00100xxxxx110110xxxxxxxxxxxxxxxx */
-{ "ldd", 0x20360000, 0xf83f0000, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 } }
+{ "ldd", 0x20360000, 0xf83f0000, ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 } }
 
 /* ldd<.di><.aa> RAD,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx110110xxxx111110xxxxxx */
-{ "ldd", 0x20360f80, 0xf83f0fc0, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 } }
+{ "ldd", 0x20360f80, 0xf83f0fc0, ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 } }
 
 /* ldd<.di><.aa> RAD,BRAKET,LIMM,RC,BRAKETdup 00100110xx110110x111xxxxxxxxxxxx */
-{ "ldd", 0x26367000, 0xff3f7000, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_AA8 } }
+{ "ldd", 0x26367000, 0xff3f7000, ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_AA8 } }
 
 /* lddl RAD,BRAKET,RB,BRAKETdup 00010xxx000000000xxxx1101xxxxxxx */
-{ "lddl", 0x10000680, 0xf8ff8780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_AA_128S } }
+{ "lddl", 0x10000680, 0xf8ff8780, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_AA_128S } }
 
 /* lddl RAD,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxxx1101xxxxxxx */
-{ "lddl", 0x10000680, 0xf8000780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA_128S } }
+{ "lddl", 0x10000680, 0xf8000780, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA_128S } }
 
 /* lddl RAD,BRAKET,XIMM,BRAKETdup 00010100000000000111x1101xxxxxxx */
-{ "lddl", 0x14007680, 0xfffff780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, XIMM, BRAKETdup }, { C_AS_128S } }
+{ "lddl", 0x14007680, 0xfffff780, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, XIMM, BRAKETdup }, { C_AS_128S } }
 
 /* lddl RAD,BRAKET,LIMM,BRAKETdup 00010110000000000111x1101xxxxxxx */
-{ "lddl", 0x16007680, 0xfffff780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_AS_128S } }
+{ "lddl", 0x16007680, 0xfffff780, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_AS_128S } }
 
 /* lddl RAD,BRAKET,RB,RC,BRAKETdup 00100xxx1111001xxxxxxxxxxxxxxxxx */
-{ "lddl", 0x20f20000, 0xf8fe0000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_AA_128 } }
+{ "lddl", 0x20f20000, 0xf8fe0000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_AA_128 } }
 
 /* lddl RAD,BRAKET,RB,XIMM,BRAKETdup 00100xxx1111001xxxxx111100xxxxxx */
-{ "lddl", 0x20f20f00, 0xf8fe0fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, XIMM, BRAKETdup }, { C_AA_128 } }
+{ "lddl", 0x20f20f00, 0xf8fe0fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, XIMM, BRAKETdup }, { C_AA_128 } }
 
 /* lddl RAD,BRAKET,RB,LIMM,BRAKETdup 00100xxx1111001xxxxx111110xxxxxx */
-{ "lddl", 0x20f20f80, 0xf8fe0fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_AA_128 } }
+{ "lddl", 0x20f20f80, 0xf8fe0fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_AA_128 } }
 
 /* lddl RAD,BRAKET,XIMM,RC,BRAKETdup 001001001111001xx111xxxxxxxxxxxx */
-{ "lddl", 0x24f27000, 0xfffe7000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, XIMM, RC, BRAKETdup }, { C_AS_128 } }
+{ "lddl", 0x24f27000, 0xfffe7000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, XIMM, RC, BRAKETdup }, { C_AS_128 } }
 
 /* lddl RAD,BRAKET,LIMM,RC,BRAKETdup 001001101111001xx111xxxxxxxxxxxx */
-{ "lddl", 0x26f27000, 0xfffe7000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_AS_128 } }
+{ "lddl", 0x26f27000, 0xfffe7000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_AS_128 } }
 
 /* ldl<.aa> RA_CHK,BRAKET,RB,BRAKETdup 00010xxx000000000xxx1xx001xxxxxx */
-{ "ldl", 0x10000840, 0xf8ff89c0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA21 } }
+{ "ldl", 0x10000840, 0xf8ff89c0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA21 } }
 
 /* ldl<.aa> ZA,BRAKET,RB,BRAKETdup 00010xxx000000000xxx1xx001111110 */
-{ "ldl", 0x1000087e, 0xf8ff89ff, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA21 } }
+{ "ldl", 0x1000087e, 0xf8ff89ff, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA21 } }
 
 /* ldl<.aa> RA_CHK,BRAKET,RB,RC,BRAKETdup 00100xxxxx1100011xxxxxxxxxxxxxxx */
-{ "ldl", 0x20318000, 0xf83f8000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_L, C_AA8 } }
+{ "ldl", 0x20318000, 0xf83f8000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_L, C_AA8 } }
 
 /* ldl<.aa> ZA,BRAKET,RB,RC,BRAKETdup 00100xxxxx1100011xxxxxxxxx111110 */
-{ "ldl", 0x2031803e, 0xf83f803f, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_L, C_AA8 } }
+{ "ldl", 0x2031803e, 0xf83f803f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_L, C_AA8 } }
 
 /* ldl<.aa> RA_CHK,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxx1xx001xxxxxx */
-{ "ldl", 0x10000840, 0xf80009c0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 } }
+{ "ldl", 0x10000840, 0xf80009c0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 } }
 
 /* ldl<.aa> ZA,BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxx1xx001111110 */
-{ "ldl", 0x1000087e, 0xf80009ff, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 } }
+{ "ldl", 0x1000087e, 0xf80009ff, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 } }
 
 /* ldl ZA,BRAKET,LIMM,BRAKETdup 00010110000000000111100001111110 */
-{ "ldl", 0x1600787e, 0xffffffff, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L } }
+{ "ldl", 0x1600787e, 0xffffffff, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L } }
 
 /* ldl RA_CHK,BRAKET,LIMM,BRAKETdup 00010110000000000111100001xxxxxx */
-{ "ldl", 0x16007840, 0xffffffc0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L } }
+{ "ldl", 0x16007840, 0xffffffc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L } }
 
 /* ldl<.aa> RA_CHK,BRAKET,RB,XIMM,BRAKETdup 00100xxxxx1100011xxx111100xxxxxx */
-{ "ldl", 0x20318f00, 0xf83f8fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_L, C_AA8 } }
+{ "ldl", 0x20318f00, 0xf83f8fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_L, C_AA8 } }
 
 /* ldl<.aa> RA_CHK,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx1100011xxx111110xxxxxx */
-{ "ldl", 0x20318f80, 0xf83f8fc0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_L, C_AA8 } }
+{ "ldl", 0x20318f80, 0xf83f8fc0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_L, C_AA8 } }
 
 /* ldl<.aa> ZA,BRAKET,RB,LIMM,BRAKETdup 00100xxxxx1100011xxx111110111110 */
-{ "ldl", 0x20318fbe, 0xf83f8fff, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_L, C_AA8 } }
+{ "ldl", 0x20318fbe, 0xf83f8fff, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_L, C_AA8 } }
 
 /* ldl ZA,BRAKET,LIMM,RC,BRAKETdup 00100110001100011111xxxxxx111110 */
-{ "ldl", 0x2631f03e, 0xfffff03f, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_L } }
+{ "ldl", 0x2631f03e, 0xfffff03f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_L } }
 
 /* ldl<.aa> RA_CHK,BRAKET,XIMM,RC,BRAKETdup 00100100xx1100011111xxxxxxxxxxxx */
-{ "ldl", 0x2431f000, 0xff3ff000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_L, C_AA8 } }
+{ "ldl", 0x2431f000, 0xff3ff000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_L, C_AA8 } }
 
 /* ldl<.aa> RA_CHK,BRAKET,LO32,RC,BRAKETdup 00100110xx1100011111xxxxxxxxxxxx */
-{ "ldl", 0x2631f000, 0xff3ff000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LO32, RC, BRAKETdup }, { C_ZZ_L, C_AA8 } }
+{ "ldl", 0x2631f000, 0xff3ff000, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LO32, RC, BRAKETdup }, { C_ZZ_L, C_AA8 } }
 
 /* ldl<.aa> RA_CHK,BRAKET,LO32,SIMM9_8,BRAKETdup 00010110xxxxxxxxx1111xx001xxxxxx */
-{ "ldl", 0x16007840, 0xff0079c0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LO32, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 } }
+{ "ldl", 0x16007840, 0xff0079c0, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_CHK, BRAKET, LO32, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 } }
 
 /* ldl<.aa> ZA,BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx1111xx001111110 */
-{ "ldl", 0x1600787e, 0xff0079ff, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 } }
+{ "ldl", 0x1600787e, 0xff0079ff, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 } }
 
 /* ldb_s RA_S,BRAKET,RB_S,RC_S,BRAKETdup 01100xxxxxx01xxx */
-{ "ldb_s", 0x00006008, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_B } }
+{ "ldb_s", 0x00006008, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_B } }
 
 /* ldb_s RC_S,BRAKET,RB_S,UIMM5_11_S,BRAKETdup 10001xxxxxxxxxxx */
-{ "ldb_s", 0x00008800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B } }
+{ "ldb_s", 0x00008800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B } }
 
 /* ldb_s RB_S,BRAKET,SP_S,UIMM7_A32_11_S,BRAKETdup 11000xxx001xxxxx */
-{ "ldb_s", 0x0000c020, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B } }
+{ "ldb_s", 0x0000c020, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B } }
 
 /* ldb_s R0_S,BRAKET,GP_S,SIMM9_7_S,BRAKETdup 1100101xxxxxxxxx */
-{ "ldb_s", 0x0000ca00, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { C_ZZ_B } }
+{ "ldb_s", 0x0000ca00, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { C_ZZ_B } }
 
 /* ldh_s RA_S,BRAKET,RB_S,RC_S,BRAKETdup 01100xxxxxx10xxx */
-{ "ldh_s", 0x00006010, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H } }
+{ "ldh_s", 0x00006010, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H } }
 
 /* ldh_s RC_S,BRAKET,RB_S,UIMM6_A16_11_S,BRAKETdup 10010xxxxxxxxxxx */
-{ "ldh_s", 0x00009000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H } }
+{ "ldh_s", 0x00009000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H } }
 
 /* ldh_s RC_S,BRAKET,RB_S,UIMM6_A16_11_S,BRAKETdup 10011xxxxxxxxxxx */
-{ "ldh_s", 0x00009800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H, C_XHARD } }
+{ "ldh_s", 0x00009800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H, C_XHARD } }
 
 /* ldh_s R0_S,BRAKET,GP_S,SIMM10_A16_7_Sbis,BRAKETdup 1100110xxxxxxxxx */
-{ "ldh_s", 0x0000cc00, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { C_ZZ_H } }
+{ "ldh_s", 0x0000cc00, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { C_ZZ_H } }
 
 /* ld_s RA_S,BRAKET,RB_S,RC_S,BRAKETdup 01100xxxxxx00xxx */
-{ "ld_s", 0x00006000, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 } }
+{ "ld_s", 0x00006000, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 } }
 
 /* ld_s RA_S,BRAKET,RB_S,RC_S,BRAKETdup 01001xxxxxx00xxx */
 { "ld_s", 0x00004800, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, CD, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_AS } }
 
 /* ld_s RB_S,BRAKET,SP_S,UIMM7_A32_11_S,BRAKETdup 11000xxx000xxxxx */
-{ "ld_s", 0x0000c000, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 } }
+{ "ld_s", 0x0000c000, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 } }
 
 /* ld_s RC_S,BRAKET,RB_S,UIMM7_A32_11_S,BRAKETdup 10000xxxxxxxxxxx */
-{ "ld_s", 0x00008000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 } }
+{ "ld_s", 0x00008000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 } }
 
 /* ld_s RB_S,BRAKET,PCL_S,UIMM10_A32_8_S,BRAKETdup 11010xxxxxxxxxxx */
-{ "ld_s", 0x0000d000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { RB_S, BRAKET, PCL_S, UIMM10_A32_8_S, BRAKETdup }, { 0 } }
+{ "ld_s", 0x0000d000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { RB_S, BRAKET, PCL_S, UIMM10_A32_8_S, BRAKETdup }, { 0 } }
 
 /* ld_s R0_S,BRAKET,GP_S,SIMM11_A32_7_S,BRAKETdup 1100100xxxxxxxxx */
-{ "ld_s", 0x0000c800, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM11_A32_7_S, BRAKETdup }, { 0 } }
+{ "ld_s", 0x0000c800, 0x0000fe00, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, ARC_INSN_SUBCLASS_NONE, { R0_S, BRAKET, GP_S, SIMM11_A32_7_S, BRAKETdup }, { 0 } }
 
 /* ld_s R1_S,BRAKET,GP_S,SIMM11_A32_13_S,BRAKETdup 01010xxxxxx00xxx */
 { "ld_s", 0x00005000, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOAD, CD, { R1_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 } }
 
 /* llock<.di> RB,BRAKET,RC,BRAKETdup 00100xxx00101111xxxxxxxxxx010000 */
-{ "llock", 0x202f0010, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 } }
+{ "llock", 0x202f0010, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 } }
 
 /* llock<.di> ZA,BRAKET,RC,BRAKETdup 0010011000101111x111xxxxxx010000 */
-{ "llock", 0x262f7010, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 } }
+{ "llock", 0x262f7010, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 } }
 
 /* llock<.di> RB,BRAKET,UIMM6_20,BRAKETdup 00100xxx01101111xxxxxxxxxx010000 */
-{ "llock", 0x206f0010, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
+{ "llock", 0x206f0010, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
 
 /* llock<.di> ZA,BRAKET,UIMM6_20,BRAKETdup 0010011001101111x111xxxxxx010000 */
-{ "llock", 0x266f7010, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
+{ "llock", 0x266f7010, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
 
 /* llock<.di> RB,BRAKET,LIMM,BRAKETdup 00100xxx00101111xxxx111110010000 */
-{ "llock", 0x202f0f90, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 } }
+{ "llock", 0x202f0f90, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 } }
 
 /* llock<.di> ZA,BRAKET,LIMM,BRAKETdup 0010011000101111x111111110010000 */
-{ "llock", 0x262f7f90, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 } }
+{ "llock", 0x262f7f90, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LLOCK, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 } }
 
 /* llockl<.aq> RB,BRAKET,RC,BRAKETdup 01011xxx00101111xxxxxxxxxx010000 */
-{ "llockl", 0x582f0010, 0xf8ff003f, ARC_OPCODE_ARC64, LLOCK, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ } }
+{ "llockl", 0x582f0010, 0xf8ff003f, ARC_OPCODE_ARC64, LLOCK, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ } }
 
 /* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010.  */
-{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARC32, LLOCK, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
+{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARC32, LLOCK, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* llockd<.di> b,limm 00100bbb00101111DBBB111110010010.  */
-{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARC32, LLOCK, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
+{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARC32, LLOCK, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* lr RB_CHK,BRAKET,RC,BRAKETdup 00100xxx00101010xxxxxxxxxxxxxxxx */
-{ "lr", 0x202a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "lr", 0x202a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* lr ZA,BRAKET,RC,BRAKETdup 0010011000101010x111xxxxxxxxxxxx */
-{ "lr", 0x262a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { ZA, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "lr", 0x262a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* lr RB_CHK,BRAKET,UIMM6_20,BRAKETdup 00100xxx01101010xxxxxxxxxx000000 */
-{ "lr", 0x206a0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "lr", 0x206a0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* lr ZA,BRAKET,UIMM6_20,BRAKETdup 0010011001101010x111xxxxxx000000 */
-{ "lr", 0x266a7000, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "lr", 0x266a7000, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* lr RB_CHK,BRAKET,SIMM12_20,BRAKETdup 00100xxx10101010xxxxxxxxxxxxxxxx */
-{ "lr", 0x20aa0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "lr", 0x20aa0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* lr ZA,BRAKET,SIMM12_20,BRAKETdup 0010011010101010x111xxxxxxxxxxxx */
-{ "lr", 0x26aa7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "lr", 0x26aa7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* lr RB_CHK,BRAKET,LIMM,BRAKETdup 00100xxx00101010xxxx111110xxxxxx */
-{ "lr", 0x202a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "lr", 0x202a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* lr ZA,BRAKET,LIMM,BRAKETdup 0010011000101010x111111110xxxxxx */
-{ "lr", 0x262a7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "lr", 0x262a7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* lrl RB_CHK,BRAKET,RC,BRAKETdup 01011xxx001010100xxxxxxxxxxxxxxx */
-{ "lrl", 0x582a0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "lrl", 0x582a0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* lrl RB_CHK,BRAKET,UIMM6_20,BRAKETdup 01011xxx011010100xxxxxxxxxxxxxxx */
-{ "lrl", 0x586a0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "lrl", 0x586a0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* lrl RB_CHK,BRAKET,SIMM12_20,BRAKETdup 01011xxx101010100xxxxxxxxxxxxxxx */
-{ "lrl", 0x58aa0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "lrl", 0x58aa0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* lrl RB_CHK,BRAKET,XIMM,BRAKETdup 01011xxx001010100xxx111100xxxxxx */
-{ "lrl", 0x582a0f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, XIMM, BRAKETdup }, { 0 } }
+{ "lrl", 0x582a0f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, XIMM, BRAKETdup }, { 0 } }
 
 /* lrl RB_CHK,BRAKET,LIMM,BRAKETdup 01011xxx001010100xxx111110xxxxxx */
-{ "lrl", 0x582a0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "lrl", 0x582a0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* lsl16<.f> RB,RC 00101xxx00101111xxxxxxxxxx001010 */
 { "lsl16", 0x282f000a, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, SWAP, { RB, RC }, { C_F } }
@@ -4799,10 +4799,10 @@
 { "lsl8", 0x2e2f7f8f, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, SHFT1, { ZA, LIMM }, { C_F } }
 
 /* lsr<.f> RB,RC 00100xxx00101111xxxxxxxxxx000010 */
-{ "lsr", 0x202f0002, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_F } }
+{ "lsr", 0x202f0002, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* lsr<.f> ZA,RC 0010011000101111x111xxxxxx000010 */
-{ "lsr", 0x262f7002, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RC }, { C_F } }
+{ "lsr", 0x262f7002, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* lsr<.f> RA,RB,RC 00101xxx00000001xxxxxxxxxxxxxxxx */
 { "lsr", 0x28010000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, RB, RC }, { C_F } }
@@ -4814,10 +4814,10 @@
 { "lsr", 0x28c10000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* lsr<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx000010 */
-{ "lsr", 0x206f0002, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "lsr", 0x206f0002, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* lsr<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx000010 */
-{ "lsr", 0x266f7002, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "lsr", 0x266f7002, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* lsr<.f> RA,RB,UIMM6_20 00101xxx01000001xxxxxxxxxxxxxxxx */
 { "lsr", 0x28410000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F } }
@@ -4832,10 +4832,10 @@
 { "lsr", 0x28810000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* lsr<.f> RB,LIMM 00100xxx00101111xxxx111110000010 */
-{ "lsr", 0x202f0f82, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_F } }
+{ "lsr", 0x202f0f82, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* lsr<.f> ZA,LIMM 0010011000101111x111111110000010 */
-{ "lsr", 0x262f7f82, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM }, { C_F } }
+{ "lsr", 0x262f7f82, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* lsr<.f> RA,LIMM,RC 0010111000000001x111xxxxxxxxxxxx */
 { "lsr", 0x2e017000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F } }
@@ -4913,106 +4913,106 @@
 { "lsr8", 0x2e2f7f8e, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, SHFT1, { ZA, LIMM }, { C_F } }
 
 /* lsrl<.f> RA,RB,RC 01011xxx00100001xxxxxxxxxxxxxxxx */
-{ "lsrl", 0x58210000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "lsrl", 0x58210000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* lsrl<.f> ZA,RB,RC 01011xxx00100001xxxxxxxxxx111110 */
-{ "lsrl", 0x5821003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "lsrl", 0x5821003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* lsrl<.f><.cc> RB,RBdup,RC 01011xxx11100001xxxxxxxxxx0xxxxx */
-{ "lsrl", 0x58e10000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "lsrl", 0x58e10000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* lsrl<.f> RA,RB,UIMM6_20 01011xxx01100001xxxxxxxxxxxxxxxx */
-{ "lsrl", 0x58610000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "lsrl", 0x58610000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* lsrl<.f> ZA,RB,UIMM6_20 01011xxx01100001xxxxxxxxxx111110 */
-{ "lsrl", 0x5861003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "lsrl", 0x5861003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* lsrl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11100001xxxxxxxxxx1xxxxx */
-{ "lsrl", 0x58e10020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "lsrl", 0x58e10020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* lsrl<.f> RB,RBdup,SIMM12_20 01011xxx10100001xxxxxxxxxxxxxxxx */
-{ "lsrl", 0x58a10000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "lsrl", 0x58a10000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* lsrl<.f> RA,XIMM,RC 0101110000100001x111xxxxxxxxxxxx */
-{ "lsrl", 0x5c217000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "lsrl", 0x5c217000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* lsrl<.f> RA,RB,XIMM 01011xxx00100001xxxx111100xxxxxx */
-{ "lsrl", 0x58210f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "lsrl", 0x58210f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* lsrl<.f> ZA,XIMM,RC 0101110000100001x111xxxxxx111110 */
-{ "lsrl", 0x5c21703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "lsrl", 0x5c21703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* lsrl<.f> ZA,RB,XIMM 01011xxx00100001xxxx111100111110 */
-{ "lsrl", 0x58210f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "lsrl", 0x58210f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* lsrl<.f><.cc> ZA,XIMM,RC 0101110011100001x111xxxxxx0xxxxx */
-{ "lsrl", 0x5ce17000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "lsrl", 0x5ce17000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* lsrl<.f><.cc> RB,RBdup,XIMM 01011xxx11100001xxxx1111000xxxxx */
-{ "lsrl", 0x58e10f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "lsrl", 0x58e10f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* lsrl<.f> RA,XIMM,UIMM6_20 0101110001100001x111xxxxxxxxxxxx */
-{ "lsrl", 0x5c617000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "lsrl", 0x5c617000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* lsrl<.f> ZA,XIMM,UIMM6_20 0101110001100001x111xxxxxx111110 */
-{ "lsrl", 0x5c61703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "lsrl", 0x5c61703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* lsrl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011100001x111xxxxxx1xxxxx */
-{ "lsrl", 0x5ce17020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "lsrl", 0x5ce17020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* lsrl<.f> RA,LIMM,RC 0101111000100001x111xxxxxxxxxxxx */
-{ "lsrl", 0x5e217000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "lsrl", 0x5e217000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* lsrl<.f> RA,RB,LIMM 01011xxx00100001xxxx111110xxxxxx */
-{ "lsrl", 0x58210f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "lsrl", 0x58210f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* lsrl<.f> ZA,LIMM,RC 0101111000100001x111xxxxxx111110 */
-{ "lsrl", 0x5e21703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "lsrl", 0x5e21703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* lsrl<.f> ZA,RB,LIMM 01011xxx00100001xxxx111110111110 */
-{ "lsrl", 0x58210fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "lsrl", 0x58210fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* lsrl<.f><.cc> ZA,LIMM,RC 0101111011100001x111xxxxxx0xxxxx */
-{ "lsrl", 0x5ee17000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "lsrl", 0x5ee17000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* lsrl<.f><.cc> RB,RBdup,LIMM 01011xxx11100001xxxx1111100xxxxx */
-{ "lsrl", 0x58e10f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "lsrl", 0x58e10f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* lsrl<.f> RA,LIMM,UIMM6_20 0101111001100001x111xxxxxxxxxxxx */
-{ "lsrl", 0x5e617000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "lsrl", 0x5e617000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* lsrl<.f> ZA,LIMM,UIMM6_20 0101111001100001x111xxxxxx111110 */
-{ "lsrl", 0x5e61703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "lsrl", 0x5e61703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* lsrl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011100001x111xxxxxx1xxxxx */
-{ "lsrl", 0x5ee17020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "lsrl", 0x5ee17020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* lsrl<.f> ZA,XIMM,SIMM12_20 0101110010100001x111xxxxxxxxxxxx */
-{ "lsrl", 0x5ca17000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "lsrl", 0x5ca17000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* lsrl<.f> ZA,LIMM,SIMM12_20 0101111010100001x111xxxxxxxxxxxx */
-{ "lsrl", 0x5ea17000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "lsrl", 0x5ea17000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* lsrl<.f> RA,XIMM,XIMMdup 0101110000100001x111111100xxxxxx */
-{ "lsrl", 0x5c217f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "lsrl", 0x5c217f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* lsrl<.f> ZA,XIMM,XIMMdup 0101110000100001x111111100111110 */
-{ "lsrl", 0x5c217f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "lsrl", 0x5c217f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* lsrl<.f><.cc> ZA,XIMM,XIMMdup 0101110011100001x1111111000xxxxx */
-{ "lsrl", 0x5ce17f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "lsrl", 0x5ce17f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* lsrl<.f> RA,LIMM,LIMMdup 0101111000100001x111111110xxxxxx */
-{ "lsrl", 0x5e217f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "lsrl", 0x5e217f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* lsrl<.f> ZA,LIMM,LIMMdup 0101111000100001x111111110111110 */
-{ "lsrl", 0x5e217fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "lsrl", 0x5e217fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* lsrl<.f><.cc> ZA,LIMM,LIMMdup 0101111011100001x1111111100xxxxx */
-{ "lsrl", 0x5ee17f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "lsrl", 0x5ee17f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* lsr_s RB_S,RC_S 01111xxxxxx11101 */
-{ "lsr_s", 0x0000781d, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RC_S }, { 0 } }
+{ "lsr_s", 0x0000781d, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* lsr_s RB_S,RB_Sdup,RC_S 01111xxxxxx11001 */
 { "lsr_s", 0x00007819, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 } }
@@ -5021,28 +5021,28 @@
 { "lsr_s", 0x0000b820, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
 
 /* lstl<.f> RB,RC 01011xxx00101111xxxxxxxxxx000010 */
-{ "lstl", 0x582f0002, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "lstl", 0x582f0002, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* lstl<.f> ZA,RC 0101111000101111x111xxxxxx000010 */
-{ "lstl", 0x5e2f7002, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "lstl", 0x5e2f7002, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* lstl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx000010 */
-{ "lstl", 0x586f0002, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "lstl", 0x586f0002, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* lstl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx000010 */
-{ "lstl", 0x5e6f7002, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "lstl", 0x5e6f7002, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* lstl<.f> RB,XIMM 01011xxx00101111xxxx111100000010 */
-{ "lstl", 0x582f0f02, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "lstl", 0x582f0f02, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* lstl<.f> ZA,XIMM 0101111000101111x111111100000010 */
-{ "lstl", 0x5e2f7f02, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "lstl", 0x5e2f7f02, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* lstl<.f> RB,LIMM 01011xxx00101111xxxx111110000010 */
-{ "lstl", 0x582f0f82, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "lstl", 0x582f0f82, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* lstl<.f> ZA,LIMM 0101111000101111x111111110000010 */
-{ "lstl", 0x5e2f7f82, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "lstl", 0x5e2f7f82, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* mac<.f> RA_CHK,RB,RC 00101xxx00001110xxxxxxxxxxxxxxxx */
 { "mac", 0x280e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F } }
@@ -5285,454 +5285,454 @@
 { "macu", 0x2ecf7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* max<.f> RA,RB,RC 00100xxx00001000xxxxxxxxxxxxxxxx */
-{ "max", 0x20080000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "max", 0x20080000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* max<.f> ZA,RB,RC 00100xxx00001000xxxxxxxxxx111110 */
-{ "max", 0x2008003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "max", 0x2008003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* max<.f><.cc> RB,RBdup,RC 00100xxx11001000xxxxxxxxxx0xxxxx */
-{ "max", 0x20c80000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "max", 0x20c80000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* max<.f> RA,RB,UIMM6_20 00100xxx01001000xxxxxxxxxxxxxxxx */
-{ "max", 0x20480000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "max", 0x20480000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* max<.f> ZA,RB,UIMM6_20 00100xxx01001000xxxxxxxxxx111110 */
-{ "max", 0x2048003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "max", 0x2048003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* max<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11001000xxxxxxxxxx1xxxxx */
-{ "max", 0x20c80020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "max", 0x20c80020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* max<.f> RB,RBdup,SIMM12_20 00100xxx10001000xxxxxxxxxxxxxxxx */
-{ "max", 0x20880000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "max", 0x20880000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* max<.f> RA,LIMM,RC 0010011000001000x111xxxxxxxxxxxx */
-{ "max", 0x26087000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "max", 0x26087000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* max<.f> RA,RB,LIMM 00100xxx00001000xxxx111110xxxxxx */
-{ "max", 0x20080f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "max", 0x20080f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* max<.f> ZA,LIMM,RC 0010011000001000x111xxxxxx111110 */
-{ "max", 0x2608703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "max", 0x2608703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* max<.f> ZA,RB,LIMM 00100xxx00001000xxxx111110111110 */
-{ "max", 0x20080fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "max", 0x20080fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* max<.f><.cc> RB,RBdup,LIMM 00100xxx11001000xxxx1111100xxxxx */
-{ "max", 0x20c80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "max", 0x20c80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* max<.f><.cc> ZA,LIMM,RC 0010011011001000x111xxxxxx0xxxxx */
-{ "max", 0x26c87000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "max", 0x26c87000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* max<.f> RA,LIMM,UIMM6_20 0010011001001000x111xxxxxxxxxxxx */
-{ "max", 0x26487000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "max", 0x26487000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* max<.f> ZA,LIMM,UIMM6_20 0010011001001000x111xxxxxx111110 */
-{ "max", 0x2648703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "max", 0x2648703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* max<.f><.cc> ZA,LIMM,UIMM6_20 0010011011001000x111xxxxxx1xxxxx */
-{ "max", 0x26c87020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "max", 0x26c87020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* max<.f> ZA,LIMM,SIMM12_20 0010011010001000x111xxxxxxxxxxxx */
-{ "max", 0x26887000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "max", 0x26887000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* max<.f> RA,LIMM,LIMMdup 0010011000001000x111111110xxxxxx */
-{ "max", 0x26087f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "max", 0x26087f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* max<.f> ZA,LIMM,LIMMdup 0010011000001000x111111110111110 */
-{ "max", 0x26087fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "max", 0x26087fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* max<.f><.cc> ZA,LIMM,LIMMdup 0010011011001000x1111111100xxxxx */
-{ "max", 0x26c87f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "max", 0x26c87f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* maxl<.f> RA,RB,RC 01011xxx00001000xxxxxxxxxxxxxxxx */
-{ "maxl", 0x58080000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "maxl", 0x58080000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* maxl<.f> ZA,RB,RC 01011xxx00001000xxxxxxxxxx111110 */
-{ "maxl", 0x5808003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "maxl", 0x5808003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* maxl<.f><.cc> RB,RBdup,RC 01011xxx11001000xxxxxxxxxx0xxxxx */
-{ "maxl", 0x58c80000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "maxl", 0x58c80000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* maxl<.f> RA,RB,UIMM6_20 01011xxx01001000xxxxxxxxxxxxxxxx */
-{ "maxl", 0x58480000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "maxl", 0x58480000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* maxl<.f> ZA,RB,UIMM6_20 01011xxx01001000xxxxxxxxxx111110 */
-{ "maxl", 0x5848003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "maxl", 0x5848003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* maxl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11001000xxxxxxxxxx1xxxxx */
-{ "maxl", 0x58c80020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "maxl", 0x58c80020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* maxl<.f> RB,RBdup,SIMM12_20 01011xxx10001000xxxxxxxxxxxxxxxx */
-{ "maxl", 0x58880000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "maxl", 0x58880000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* maxl<.f> RA,XIMM,RC 0101110000001000x111xxxxxxxxxxxx */
-{ "maxl", 0x5c087000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "maxl", 0x5c087000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* maxl<.f> RA,RB,XIMM 01011xxx00001000xxxx111100xxxxxx */
-{ "maxl", 0x58080f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "maxl", 0x58080f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* maxl<.f> ZA,XIMM,RC 0101110000001000x111xxxxxx111110 */
-{ "maxl", 0x5c08703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "maxl", 0x5c08703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* maxl<.f> ZA,RB,XIMM 01011xxx00001000xxxx111100111110 */
-{ "maxl", 0x58080f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "maxl", 0x58080f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* maxl<.f><.cc> ZA,XIMM,RC 0101110011001000x111xxxxxx0xxxxx */
-{ "maxl", 0x5cc87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "maxl", 0x5cc87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* maxl<.f><.cc> RB,RBdup,XIMM 01011xxx11001000xxxx1111000xxxxx */
-{ "maxl", 0x58c80f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "maxl", 0x58c80f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* maxl<.f> RA,XIMM,UIMM6_20 0101110001001000x111xxxxxxxxxxxx */
-{ "maxl", 0x5c487000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "maxl", 0x5c487000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* maxl<.f> ZA,XIMM,UIMM6_20 0101110001001000x111xxxxxx111110 */
-{ "maxl", 0x5c48703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "maxl", 0x5c48703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* maxl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011001000x111xxxxxx1xxxxx */
-{ "maxl", 0x5cc87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "maxl", 0x5cc87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* maxl<.f> RA,LIMM,RC 0101111000001000x111xxxxxxxxxxxx */
-{ "maxl", 0x5e087000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "maxl", 0x5e087000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* maxl<.f> RA,RB,LIMM 01011xxx00001000xxxx111110xxxxxx */
-{ "maxl", 0x58080f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "maxl", 0x58080f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* maxl<.f> ZA,LIMM,RC 0101111000001000x111xxxxxx111110 */
-{ "maxl", 0x5e08703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "maxl", 0x5e08703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* maxl<.f> ZA,RB,LIMM 01011xxx00001000xxxx111110111110 */
-{ "maxl", 0x58080fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "maxl", 0x58080fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* maxl<.f><.cc> ZA,LIMM,RC 0101111011001000x111xxxxxx0xxxxx */
-{ "maxl", 0x5ec87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "maxl", 0x5ec87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* maxl<.f><.cc> RB,RBdup,LIMM 01011xxx11001000xxxx1111100xxxxx */
-{ "maxl", 0x58c80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "maxl", 0x58c80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* maxl<.f> RA,LIMM,UIMM6_20 0101111001001000x111xxxxxxxxxxxx */
-{ "maxl", 0x5e487000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "maxl", 0x5e487000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* maxl<.f> ZA,LIMM,UIMM6_20 0101111001001000x111xxxxxx111110 */
-{ "maxl", 0x5e48703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "maxl", 0x5e48703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* maxl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011001000x111xxxxxx1xxxxx */
-{ "maxl", 0x5ec87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "maxl", 0x5ec87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* maxl<.f> ZA,XIMM,SIMM12_20 0101110010001000x111xxxxxxxxxxxx */
-{ "maxl", 0x5c887000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "maxl", 0x5c887000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* maxl<.f> ZA,LIMM,SIMM12_20 0101111010001000x111xxxxxxxxxxxx */
-{ "maxl", 0x5e887000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "maxl", 0x5e887000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* maxl<.f> RA,XIMM,XIMMdup 0101110000001000x111111100xxxxxx */
-{ "maxl", 0x5c087f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "maxl", 0x5c087f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* maxl<.f> ZA,XIMM,XIMMdup 0101110000001000x111111100111110 */
-{ "maxl", 0x5c087f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "maxl", 0x5c087f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* maxl<.f><.cc> ZA,XIMM,XIMMdup 0101110011001000x1111111000xxxxx */
-{ "maxl", 0x5cc87f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "maxl", 0x5cc87f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* maxl<.f> RA,LIMM,LIMMdup 0101111000001000x111111110xxxxxx */
-{ "maxl", 0x5e087f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "maxl", 0x5e087f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* maxl<.f> ZA,LIMM,LIMMdup 0101111000001000x111111110111110 */
-{ "maxl", 0x5e087fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "maxl", 0x5e087fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* maxl<.f><.cc> ZA,LIMM,LIMMdup 0101111011001000x1111111100xxxxx */
-{ "maxl", 0x5ec87f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "maxl", 0x5ec87f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* min<.f> RA,RB,RC 00100xxx00001001xxxxxxxxxxxxxxxx */
-{ "min", 0x20090000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "min", 0x20090000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* min<.f> ZA,RB,RC 00100xxx00001001xxxxxxxxxx111110 */
-{ "min", 0x2009003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "min", 0x2009003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* min<.f><.cc> RB,RBdup,RC 00100xxx11001001xxxxxxxxxx0xxxxx */
-{ "min", 0x20c90000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "min", 0x20c90000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* min<.f> RA,RB,UIMM6_20 00100xxx01001001xxxxxxxxxxxxxxxx */
-{ "min", 0x20490000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "min", 0x20490000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* min<.f> ZA,RB,UIMM6_20 00100xxx01001001xxxxxxxxxx111110 */
-{ "min", 0x2049003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "min", 0x2049003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* min<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11001001xxxxxxxxxx1xxxxx */
-{ "min", 0x20c90020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "min", 0x20c90020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* min<.f> RB,RBdup,SIMM12_20 00100xxx10001001xxxxxxxxxxxxxxxx */
-{ "min", 0x20890000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "min", 0x20890000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* min<.f> RA,LIMM,RC 0010011000001001x111xxxxxxxxxxxx */
-{ "min", 0x26097000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "min", 0x26097000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* min<.f> RA,RB,LIMM 00100xxx00001001xxxx111110xxxxxx */
-{ "min", 0x20090f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "min", 0x20090f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* min<.f> ZA,LIMM,RC 0010011000001001x111xxxxxx111110 */
-{ "min", 0x2609703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "min", 0x2609703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* min<.f> ZA,RB,LIMM 00100xxx00001001xxxx111110111110 */
-{ "min", 0x20090fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "min", 0x20090fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* min<.f><.cc> RB,RBdup,LIMM 00100xxx11001001xxxx1111100xxxxx */
-{ "min", 0x20c90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "min", 0x20c90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* min<.f><.cc> ZA,LIMM,RC 0010011011001001x111xxxxxx0xxxxx */
-{ "min", 0x26c97000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "min", 0x26c97000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* min<.f> RA,LIMM,UIMM6_20 0010011001001001x111xxxxxxxxxxxx */
-{ "min", 0x26497000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "min", 0x26497000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* min<.f> ZA,LIMM,UIMM6_20 0010011001001001x111xxxxxx111110 */
-{ "min", 0x2649703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "min", 0x2649703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* min<.f><.cc> ZA,LIMM,UIMM6_20 0010011011001001x111xxxxxx1xxxxx */
-{ "min", 0x26c97020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "min", 0x26c97020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* min<.f> ZA,LIMM,SIMM12_20 0010011010001001x111xxxxxxxxxxxx */
-{ "min", 0x26897000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "min", 0x26897000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* min<.f> RA,LIMM,LIMMdup 0010011000001001x111111110xxxxxx */
-{ "min", 0x26097f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "min", 0x26097f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* min<.f> ZA,LIMM,LIMMdup 0010011000001001x111111110111110 */
-{ "min", 0x26097fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "min", 0x26097fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* min<.f><.cc> ZA,LIMM,LIMMdup 0010011011001001x1111111100xxxxx */
-{ "min", 0x26c97f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "min", 0x26c97f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* minl<.f> RA,RB,RC 01011xxx00001001xxxxxxxxxxxxxxxx */
-{ "minl", 0x58090000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "minl", 0x58090000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* minl<.f> ZA,RB,RC 01011xxx00001001xxxxxxxxxx111110 */
-{ "minl", 0x5809003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "minl", 0x5809003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* minl<.f><.cc> RB,RBdup,RC 01011xxx11001001xxxxxxxxxx0xxxxx */
-{ "minl", 0x58c90000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "minl", 0x58c90000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* minl<.f> RA,RB,UIMM6_20 01011xxx01001001xxxxxxxxxxxxxxxx */
-{ "minl", 0x58490000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "minl", 0x58490000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* minl<.f> ZA,RB,UIMM6_20 01011xxx01001001xxxxxxxxxx111110 */
-{ "minl", 0x5849003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "minl", 0x5849003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* minl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11001001xxxxxxxxxx1xxxxx */
-{ "minl", 0x58c90020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "minl", 0x58c90020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* minl<.f> RB,RBdup,SIMM12_20 01011xxx10001001xxxxxxxxxxxxxxxx */
-{ "minl", 0x58890000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "minl", 0x58890000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* minl<.f> RA,XIMM,RC 0101110000001001x111xxxxxxxxxxxx */
-{ "minl", 0x5c097000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "minl", 0x5c097000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* minl<.f> RA,RB,XIMM 01011xxx00001001xxxx111100xxxxxx */
-{ "minl", 0x58090f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "minl", 0x58090f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* minl<.f> ZA,XIMM,RC 0101110000001001x111xxxxxx111110 */
-{ "minl", 0x5c09703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "minl", 0x5c09703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* minl<.f> ZA,RB,XIMM 01011xxx00001001xxxx111100111110 */
-{ "minl", 0x58090f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "minl", 0x58090f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* minl<.f><.cc> ZA,XIMM,RC 0101110011001001x111xxxxxx0xxxxx */
-{ "minl", 0x5cc97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "minl", 0x5cc97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* minl<.f><.cc> RB,RBdup,XIMM 01011xxx11001001xxxx1111000xxxxx */
-{ "minl", 0x58c90f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "minl", 0x58c90f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* minl<.f> RA,XIMM,UIMM6_20 0101110001001001x111xxxxxxxxxxxx */
-{ "minl", 0x5c497000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "minl", 0x5c497000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* minl<.f> ZA,XIMM,UIMM6_20 0101110001001001x111xxxxxx111110 */
-{ "minl", 0x5c49703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "minl", 0x5c49703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* minl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011001001x111xxxxxx1xxxxx */
-{ "minl", 0x5cc97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "minl", 0x5cc97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* minl<.f> RA,LIMM,RC 0101111000001001x111xxxxxxxxxxxx */
-{ "minl", 0x5e097000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "minl", 0x5e097000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* minl<.f> RA,RB,LIMM 01011xxx00001001xxxx111110xxxxxx */
-{ "minl", 0x58090f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "minl", 0x58090f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* minl<.f> ZA,LIMM,RC 0101111000001001x111xxxxxx111110 */
-{ "minl", 0x5e09703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "minl", 0x5e09703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* minl<.f> ZA,RB,LIMM 01011xxx00001001xxxx111110111110 */
-{ "minl", 0x58090fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "minl", 0x58090fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* minl<.f><.cc> ZA,LIMM,RC 0101111011001001x111xxxxxx0xxxxx */
-{ "minl", 0x5ec97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "minl", 0x5ec97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* minl<.f><.cc> RB,RBdup,LIMM 01011xxx11001001xxxx1111100xxxxx */
-{ "minl", 0x58c90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "minl", 0x58c90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* minl<.f> RA,LIMM,UIMM6_20 0101111001001001x111xxxxxxxxxxxx */
-{ "minl", 0x5e497000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "minl", 0x5e497000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* minl<.f> ZA,LIMM,UIMM6_20 0101111001001001x111xxxxxx111110 */
-{ "minl", 0x5e49703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "minl", 0x5e49703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* minl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011001001x111xxxxxx1xxxxx */
-{ "minl", 0x5ec97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "minl", 0x5ec97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* minl<.f> ZA,XIMM,SIMM12_20 0101110010001001x111xxxxxxxxxxxx */
-{ "minl", 0x5c897000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "minl", 0x5c897000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* minl<.f> ZA,LIMM,SIMM12_20 0101111010001001x111xxxxxxxxxxxx */
-{ "minl", 0x5e897000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "minl", 0x5e897000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* minl<.f> RA,XIMM,XIMMdup 0101110000001001x111111100xxxxxx */
-{ "minl", 0x5c097f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "minl", 0x5c097f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* minl<.f> ZA,XIMM,XIMMdup 0101110000001001x111111100111110 */
-{ "minl", 0x5c097f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "minl", 0x5c097f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* minl<.f><.cc> ZA,XIMM,XIMMdup 0101110011001001x1111111000xxxxx */
-{ "minl", 0x5cc97f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "minl", 0x5cc97f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* minl<.f> RA,LIMM,LIMMdup 0101111000001001x111111110xxxxxx */
-{ "minl", 0x5e097f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "minl", 0x5e097f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* minl<.f> ZA,LIMM,LIMMdup 0101111000001001x111111110111110 */
-{ "minl", 0x5e097fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "minl", 0x5e097fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* minl<.f><.cc> ZA,LIMM,LIMMdup 0101111011001001x1111111100xxxxx */
-{ "minl", 0x5ec97f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "minl", 0x5ec97f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* nop  00100110010010100111000000000000 */
-{ "nop", 0x264a7000, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, {  }, { 0 } }
+{ "nop", 0x264a7000, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* mov<.f> RB,RC 00100xxx00001010xxxxxxxxxxxxxxxx */
-{ "mov", 0x200a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RC }, { C_F } }
+{ "mov", 0x200a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* mov<.f> ZA,RC 0010011000001010x111xxxxxxxxxxxx */
-{ "mov", 0x260a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RC }, { C_F } }
+{ "mov", 0x260a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* mov<.f><.cc> RB,RC 00100xxx11001010xxxxxxxxxx0xxxxx */
-{ "mov", 0x20ca0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RC }, { C_F, C_CC } }
+{ "mov", 0x20ca0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F, C_CC } }
 
 /* mov<.f><.cc> ZA,RC 0010011011001010x111xxxxxx0xxxxx */
-{ "mov", 0x26ca7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RC }, { C_F, C_CC } }
+{ "mov", 0x26ca7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F, C_CC } }
 
 /* mov<.f> RB,UIMM6_20 00100xxx01001010xxxxxxxxxxxxxxxx */
-{ "mov", 0x204a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "mov", 0x204a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* mov<.f> ZA,UIMM6_20 0010011001001010x111xxxxxxxxxxxx */
-{ "mov", 0x264a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "mov", 0x264a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* mov<.f><.cc> RB,UIMM6_20 00100xxx11001010xxxxxxxxxx1xxxxx */
-{ "mov", 0x20ca0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, UIMM6_20 }, { C_F, C_CC } }
+{ "mov", 0x20ca0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F, C_CC } }
 
 /* mov<.f><.cc> ZA,UIMM6_20 0010011011001010x111xxxxxx1xxxxx */
-{ "mov", 0x26ca7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, UIMM6_20 }, { C_F, C_CC } }
+{ "mov", 0x26ca7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F, C_CC } }
 
 /* mov<.f> RB,SIMM12_20 00100xxx10001010xxxxxxxxxxxxxxxx */
-{ "mov", 0x208a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, SIMM12_20 }, { C_F } }
+{ "mov", 0x208a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { C_F } }
 
 /* mov<.f> ZA,SIMM12_20 0010011010001010x111xxxxxxxxxxxx */
-{ "mov", 0x268a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, SIMM12_20 }, { C_F } }
+{ "mov", 0x268a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, SIMM12_20 }, { C_F } }
 
 /* mov<.f> RB,LIMM 00100xxx00001010xxxx111110xxxxxx */
-{ "mov", 0x200a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, LIMM }, { C_F } }
+{ "mov", 0x200a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* mov<.f> ZA,LIMM 0010011000001010x111111110xxxxxx */
-{ "mov", 0x260a7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM }, { C_F } }
+{ "mov", 0x260a7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* mov<.f><.cc> RB,LIMM 00100xxx11001010xxxx1111100xxxxx */
-{ "mov", 0x20ca0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, LIMM }, { C_F, C_CC } }
+{ "mov", 0x20ca0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F, C_CC } }
 
 /* mov<.f><.cc> ZA,LIMM 0010011011001010x1111111100xxxxx */
-{ "mov", 0x26ca7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM }, { C_F, C_CC } }
+{ "mov", 0x26ca7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F, C_CC } }
 
 /* movhl RB,RC 01011xxx000010110xxxxxxxxxxxxxxx */
-{ "movhl", 0x580b0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 } }
+{ "movhl", 0x580b0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* movhl<.cc> RB,RC 01011xxx110010110xxxxxxxxx0xxxxx */
-{ "movhl", 0x58cb0000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC } }
+{ "movhl", 0x58cb0000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* movhl RB,UIMM6_20 01011xxx010010110xxxxxxxxxxxxxxx */
-{ "movhl", 0x584b0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "movhl", 0x584b0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* movhl<.cc> RB,UIMM6_20 01011xxx110010110xxxxxxxxx1xxxxx */
-{ "movhl", 0x58cb0020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "movhl", 0x58cb0020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* movhl RB,SIMM12_20 01011xxx100010110xxxxxxxxxxxxxxx */
-{ "movhl", 0x588b0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "movhl", 0x588b0000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* movhl RB,HI32 01011xxx000010110xxx111110xxxxxx */
-{ "movhl", 0x580b0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, HI32 }, { 0 } }
+{ "movhl", 0x580b0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, HI32 }, { 0 } }
 
 /* movhl<.cc> RB,HI32 01011xxx110010110xxx1111100xxxxx */
-{ "movhl", 0x58cb0f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, HI32 }, { C_CC } }
+{ "movhl", 0x58cb0f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, HI32 }, { C_CC } }
 
 /* movhl_s RH_S,HI32 01110000xxx010xx */
-{ "movhl_s", 0x00007008, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, HI32 }, { 0 } }
+{ "movhl_s", 0x00007008, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, HI32 }, { 0 } }
 
 /* movl<.f> RB,RC 01011xxx00001010xxxxxxxxxxxxxxxx */
-{ "movl", 0x580a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "movl", 0x580a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* movl<.f><.cc> RB,RC 01011xxx11001010xxxxxxxxxx0xxxxx */
-{ "movl", 0x58ca0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F, C_CC } }
+{ "movl", 0x58ca0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F, C_CC } }
 
 /* movl<.f> RB,UIMM6_20 01011xxx01001010xxxxxxxxxxxxxxxx */
-{ "movl", 0x584a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "movl", 0x584a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* movl<.f><.cc> RB,UIMM6_20 01011xxx11001010xxxxxxxxxx1xxxxx */
-{ "movl", 0x58ca0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F, C_CC } }
+{ "movl", 0x58ca0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F, C_CC } }
 
 /* movl<.f> RB,SIMM12_20 01011xxx10001010xxxxxxxxxxxxxxxx */
-{ "movl", 0x588a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { C_F } }
+{ "movl", 0x588a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { C_F } }
 
 /* movl<.f> RB,XIMM 01011xxx00001010xxxx111100xxxxxx */
-{ "movl", 0x580a0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "movl", 0x580a0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* movl<.f><.cc> RB,XIMM 01011xxx11001010xxxx1111000xxxxx */
-{ "movl", 0x58ca0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F, C_CC } }
+{ "movl", 0x58ca0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F, C_CC } }
 
 /* movl<.f> RB,LIMM 01011xxx00001010xxxx111110xxxxxx */
-{ "movl", 0x580a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "movl", 0x580a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* movl<.f><.cc> RB,LIMM 01011xxx11001010xxxx1111100xxxxx */
-{ "movl", 0x58ca0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F, C_CC } }
+{ "movl", 0x58ca0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F, C_CC } }
 
 /* movl_s G_S,RH_S 01000xxxxxxxx1xx */
-{ "movl_s", 0x00004004, 0x0000f804, ARC_OPCODE_ARC64, ARITH, NONE, { G_S, RH_S }, { 0 } }
+{ "movl_s", 0x00004004, 0x0000f804, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { G_S, RH_S }, { 0 } }
 
 /* movl_s RB_S,UIMM8_8_S 11011xxxxxxxxxxx */
-{ "movl_s", 0x0000d800, 0x0000f800, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, UIMM8_8_S }, { 0 } }
+{ "movl_s", 0x0000d800, 0x0000f800, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, UIMM8_8_S }, { 0 } }
 
 /* movl_s G_S,LIMM_S 01000xxx110xx111 */
-{ "movl_s", 0x000040c7, 0x0000f8e7, ARC_OPCODE_ARC64, MOVE, NONE, { G_S, LIMM_S }, { 0 } }
+{ "movl_s", 0x000040c7, 0x0000f8e7, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { G_S, LIMM_S }, { 0 } }
 
 /* mov_s RB_S,RH_S 01110xxxxxx111xx */
-{ "mov_s", 0x0000701c, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB_S, RH_S }, { C_NE, C_CC_NE } }
+{ "mov_s", 0x0000701c, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB_S, RH_S }, { C_NE, C_CC_NE } }
 
 /* mov_s G_S,RH_S 01000xxxxxxxx0xx */
-{ "mov_s", 0x00004000, 0x0000f804, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { G_S, RH_S }, { 0 } }
+{ "mov_s", 0x00004000, 0x0000f804, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { G_S, RH_S }, { 0 } }
 
 /* mov_s ZA_S,RH_S 01000110xxx110xx */
-{ "mov_s", 0x00004618, 0x0000ff1c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA_S, RH_S }, { 0 } }
+{ "mov_s", 0x00004618, 0x0000ff1c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA_S, RH_S }, { 0 } }
 
 /* mov_s RH_S,SIMM3_5_S 01110xxxxxx011xx */
-{ "mov_s", 0x0000700c, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RH_S, SIMM3_5_S }, { 0 } }
+{ "mov_s", 0x0000700c, 0x0000f81c, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RH_S, SIMM3_5_S }, { 0 } }
 
 /* mov_s ZA_S,SIMM3_5_S 01110xxx11001111 */
-{ "mov_s", 0x000070cf, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA_S, SIMM3_5_S }, { 0 } }
+{ "mov_s", 0x000070cf, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA_S, SIMM3_5_S }, { 0 } }
 
 /* mov_s RB_S,UIMM8_8_S 11011xxxxxxxxxxx */
-{ "mov_s", 0x0000d800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB_S, UIMM8_8_S }, { 0 } }
+{ "mov_s", 0x0000d800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB_S, UIMM8_8_S }, { 0 } }
 
 /* mov_s RB_S,LIMM_S 01110xxx11011111 */
-{ "mov_s", 0x000070df, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB_S, LIMM_S }, { C_NE, C_CC_NE } }
+{ "mov_s", 0x000070df, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB_S, LIMM_S }, { C_NE, C_CC_NE } }
 
 /* mov_s G_S,LIMM_S 01000xxx110xx011 */
-{ "mov_s", 0x000040c3, 0x0000f8e7, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { G_S, LIMM_S }, { 0 } }
+{ "mov_s", 0x000040c3, 0x0000f8e7, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { G_S, LIMM_S }, { 0 } }
 
 /* mov_s ZA_S,LIMM_S 0100011011011011 */
-{ "mov_s", 0x000046db, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA_S, LIMM_S }, { 0 } }
+{ "mov_s", 0x000046db, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA_S, LIMM_S }, { 0 } }
 
 /* mpy<.f> RA_CHK,RB,RC 00100xxx00011010xxxxxxxxxxxxxxxx */
 { "mpy", 0x201a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F } }
@@ -6224,379 +6224,379 @@
 { "mpy_s", 0x0000780c, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY6E, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* neg<.f> RA,RB 00100xxx01001110xxxx000000xxxxxx */
-{ "neg", 0x204e0000, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB }, { C_F } }
+{ "neg", 0x204e0000, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB }, { C_F } }
 
 /* neg<.f><.cc> RB,RBdup 00100xxx11001110xxxx0000001xxxxx */
-{ "neg", 0x20ce0020, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup }, { C_F, C_CC } }
+{ "neg", 0x20ce0020, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup }, { C_F, C_CC } }
 
 /* neg<.f> RA,LIMM 0010011001001110x111000000xxxxxx */
-{ "neg", 0x264e7000, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM }, { C_F } }
+{ "neg", 0x264e7000, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM }, { C_F } }
 
 /* neg<.f><.cc> ZA,LIMM 0010011011001110x1110000001xxxxx */
-{ "neg", 0x26ce7020, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F, C_CC } }
+{ "neg", 0x26ce7020, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F, C_CC } }
 
 /* neg_s RB_S,RC_S 01111xxxxxx10011 */
-{ "neg_s", 0x00007813, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RC_S }, { 0 } }
+{ "neg_s", 0x00007813, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* nop_s  0111100011100000 */
-{ "nop_s", 0x000078e0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, {  }, { 0 } }
+{ "nop_s", 0x000078e0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* norm<.f> RB,RC 00101xxx00101111xxxxxxxxxx000001 */
-{ "norm", 0x282f0001, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "norm", 0x282f0001, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* norm<.f> ZA,RC 0010111000101111x111xxxxxx000001 */
-{ "norm", 0x2e2f7001, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "norm", 0x2e2f7001, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* norm<.f> RB,UIMM6_20 00101xxx01101111xxxxxxxxxx000001 */
-{ "norm", 0x286f0001, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "norm", 0x286f0001, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* norm<.f> ZA,UIMM6_20 0010111001101111x111xxxxxx000001 */
-{ "norm", 0x2e6f7001, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "norm", 0x2e6f7001, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* norm<.f> RB,LIMM 00101xxx00101111xxxx111110000001 */
-{ "norm", 0x282f0f81, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "norm", 0x282f0f81, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* norm<.f> ZA,LIMM 0010111000101111x111111110000001 */
-{ "norm", 0x2e2f7f81, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "norm", 0x2e2f7f81, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* normh<.f> RB,RC 00101xxx00101111xxxxxxxxxx001000 */
-{ "normh", 0x282f0008, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "normh", 0x282f0008, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* normh<.f> ZA,RC 0010111000101111x111xxxxxx001000 */
-{ "normh", 0x2e2f7008, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "normh", 0x2e2f7008, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* normh<.f> RB,UIMM6_20 00101xxx01101111xxxxxxxxxx001000 */
-{ "normh", 0x286f0008, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "normh", 0x286f0008, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* normh<.f> ZA,UIMM6_20 0010111001101111x111xxxxxx001000 */
-{ "normh", 0x2e6f7008, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "normh", 0x2e6f7008, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* normh<.f> RB,LIMM 00101xxx00101111xxxx111110001000 */
-{ "normh", 0x282f0f88, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "normh", 0x282f0f88, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* normh<.f> ZA,LIMM 0010111000101111x111111110001000 */
-{ "normh", 0x2e2f7f88, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "normh", 0x2e2f7f88, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* norml<.f> RB,RC 01011xxx00101111xxxxxxxxxx100001 */
-{ "norml", 0x582f0021, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "norml", 0x582f0021, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* norml<.f> ZA,RC 0101111000101111x111xxxxxx100001 */
-{ "norml", 0x5e2f7021, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "norml", 0x5e2f7021, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* norml<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx100001 */
-{ "norml", 0x586f0021, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "norml", 0x586f0021, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* norml<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx100001 */
-{ "norml", 0x5e6f7021, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "norml", 0x5e6f7021, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* norml<.f> RB,XIMM 01011xxx00101111xxxx111100100001 */
-{ "norml", 0x582f0f21, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "norml", 0x582f0f21, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* norml<.f> ZA,XIMM 0101111000101111x111111100100001 */
-{ "norml", 0x5e2f7f21, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "norml", 0x5e2f7f21, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* norml<.f> RB,LIMM 01011xxx00101111xxxx111110100001 */
-{ "norml", 0x582f0fa1, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "norml", 0x582f0fa1, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* norml<.f> ZA,LIMM 0101111000101111x111111110100001 */
-{ "norml", 0x5e2f7fa1, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "norml", 0x5e2f7fa1, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* not<.f> RB,RC 00100xxx00101111xxxxxxxxxx001010 */
-{ "not", 0x202f000a, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_F } }
+{ "not", 0x202f000a, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* not<.f> ZA,RC 0010011000101111x111xxxxxx001010 */
-{ "not", 0x262f700a, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RC }, { C_F } }
+{ "not", 0x262f700a, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* not<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx001010 */
-{ "not", 0x206f000a, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "not", 0x206f000a, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* not<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx001010 */
-{ "not", 0x266f700a, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "not", 0x266f700a, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* not<.f> RB,LIMM 00100xxx00101111xxxx111110001010 */
-{ "not", 0x202f0f8a, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_F } }
+{ "not", 0x202f0f8a, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* not<.f> ZA,LIMM 0010011000101111x111111110001010 */
-{ "not", 0x262f7f8a, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM }, { C_F } }
+{ "not", 0x262f7f8a, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* notl<.f> RB,RC 01011xxx00101111xxxxxxxxxx001010 */
-{ "notl", 0x582f000a, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "notl", 0x582f000a, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* notl<.f> ZA,RC 0101111000101111x111xxxxxx001010 */
-{ "notl", 0x5e2f700a, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "notl", 0x5e2f700a, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* notl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx001010 */
-{ "notl", 0x586f000a, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "notl", 0x586f000a, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* notl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx001010 */
-{ "notl", 0x5e6f700a, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "notl", 0x5e6f700a, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* notl<.f> RB,XIMM 01011xxx00101111xxxx111100001010 */
-{ "notl", 0x582f0f0a, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "notl", 0x582f0f0a, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* notl<.f> ZA,XIMM 0101111000101111x111111100001010 */
-{ "notl", 0x5e2f7f0a, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "notl", 0x5e2f7f0a, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* notl<.f> RB,LIMM 01011xxx00101111xxxx111110001010 */
-{ "notl", 0x582f0f8a, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "notl", 0x582f0f8a, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* notl<.f> ZA,LIMM 0101111000101111x111111110001010 */
-{ "notl", 0x5e2f7f8a, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "notl", 0x5e2f7f8a, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* not_s RB_S,RC_S 01111xxxxxx10010 */
-{ "not_s", 0x00007812, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RC_S }, { 0 } }
+{ "not_s", 0x00007812, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* or<.f> RA,RB,RC 00100xxx00000101xxxxxxxxxxxxxxxx */
-{ "or", 0x20050000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "or", 0x20050000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* or<.f> ZA,RB,RC 00100xxx00000101xxxxxxxxxx111110 */
-{ "or", 0x2005003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "or", 0x2005003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* or<.f><.cc> RB,RBdup,RC 00100xxx11000101xxxxxxxxxx0xxxxx */
-{ "or", 0x20c50000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "or", 0x20c50000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* or<.f> RA,RB,UIMM6_20 00100xxx01000101xxxxxxxxxxxxxxxx */
-{ "or", 0x20450000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "or", 0x20450000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* or<.f> ZA,RB,UIMM6_20 00100xxx01000101xxxxxxxxxx111110 */
-{ "or", 0x2045003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "or", 0x2045003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* or<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11000101xxxxxxxxxx1xxxxx */
-{ "or", 0x20c50020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "or", 0x20c50020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* or<.f> RB,RBdup,SIMM12_20 00100xxx10000101xxxxxxxxxxxxxxxx */
-{ "or", 0x20850000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "or", 0x20850000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* or<.f> RA,LIMM,RC 0010011000000101x111xxxxxxxxxxxx */
-{ "or", 0x26057000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "or", 0x26057000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* or<.f> RA,RB,LIMM 00100xxx00000101xxxx111110xxxxxx */
-{ "or", 0x20050f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "or", 0x20050f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* or<.f> ZA,LIMM,RC 0010011000000101x111xxxxxx111110 */
-{ "or", 0x2605703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "or", 0x2605703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* or<.f> ZA,RB,LIMM 00100xxx00000101xxxx111110111110 */
-{ "or", 0x20050fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "or", 0x20050fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* or<.f><.cc> RB,RBdup,LIMM 00100xxx11000101xxxx1111100xxxxx */
-{ "or", 0x20c50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "or", 0x20c50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* or<.f><.cc> ZA,LIMM,RC 0010011011000101x111xxxxxx0xxxxx */
-{ "or", 0x26c57000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "or", 0x26c57000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* or<.f> RA,LIMM,UIMM6_20 0010011001000101x111xxxxxxxxxxxx */
-{ "or", 0x26457000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "or", 0x26457000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* or<.f> ZA,LIMM,UIMM6_20 0010011001000101x111xxxxxx111110 */
-{ "or", 0x2645703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "or", 0x2645703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* or<.f><.cc> ZA,LIMM,UIMM6_20 0010011011000101x111xxxxxx1xxxxx */
-{ "or", 0x26c57020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "or", 0x26c57020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* or<.f> ZA,LIMM,SIMM12_20 0010011010000101x111xxxxxxxxxxxx */
-{ "or", 0x26857000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "or", 0x26857000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* or<.f> RA,LIMM,LIMMdup 0010011000000101x111111110xxxxxx */
-{ "or", 0x26057f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "or", 0x26057f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* or<.f> ZA,LIMM,LIMMdup 0010011000000101x111111110111110 */
-{ "or", 0x26057fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "or", 0x26057fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* or<.f><.cc> ZA,LIMM,LIMMdup 0010011011000101x1111111100xxxxx */
-{ "or", 0x26c57f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "or", 0x26c57f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* orl<.f> RA,RB,RC 01011xxx00000101xxxxxxxxxxxxxxxx */
-{ "orl", 0x58050000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "orl", 0x58050000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* orl<.f> ZA,RB,RC 01011xxx00000101xxxxxxxxxx111110 */
-{ "orl", 0x5805003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "orl", 0x5805003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* orl<.f><.cc> RB,RBdup,RC 01011xxx11000101xxxxxxxxxx0xxxxx */
-{ "orl", 0x58c50000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "orl", 0x58c50000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* orl<.f> RA,RB,UIMM6_20 01011xxx01000101xxxxxxxxxxxxxxxx */
-{ "orl", 0x58450000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "orl", 0x58450000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* orl<.f> ZA,RB,UIMM6_20 01011xxx01000101xxxxxxxxxx111110 */
-{ "orl", 0x5845003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "orl", 0x5845003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* orl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11000101xxxxxxxxxx1xxxxx */
-{ "orl", 0x58c50020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "orl", 0x58c50020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* orl<.f> RB,RBdup,SIMM12_20 01011xxx10000101xxxxxxxxxxxxxxxx */
-{ "orl", 0x58850000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "orl", 0x58850000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* orl<.f> RA,XIMM,RC 0101110000000101x111xxxxxxxxxxxx */
-{ "orl", 0x5c057000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "orl", 0x5c057000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* orl<.f> RA,RB,XIMM 01011xxx00000101xxxx111100xxxxxx */
-{ "orl", 0x58050f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "orl", 0x58050f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* orl<.f> ZA,XIMM,RC 0101110000000101x111xxxxxx111110 */
-{ "orl", 0x5c05703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "orl", 0x5c05703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* orl<.f> ZA,RB,XIMM 01011xxx00000101xxxx111100111110 */
-{ "orl", 0x58050f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "orl", 0x58050f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* orl<.f><.cc> ZA,XIMM,RC 0101110011000101x111xxxxxx0xxxxx */
-{ "orl", 0x5cc57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "orl", 0x5cc57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* orl<.f><.cc> RB,RBdup,XIMM 01011xxx11000101xxxx1111000xxxxx */
-{ "orl", 0x58c50f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "orl", 0x58c50f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* orl<.f> RA,XIMM,UIMM6_20 0101110001000101x111xxxxxxxxxxxx */
-{ "orl", 0x5c457000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "orl", 0x5c457000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* orl<.f> ZA,XIMM,UIMM6_20 0101110001000101x111xxxxxx111110 */
-{ "orl", 0x5c45703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "orl", 0x5c45703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* orl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011000101x111xxxxxx1xxxxx */
-{ "orl", 0x5cc57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "orl", 0x5cc57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* orl<.f> RA,LIMM,RC 0101111000000101x111xxxxxxxxxxxx */
-{ "orl", 0x5e057000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "orl", 0x5e057000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* orl<.f> RA,RB,LO32 01011xxx00000101xxxx111110xxxxxx */
-{ "orl", 0x58050f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LO32 }, { C_F } }
+{ "orl", 0x58050f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LO32 }, { C_F } }
 
 /* orl<.f> RA,RB,LIMM 01011xxx00000101xxxx111110xxxxxx */
-{ "orl", 0x58050f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "orl", 0x58050f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* orl<.f> ZA,LIMM,RC 0101111000000101x111xxxxxx111110 */
-{ "orl", 0x5e05703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "orl", 0x5e05703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* orl<.f> ZA,RB,LIMM 01011xxx00000101xxxx111110111110 */
-{ "orl", 0x58050fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "orl", 0x58050fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* orl<.f><.cc> ZA,LIMM,RC 0101111011000101x111xxxxxx0xxxxx */
-{ "orl", 0x5ec57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "orl", 0x5ec57000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* orl<.f><.cc> RB,RBdup,LIMM 01011xxx11000101xxxx1111100xxxxx */
-{ "orl", 0x58c50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "orl", 0x58c50f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* orl<.f> RA,LIMM,UIMM6_20 0101111001000101x111xxxxxxxxxxxx */
-{ "orl", 0x5e457000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "orl", 0x5e457000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* orl<.f> ZA,LIMM,UIMM6_20 0101111001000101x111xxxxxx111110 */
-{ "orl", 0x5e45703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "orl", 0x5e45703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* orl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011000101x111xxxxxx1xxxxx */
-{ "orl", 0x5ec57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "orl", 0x5ec57020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* orl<.f> ZA,XIMM,SIMM12_20 0101110010000101x111xxxxxxxxxxxx */
-{ "orl", 0x5c857000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "orl", 0x5c857000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* orl<.f> ZA,LIMM,SIMM12_20 0101111010000101x111xxxxxxxxxxxx */
-{ "orl", 0x5e857000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "orl", 0x5e857000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* orl<.f> RA,XIMM,XIMMdup 0101110000000101x111111100xxxxxx */
-{ "orl", 0x5c057f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "orl", 0x5c057f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* orl<.f> ZA,XIMM,XIMMdup 0101110000000101x111111100111110 */
-{ "orl", 0x5c057f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "orl", 0x5c057f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* orl<.f><.cc> ZA,XIMM,XIMMdup 0101110011000101x1111111000xxxxx */
-{ "orl", 0x5cc57f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "orl", 0x5cc57f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* orl<.f> RA,LIMM,LIMMdup 0101111000000101x111111110xxxxxx */
-{ "orl", 0x5e057f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "orl", 0x5e057f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* orl<.f> ZA,LIMM,LIMMdup 0101111000000101x111111110111110 */
-{ "orl", 0x5e057fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "orl", 0x5e057fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* orl<.f><.cc> ZA,LIMM,LIMMdup 0101111011000101x1111111100xxxxx */
-{ "orl", 0x5ec57f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "orl", 0x5ec57f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* orl_s RB_S,RB_Sdup,RC_S 01111xxxxxx10111 */
-{ "orl_s", 0x00007817, 0x0000f81f, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "orl_s", 0x00007817, 0x0000f81f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* orl_s RH_S,RH_Sdup,LO32 01110000xxx110xx */
-{ "orl_s", 0x00007018, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, LO32 }, { 0 } }
+{ "orl_s", 0x00007018, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, RH_Sdup, LO32 }, { 0 } }
 
 /* orl_s RH_S,PCL_S,LO32 01110010xxx110xx */
-{ "orl_s", 0x00007218, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, LO32 }, { 0 } }
+{ "orl_s", 0x00007218, 0x0000ff1c, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RH_S, PCL_S, LO32 }, { 0 } }
 
 /* or_s RB_S,RB_Sdup,RC_S 01111xxxxxx00101 */
-{ "or_s", 0x00007805, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "or_s", 0x00007805, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* pop_s b 11000bbb11000001.  */
-{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, NONE, { RB_S }, { C_AA_AB }},
+{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, ARC_INSN_SUBCLASS_NONE, { RB_S }, { C_AA_AB }},
 
 /* pop_s BLINK 11000RRR11010001.  */
-{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, NONE, { BLINK_S }, { C_AA_AB }},
+{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, ARC_INSN_SUBCLASS_NONE, { BLINK_S }, { C_AA_AB }},
 
 /* popdl_s RBB_S 11000xxx1101xxx1 */
-{ "popdl_s", 0x0000c0d1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S_CHK }, { 0 } }
+{ "popdl_s", 0x0000c0d1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RBB_S_CHK }, { 0 } }
 
 /* popl_s RBB_S 11000xxx1100xxx1 */
-{ "popl_s", 0x0000c0c1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 } }
+{ "popl_s", 0x0000c0c1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RBB_S }, { 0 } }
 
 /* prealloc<.aa> BRAKET,RB,RC,BRAKETdup 00100xxxxx1100010xxxxxxxxx111110 */
-{ "prealloc", 0x2031003e, 0xf83f803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 } }
+{ "prealloc", 0x2031003e, 0xf83f803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 } }
 
 /* prealloc<.aa> BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxx0xx001111110 */
-{ "prealloc", 0x1000007e, 0xf80009ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 } }
+{ "prealloc", 0x1000007e, 0xf80009ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 } }
 
 /* prealloc<.aa> BRAKET,RB,LIMM,BRAKETdup 00100xxxxx1100010xxx111110111110 */
-{ "prealloc", 0x20310fbe, 0xf83f8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 } }
+{ "prealloc", 0x20310fbe, 0xf83f8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 } }
 
 /* prealloc BRAKET,LIMM,RC,BRAKETdup 00100110xx1100010111xxxxxx111110 */
-{ "prealloc", 0x2631703e, 0xff3ff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 } }
+{ "prealloc", 0x2631703e, 0xff3ff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 } }
 
 /* prealloc BRAKET,LIMM,BRAKETdup 000101100000000001110xx001111110 */
-{ "prealloc", 0x1600707e, 0xfffff9ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "prealloc", 0x1600707e, 0xfffff9ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* prealloc BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx1110xx001111110 */
-{ "prealloc", 0x1600707e, 0xff0079ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 } }
+{ "prealloc", 0x1600707e, 0xff0079ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 } }
 
 /* prefetch<.aa> BRAKET,RB,RC,BRAKETdup 00100xxxxx1100000xxxxxxxxx111110 */
-{ "prefetch", 0x2030003e, 0xf83f803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 } }
+{ "prefetch", 0x2030003e, 0xf83f803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 } }
 
 /* prefetch<.aa> BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxx0xx000111110 */
-{ "prefetch", 0x1000003e, 0xf80009ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 } }
+{ "prefetch", 0x1000003e, 0xf80009ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 } }
 
 /* prefetch<.aa> BRAKET,RB,LIMM,BRAKETdup 00100xxxxx1100000xxx111110111110 */
-{ "prefetch", 0x20300fbe, 0xf83f8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 } }
+{ "prefetch", 0x20300fbe, 0xf83f8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 } }
 
 /* prefetch BRAKET,LIMM,RC,BRAKETdup 00100110xx1100000111xxxxxx111110 */
-{ "prefetch", 0x2630703e, 0xff3ff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 } }
+{ "prefetch", 0x2630703e, 0xff3ff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 } }
 
 /* prefetch BRAKET,LIMM,BRAKETdup 000101100000000001110xx000111110 */
-{ "prefetch", 0x1600703e, 0xfffff9ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "prefetch", 0x1600703e, 0xfffff9ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* prefetch BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx1110xx000111110 */
-{ "prefetch", 0x1600703e, 0xff0079ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 } }
+{ "prefetch", 0x1600703e, 0xff0079ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 } }
 
 /* prefetchw<.aa> BRAKET,RB,RC,BRAKETdup 00100xxxxx1100001xxxxxxxxx111110 */
-{ "prefetchw", 0x2030803e, 0xf83f803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 } }
+{ "prefetchw", 0x2030803e, 0xf83f803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 } }
 
 /* prefetchw<.aa> BRAKET,RB,SIMM9_8,BRAKETdup 00010xxxxxxxxxxxxxxx1xx000111110 */
-{ "prefetchw", 0x1000083e, 0xf80009ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 } }
+{ "prefetchw", 0x1000083e, 0xf80009ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 } }
 
 /* prefetchw<.aa> BRAKET,RB,LIMM,BRAKETdup 00100xxxxx1100001xxx111110111110 */
-{ "prefetchw", 0x20308fbe, 0xf83f8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 } }
+{ "prefetchw", 0x20308fbe, 0xf83f8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 } }
 
 /* prefetchw BRAKET,LIMM,RC,BRAKETdup 00100110xx1100001111xxxxxx111110 */
-{ "prefetchw", 0x2630f03e, 0xff3ff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 } }
+{ "prefetchw", 0x2630f03e, 0xff3ff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 } }
 
 /* prefetchw BRAKET,LIMM,BRAKETdup 000101100000000001111xx000111110 */
-{ "prefetchw", 0x1600783e, 0xfffff9ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "prefetchw", 0x1600783e, 0xfffff9ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* prefetchw BRAKET,LIMM,SIMM9_8,BRAKETdup 00010110xxxxxxxxx1111xx000111110 */
-{ "prefetchw", 0x1600783e, 0xff0079ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 } }
+{ "prefetchw", 0x1600783e, 0xff0079ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MEMORY, ARC_INSN_SUBCLASS_NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 } }
 
 /* push_s b 11000bbb11100001.  */
-{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, NONE, { RB_S }, { C_AA_AW }},
+{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, ARC_INSN_SUBCLASS_NONE, { RB_S }, { C_AA_AW }},
 
 /* push_s blink 11000RRR11110001.  */
-{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, NONE, { BLINK_S }, { C_AA_AW }},
+{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, ARC_INSN_SUBCLASS_NONE, { BLINK_S }, { C_AA_AW }},
 
 /* pushdl_s RBB_S 11000xxx1111xxx1 */
-{ "pushdl_s", 0x0000c0f1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S_CHK }, { 0 } }
+{ "pushdl_s", 0x0000c0f1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RBB_S_CHK }, { 0 } }
 
 /* pushl_s RBB_S 11000xxx1110xxx1 */
-{ "pushl_s", 0x0000c0e1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 } }
+{ "pushl_s", 0x0000c0e1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RBB_S }, { 0 } }
 
 /* qmach<.f> RA_CHK,RB,RC 00101xxx00110100xxxxxxxxxxxxxxxx */
 { "qmach", 0x28340000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F } }
@@ -6839,82 +6839,82 @@
 { "qmpyhu", 0x2ef17f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* rcmp RB,RC 00100xxx000011011xxxxxxxxxxxxxxx */
-{ "rcmp", 0x200d8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { 0 } }
+{ "rcmp", 0x200d8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* rcmp<.cc> RB,RC 00100xxx110011011xxxxxxxxx0xxxxx */
-{ "rcmp", 0x20cd8000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_CC } }
+{ "rcmp", 0x20cd8000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* rcmp RB,UIMM6_20 00100xxx010011011xxxxxxxxxxxxxxx */
-{ "rcmp", 0x204d8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "rcmp", 0x204d8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* rcmp<.cc> RB,UIMM6_20 00100xxx110011011xxxxxxxxx1xxxxx */
-{ "rcmp", 0x20cd8020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "rcmp", 0x20cd8020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* rcmp RB,SIMM12_20 00100xxx100011011xxxxxxxxxxxxxxx */
-{ "rcmp", 0x208d8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "rcmp", 0x208d8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* rcmp LIMM,RC 00100110000011011111xxxxxxxxxxxx */
-{ "rcmp", 0x260df000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, RC }, { 0 } }
+{ "rcmp", 0x260df000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { 0 } }
 
 /* rcmp RB,LIMM 00100xxx000011011xxx111110xxxxxx */
-{ "rcmp", 0x200d8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { 0 } }
+{ "rcmp", 0x200d8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { 0 } }
 
 /* rcmp<.cc> LIMM,RC 00100110110011011111xxxxxx0xxxxx */
-{ "rcmp", 0x26cdf000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, RC }, { C_CC } }
+{ "rcmp", 0x26cdf000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { C_CC } }
 
 /* rcmp<.cc> RB,LIMM 00100xxx110011011xxx1111100xxxxx */
-{ "rcmp", 0x20cd8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_CC } }
+{ "rcmp", 0x20cd8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_CC } }
 
 /* rcmp LIMM,UIMM6_20 00100110010011011111xxxxxxxxxxxx */
-{ "rcmp", 0x264df000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 } }
+{ "rcmp", 0x264df000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { 0 } }
 
 /* rcmp<.cc> LIMM,UIMM6_20 00100110110011011111xxxxxx1xxxxx */
-{ "rcmp", 0x26cdf020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC } }
+{ "rcmp", 0x26cdf020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { C_CC } }
 
 /* rcmp LIMM,SIMM12_20 00100110100011011111xxxxxxxxxxxx */
-{ "rcmp", 0x268df000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 } }
+{ "rcmp", 0x268df000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, SIMM12_20 }, { 0 } }
 
 /* rcmp LIMM,LIMMdup 00100110000011011111111110xxxxxx */
-{ "rcmp", 0x260dff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, LIMMdup }, { 0 } }
+{ "rcmp", 0x260dff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup }, { 0 } }
 
 /* rcmp<.cc> LIMM,LIMMdup 001001101100110111111111100xxxxx */
-{ "rcmp", 0x26cdff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { LIMM, LIMMdup }, { C_CC } }
+{ "rcmp", 0x26cdff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup }, { C_CC } }
 
 /* rcmpl RB,RC 01011xxx000011011xxxxxxxxxxxxxxx */
-{ "rcmpl", 0x580d8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 } }
+{ "rcmpl", 0x580d8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* rcmpl<.cc> RB,RC 01011xxx110011011xxxxxxxxx0xxxxx */
-{ "rcmpl", 0x58cd8000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC } }
+{ "rcmpl", 0x58cd8000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* rcmpl RB,UIMM6_20 01011xxx010011011xxxxxxxxxxxxxxx */
-{ "rcmpl", 0x584d8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "rcmpl", 0x584d8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* rcmpl<.cc> RB,UIMM6_20 01011xxx110011011xxxxxxxxx1xxxxx */
-{ "rcmpl", 0x58cd8020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "rcmpl", 0x58cd8020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* rcmpl RB,SIMM12_20 01011xxx100011011xxxxxxxxxxxxxxx */
-{ "rcmpl", 0x588d8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "rcmpl", 0x588d8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* rcmpl XIMM,RC 01011100000011011111xxxxxxxxxxxx */
-{ "rcmpl", 0x5c0df000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 } }
+{ "rcmpl", 0x5c0df000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { XIMM, RC }, { 0 } }
 
 /* rcmpl RB,XIMM 01011xxx000011011xxx111100xxxxxx */
-{ "rcmpl", 0x580d8f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 } }
+{ "rcmpl", 0x580d8f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { 0 } }
 
 /* rcmpl<.cc> RB,XIMM 01011xxx110011011xxx1111000xxxxx */
-{ "rcmpl", 0x58cd8f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC } }
+{ "rcmpl", 0x58cd8f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_CC } }
 
 /* rcmpl LIMM,RC 01011110000011011111xxxxxxxxxxxx */
-{ "rcmpl", 0x5e0df000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 } }
+{ "rcmpl", 0x5e0df000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { 0 } }
 
 /* rcmpl RB,LIMM 01011xxx000011011xxx111110xxxxxx */
-{ "rcmpl", 0x580d8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 } }
+{ "rcmpl", 0x580d8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { 0 } }
 
 /* rcmpl<.cc> RB,LIMM 01011xxx110011011xxx1111100xxxxx */
-{ "rcmpl", 0x58cd8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC } }
+{ "rcmpl", 0x58cd8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_CC } }
 
 /* rcmpl LIMM,UIMM6_20 01011110010011011111xxxxxxxxxxxx */
-{ "rcmpl", 0x5e4df000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 } }
+{ "rcmpl", 0x5e4df000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { 0 } }
 
 /* rem<.f> RA_CHK,RB,RC 00101xxx00001000xxxxxxxxxxxxxxxx */
 { "rem", 0x28080000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F } }
@@ -6977,103 +6977,103 @@
 { "rem", 0x2ec87f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* reml<.f> RA,RB,RC 01011xxx00101000xxxxxxxxxxxxxxxx */
-{ "reml", 0x58280000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "reml", 0x58280000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* reml<.f> ZA,RB,RC 01011xxx00101000xxxxxxxxxx111110 */
-{ "reml", 0x5828003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "reml", 0x5828003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* reml<.f><.cc> RB,RBdup,RC 01011xxx11101000xxxxxxxxxx0xxxxx */
-{ "reml", 0x58e80000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "reml", 0x58e80000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* reml<.f> RA,RB,UIMM6_20 01011xxx01101000xxxxxxxxxxxxxxxx */
-{ "reml", 0x58680000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "reml", 0x58680000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* reml<.f> ZA,RB,UIMM6_20 01011xxx01101000xxxxxxxxxx111110 */
-{ "reml", 0x5868003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "reml", 0x5868003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* reml<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11101000xxxxxxxxxx1xxxxx */
-{ "reml", 0x58e80020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "reml", 0x58e80020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* reml<.f> RB,RBdup,SIMM12_20 01011xxx10101000xxxxxxxxxxxxxxxx */
-{ "reml", 0x58a80000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "reml", 0x58a80000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* reml<.f> RA,XIMM,RC 0101110000101000x111xxxxxxxxxxxx */
-{ "reml", 0x5c287000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "reml", 0x5c287000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* reml<.f> RA,RB,XIMM 01011xxx00101000xxxx111100xxxxxx */
-{ "reml", 0x58280f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "reml", 0x58280f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* reml<.f> ZA,XIMM,RC 0101110000101000x111xxxxxx111110 */
-{ "reml", 0x5c28703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "reml", 0x5c28703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* reml<.f> ZA,RB,XIMM 01011xxx00101000xxxx111100111110 */
-{ "reml", 0x58280f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "reml", 0x58280f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* reml<.f><.cc> ZA,XIMM,RC 0101110011101000x111xxxxxx0xxxxx */
-{ "reml", 0x5ce87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "reml", 0x5ce87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* reml<.f><.cc> RB,RBdup,XIMM 01011xxx11101000xxxx1111000xxxxx */
-{ "reml", 0x58e80f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "reml", 0x58e80f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* reml<.f> RA,XIMM,UIMM6_20 0101110001101000x111xxxxxxxxxxxx */
-{ "reml", 0x5c687000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "reml", 0x5c687000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* reml<.f> ZA,XIMM,UIMM6_20 0101110001101000x111xxxxxx111110 */
-{ "reml", 0x5c68703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "reml", 0x5c68703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* reml<.f><.cc> ZA,XIMM,UIMM6_20 0101110011101000x111xxxxxx1xxxxx */
-{ "reml", 0x5ce87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "reml", 0x5ce87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* reml<.f> RA,LIMM,RC 0101111000101000x111xxxxxxxxxxxx */
-{ "reml", 0x5e287000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "reml", 0x5e287000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* reml<.f> RA,RB,LIMM 01011xxx00101000xxxx111110xxxxxx */
-{ "reml", 0x58280f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "reml", 0x58280f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* reml<.f> ZA,LIMM,RC 0101111000101000x111xxxxxx111110 */
-{ "reml", 0x5e28703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "reml", 0x5e28703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* reml<.f> ZA,RB,LIMM 01011xxx00101000xxxx111110111110 */
-{ "reml", 0x58280fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "reml", 0x58280fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* reml<.f><.cc> ZA,LIMM,RC 0101111011101000x111xxxxxx0xxxxx */
-{ "reml", 0x5ee87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "reml", 0x5ee87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* reml<.f><.cc> RB,RBdup,LIMM 01011xxx11101000xxxx1111100xxxxx */
-{ "reml", 0x58e80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "reml", 0x58e80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* reml<.f> RA,LIMM,UIMM6_20 0101111001101000x111xxxxxxxxxxxx */
-{ "reml", 0x5e687000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "reml", 0x5e687000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* reml<.f> ZA,LIMM,UIMM6_20 0101111001101000x111xxxxxx111110 */
-{ "reml", 0x5e68703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "reml", 0x5e68703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* reml<.f><.cc> ZA,LIMM,UIMM6_20 0101111011101000x111xxxxxx1xxxxx */
-{ "reml", 0x5ee87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "reml", 0x5ee87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* reml<.f> ZA,XIMM,SIMM12_20 0101110010101000x111xxxxxxxxxxxx */
-{ "reml", 0x5ca87000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "reml", 0x5ca87000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* reml<.f> ZA,LIMM,SIMM12_20 0101111010101000x111xxxxxxxxxxxx */
-{ "reml", 0x5ea87000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "reml", 0x5ea87000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* reml<.f> RA,XIMM,XIMMdup 0101110000101000x111111100xxxxxx */
-{ "reml", 0x5c287f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "reml", 0x5c287f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* reml<.f> ZA,XIMM,XIMMdup 0101110000101000x111111100111110 */
-{ "reml", 0x5c287f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "reml", 0x5c287f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* reml<.f><.cc> ZA,XIMM,XIMMdup 0101110011101000x1111111000xxxxx */
-{ "reml", 0x5ce87f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "reml", 0x5ce87f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* reml<.f> RA,LIMM,LIMMdup 0101111000101000x111111110xxxxxx */
-{ "reml", 0x5e287f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "reml", 0x5e287f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* reml<.f> ZA,LIMM,LIMMdup 0101111000101000x111111110111110 */
-{ "reml", 0x5e287fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "reml", 0x5e287fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* reml<.f><.cc> ZA,LIMM,LIMMdup 0101111011101000x1111111100xxxxx */
-{ "reml", 0x5ee87f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "reml", 0x5ee87f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* remu<.f> RA_CHK,RB,RC 00101xxx00001001xxxxxxxxxxxxxxxx */
 { "remu", 0x28090000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F } }
@@ -7136,139 +7136,139 @@
 { "remu", 0x2ec97f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* remul<.f> RA,RB,RC 01011xxx00101001xxxxxxxxxxxxxxxx */
-{ "remul", 0x58290000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "remul", 0x58290000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* remul<.f> ZA,RB,RC 01011xxx00101001xxxxxxxxxx111110 */
-{ "remul", 0x5829003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "remul", 0x5829003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* remul<.f><.cc> RB,RBdup,RC 01011xxx11101001xxxxxxxxxx0xxxxx */
-{ "remul", 0x58e90000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "remul", 0x58e90000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* remul<.f> RA,RB,UIMM6_20 01011xxx01101001xxxxxxxxxxxxxxxx */
-{ "remul", 0x58690000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "remul", 0x58690000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* remul<.f> ZA,RB,UIMM6_20 01011xxx01101001xxxxxxxxxx111110 */
-{ "remul", 0x5869003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "remul", 0x5869003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* remul<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11101001xxxxxxxxxx1xxxxx */
-{ "remul", 0x58e90020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "remul", 0x58e90020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* remul<.f> RB,RBdup,SIMM12_20 01011xxx10101001xxxxxxxxxxxxxxxx */
-{ "remul", 0x58a90000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "remul", 0x58a90000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* remul<.f> RA,XIMM,RC 0101110000101001x111xxxxxxxxxxxx */
-{ "remul", 0x5c297000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "remul", 0x5c297000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* remul<.f> RA,RB,XIMM 01011xxx00101001xxxx111100xxxxxx */
-{ "remul", 0x58290f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "remul", 0x58290f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* remul<.f> ZA,XIMM,RC 0101110000101001x111xxxxxx111110 */
-{ "remul", 0x5c29703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "remul", 0x5c29703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* remul<.f> ZA,RB,XIMM 01011xxx00101001xxxx111100111110 */
-{ "remul", 0x58290f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "remul", 0x58290f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* remul<.f><.cc> ZA,XIMM,RC 0101110011101001x111xxxxxx0xxxxx */
-{ "remul", 0x5ce97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "remul", 0x5ce97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* remul<.f><.cc> RB,RBdup,XIMM 01011xxx11101001xxxx1111000xxxxx */
-{ "remul", 0x58e90f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "remul", 0x58e90f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* remul<.f> RA,XIMM,UIMM6_20 0101110001101001x111xxxxxxxxxxxx */
-{ "remul", 0x5c697000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "remul", 0x5c697000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* remul<.f> ZA,XIMM,UIMM6_20 0101110001101001x111xxxxxx111110 */
-{ "remul", 0x5c69703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "remul", 0x5c69703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* remul<.f><.cc> ZA,XIMM,UIMM6_20 0101110011101001x111xxxxxx1xxxxx */
-{ "remul", 0x5ce97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "remul", 0x5ce97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* remul<.f> RA,LIMM,RC 0101111000101001x111xxxxxxxxxxxx */
-{ "remul", 0x5e297000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "remul", 0x5e297000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* remul<.f> RA,RB,LIMM 01011xxx00101001xxxx111110xxxxxx */
-{ "remul", 0x58290f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "remul", 0x58290f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* remul<.f> ZA,LIMM,RC 0101111000101001x111xxxxxx111110 */
-{ "remul", 0x5e29703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "remul", 0x5e29703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* remul<.f> ZA,RB,LIMM 01011xxx00101001xxxx111110111110 */
-{ "remul", 0x58290fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "remul", 0x58290fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* remul<.f><.cc> ZA,LIMM,RC 0101111011101001x111xxxxxx0xxxxx */
-{ "remul", 0x5ee97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "remul", 0x5ee97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* remul<.f><.cc> RB,RBdup,LIMM 01011xxx11101001xxxx1111100xxxxx */
-{ "remul", 0x58e90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "remul", 0x58e90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* remul<.f> RA,LIMM,UIMM6_20 0101111001101001x111xxxxxxxxxxxx */
-{ "remul", 0x5e697000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "remul", 0x5e697000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* remul<.f> ZA,LIMM,UIMM6_20 0101111001101001x111xxxxxx111110 */
-{ "remul", 0x5e69703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "remul", 0x5e69703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* remul<.f><.cc> ZA,LIMM,UIMM6_20 0101111011101001x111xxxxxx1xxxxx */
-{ "remul", 0x5ee97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "remul", 0x5ee97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* remul<.f> ZA,XIMM,SIMM12_20 0101110010101001x111xxxxxxxxxxxx */
-{ "remul", 0x5ca97000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "remul", 0x5ca97000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* remul<.f> ZA,LIMM,SIMM12_20 0101111010101001x111xxxxxxxxxxxx */
-{ "remul", 0x5ea97000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "remul", 0x5ea97000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* remul<.f> RA,XIMM,XIMMdup 0101110000101001x111111100xxxxxx */
-{ "remul", 0x5c297f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "remul", 0x5c297f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* remul<.f> ZA,XIMM,XIMMdup 0101110000101001x111111100111110 */
-{ "remul", 0x5c297f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "remul", 0x5c297f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* remul<.f><.cc> ZA,XIMM,XIMMdup 0101110011101001x1111111000xxxxx */
-{ "remul", 0x5ce97f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "remul", 0x5ce97f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* remul<.f> RA,LIMM,LIMMdup 0101111000101001x111111110xxxxxx */
-{ "remul", 0x5e297f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "remul", 0x5e297f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* remul<.f> ZA,LIMM,LIMMdup 0101111000101001x111111110111110 */
-{ "remul", 0x5e297fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "remul", 0x5e297fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* remul<.f><.cc> ZA,LIMM,LIMMdup 0101111011101001x1111111100xxxxx */
-{ "remul", 0x5ee97f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "remul", 0x5ee97f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* rlc<.f> RB,RC 00100xxx00101111xxxxxxxxxx001011 */
-{ "rlc", 0x202f000b, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_F } }
+{ "rlc", 0x202f000b, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* rlc<.f> ZA,RC 0010011000101111x111xxxxxx001011 */
-{ "rlc", 0x262f700b, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RC }, { C_F } }
+{ "rlc", 0x262f700b, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* rlc<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx001011 */
-{ "rlc", 0x206f000b, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "rlc", 0x206f000b, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* rlc<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx001011 */
-{ "rlc", 0x266f700b, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "rlc", 0x266f700b, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* rlc<.f> RB,LIMM 00100xxx00101111xxxx111110001011 */
-{ "rlc", 0x202f0f8b, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_F } }
+{ "rlc", 0x202f0f8b, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* rlc<.f> ZA,LIMM 0010011000101111x111111110001011 */
-{ "rlc", 0x262f7f8b, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM }, { C_F } }
+{ "rlc", 0x262f7f8b, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* rol<.f> RB,RC 00100xxx00101111xxxxxxxxxx001101 */
-{ "rol", 0x202f000d, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_F } }
+{ "rol", 0x202f000d, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* rol<.f> ZA,RC 0010011000101111x111xxxxxx001101 */
-{ "rol", 0x262f700d, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RC }, { C_F } }
+{ "rol", 0x262f700d, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* rol<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx001101 */
-{ "rol", 0x206f000d, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "rol", 0x206f000d, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* rol<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx001101 */
-{ "rol", 0x266f700d, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "rol", 0x266f700d, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* rol<.f> RB,LIMM 00100xxx00101111xxxx111110001101 */
-{ "rol", 0x202f0f8d, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_F } }
+{ "rol", 0x202f0f8d, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* rol<.f> ZA,LIMM 0010011000101111x111111110001101 */
-{ "rol", 0x262f7f8d, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM }, { C_F } }
+{ "rol", 0x262f7f8d, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* rol8<.f> RB,RC 00101xxx00101111xxxxxxxxxx010000 */
 { "rol8", 0x282f0010, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT1, { RB, RC }, { C_F } }
@@ -7289,10 +7289,10 @@
 { "rol8", 0x2e2f7f90, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT1, { ZA, LIMM }, { C_F } }
 
 /* ror<.f> RB,RC 00100xxx00101111xxxxxxxxxx000011 */
-{ "ror", 0x202f0003, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_F } }
+{ "ror", 0x202f0003, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* ror<.f> ZA,RC 0010011000101111x111xxxxxx000011 */
-{ "ror", 0x262f7003, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RC }, { C_F } }
+{ "ror", 0x262f7003, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* ror<.f> RA,RB,RC 00101xxx00000011xxxxxxxxxxxxxxxx */
 { "ror", 0x28030000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, RB, RC }, { C_F } }
@@ -7304,10 +7304,10 @@
 { "ror", 0x28c30000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* ror<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx000011 */
-{ "ror", 0x206f0003, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "ror", 0x206f0003, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* ror<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx000011 */
-{ "ror", 0x266f7003, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "ror", 0x266f7003, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* ror<.f> RA,RB,UIMM6_20 00101xxx01000011xxxxxxxxxxxxxxxx */
 { "ror", 0x28430000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F } }
@@ -7322,10 +7322,10 @@
 { "ror", 0x28830000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* ror<.f> RB,LIMM 00100xxx00101111xxxx111110000011 */
-{ "ror", 0x202f0f83, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_F } }
+{ "ror", 0x202f0f83, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* ror<.f> ZA,LIMM 0010011000101111x111111110000011 */
-{ "ror", 0x262f7f83, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM }, { C_F } }
+{ "ror", 0x262f7f83, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* ror<.f> RA,LIMM,RC 0010111000000011x111xxxxxxxxxxxx */
 { "ror", 0x2e037000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F } }
@@ -7385,2545 +7385,2545 @@
 { "ror8", 0x2e2f7f91, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, SHFT1, { ZA, LIMM }, { C_F } }
 
 /* rrc<.f> RB,RC 00100xxx00101111xxxxxxxxxx000100 */
-{ "rrc", 0x202f0004, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_F } }
+{ "rrc", 0x202f0004, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* rrc<.f> ZA,RC 0010011000101111x111xxxxxx000100 */
-{ "rrc", 0x262f7004, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RC }, { C_F } }
+{ "rrc", 0x262f7004, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* rrc<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx000100 */
-{ "rrc", 0x206f0004, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "rrc", 0x206f0004, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* rrc<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx000100 */
-{ "rrc", 0x266f7004, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "rrc", 0x266f7004, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* rrc<.f> RB,LIMM 00100xxx00101111xxxx111110000100 */
-{ "rrc", 0x202f0f84, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_F } }
+{ "rrc", 0x202f0f84, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* rrc<.f> ZA,LIMM 0010011000101111x111111110000100 */
-{ "rrc", 0x262f7f84, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM }, { C_F } }
+{ "rrc", 0x262f7f84, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* rsub<.f> RA,RB,RC 00100xxx00001110xxxxxxxxxxxxxxxx */
-{ "rsub", 0x200e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "rsub", 0x200e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* rsub<.f> ZA,RB,RC 00100xxx00001110xxxxxxxxxx111110 */
-{ "rsub", 0x200e003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "rsub", 0x200e003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* rsub<.f><.cc> RB,RBdup,RC 00100xxx11001110xxxxxxxxxx0xxxxx */
-{ "rsub", 0x20ce0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "rsub", 0x20ce0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* rsub<.f> RA,RB,UIMM6_20 00100xxx01001110xxxxxxxxxxxxxxxx */
-{ "rsub", 0x204e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "rsub", 0x204e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* rsub<.f> ZA,RB,UIMM6_20 00100xxx01001110xxxxxxxxxx111110 */
-{ "rsub", 0x204e003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "rsub", 0x204e003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* rsub<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11001110xxxxxxxxxx1xxxxx */
-{ "rsub", 0x20ce0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "rsub", 0x20ce0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* rsub<.f> RB,RBdup,SIMM12_20 00100xxx10001110xxxxxxxxxxxxxxxx */
-{ "rsub", 0x208e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "rsub", 0x208e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* rsub<.f> RA,LIMM,RC 0010011000001110x111xxxxxxxxxxxx */
-{ "rsub", 0x260e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "rsub", 0x260e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* rsub<.f> RA,RB,LIMM 00100xxx00001110xxxx111110xxxxxx */
-{ "rsub", 0x200e0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "rsub", 0x200e0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* rsub<.f> ZA,LIMM,RC 0010011000001110x111xxxxxx111110 */
-{ "rsub", 0x260e703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "rsub", 0x260e703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* rsub<.f> ZA,RB,LIMM 00100xxx00001110xxxx111110111110 */
-{ "rsub", 0x200e0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "rsub", 0x200e0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* rsub<.f><.cc> RB,RBdup,LIMM 00100xxx11001110xxxx1111100xxxxx */
-{ "rsub", 0x20ce0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "rsub", 0x20ce0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* rsub<.f><.cc> ZA,LIMM,RC 0010011011001110x111xxxxxx0xxxxx */
-{ "rsub", 0x26ce7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "rsub", 0x26ce7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* rsub<.f> RA,LIMM,UIMM6_20 0010011001001110x111xxxxxxxxxxxx */
-{ "rsub", 0x264e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "rsub", 0x264e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* rsub<.f> ZA,LIMM,UIMM6_20 0010011001001110x111xxxxxx111110 */
-{ "rsub", 0x264e703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "rsub", 0x264e703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* rsub<.f><.cc> ZA,LIMM,UIMM6_20 0010011011001110x111xxxxxx1xxxxx */
-{ "rsub", 0x26ce7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "rsub", 0x26ce7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* rsub<.f> ZA,LIMM,SIMM12_20 0010011010001110x111xxxxxxxxxxxx */
-{ "rsub", 0x268e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "rsub", 0x268e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* rsub<.f> RA,LIMM,LIMMdup 0010011000001110x111111110xxxxxx */
-{ "rsub", 0x260e7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "rsub", 0x260e7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* rsub<.f> ZA,LIMM,LIMMdup 0010011000001110x111111110111110 */
-{ "rsub", 0x260e7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "rsub", 0x260e7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* rsub<.f><.cc> ZA,LIMM,LIMMdup 0010011011001110x1111111100xxxxx */
-{ "rsub", 0x26ce7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "rsub", 0x26ce7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* rsubl<.f> RA,RB,RC 01011xxx00001110xxxxxxxxxxxxxxxx */
-{ "rsubl", 0x580e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "rsubl", 0x580e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* rsubl<.f> ZA,RB,RC 01011xxx00001110xxxxxxxxxx111110 */
-{ "rsubl", 0x580e003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "rsubl", 0x580e003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* rsubl<.f><.cc> RB,RBdup,RC 01011xxx11001110xxxxxxxxxx0xxxxx */
-{ "rsubl", 0x58ce0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "rsubl", 0x58ce0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* rsubl<.f> RA,RB,UIMM6_20 01011xxx01001110xxxxxxxxxxxxxxxx */
-{ "rsubl", 0x584e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "rsubl", 0x584e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* rsubl<.f> ZA,RB,UIMM6_20 01011xxx01001110xxxxxxxxxx111110 */
-{ "rsubl", 0x584e003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "rsubl", 0x584e003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* rsubl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11001110xxxxxxxxxx1xxxxx */
-{ "rsubl", 0x58ce0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "rsubl", 0x58ce0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* rsubl<.f> RB,RBdup,SIMM12_20 01011xxx10001110xxxxxxxxxxxxxxxx */
-{ "rsubl", 0x588e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "rsubl", 0x588e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* rsubl<.f> RA,XIMM,RC 0101110000001110x111xxxxxxxxxxxx */
-{ "rsubl", 0x5c0e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "rsubl", 0x5c0e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* rsubl<.f> RA,RB,XIMM 01011xxx00001110xxxx111100xxxxxx */
-{ "rsubl", 0x580e0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "rsubl", 0x580e0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* rsubl<.f> ZA,XIMM,RC 0101110000001110x111xxxxxx111110 */
-{ "rsubl", 0x5c0e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "rsubl", 0x5c0e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* rsubl<.f> ZA,RB,XIMM 01011xxx00001110xxxx111100111110 */
-{ "rsubl", 0x580e0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "rsubl", 0x580e0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* rsubl<.f><.cc> ZA,XIMM,RC 0101110011001110x111xxxxxx0xxxxx */
-{ "rsubl", 0x5cce7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "rsubl", 0x5cce7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* rsubl<.f><.cc> RB,RBdup,XIMM 01011xxx11001110xxxx1111000xxxxx */
-{ "rsubl", 0x58ce0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "rsubl", 0x58ce0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* rsubl<.f> RA,XIMM,UIMM6_20 0101110001001110x111xxxxxxxxxxxx */
-{ "rsubl", 0x5c4e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "rsubl", 0x5c4e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* rsubl<.f> ZA,XIMM,UIMM6_20 0101110001001110x111xxxxxx111110 */
-{ "rsubl", 0x5c4e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "rsubl", 0x5c4e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* rsubl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011001110x111xxxxxx1xxxxx */
-{ "rsubl", 0x5cce7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "rsubl", 0x5cce7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* rsubl<.f> RA,LIMM,RC 0101111000001110x111xxxxxxxxxxxx */
-{ "rsubl", 0x5e0e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "rsubl", 0x5e0e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* rsubl<.f> RA,RB,LIMM 01011xxx00001110xxxx111110xxxxxx */
-{ "rsubl", 0x580e0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "rsubl", 0x580e0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* rsubl<.f> ZA,LIMM,RC 0101111000001110x111xxxxxx111110 */
-{ "rsubl", 0x5e0e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "rsubl", 0x5e0e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* rsubl<.f> ZA,RB,LIMM 01011xxx00001110xxxx111110111110 */
-{ "rsubl", 0x580e0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "rsubl", 0x580e0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* rsubl<.f><.cc> ZA,LIMM,RC 0101111011001110x111xxxxxx0xxxxx */
-{ "rsubl", 0x5ece7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "rsubl", 0x5ece7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* rsubl<.f><.cc> RB,RBdup,LIMM 01011xxx11001110xxxx1111100xxxxx */
-{ "rsubl", 0x58ce0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "rsubl", 0x58ce0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* rsubl<.f> RA,LIMM,UIMM6_20 0101111001001110x111xxxxxxxxxxxx */
-{ "rsubl", 0x5e4e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "rsubl", 0x5e4e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* rsubl<.f> ZA,LIMM,UIMM6_20 0101111001001110x111xxxxxx111110 */
-{ "rsubl", 0x5e4e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "rsubl", 0x5e4e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* rsubl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011001110x111xxxxxx1xxxxx */
-{ "rsubl", 0x5ece7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "rsubl", 0x5ece7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* rsubl<.f> ZA,XIMM,SIMM12_20 0101110010001110x111xxxxxxxxxxxx */
-{ "rsubl", 0x5c8e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "rsubl", 0x5c8e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* rsubl<.f> ZA,LIMM,SIMM12_20 0101111010001110x111xxxxxxxxxxxx */
-{ "rsubl", 0x5e8e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "rsubl", 0x5e8e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* rsubl<.f> RA,XIMM,XIMMdup 0101110000001110x111111100xxxxxx */
-{ "rsubl", 0x5c0e7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "rsubl", 0x5c0e7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* rsubl<.f> ZA,XIMM,XIMMdup 0101110000001110x111111100111110 */
-{ "rsubl", 0x5c0e7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "rsubl", 0x5c0e7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* rsubl<.f><.cc> ZA,XIMM,XIMMdup 0101110011001110x1111111000xxxxx */
-{ "rsubl", 0x5cce7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "rsubl", 0x5cce7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* rsubl<.f> RA,LIMM,LIMMdup 0101111000001110x111111110xxxxxx */
-{ "rsubl", 0x5e0e7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "rsubl", 0x5e0e7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* rsubl<.f> ZA,LIMM,LIMMdup 0101111000001110x111111110111110 */
-{ "rsubl", 0x5e0e7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "rsubl", 0x5e0e7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* rsubl<.f><.cc> ZA,LIMM,LIMMdup 0101111011001110x1111111100xxxxx */
-{ "rsubl", 0x5ece7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "rsubl", 0x5ece7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* rtie  00100100011011110000000000111111 */
-{ "rtie", 0x246f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, {  }, { 0 } }
+{ "rtie", 0x246f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* sbc<.f> RA,RB,RC 00100xxx00000011xxxxxxxxxxxxxxxx */
-{ "sbc", 0x20030000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "sbc", 0x20030000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sbc<.f> ZA,RB,RC 00100xxx00000011xxxxxxxxxx111110 */
-{ "sbc", 0x2003003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "sbc", 0x2003003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sbc<.f><.cc> RB,RBdup,RC 00100xxx11000011xxxxxxxxxx0xxxxx */
-{ "sbc", 0x20c30000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sbc", 0x20c30000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sbc<.f> RA,RB,UIMM6_20 00100xxx01000011xxxxxxxxxxxxxxxx */
-{ "sbc", 0x20430000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sbc", 0x20430000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sbc<.f> ZA,RB,UIMM6_20 00100xxx01000011xxxxxxxxxx111110 */
-{ "sbc", 0x2043003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sbc", 0x2043003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sbc<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11000011xxxxxxxxxx1xxxxx */
-{ "sbc", 0x20c30020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sbc", 0x20c30020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sbc<.f> RB,RBdup,SIMM12_20 00100xxx10000011xxxxxxxxxxxxxxxx */
-{ "sbc", 0x20830000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sbc", 0x20830000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sbc<.f> RA,LIMM,RC 0010011000000011x111xxxxxxxxxxxx */
-{ "sbc", 0x26037000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sbc", 0x26037000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sbc<.f> RA,RB,LIMM 00100xxx00000011xxxx111110xxxxxx */
-{ "sbc", 0x20030f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sbc", 0x20030f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sbc<.f> ZA,LIMM,RC 0010011000000011x111xxxxxx111110 */
-{ "sbc", 0x2603703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sbc", 0x2603703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sbc<.f> ZA,RB,LIMM 00100xxx00000011xxxx111110111110 */
-{ "sbc", 0x20030fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sbc", 0x20030fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sbc<.f><.cc> RB,RBdup,LIMM 00100xxx11000011xxxx1111100xxxxx */
-{ "sbc", 0x20c30f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sbc", 0x20c30f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sbc<.f><.cc> ZA,LIMM,RC 0010011011000011x111xxxxxx0xxxxx */
-{ "sbc", 0x26c37000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sbc", 0x26c37000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sbc<.f> RA,LIMM,UIMM6_20 0010011001000011x111xxxxxxxxxxxx */
-{ "sbc", 0x26437000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sbc", 0x26437000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sbc<.f> ZA,LIMM,UIMM6_20 0010011001000011x111xxxxxx111110 */
-{ "sbc", 0x2643703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sbc", 0x2643703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sbc<.f><.cc> ZA,LIMM,UIMM6_20 0010011011000011x111xxxxxx1xxxxx */
-{ "sbc", 0x26c37020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sbc", 0x26c37020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sbc<.f> ZA,LIMM,SIMM12_20 0010011010000011x111xxxxxxxxxxxx */
-{ "sbc", 0x26837000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sbc", 0x26837000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sbc<.f> RA,LIMM,LIMMdup 0010011000000011x111111110xxxxxx */
-{ "sbc", 0x26037f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sbc", 0x26037f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sbc<.f> ZA,LIMM,LIMMdup 0010011000000011x111111110111110 */
-{ "sbc", 0x26037fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sbc", 0x26037fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sbc<.f><.cc> ZA,LIMM,LIMMdup 0010011011000011x1111111100xxxxx */
-{ "sbc", 0x26c37f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sbc", 0x26c37f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sbcl<.f> RA,RB,RC 01011xxx00000011xxxxxxxxxxxxxxxx */
-{ "sbcl", 0x58030000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "sbcl", 0x58030000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sbcl<.f> ZA,RB,RC 01011xxx00000011xxxxxxxxxx111110 */
-{ "sbcl", 0x5803003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "sbcl", 0x5803003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sbcl<.f><.cc> RB,RBdup,RC 01011xxx11000011xxxxxxxxxx0xxxxx */
-{ "sbcl", 0x58c30000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sbcl", 0x58c30000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sbcl<.f> RA,RB,UIMM6_20 01011xxx01000011xxxxxxxxxxxxxxxx */
-{ "sbcl", 0x58430000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sbcl", 0x58430000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sbcl<.f> ZA,RB,UIMM6_20 01011xxx01000011xxxxxxxxxx111110 */
-{ "sbcl", 0x5843003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sbcl", 0x5843003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sbcl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11000011xxxxxxxxxx1xxxxx */
-{ "sbcl", 0x58c30020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sbcl", 0x58c30020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sbcl<.f> RB,RBdup,SIMM12_20 01011xxx10000011xxxxxxxxxxxxxxxx */
-{ "sbcl", 0x58830000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sbcl", 0x58830000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sbcl<.f> RA,XIMM,RC 0101110000000011x111xxxxxxxxxxxx */
-{ "sbcl", 0x5c037000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "sbcl", 0x5c037000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* sbcl<.f> RA,RB,XIMM 01011xxx00000011xxxx111100xxxxxx */
-{ "sbcl", 0x58030f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "sbcl", 0x58030f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* sbcl<.f> ZA,XIMM,RC 0101110000000011x111xxxxxx111110 */
-{ "sbcl", 0x5c03703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "sbcl", 0x5c03703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* sbcl<.f> ZA,RB,XIMM 01011xxx00000011xxxx111100111110 */
-{ "sbcl", 0x58030f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "sbcl", 0x58030f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* sbcl<.f><.cc> ZA,XIMM,RC 0101110011000011x111xxxxxx0xxxxx */
-{ "sbcl", 0x5cc37000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "sbcl", 0x5cc37000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* sbcl<.f><.cc> RB,RBdup,XIMM 01011xxx11000011xxxx1111000xxxxx */
-{ "sbcl", 0x58c30f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "sbcl", 0x58c30f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* sbcl<.f> RA,XIMM,UIMM6_20 0101110001000011x111xxxxxxxxxxxx */
-{ "sbcl", 0x5c437000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "sbcl", 0x5c437000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sbcl<.f> ZA,XIMM,UIMM6_20 0101110001000011x111xxxxxx111110 */
-{ "sbcl", 0x5c43703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "sbcl", 0x5c43703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sbcl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011000011x111xxxxxx1xxxxx */
-{ "sbcl", 0x5cc37020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sbcl", 0x5cc37020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sbcl<.f> RA,LIMM,RC 0101111000000011x111xxxxxxxxxxxx */
-{ "sbcl", 0x5e037000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sbcl", 0x5e037000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sbcl<.f> RA,RB,LIMM 01011xxx00000011xxxx111110xxxxxx */
-{ "sbcl", 0x58030f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sbcl", 0x58030f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sbcl<.f> ZA,LIMM,RC 0101111000000011x111xxxxxx111110 */
-{ "sbcl", 0x5e03703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sbcl", 0x5e03703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sbcl<.f> ZA,RB,LIMM 01011xxx00000011xxxx111110111110 */
-{ "sbcl", 0x58030fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sbcl", 0x58030fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sbcl<.f><.cc> ZA,LIMM,RC 0101111011000011x111xxxxxx0xxxxx */
-{ "sbcl", 0x5ec37000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sbcl", 0x5ec37000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sbcl<.f><.cc> RB,RBdup,LIMM 01011xxx11000011xxxx1111100xxxxx */
-{ "sbcl", 0x58c30f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sbcl", 0x58c30f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sbcl<.f> RA,LIMM,UIMM6_20 0101111001000011x111xxxxxxxxxxxx */
-{ "sbcl", 0x5e437000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sbcl", 0x5e437000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sbcl<.f> ZA,LIMM,UIMM6_20 0101111001000011x111xxxxxx111110 */
-{ "sbcl", 0x5e43703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sbcl", 0x5e43703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sbcl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011000011x111xxxxxx1xxxxx */
-{ "sbcl", 0x5ec37020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sbcl", 0x5ec37020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sbcl<.f> ZA,XIMM,SIMM12_20 0101110010000011x111xxxxxxxxxxxx */
-{ "sbcl", 0x5c837000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "sbcl", 0x5c837000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* sbcl<.f> ZA,LIMM,SIMM12_20 0101111010000011x111xxxxxxxxxxxx */
-{ "sbcl", 0x5e837000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sbcl", 0x5e837000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sbcl<.f> RA,XIMM,XIMMdup 0101110000000011x111111100xxxxxx */
-{ "sbcl", 0x5c037f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "sbcl", 0x5c037f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* sbcl<.f> ZA,XIMM,XIMMdup 0101110000000011x111111100111110 */
-{ "sbcl", 0x5c037f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "sbcl", 0x5c037f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* sbcl<.f><.cc> ZA,XIMM,XIMMdup 0101110011000011x1111111000xxxxx */
-{ "sbcl", 0x5cc37f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "sbcl", 0x5cc37f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* sbcl<.f> RA,LIMM,LIMMdup 0101111000000011x111111110xxxxxx */
-{ "sbcl", 0x5e037f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sbcl", 0x5e037f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sbcl<.f> ZA,LIMM,LIMMdup 0101111000000011x111111110111110 */
-{ "sbcl", 0x5e037fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sbcl", 0x5e037fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sbcl<.f><.cc> ZA,LIMM,LIMMdup 0101111011000011x1111111100xxxxx */
-{ "sbcl", 0x5ec37f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sbcl", 0x5ec37f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* scond<.di> RB,BRAKET,RC,BRAKETdup 00100xxx00101111xxxxxxxxxx010001 */
-{ "scond", 0x202f0011, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SCOND, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 } }
+{ "scond", 0x202f0011, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SCOND, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 } }
 
 /* scond<.di> RB,BRAKET,UIMM6_20,BRAKETdup 00100xxx01101111xxxxxxxxxx010001 */
-{ "scond", 0x206f0011, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SCOND, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
+{ "scond", 0x206f0011, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SCOND, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 } }
 
 /* scond<.di> RB,BRAKET,LIMM,BRAKETdup 00100xxx00101111xxxx111110010001 */
-{ "scond", 0x202f0f91, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SCOND, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 } }
+{ "scond", 0x202f0f91, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SCOND, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 } }
 
 /* scondl RB,BRAKET,RC,BRAKETdup 01011xxx00101111xxxxxxxxxx010001 */
-{ "scondl", 0x582f0011, 0xf8ff003f, ARC_OPCODE_ARC64, SCOND, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_RL } }
+{ "scondl", 0x582f0011, 0xf8ff003f, ARC_OPCODE_ARC64, SCOND, ARC_INSN_SUBCLASS_NONE, { RB, BRAKET, RC, BRAKETdup }, { C_RL } }
 
 /* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011.  */
-{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARC32, SCOND, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
+{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARC32, SCOND, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* scondd<.di> b,limm 00100bbb00101111DBBB111110010011.  */
-{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARC32, SCOND, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
+{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARC32, SCOND, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* seteq<.f> RA,RB,RC 00100xxx00111000xxxxxxxxxxxxxxxx */
-{ "seteq", 0x20380000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "seteq", 0x20380000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* seteq<.f> ZA,RB,RC 00100xxx00111000xxxxxxxxxx111110 */
-{ "seteq", 0x2038003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "seteq", 0x2038003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* seteq<.f><.cc> RB,RBdup,RC 00100xxx11111000xxxxxxxxxx0xxxxx */
-{ "seteq", 0x20f80000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "seteq", 0x20f80000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* seteq<.f> RA,RB,UIMM6_20 00100xxx01111000xxxxxxxxxxxxxxxx */
-{ "seteq", 0x20780000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "seteq", 0x20780000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* seteq<.f> ZA,RB,UIMM6_20 00100xxx01111000xxxxxxxxxx111110 */
-{ "seteq", 0x2078003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "seteq", 0x2078003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* seteq<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11111000xxxxxxxxxx1xxxxx */
-{ "seteq", 0x20f80020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "seteq", 0x20f80020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* seteq<.f> RB,RBdup,SIMM12_20 00100xxx10111000xxxxxxxxxxxxxxxx */
-{ "seteq", 0x20b80000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "seteq", 0x20b80000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* seteq<.f> RA,LIMM,RC 0010011000111000x111xxxxxxxxxxxx */
-{ "seteq", 0x26387000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "seteq", 0x26387000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* seteq<.f> RA,RB,LIMM 00100xxx00111000xxxx111110xxxxxx */
-{ "seteq", 0x20380f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "seteq", 0x20380f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* seteq<.f> ZA,LIMM,RC 0010011000111000x111xxxxxx111110 */
-{ "seteq", 0x2638703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "seteq", 0x2638703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* seteq<.f> ZA,RB,LIMM 00100xxx00111000xxxx111110111110 */
-{ "seteq", 0x20380fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "seteq", 0x20380fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* seteq<.f><.cc> RB,RBdup,LIMM 00100xxx11111000xxxx1111100xxxxx */
-{ "seteq", 0x20f80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "seteq", 0x20f80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* seteq<.f><.cc> ZA,LIMM,RC 0010011011111000x111xxxxxx0xxxxx */
-{ "seteq", 0x26f87000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "seteq", 0x26f87000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* seteq<.f> RA,LIMM,UIMM6_20 0010011001111000x111xxxxxxxxxxxx */
-{ "seteq", 0x26787000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "seteq", 0x26787000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* seteq<.f> ZA,LIMM,UIMM6_20 0010011001111000x111xxxxxx111110 */
-{ "seteq", 0x2678703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "seteq", 0x2678703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* seteq<.f><.cc> ZA,LIMM,UIMM6_20 0010011011111000x111xxxxxx1xxxxx */
-{ "seteq", 0x26f87020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "seteq", 0x26f87020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* seteq<.f> ZA,LIMM,SIMM12_20 0010011010111000x111xxxxxxxxxxxx */
-{ "seteq", 0x26b87000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "seteq", 0x26b87000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* seteq<.f> RA,LIMM,LIMMdup 0010011000111000x111111110xxxxxx */
-{ "seteq", 0x26387f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "seteq", 0x26387f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* seteq<.f> ZA,LIMM,LIMMdup 0010011000111000x111111110111110 */
-{ "seteq", 0x26387fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "seteq", 0x26387fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* seteq<.f><.cc> ZA,LIMM,LIMMdup 0010011011111000x1111111100xxxxx */
-{ "seteq", 0x26f87f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "seteq", 0x26f87f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* seteql<.f> RA,RB,RC 01011xxx00111000xxxxxxxxxxxxxxxx */
-{ "seteql", 0x58380000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "seteql", 0x58380000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* seteql<.f> ZA,RB,RC 01011xxx00111000xxxxxxxxxx111110 */
-{ "seteql", 0x5838003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "seteql", 0x5838003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* seteql<.f><.cc> RB,RBdup,RC 01011xxx11111000xxxxxxxxxx0xxxxx */
-{ "seteql", 0x58f80000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "seteql", 0x58f80000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* seteql<.f> RA,RB,UIMM6_20 01011xxx01111000xxxxxxxxxxxxxxxx */
-{ "seteql", 0x58780000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "seteql", 0x58780000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* seteql<.f> ZA,RB,UIMM6_20 01011xxx01111000xxxxxxxxxx111110 */
-{ "seteql", 0x5878003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "seteql", 0x5878003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* seteql<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11111000xxxxxxxxxx1xxxxx */
-{ "seteql", 0x58f80020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "seteql", 0x58f80020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* seteql<.f> RB,RBdup,SIMM12_20 01011xxx10111000xxxxxxxxxxxxxxxx */
-{ "seteql", 0x58b80000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "seteql", 0x58b80000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* seteql<.f> RA,XIMM,RC 0101110000111000x111xxxxxxxxxxxx */
-{ "seteql", 0x5c387000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "seteql", 0x5c387000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* seteql<.f> RA,RB,XIMM 01011xxx00111000xxxx111100xxxxxx */
-{ "seteql", 0x58380f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "seteql", 0x58380f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* seteql<.f> ZA,XIMM,RC 0101110000111000x111xxxxxx111110 */
-{ "seteql", 0x5c38703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "seteql", 0x5c38703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* seteql<.f> ZA,RB,XIMM 01011xxx00111000xxxx111100111110 */
-{ "seteql", 0x58380f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "seteql", 0x58380f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* seteql<.f><.cc> ZA,XIMM,RC 0101110011111000x111xxxxxx0xxxxx */
-{ "seteql", 0x5cf87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "seteql", 0x5cf87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* seteql<.f><.cc> RB,RBdup,XIMM 01011xxx11111000xxxx1111000xxxxx */
-{ "seteql", 0x58f80f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "seteql", 0x58f80f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* seteql<.f> RA,XIMM,UIMM6_20 0101110001111000x111xxxxxxxxxxxx */
-{ "seteql", 0x5c787000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "seteql", 0x5c787000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* seteql<.f> ZA,XIMM,UIMM6_20 0101110001111000x111xxxxxx111110 */
-{ "seteql", 0x5c78703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "seteql", 0x5c78703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* seteql<.f><.cc> ZA,XIMM,UIMM6_20 0101110011111000x111xxxxxx1xxxxx */
-{ "seteql", 0x5cf87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "seteql", 0x5cf87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* seteql<.f> RA,LIMM,RC 0101111000111000x111xxxxxxxxxxxx */
-{ "seteql", 0x5e387000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "seteql", 0x5e387000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* seteql<.f> RA,RB,LIMM 01011xxx00111000xxxx111110xxxxxx */
-{ "seteql", 0x58380f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "seteql", 0x58380f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* seteql<.f> ZA,LIMM,RC 0101111000111000x111xxxxxx111110 */
-{ "seteql", 0x5e38703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "seteql", 0x5e38703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* seteql<.f> ZA,RB,LIMM 01011xxx00111000xxxx111110111110 */
-{ "seteql", 0x58380fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "seteql", 0x58380fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* seteql<.f><.cc> ZA,LIMM,RC 0101111011111000x111xxxxxx0xxxxx */
-{ "seteql", 0x5ef87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "seteql", 0x5ef87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* seteql<.f><.cc> RB,RBdup,LIMM 01011xxx11111000xxxx1111100xxxxx */
-{ "seteql", 0x58f80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "seteql", 0x58f80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* seteql<.f> RA,LIMM,UIMM6_20 0101111001111000x111xxxxxxxxxxxx */
-{ "seteql", 0x5e787000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "seteql", 0x5e787000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* seteql<.f> ZA,LIMM,UIMM6_20 0101111001111000x111xxxxxx111110 */
-{ "seteql", 0x5e78703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "seteql", 0x5e78703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* seteql<.f><.cc> ZA,LIMM,UIMM6_20 0101111011111000x111xxxxxx1xxxxx */
-{ "seteql", 0x5ef87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "seteql", 0x5ef87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* seteql<.f> ZA,XIMM,SIMM12_20 0101110010111000x111xxxxxxxxxxxx */
-{ "seteql", 0x5cb87000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "seteql", 0x5cb87000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* seteql<.f> ZA,LIMM,SIMM12_20 0101111010111000x111xxxxxxxxxxxx */
-{ "seteql", 0x5eb87000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "seteql", 0x5eb87000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* seteql<.f> RA,XIMM,XIMMdup 0101110000111000x111111100xxxxxx */
-{ "seteql", 0x5c387f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "seteql", 0x5c387f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* seteql<.f> ZA,XIMM,XIMMdup 0101110000111000x111111100111110 */
-{ "seteql", 0x5c387f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "seteql", 0x5c387f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* seteql<.f><.cc> ZA,XIMM,XIMMdup 0101110011111000x1111111000xxxxx */
-{ "seteql", 0x5cf87f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "seteql", 0x5cf87f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* seteql<.f> RA,LIMM,LIMMdup 0101111000111000x111111110xxxxxx */
-{ "seteql", 0x5e387f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "seteql", 0x5e387f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* seteql<.f> ZA,LIMM,LIMMdup 0101111000111000x111111110111110 */
-{ "seteql", 0x5e387fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "seteql", 0x5e387fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* seteql<.f><.cc> ZA,LIMM,LIMMdup 0101111011111000x1111111100xxxxx */
-{ "seteql", 0x5ef87f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "seteql", 0x5ef87f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setge<.f> RA,RB,RC 00100xxx00111011xxxxxxxxxxxxxxxx */
-{ "setge", 0x203b0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "setge", 0x203b0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setge<.f> ZA,RB,RC 00100xxx00111011xxxxxxxxxx111110 */
-{ "setge", 0x203b003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "setge", 0x203b003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setge<.f><.cc> RB,RBdup,RC 00100xxx11111011xxxxxxxxxx0xxxxx */
-{ "setge", 0x20fb0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setge", 0x20fb0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setge<.f> RA,RB,UIMM6_20 00100xxx01111011xxxxxxxxxxxxxxxx */
-{ "setge", 0x207b0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setge", 0x207b0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setge<.f> ZA,RB,UIMM6_20 00100xxx01111011xxxxxxxxxx111110 */
-{ "setge", 0x207b003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setge", 0x207b003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setge<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11111011xxxxxxxxxx1xxxxx */
-{ "setge", 0x20fb0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setge", 0x20fb0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setge<.f> RB,RBdup,SIMM12_20 00100xxx10111011xxxxxxxxxxxxxxxx */
-{ "setge", 0x20bb0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setge", 0x20bb0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setge<.f> RA,LIMM,RC 0010011000111011x111xxxxxxxxxxxx */
-{ "setge", 0x263b7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setge", 0x263b7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setge<.f> RA,RB,LIMM 00100xxx00111011xxxx111110xxxxxx */
-{ "setge", 0x203b0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setge", 0x203b0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setge<.f> ZA,LIMM,RC 0010011000111011x111xxxxxx111110 */
-{ "setge", 0x263b703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setge", 0x263b703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setge<.f> ZA,RB,LIMM 00100xxx00111011xxxx111110111110 */
-{ "setge", 0x203b0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setge", 0x203b0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setge<.f><.cc> RB,RBdup,LIMM 00100xxx11111011xxxx1111100xxxxx */
-{ "setge", 0x20fb0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setge", 0x20fb0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setge<.f><.cc> ZA,LIMM,RC 0010011011111011x111xxxxxx0xxxxx */
-{ "setge", 0x26fb7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setge", 0x26fb7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setge<.f> RA,LIMM,UIMM6_20 0010011001111011x111xxxxxxxxxxxx */
-{ "setge", 0x267b7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setge", 0x267b7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setge<.f> ZA,LIMM,UIMM6_20 0010011001111011x111xxxxxx111110 */
-{ "setge", 0x267b703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setge", 0x267b703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setge<.f><.cc> ZA,LIMM,UIMM6_20 0010011011111011x111xxxxxx1xxxxx */
-{ "setge", 0x26fb7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setge", 0x26fb7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setge<.f> ZA,LIMM,SIMM12_20 0010011010111011x111xxxxxxxxxxxx */
-{ "setge", 0x26bb7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setge", 0x26bb7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setge<.f> RA,LIMM,LIMMdup 0010011000111011x111111110xxxxxx */
-{ "setge", 0x263b7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setge", 0x263b7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setge<.f> ZA,LIMM,LIMMdup 0010011000111011x111111110111110 */
-{ "setge", 0x263b7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setge", 0x263b7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setge<.f><.cc> ZA,LIMM,LIMMdup 0010011011111011x1111111100xxxxx */
-{ "setge", 0x26fb7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setge", 0x26fb7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setgel<.f> RA,RB,RC 01011xxx00111011xxxxxxxxxxxxxxxx */
-{ "setgel", 0x583b0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "setgel", 0x583b0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setgel<.f> ZA,RB,RC 01011xxx00111011xxxxxxxxxx111110 */
-{ "setgel", 0x583b003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "setgel", 0x583b003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setgel<.f><.cc> RB,RBdup,RC 01011xxx11111011xxxxxxxxxx0xxxxx */
-{ "setgel", 0x58fb0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setgel", 0x58fb0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setgel<.f> RA,RB,UIMM6_20 01011xxx01111011xxxxxxxxxxxxxxxx */
-{ "setgel", 0x587b0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setgel", 0x587b0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setgel<.f> ZA,RB,UIMM6_20 01011xxx01111011xxxxxxxxxx111110 */
-{ "setgel", 0x587b003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setgel", 0x587b003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setgel<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11111011xxxxxxxxxx1xxxxx */
-{ "setgel", 0x58fb0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setgel", 0x58fb0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setgel<.f> RB,RBdup,SIMM12_20 01011xxx10111011xxxxxxxxxxxxxxxx */
-{ "setgel", 0x58bb0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setgel", 0x58bb0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setgel<.f> RA,XIMM,RC 0101110000111011x111xxxxxxxxxxxx */
-{ "setgel", 0x5c3b7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "setgel", 0x5c3b7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* setgel<.f> RA,RB,XIMM 01011xxx00111011xxxx111100xxxxxx */
-{ "setgel", 0x583b0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "setgel", 0x583b0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* setgel<.f> ZA,XIMM,RC 0101110000111011x111xxxxxx111110 */
-{ "setgel", 0x5c3b703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "setgel", 0x5c3b703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* setgel<.f> ZA,RB,XIMM 01011xxx00111011xxxx111100111110 */
-{ "setgel", 0x583b0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "setgel", 0x583b0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* setgel<.f><.cc> ZA,XIMM,RC 0101110011111011x111xxxxxx0xxxxx */
-{ "setgel", 0x5cfb7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "setgel", 0x5cfb7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* setgel<.f><.cc> RB,RBdup,XIMM 01011xxx11111011xxxx1111000xxxxx */
-{ "setgel", 0x58fb0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "setgel", 0x58fb0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* setgel<.f> RA,XIMM,UIMM6_20 0101110001111011x111xxxxxxxxxxxx */
-{ "setgel", 0x5c7b7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "setgel", 0x5c7b7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setgel<.f> ZA,XIMM,UIMM6_20 0101110001111011x111xxxxxx111110 */
-{ "setgel", 0x5c7b703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "setgel", 0x5c7b703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setgel<.f><.cc> ZA,XIMM,UIMM6_20 0101110011111011x111xxxxxx1xxxxx */
-{ "setgel", 0x5cfb7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setgel", 0x5cfb7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setgel<.f> RA,LIMM,RC 0101111000111011x111xxxxxxxxxxxx */
-{ "setgel", 0x5e3b7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setgel", 0x5e3b7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setgel<.f> RA,RB,LIMM 01011xxx00111011xxxx111110xxxxxx */
-{ "setgel", 0x583b0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setgel", 0x583b0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setgel<.f> ZA,LIMM,RC 0101111000111011x111xxxxxx111110 */
-{ "setgel", 0x5e3b703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setgel", 0x5e3b703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setgel<.f> ZA,RB,LIMM 01011xxx00111011xxxx111110111110 */
-{ "setgel", 0x583b0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setgel", 0x583b0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setgel<.f><.cc> ZA,LIMM,RC 0101111011111011x111xxxxxx0xxxxx */
-{ "setgel", 0x5efb7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setgel", 0x5efb7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setgel<.f><.cc> RB,RBdup,LIMM 01011xxx11111011xxxx1111100xxxxx */
-{ "setgel", 0x58fb0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setgel", 0x58fb0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setgel<.f> RA,LIMM,UIMM6_20 0101111001111011x111xxxxxxxxxxxx */
-{ "setgel", 0x5e7b7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setgel", 0x5e7b7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setgel<.f> ZA,LIMM,UIMM6_20 0101111001111011x111xxxxxx111110 */
-{ "setgel", 0x5e7b703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setgel", 0x5e7b703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setgel<.f><.cc> ZA,LIMM,UIMM6_20 0101111011111011x111xxxxxx1xxxxx */
-{ "setgel", 0x5efb7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setgel", 0x5efb7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setgel<.f> ZA,XIMM,SIMM12_20 0101110010111011x111xxxxxxxxxxxx */
-{ "setgel", 0x5cbb7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "setgel", 0x5cbb7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* setgel<.f> ZA,LIMM,SIMM12_20 0101111010111011x111xxxxxxxxxxxx */
-{ "setgel", 0x5ebb7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setgel", 0x5ebb7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setgel<.f> RA,XIMM,XIMMdup 0101110000111011x111111100xxxxxx */
-{ "setgel", 0x5c3b7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "setgel", 0x5c3b7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* setgel<.f> ZA,XIMM,XIMMdup 0101110000111011x111111100111110 */
-{ "setgel", 0x5c3b7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "setgel", 0x5c3b7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* setgel<.f><.cc> ZA,XIMM,XIMMdup 0101110011111011x1111111000xxxxx */
-{ "setgel", 0x5cfb7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "setgel", 0x5cfb7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* setgel<.f> RA,LIMM,LIMMdup 0101111000111011x111111110xxxxxx */
-{ "setgel", 0x5e3b7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setgel", 0x5e3b7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setgel<.f> ZA,LIMM,LIMMdup 0101111000111011x111111110111110 */
-{ "setgel", 0x5e3b7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setgel", 0x5e3b7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setgel<.f><.cc> ZA,LIMM,LIMMdup 0101111011111011x1111111100xxxxx */
-{ "setgel", 0x5efb7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setgel", 0x5efb7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setgt<.f> RA,RB,RC 00100xxx00111111xxxxxxxxxxxxxxxx */
-{ "setgt", 0x203f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "setgt", 0x203f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setgt<.f> ZA,RB,RC 00100xxx00111111xxxxxxxxxx111110 */
-{ "setgt", 0x203f003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "setgt", 0x203f003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setgt<.f><.cc> RB,RBdup,RC 00100xxx11111111xxxxxxxxxx0xxxxx */
-{ "setgt", 0x20ff0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setgt", 0x20ff0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setgt<.f> RA,RB,UIMM6_20 00100xxx01111111xxxxxxxxxxxxxxxx */
-{ "setgt", 0x207f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setgt", 0x207f0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setgt<.f> ZA,RB,UIMM6_20 00100xxx01111111xxxxxxxxxx111110 */
-{ "setgt", 0x207f003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setgt", 0x207f003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setgt<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11111111xxxxxxxxxx1xxxxx */
-{ "setgt", 0x20ff0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setgt", 0x20ff0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setgt<.f> RB,RBdup,SIMM12_20 00100xxx10111111xxxxxxxxxxxxxxxx */
-{ "setgt", 0x20bf0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setgt", 0x20bf0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setgt<.f> RA,LIMM,RC 0010011000111111x111xxxxxxxxxxxx */
-{ "setgt", 0x263f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setgt", 0x263f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setgt<.f> RA,RB,LIMM 00100xxx00111111xxxx111110xxxxxx */
-{ "setgt", 0x203f0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setgt", 0x203f0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setgt<.f> ZA,LIMM,RC 0010011000111111x111xxxxxx111110 */
-{ "setgt", 0x263f703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setgt", 0x263f703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setgt<.f> ZA,RB,LIMM 00100xxx00111111xxxx111110111110 */
-{ "setgt", 0x203f0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setgt", 0x203f0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setgt<.f><.cc> RB,RBdup,LIMM 00100xxx11111111xxxx1111100xxxxx */
-{ "setgt", 0x20ff0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setgt", 0x20ff0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setgt<.f><.cc> ZA,LIMM,RC 0010011011111111x111xxxxxx0xxxxx */
-{ "setgt", 0x26ff7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setgt", 0x26ff7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setgt<.f> RA,LIMM,UIMM6_20 0010011001111111x111xxxxxxxxxxxx */
-{ "setgt", 0x267f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setgt", 0x267f7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setgt<.f> ZA,LIMM,UIMM6_20 0010011001111111x111xxxxxx111110 */
-{ "setgt", 0x267f703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setgt", 0x267f703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setgt<.f><.cc> ZA,LIMM,UIMM6_20 0010011011111111x111xxxxxx1xxxxx */
-{ "setgt", 0x26ff7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setgt", 0x26ff7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setgt<.f> ZA,LIMM,SIMM12_20 0010011010111111x111xxxxxxxxxxxx */
-{ "setgt", 0x26bf7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setgt", 0x26bf7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setgt<.f> RA,LIMM,LIMMdup 0010011000111111x111111110xxxxxx */
-{ "setgt", 0x263f7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setgt", 0x263f7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setgt<.f> ZA,LIMM,LIMMdup 0010011000111111x111111110111110 */
-{ "setgt", 0x263f7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setgt", 0x263f7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setgt<.f><.cc> ZA,LIMM,LIMMdup 0010011011111111x1111111100xxxxx */
-{ "setgt", 0x26ff7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setgt", 0x26ff7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setgtl<.f> RA,RB,RC 01011xxx00111111xxxxxxxxxxxxxxxx */
-{ "setgtl", 0x583f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "setgtl", 0x583f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setgtl<.f> ZA,RB,RC 01011xxx00111111xxxxxxxxxx111110 */
-{ "setgtl", 0x583f003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "setgtl", 0x583f003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setgtl<.f><.cc> RB,RBdup,RC 01011xxx11111111xxxxxxxxxx0xxxxx */
-{ "setgtl", 0x58ff0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setgtl", 0x58ff0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setgtl<.f> RA,RB,UIMM6_20 01011xxx01111111xxxxxxxxxxxxxxxx */
-{ "setgtl", 0x587f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setgtl", 0x587f0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setgtl<.f> ZA,RB,UIMM6_20 01011xxx01111111xxxxxxxxxx111110 */
-{ "setgtl", 0x587f003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setgtl", 0x587f003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setgtl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11111111xxxxxxxxxx1xxxxx */
-{ "setgtl", 0x58ff0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setgtl", 0x58ff0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setgtl<.f> RB,RBdup,SIMM12_20 01011xxx10111111xxxxxxxxxxxxxxxx */
-{ "setgtl", 0x58bf0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setgtl", 0x58bf0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setgtl<.f> RA,XIMM,RC 0101110000111111x111xxxxxxxxxxxx */
-{ "setgtl", 0x5c3f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "setgtl", 0x5c3f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* setgtl<.f> RA,RB,XIMM 01011xxx00111111xxxx111100xxxxxx */
-{ "setgtl", 0x583f0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "setgtl", 0x583f0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* setgtl<.f> ZA,XIMM,RC 0101110000111111x111xxxxxx111110 */
-{ "setgtl", 0x5c3f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "setgtl", 0x5c3f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* setgtl<.f> ZA,RB,XIMM 01011xxx00111111xxxx111100111110 */
-{ "setgtl", 0x583f0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "setgtl", 0x583f0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* setgtl<.f><.cc> ZA,XIMM,RC 0101110011111111x111xxxxxx0xxxxx */
-{ "setgtl", 0x5cff7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "setgtl", 0x5cff7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* setgtl<.f><.cc> RB,RBdup,XIMM 01011xxx11111111xxxx1111000xxxxx */
-{ "setgtl", 0x58ff0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "setgtl", 0x58ff0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* setgtl<.f> RA,XIMM,UIMM6_20 0101110001111111x111xxxxxxxxxxxx */
-{ "setgtl", 0x5c7f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "setgtl", 0x5c7f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setgtl<.f> ZA,XIMM,UIMM6_20 0101110001111111x111xxxxxx111110 */
-{ "setgtl", 0x5c7f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "setgtl", 0x5c7f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setgtl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011111111x111xxxxxx1xxxxx */
-{ "setgtl", 0x5cff7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setgtl", 0x5cff7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setgtl<.f> RA,LIMM,RC 0101111000111111x111xxxxxxxxxxxx */
-{ "setgtl", 0x5e3f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setgtl", 0x5e3f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setgtl<.f> RA,RB,LIMM 01011xxx00111111xxxx111110xxxxxx */
-{ "setgtl", 0x583f0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setgtl", 0x583f0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setgtl<.f> ZA,LIMM,RC 0101111000111111x111xxxxxx111110 */
-{ "setgtl", 0x5e3f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setgtl", 0x5e3f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setgtl<.f> ZA,RB,LIMM 01011xxx00111111xxxx111110111110 */
-{ "setgtl", 0x583f0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setgtl", 0x583f0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setgtl<.f><.cc> ZA,LIMM,RC 0101111011111111x111xxxxxx0xxxxx */
-{ "setgtl", 0x5eff7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setgtl", 0x5eff7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setgtl<.f><.cc> RB,RBdup,LIMM 01011xxx11111111xxxx1111100xxxxx */
-{ "setgtl", 0x58ff0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setgtl", 0x58ff0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setgtl<.f> RA,LIMM,UIMM6_20 0101111001111111x111xxxxxxxxxxxx */
-{ "setgtl", 0x5e7f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setgtl", 0x5e7f7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setgtl<.f> ZA,LIMM,UIMM6_20 0101111001111111x111xxxxxx111110 */
-{ "setgtl", 0x5e7f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setgtl", 0x5e7f703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setgtl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011111111x111xxxxxx1xxxxx */
-{ "setgtl", 0x5eff7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setgtl", 0x5eff7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setgtl<.f> ZA,XIMM,SIMM12_20 0101110010111111x111xxxxxxxxxxxx */
-{ "setgtl", 0x5cbf7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "setgtl", 0x5cbf7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* setgtl<.f> ZA,LIMM,SIMM12_20 0101111010111111x111xxxxxxxxxxxx */
-{ "setgtl", 0x5ebf7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setgtl", 0x5ebf7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setgtl<.f> RA,XIMM,XIMMdup 0101110000111111x111111100xxxxxx */
-{ "setgtl", 0x5c3f7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "setgtl", 0x5c3f7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* setgtl<.f> ZA,XIMM,XIMMdup 0101110000111111x111111100111110 */
-{ "setgtl", 0x5c3f7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "setgtl", 0x5c3f7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* setgtl<.f><.cc> ZA,XIMM,XIMMdup 0101110011111111x1111111000xxxxx */
-{ "setgtl", 0x5cff7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "setgtl", 0x5cff7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* setgtl<.f> RA,LIMM,LIMMdup 0101111000111111x111111110xxxxxx */
-{ "setgtl", 0x5e3f7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setgtl", 0x5e3f7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setgtl<.f> ZA,LIMM,LIMMdup 0101111000111111x111111110111110 */
-{ "setgtl", 0x5e3f7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setgtl", 0x5e3f7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setgtl<.f><.cc> ZA,LIMM,LIMMdup 0101111011111111x1111111100xxxxx */
-{ "setgtl", 0x5eff7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setgtl", 0x5eff7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* seths<.f> RA,RB,RC 00100xxx00111101xxxxxxxxxxxxxxxx */
-{ "seths", 0x203d0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "seths", 0x203d0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* seths<.f> ZA,RB,RC 00100xxx00111101xxxxxxxxxx111110 */
-{ "seths", 0x203d003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "seths", 0x203d003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* seths<.f><.cc> RB,RBdup,RC 00100xxx11111101xxxxxxxxxx0xxxxx */
-{ "seths", 0x20fd0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "seths", 0x20fd0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* seths<.f> RA,RB,UIMM6_20 00100xxx01111101xxxxxxxxxxxxxxxx */
-{ "seths", 0x207d0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "seths", 0x207d0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* seths<.f> ZA,RB,UIMM6_20 00100xxx01111101xxxxxxxxxx111110 */
-{ "seths", 0x207d003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "seths", 0x207d003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* seths<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11111101xxxxxxxxxx1xxxxx */
-{ "seths", 0x20fd0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "seths", 0x20fd0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* seths<.f> RB,RBdup,SIMM12_20 00100xxx10111101xxxxxxxxxxxxxxxx */
-{ "seths", 0x20bd0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "seths", 0x20bd0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* seths<.f> RA,LIMM,RC 0010011000111101x111xxxxxxxxxxxx */
-{ "seths", 0x263d7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "seths", 0x263d7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* seths<.f> RA,RB,LIMM 00100xxx00111101xxxx111110xxxxxx */
-{ "seths", 0x203d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "seths", 0x203d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* seths<.f> ZA,LIMM,RC 0010011000111101x111xxxxxx111110 */
-{ "seths", 0x263d703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "seths", 0x263d703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* seths<.f> ZA,RB,LIMM 00100xxx00111101xxxx111110111110 */
-{ "seths", 0x203d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "seths", 0x203d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* seths<.f><.cc> RB,RBdup,LIMM 00100xxx11111101xxxx1111100xxxxx */
-{ "seths", 0x20fd0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "seths", 0x20fd0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* seths<.f><.cc> ZA,LIMM,RC 0010011011111101x111xxxxxx0xxxxx */
-{ "seths", 0x26fd7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "seths", 0x26fd7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* seths<.f> RA,LIMM,UIMM6_20 0010011001111101x111xxxxxxxxxxxx */
-{ "seths", 0x267d7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "seths", 0x267d7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* seths<.f> ZA,LIMM,UIMM6_20 0010011001111101x111xxxxxx111110 */
-{ "seths", 0x267d703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "seths", 0x267d703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* seths<.f><.cc> ZA,LIMM,UIMM6_20 0010011011111101x111xxxxxx1xxxxx */
-{ "seths", 0x26fd7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "seths", 0x26fd7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* seths<.f> ZA,LIMM,SIMM12_20 0010011010111101x111xxxxxxxxxxxx */
-{ "seths", 0x26bd7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "seths", 0x26bd7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* seths<.f> RA,LIMM,LIMMdup 0010011000111101x111111110xxxxxx */
-{ "seths", 0x263d7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "seths", 0x263d7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* seths<.f> ZA,LIMM,LIMMdup 0010011000111101x111111110111110 */
-{ "seths", 0x263d7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "seths", 0x263d7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* seths<.f><.cc> ZA,LIMM,LIMMdup 0010011011111101x1111111100xxxxx */
-{ "seths", 0x26fd7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "seths", 0x26fd7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sethsl<.f> RA,RB,RC 01011xxx00111101xxxxxxxxxxxxxxxx */
-{ "sethsl", 0x583d0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "sethsl", 0x583d0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sethsl<.f> ZA,RB,RC 01011xxx00111101xxxxxxxxxx111110 */
-{ "sethsl", 0x583d003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "sethsl", 0x583d003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sethsl<.f><.cc> RB,RBdup,RC 01011xxx11111101xxxxxxxxxx0xxxxx */
-{ "sethsl", 0x58fd0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sethsl", 0x58fd0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sethsl<.f> RA,RB,UIMM6_20 01011xxx01111101xxxxxxxxxxxxxxxx */
-{ "sethsl", 0x587d0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sethsl", 0x587d0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sethsl<.f> ZA,RB,UIMM6_20 01011xxx01111101xxxxxxxxxx111110 */
-{ "sethsl", 0x587d003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sethsl", 0x587d003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sethsl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11111101xxxxxxxxxx1xxxxx */
-{ "sethsl", 0x58fd0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sethsl", 0x58fd0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sethsl<.f> RB,RBdup,SIMM12_20 01011xxx10111101xxxxxxxxxxxxxxxx */
-{ "sethsl", 0x58bd0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sethsl", 0x58bd0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sethsl<.f> RA,XIMM,RC 0101110000111101x111xxxxxxxxxxxx */
-{ "sethsl", 0x5c3d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "sethsl", 0x5c3d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* sethsl<.f> RA,RB,XIMM 01011xxx00111101xxxx111100xxxxxx */
-{ "sethsl", 0x583d0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "sethsl", 0x583d0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* sethsl<.f> ZA,XIMM,RC 0101110000111101x111xxxxxx111110 */
-{ "sethsl", 0x5c3d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "sethsl", 0x5c3d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* sethsl<.f> ZA,RB,XIMM 01011xxx00111101xxxx111100111110 */
-{ "sethsl", 0x583d0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "sethsl", 0x583d0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* sethsl<.f><.cc> ZA,XIMM,RC 0101110011111101x111xxxxxx0xxxxx */
-{ "sethsl", 0x5cfd7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "sethsl", 0x5cfd7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* sethsl<.f><.cc> RB,RBdup,XIMM 01011xxx11111101xxxx1111000xxxxx */
-{ "sethsl", 0x58fd0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "sethsl", 0x58fd0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* sethsl<.f> RA,XIMM,UIMM6_20 0101110001111101x111xxxxxxxxxxxx */
-{ "sethsl", 0x5c7d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "sethsl", 0x5c7d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sethsl<.f> ZA,XIMM,UIMM6_20 0101110001111101x111xxxxxx111110 */
-{ "sethsl", 0x5c7d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "sethsl", 0x5c7d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sethsl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011111101x111xxxxxx1xxxxx */
-{ "sethsl", 0x5cfd7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sethsl", 0x5cfd7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sethsl<.f> RA,LIMM,RC 0101111000111101x111xxxxxxxxxxxx */
-{ "sethsl", 0x5e3d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sethsl", 0x5e3d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sethsl<.f> RA,RB,LIMM 01011xxx00111101xxxx111110xxxxxx */
-{ "sethsl", 0x583d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sethsl", 0x583d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sethsl<.f> ZA,LIMM,RC 0101111000111101x111xxxxxx111110 */
-{ "sethsl", 0x5e3d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sethsl", 0x5e3d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sethsl<.f> ZA,RB,LIMM 01011xxx00111101xxxx111110111110 */
-{ "sethsl", 0x583d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sethsl", 0x583d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sethsl<.f><.cc> ZA,LIMM,RC 0101111011111101x111xxxxxx0xxxxx */
-{ "sethsl", 0x5efd7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sethsl", 0x5efd7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sethsl<.f><.cc> RB,RBdup,LIMM 01011xxx11111101xxxx1111100xxxxx */
-{ "sethsl", 0x58fd0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sethsl", 0x58fd0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sethsl<.f> RA,LIMM,UIMM6_20 0101111001111101x111xxxxxxxxxxxx */
-{ "sethsl", 0x5e7d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sethsl", 0x5e7d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sethsl<.f> ZA,LIMM,UIMM6_20 0101111001111101x111xxxxxx111110 */
-{ "sethsl", 0x5e7d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sethsl", 0x5e7d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sethsl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011111101x111xxxxxx1xxxxx */
-{ "sethsl", 0x5efd7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sethsl", 0x5efd7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sethsl<.f> ZA,XIMM,SIMM12_20 0101110010111101x111xxxxxxxxxxxx */
-{ "sethsl", 0x5cbd7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "sethsl", 0x5cbd7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* sethsl<.f> ZA,LIMM,SIMM12_20 0101111010111101x111xxxxxxxxxxxx */
-{ "sethsl", 0x5ebd7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sethsl", 0x5ebd7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sethsl<.f> RA,XIMM,XIMMdup 0101110000111101x111111100xxxxxx */
-{ "sethsl", 0x5c3d7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "sethsl", 0x5c3d7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* sethsl<.f> ZA,XIMM,XIMMdup 0101110000111101x111111100111110 */
-{ "sethsl", 0x5c3d7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "sethsl", 0x5c3d7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* sethsl<.f><.cc> ZA,XIMM,XIMMdup 0101110011111101x1111111000xxxxx */
-{ "sethsl", 0x5cfd7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "sethsl", 0x5cfd7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* sethsl<.f> RA,LIMM,LIMMdup 0101111000111101x111111110xxxxxx */
-{ "sethsl", 0x5e3d7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sethsl", 0x5e3d7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sethsl<.f> ZA,LIMM,LIMMdup 0101111000111101x111111110111110 */
-{ "sethsl", 0x5e3d7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sethsl", 0x5e3d7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sethsl<.f><.cc> ZA,LIMM,LIMMdup 0101111011111101x1111111100xxxxx */
-{ "sethsl", 0x5efd7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sethsl", 0x5efd7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* seti RC 00100110001011110000xxxxxx111111 */
-{ "seti", 0x262f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { RC }, { 0 } }
+{ "seti", 0x262f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { RC }, { 0 } }
 
 /* seti UIMM6_20 00100110011011110000xxxxxx111111 */
-{ "seti", 0x266f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { UIMM6_20 }, { 0 } }
+{ "seti", 0x266f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* seti LIMM 00100110001011110000111110111111 */
-{ "seti", 0x262f0fbf, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, { LIMM }, { 0 } }
+{ "seti", 0x262f0fbf, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, { LIMM }, { 0 } }
 
 /* seti  00100110011011110000000000111111 */
-{ "seti", 0x266f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, {  }, { 0 } }
+{ "seti", 0x266f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* setle<.f> RA,RB,RC 00100xxx00111110xxxxxxxxxxxxxxxx */
-{ "setle", 0x203e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "setle", 0x203e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setle<.f> ZA,RB,RC 00100xxx00111110xxxxxxxxxx111110 */
-{ "setle", 0x203e003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "setle", 0x203e003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setle<.f><.cc> RB,RBdup,RC 00100xxx11111110xxxxxxxxxx0xxxxx */
-{ "setle", 0x20fe0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setle", 0x20fe0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setle<.f> RA,RB,UIMM6_20 00100xxx01111110xxxxxxxxxxxxxxxx */
-{ "setle", 0x207e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setle", 0x207e0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setle<.f> ZA,RB,UIMM6_20 00100xxx01111110xxxxxxxxxx111110 */
-{ "setle", 0x207e003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setle", 0x207e003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setle<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11111110xxxxxxxxxx1xxxxx */
-{ "setle", 0x20fe0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setle", 0x20fe0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setle<.f> RB,RBdup,SIMM12_20 00100xxx10111110xxxxxxxxxxxxxxxx */
-{ "setle", 0x20be0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setle", 0x20be0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setle<.f> RA,LIMM,RC 0010011000111110x111xxxxxxxxxxxx */
-{ "setle", 0x263e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setle", 0x263e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setle<.f> RA,RB,LIMM 00100xxx00111110xxxx111110xxxxxx */
-{ "setle", 0x203e0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setle", 0x203e0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setle<.f> ZA,LIMM,RC 0010011000111110x111xxxxxx111110 */
-{ "setle", 0x263e703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setle", 0x263e703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setle<.f> ZA,RB,LIMM 00100xxx00111110xxxx111110111110 */
-{ "setle", 0x203e0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setle", 0x203e0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setle<.f><.cc> RB,RBdup,LIMM 00100xxx11111110xxxx1111100xxxxx */
-{ "setle", 0x20fe0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setle", 0x20fe0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setle<.f><.cc> ZA,LIMM,RC 0010011011111110x111xxxxxx0xxxxx */
-{ "setle", 0x26fe7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setle", 0x26fe7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setle<.f> RA,LIMM,UIMM6_20 0010011001111110x111xxxxxxxxxxxx */
-{ "setle", 0x267e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setle", 0x267e7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setle<.f> ZA,LIMM,UIMM6_20 0010011001111110x111xxxxxx111110 */
-{ "setle", 0x267e703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setle", 0x267e703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setle<.f><.cc> ZA,LIMM,UIMM6_20 0010011011111110x111xxxxxx1xxxxx */
-{ "setle", 0x26fe7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setle", 0x26fe7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setle<.f> ZA,LIMM,SIMM12_20 0010011010111110x111xxxxxxxxxxxx */
-{ "setle", 0x26be7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setle", 0x26be7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setle<.f> RA,LIMM,LIMMdup 0010011000111110x111111110xxxxxx */
-{ "setle", 0x263e7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setle", 0x263e7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setle<.f> ZA,LIMM,LIMMdup 0010011000111110x111111110111110 */
-{ "setle", 0x263e7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setle", 0x263e7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setle<.f><.cc> ZA,LIMM,LIMMdup 0010011011111110x1111111100xxxxx */
-{ "setle", 0x26fe7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setle", 0x26fe7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setlel<.f> RA,RB,RC 01011xxx00111110xxxxxxxxxxxxxxxx */
-{ "setlel", 0x583e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "setlel", 0x583e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setlel<.f> ZA,RB,RC 01011xxx00111110xxxxxxxxxx111110 */
-{ "setlel", 0x583e003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "setlel", 0x583e003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setlel<.f><.cc> RB,RBdup,RC 01011xxx11111110xxxxxxxxxx0xxxxx */
-{ "setlel", 0x58fe0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setlel", 0x58fe0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setlel<.f> RA,RB,UIMM6_20 01011xxx01111110xxxxxxxxxxxxxxxx */
-{ "setlel", 0x587e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setlel", 0x587e0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setlel<.f> ZA,RB,UIMM6_20 01011xxx01111110xxxxxxxxxx111110 */
-{ "setlel", 0x587e003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setlel", 0x587e003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setlel<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11111110xxxxxxxxxx1xxxxx */
-{ "setlel", 0x58fe0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setlel", 0x58fe0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlel<.f> RB,RBdup,SIMM12_20 01011xxx10111110xxxxxxxxxxxxxxxx */
-{ "setlel", 0x58be0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setlel", 0x58be0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setlel<.f> RA,XIMM,RC 0101110000111110x111xxxxxxxxxxxx */
-{ "setlel", 0x5c3e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "setlel", 0x5c3e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* setlel<.f> RA,RB,XIMM 01011xxx00111110xxxx111100xxxxxx */
-{ "setlel", 0x583e0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "setlel", 0x583e0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* setlel<.f> ZA,XIMM,RC 0101110000111110x111xxxxxx111110 */
-{ "setlel", 0x5c3e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "setlel", 0x5c3e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* setlel<.f> ZA,RB,XIMM 01011xxx00111110xxxx111100111110 */
-{ "setlel", 0x583e0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "setlel", 0x583e0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* setlel<.f><.cc> ZA,XIMM,RC 0101110011111110x111xxxxxx0xxxxx */
-{ "setlel", 0x5cfe7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "setlel", 0x5cfe7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* setlel<.f><.cc> RB,RBdup,XIMM 01011xxx11111110xxxx1111000xxxxx */
-{ "setlel", 0x58fe0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "setlel", 0x58fe0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* setlel<.f> RA,XIMM,UIMM6_20 0101110001111110x111xxxxxxxxxxxx */
-{ "setlel", 0x5c7e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "setlel", 0x5c7e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setlel<.f> ZA,XIMM,UIMM6_20 0101110001111110x111xxxxxx111110 */
-{ "setlel", 0x5c7e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "setlel", 0x5c7e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setlel<.f><.cc> ZA,XIMM,UIMM6_20 0101110011111110x111xxxxxx1xxxxx */
-{ "setlel", 0x5cfe7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setlel", 0x5cfe7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlel<.f> RA,LIMM,RC 0101111000111110x111xxxxxxxxxxxx */
-{ "setlel", 0x5e3e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setlel", 0x5e3e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setlel<.f> RA,RB,LIMM 01011xxx00111110xxxx111110xxxxxx */
-{ "setlel", 0x583e0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setlel", 0x583e0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setlel<.f> ZA,LIMM,RC 0101111000111110x111xxxxxx111110 */
-{ "setlel", 0x5e3e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setlel", 0x5e3e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setlel<.f> ZA,RB,LIMM 01011xxx00111110xxxx111110111110 */
-{ "setlel", 0x583e0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setlel", 0x583e0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setlel<.f><.cc> ZA,LIMM,RC 0101111011111110x111xxxxxx0xxxxx */
-{ "setlel", 0x5efe7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setlel", 0x5efe7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setlel<.f><.cc> RB,RBdup,LIMM 01011xxx11111110xxxx1111100xxxxx */
-{ "setlel", 0x58fe0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setlel", 0x58fe0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setlel<.f> RA,LIMM,UIMM6_20 0101111001111110x111xxxxxxxxxxxx */
-{ "setlel", 0x5e7e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setlel", 0x5e7e7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setlel<.f> ZA,LIMM,UIMM6_20 0101111001111110x111xxxxxx111110 */
-{ "setlel", 0x5e7e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setlel", 0x5e7e703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setlel<.f><.cc> ZA,LIMM,UIMM6_20 0101111011111110x111xxxxxx1xxxxx */
-{ "setlel", 0x5efe7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setlel", 0x5efe7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlel<.f> ZA,XIMM,SIMM12_20 0101110010111110x111xxxxxxxxxxxx */
-{ "setlel", 0x5cbe7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "setlel", 0x5cbe7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* setlel<.f> ZA,LIMM,SIMM12_20 0101111010111110x111xxxxxxxxxxxx */
-{ "setlel", 0x5ebe7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setlel", 0x5ebe7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setlel<.f> RA,XIMM,XIMMdup 0101110000111110x111111100xxxxxx */
-{ "setlel", 0x5c3e7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "setlel", 0x5c3e7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* setlel<.f> ZA,XIMM,XIMMdup 0101110000111110x111111100111110 */
-{ "setlel", 0x5c3e7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "setlel", 0x5c3e7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* setlel<.f><.cc> ZA,XIMM,XIMMdup 0101110011111110x1111111000xxxxx */
-{ "setlel", 0x5cfe7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "setlel", 0x5cfe7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* setlel<.f> RA,LIMM,LIMMdup 0101111000111110x111111110xxxxxx */
-{ "setlel", 0x5e3e7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setlel", 0x5e3e7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setlel<.f> ZA,LIMM,LIMMdup 0101111000111110x111111110111110 */
-{ "setlel", 0x5e3e7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setlel", 0x5e3e7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setlel<.f><.cc> ZA,LIMM,LIMMdup 0101111011111110x1111111100xxxxx */
-{ "setlel", 0x5efe7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setlel", 0x5efe7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setlo<.f> RA,RB,RC 00100xxx00111100xxxxxxxxxxxxxxxx */
-{ "setlo", 0x203c0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "setlo", 0x203c0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setlo<.f> ZA,RB,RC 00100xxx00111100xxxxxxxxxx111110 */
-{ "setlo", 0x203c003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "setlo", 0x203c003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setlo<.f><.cc> RB,RBdup,RC 00100xxx11111100xxxxxxxxxx0xxxxx */
-{ "setlo", 0x20fc0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setlo", 0x20fc0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setlo<.f> RA,RB,UIMM6_20 00100xxx01111100xxxxxxxxxxxxxxxx */
-{ "setlo", 0x207c0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setlo", 0x207c0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setlo<.f> ZA,RB,UIMM6_20 00100xxx01111100xxxxxxxxxx111110 */
-{ "setlo", 0x207c003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setlo", 0x207c003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setlo<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11111100xxxxxxxxxx1xxxxx */
-{ "setlo", 0x20fc0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setlo", 0x20fc0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlo<.f> RB,RBdup,SIMM12_20 00100xxx10111100xxxxxxxxxxxxxxxx */
-{ "setlo", 0x20bc0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setlo", 0x20bc0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setlo<.f> RA,LIMM,RC 0010011000111100x111xxxxxxxxxxxx */
-{ "setlo", 0x263c7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setlo", 0x263c7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setlo<.f> RA,RB,LIMM 00100xxx00111100xxxx111110xxxxxx */
-{ "setlo", 0x203c0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setlo", 0x203c0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setlo<.f> ZA,LIMM,RC 0010011000111100x111xxxxxx111110 */
-{ "setlo", 0x263c703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setlo", 0x263c703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setlo<.f> ZA,RB,LIMM 00100xxx00111100xxxx111110111110 */
-{ "setlo", 0x203c0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setlo", 0x203c0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setlo<.f><.cc> RB,RBdup,LIMM 00100xxx11111100xxxx1111100xxxxx */
-{ "setlo", 0x20fc0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setlo", 0x20fc0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setlo<.f><.cc> ZA,LIMM,RC 0010011011111100x111xxxxxx0xxxxx */
-{ "setlo", 0x26fc7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setlo", 0x26fc7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setlo<.f> RA,LIMM,UIMM6_20 0010011001111100x111xxxxxxxxxxxx */
-{ "setlo", 0x267c7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setlo", 0x267c7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setlo<.f> ZA,LIMM,UIMM6_20 0010011001111100x111xxxxxx111110 */
-{ "setlo", 0x267c703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setlo", 0x267c703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setlo<.f><.cc> ZA,LIMM,UIMM6_20 0010011011111100x111xxxxxx1xxxxx */
-{ "setlo", 0x26fc7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setlo", 0x26fc7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlo<.f> ZA,LIMM,SIMM12_20 0010011010111100x111xxxxxxxxxxxx */
-{ "setlo", 0x26bc7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setlo", 0x26bc7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setlo<.f> RA,LIMM,LIMMdup 0010011000111100x111111110xxxxxx */
-{ "setlo", 0x263c7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setlo", 0x263c7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setlo<.f> ZA,LIMM,LIMMdup 0010011000111100x111111110111110 */
-{ "setlo", 0x263c7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setlo", 0x263c7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setlo<.f><.cc> ZA,LIMM,LIMMdup 0010011011111100x1111111100xxxxx */
-{ "setlo", 0x26fc7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setlo", 0x26fc7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setlol<.f> RA,RB,RC 01011xxx00111100xxxxxxxxxxxxxxxx */
-{ "setlol", 0x583c0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "setlol", 0x583c0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setlol<.f> ZA,RB,RC 01011xxx00111100xxxxxxxxxx111110 */
-{ "setlol", 0x583c003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "setlol", 0x583c003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setlol<.f><.cc> RB,RBdup,RC 01011xxx11111100xxxxxxxxxx0xxxxx */
-{ "setlol", 0x58fc0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setlol", 0x58fc0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setlol<.f> RA,RB,UIMM6_20 01011xxx01111100xxxxxxxxxxxxxxxx */
-{ "setlol", 0x587c0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setlol", 0x587c0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setlol<.f> ZA,RB,UIMM6_20 01011xxx01111100xxxxxxxxxx111110 */
-{ "setlol", 0x587c003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setlol", 0x587c003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setlol<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11111100xxxxxxxxxx1xxxxx */
-{ "setlol", 0x58fc0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setlol", 0x58fc0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlol<.f> RB,RBdup,SIMM12_20 01011xxx10111100xxxxxxxxxxxxxxxx */
-{ "setlol", 0x58bc0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setlol", 0x58bc0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setlol<.f> RA,XIMM,RC 0101110000111100x111xxxxxxxxxxxx */
-{ "setlol", 0x5c3c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "setlol", 0x5c3c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* setlol<.f> RA,RB,XIMM 01011xxx00111100xxxx111100xxxxxx */
-{ "setlol", 0x583c0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "setlol", 0x583c0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* setlol<.f> ZA,XIMM,RC 0101110000111100x111xxxxxx111110 */
-{ "setlol", 0x5c3c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "setlol", 0x5c3c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* setlol<.f> ZA,RB,XIMM 01011xxx00111100xxxx111100111110 */
-{ "setlol", 0x583c0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "setlol", 0x583c0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* setlol<.f><.cc> ZA,XIMM,RC 0101110011111100x111xxxxxx0xxxxx */
-{ "setlol", 0x5cfc7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "setlol", 0x5cfc7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* setlol<.f><.cc> RB,RBdup,XIMM 01011xxx11111100xxxx1111000xxxxx */
-{ "setlol", 0x58fc0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "setlol", 0x58fc0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* setlol<.f> RA,XIMM,UIMM6_20 0101110001111100x111xxxxxxxxxxxx */
-{ "setlol", 0x5c7c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "setlol", 0x5c7c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setlol<.f> ZA,XIMM,UIMM6_20 0101110001111100x111xxxxxx111110 */
-{ "setlol", 0x5c7c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "setlol", 0x5c7c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setlol<.f><.cc> ZA,XIMM,UIMM6_20 0101110011111100x111xxxxxx1xxxxx */
-{ "setlol", 0x5cfc7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setlol", 0x5cfc7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlol<.f> RA,LIMM,RC 0101111000111100x111xxxxxxxxxxxx */
-{ "setlol", 0x5e3c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setlol", 0x5e3c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setlol<.f> RA,RB,LIMM 01011xxx00111100xxxx111110xxxxxx */
-{ "setlol", 0x583c0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setlol", 0x583c0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setlol<.f> ZA,LIMM,RC 0101111000111100x111xxxxxx111110 */
-{ "setlol", 0x5e3c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setlol", 0x5e3c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setlol<.f> ZA,RB,LIMM 01011xxx00111100xxxx111110111110 */
-{ "setlol", 0x583c0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setlol", 0x583c0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setlol<.f><.cc> ZA,LIMM,RC 0101111011111100x111xxxxxx0xxxxx */
-{ "setlol", 0x5efc7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setlol", 0x5efc7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setlol<.f><.cc> RB,RBdup,LIMM 01011xxx11111100xxxx1111100xxxxx */
-{ "setlol", 0x58fc0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setlol", 0x58fc0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setlol<.f> RA,LIMM,UIMM6_20 0101111001111100x111xxxxxxxxxxxx */
-{ "setlol", 0x5e7c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setlol", 0x5e7c7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setlol<.f> ZA,LIMM,UIMM6_20 0101111001111100x111xxxxxx111110 */
-{ "setlol", 0x5e7c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setlol", 0x5e7c703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setlol<.f><.cc> ZA,LIMM,UIMM6_20 0101111011111100x111xxxxxx1xxxxx */
-{ "setlol", 0x5efc7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setlol", 0x5efc7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlol<.f> ZA,XIMM,SIMM12_20 0101110010111100x111xxxxxxxxxxxx */
-{ "setlol", 0x5cbc7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "setlol", 0x5cbc7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* setlol<.f> ZA,LIMM,SIMM12_20 0101111010111100x111xxxxxxxxxxxx */
-{ "setlol", 0x5ebc7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setlol", 0x5ebc7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setlol<.f> RA,XIMM,XIMMdup 0101110000111100x111111100xxxxxx */
-{ "setlol", 0x5c3c7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "setlol", 0x5c3c7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* setlol<.f> ZA,XIMM,XIMMdup 0101110000111100x111111100111110 */
-{ "setlol", 0x5c3c7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "setlol", 0x5c3c7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* setlol<.f><.cc> ZA,XIMM,XIMMdup 0101110011111100x1111111000xxxxx */
-{ "setlol", 0x5cfc7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "setlol", 0x5cfc7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* setlol<.f> RA,LIMM,LIMMdup 0101111000111100x111111110xxxxxx */
-{ "setlol", 0x5e3c7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setlol", 0x5e3c7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setlol<.f> ZA,LIMM,LIMMdup 0101111000111100x111111110111110 */
-{ "setlol", 0x5e3c7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setlol", 0x5e3c7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setlol<.f><.cc> ZA,LIMM,LIMMdup 0101111011111100x1111111100xxxxx */
-{ "setlol", 0x5efc7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setlol", 0x5efc7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setlt<.f> RA,RB,RC 00100xxx00111010xxxxxxxxxxxxxxxx */
-{ "setlt", 0x203a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "setlt", 0x203a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setlt<.f> ZA,RB,RC 00100xxx00111010xxxxxxxxxx111110 */
-{ "setlt", 0x203a003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "setlt", 0x203a003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setlt<.f><.cc> RB,RBdup,RC 00100xxx11111010xxxxxxxxxx0xxxxx */
-{ "setlt", 0x20fa0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setlt", 0x20fa0000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setlt<.f> RA,RB,UIMM6_20 00100xxx01111010xxxxxxxxxxxxxxxx */
-{ "setlt", 0x207a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setlt", 0x207a0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setlt<.f> ZA,RB,UIMM6_20 00100xxx01111010xxxxxxxxxx111110 */
-{ "setlt", 0x207a003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setlt", 0x207a003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setlt<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11111010xxxxxxxxxx1xxxxx */
-{ "setlt", 0x20fa0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setlt", 0x20fa0020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlt<.f> RB,RBdup,SIMM12_20 00100xxx10111010xxxxxxxxxxxxxxxx */
-{ "setlt", 0x20ba0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setlt", 0x20ba0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setlt<.f> RA,LIMM,RC 0010011000111010x111xxxxxxxxxxxx */
-{ "setlt", 0x263a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setlt", 0x263a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setlt<.f> RA,RB,LIMM 00100xxx00111010xxxx111110xxxxxx */
-{ "setlt", 0x203a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setlt", 0x203a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setlt<.f> ZA,LIMM,RC 0010011000111010x111xxxxxx111110 */
-{ "setlt", 0x263a703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setlt", 0x263a703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setlt<.f> ZA,RB,LIMM 00100xxx00111010xxxx111110111110 */
-{ "setlt", 0x203a0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setlt", 0x203a0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setlt<.f><.cc> RB,RBdup,LIMM 00100xxx11111010xxxx1111100xxxxx */
-{ "setlt", 0x20fa0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setlt", 0x20fa0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setlt<.f><.cc> ZA,LIMM,RC 0010011011111010x111xxxxxx0xxxxx */
-{ "setlt", 0x26fa7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setlt", 0x26fa7000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setlt<.f> RA,LIMM,UIMM6_20 0010011001111010x111xxxxxxxxxxxx */
-{ "setlt", 0x267a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setlt", 0x267a7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setlt<.f> ZA,LIMM,UIMM6_20 0010011001111010x111xxxxxx111110 */
-{ "setlt", 0x267a703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setlt", 0x267a703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setlt<.f><.cc> ZA,LIMM,UIMM6_20 0010011011111010x111xxxxxx1xxxxx */
-{ "setlt", 0x26fa7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setlt", 0x26fa7020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setlt<.f> ZA,LIMM,SIMM12_20 0010011010111010x111xxxxxxxxxxxx */
-{ "setlt", 0x26ba7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setlt", 0x26ba7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setlt<.f> RA,LIMM,LIMMdup 0010011000111010x111111110xxxxxx */
-{ "setlt", 0x263a7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setlt", 0x263a7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setlt<.f> ZA,LIMM,LIMMdup 0010011000111010x111111110111110 */
-{ "setlt", 0x263a7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setlt", 0x263a7fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setlt<.f><.cc> ZA,LIMM,LIMMdup 0010011011111010x1111111100xxxxx */
-{ "setlt", 0x26fa7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setlt", 0x26fa7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setltl<.f> RA,RB,RC 01011xxx00111010xxxxxxxxxxxxxxxx */
-{ "setltl", 0x583a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "setltl", 0x583a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setltl<.f> ZA,RB,RC 01011xxx00111010xxxxxxxxxx111110 */
-{ "setltl", 0x583a003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "setltl", 0x583a003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setltl<.f><.cc> RB,RBdup,RC 01011xxx11111010xxxxxxxxxx0xxxxx */
-{ "setltl", 0x58fa0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setltl", 0x58fa0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setltl<.f> RA,RB,UIMM6_20 01011xxx01111010xxxxxxxxxxxxxxxx */
-{ "setltl", 0x587a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setltl", 0x587a0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setltl<.f> ZA,RB,UIMM6_20 01011xxx01111010xxxxxxxxxx111110 */
-{ "setltl", 0x587a003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setltl", 0x587a003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setltl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11111010xxxxxxxxxx1xxxxx */
-{ "setltl", 0x58fa0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setltl", 0x58fa0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setltl<.f> RB,RBdup,SIMM12_20 01011xxx10111010xxxxxxxxxxxxxxxx */
-{ "setltl", 0x58ba0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setltl", 0x58ba0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setltl<.f> RA,XIMM,RC 0101110000111010x111xxxxxxxxxxxx */
-{ "setltl", 0x5c3a7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "setltl", 0x5c3a7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* setltl<.f> RA,RB,XIMM 01011xxx00111010xxxx111100xxxxxx */
-{ "setltl", 0x583a0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "setltl", 0x583a0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* setltl<.f> ZA,XIMM,RC 0101110000111010x111xxxxxx111110 */
-{ "setltl", 0x5c3a703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "setltl", 0x5c3a703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* setltl<.f> ZA,RB,XIMM 01011xxx00111010xxxx111100111110 */
-{ "setltl", 0x583a0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "setltl", 0x583a0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* setltl<.f><.cc> ZA,XIMM,RC 0101110011111010x111xxxxxx0xxxxx */
-{ "setltl", 0x5cfa7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "setltl", 0x5cfa7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* setltl<.f><.cc> RB,RBdup,XIMM 01011xxx11111010xxxx1111000xxxxx */
-{ "setltl", 0x58fa0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "setltl", 0x58fa0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* setltl<.f> RA,XIMM,UIMM6_20 0101110001111010x111xxxxxxxxxxxx */
-{ "setltl", 0x5c7a7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "setltl", 0x5c7a7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setltl<.f> ZA,XIMM,UIMM6_20 0101110001111010x111xxxxxx111110 */
-{ "setltl", 0x5c7a703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "setltl", 0x5c7a703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setltl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011111010x111xxxxxx1xxxxx */
-{ "setltl", 0x5cfa7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setltl", 0x5cfa7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setltl<.f> RA,LIMM,RC 0101111000111010x111xxxxxxxxxxxx */
-{ "setltl", 0x5e3a7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setltl", 0x5e3a7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setltl<.f> RA,RB,LIMM 01011xxx00111010xxxx111110xxxxxx */
-{ "setltl", 0x583a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setltl", 0x583a0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setltl<.f> ZA,LIMM,RC 0101111000111010x111xxxxxx111110 */
-{ "setltl", 0x5e3a703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setltl", 0x5e3a703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setltl<.f> ZA,RB,LIMM 01011xxx00111010xxxx111110111110 */
-{ "setltl", 0x583a0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setltl", 0x583a0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setltl<.f><.cc> ZA,LIMM,RC 0101111011111010x111xxxxxx0xxxxx */
-{ "setltl", 0x5efa7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setltl", 0x5efa7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setltl<.f><.cc> RB,RBdup,LIMM 01011xxx11111010xxxx1111100xxxxx */
-{ "setltl", 0x58fa0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setltl", 0x58fa0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setltl<.f> RA,LIMM,UIMM6_20 0101111001111010x111xxxxxxxxxxxx */
-{ "setltl", 0x5e7a7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setltl", 0x5e7a7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setltl<.f> ZA,LIMM,UIMM6_20 0101111001111010x111xxxxxx111110 */
-{ "setltl", 0x5e7a703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setltl", 0x5e7a703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setltl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011111010x111xxxxxx1xxxxx */
-{ "setltl", 0x5efa7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setltl", 0x5efa7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setltl<.f> ZA,XIMM,SIMM12_20 0101110010111010x111xxxxxxxxxxxx */
-{ "setltl", 0x5cba7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "setltl", 0x5cba7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* setltl<.f> ZA,LIMM,SIMM12_20 0101111010111010x111xxxxxxxxxxxx */
-{ "setltl", 0x5eba7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setltl", 0x5eba7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setltl<.f> RA,XIMM,XIMMdup 0101110000111010x111111100xxxxxx */
-{ "setltl", 0x5c3a7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "setltl", 0x5c3a7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* setltl<.f> ZA,XIMM,XIMMdup 0101110000111010x111111100111110 */
-{ "setltl", 0x5c3a7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "setltl", 0x5c3a7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* setltl<.f><.cc> ZA,XIMM,XIMMdup 0101110011111010x1111111000xxxxx */
-{ "setltl", 0x5cfa7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "setltl", 0x5cfa7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* setltl<.f> RA,LIMM,LIMMdup 0101111000111010x111111110xxxxxx */
-{ "setltl", 0x5e3a7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setltl", 0x5e3a7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setltl<.f> ZA,LIMM,LIMMdup 0101111000111010x111111110111110 */
-{ "setltl", 0x5e3a7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setltl", 0x5e3a7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setltl<.f><.cc> ZA,LIMM,LIMMdup 0101111011111010x1111111100xxxxx */
-{ "setltl", 0x5efa7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setltl", 0x5efa7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setne<.f> RA,RB,RC 00100xxx00111001xxxxxxxxxxxxxxxx */
-{ "setne", 0x20390000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "setne", 0x20390000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setne<.f> ZA,RB,RC 00100xxx00111001xxxxxxxxxx111110 */
-{ "setne", 0x2039003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "setne", 0x2039003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setne<.f><.cc> RB,RBdup,RC 00100xxx11111001xxxxxxxxxx0xxxxx */
-{ "setne", 0x20f90000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setne", 0x20f90000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setne<.f> RA,RB,UIMM6_20 00100xxx01111001xxxxxxxxxxxxxxxx */
-{ "setne", 0x20790000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setne", 0x20790000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setne<.f> ZA,RB,UIMM6_20 00100xxx01111001xxxxxxxxxx111110 */
-{ "setne", 0x2079003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setne", 0x2079003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setne<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11111001xxxxxxxxxx1xxxxx */
-{ "setne", 0x20f90020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setne", 0x20f90020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setne<.f> RB,RBdup,SIMM12_20 00100xxx10111001xxxxxxxxxxxxxxxx */
-{ "setne", 0x20b90000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setne", 0x20b90000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setne<.f> RA,LIMM,RC 0010011000111001x111xxxxxxxxxxxx */
-{ "setne", 0x26397000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setne", 0x26397000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setne<.f> RA,RB,LIMM 00100xxx00111001xxxx111110xxxxxx */
-{ "setne", 0x20390f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setne", 0x20390f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setne<.f> ZA,LIMM,RC 0010011000111001x111xxxxxx111110 */
-{ "setne", 0x2639703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setne", 0x2639703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setne<.f> ZA,RB,LIMM 00100xxx00111001xxxx111110111110 */
-{ "setne", 0x20390fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setne", 0x20390fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setne<.f><.cc> RB,RBdup,LIMM 00100xxx11111001xxxx1111100xxxxx */
-{ "setne", 0x20f90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setne", 0x20f90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setne<.f><.cc> ZA,LIMM,RC 0010011011111001x111xxxxxx0xxxxx */
-{ "setne", 0x26f97000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setne", 0x26f97000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setne<.f> RA,LIMM,UIMM6_20 0010011001111001x111xxxxxxxxxxxx */
-{ "setne", 0x26797000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setne", 0x26797000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setne<.f> ZA,LIMM,UIMM6_20 0010011001111001x111xxxxxx111110 */
-{ "setne", 0x2679703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setne", 0x2679703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setne<.f><.cc> ZA,LIMM,UIMM6_20 0010011011111001x111xxxxxx1xxxxx */
-{ "setne", 0x26f97020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setne", 0x26f97020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setne<.f> ZA,LIMM,SIMM12_20 0010011010111001x111xxxxxxxxxxxx */
-{ "setne", 0x26b97000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setne", 0x26b97000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setne<.f> RA,LIMM,LIMMdup 0010011000111001x111111110xxxxxx */
-{ "setne", 0x26397f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setne", 0x26397f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setne<.f> ZA,LIMM,LIMMdup 0010011000111001x111111110111110 */
-{ "setne", 0x26397fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setne", 0x26397fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setne<.f><.cc> ZA,LIMM,LIMMdup 0010011011111001x1111111100xxxxx */
-{ "setne", 0x26f97f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setne", 0x26f97f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* setnel<.f> RA,RB,RC 01011xxx00111001xxxxxxxxxxxxxxxx */
-{ "setnel", 0x58390000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "setnel", 0x58390000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* setnel<.f> ZA,RB,RC 01011xxx00111001xxxxxxxxxx111110 */
-{ "setnel", 0x5839003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "setnel", 0x5839003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* setnel<.f><.cc> RB,RBdup,RC 01011xxx11111001xxxxxxxxxx0xxxxx */
-{ "setnel", 0x58f90000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "setnel", 0x58f90000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* setnel<.f> RA,RB,UIMM6_20 01011xxx01111001xxxxxxxxxxxxxxxx */
-{ "setnel", 0x58790000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "setnel", 0x58790000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* setnel<.f> ZA,RB,UIMM6_20 01011xxx01111001xxxxxxxxxx111110 */
-{ "setnel", 0x5879003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "setnel", 0x5879003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* setnel<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11111001xxxxxxxxxx1xxxxx */
-{ "setnel", 0x58f90020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "setnel", 0x58f90020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* setnel<.f> RB,RBdup,SIMM12_20 01011xxx10111001xxxxxxxxxxxxxxxx */
-{ "setnel", 0x58b90000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "setnel", 0x58b90000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* setnel<.f> RA,XIMM,RC 0101110000111001x111xxxxxxxxxxxx */
-{ "setnel", 0x5c397000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "setnel", 0x5c397000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* setnel<.f> RA,RB,XIMM 01011xxx00111001xxxx111100xxxxxx */
-{ "setnel", 0x58390f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "setnel", 0x58390f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* setnel<.f> ZA,XIMM,RC 0101110000111001x111xxxxxx111110 */
-{ "setnel", 0x5c39703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "setnel", 0x5c39703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* setnel<.f> ZA,RB,XIMM 01011xxx00111001xxxx111100111110 */
-{ "setnel", 0x58390f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "setnel", 0x58390f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* setnel<.f><.cc> ZA,XIMM,RC 0101110011111001x111xxxxxx0xxxxx */
-{ "setnel", 0x5cf97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "setnel", 0x5cf97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* setnel<.f><.cc> RB,RBdup,XIMM 01011xxx11111001xxxx1111000xxxxx */
-{ "setnel", 0x58f90f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "setnel", 0x58f90f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* setnel<.f> RA,XIMM,UIMM6_20 0101110001111001x111xxxxxxxxxxxx */
-{ "setnel", 0x5c797000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "setnel", 0x5c797000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setnel<.f> ZA,XIMM,UIMM6_20 0101110001111001x111xxxxxx111110 */
-{ "setnel", 0x5c79703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "setnel", 0x5c79703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* setnel<.f><.cc> ZA,XIMM,UIMM6_20 0101110011111001x111xxxxxx1xxxxx */
-{ "setnel", 0x5cf97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setnel", 0x5cf97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setnel<.f> RA,LIMM,RC 0101111000111001x111xxxxxxxxxxxx */
-{ "setnel", 0x5e397000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "setnel", 0x5e397000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* setnel<.f> RA,RB,LIMM 01011xxx00111001xxxx111110xxxxxx */
-{ "setnel", 0x58390f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "setnel", 0x58390f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* setnel<.f> ZA,LIMM,RC 0101111000111001x111xxxxxx111110 */
-{ "setnel", 0x5e39703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "setnel", 0x5e39703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* setnel<.f> ZA,RB,LIMM 01011xxx00111001xxxx111110111110 */
-{ "setnel", 0x58390fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "setnel", 0x58390fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* setnel<.f><.cc> ZA,LIMM,RC 0101111011111001x111xxxxxx0xxxxx */
-{ "setnel", 0x5ef97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "setnel", 0x5ef97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* setnel<.f><.cc> RB,RBdup,LIMM 01011xxx11111001xxxx1111100xxxxx */
-{ "setnel", 0x58f90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "setnel", 0x58f90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* setnel<.f> RA,LIMM,UIMM6_20 0101111001111001x111xxxxxxxxxxxx */
-{ "setnel", 0x5e797000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "setnel", 0x5e797000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setnel<.f> ZA,LIMM,UIMM6_20 0101111001111001x111xxxxxx111110 */
-{ "setnel", 0x5e79703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "setnel", 0x5e79703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* setnel<.f><.cc> ZA,LIMM,UIMM6_20 0101111011111001x111xxxxxx1xxxxx */
-{ "setnel", 0x5ef97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "setnel", 0x5ef97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* setnel<.f> ZA,XIMM,SIMM12_20 0101110010111001x111xxxxxxxxxxxx */
-{ "setnel", 0x5cb97000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "setnel", 0x5cb97000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* setnel<.f> ZA,LIMM,SIMM12_20 0101111010111001x111xxxxxxxxxxxx */
-{ "setnel", 0x5eb97000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "setnel", 0x5eb97000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* setnel<.f> RA,XIMM,XIMMdup 0101110000111001x111111100xxxxxx */
-{ "setnel", 0x5c397f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "setnel", 0x5c397f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* setnel<.f> ZA,XIMM,XIMMdup 0101110000111001x111111100111110 */
-{ "setnel", 0x5c397f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "setnel", 0x5c397f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* setnel<.f><.cc> ZA,XIMM,XIMMdup 0101110011111001x1111111000xxxxx */
-{ "setnel", 0x5cf97f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "setnel", 0x5cf97f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* setnel<.f> RA,LIMM,LIMMdup 0101111000111001x111111110xxxxxx */
-{ "setnel", 0x5e397f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "setnel", 0x5e397f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* setnel<.f> ZA,LIMM,LIMMdup 0101111000111001x111111110111110 */
-{ "setnel", 0x5e397fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "setnel", 0x5e397fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* setnel<.f><.cc> ZA,LIMM,LIMMdup 0101111011111001x1111111100xxxxx */
-{ "setnel", 0x5ef97f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "setnel", 0x5ef97f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sexb<.f> RB,RC 00100xxx00101111xxxxxxxxxx000101 */
-{ "sexb", 0x202f0005, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "sexb", 0x202f0005, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* sexb<.f> ZA,RC 0010011000101111x111xxxxxx000101 */
-{ "sexb", 0x262f7005, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "sexb", 0x262f7005, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* sexb<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx000101 */
-{ "sexb", 0x206f0005, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "sexb", 0x206f0005, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* sexb<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx000101 */
-{ "sexb", 0x266f7005, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "sexb", 0x266f7005, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* sexb<.f> RB,LIMM 00100xxx00101111xxxx111110000101 */
-{ "sexb", 0x202f0f85, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "sexb", 0x202f0f85, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* sexb<.f> ZA,LIMM 0010011000101111x111111110000101 */
-{ "sexb", 0x262f7f85, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "sexb", 0x262f7f85, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* sexbl<.f> RB,RC 01011xxx00101111xxxxxxxxxx000101 */
-{ "sexbl", 0x582f0005, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "sexbl", 0x582f0005, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* sexbl<.f> ZA,RC 0101111000101111x111xxxxxx000101 */
-{ "sexbl", 0x5e2f7005, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "sexbl", 0x5e2f7005, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* sexbl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx000101 */
-{ "sexbl", 0x586f0005, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "sexbl", 0x586f0005, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* sexbl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx000101 */
-{ "sexbl", 0x5e6f7005, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "sexbl", 0x5e6f7005, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* sexbl<.f> RB,XIMM 01011xxx00101111xxxx111100000101 */
-{ "sexbl", 0x582f0f05, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "sexbl", 0x582f0f05, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* sexbl<.f> ZA,XIMM 0101111000101111x111111100000101 */
-{ "sexbl", 0x5e2f7f05, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "sexbl", 0x5e2f7f05, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* sexbl<.f> RB,LIMM 01011xxx00101111xxxx111110000101 */
-{ "sexbl", 0x582f0f85, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "sexbl", 0x582f0f85, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* sexbl<.f> ZA,LIMM 0101111000101111x111111110000101 */
-{ "sexbl", 0x5e2f7f85, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "sexbl", 0x5e2f7f85, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* sexb_s RB_S,RC_S 01111xxxxxx01101 */
-{ "sexb_s", 0x0000780d, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RC_S }, { 0 } }
+{ "sexb_s", 0x0000780d, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* sexh<.f> RB,RC 00100xxx00101111xxxxxxxxxx000110 */
-{ "sexh", 0x202f0006, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, RC }, { C_F } }
+{ "sexh", 0x202f0006, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* sexh<.f> ZA,RC 0010011000101111x111xxxxxx000110 */
-{ "sexh", 0x262f7006, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "sexh", 0x262f7006, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* sexh<.f> RB,UIMM6_20 00100xxx01101111xxxxxxxxxx000110 */
-{ "sexh", 0x206f0006, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "sexh", 0x206f0006, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* sexh<.f> ZA,UIMM6_20 0010011001101111x111xxxxxx000110 */
-{ "sexh", 0x266f7006, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "sexh", 0x266f7006, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* sexh<.f> RB,LIMM 00100xxx00101111xxxx111110000110 */
-{ "sexh", 0x202f0f86, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "sexh", 0x202f0f86, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* sexh<.f> ZA,LIMM 0010011000101111x111111110000110 */
-{ "sexh", 0x262f7f86, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "sexh", 0x262f7f86, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* sexhl<.f> RB,RC 01011xxx00101111xxxxxxxxxx000110 */
-{ "sexhl", 0x582f0006, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "sexhl", 0x582f0006, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* sexhl<.f> ZA,RC 0101111000101111x111xxxxxx000110 */
-{ "sexhl", 0x5e2f7006, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "sexhl", 0x5e2f7006, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* sexhl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx000110 */
-{ "sexhl", 0x586f0006, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "sexhl", 0x586f0006, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* sexhl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx000110 */
-{ "sexhl", 0x5e6f7006, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "sexhl", 0x5e6f7006, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* sexhl<.f> RB,XIMM 01011xxx00101111xxxx111100000110 */
-{ "sexhl", 0x582f0f06, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "sexhl", 0x582f0f06, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* sexhl<.f> ZA,XIMM 0101111000101111x111111100000110 */
-{ "sexhl", 0x5e2f7f06, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "sexhl", 0x5e2f7f06, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* sexhl<.f> RB,LIMM 01011xxx00101111xxxx111110000110 */
-{ "sexhl", 0x582f0f86, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "sexhl", 0x582f0f86, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* sexhl<.f> ZA,LIMM 0101111000101111x111111110000110 */
-{ "sexhl", 0x5e2f7f86, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "sexhl", 0x5e2f7f86, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* sexh_s RB_S,RC_S 01111xxxxxx01110 */
-{ "sexh_s", 0x0000780e, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, RC_S }, { 0 } }
+{ "sexh_s", 0x0000780e, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* sexwl<.f> RB,RC 01011xxx00101111xxxxxxxxxx000111 */
-{ "sexwl", 0x582f0007, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "sexwl", 0x582f0007, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* sexwl<.f> ZA,RC 0101111000101111x111xxxxxx000111 */
-{ "sexwl", 0x5e2f7007, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "sexwl", 0x5e2f7007, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* sexwl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx000111 */
-{ "sexwl", 0x586f0007, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "sexwl", 0x586f0007, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* sexwl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx000111 */
-{ "sexwl", 0x5e6f7007, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "sexwl", 0x5e6f7007, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* sexwl<.f> RB,XIMM 01011xxx00101111xxxx111100000111 */
-{ "sexwl", 0x582f0f07, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "sexwl", 0x582f0f07, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* sexwl<.f> ZA,XIMM 0101111000101111x111111100000111 */
-{ "sexwl", 0x5e2f7f07, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "sexwl", 0x5e2f7f07, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* sexwl<.f> RB,LIMM 01011xxx00101111xxxx111110000111 */
-{ "sexwl", 0x582f0f87, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "sexwl", 0x582f0f87, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* sexwl<.f> ZA,LIMM 0101111000101111x111111110000111 */
-{ "sexwl", 0x5e2f7f87, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "sexwl", 0x5e2f7f87, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* sleep RC 00100001001011110000xxxxxx111111 */
-{ "sleep", 0x212f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { RC }, { 0 } }
+{ "sleep", 0x212f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { RC }, { 0 } }
 
 /* sleep UIMM6_20 00100001011011110000xxxxxx111111 */
-{ "sleep", 0x216f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { UIMM6_20 }, { 0 } }
+{ "sleep", 0x216f003f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* sleep LIMM 00100001001011110000111110111111 */
-{ "sleep", 0x212f0fbf, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { LIMM }, { 0 } }
+{ "sleep", 0x212f0fbf, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { LIMM }, { 0 } }
 
 /* sleep  00100001011011110000000000111111 */
-{ "sleep", 0x216f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, {  }, { 0 } }
+{ "sleep", 0x216f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* sr RB_CHK,BRAKET,RC,BRAKETdup 00100xxx00101011xxxxxxxxxxxxxxxx */
-{ "sr", 0x202b0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "sr", 0x202b0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* sr RB_CHK,BRAKET,UIMM6_20,BRAKETdup 00100xxx01101011xxxxxxxxxx000000 */
-{ "sr", 0x206b0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "sr", 0x206b0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* sr RB_CHK,BRAKET,SIMM12_20,BRAKETdup 00100xxx10101011xxxxxxxxxxxxxxxx */
-{ "sr", 0x20ab0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "sr", 0x20ab0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* sr LIMM,BRAKET,RC,BRAKETdup 0010011000101011x111xxxxxxxxxxxx */
-{ "sr", 0x262b7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "sr", 0x262b7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* sr RB_CHK,BRAKET,LIMM,BRAKETdup 00100xxx00101011xxxx111110xxxxxx */
-{ "sr", 0x202b0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "sr", 0x202b0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* sr LIMM,BRAKET,UIMM6_20,BRAKETdup 0010011001101011x111xxxxxx000000 */
-{ "sr", 0x266b7000, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "sr", 0x266b7000, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* sr LIMM,BRAKET,SIMM12_20,BRAKETdup 0010011010101011x111xxxxxxxxxxxx */
-{ "sr", 0x26ab7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "sr", 0x26ab7000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* sr LIMM,BRAKET,LIMMdup,BRAKETdup 0010011000101011x111111110xxxxxx */
-{ "sr", 0x262b7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 } }
+{ "sr", 0x262b7f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, AUXREG, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 } }
 
 /* srl RB_CHK,BRAKET,RC,BRAKETdup 01011xxx001010110xxxxxxxxxxxxxxx */
-{ "srl", 0x582b0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
+{ "srl", 0x582b0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 } }
 
 /* srl RB_CHK,BRAKET,UIMM6_20,BRAKETdup 01011xxx011010110xxxxxxxxxxxxxxx */
-{ "srl", 0x586b0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
+{ "srl", 0x586b0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 } }
 
 /* srl RB_CHK,BRAKET,SIMM12_20,BRAKETdup 01011xxx101010110xxxxxxxxxxxxxxx */
-{ "srl", 0x58ab0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
+{ "srl", 0x58ab0000, 0xf8ff8000, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 } }
 
 /* srl RB_CHK,BRAKET,XIMM,BRAKETdup 01011xxx001010110xxx111100xxxxxx */
-{ "srl", 0x582b0f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, XIMM, BRAKETdup }, { 0 } }
+{ "srl", 0x582b0f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, XIMM, BRAKETdup }, { 0 } }
 
 /* srl RB_CHK,BRAKET,LIMM,BRAKETdup 01011xxx001010110xxx111110xxxxxx */
-{ "srl", 0x582b0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "srl", 0x582b0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, AUXREG, ARC_INSN_SUBCLASS_NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* st<.di><.aa> RC,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxxxxxxx0 */
-{ "st", 0x18000000, 0xf8000001, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 } }
+{ "st", 0x18000000, 0xf8000001, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 } }
 
 /* st<.di><.aa> W6,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxxxxxxx1 */
-{ "st", 0x18000001, 0xf8000001, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZW6, C_DI26, C_AA27 } }
+{ "st", 0x18000001, 0xf8000001, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZW6, C_DI26, C_AA27 } }
 
 /* st<.aa> W6,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxx0xxxx1 */
-{ "st", 0x18000001, 0xf8000021, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZH1, C_AA27 } }
+{ "st", 0x18000001, 0xf8000021, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZH1, C_AA27 } }
 
 /* st<.di><.aa> LIMM,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxx111110xxxxx0 */
-{ "st", 0x18000f80, 0xf8000fc1, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 } }
+{ "st", 0x18000f80, 0xf8000fc1, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 } }
 
 /* st<.di> RC,BRAKET,LIMM,SIMM9_8,BRAKETdup 00011110xxxxxxxxx111xxxxxxxxxxx0 */
-{ "st", 0x1e007000, 0xff007001, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { RC, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26 } }
+{ "st", 0x1e007000, 0xff007001, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RC, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26 } }
 
 /* st<.di> W6,BRAKET,LIMM,SIMM9_8,BRAKETdup 00011110xxxxxxxxx111xxxxxxxxxxx1 */
-{ "st", 0x1e007001, 0xff007001, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZW6, C_DI26 } }
+{ "st", 0x1e007001, 0xff007001, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZW6, C_DI26 } }
 
 /* st W6,BRAKET,LIMM,SIMM9_8,BRAKETdup 00011110xxxxxxxxx111xxxxxx0xxxx1 */
-{ "st", 0x1e007001, 0xff007021, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZH1 } }
+{ "st", 0x1e007001, 0xff007021, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZH1 } }
 
 /* st<.di> LIMM,BRAKET,LIMMdup,SIMM9_8,BRAKETdup 00011110xxxxxxxxx111111110xxxxx0 */
-{ "st", 0x1e007f80, 0xff007fc1, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26 } }
+{ "st", 0x1e007f80, 0xff007fc1, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26 } }
 
 /* stb_s RC_S,BRAKET,RB_S,UIMM5_11_S,BRAKETdup 10101xxxxxxxxxxx */
-{ "stb_s", 0x0000a800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B } }
+{ "stb_s", 0x0000a800, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B } }
 
 /* stb_s RB_S,BRAKET,SP_S,UIMM7_A32_11_S,BRAKETdup 11000xxx011xxxxx */
-{ "stb_s", 0x0000c060, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B } }
+{ "stb_s", 0x0000c060, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B } }
 
 /* std<.di><.aa> RCD,BRAKET,RB,BRAKETdup 00011xxx000000000xxxxxxxxxxxx110 */
-{ "std", 0x18000006, 0xf8ff8007, ARC_OPCODE_ARC32, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x18000006, 0xf8ff8007, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> W6,BRAKET,RB,BRAKETdup 00011xxx000000000xxxxxxxxxxxx111 */
-{ "std", 0x18000007, 0xf8ff8007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x18000007, 0xf8ff8007, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> LIMM,BRAKET,RB,BRAKETdup 00011xxx000000000xxx111110xxx110 */
-{ "std", 0x18000f86, 0xf8ff8fc7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x18000f86, 0xf8ff8fc7, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> RCD,BRAKET,LIMM,BRAKETdup 00011110000000000111xxxxxxxxx110 */
-{ "std", 0x1e007006, 0xfffff007, ARC_OPCODE_ARC32, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x1e007006, 0xfffff007, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> W6,BRAKET,LIMM,BRAKETdup 00011110000000000111xxxxxxxxx111 */
-{ "std", 0x1e007007, 0xfffff007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x1e007007, 0xfffff007, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> LIMM,BRAKET,LIMMdup,BRAKETdup 00011110000000000111111110xxx110 */
-{ "std", 0x1e007f86, 0xffffffc7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x1e007f86, 0xffffffc7, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> RCD,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxxxxx110 */
-{ "std", 0x18000006, 0xf8000007, ARC_OPCODE_ARC32, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x18000006, 0xf8000007, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> W6,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxxxxxxxxxxx111 */
-{ "std", 0x18000007, 0xf8000007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x18000007, 0xf8000007, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> LIMM,BRAKET,RB,SIMM9_8,BRAKETdup 00011xxxxxxxxxxxxxxx111110xxx110 */
-{ "std", 0x18000f86, 0xf8000fc7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x18000f86, 0xf8000fc7, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> RCD,BRAKET,LIMM,SIMM9_8,BRAKETdup 00011110xxxxxxxxx111xxxxxxxxx110 */
-{ "std", 0x1e007006, 0xff007007, ARC_OPCODE_ARC32, STORE, NONE, { RCD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x1e007006, 0xff007007, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RCD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> W6,BRAKET,LIMM,SIMM9_8,BRAKETdup 00011110xxxxxxxxx111xxxxxxxxx111 */
-{ "std", 0x1e007007, 0xff007007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x1e007007, 0xff007007, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* std<.di><.aa> LIMM,BRAKET,LIMMdup,SIMM9_8,BRAKETdup 00011110xxxxxxxxx111111110xxx110 */
-{ "std", 0x1e007f86, 0xff007fc7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
+{ "std", 0x1e007f86, 0xff007fc7, ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 } }
 
 /* sth_s RC_S,BRAKET,RB_S,UIMM6_A16_11_S,BRAKETdup 10110xxxxxxxxxxx */
-{ "sth_s", 0x0000b000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H } }
+{ "sth_s", 0x0000b000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H } }
 
 /* st_s RB_S,BRAKET,SP_S,UIMM7_A32_11_S,BRAKETdup 11000xxx010xxxxx */
-{ "st_s", 0x0000c040, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 } }
+{ "st_s", 0x0000c040, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 } }
 
 /* st_s RC_S,BRAKET,RB_S,UIMM7_A32_11_S,BRAKETdup 10100xxxxxxxxxxx */
-{ "st_s", 0x0000a000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 } }
+{ "st_s", 0x0000a000, 0x0000f800, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, ARC_INSN_SUBCLASS_NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 } }
 
 /* st_s R0_S,BRAKET,GP_S,SIMM11_A32_13_S,BRAKETdup 01010xxxxxx10xxx */
 { "st_s", 0x00005010, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, STORE, CD, { R0_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 } }
 
 /* sub<.f> RA,RB,RC 00100xxx00000010xxxxxxxxxxxxxxxx */
-{ "sub", 0x20020000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, RC }, { C_F } }
+{ "sub", 0x20020000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sub<.f> ZA,RB,RC 00100xxx00000010xxxxxxxxxx111110 */
-{ "sub", 0x2002003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, RC }, { C_F } }
+{ "sub", 0x2002003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sub<.f><.cc> RB,RBdup,RC 00100xxx11000010xxxxxxxxxx0xxxxx */
-{ "sub", 0x20c20000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sub", 0x20c20000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sub<.f> RA,RB,UIMM6_20 00100xxx01000010xxxxxxxxxxxxxxxx */
-{ "sub", 0x20420000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sub", 0x20420000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sub<.f> ZA,RB,UIMM6_20 00100xxx01000010xxxxxxxxxx111110 */
-{ "sub", 0x2042003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sub", 0x2042003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sub<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11000010xxxxxxxxxx1xxxxx */
-{ "sub", 0x20c20020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sub", 0x20c20020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub<.f> RB,RBdup,SIMM12_20 00100xxx10000010xxxxxxxxxxxxxxxx */
-{ "sub", 0x20820000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sub", 0x20820000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sub<.f> RA,LIMM,RC 0010011000000010x111xxxxxxxxxxxx */
-{ "sub", 0x26027000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sub", 0x26027000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sub<.f> RA,RB,LIMM 00100xxx00000010xxxx111110xxxxxx */
-{ "sub", 0x20020f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sub", 0x20020f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sub<.f> ZA,LIMM,RC 0010011000000010x111xxxxxx111110 */
-{ "sub", 0x2602703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sub", 0x2602703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sub<.f> ZA,RB,LIMM 00100xxx00000010xxxx111110111110 */
-{ "sub", 0x20020fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sub", 0x20020fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sub<.f><.cc> RB,RBdup,LIMM 00100xxx11000010xxxx1111100xxxxx */
-{ "sub", 0x20c20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sub", 0x20c20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sub<.f><.cc> ZA,LIMM,RC 0010011011000010x111xxxxxx0xxxxx */
-{ "sub", 0x26c27000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sub", 0x26c27000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sub<.f> RA,LIMM,UIMM6_20 0010011001000010x111xxxxxxxxxxxx */
-{ "sub", 0x26427000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub", 0x26427000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub<.f> ZA,LIMM,UIMM6_20 0010011001000010x111xxxxxx111110 */
-{ "sub", 0x2642703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub", 0x2642703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub<.f><.cc> ZA,LIMM,UIMM6_20 0010011011000010x111xxxxxx1xxxxx */
-{ "sub", 0x26c27020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub", 0x26c27020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub<.f> ZA,LIMM,SIMM12_20 0010011010000010x111xxxxxxxxxxxx */
-{ "sub", 0x26827000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sub", 0x26827000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sub<.f> RA,LIMM,LIMMdup 0010011000000010x111111110xxxxxx */
-{ "sub", 0x26027f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sub", 0x26027f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sub<.f> ZA,LIMM,LIMMdup 0010011000000010x111111110111110 */
-{ "sub", 0x26027fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sub", 0x26027fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sub<.f><.cc> ZA,LIMM,LIMMdup 0010011011000010x1111111100xxxxx */
-{ "sub", 0x26c27f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sub", 0x26c27f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sub1<.f> RA,RB,RC 00100xxx00010111xxxxxxxxxxxxxxxx */
-{ "sub1", 0x20170000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, RC }, { C_F } }
+{ "sub1", 0x20170000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sub1<.f> ZA,RB,RC 00100xxx00010111xxxxxxxxxx111110 */
-{ "sub1", 0x2017003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, RC }, { C_F } }
+{ "sub1", 0x2017003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sub1<.f><.cc> RB,RBdup,RC 00100xxx11010111xxxxxxxxxx0xxxxx */
-{ "sub1", 0x20d70000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sub1", 0x20d70000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sub1<.f> RA,RB,UIMM6_20 00100xxx01010111xxxxxxxxxxxxxxxx */
-{ "sub1", 0x20570000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sub1", 0x20570000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sub1<.f> ZA,RB,UIMM6_20 00100xxx01010111xxxxxxxxxx111110 */
-{ "sub1", 0x2057003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sub1", 0x2057003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sub1<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11010111xxxxxxxxxx1xxxxx */
-{ "sub1", 0x20d70020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sub1", 0x20d70020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub1<.f> RB,RBdup,SIMM12_20 00100xxx10010111xxxxxxxxxxxxxxxx */
-{ "sub1", 0x20970000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sub1", 0x20970000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sub1<.f> RA,LIMM,RC 0010011000010111x111xxxxxxxxxxxx */
-{ "sub1", 0x26177000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sub1", 0x26177000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sub1<.f> RA,RB,LIMM 00100xxx00010111xxxx111110xxxxxx */
-{ "sub1", 0x20170f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sub1", 0x20170f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sub1<.f> ZA,LIMM,RC 0010011000010111x111xxxxxx111110 */
-{ "sub1", 0x2617703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sub1", 0x2617703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sub1<.f> ZA,RB,LIMM 00100xxx00010111xxxx111110111110 */
-{ "sub1", 0x20170fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sub1", 0x20170fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sub1<.f><.cc> RB,RBdup,LIMM 00100xxx11010111xxxx1111100xxxxx */
-{ "sub1", 0x20d70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sub1", 0x20d70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sub1<.f><.cc> ZA,LIMM,RC 0010011011010111x111xxxxxx0xxxxx */
-{ "sub1", 0x26d77000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sub1", 0x26d77000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sub1<.f> RA,LIMM,UIMM6_20 0010011001010111x111xxxxxxxxxxxx */
-{ "sub1", 0x26577000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub1", 0x26577000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub1<.f> ZA,LIMM,UIMM6_20 0010011001010111x111xxxxxx111110 */
-{ "sub1", 0x2657703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub1", 0x2657703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub1<.f><.cc> ZA,LIMM,UIMM6_20 0010011011010111x111xxxxxx1xxxxx */
-{ "sub1", 0x26d77020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub1", 0x26d77020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub1<.f> ZA,LIMM,SIMM12_20 0010011010010111x111xxxxxxxxxxxx */
-{ "sub1", 0x26977000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sub1", 0x26977000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sub1<.f> RA,LIMM,LIMMdup 0010011000010111x111111110xxxxxx */
-{ "sub1", 0x26177f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sub1", 0x26177f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sub1<.f> ZA,LIMM,LIMMdup 0010011000010111x111111110111110 */
-{ "sub1", 0x26177fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sub1", 0x26177fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sub1<.f><.cc> ZA,LIMM,LIMMdup 0010011011010111x1111111100xxxxx */
-{ "sub1", 0x26d77f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sub1", 0x26d77f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sub1l<.f> RA,RB,RC 01011xxx00010111xxxxxxxxxxxxxxxx */
-{ "sub1l", 0x58170000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "sub1l", 0x58170000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sub1l<.f> ZA,RB,RC 01011xxx00010111xxxxxxxxxx111110 */
-{ "sub1l", 0x5817003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "sub1l", 0x5817003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sub1l<.f><.cc> RB,RBdup,RC 01011xxx11010111xxxxxxxxxx0xxxxx */
-{ "sub1l", 0x58d70000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sub1l", 0x58d70000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sub1l<.f> RA,RB,UIMM6_20 01011xxx01010111xxxxxxxxxxxxxxxx */
-{ "sub1l", 0x58570000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sub1l", 0x58570000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sub1l<.f> ZA,RB,UIMM6_20 01011xxx01010111xxxxxxxxxx111110 */
-{ "sub1l", 0x5857003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sub1l", 0x5857003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sub1l<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11010111xxxxxxxxxx1xxxxx */
-{ "sub1l", 0x58d70020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sub1l", 0x58d70020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub1l<.f> RB,RBdup,SIMM12_20 01011xxx10010111xxxxxxxxxxxxxxxx */
-{ "sub1l", 0x58970000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sub1l", 0x58970000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sub1l<.f> RA,XIMM,RC 0101110000010111x111xxxxxxxxxxxx */
-{ "sub1l", 0x5c177000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "sub1l", 0x5c177000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* sub1l<.f> RA,RB,XIMM 01011xxx00010111xxxx111100xxxxxx */
-{ "sub1l", 0x58170f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "sub1l", 0x58170f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* sub1l<.f> ZA,XIMM,RC 0101110000010111x111xxxxxx111110 */
-{ "sub1l", 0x5c17703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "sub1l", 0x5c17703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* sub1l<.f> ZA,RB,XIMM 01011xxx00010111xxxx111100111110 */
-{ "sub1l", 0x58170f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "sub1l", 0x58170f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* sub1l<.f><.cc> ZA,XIMM,RC 0101110011010111x111xxxxxx0xxxxx */
-{ "sub1l", 0x5cd77000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "sub1l", 0x5cd77000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* sub1l<.f><.cc> RB,RBdup,XIMM 01011xxx11010111xxxx1111000xxxxx */
-{ "sub1l", 0x58d70f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "sub1l", 0x58d70f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* sub1l<.f> RA,XIMM,UIMM6_20 0101110001010111x111xxxxxxxxxxxx */
-{ "sub1l", 0x5c577000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "sub1l", 0x5c577000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sub1l<.f> ZA,XIMM,UIMM6_20 0101110001010111x111xxxxxx111110 */
-{ "sub1l", 0x5c57703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "sub1l", 0x5c57703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sub1l<.f><.cc> ZA,XIMM,UIMM6_20 0101110011010111x111xxxxxx1xxxxx */
-{ "sub1l", 0x5cd77020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub1l", 0x5cd77020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub1l<.f> RA,LIMM,RC 0101111000010111x111xxxxxxxxxxxx */
-{ "sub1l", 0x5e177000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sub1l", 0x5e177000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sub1l<.f> RA,RB,LIMM 01011xxx00010111xxxx111110xxxxxx */
-{ "sub1l", 0x58170f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sub1l", 0x58170f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sub1l<.f> ZA,LIMM,RC 0101111000010111x111xxxxxx111110 */
-{ "sub1l", 0x5e17703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sub1l", 0x5e17703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sub1l<.f> ZA,RB,LIMM 01011xxx00010111xxxx111110111110 */
-{ "sub1l", 0x58170fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sub1l", 0x58170fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sub1l<.f><.cc> ZA,LIMM,RC 0101111011010111x111xxxxxx0xxxxx */
-{ "sub1l", 0x5ed77000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sub1l", 0x5ed77000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sub1l<.f><.cc> RB,RBdup,LIMM 01011xxx11010111xxxx1111100xxxxx */
-{ "sub1l", 0x58d70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sub1l", 0x58d70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sub1l<.f> RA,LIMM,UIMM6_20 0101111001010111x111xxxxxxxxxxxx */
-{ "sub1l", 0x5e577000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub1l", 0x5e577000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub1l<.f> ZA,LIMM,UIMM6_20 0101111001010111x111xxxxxx111110 */
-{ "sub1l", 0x5e57703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub1l", 0x5e57703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub1l<.f><.cc> ZA,LIMM,UIMM6_20 0101111011010111x111xxxxxx1xxxxx */
-{ "sub1l", 0x5ed77020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub1l", 0x5ed77020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub1l<.f> ZA,XIMM,SIMM12_20 0101110010010111x111xxxxxxxxxxxx */
-{ "sub1l", 0x5c977000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "sub1l", 0x5c977000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* sub1l<.f> ZA,LIMM,SIMM12_20 0101111010010111x111xxxxxxxxxxxx */
-{ "sub1l", 0x5e977000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sub1l", 0x5e977000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sub1l<.f> RA,XIMM,XIMMdup 0101110000010111x111111100xxxxxx */
-{ "sub1l", 0x5c177f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "sub1l", 0x5c177f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* sub1l<.f> ZA,XIMM,XIMMdup 0101110000010111x111111100111110 */
-{ "sub1l", 0x5c177f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "sub1l", 0x5c177f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* sub1l<.f><.cc> ZA,XIMM,XIMMdup 0101110011010111x1111111000xxxxx */
-{ "sub1l", 0x5cd77f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "sub1l", 0x5cd77f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* sub1l<.f> RA,LIMM,LIMMdup 0101111000010111x111111110xxxxxx */
-{ "sub1l", 0x5e177f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sub1l", 0x5e177f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sub1l<.f> ZA,LIMM,LIMMdup 0101111000010111x111111110111110 */
-{ "sub1l", 0x5e177fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sub1l", 0x5e177fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sub1l<.f><.cc> ZA,LIMM,LIMMdup 0101111011010111x1111111100xxxxx */
-{ "sub1l", 0x5ed77f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sub1l", 0x5ed77f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sub2<.f> RA,RB,RC 00100xxx00011000xxxxxxxxxxxxxxxx */
-{ "sub2", 0x20180000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, RC }, { C_F } }
+{ "sub2", 0x20180000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sub2<.f> ZA,RB,RC 00100xxx00011000xxxxxxxxxx111110 */
-{ "sub2", 0x2018003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, RC }, { C_F } }
+{ "sub2", 0x2018003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sub2<.f><.cc> RB,RBdup,RC 00100xxx11011000xxxxxxxxxx0xxxxx */
-{ "sub2", 0x20d80000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sub2", 0x20d80000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sub2<.f> RA,RB,UIMM6_20 00100xxx01011000xxxxxxxxxxxxxxxx */
-{ "sub2", 0x20580000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sub2", 0x20580000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sub2<.f> ZA,RB,UIMM6_20 00100xxx01011000xxxxxxxxxx111110 */
-{ "sub2", 0x2058003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sub2", 0x2058003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sub2<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11011000xxxxxxxxxx1xxxxx */
-{ "sub2", 0x20d80020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sub2", 0x20d80020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub2<.f> RB,RBdup,SIMM12_20 00100xxx10011000xxxxxxxxxxxxxxxx */
-{ "sub2", 0x20980000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sub2", 0x20980000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sub2<.f> RA,LIMM,RC 0010011000011000x111xxxxxxxxxxxx */
-{ "sub2", 0x26187000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sub2", 0x26187000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sub2<.f> RA,RB,LIMM 00100xxx00011000xxxx111110xxxxxx */
-{ "sub2", 0x20180f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sub2", 0x20180f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sub2<.f> ZA,LIMM,RC 0010011000011000x111xxxxxx111110 */
-{ "sub2", 0x2618703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sub2", 0x2618703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sub2<.f> ZA,RB,LIMM 00100xxx00011000xxxx111110111110 */
-{ "sub2", 0x20180fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sub2", 0x20180fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sub2<.f><.cc> RB,RBdup,LIMM 00100xxx11011000xxxx1111100xxxxx */
-{ "sub2", 0x20d80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sub2", 0x20d80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sub2<.f><.cc> ZA,LIMM,RC 0010011011011000x111xxxxxx0xxxxx */
-{ "sub2", 0x26d87000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sub2", 0x26d87000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sub2<.f> RA,LIMM,UIMM6_20 0010011001011000x111xxxxxxxxxxxx */
-{ "sub2", 0x26587000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub2", 0x26587000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub2<.f> ZA,LIMM,UIMM6_20 0010011001011000x111xxxxxx111110 */
-{ "sub2", 0x2658703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub2", 0x2658703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub2<.f><.cc> ZA,LIMM,UIMM6_20 0010011011011000x111xxxxxx1xxxxx */
-{ "sub2", 0x26d87020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub2", 0x26d87020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub2<.f> ZA,LIMM,SIMM12_20 0010011010011000x111xxxxxxxxxxxx */
-{ "sub2", 0x26987000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sub2", 0x26987000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sub2<.f> RA,LIMM,LIMMdup 0010011000011000x111111110xxxxxx */
-{ "sub2", 0x26187f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sub2", 0x26187f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sub2<.f> ZA,LIMM,LIMMdup 0010011000011000x111111110111110 */
-{ "sub2", 0x26187fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sub2", 0x26187fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sub2<.f><.cc> ZA,LIMM,LIMMdup 0010011011011000x1111111100xxxxx */
-{ "sub2", 0x26d87f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sub2", 0x26d87f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sub2l<.f> RA,RB,RC 01011xxx00011000xxxxxxxxxxxxxxxx */
-{ "sub2l", 0x58180000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "sub2l", 0x58180000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sub2l<.f> ZA,RB,RC 01011xxx00011000xxxxxxxxxx111110 */
-{ "sub2l", 0x5818003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "sub2l", 0x5818003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sub2l<.f><.cc> RB,RBdup,RC 01011xxx11011000xxxxxxxxxx0xxxxx */
-{ "sub2l", 0x58d80000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sub2l", 0x58d80000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sub2l<.f> RA,RB,UIMM6_20 01011xxx01011000xxxxxxxxxxxxxxxx */
-{ "sub2l", 0x58580000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sub2l", 0x58580000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sub2l<.f> ZA,RB,UIMM6_20 01011xxx01011000xxxxxxxxxx111110 */
-{ "sub2l", 0x5858003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sub2l", 0x5858003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sub2l<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11011000xxxxxxxxxx1xxxxx */
-{ "sub2l", 0x58d80020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sub2l", 0x58d80020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub2l<.f> RB,RBdup,SIMM12_20 01011xxx10011000xxxxxxxxxxxxxxxx */
-{ "sub2l", 0x58980000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sub2l", 0x58980000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sub2l<.f> RA,XIMM,RC 0101110000011000x111xxxxxxxxxxxx */
-{ "sub2l", 0x5c187000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "sub2l", 0x5c187000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* sub2l<.f> RA,RB,XIMM 01011xxx00011000xxxx111100xxxxxx */
-{ "sub2l", 0x58180f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "sub2l", 0x58180f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* sub2l<.f> ZA,XIMM,RC 0101110000011000x111xxxxxx111110 */
-{ "sub2l", 0x5c18703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "sub2l", 0x5c18703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* sub2l<.f> ZA,RB,XIMM 01011xxx00011000xxxx111100111110 */
-{ "sub2l", 0x58180f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "sub2l", 0x58180f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* sub2l<.f><.cc> ZA,XIMM,RC 0101110011011000x111xxxxxx0xxxxx */
-{ "sub2l", 0x5cd87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "sub2l", 0x5cd87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* sub2l<.f><.cc> RB,RBdup,XIMM 01011xxx11011000xxxx1111000xxxxx */
-{ "sub2l", 0x58d80f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "sub2l", 0x58d80f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* sub2l<.f> RA,XIMM,UIMM6_20 0101110001011000x111xxxxxxxxxxxx */
-{ "sub2l", 0x5c587000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "sub2l", 0x5c587000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sub2l<.f> ZA,XIMM,UIMM6_20 0101110001011000x111xxxxxx111110 */
-{ "sub2l", 0x5c58703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "sub2l", 0x5c58703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sub2l<.f><.cc> ZA,XIMM,UIMM6_20 0101110011011000x111xxxxxx1xxxxx */
-{ "sub2l", 0x5cd87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub2l", 0x5cd87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub2l<.f> RA,LIMM,RC 0101111000011000x111xxxxxxxxxxxx */
-{ "sub2l", 0x5e187000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sub2l", 0x5e187000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sub2l<.f> RA,RB,LIMM 01011xxx00011000xxxx111110xxxxxx */
-{ "sub2l", 0x58180f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sub2l", 0x58180f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sub2l<.f> ZA,LIMM,RC 0101111000011000x111xxxxxx111110 */
-{ "sub2l", 0x5e18703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sub2l", 0x5e18703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sub2l<.f> ZA,RB,LIMM 01011xxx00011000xxxx111110111110 */
-{ "sub2l", 0x58180fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sub2l", 0x58180fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sub2l<.f><.cc> ZA,LIMM,RC 0101111011011000x111xxxxxx0xxxxx */
-{ "sub2l", 0x5ed87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sub2l", 0x5ed87000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sub2l<.f><.cc> RB,RBdup,LIMM 01011xxx11011000xxxx1111100xxxxx */
-{ "sub2l", 0x58d80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sub2l", 0x58d80f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sub2l<.f> RA,LIMM,UIMM6_20 0101111001011000x111xxxxxxxxxxxx */
-{ "sub2l", 0x5e587000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub2l", 0x5e587000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub2l<.f> ZA,LIMM,UIMM6_20 0101111001011000x111xxxxxx111110 */
-{ "sub2l", 0x5e58703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub2l", 0x5e58703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub2l<.f><.cc> ZA,LIMM,UIMM6_20 0101111011011000x111xxxxxx1xxxxx */
-{ "sub2l", 0x5ed87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub2l", 0x5ed87020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub2l<.f> ZA,XIMM,SIMM12_20 0101110010011000x111xxxxxxxxxxxx */
-{ "sub2l", 0x5c987000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "sub2l", 0x5c987000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* sub2l<.f> ZA,LIMM,SIMM12_20 0101111010011000x111xxxxxxxxxxxx */
-{ "sub2l", 0x5e987000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sub2l", 0x5e987000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sub2l<.f> RA,XIMM,XIMMdup 0101110000011000x111111100xxxxxx */
-{ "sub2l", 0x5c187f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "sub2l", 0x5c187f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* sub2l<.f> ZA,XIMM,XIMMdup 0101110000011000x111111100111110 */
-{ "sub2l", 0x5c187f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "sub2l", 0x5c187f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* sub2l<.f><.cc> ZA,XIMM,XIMMdup 0101110011011000x1111111000xxxxx */
-{ "sub2l", 0x5cd87f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "sub2l", 0x5cd87f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* sub2l<.f> RA,LIMM,LIMMdup 0101111000011000x111111110xxxxxx */
-{ "sub2l", 0x5e187f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sub2l", 0x5e187f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sub2l<.f> ZA,LIMM,LIMMdup 0101111000011000x111111110111110 */
-{ "sub2l", 0x5e187fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sub2l", 0x5e187fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sub2l<.f><.cc> ZA,LIMM,LIMMdup 0101111011011000x1111111100xxxxx */
-{ "sub2l", 0x5ed87f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sub2l", 0x5ed87f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sub3<.f> RA,RB,RC 00100xxx00011001xxxxxxxxxxxxxxxx */
-{ "sub3", 0x20190000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, RC }, { C_F } }
+{ "sub3", 0x20190000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sub3<.f> ZA,RB,RC 00100xxx00011001xxxxxxxxxx111110 */
-{ "sub3", 0x2019003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, RC }, { C_F } }
+{ "sub3", 0x2019003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sub3<.f><.cc> RB,RBdup,RC 00100xxx11011001xxxxxxxxxx0xxxxx */
-{ "sub3", 0x20d90000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sub3", 0x20d90000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sub3<.f> RA,RB,UIMM6_20 00100xxx01011001xxxxxxxxxxxxxxxx */
-{ "sub3", 0x20590000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sub3", 0x20590000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sub3<.f> ZA,RB,UIMM6_20 00100xxx01011001xxxxxxxxxx111110 */
-{ "sub3", 0x2059003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sub3", 0x2059003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sub3<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11011001xxxxxxxxxx1xxxxx */
-{ "sub3", 0x20d90020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sub3", 0x20d90020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub3<.f> RB,RBdup,SIMM12_20 00100xxx10011001xxxxxxxxxxxxxxxx */
-{ "sub3", 0x20990000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sub3", 0x20990000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sub3<.f> RA,LIMM,RC 0010011000011001x111xxxxxxxxxxxx */
-{ "sub3", 0x26197000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sub3", 0x26197000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sub3<.f> RA,RB,LIMM 00100xxx00011001xxxx111110xxxxxx */
-{ "sub3", 0x20190f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sub3", 0x20190f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sub3<.f> ZA,LIMM,RC 0010011000011001x111xxxxxx111110 */
-{ "sub3", 0x2619703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sub3", 0x2619703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sub3<.f> ZA,RB,LIMM 00100xxx00011001xxxx111110111110 */
-{ "sub3", 0x20190fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sub3", 0x20190fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sub3<.f><.cc> RB,RBdup,LIMM 00100xxx11011001xxxx1111100xxxxx */
-{ "sub3", 0x20d90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sub3", 0x20d90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sub3<.f><.cc> ZA,LIMM,RC 0010011011011001x111xxxxxx0xxxxx */
-{ "sub3", 0x26d97000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sub3", 0x26d97000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sub3<.f> RA,LIMM,UIMM6_20 0010011001011001x111xxxxxxxxxxxx */
-{ "sub3", 0x26597000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub3", 0x26597000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub3<.f> ZA,LIMM,UIMM6_20 0010011001011001x111xxxxxx111110 */
-{ "sub3", 0x2659703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub3", 0x2659703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub3<.f><.cc> ZA,LIMM,UIMM6_20 0010011011011001x111xxxxxx1xxxxx */
-{ "sub3", 0x26d97020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub3", 0x26d97020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub3<.f> ZA,LIMM,SIMM12_20 0010011010011001x111xxxxxxxxxxxx */
-{ "sub3", 0x26997000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sub3", 0x26997000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sub3<.f> RA,LIMM,LIMMdup 0010011000011001x111111110xxxxxx */
-{ "sub3", 0x26197f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sub3", 0x26197f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sub3<.f> ZA,LIMM,LIMMdup 0010011000011001x111111110111110 */
-{ "sub3", 0x26197fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sub3", 0x26197fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sub3<.f><.cc> ZA,LIMM,LIMMdup 0010011011011001x1111111100xxxxx */
-{ "sub3", 0x26d97f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sub3", 0x26d97f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* sub3l<.f> RA,RB,RC 01011xxx00011001xxxxxxxxxxxxxxxx */
-{ "sub3l", 0x58190000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "sub3l", 0x58190000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* sub3l<.f> ZA,RB,RC 01011xxx00011001xxxxxxxxxx111110 */
-{ "sub3l", 0x5819003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "sub3l", 0x5819003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* sub3l<.f><.cc> RB,RBdup,RC 01011xxx11011001xxxxxxxxxx0xxxxx */
-{ "sub3l", 0x58d90000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "sub3l", 0x58d90000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* sub3l<.f> RA,RB,UIMM6_20 01011xxx01011001xxxxxxxxxxxxxxxx */
-{ "sub3l", 0x58590000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "sub3l", 0x58590000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* sub3l<.f> ZA,RB,UIMM6_20 01011xxx01011001xxxxxxxxxx111110 */
-{ "sub3l", 0x5859003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "sub3l", 0x5859003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* sub3l<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11011001xxxxxxxxxx1xxxxx */
-{ "sub3l", 0x58d90020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "sub3l", 0x58d90020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub3l<.f> RB,RBdup,SIMM12_20 01011xxx10011001xxxxxxxxxxxxxxxx */
-{ "sub3l", 0x58990000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "sub3l", 0x58990000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* sub3l<.f> RA,XIMM,RC 0101110000011001x111xxxxxxxxxxxx */
-{ "sub3l", 0x5c197000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "sub3l", 0x5c197000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* sub3l<.f> RA,RB,XIMM 01011xxx00011001xxxx111100xxxxxx */
-{ "sub3l", 0x58190f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "sub3l", 0x58190f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* sub3l<.f> ZA,XIMM,RC 0101110000011001x111xxxxxx111110 */
-{ "sub3l", 0x5c19703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "sub3l", 0x5c19703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* sub3l<.f> ZA,RB,XIMM 01011xxx00011001xxxx111100111110 */
-{ "sub3l", 0x58190f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "sub3l", 0x58190f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* sub3l<.f><.cc> ZA,XIMM,RC 0101110011011001x111xxxxxx0xxxxx */
-{ "sub3l", 0x5cd97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "sub3l", 0x5cd97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* sub3l<.f><.cc> RB,RBdup,XIMM 01011xxx11011001xxxx1111000xxxxx */
-{ "sub3l", 0x58d90f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "sub3l", 0x58d90f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* sub3l<.f> RA,XIMM,UIMM6_20 0101110001011001x111xxxxxxxxxxxx */
-{ "sub3l", 0x5c597000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "sub3l", 0x5c597000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sub3l<.f> ZA,XIMM,UIMM6_20 0101110001011001x111xxxxxx111110 */
-{ "sub3l", 0x5c59703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "sub3l", 0x5c59703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* sub3l<.f><.cc> ZA,XIMM,UIMM6_20 0101110011011001x111xxxxxx1xxxxx */
-{ "sub3l", 0x5cd97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub3l", 0x5cd97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub3l<.f> RA,LIMM,RC 0101111000011001x111xxxxxxxxxxxx */
-{ "sub3l", 0x5e197000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "sub3l", 0x5e197000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* sub3l<.f> RA,RB,LIMM 01011xxx00011001xxxx111110xxxxxx */
-{ "sub3l", 0x58190f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "sub3l", 0x58190f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* sub3l<.f> ZA,LIMM,RC 0101111000011001x111xxxxxx111110 */
-{ "sub3l", 0x5e19703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "sub3l", 0x5e19703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* sub3l<.f> ZA,RB,LIMM 01011xxx00011001xxxx111110111110 */
-{ "sub3l", 0x58190fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "sub3l", 0x58190fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* sub3l<.f><.cc> ZA,LIMM,RC 0101111011011001x111xxxxxx0xxxxx */
-{ "sub3l", 0x5ed97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "sub3l", 0x5ed97000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* sub3l<.f><.cc> RB,RBdup,LIMM 01011xxx11011001xxxx1111100xxxxx */
-{ "sub3l", 0x58d90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "sub3l", 0x58d90f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* sub3l<.f> RA,LIMM,UIMM6_20 0101111001011001x111xxxxxxxxxxxx */
-{ "sub3l", 0x5e597000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub3l", 0x5e597000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub3l<.f> ZA,LIMM,UIMM6_20 0101111001011001x111xxxxxx111110 */
-{ "sub3l", 0x5e59703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "sub3l", 0x5e59703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* sub3l<.f><.cc> ZA,LIMM,UIMM6_20 0101111011011001x111xxxxxx1xxxxx */
-{ "sub3l", 0x5ed97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "sub3l", 0x5ed97020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* sub3l<.f> ZA,XIMM,SIMM12_20 0101110010011001x111xxxxxxxxxxxx */
-{ "sub3l", 0x5c997000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "sub3l", 0x5c997000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* sub3l<.f> ZA,LIMM,SIMM12_20 0101111010011001x111xxxxxxxxxxxx */
-{ "sub3l", 0x5e997000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "sub3l", 0x5e997000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* sub3l<.f> RA,XIMM,XIMMdup 0101110000011001x111111100xxxxxx */
-{ "sub3l", 0x5c197f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "sub3l", 0x5c197f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* sub3l<.f> ZA,XIMM,XIMMdup 0101110000011001x111111100111110 */
-{ "sub3l", 0x5c197f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "sub3l", 0x5c197f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* sub3l<.f><.cc> ZA,XIMM,XIMMdup 0101110011011001x1111111000xxxxx */
-{ "sub3l", 0x5cd97f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "sub3l", 0x5cd97f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* sub3l<.f> RA,LIMM,LIMMdup 0101111000011001x111111110xxxxxx */
-{ "sub3l", 0x5e197f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "sub3l", 0x5e197f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* sub3l<.f> ZA,LIMM,LIMMdup 0101111000011001x111111110111110 */
-{ "sub3l", 0x5e197fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "sub3l", 0x5e197fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* sub3l<.f><.cc> ZA,LIMM,LIMMdup 0101111011011001x1111111100xxxxx */
-{ "sub3l", 0x5ed97f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "sub3l", 0x5ed97f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* subl<.f> RA,RB,RC 01011xxx00000010xxxxxxxxxxxxxxxx */
-{ "subl", 0x58020000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "subl", 0x58020000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* subl<.f> ZA,RB,RC 01011xxx00000010xxxxxxxxxx111110 */
-{ "subl", 0x5802003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "subl", 0x5802003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* subl<.f><.cc> RB,RBdup,RC 01011xxx11000010xxxxxxxxxx0xxxxx */
-{ "subl", 0x58c20000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "subl", 0x58c20000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* subl<.f> RA,RB,UIMM6_20 01011xxx01000010xxxxxxxxxxxxxxxx */
-{ "subl", 0x58420000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "subl", 0x58420000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* subl<.f> ZA,RB,UIMM6_20 01011xxx01000010xxxxxxxxxx111110 */
-{ "subl", 0x5842003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "subl", 0x5842003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* subl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11000010xxxxxxxxxx1xxxxx */
-{ "subl", 0x58c20020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "subl", 0x58c20020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* subl<.f> RB,RBdup,SIMM12_20 01011xxx10000010xxxxxxxxxxxxxxxx */
-{ "subl", 0x58820000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "subl", 0x58820000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* subl<.f> RA,XIMM,RC 0101110000000010x111xxxxxxxxxxxx */
-{ "subl", 0x5c027000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "subl", 0x5c027000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* subl<.f> RA,RB,XIMM 01011xxx00000010xxxx111100xxxxxx */
-{ "subl", 0x58020f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "subl", 0x58020f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* subl<.f> ZA,XIMM,RC 0101110000000010x111xxxxxx111110 */
-{ "subl", 0x5c02703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "subl", 0x5c02703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* subl<.f> ZA,RB,XIMM 01011xxx00000010xxxx111100111110 */
-{ "subl", 0x58020f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "subl", 0x58020f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* subl<.f><.cc> ZA,XIMM,RC 0101110011000010x111xxxxxx0xxxxx */
-{ "subl", 0x5cc27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "subl", 0x5cc27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* subl<.f><.cc> RB,RBdup,XIMM 01011xxx11000010xxxx1111000xxxxx */
-{ "subl", 0x58c20f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "subl", 0x58c20f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* subl<.f> RA,XIMM,UIMM6_20 0101110001000010x111xxxxxxxxxxxx */
-{ "subl", 0x5c427000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "subl", 0x5c427000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* subl<.f> ZA,XIMM,UIMM6_20 0101110001000010x111xxxxxx111110 */
-{ "subl", 0x5c42703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "subl", 0x5c42703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* subl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011000010x111xxxxxx1xxxxx */
-{ "subl", 0x5cc27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "subl", 0x5cc27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* subl<.f> RA,LIMM,RC 0101111000000010x111xxxxxxxxxxxx */
-{ "subl", 0x5e027000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "subl", 0x5e027000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* subl<.f> RA,RB,LIMM 01011xxx00000010xxxx111110xxxxxx */
-{ "subl", 0x58020f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "subl", 0x58020f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* subl<.f> ZA,LIMM,RC 0101111000000010x111xxxxxx111110 */
-{ "subl", 0x5e02703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "subl", 0x5e02703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* subl<.f> ZA,RB,LIMM 01011xxx00000010xxxx111110111110 */
-{ "subl", 0x58020fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "subl", 0x58020fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* subl<.f><.cc> ZA,LIMM,RC 0101111011000010x111xxxxxx0xxxxx */
-{ "subl", 0x5ec27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "subl", 0x5ec27000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* subl<.f><.cc> RB,RBdup,LIMM 01011xxx11000010xxxx1111100xxxxx */
-{ "subl", 0x58c20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "subl", 0x58c20f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* subl<.f> RA,LIMM,UIMM6_20 0101111001000010x111xxxxxxxxxxxx */
-{ "subl", 0x5e427000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "subl", 0x5e427000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* subl<.f> ZA,LIMM,UIMM6_20 0101111001000010x111xxxxxx111110 */
-{ "subl", 0x5e42703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "subl", 0x5e42703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* subl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011000010x111xxxxxx1xxxxx */
-{ "subl", 0x5ec27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "subl", 0x5ec27020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* subl<.f> ZA,XIMM,SIMM12_20 0101110010000010x111xxxxxxxxxxxx */
-{ "subl", 0x5c827000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "subl", 0x5c827000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* subl<.f> ZA,LIMM,SIMM12_20 0101111010000010x111xxxxxxxxxxxx */
-{ "subl", 0x5e827000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "subl", 0x5e827000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* subl<.f> RA,XIMM,XIMMdup 0101110000000010x111111100xxxxxx */
-{ "subl", 0x5c027f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "subl", 0x5c027f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* subl<.f> ZA,XIMM,XIMMdup 0101110000000010x111111100111110 */
-{ "subl", 0x5c027f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "subl", 0x5c027f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* subl<.f><.cc> ZA,XIMM,XIMMdup 0101110011000010x1111111000xxxxx */
-{ "subl", 0x5cc27f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "subl", 0x5cc27f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* subl<.f> RA,LIMM,LIMMdup 0101111000000010x111111110xxxxxx */
-{ "subl", 0x5e027f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "subl", 0x5e027f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* subl<.f> ZA,LIMM,LIMMdup 0101111000000010x111111110111110 */
-{ "subl", 0x5e027fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "subl", 0x5e027fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* subl<.f><.cc> ZA,LIMM,LIMMdup 0101111011000010x1111111100xxxxx */
-{ "subl", 0x5ec27f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "subl", 0x5ec27f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* subl_s SP_S,SP_Sdup,UIMM9_A32_11_S 11000xx1101xxxxx */
-{ "subl_s", 0x0000c1a0, 0x0000f9e0, ARC_OPCODE_ARC64, ARITH, NONE, { SP_S, SP_Sdup, UIMM9_A32_11_S }, { 0 } }
+{ "subl_s", 0x0000c1a0, 0x0000f9e0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { SP_S, SP_Sdup, UIMM9_A32_11_S }, { 0 } }
 
 /* subl_s RB_S,RB_Sdup,RC_S 01111xxxxxx00011 */
-{ "subl_s", 0x00007803, 0x0000f81f, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "subl_s", 0x00007803, 0x0000f81f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* sub_s RB_S,RB_Sdup,RB_Sdup 01111xxx11000000 */
-{ "sub_s", 0x000078c0, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE, C_CC_NE } }
+{ "sub_s", 0x000078c0, 0x0000f8ff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE, C_CC_NE } }
 
 /* sub_s RB_S,RB_Sdup,RC_S 01111xxxxxx00010 */
-{ "sub_s", 0x00007802, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "sub_s", 0x00007802, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* sub_s RA_S,RB_S,RC_S 01001xxxxxx10xxx */
 { "sub_s", 0x00004810, 0x0000f818, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, CD, { RA_S, RB_S, RC_S }, { 0 } }
 
 /* sub_s RB_S,RB_Sdup,UIMM5_11_S 10111xxx011xxxxx */
-{ "sub_s", 0x0000b860, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
+{ "sub_s", 0x0000b860, 0x0000f8e0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 } }
 
 /* sub_s SP,SP,u7 11000001101uuuuu.  */
-{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC32, SUB, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
+{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC32, SUB, ARC_INSN_SUBCLASS_NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
 
 /* swap<.f> RB,RC 00101xxx00101111xxxxxxxxxx000000 */
 { "swap", 0x282f0000, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, SWAP, { RB, RC }, { C_F } }
@@ -9962,142 +9962,142 @@
 { "swape", 0x2e2f7f89, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, SWAP, { ZA, LIMM }, { C_F } }
 
 /* swapel<.f> RB,RC 01011xxx00101111xxxxxxxxxx101001 */
-{ "swapel", 0x582f0029, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "swapel", 0x582f0029, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* swapel<.f> ZA,RC 0101111000101111x111xxxxxx101001 */
-{ "swapel", 0x5e2f7029, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "swapel", 0x5e2f7029, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* swapel<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx101001 */
-{ "swapel", 0x586f0029, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "swapel", 0x586f0029, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* swapel<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx101001 */
-{ "swapel", 0x5e6f7029, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "swapel", 0x5e6f7029, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* swapel<.f> RB,XIMM 01011xxx00101111xxxx111100101001 */
-{ "swapel", 0x582f0f29, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "swapel", 0x582f0f29, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* swapel<.f> ZA,XIMM 0101111000101111x111111100101001 */
-{ "swapel", 0x5e2f7f29, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "swapel", 0x5e2f7f29, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* swapel<.f> RB,LIMM 01011xxx00101111xxxx111110101001 */
-{ "swapel", 0x582f0fa9, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "swapel", 0x582f0fa9, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* swapel<.f> ZA,LIMM 0101111000101111x111111110101001 */
-{ "swapel", 0x5e2f7fa9, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "swapel", 0x5e2f7fa9, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* swapl<.f> RB,RC 01011xxx00101111xxxxxxxxxx100000 */
-{ "swapl", 0x582f0020, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F } }
+{ "swapl", 0x582f0020, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_F } }
 
 /* swapl<.f> ZA,RC 0101111000101111x111xxxxxx100000 */
-{ "swapl", 0x5e2f7020, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F } }
+{ "swapl", 0x5e2f7020, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RC }, { C_F } }
 
 /* swapl<.f> RB,UIMM6_20 01011xxx01101111xxxxxxxxxx100000 */
-{ "swapl", 0x586f0020, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F } }
+{ "swapl", 0x586f0020, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_F } }
 
 /* swapl<.f> ZA,UIMM6_20 0101111001101111x111xxxxxx100000 */
-{ "swapl", 0x5e6f7020, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F } }
+{ "swapl", 0x5e6f7020, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, UIMM6_20 }, { C_F } }
 
 /* swapl<.f> RB,XIMM 01011xxx00101111xxxx111100100000 */
-{ "swapl", 0x582f0f20, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F } }
+{ "swapl", 0x582f0f20, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_F } }
 
 /* swapl<.f> ZA,XIMM 0101111000101111x111111100100000 */
-{ "swapl", 0x5e2f7f20, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F } }
+{ "swapl", 0x5e2f7f20, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM }, { C_F } }
 
 /* swapl<.f> RB,LIMM 01011xxx00101111xxxx111110100000 */
-{ "swapl", 0x582f0fa0, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F } }
+{ "swapl", 0x582f0fa0, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_F } }
 
 /* swapl<.f> ZA,LIMM 0101111000101111x111111110100000 */
-{ "swapl", 0x5e2f7fa0, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F } }
+{ "swapl", 0x5e2f7fa0, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM }, { C_F } }
 
 /* swi  00100010011011110000000000111111 */
-{ "swi", 0x226f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, {  }, { 0 } }
+{ "swi", 0x226f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* swi_s  0111101011100000 */
-{ "swi_s", 0x00007ae0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, {  }, { 0 } }
+{ "swi_s", 0x00007ae0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* swi_s UIMM6_5_S 01111xxxxxx11111 */
-{ "swi_s", 0x0000781f, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { UIMM6_5_S }, { 0 } }
+{ "swi_s", 0x0000781f, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { UIMM6_5_S }, { 0 } }
 
 /* sync  00100011011011110000000000111111 */
-{ "sync", 0x236f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, NONE, {  }, { 0 } }
+{ "sync", 0x236f003f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, CONTROL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* trap_s UIMM6_5_S 01111xxxxxx11110 */
-{ "trap_s", 0x0000781e, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { UIMM6_5_S }, { 0 } }
+{ "trap_s", 0x0000781e, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { UIMM6_5_S }, { 0 } }
 
 /* tst RB,RC 00100xxx000010111xxxxxxxxxxxxxxx */
-{ "tst", 0x200b8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { 0 } }
+{ "tst", 0x200b8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* tst<.cc> RB,RC 00100xxx110010111xxxxxxxxx0xxxxx */
-{ "tst", 0x20cb8000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RC }, { C_CC } }
+{ "tst", 0x20cb8000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* tst RB,UIMM6_20 00100xxx010010111xxxxxxxxxxxxxxx */
-{ "tst", 0x204b8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "tst", 0x204b8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* tst<.cc> RB,UIMM6_20 00100xxx110010111xxxxxxxxx1xxxxx */
-{ "tst", 0x20cb8020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "tst", 0x20cb8020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* tst RB,SIMM12_20 00100xxx100010111xxxxxxxxxxxxxxx */
-{ "tst", 0x208b8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "tst", 0x208b8000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* tst LIMM,RC 00100110000010111111xxxxxxxxxxxx */
-{ "tst", 0x260bf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, RC }, { 0 } }
+{ "tst", 0x260bf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { 0 } }
 
 /* tst RB,LIMM 00100xxx000010111xxx111110xxxxxx */
-{ "tst", 0x200b8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { 0 } }
+{ "tst", 0x200b8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { 0 } }
 
 /* tst<.cc> RB,LIMM 00100xxx110010111xxx1111100xxxxx */
-{ "tst", 0x20cb8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, LIMM }, { C_CC } }
+{ "tst", 0x20cb8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_CC } }
 
 /* tst<.cc> LIMM,RC 00100110110010111111xxxxxx0xxxxx */
-{ "tst", 0x26cbf000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, RC }, { C_CC } }
+{ "tst", 0x26cbf000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, RC }, { C_CC } }
 
 /* tst LIMM,UIMM6_20 00100110010010111111xxxxxxxxxxxx */
-{ "tst", 0x264bf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 } }
+{ "tst", 0x264bf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { 0 } }
 
 /* tst<.cc> LIMM,UIMM6_20 00100110110010111111xxxxxx1xxxxx */
-{ "tst", 0x26cbf020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC } }
+{ "tst", 0x26cbf020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, UIMM6_20 }, { C_CC } }
 
 /* tst LIMM,SIMM12_20 00100110100010111111xxxxxxxxxxxx */
-{ "tst", 0x268bf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 } }
+{ "tst", 0x268bf000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, SIMM12_20 }, { 0 } }
 
 /* tst LIMM,LIMMdup 00100110000010111111111110xxxxxx */
-{ "tst", 0x260bff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 } }
+{ "tst", 0x260bff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup }, { 0 } }
 
 /* tst<.cc> LIMM,LIMMdup 001001101100101111111111100xxxxx */
-{ "tst", 0x26cbff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC } }
+{ "tst", 0x26cbff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { LIMM, LIMMdup }, { C_CC } }
 
 /* tstl RB,RC 01011xxx000010111xxxxxxxxxxxxxxx */
-{ "tstl", 0x580b8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 } }
+{ "tstl", 0x580b8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { 0 } }
 
 /* tstl<.cc> RB,RC 01011xxx110010111xxxxxxxxx0xxxxx */
-{ "tstl", 0x58cb8000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC } }
+{ "tstl", 0x58cb8000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RC }, { C_CC } }
 
 /* tstl RB,UIMM6_20 01011xxx010010111xxxxxxxxxxxxxxx */
-{ "tstl", 0x584b8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 } }
+{ "tstl", 0x584b8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { 0 } }
 
 /* tstl<.cc> RB,UIMM6_20 01011xxx110010111xxxxxxxxx1xxxxx */
-{ "tstl", 0x58cb8020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC } }
+{ "tstl", 0x58cb8020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, UIMM6_20 }, { C_CC } }
 
 /* tstl RB,SIMM12_20 01011xxx100010111xxxxxxxxxxxxxxx */
-{ "tstl", 0x588b8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 } }
+{ "tstl", 0x588b8000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, SIMM12_20 }, { 0 } }
 
 /* tstl RB,XIMM 01011xxx000010111xxx111100xxxxxx */
-{ "tstl", 0x580b8f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 } }
+{ "tstl", 0x580b8f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { 0 } }
 
 /* tstl<.cc> RB,XIMM 01011xxx110010111xxx1111000xxxxx */
-{ "tstl", 0x58cb8f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC } }
+{ "tstl", 0x58cb8f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, XIMM }, { C_CC } }
 
 /* tstl RB,LIMM 01011xxx000010111xxx111110xxxxxx */
-{ "tstl", 0x580b8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 } }
+{ "tstl", 0x580b8f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { 0 } }
 
 /* tstl<.cc> RB,LIMM 01011xxx110010111xxx1111100xxxxx */
-{ "tstl", 0x58cb8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC } }
+{ "tstl", 0x58cb8f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, LIMM }, { C_CC } }
 
 /* tst_s RB_S,RC_S 01111xxxxxx01011 */
-{ "tst_s", 0x0000780b, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RC_S }, { 0 } }
+{ "tst_s", 0x0000780b, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RC_S }, { 0 } }
 
 /* unimp_s  0111100111100000 */
-{ "unimp_s", 0x000079e0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, {  }, { 0 } }
+{ "unimp_s", 0x000079e0, 0x0000ffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* vadd2 RA_CHK,RB,RC 00101xxx001111000xxxxxxxxxxxxxxx */
 { "vadd2", 0x283c0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 } }
@@ -10460,124 +10460,124 @@
 { "vaddsub4h", 0x2efa7f80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vmac2h RA_CHK,RB,RC 00101xxx000111100xxxxxxxxxxxxxxx */
-{ "vmac2h", 0x281e0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, RB, RC }, { 0 } }
+{ "vmac2h", 0x281e0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, RB, RC }, { 0 } }
 
 /* vmac2h ZA,RB,RC 00101xxx000111100xxxxxxxxx111110 */
-{ "vmac2h", 0x281e003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, RB, RC }, { 0 } }
+{ "vmac2h", 0x281e003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vmac2h<.cc> RB_CHK,RBdup,RC 00101xxx110111100xxxxxxxxx0xxxxx */
-{ "vmac2h", 0x28de0000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RB_CHK, RBdup, RC }, { C_CC } }
+{ "vmac2h", 0x28de0000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RB_CHK, RBdup, RC }, { C_CC } }
 
 /* vmac2h RA_CHK,RB,UIMM6_20 00101xxx010111100xxxxxxxxxxxxxxx */
-{ "vmac2h", 0x285e0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, RB, UIMM6_20_SPLITH }, { 0 } }
+{ "vmac2h", 0x285e0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, RB, UIMM6_20_SPLITH }, { 0 } }
 
 /* vmac2h ZA,RB,UIMM6_20 00101xxx010111100xxxxxxxxx111110 */
-{ "vmac2h", 0x285e003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, RB, UIMM6_20_SPLITH }, { 0 } }
+{ "vmac2h", 0x285e003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20_SPLITH }, { 0 } }
 
 /* vmac2h<.cc> RB_CHK,RBdup,UIMM6_20 00101xxx110111100xxxxxxxxx1xxxxx */
-{ "vmac2h", 0x28de0020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RB_CHK, RBdup, UIMM6_20_SPLITH }, { C_CC } }
+{ "vmac2h", 0x28de0020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RB_CHK, RBdup, UIMM6_20_SPLITH }, { C_CC } }
 
 /* vmac2h RB_CHK,RBdup,SIMM12_20 00101xxx100111100xxxxxxxxxxxxxxx */
-{ "vmac2h", 0x289e0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RB_CHK, RBdup, SIMM12_20_SPLITH }, { 0 } }
+{ "vmac2h", 0x289e0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RB_CHK, RBdup, SIMM12_20_SPLITH }, { 0 } }
 
 /* vmac2h RA_CHK,LIMM,RC 00101110000111100111xxxxxxxxxxxx */
-{ "vmac2h", 0x2e1e7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, LIMM, RC }, { 0 } }
+{ "vmac2h", 0x2e1e7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, LIMM, RC }, { 0 } }
 
 /* vmac2h RA_CHK,RB,LIMM 00101xxx000111100xxx111110xxxxxx */
-{ "vmac2h", 0x281e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, RB, LIMM }, { 0 } }
+{ "vmac2h", 0x281e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, RB, LIMM }, { 0 } }
 
 /* vmac2h ZA,LIMM,RC 00101110000111100111xxxxxx111110 */
-{ "vmac2h", 0x2e1e703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vmac2h", 0x2e1e703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vmac2h ZA,RB,LIMM 00101xxx000111100xxx111110111110 */
-{ "vmac2h", 0x281e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vmac2h", 0x281e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vmac2h<.cc> RB_CHK,RBdup,LIMM 00101xxx110111100xxx1111100xxxxx */
-{ "vmac2h", 0x28de0f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RB_CHK, RBdup, LIMM }, { C_CC } }
+{ "vmac2h", 0x28de0f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RB_CHK, RBdup, LIMM }, { C_CC } }
 
 /* vmac2h<.cc> ZA,LIMM,RC 00101110110111100111xxxxxx0xxxxx */
-{ "vmac2h", 0x2ede7000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vmac2h", 0x2ede7000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vmac2h RA_CHK,LIMM,UIMM6_20 00101110010111100111xxxxxxxxxxxx */
-{ "vmac2h", 0x2e5e7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, LIMM, UIMM6_20_SPLITH }, { 0 } }
+{ "vmac2h", 0x2e5e7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, LIMM, UIMM6_20_SPLITH }, { 0 } }
 
 /* vmac2h ZA,LIMM,UIMM6_20 00101110010111100111xxxxxx111110 */
-{ "vmac2h", 0x2e5e703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, UIMM6_20_SPLITH }, { 0 } }
+{ "vmac2h", 0x2e5e703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20_SPLITH }, { 0 } }
 
 /* vmac2h<.cc> ZA,LIMM,UIMM6_20 00101110110111100111xxxxxx1xxxxx */
-{ "vmac2h", 0x2ede7020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, UIMM6_20_SPLITH }, { C_CC } }
+{ "vmac2h", 0x2ede7020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20_SPLITH }, { C_CC } }
 
 /* vmac2h ZA,LIMM,SIMM12_20 00101110100111100111xxxxxxxxxxxx */
-{ "vmac2h", 0x2e9e7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, SIMM12_20_SPLITH }, { 0 } }
+{ "vmac2h", 0x2e9e7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20_SPLITH }, { 0 } }
 
 /* vmac2h RA_CHK,LIMM,LIMMdup 00101110000111100111111110xxxxxx */
-{ "vmac2h", 0x2e1e7f80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 } }
+{ "vmac2h", 0x2e1e7f80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, LIMM, LIMMdup }, { 0 } }
 
 /* vmac2h ZA,LIMM,LIMMdup 00101110000111100111111110111110 */
-{ "vmac2h", 0x2e1e7fbe, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vmac2h", 0x2e1e7fbe, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vmac2h<.cc> ZA,LIMM,LIMMdup 001011101101111001111111100xxxxx */
-{ "vmac2h", 0x2ede7f80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vmac2h", 0x2ede7f80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vmac2hu RA_CHK,RB,RC 00101xxx000111110xxxxxxxxxxxxxxx */
-{ "vmac2hu", 0x281f0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, RB, RC }, { 0 } }
+{ "vmac2hu", 0x281f0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, RB, RC }, { 0 } }
 
 /* vmac2hu ZA,RB,RC 00101xxx000111110xxxxxxxxx111110 */
-{ "vmac2hu", 0x281f003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, RB, RC }, { 0 } }
+{ "vmac2hu", 0x281f003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vmac2hu<.cc> RB_CHK,RBdup,RC 00101xxx110111110xxxxxxxxx0xxxxx */
-{ "vmac2hu", 0x28df0000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RB_CHK, RBdup, RC }, { C_CC } }
+{ "vmac2hu", 0x28df0000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RB_CHK, RBdup, RC }, { C_CC } }
 
 /* vmac2hu RA_CHK,RB,UIMM6_20 00101xxx010111110xxxxxxxxxxxxxxx */
-{ "vmac2hu", 0x285f0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, RB, UIMM6_20_SPLITH }, { 0 } }
+{ "vmac2hu", 0x285f0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, RB, UIMM6_20_SPLITH }, { 0 } }
 
 /* vmac2hu ZA,RB,UIMM6_20 00101xxx010111110xxxxxxxxx111110 */
-{ "vmac2hu", 0x285f003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, RB, UIMM6_20_SPLITH }, { 0 } }
+{ "vmac2hu", 0x285f003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20_SPLITH }, { 0 } }
 
 /* vmac2hu<.cc> RB_CHK,RBdup,UIMM6_20 00101xxx110111110xxxxxxxxx1xxxxx */
-{ "vmac2hu", 0x28df0020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RB_CHK, RBdup, UIMM6_20_SPLITH }, { C_CC } }
+{ "vmac2hu", 0x28df0020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RB_CHK, RBdup, UIMM6_20_SPLITH }, { C_CC } }
 
 /* vmac2hu RB_CHK,RBdup,SIMM12_20 00101xxx100111110xxxxxxxxxxxxxxx */
-{ "vmac2hu", 0x289f0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RB_CHK, RBdup, SIMM12_20_SPLITH }, { 0 } }
+{ "vmac2hu", 0x289f0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RB_CHK, RBdup, SIMM12_20_SPLITH }, { 0 } }
 
 /* vmac2hu RA_CHK,LIMM,RC 00101110000111110111xxxxxxxxxxxx */
-{ "vmac2hu", 0x2e1f7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, LIMM, RC }, { 0 } }
+{ "vmac2hu", 0x2e1f7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, LIMM, RC }, { 0 } }
 
 /* vmac2hu RA_CHK,RB,LIMM 00101xxx000111110xxx111110xxxxxx */
-{ "vmac2hu", 0x281f0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, RB, LIMM }, { 0 } }
+{ "vmac2hu", 0x281f0f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, RB, LIMM }, { 0 } }
 
 /* vmac2hu ZA,LIMM,RC 00101110000111110111xxxxxx111110 */
-{ "vmac2hu", 0x2e1f703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vmac2hu", 0x2e1f703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vmac2hu ZA,RB,LIMM 00101xxx000111110xxx111110111110 */
-{ "vmac2hu", 0x281f0fbe, 0xf8ff8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vmac2hu", 0x281f0fbe, 0xf8ff8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vmac2hu<.cc> RB_CHK,RBdup,LIMM 00101xxx110111110xxx1111100xxxxx */
-{ "vmac2hu", 0x28df0f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RB_CHK, RBdup, LIMM }, { C_CC } }
+{ "vmac2hu", 0x28df0f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RB_CHK, RBdup, LIMM }, { C_CC } }
 
 /* vmac2hu<.cc> ZA,LIMM,RC 00101110110111110111xxxxxx0xxxxx */
-{ "vmac2hu", 0x2edf7000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vmac2hu", 0x2edf7000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vmac2hu RA_CHK,LIMM,UIMM6_20 00101110010111110111xxxxxxxxxxxx */
-{ "vmac2hu", 0x2e5f7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, LIMM, UIMM6_20_SPLITH }, { 0 } }
+{ "vmac2hu", 0x2e5f7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, LIMM, UIMM6_20_SPLITH }, { 0 } }
 
 /* vmac2hu ZA,LIMM,UIMM6_20 00101110010111110111xxxxxx111110 */
-{ "vmac2hu", 0x2e5f703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, UIMM6_20_SPLITH }, { 0 } }
+{ "vmac2hu", 0x2e5f703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20_SPLITH }, { 0 } }
 
 /* vmac2hu<.cc> ZA,LIMM,UIMM6_20 00101110110111110111xxxxxx1xxxxx */
-{ "vmac2hu", 0x2edf7020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, UIMM6_20_SPLITH }, { C_CC } }
+{ "vmac2hu", 0x2edf7020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20_SPLITH }, { C_CC } }
 
 /* vmac2hu ZA,LIMM,SIMM12_20 00101110100111110111xxxxxxxxxxxx */
-{ "vmac2hu", 0x2e9f7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, SIMM12_20_SPLITH }, { 0 } }
+{ "vmac2hu", 0x2e9f7000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20_SPLITH }, { 0 } }
 
 /* vmac2hu RA_CHK,LIMM,LIMMdup 00101110000111110111111110xxxxxx */
-{ "vmac2hu", 0x2e1f7f80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 } }
+{ "vmac2hu", 0x2e1f7f80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { RA_CHK, LIMM, LIMMdup }, { 0 } }
 
 /* vmac2hu ZA,LIMM,LIMMdup 00101110000111110111111110111110 */
-{ "vmac2hu", 0x2e1f7fbe, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vmac2hu", 0x2e1f7fbe, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vmac2hu<.cc> ZA,LIMM,LIMMdup 001011101101111101111111100xxxxx */
-{ "vmac2hu", 0x2edf7f80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vmac2hu", 0x2edf7f80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vmpy2h RA_CHK,RB,RC 00101xxx000111000xxxxxxxxxxxxxxx */
 { "vmpy2h", 0x281c0000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY8E, { RA_CHK, RB, RC }, { 0 } }
@@ -11060,19 +11060,19 @@
 { "vsubadd4h", 0x2efb7f80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* wevt RC 00100000001011110001xxxxxx111111 */
-{ "wevt", 0x202f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { RC }, { 0 } }
+{ "wevt", 0x202f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { RC }, { 0 } }
 
 /* wevt  00100000011011110001000000111111 */
-{ "wevt", 0x206f103f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, {  }, { 0 } }
+{ "wevt", 0x206f103f, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, {  }, { 0 } }
 
 /* wevt UIMM6_20 00100000011011110001xxxxxx111111 */
-{ "wevt", 0x206f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { UIMM6_20 }, { 0 } }
+{ "wevt", 0x206f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* wlfc RC 00100001001011110001xxxxxx111111 */
-{ "wlfc", 0x212f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { RC }, { 0 } }
+{ "wlfc", 0x212f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { RC }, { 0 } }
 
 /* wlfc UIMM6_20 00100001011011110001xxxxxx111111 */
-{ "wlfc", 0x216f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, NONE, { UIMM6_20 }, { 0 } }
+{ "wlfc", 0x216f103f, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, KERNEL, ARC_INSN_SUBCLASS_NONE, { UIMM6_20 }, { 0 } }
 
 /* xbfu<.f> RA,RB,RC 00100xxx00101101xxxxxxxxxxxxxxxx */
 { "xbfu", 0x202d0000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, SHFT2, { RA, RB, RC }, { C_F } }
@@ -11135,1655 +11135,1655 @@
 { "xbfu", 0x26ed7f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* xbful<.f> RA,RB,RC 01011xxx00101101xxxxxxxxxxxxxxxx */
-{ "xbful", 0x582d0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "xbful", 0x582d0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* xbful<.f> ZA,RB,RC 01011xxx00101101xxxxxxxxxx111110 */
-{ "xbful", 0x582d003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "xbful", 0x582d003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* xbful<.f><.cc> RB,RBdup,RC 01011xxx11101101xxxxxxxxxx0xxxxx */
-{ "xbful", 0x58ed0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "xbful", 0x58ed0000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* xbful<.f> RA,RB,UIMM6_20 01011xxx01101101xxxxxxxxxxxxxxxx */
-{ "xbful", 0x586d0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "xbful", 0x586d0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* xbful<.f> ZA,RB,UIMM6_20 01011xxx01101101xxxxxxxxxx111110 */
-{ "xbful", 0x586d003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "xbful", 0x586d003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* xbful<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11101101xxxxxxxxxx1xxxxx */
-{ "xbful", 0x58ed0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "xbful", 0x58ed0020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* xbful<.f> RB,RBdup,SIMM12_20 01011xxx10101101xxxxxxxxxxxxxxxx */
-{ "xbful", 0x58ad0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "xbful", 0x58ad0000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* xbful<.f> RA,XIMM,RC 0101110000101101x111xxxxxxxxxxxx */
-{ "xbful", 0x5c2d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "xbful", 0x5c2d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* xbful<.f> RA,RB,XIMM 01011xxx00101101xxxx111100xxxxxx */
-{ "xbful", 0x582d0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "xbful", 0x582d0f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* xbful<.f> ZA,XIMM,RC 0101110000101101x111xxxxxx111110 */
-{ "xbful", 0x5c2d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "xbful", 0x5c2d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* xbful<.f> ZA,RB,XIMM 01011xxx00101101xxxx111100111110 */
-{ "xbful", 0x582d0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "xbful", 0x582d0f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* xbful<.f><.cc> ZA,XIMM,RC 0101110011101101x111xxxxxx0xxxxx */
-{ "xbful", 0x5ced7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "xbful", 0x5ced7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* xbful<.f><.cc> RB,RBdup,XIMM 01011xxx11101101xxxx1111000xxxxx */
-{ "xbful", 0x58ed0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "xbful", 0x58ed0f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* xbful<.f> RA,XIMM,UIMM6_20 0101110001101101x111xxxxxxxxxxxx */
-{ "xbful", 0x5c6d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "xbful", 0x5c6d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* xbful<.f> ZA,XIMM,UIMM6_20 0101110001101101x111xxxxxx111110 */
-{ "xbful", 0x5c6d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "xbful", 0x5c6d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* xbful<.f><.cc> ZA,XIMM,UIMM6_20 0101110011101101x111xxxxxx1xxxxx */
-{ "xbful", 0x5ced7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "xbful", 0x5ced7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* xbful<.f> RA,LIMM,RC 0101111000101101x111xxxxxxxxxxxx */
-{ "xbful", 0x5e2d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "xbful", 0x5e2d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* xbful<.f> RA,RB,LIMM 01011xxx00101101xxxx111110xxxxxx */
-{ "xbful", 0x582d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "xbful", 0x582d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* xbful<.f> ZA,LIMM,RC 0101111000101101x111xxxxxx111110 */
-{ "xbful", 0x5e2d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "xbful", 0x5e2d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* xbful<.f> ZA,RB,LIMM 01011xxx00101101xxxx111110111110 */
-{ "xbful", 0x582d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "xbful", 0x582d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* xbful<.f><.cc> ZA,LIMM,RC 0101111011101101x111xxxxxx0xxxxx */
-{ "xbful", 0x5eed7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "xbful", 0x5eed7000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* xbful<.f><.cc> RB,RBdup,LIMM 01011xxx11101101xxxx1111100xxxxx */
-{ "xbful", 0x58ed0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "xbful", 0x58ed0f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* xbful<.f> RA,LIMM,UIMM6_20 0101111001101101x111xxxxxxxxxxxx */
-{ "xbful", 0x5e6d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "xbful", 0x5e6d7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* xbful<.f> ZA,LIMM,UIMM6_20 0101111001101101x111xxxxxx111110 */
-{ "xbful", 0x5e6d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "xbful", 0x5e6d703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* xbful<.f><.cc> ZA,LIMM,UIMM6_20 0101111011101101x111xxxxxx1xxxxx */
-{ "xbful", 0x5eed7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "xbful", 0x5eed7020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* xbful<.f> ZA,XIMM,SIMM12_20 0101110010101101x111xxxxxxxxxxxx */
-{ "xbful", 0x5cad7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "xbful", 0x5cad7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* xbful<.f> ZA,LIMM,SIMM12_20 0101111010101101x111xxxxxxxxxxxx */
-{ "xbful", 0x5ead7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "xbful", 0x5ead7000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* xbful<.f> RA,XIMM,XIMMdup 0101110000101101x111111100xxxxxx */
-{ "xbful", 0x5c2d7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "xbful", 0x5c2d7f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* xbful<.f> ZA,XIMM,XIMMdup 0101110000101101x111111100111110 */
-{ "xbful", 0x5c2d7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "xbful", 0x5c2d7f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* xbful<.f><.cc> ZA,XIMM,XIMMdup 0101110011101101x1111111000xxxxx */
-{ "xbful", 0x5ced7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "xbful", 0x5ced7f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* xbful<.f> RA,LIMM,LIMMdup 0101111000101101x111111110xxxxxx */
-{ "xbful", 0x5e2d7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "xbful", 0x5e2d7f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* xbful<.f> ZA,LIMM,LIMMdup 0101111000101101x111111110111110 */
-{ "xbful", 0x5e2d7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "xbful", 0x5e2d7fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* xbful<.f><.cc> ZA,LIMM,LIMMdup 0101111011101101x1111111100xxxxx */
-{ "xbful", 0x5eed7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "xbful", 0x5eed7f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* xor<.f> RA,RB,RC 00100xxx00000111xxxxxxxxxxxxxxxx */
-{ "xor", 0x20070000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, RC }, { C_F } }
+{ "xor", 0x20070000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* xor<.f> ZA,RB,RC 00100xxx00000111xxxxxxxxxx111110 */
-{ "xor", 0x2007003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, RC }, { C_F } }
+{ "xor", 0x2007003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* xor<.f><.cc> RB,RBdup,RC 00100xxx11000111xxxxxxxxxx0xxxxx */
-{ "xor", 0x20c70000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "xor", 0x20c70000, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* xor<.f> RA,RB,UIMM6_20 00100xxx01000111xxxxxxxxxxxxxxxx */
-{ "xor", 0x20470000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "xor", 0x20470000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* xor<.f> ZA,RB,UIMM6_20 00100xxx01000111xxxxxxxxxx111110 */
-{ "xor", 0x2047003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "xor", 0x2047003e, 0xf8ff003f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* xor<.f><.cc> RB,RBdup,UIMM6_20 00100xxx11000111xxxxxxxxxx1xxxxx */
-{ "xor", 0x20c70020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "xor", 0x20c70020, 0xf8ff0020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* xor<.f> RB,RBdup,SIMM12_20 00100xxx10000111xxxxxxxxxxxxxxxx */
-{ "xor", 0x20870000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "xor", 0x20870000, 0xf8ff0000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* xor<.f> RA,LIMM,RC 0010011000000111x111xxxxxxxxxxxx */
-{ "xor", 0x26077000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, RC }, { C_F } }
+{ "xor", 0x26077000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* xor<.f> RA,RB,LIMM 00100xxx00000111xxxx111110xxxxxx */
-{ "xor", 0x20070f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, RB, LIMM }, { C_F } }
+{ "xor", 0x20070f80, 0xf8ff0fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* xor<.f> ZA,LIMM,RC 0010011000000111x111xxxxxx111110 */
-{ "xor", 0x2607703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "xor", 0x2607703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* xor<.f> ZA,RB,LIMM 00100xxx00000111xxxx111110111110 */
-{ "xor", 0x20070fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "xor", 0x20070fbe, 0xf8ff0fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* xor<.f><.cc> ZA,LIMM,RC 0010011011000111x111xxxxxx0xxxxx */
-{ "xor", 0x26c77000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "xor", 0x26c77000, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* xor<.f><.cc> RB,RBdup,LIMM 00100xxx11000111xxxx1111100xxxxx */
-{ "xor", 0x20c70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "xor", 0x20c70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* xor<.f> RA,LIMM,UIMM6_20 0010011001000111x111xxxxxxxxxxxx */
-{ "xor", 0x26477000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "xor", 0x26477000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* xor<.f> ZA,LIMM,UIMM6_20 0010011001000111x111xxxxxx111110 */
-{ "xor", 0x2647703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "xor", 0x2647703e, 0xffff703f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* xor<.f><.cc> ZA,LIMM,UIMM6_20 0010011011000111x111xxxxxx1xxxxx */
-{ "xor", 0x26c77020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "xor", 0x26c77020, 0xffff7020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* xor<.f> ZA,LIMM,SIMM12_20 0010011010000111x111xxxxxxxxxxxx */
-{ "xor", 0x26877000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "xor", 0x26877000, 0xffff7000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* xor<.f> RA,LIMM,LIMMdup 0010011000000111x111111110xxxxxx */
-{ "xor", 0x26077f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "xor", 0x26077f80, 0xffff7fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* xor<.f> ZA,LIMM,LIMMdup 0010011000000111x111111110111110 */
-{ "xor", 0x26077fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "xor", 0x26077fbe, 0xffff7fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* xor<.f><.cc> ZA,LIMM,LIMMdup 0010011011000111x1111111100xxxxx */
-{ "xor", 0x26c77f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "xor", 0x26c77f80, 0xffff7fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* xorl<.f> RA,RB,RC 01011xxx00000111xxxxxxxxxxxxxxxx */
-{ "xorl", 0x58070000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F } }
+{ "xorl", 0x58070000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { C_F } }
 
 /* xorl<.f> ZA,RB,RC 01011xxx00000111xxxxxxxxxx111110 */
-{ "xorl", 0x5807003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F } }
+{ "xorl", 0x5807003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { C_F } }
 
 /* xorl<.f><.cc> RB,RBdup,RC 01011xxx11000111xxxxxxxxxx0xxxxx */
-{ "xorl", 0x58c70000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC } }
+{ "xorl", 0x58c70000, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_F, C_CC } }
 
 /* xorl<.f> RA,RB,UIMM6_20 01011xxx01000111xxxxxxxxxxxxxxxx */
-{ "xorl", 0x58470000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F } }
+{ "xorl", 0x58470000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { C_F } }
 
 /* xorl<.f> ZA,RB,UIMM6_20 01011xxx01000111xxxxxxxxxx111110 */
-{ "xorl", 0x5847003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F } }
+{ "xorl", 0x5847003e, 0xf8ff003f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { C_F } }
 
 /* xorl<.f><.cc> RB,RBdup,UIMM6_20 01011xxx11000111xxxxxxxxxx1xxxxx */
-{ "xorl", 0x58c70020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
+{ "xorl", 0x58c70020, 0xf8ff0020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC } }
 
 /* xorl<.f> RB,RBdup,SIMM12_20 01011xxx10000111xxxxxxxxxxxxxxxx */
-{ "xorl", 0x58870000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
+{ "xorl", 0x58870000, 0xf8ff0000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { C_F } }
 
 /* xorl<.f> RA,XIMM,RC 0101110000000111x111xxxxxxxxxxxx */
-{ "xorl", 0x5c077000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F } }
+{ "xorl", 0x5c077000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { C_F } }
 
 /* xorl<.f> RA,RB,XIMM 01011xxx00000111xxxx111100xxxxxx */
-{ "xorl", 0x58070f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F } }
+{ "xorl", 0x58070f00, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { C_F } }
 
 /* xorl<.f> ZA,XIMM,RC 0101110000000111x111xxxxxx111110 */
-{ "xorl", 0x5c07703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F } }
+{ "xorl", 0x5c07703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F } }
 
 /* xorl<.f> ZA,RB,XIMM 01011xxx00000111xxxx111100111110 */
-{ "xorl", 0x58070f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F } }
+{ "xorl", 0x58070f3e, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, XIMM }, { C_F } }
 
 /* xorl<.f><.cc> ZA,XIMM,RC 0101110011000111x111xxxxxx0xxxxx */
-{ "xorl", 0x5cc77000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
+{ "xorl", 0x5cc77000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, RC }, { C_F, C_CC } }
 
 /* xorl<.f><.cc> RB,RBdup,XIMM 01011xxx11000111xxxx1111000xxxxx */
-{ "xorl", 0x58c70f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
+{ "xorl", 0x58c70f00, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_F, C_CC } }
 
 /* xorl<.f> RA,XIMM,UIMM6_20 0101110001000111x111xxxxxxxxxxxx */
-{ "xorl", 0x5c477000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
+{ "xorl", 0x5c477000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { C_F } }
 
 /* xorl<.f> ZA,XIMM,UIMM6_20 0101110001000111x111xxxxxx111110 */
-{ "xorl", 0x5c47703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
+{ "xorl", 0x5c47703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F } }
 
 /* xorl<.f><.cc> ZA,XIMM,UIMM6_20 0101110011000111x111xxxxxx1xxxxx */
-{ "xorl", 0x5cc77020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "xorl", 0x5cc77020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* xorl<.f> RA,LIMM,RC 0101111000000111x111xxxxxxxxxxxx */
-{ "xorl", 0x5e077000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F } }
+{ "xorl", 0x5e077000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { C_F } }
 
 /* xorl<.f> RA,RB,LIMM 01011xxx00000111xxxx111110xxxxxx */
-{ "xorl", 0x58070f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F } }
+{ "xorl", 0x58070f80, 0xf8ff0fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { C_F } }
 
 /* xorl<.f> ZA,LIMM,RC 0101111000000111x111xxxxxx111110 */
-{ "xorl", 0x5e07703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F } }
+{ "xorl", 0x5e07703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F } }
 
 /* xorl<.f> ZA,RB,LIMM 01011xxx00000111xxxx111110111110 */
-{ "xorl", 0x58070fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F } }
+{ "xorl", 0x58070fbe, 0xf8ff0fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { C_F } }
 
 /* xorl<.f><.cc> ZA,LIMM,RC 0101111011000111x111xxxxxx0xxxxx */
-{ "xorl", 0x5ec77000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
+{ "xorl", 0x5ec77000, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_F, C_CC } }
 
 /* xorl<.f><.cc> RB,RBdup,LIMM 01011xxx11000111xxxx1111100xxxxx */
-{ "xorl", 0x58c70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
+{ "xorl", 0x58c70f80, 0xf8ff0fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_F, C_CC } }
 
 /* xorl<.f> RA,LIMM,UIMM6_20 0101111001000111x111xxxxxxxxxxxx */
-{ "xorl", 0x5e477000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
+{ "xorl", 0x5e477000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { C_F } }
 
 /* xorl<.f> ZA,LIMM,UIMM6_20 0101111001000111x111xxxxxx111110 */
-{ "xorl", 0x5e47703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
+{ "xorl", 0x5e47703e, 0xffff703f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F } }
 
 /* xorl<.f><.cc> ZA,LIMM,UIMM6_20 0101111011000111x111xxxxxx1xxxxx */
-{ "xorl", 0x5ec77020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
+{ "xorl", 0x5ec77020, 0xffff7020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC } }
 
 /* xorl<.f> ZA,XIMM,SIMM12_20 0101110010000111x111xxxxxxxxxxxx */
-{ "xorl", 0x5c877000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
+{ "xorl", 0x5c877000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, SIMM12_20 }, { C_F } }
 
 /* xorl<.f> ZA,LIMM,SIMM12_20 0101111010000111x111xxxxxxxxxxxx */
-{ "xorl", 0x5e877000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
+{ "xorl", 0x5e877000, 0xffff7000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { C_F } }
 
 /* xorl<.f> RA,XIMM,XIMMdup 0101110000000111x111111100xxxxxx */
-{ "xorl", 0x5c077f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F } }
+{ "xorl", 0x5c077f00, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, XIMMdup }, { C_F } }
 
 /* xorl<.f> ZA,XIMM,XIMMdup 0101110000000111x111111100111110 */
-{ "xorl", 0x5c077f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F } }
+{ "xorl", 0x5c077f3e, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F } }
 
 /* xorl<.f><.cc> ZA,XIMM,XIMMdup 0101110011000111x1111111000xxxxx */
-{ "xorl", 0x5cc77f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
+{ "xorl", 0x5cc77f00, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC } }
 
 /* xorl<.f> RA,LIMM,LIMMdup 0101111000000111x111111110xxxxxx */
-{ "xorl", 0x5e077f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F } }
+{ "xorl", 0x5e077f80, 0xffff7fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { C_F } }
 
 /* xorl<.f> ZA,LIMM,LIMMdup 0101111000000111x111111110111110 */
-{ "xorl", 0x5e077fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F } }
+{ "xorl", 0x5e077fbe, 0xffff7fff, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F } }
 
 /* xorl<.f><.cc> ZA,LIMM,LIMMdup 0101111011000111x1111111100xxxxx */
-{ "xorl", 0x5ec77f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
+{ "xorl", 0x5ec77f80, 0xffff7fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC } }
 
 /* xor_s RB_S,RB_Sdup,RC_S 01111xxxxxx00111 */
-{ "xor_s", 0x00007807, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
+{ "xor_s", 0x00007807, 0x0000f81f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, LOGICAL, ARC_INSN_SUBCLASS_NONE, { RB_S, RB_Sdup, RC_S }, { 0 } }
 
 /* fhmadd FA,FB,FC,FD 11100xxxxxxxx00000xx1xxxxx0xxxxx */
-{ "fhmadd", 0xe0000800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fhmadd", 0xe0000800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fhmsub FA,FB,FC,FD 11100xxxxxxxx00000xx1xxxxx1xxxxx */
-{ "fhmsub", 0xe0000820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fhmsub", 0xe0000820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fhnmadd FA,FB,FC,FD 11100xxxxxxxx00100xx1xxxxx0xxxxx */
-{ "fhnmadd", 0xe0010800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fhnmadd", 0xe0010800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fhnmsub FA,FB,FC,FD 11100xxxxxxxx00100xx1xxxxx1xxxxx */
-{ "fhnmsub", 0xe0010820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fhnmsub", 0xe0010820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fsmadd FA,FB,FC,FD 11100xxxxxxxx00001xx1xxxxx0xxxxx */
-{ "fsmadd", 0xe0004800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fsmadd", 0xe0004800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fsmsub FA,FB,FC,FD 11100xxxxxxxx00001xx1xxxxx1xxxxx */
-{ "fsmsub", 0xe0004820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fsmsub", 0xe0004820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fsnmadd FA,FB,FC,FD 11100xxxxxxxx00101xx1xxxxx0xxxxx */
-{ "fsnmadd", 0xe0014800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fsnmadd", 0xe0014800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fsnmsub FA,FB,FC,FD 11100xxxxxxxx00101xx1xxxxx1xxxxx */
-{ "fsnmsub", 0xe0014820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fsnmsub", 0xe0014820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fdmadd FA,FB,FC,FD 11100xxxxxxxx00010xx1xxxxx0xxxxx */
-{ "fdmadd", 0xe0008800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fdmadd", 0xe0008800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fdmsub FA,FB,FC,FD 11100xxxxxxxx00010xx1xxxxx1xxxxx */
-{ "fdmsub", 0xe0008820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fdmsub", 0xe0008820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fdnmadd FA,FB,FC,FD 11100xxxxxxxx00110xx1xxxxx0xxxxx */
-{ "fdnmadd", 0xe0018800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fdnmadd", 0xe0018800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* fdnmsub FA,FB,FC,FD 11100xxxxxxxx00110xx1xxxxx1xxxxx */
-{ "fdnmsub", 0xe0018820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "fdnmsub", 0xe0018820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfhmadd FA,FB,FC,FD 11100xxxxxxxx01000xx1xxxxx0xxxxx */
-{ "vfhmadd", 0xe0020800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfhmadd", 0xe0020800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfhmsub FA,FB,FC,FD 11100xxxxxxxx01000xx1xxxxx1xxxxx */
-{ "vfhmsub", 0xe0020820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfhmsub", 0xe0020820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfhnmadd FA,FB,FC,FD 11100xxxxxxxx01100xx1xxxxx0xxxxx */
-{ "vfhnmadd", 0xe0030800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfhnmadd", 0xe0030800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfhnmsub FA,FB,FC,FD 11100xxxxxxxx01100xx1xxxxx1xxxxx */
-{ "vfhnmsub", 0xe0030820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfhnmsub", 0xe0030820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfhmadds FA,FB,FC,FD 11100xxxxxxxx11000xx1xxxxx0xxxxx */
-{ "vfhmadds", 0xe0060800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfhmadds", 0xe0060800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfhmsubs FA,FB,FC,FD 11100xxxxxxxx11000xx1xxxxx1xxxxx */
-{ "vfhmsubs", 0xe0060820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfhmsubs", 0xe0060820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfhnmadds FA,FB,FC,FD 11100xxxxxxxx11100xx1xxxxx0xxxxx */
-{ "vfhnmadds", 0xe0070800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfhnmadds", 0xe0070800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfhnmsubs FA,FB,FC,FD 11100xxxxxxxx11100xx1xxxxx1xxxxx */
-{ "vfhnmsubs", 0xe0070820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfhnmsubs", 0xe0070820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfsmadd FA,FB,FC,FD 11100xxxxxxxx01001xx1xxxxx0xxxxx */
-{ "vfsmadd", 0xe0024800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfsmadd", 0xe0024800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfsmsub FA,FB,FC,FD 11100xxxxxxxx01001xx1xxxxx1xxxxx */
-{ "vfsmsub", 0xe0024820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfsmsub", 0xe0024820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfsnmadd FA,FB,FC,FD 11100xxxxxxxx01101xx1xxxxx0xxxxx */
-{ "vfsnmadd", 0xe0034800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfsnmadd", 0xe0034800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfsnmsub FA,FB,FC,FD 11100xxxxxxxx01101xx1xxxxx1xxxxx */
-{ "vfsnmsub", 0xe0034820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfsnmsub", 0xe0034820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfsmadds FA,FB,FC,FD 11100xxxxxxxx11001xx1xxxxx0xxxxx */
-{ "vfsmadds", 0xe0064800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfsmadds", 0xe0064800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfsmsubs FA,FB,FC,FD 11100xxxxxxxx11001xx1xxxxx1xxxxx */
-{ "vfsmsubs", 0xe0064820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfsmsubs", 0xe0064820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfsnmadds FA,FB,FC,FD 11100xxxxxxxx11101xx1xxxxx0xxxxx */
-{ "vfsnmadds", 0xe0074800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfsnmadds", 0xe0074800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfsnmsubs FA,FB,FC,FD 11100xxxxxxxx11101xx1xxxxx1xxxxx */
-{ "vfsnmsubs", 0xe0074820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC, FD }, { 0 } }
+{ "vfsnmsubs", 0xe0074820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC, FD }, { 0 } }
 
 /* vfdmadd FDA,FDB,FDC,FDD 11100xxxxxxxx01010xx1xxxxx0xxxxx */
-{ "vfdmadd", 0xe0028800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC, FDD }, { 0 } }
+{ "vfdmadd", 0xe0028800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC, FDD }, { 0 } }
 
 /* vfdmsub FDA,FDB,FDC,FDD 11100xxxxxxxx01010xx1xxxxx1xxxxx */
-{ "vfdmsub", 0xe0028820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC, FDD }, { 0 } }
+{ "vfdmsub", 0xe0028820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC, FDD }, { 0 } }
 
 /* vfdnmadd FDA,FDB,FDC,FDD 11100xxxxxxxx01110xx1xxxxx0xxxxx */
-{ "vfdnmadd", 0xe0038800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC, FDD }, { 0 } }
+{ "vfdnmadd", 0xe0038800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC, FDD }, { 0 } }
 
 /* vfdnmsub FDA,FDB,FDC,FDD 11100xxxxxxxx01110xx1xxxxx1xxxxx */
-{ "vfdnmsub", 0xe0038820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC, FDD }, { 0 } }
+{ "vfdnmsub", 0xe0038820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC, FDD }, { 0 } }
 
 /* vfdmadds FDA,FDB,FDC,FDD 11100xxxxxxxx11010xx1xxxxx0xxxxx */
-{ "vfdmadds", 0xe0068800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC, FDD }, { 0 } }
+{ "vfdmadds", 0xe0068800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC, FDD }, { 0 } }
 
 /* vfdmsubs FDA,FDB,FDC,FDD 11100xxxxxxxx11010xx1xxxxx1xxxxx */
-{ "vfdmsubs", 0xe0068820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC, FDD }, { 0 } }
+{ "vfdmsubs", 0xe0068820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC, FDD }, { 0 } }
 
 /* vfdnmadds FDA,FDB,FDC,FDD 11100xxxxxxxx11110xx1xxxxx0xxxxx */
-{ "vfdnmadds", 0xe0078800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC, FDD }, { 0 } }
+{ "vfdnmadds", 0xe0078800, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC, FDD }, { 0 } }
 
 /* vfdnmsubs FDA,FDB,FDC,FDD 11100xxxxxxxx11110xx1xxxxx1xxxxx */
-{ "vfdnmsubs", 0xe0078820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC, FDD }, { 0 } }
+{ "vfdnmsubs", 0xe0078820, 0xf807c820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC, FDD }, { 0 } }
 
 /* fhadd FA,FB,FC 11100xxx0000000000xx0xxxxx1xxxxx */
-{ "fhadd", 0xe0000020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhadd", 0xe0000020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhsub FA,FB,FC 11100xxx0000000100xx0xxxxx1xxxxx */
-{ "fhsub", 0xe0010020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhsub", 0xe0010020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhmul FA,FB,FC 11100xxx0000001000xx0xxxxx1xxxxx */
-{ "fhmul", 0xe0020020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhmul", 0xe0020020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhdiv FA,FB,FC 11100xxx0000001100xx0xxxxx1xxxxx */
-{ "fhdiv", 0xe0030020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhdiv", 0xe0030020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhmin FA,FB,FC 11100xxx0000011000xx0xxxxx1xxxxx */
-{ "fhmin", 0xe0060020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhmin", 0xe0060020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhmax FA,FB,FC 11100xxx0000011100xx0xxxxx1xxxxx */
-{ "fhmax", 0xe0070020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhmax", 0xe0070020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhsgnj FA,FB,FC 11100xxx0000100000xx0xxxxx1xxxxx */
-{ "fhsgnj", 0xe0080020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhsgnj", 0xe0080020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhsgnjn FA,FB,FC 11100xxx0000101000xx0xxxxx1xxxxx */
-{ "fhsgnjn", 0xe00a0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhsgnjn", 0xe00a0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhsgnjx FA,FB,FC 11100xxx0000101100xx0xxxxx1xxxxx */
-{ "fhsgnjx", 0xe00b0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fhsgnjx", 0xe00b0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fsadd FA,FB,FC 11100xxx0000000001xx0xxxxx1xxxxx */
-{ "fsadd", 0xe0004020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fsadd", 0xe0004020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fssub FA,FB,FC 11100xxx0000000101xx0xxxxx1xxxxx */
-{ "fssub", 0xe0014020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fssub", 0xe0014020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fsmul FA,FB,FC 11100xxx0000001001xx0xxxxx1xxxxx */
-{ "fsmul", 0xe0024020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fsmul", 0xe0024020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fsdiv FA,FB,FC 11100xxx0000001101xx0xxxxx1xxxxx */
-{ "fsdiv", 0xe0034020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fsdiv", 0xe0034020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fsmin FA,FB,FC 11100xxx0000011001xx0xxxxx1xxxxx */
-{ "fsmin", 0xe0064020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fsmin", 0xe0064020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fsmax FA,FB,FC 11100xxx0000011101xx0xxxxx1xxxxx */
-{ "fsmax", 0xe0074020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fsmax", 0xe0074020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fssgnj FA,FB,FC 11100xxx0000100001xx0xxxxx1xxxxx */
-{ "fssgnj", 0xe0084020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fssgnj", 0xe0084020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fssgnjn FA,FB,FC 11100xxx0000101001xx0xxxxx1xxxxx */
-{ "fssgnjn", 0xe00a4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fssgnjn", 0xe00a4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fssgnjx FA,FB,FC 11100xxx0000101101xx0xxxxx1xxxxx */
-{ "fssgnjx", 0xe00b4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fssgnjx", 0xe00b4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fdadd FA,FB,FC 11100xxx0000000010xx0xxxxx1xxxxx */
-{ "fdadd", 0xe0008020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fdadd", 0xe0008020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fdsub FA,FB,FC 11100xxx0000000110xx0xxxxx1xxxxx */
-{ "fdsub", 0xe0018020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fdsub", 0xe0018020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fdmul FA,FB,FC 11100xxx0000001010xx0xxxxx1xxxxx */
-{ "fdmul", 0xe0028020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fdmul", 0xe0028020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fddiv FA,FB,FC 11100xxx0000001110xx0xxxxx1xxxxx */
-{ "fddiv", 0xe0038020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fddiv", 0xe0038020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fdmin FA,FB,FC 11100xxx0000011010xx0xxxxx1xxxxx */
-{ "fdmin", 0xe0068020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fdmin", 0xe0068020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fdmax FA,FB,FC 11100xxx0000011110xx0xxxxx1xxxxx */
-{ "fdmax", 0xe0078020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fdmax", 0xe0078020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fdsgnj FA,FB,FC 11100xxx0000100010xx0xxxxx1xxxxx */
-{ "fdsgnj", 0xe0088020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fdsgnj", 0xe0088020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fdsgnjn FA,FB,FC 11100xxx0000101010xx0xxxxx1xxxxx */
-{ "fdsgnjn", 0xe00a8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fdsgnjn", 0xe00a8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fdsgnjx FA,FB,FC 11100xxx0000101110xx0xxxxx1xxxxx */
-{ "fdsgnjx", 0xe00b8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "fdsgnjx", 0xe00b8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* fhcmp FB,FC 11100xxx0000010000xx0xxxxx1xxxxx */
-{ "fhcmp", 0xe0040020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FB, FC }, { 0 } }
+{ "fhcmp", 0xe0040020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FB, FC }, { 0 } }
 
 /* fhcmpf FB,FC 11100xxx0000010100xx0xxxxx1xxxxx */
-{ "fhcmpf", 0xe0050020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FB, FC }, { 0 } }
+{ "fhcmpf", 0xe0050020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FB, FC }, { 0 } }
 
 /* fscmp FB,FC 11100xxx0000010001xx0xxxxx1xxxxx */
-{ "fscmp", 0xe0044020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FB, FC }, { 0 } }
+{ "fscmp", 0xe0044020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FB, FC }, { 0 } }
 
 /* fscmpf FB,FC 11100xxx0000010101xx0xxxxx1xxxxx */
-{ "fscmpf", 0xe0054020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FB, FC }, { 0 } }
+{ "fscmpf", 0xe0054020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FB, FC }, { 0 } }
 
 /* fdcmp FB,FC 11100xxx0000010010xx0xxxxx1xxxxx */
-{ "fdcmp", 0xe0048020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FB, FC }, { 0 } }
+{ "fdcmp", 0xe0048020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FB, FC }, { 0 } }
 
 /* fdcmpf FB,FC 11100xxx0000010110xx0xxxxx1xxxxx */
-{ "fdcmpf", 0xe0058020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FB, FC }, { 0 } }
+{ "fdcmpf", 0xe0058020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FB, FC }, { 0 } }
 
 /* vfhadd FA,FB,FC 11100xxx0001000000xx0xxxxx1xxxxx */
-{ "vfhadd", 0xe0100020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhadd", 0xe0100020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhsub FA,FB,FC 11100xxx0001000100xx0xxxxx1xxxxx */
-{ "vfhsub", 0xe0110020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhsub", 0xe0110020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhmul FA,FB,FC 11100xxx0001001000xx0xxxxx1xxxxx */
-{ "vfhmul", 0xe0120020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhmul", 0xe0120020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhdiv FA,FB,FC 11100xxx0001001100xx0xxxxx1xxxxx */
-{ "vfhdiv", 0xe0130020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhdiv", 0xe0130020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhadds FA,FB,FC 11100xxx0001010000xx0xxxxx1xxxxx */
-{ "vfhadds", 0xe0140020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhadds", 0xe0140020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhsubs FA,FB,FC 11100xxx0001010100xx0xxxxx1xxxxx */
-{ "vfhsubs", 0xe0150020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhsubs", 0xe0150020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhmuls FA,FB,FC 11100xxx0001011000xx0xxxxx1xxxxx */
-{ "vfhmuls", 0xe0160020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhmuls", 0xe0160020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhdivs FA,FB,FC 11100xxx0001011100xx0xxxxx1xxxxx */
-{ "vfhdivs", 0xe0170020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhdivs", 0xe0170020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhunpkl FA,FB,FC 11100xxx0001100000xx0xxxxx1xxxxx */
-{ "vfhunpkl", 0xe0180020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhunpkl", 0xe0180020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhunpkm FA,FB,FC 11100xxx0001100100xx0xxxxx1xxxxx */
-{ "vfhunpkm", 0xe0190020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhunpkm", 0xe0190020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhpackl FA,FB,FC 11100xxx0001101000xx0xxxxx1xxxxx */
-{ "vfhpackl", 0xe01a0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhpackl", 0xe01a0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhpackm FA,FB,FC 11100xxx0001101100xx0xxxxx1xxxxx */
-{ "vfhpackm", 0xe01b0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhpackm", 0xe01b0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhbflyl FA,FB,FC 11100xxx0001110000xx0xxxxx1xxxxx */
-{ "vfhbflyl", 0xe01c0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhbflyl", 0xe01c0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhbflym FA,FB,FC 11100xxx0001110100xx0xxxxx1xxxxx */
-{ "vfhbflym", 0xe01d0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhbflym", 0xe01d0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhaddsub FA,FB,FC 11100xxx0001111000xx0xxxxx1xxxxx */
-{ "vfhaddsub", 0xe01e0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhaddsub", 0xe01e0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfhsubadd FA,FB,FC 11100xxx0001111100xx0xxxxx1xxxxx */
-{ "vfhsubadd", 0xe01f0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfhsubadd", 0xe01f0020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsadd FA,FB,FC 11100xxx0001000001xx0xxxxx1xxxxx */
-{ "vfsadd", 0xe0104020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsadd", 0xe0104020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfssub FA,FB,FC 11100xxx0001000101xx0xxxxx1xxxxx */
-{ "vfssub", 0xe0114020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfssub", 0xe0114020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsmul FA,FB,FC 11100xxx0001001001xx0xxxxx1xxxxx */
-{ "vfsmul", 0xe0124020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsmul", 0xe0124020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsdiv FA,FB,FC 11100xxx0001001101xx0xxxxx1xxxxx */
-{ "vfsdiv", 0xe0134020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsdiv", 0xe0134020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsadds FA,FB,FC 11100xxx0001010001xx0xxxxx1xxxxx */
-{ "vfsadds", 0xe0144020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsadds", 0xe0144020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfssubs FA,FB,FC 11100xxx0001010101xx0xxxxx1xxxxx */
-{ "vfssubs", 0xe0154020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfssubs", 0xe0154020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsmuls FA,FB,FC 11100xxx0001011001xx0xxxxx1xxxxx */
-{ "vfsmuls", 0xe0164020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsmuls", 0xe0164020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsdivs FA,FB,FC 11100xxx0001011101xx0xxxxx1xxxxx */
-{ "vfsdivs", 0xe0174020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsdivs", 0xe0174020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsunpkl FA,FB,FC 11100xxx0001100001xx0xxxxx1xxxxx */
-{ "vfsunpkl", 0xe0184020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsunpkl", 0xe0184020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsunpkm FA,FB,FC 11100xxx0001100101xx0xxxxx1xxxxx */
-{ "vfsunpkm", 0xe0194020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsunpkm", 0xe0194020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfspackl FA,FB,FC 11100xxx0001101001xx0xxxxx1xxxxx */
-{ "vfspackl", 0xe01a4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfspackl", 0xe01a4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfspackm FA,FB,FC 11100xxx0001101101xx0xxxxx1xxxxx */
-{ "vfspackm", 0xe01b4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfspackm", 0xe01b4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsbflyl FA,FB,FC 11100xxx0001110001xx0xxxxx1xxxxx */
-{ "vfsbflyl", 0xe01c4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsbflyl", 0xe01c4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsbflym FA,FB,FC 11100xxx0001110101xx0xxxxx1xxxxx */
-{ "vfsbflym", 0xe01d4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsbflym", 0xe01d4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfsaddsub FA,FB,FC 11100xxx0001111001xx0xxxxx1xxxxx */
-{ "vfsaddsub", 0xe01e4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfsaddsub", 0xe01e4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfssubadd FA,FB,FC 11100xxx0001111101xx0xxxxx1xxxxx */
-{ "vfssubadd", 0xe01f4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, FC }, { 0 } }
+{ "vfssubadd", 0xe01f4020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, FC }, { 0 } }
 
 /* vfdadd FDA,FDB,FDC 11100xxx0001000010xx0xxxxx1xxxxx */
-{ "vfdadd", 0xe0108020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdadd", 0xe0108020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdsub FDA,FDB,FDC 11100xxx0001000110xx0xxxxx1xxxxx */
-{ "vfdsub", 0xe0118020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdsub", 0xe0118020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdmul FDA,FDB,FDC 11100xxx0001001010xx0xxxxx1xxxxx */
-{ "vfdmul", 0xe0128020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdmul", 0xe0128020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfddiv FDA,FDB,FDC 11100xxx0001001110xx0xxxxx1xxxxx */
-{ "vfddiv", 0xe0138020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfddiv", 0xe0138020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdadds FDA,FDB,FDC 11100xxx0001010010xx0xxxxx1xxxxx */
-{ "vfdadds", 0xe0148020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdadds", 0xe0148020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdsubs FDA,FDB,FDC 11100xxx0001010110xx0xxxxx1xxxxx */
-{ "vfdsubs", 0xe0158020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdsubs", 0xe0158020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdmuls FDA,FDB,FDC 11100xxx0001011010xx0xxxxx1xxxxx */
-{ "vfdmuls", 0xe0168020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdmuls", 0xe0168020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfddivs FDA,FDB,FDC 11100xxx0001011110xx0xxxxx1xxxxx */
-{ "vfddivs", 0xe0178020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfddivs", 0xe0178020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdunpkl FDA,FDB,FDC 11100xxx0001100010xx0xxxxx1xxxxx */
-{ "vfdunpkl", 0xe0188020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdunpkl", 0xe0188020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdunpkm FDA,FDB,FDC 11100xxx0001100110xx0xxxxx1xxxxx */
-{ "vfdunpkm", 0xe0198020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdunpkm", 0xe0198020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdpackl FDA,FDB,FDC 11100xxx0001101010xx0xxxxx1xxxxx */
-{ "vfdpackl", 0xe01a8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdpackl", 0xe01a8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdpackm FDA,FDB,FDC 11100xxx0001101110xx0xxxxx1xxxxx */
-{ "vfdpackm", 0xe01b8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdpackm", 0xe01b8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdbflyl FDA,FDB,FDC 11100xxx0001110010xx0xxxxx1xxxxx */
-{ "vfdbflyl", 0xe01c8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdbflyl", 0xe01c8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdbflym FDA,FDB,FDC 11100xxx0001110110xx0xxxxx1xxxxx */
-{ "vfdbflym", 0xe01d8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdbflym", 0xe01d8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdaddsub FDA,FDB,FDC 11100xxx0001111010xx0xxxxx1xxxxx */
-{ "vfdaddsub", 0xe01e8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdaddsub", 0xe01e8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* vfdsubadd FDA,FDB,FDC 11100xxx0001111110xx0xxxxx1xxxxx */
-{ "vfdsubadd", 0xe01f8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB, FDC }, { 0 } }
+{ "vfdsubadd", 0xe01f8020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB, FDC }, { 0 } }
 
 /* fhsqrt FA,FB 111000000100000000000xxxxx1xxxxx */
-{ "fhsqrt", 0xe0400020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "fhsqrt", 0xe0400020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* fssqrt FA,FB 111000000100000001000xxxxx1xxxxx */
-{ "fssqrt", 0xe0404020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "fssqrt", 0xe0404020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* fdsqrt FA,FB 111000000100000010000xxxxx1xxxxx */
-{ "fdsqrt", 0xe0408020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "fdsqrt", 0xe0408020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* vfhsqrt FA,FB 111000000100000100000xxxxx1xxxxx */
-{ "vfhsqrt", 0xe0410020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "vfhsqrt", 0xe0410020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* vfssqrt FA,FB 111000000100000101000xxxxx1xxxxx */
-{ "vfssqrt", 0xe0414020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "vfssqrt", 0xe0414020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* vfdsqrt FDA,FDB 111000000100000110000xxxxx1xxxxx */
-{ "vfdsqrt", 0xe0418020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB }, { 0 } }
+{ "vfdsqrt", 0xe0418020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB }, { 0 } }
 
 /* vfhexch FA,FB 111000000100001000000xxxxx1xxxxx */
-{ "vfhexch", 0xe0420020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "vfhexch", 0xe0420020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* vfsexch FA,FB 111000000100001001000xxxxx1xxxxx */
-{ "vfsexch", 0xe0424020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "vfsexch", 0xe0424020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* vfdexch FDA,FDB 111000000100001010000xxxxx1xxxxx */
-{ "vfdexch", 0xe0428020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FDA, FDB }, { 0 } }
+{ "vfdexch", 0xe0428020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FDA, FDB }, { 0 } }
 
 /* fhmov FA,FB 11100xxx0100100000xx0xxxxx1xxxxx */
-{ "fhmov", 0xe0480020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { C_FPCC } }
+{ "fhmov", 0xe0480020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { C_FPCC } }
 
 /* fsmov FA,FB 11100xxx0100100001xx0xxxxx1xxxxx */
-{ "fsmov", 0xe0484020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { C_FPCC } }
+{ "fsmov", 0xe0484020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { C_FPCC } }
 
 /* fdmov FA,FB 11100xxx0100100010xx0xxxxx1xxxxx */
-{ "fdmov", 0xe0488020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { C_FPCC } }
+{ "fdmov", 0xe0488020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { C_FPCC } }
 
 /* vfhmov FA,FB 11100xxx0100100100xx0xxxxx1xxxxx */
-{ "vfhmov", 0xe0490020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { C_FPCC } }
+{ "vfhmov", 0xe0490020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { C_FPCC } }
 
 /* vfsmov FA,FB 11100xxx0100100101xx0xxxxx1xxxxx */
-{ "vfsmov", 0xe0494020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { C_FPCC } }
+{ "vfsmov", 0xe0494020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { C_FPCC } }
 
 /* vfdmov FA,FB 11100xxx0100100110xx0xxxxx1xxxxx */
-{ "vfdmov", 0xe0498020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { C_FPCC } }
+{ "vfdmov", 0xe0498020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { C_FPCC } }
 
 /* fuint2s FA,FRB 11100xxx1110000000xx0xxxxx100000 */
-{ "fuint2s", 0xe0e00020, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "fuint2s", 0xe0e00020, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* fuint2d FA,FRB 11100xxx1110000100xx0xxxxx100000 */
-{ "fuint2d", 0xe0e10020, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "fuint2d", 0xe0e10020, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* ful2s FA,FRB 11100xxx1110001000xx0xxxxx100000 */
-{ "ful2s", 0xe0e20020, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "ful2s", 0xe0e20020, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* ful2d FA,FRB 11100xxx1110001100xx0xxxxx100000 */
-{ "ful2d", 0xe0e30020, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "ful2d", 0xe0e30020, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* fs2uint FRD,FC 11100xxx0110000000xx0xxxxx100001 */
-{ "fs2uint", 0xe0600021, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fs2uint", 0xe0600021, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fs2ul FRD,FC 11100xxx0110000100xx0xxxxx100001 */
-{ "fs2ul", 0xe0610021, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fs2ul", 0xe0610021, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fd2uint FRD,FC 11100xxx0110001000xx0xxxxx100001 */
-{ "fd2uint", 0xe0620021, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fd2uint", 0xe0620021, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fd2ul FRD,FC 11100xxx0110001100xx0xxxxx100001 */
-{ "fd2ul", 0xe0630021, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fd2ul", 0xe0630021, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fint2s FA,FRB 11100xxx1110000000xx0xxxxx100010 */
-{ "fint2s", 0xe0e00022, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "fint2s", 0xe0e00022, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* fint2d FA,FRB 11100xxx1110000100xx0xxxxx100010 */
-{ "fint2d", 0xe0e10022, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "fint2d", 0xe0e10022, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* fl2s FA,FRB 11100xxx1110001000xx0xxxxx100010 */
-{ "fl2s", 0xe0e20022, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "fl2s", 0xe0e20022, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* fl2d FA,FRB 11100xxx1110001100xx0xxxxx100010 */
-{ "fl2d", 0xe0e30022, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "fl2d", 0xe0e30022, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* fs2int FRD,FC 11100xxx0110000000xx0xxxxx100011 */
-{ "fs2int", 0xe0600023, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fs2int", 0xe0600023, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fs2l FRD,FC 11100xxx0110000100xx0xxxxx100011 */
-{ "fs2l", 0xe0610023, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fs2l", 0xe0610023, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fd2int FRD,FC 11100xxx0110001000xx0xxxxx100011 */
-{ "fd2int", 0xe0620023, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fd2int", 0xe0620023, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fd2l FRD,FC 11100xxx0110001100xx0xxxxx100011 */
-{ "fd2l", 0xe0630023, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fd2l", 0xe0630023, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fs2d FA,FC 11100xxx0110000100xx0xxxxx100100 */
-{ "fs2d", 0xe0610024, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fs2d", 0xe0610024, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fd2s FA,FC 11100xxx0110001000xx0xxxxx100100 */
-{ "fd2s", 0xe0620024, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fd2s", 0xe0620024, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fsrnd FA,FC 11100xxx0110000000xx0xxxxx100110 */
-{ "fsrnd", 0xe0600026, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fsrnd", 0xe0600026, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fdrnd FA,FC 11100xxx0110001100xx0xxxxx100110 */
-{ "fdrnd", 0xe0630026, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fdrnd", 0xe0630026, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fs2uint_rz FRD,FC 11100xxx0110000000xx0xxxxx101001 */
-{ "fs2uint_rz", 0xe0600029, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fs2uint_rz", 0xe0600029, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fs2ul_rz FRD,FC 11100xxx0110000100xx0xxxxx101001 */
-{ "fs2ul_rz", 0xe0610029, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fs2ul_rz", 0xe0610029, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fd2uint_rz FRD,FC 11100xxx0110001000xx0xxxxx101001 */
-{ "fd2uint_rz", 0xe0620029, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fd2uint_rz", 0xe0620029, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fd2ul_rz FRD,FC 11100xxx0110001100xx0xxxxx101001 */
-{ "fd2ul_rz", 0xe0630029, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fd2ul_rz", 0xe0630029, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fs2int_rz FRD,FC 11100xxx0110000000xx0xxxxx101011 */
-{ "fs2int_rz", 0xe060002b, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fs2int_rz", 0xe060002b, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fs2l_rz FRD,FC 11100xxx0110000100xx0xxxxx101011 */
-{ "fs2l_rz", 0xe061002b, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fs2l_rz", 0xe061002b, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fd2int_rz FRD,FC 11100xxx0110001000xx0xxxxx101011 */
-{ "fd2int_rz", 0xe062002b, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fd2int_rz", 0xe062002b, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fd2l_rz FRD,FC 11100xxx0110001100xx0xxxxx101011 */
-{ "fd2l_rz", 0xe063002b, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fd2l_rz", 0xe063002b, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fsrnd_rz FA,FC 11100xxx0110000000xx0xxxxx101110 */
-{ "fsrnd_rz", 0xe060002e, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fsrnd_rz", 0xe060002e, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fdrnd_rz FA,FC 11100xxx0110001100xx0xxxxx101110 */
-{ "fdrnd_rz", 0xe063002e, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fdrnd_rz", 0xe063002e, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fmvi2s FA,FRB 11100xxx1110000000xx0xxxxx110000 */
-{ "fmvi2s", 0xe0e00030, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "fmvi2s", 0xe0e00030, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* fmvl2d FA,FRB 11100xxx1110001100xx0xxxxx110000 */
-{ "fmvl2d", 0xe0e30030, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FRB }, { 0 } }
+{ "fmvl2d", 0xe0e30030, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FRB }, { 0 } }
 
 /* fmvs2i FRD,FC 11100xxx0110000000xx0xxxxx110001 */
-{ "fmvs2i", 0xe0600031, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fmvs2i", 0xe0600031, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fmvd2l FRD,FC 11100xxx0110001100xx0xxxxx110001 */
-{ "fmvd2l", 0xe0630031, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FRD, FC }, { 0 } }
+{ "fmvd2l", 0xe0630031, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FRD, FC }, { 0 } }
 
 /* fs2h FA,FC 11100xxx0110000000xx0xxxxx110100 */
-{ "fs2h", 0xe0600034, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fs2h", 0xe0600034, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fh2s FA,FC 11100xxx0110000000xx0xxxxx110101 */
-{ "fh2s", 0xe0600035, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fh2s", 0xe0600035, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fs2h_rz FA,FC 11100xxx0110000000xx0xxxxx111100 */
-{ "fs2h_rz", 0xe060003c, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FC }, { 0 } }
+{ "fs2h_rz", 0xe060003c, 0xf8ffc83f, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FC }, { 0 } }
 
 /* fld16<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx0xx100 */
-{ "fld16", 0x68000004, 0xf8000827, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fld16", 0x68000004, 0xf8000827, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fld16 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx000100 */
-{ "fld16", 0x6e007004, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fld16", 0x6e007004, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fld32<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx0xx000 */
-{ "fld32", 0x68000000, 0xf8000827, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fld32", 0x68000000, 0xf8000827, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fld32 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx000000 */
-{ "fld32", 0x6e007000, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fld32", 0x6e007000, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fld64<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx0xx010 */
-{ "fld64", 0x68000002, 0xf8000827, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fld64", 0x68000002, 0xf8000827, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fld64 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx000010 */
-{ "fld64", 0x6e007002, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fld64", 0x6e007002, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fldd32<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx1xx000 */
-{ "fldd32", 0x68000020, 0xf8000827, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fldd32", 0x68000020, 0xf8000827, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fldd32 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx100000 */
-{ "fldd32", 0x6e007020, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fldd32", 0x6e007020, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fldd64<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx1xx010 */
-{ "fldd64", 0x68000022, 0xf8000827, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fldd64", 0x68000022, 0xf8000827, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fldd64 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx100010 */
-{ "fldd64", 0x6e007022, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fldd64", 0x6e007022, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fst16<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx0xx101 */
-{ "fst16", 0x68000005, 0xf8000827, ARC_OPCODE_ARC64, STORE, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fst16", 0x68000005, 0xf8000827, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fst16 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx000101 */
-{ "fst16", 0x6e007005, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fst16", 0x6e007005, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fst32<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx0xx001 */
-{ "fst32", 0x68000001, 0xf8000827, ARC_OPCODE_ARC64, STORE, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fst32", 0x68000001, 0xf8000827, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fst32 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx000001 */
-{ "fst32", 0x6e007001, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fst32", 0x6e007001, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fst64<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx0xx011 */
-{ "fst64", 0x68000003, 0xf8000827, ARC_OPCODE_ARC64, STORE, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fst64", 0x68000003, 0xf8000827, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fst64 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx000011 */
-{ "fst64", 0x6e007003, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fst64", 0x6e007003, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fstd32<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx1xx001 */
-{ "fstd32", 0x68000021, 0xf8000827, ARC_OPCODE_ARC64, STORE, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fstd32", 0x68000021, 0xf8000827, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fstd32 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx100001 */
-{ "fstd32", 0x6e007021, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fstd32", 0x6e007021, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* fstd64<.aa> FA,BRAKET,RB,SIMM9_8,BRAKETdup 01101xxxxxxxxxxxxxxx0xxxxx1xx011 */
-{ "fstd64", 0x68000023, 0xf8000827, ARC_OPCODE_ARC64, STORE, NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
+{ "fstd64", 0x68000023, 0xf8000827, ARC_OPCODE_ARC64, STORE, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }
 
 /* fstd64 FA,BRAKET,LIMM,BRAKETdup 011011100000000001110xxxxx100011 */
-{ "fstd64", 0x6e007023, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
+{ "fstd64", 0x6e007023, 0xfffff83f, ARC_OPCODE_ARC64, LOAD, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, LIMM, BRAKETdup }, { 0 } }
 
 /* vfhext FA,FB,BRAKET,UIMM5_FP,BRAKETdup 11100xxx0101000000xx0xxxxx1xxxxx */
-{ "vfhext", 0xe0500020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, UIMM5_FP, BRAKETdup }, { 0 } }
+{ "vfhext", 0xe0500020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, BRAKET, UIMM5_FP, BRAKETdup }, { 0 } }
 
 /* vfhext FA,FB,BRAKET,FRB,BRAKETdup 11100xxx1000000000xx0xxxxx1xxxxx */
-{ "vfhext", 0xe0800020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, FRB, BRAKETdup }, { 0 } }
+{ "vfhext", 0xe0800020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, BRAKET, FRB, BRAKETdup }, { 0 } }
 
 /* vfsext FA,FB,BRAKET,UIMM5_FP,BRAKETdup 11100xxx0101000001xx0xxxxx1xxxxx */
-{ "vfsext", 0xe0504020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, UIMM5_FP, BRAKETdup }, { 0 } }
+{ "vfsext", 0xe0504020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, BRAKET, UIMM5_FP, BRAKETdup }, { 0 } }
 
 /* vfsext FA,FB,BRAKET,FRB,BRAKETdup 11100xxx1000000001xx0xxxxx1xxxxx */
-{ "vfsext", 0xe0804020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, FRB, BRAKETdup }, { 0 } }
+{ "vfsext", 0xe0804020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, BRAKET, FRB, BRAKETdup }, { 0 } }
 
 /* vfdext FA,FB,BRAKET,UIMM5_FP,BRAKETdup 11100xxx0101000010xx0xxxxx1xxxxx */
-{ "vfdext", 0xe0508020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, UIMM5_FP, BRAKETdup }, { 0 } }
+{ "vfdext", 0xe0508020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, BRAKET, UIMM5_FP, BRAKETdup }, { 0 } }
 
 /* vfdext FA,FB,BRAKET,FRB,BRAKETdup 11100xxx1000000010xx0xxxxx1xxxxx */
-{ "vfdext", 0xe0808020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, FRB, BRAKETdup }, { 0 } }
+{ "vfdext", 0xe0808020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB, BRAKET, FRB, BRAKETdup }, { 0 } }
 
 /* vfhins FA,BRAKET,UIMM5_FP,BRAKETdup,FB 11100xxx0101000100xx0xxxxx1xxxxx */
-{ "vfhins", 0xe0510020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, FB }, { 0 } }
+{ "vfhins", 0xe0510020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, FB }, { 0 } }
 
 /* vfhins FA,BRAKET,FRB,BRAKETdup,FB 11100xxx1000000100xx0xxxxx1xxxxx */
-{ "vfhins", 0xe0810020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, FRB, BRAKETdup, FB }, { 0 } }
+{ "vfhins", 0xe0810020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, FRB, BRAKETdup, FB }, { 0 } }
 
 /* vfsins FA,BRAKET,UIMM5_FP,BRAKETdup,FB 11100xxx0101000101xx0xxxxx1xxxxx */
-{ "vfsins", 0xe0514020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, FB }, { 0 } }
+{ "vfsins", 0xe0514020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, FB }, { 0 } }
 
 /* vfsins FA,BRAKET,FRB,BRAKETdup,FB 11100xxx1000000101xx0xxxxx1xxxxx */
-{ "vfsins", 0xe0814020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, FRB, BRAKETdup, FB }, { 0 } }
+{ "vfsins", 0xe0814020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, FRB, BRAKETdup, FB }, { 0 } }
 
 /* vfdins FA,BRAKET,UIMM5_FP,BRAKETdup,FB 11100xxx0101000110xx0xxxxx1xxxxx */
-{ "vfdins", 0xe0518020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, FB }, { 0 } }
+{ "vfdins", 0xe0518020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, FB }, { 0 } }
 
 /* vfdins FA,BRAKET,FRB,BRAKETdup,FB 11100xxx1000000110xx0xxxxx1xxxxx */
-{ "vfdins", 0xe0818020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, FRB, BRAKETdup, FB }, { 0 } }
+{ "vfdins", 0xe0818020, 0xf8ffc820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, BRAKET, FRB, BRAKETdup, FB }, { 0 } }
 
 /* vfhrep FA,FB 111000000101001000000xxxxx1xxxxx */
-{ "vfhrep", 0xe0520020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "vfhrep", 0xe0520020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* vfsrep FA,FB 111000000101001001000xxxxx1xxxxx */
-{ "vfsrep", 0xe0524020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "vfsrep", 0xe0524020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* vfdrep FA,FB 111000000101001010000xxxxx1xxxxx */
-{ "vfdrep", 0xe0528020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, { 0 } }
+{ "vfdrep", 0xe0528020, 0xfffff820, ARC_OPCODE_ARC64, FLOAT, ARC_INSN_SUBCLASS_NONE, { FA, FB }, { 0 } }
 
 /* vmin2 RA,RB,RC 00101xxx001110001xxxxxxxxxxxxxxx */
-{ "vmin2", 0x28388000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vmin2", 0x28388000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vmin2 ZA,RB,RC 00101xxx001110001xxxxxxxxx111110 */
-{ "vmin2", 0x2838803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vmin2", 0x2838803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vmin2<.cc> RB,RBdup,RC 00101xxx111110001xxxxxxxxx0xxxxx */
-{ "vmin2", 0x28f88000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vmin2", 0x28f88000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vmin2 RA,RB,UIMM6_20 00101xxx011110001xxxxxxxxxxxxxxx */
-{ "vmin2", 0x28788000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vmin2", 0x28788000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vmin2 ZA,RB,UIMM6_20 00101xxx011110001xxxxxxxxx111110 */
-{ "vmin2", 0x2878803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vmin2", 0x2878803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vmin2<.cc> RB,RBdup,UIMM6_20 00101xxx111110001xxxxxxxxx1xxxxx */
-{ "vmin2", 0x28f88020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vmin2", 0x28f88020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vmin2 RB,RBdup,SIMM12_20 00101xxx101110001xxxxxxxxxxxxxxx */
-{ "vmin2", 0x28b88000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vmin2", 0x28b88000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vmin2 RA,LIMM,RC 00101110001110001111xxxxxxxxxxxx */
-{ "vmin2", 0x2e38f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vmin2", 0x2e38f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vmin2 RA,RB,LIMM 00101xxx001110001xxx111110xxxxxx */
-{ "vmin2", 0x28388f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vmin2", 0x28388f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vmin2 ZA,LIMM,RC 00101110001110001111xxxxxx111110 */
-{ "vmin2", 0x2e38f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vmin2", 0x2e38f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vmin2 ZA,RB,LIMM 00101xxx001110001xxx111110111110 */
-{ "vmin2", 0x28388fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vmin2", 0x28388fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vmin2<.cc> ZA,LIMM,RC 00101110111110001111xxxxxx0xxxxx */
-{ "vmin2", 0x2ef8f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vmin2", 0x2ef8f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vmin2<.cc> RB,RBdup,LIMM 00101xxx111110001xxx1111100xxxxx */
-{ "vmin2", 0x28f88f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vmin2", 0x28f88f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vmin2 RA,LIMM,UIMM6_20 00101110011110001111xxxxxxxxxxxx */
-{ "vmin2", 0x2e78f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vmin2", 0x2e78f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vmin2 ZA,LIMM,UIMM6_20 00101110011110001111xxxxxx111110 */
-{ "vmin2", 0x2e78f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vmin2", 0x2e78f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vmin2<.cc> ZA,LIMM,UIMM6_20 00101110111110001111xxxxxx1xxxxx */
-{ "vmin2", 0x2ef8f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vmin2", 0x2ef8f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vmin2 ZA,LIMM,SIMM12_20 00101110101110001111xxxxxxxxxxxx */
-{ "vmin2", 0x2eb8f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vmin2", 0x2eb8f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vmin2 RA,LIMM,LIMMdup 00101110001110001111111110xxxxxx */
-{ "vmin2", 0x2e38ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vmin2", 0x2e38ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vmin2 ZA,LIMM,LIMMdup 00101110001110001111111110111110 */
-{ "vmin2", 0x2e38ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vmin2", 0x2e38ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vmin2<.cc> ZA,LIMM,LIMMdup 001011101111100011111111100xxxxx */
-{ "vmin2", 0x2ef8ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vmin2", 0x2ef8ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vmin2 RA,RB,RC 00100xxx000100010xxxxxxxxxxxxxxx */
-{ "vmin2", 0x20110000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vmin2", 0x20110000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vmin2 ZA,RB,RC 00100xxx000100010xxxxxxxxx111110 */
-{ "vmin2", 0x2011003e, 0xf8ff803f, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vmin2", 0x2011003e, 0xf8ff803f, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vmin2<.cc> RB,RBdup,RC 00100xxx110100010xxxxxxxxx0xxxxx */
-{ "vmin2", 0x20d10000, 0xf8ff8020, ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vmin2", 0x20d10000, 0xf8ff8020, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vmin2 RA,RB,UIMM6_20 00100xxx010100010xxxxxxxxxxxxxxx */
-{ "vmin2", 0x20510000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vmin2", 0x20510000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vmin2 ZA,RB,UIMM6_20 00100xxx010100010xxxxxxxxx111110 */
-{ "vmin2", 0x2051003e, 0xf8ff803f, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vmin2", 0x2051003e, 0xf8ff803f, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vmin2<.cc> RB,RBdup,UIMM6_20 00100xxx110100010xxxxxxxxx1xxxxx */
-{ "vmin2", 0x20d10020, 0xf8ff8020, ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vmin2", 0x20d10020, 0xf8ff8020, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vmin2 RB,RBdup,SIMM12_20 00100xxx100100010xxxxxxxxxxxxxxx */
-{ "vmin2", 0x20910000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vmin2", 0x20910000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vmin2 RA,LIMM,RC 00100110000100010111xxxxxxxxxxxx */
-{ "vmin2", 0x26117000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vmin2", 0x26117000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vmin2 RA,RB,LIMM 00100xxx000100010xxx111110xxxxxx */
-{ "vmin2", 0x20110f80, 0xf8ff8fc0, ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vmin2", 0x20110f80, 0xf8ff8fc0, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vmin2 ZA,LIMM,RC 00100110000100010111xxxxxx111110 */
-{ "vmin2", 0x2611703e, 0xfffff03f, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vmin2", 0x2611703e, 0xfffff03f, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vmin2 ZA,RB,LIMM 00100xxx000100010xxx111110111110 */
-{ "vmin2", 0x20110fbe, 0xf8ff8fff, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vmin2", 0x20110fbe, 0xf8ff8fff, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vmin2<.cc> ZA,LIMM,RC 00100110110100010111xxxxxx0xxxxx */
-{ "vmin2", 0x26d17000, 0xfffff020, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vmin2", 0x26d17000, 0xfffff020, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vmin2<.cc> RB,RBdup,LIMM 00100xxx110100010xxx1111100xxxxx */
-{ "vmin2", 0x20d10f80, 0xf8ff8fe0, ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vmin2", 0x20d10f80, 0xf8ff8fe0, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vmin2 RA,LIMM,UIMM6_20 00100110010100010111xxxxxxxxxxxx */
-{ "vmin2", 0x26517000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vmin2", 0x26517000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vmin2 ZA,LIMM,UIMM6_20 00100110010100010111xxxxxx111110 */
-{ "vmin2", 0x2651703e, 0xfffff03f, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vmin2", 0x2651703e, 0xfffff03f, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vmin2<.cc> ZA,LIMM,UIMM6_20 00100110110100010111xxxxxx1xxxxx */
-{ "vmin2", 0x26d17020, 0xfffff020, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vmin2", 0x26d17020, 0xfffff020, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vmin2 ZA,LIMM,SIMM12_20 00100110100100010111xxxxxxxxxxxx */
-{ "vmin2", 0x26917000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vmin2", 0x26917000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vmin2 RA,LIMM,LIMMdup 00100110000100010111111110xxxxxx */
-{ "vmin2", 0x26117f80, 0xffffffc0, ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vmin2", 0x26117f80, 0xffffffc0, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vmin2 ZA,LIMM,LIMMdup 00100110000100010111111110111110 */
-{ "vmin2", 0x26117fbe, 0xffffffff, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vmin2", 0x26117fbe, 0xffffffff, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vmin2<.cc> ZA,LIMM,LIMMdup 001001101101000101111111100xxxxx */
-{ "vmin2", 0x26d17f80, 0xffffffe0, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vmin2", 0x26d17f80, 0xffffffe0, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vmax2 RA,RB,RC 00101xxx001110011xxxxxxxxxxxxxxx */
-{ "vmax2", 0x28398000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vmax2", 0x28398000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vmax2 ZA,RB,RC 00101xxx001110011xxxxxxxxx111110 */
-{ "vmax2", 0x2839803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vmax2", 0x2839803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vmax2<.cc> RB,RBdup,RC 00101xxx111110011xxxxxxxxx0xxxxx */
-{ "vmax2", 0x28f98000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vmax2", 0x28f98000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vmax2 RA,RB,UIMM6_20 00101xxx011110011xxxxxxxxxxxxxxx */
-{ "vmax2", 0x28798000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vmax2", 0x28798000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vmax2 ZA,RB,UIMM6_20 00101xxx011110011xxxxxxxxx111110 */
-{ "vmax2", 0x2879803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vmax2", 0x2879803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vmax2<.cc> RB,RBdup,UIMM6_20 00101xxx111110011xxxxxxxxx1xxxxx */
-{ "vmax2", 0x28f98020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vmax2", 0x28f98020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vmax2 RB,RBdup,SIMM12_20 00101xxx101110011xxxxxxxxxxxxxxx */
-{ "vmax2", 0x28b98000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vmax2", 0x28b98000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vmax2 RA,LIMM,RC 00101110001110011111xxxxxxxxxxxx */
-{ "vmax2", 0x2e39f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vmax2", 0x2e39f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vmax2 RA,RB,LIMM 00101xxx001110011xxx111110xxxxxx */
-{ "vmax2", 0x28398f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vmax2", 0x28398f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vmax2 ZA,LIMM,RC 00101110001110011111xxxxxx111110 */
-{ "vmax2", 0x2e39f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vmax2", 0x2e39f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vmax2 ZA,RB,LIMM 00101xxx001110011xxx111110111110 */
-{ "vmax2", 0x28398fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vmax2", 0x28398fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vmax2<.cc> ZA,LIMM,RC 00101110111110011111xxxxxx0xxxxx */
-{ "vmax2", 0x2ef9f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vmax2", 0x2ef9f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vmax2<.cc> RB,RBdup,LIMM 00101xxx111110011xxx1111100xxxxx */
-{ "vmax2", 0x28f98f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vmax2", 0x28f98f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vmax2 RA,LIMM,UIMM6_20 00101110011110011111xxxxxxxxxxxx */
-{ "vmax2", 0x2e79f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vmax2", 0x2e79f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vmax2 ZA,LIMM,UIMM6_20 00101110011110011111xxxxxx111110 */
-{ "vmax2", 0x2e79f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vmax2", 0x2e79f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vmax2<.cc> ZA,LIMM,UIMM6_20 00101110111110011111xxxxxx1xxxxx */
-{ "vmax2", 0x2ef9f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vmax2", 0x2ef9f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vmax2 ZA,LIMM,SIMM12_20 00101110101110011111xxxxxxxxxxxx */
-{ "vmax2", 0x2eb9f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vmax2", 0x2eb9f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vmax2 RA,LIMM,LIMMdup 00101110001110011111111110xxxxxx */
-{ "vmax2", 0x2e39ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vmax2", 0x2e39ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vmax2 ZA,LIMM,LIMMdup 00101110001110011111111110111110 */
-{ "vmax2", 0x2e39ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vmax2", 0x2e39ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vmax2<.cc> ZA,LIMM,LIMMdup 001011101111100111111111100xxxxx */
-{ "vmax2", 0x2ef9ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vmax2", 0x2ef9ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vmax2 RA,RB,RC 00100xxx000010110xxxxxxxxxxxxxxx */
-{ "vmax2", 0x200b0000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vmax2", 0x200b0000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vmax2 ZA,RB,RC 00100xxx000010110xxxxxxxxx111110 */
-{ "vmax2", 0x200b003e, 0xf8ff803f, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vmax2", 0x200b003e, 0xf8ff803f, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vmax2<.cc> RB,RBdup,RC 00100xxx110010110xxxxxxxxx0xxxxx */
-{ "vmax2", 0x20cb0000, 0xf8ff8020, ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vmax2", 0x20cb0000, 0xf8ff8020, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vmax2 RA,RB,UIMM6_20 00100xxx010010110xxxxxxxxxxxxxxx */
-{ "vmax2", 0x204b0000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vmax2", 0x204b0000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vmax2 ZA,RB,UIMM6_20 00100xxx010010110xxxxxxxxx111110 */
-{ "vmax2", 0x204b003e, 0xf8ff803f, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vmax2", 0x204b003e, 0xf8ff803f, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vmax2<.cc> RB,RBdup,UIMM6_20 00100xxx110010110xxxxxxxxx1xxxxx */
-{ "vmax2", 0x20cb0020, 0xf8ff8020, ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vmax2", 0x20cb0020, 0xf8ff8020, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vmax2 RB,RBdup,SIMM12_20 00100xxx100010110xxxxxxxxxxxxxxx */
-{ "vmax2", 0x208b0000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vmax2", 0x208b0000, 0xf8ff8000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vmax2 RA,LIMM,RC 00100110000010110111xxxxxxxxxxxx */
-{ "vmax2", 0x260b7000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vmax2", 0x260b7000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vmax2 RA,RB,LIMM 00100xxx000010110xxx111110xxxxxx */
-{ "vmax2", 0x200b0f80, 0xf8ff8fc0, ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vmax2", 0x200b0f80, 0xf8ff8fc0, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vmax2 ZA,LIMM,RC 00100110000010110111xxxxxx111110 */
-{ "vmax2", 0x260b703e, 0xfffff03f, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vmax2", 0x260b703e, 0xfffff03f, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vmax2 ZA,RB,LIMM 00100xxx000010110xxx111110111110 */
-{ "vmax2", 0x200b0fbe, 0xf8ff8fff, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vmax2", 0x200b0fbe, 0xf8ff8fff, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vmax2<.cc> ZA,LIMM,RC 00100110110010110111xxxxxx0xxxxx */
-{ "vmax2", 0x26cb7000, 0xfffff020, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vmax2", 0x26cb7000, 0xfffff020, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vmax2<.cc> RB,RBdup,LIMM 00100xxx110010110xxx1111100xxxxx */
-{ "vmax2", 0x20cb0f80, 0xf8ff8fe0, ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vmax2", 0x20cb0f80, 0xf8ff8fe0, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vmax2 RA,LIMM,UIMM6_20 00100110010010110111xxxxxxxxxxxx */
-{ "vmax2", 0x264b7000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vmax2", 0x264b7000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vmax2 ZA,LIMM,UIMM6_20 00100110010010110111xxxxxx111110 */
-{ "vmax2", 0x264b703e, 0xfffff03f, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vmax2", 0x264b703e, 0xfffff03f, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vmax2<.cc> ZA,LIMM,UIMM6_20 00100110110010110111xxxxxx1xxxxx */
-{ "vmax2", 0x26cb7020, 0xfffff020, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vmax2", 0x26cb7020, 0xfffff020, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vmax2 ZA,LIMM,SIMM12_20 00100110100010110111xxxxxxxxxxxx */
-{ "vmax2", 0x268b7000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vmax2", 0x268b7000, 0xfffff000, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vmax2 RA,LIMM,LIMMdup 00100110000010110111111110xxxxxx */
-{ "vmax2", 0x260b7f80, 0xffffffc0, ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vmax2", 0x260b7f80, 0xffffffc0, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vmax2 ZA,LIMM,LIMMdup 00100110000010110111111110111110 */
-{ "vmax2", 0x260b7fbe, 0xffffffff, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vmax2", 0x260b7fbe, 0xffffffff, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vmax2<.cc> ZA,LIMM,LIMMdup 001001101100101101111111100xxxxx */
-{ "vmax2", 0x26cb7f80, 0xffffffe0, ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vmax2", 0x26cb7f80, 0xffffffe0, ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vpack4hl RA,RB,RC 01011xxx001100001xxxxxxxxxxxxxxx */
-{ "vpack4hl", 0x58308000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vpack4hl", 0x58308000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vpack4hl ZA,RB,RC 01011xxx001100001xxxxxxxxx111110 */
-{ "vpack4hl", 0x5830803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vpack4hl", 0x5830803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vpack4hl<.cc> RB,RBdup,RC 01011xxx111100001xxxxxxxxx0xxxxx */
-{ "vpack4hl", 0x58f08000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vpack4hl", 0x58f08000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vpack4hl RA,RB,UIMM6_20 01011xxx011100001xxxxxxxxxxxxxxx */
-{ "vpack4hl", 0x58708000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vpack4hl", 0x58708000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack4hl ZA,RB,UIMM6_20 01011xxx011100001xxxxxxxxx111110 */
-{ "vpack4hl", 0x5870803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vpack4hl", 0x5870803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack4hl<.cc> RB,RBdup,UIMM6_20 01011xxx111100001xxxxxxxxx1xxxxx */
-{ "vpack4hl", 0x58f08020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vpack4hl", 0x58f08020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vpack4hl RB,RBdup,SIMM12_20 01011xxx101100001xxxxxxxxxxxxxxx */
-{ "vpack4hl", 0x58b08000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vpack4hl", 0x58b08000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vpack4hl RA,LIMM,RC 01011110001100001111xxxxxxxxxxxx */
-{ "vpack4hl", 0x5e30f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vpack4hl", 0x5e30f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vpack4hl RA,RB,LIMM 01011xxx001100001xxx111110xxxxxx */
-{ "vpack4hl", 0x58308f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vpack4hl", 0x58308f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vpack4hl ZA,LIMM,RC 01011110001100001111xxxxxx111110 */
-{ "vpack4hl", 0x5e30f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vpack4hl", 0x5e30f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vpack4hl ZA,RB,LIMM 01011xxx001100001xxx111110111110 */
-{ "vpack4hl", 0x58308fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vpack4hl", 0x58308fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vpack4hl<.cc> ZA,LIMM,RC 01011110111100001111xxxxxx0xxxxx */
-{ "vpack4hl", 0x5ef0f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vpack4hl", 0x5ef0f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vpack4hl<.cc> RB,RBdup,LIMM 01011xxx111100001xxx1111100xxxxx */
-{ "vpack4hl", 0x58f08f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vpack4hl", 0x58f08f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vpack4hl RA,LIMM,UIMM6_20 01011110011100001111xxxxxxxxxxxx */
-{ "vpack4hl", 0x5e70f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack4hl", 0x5e70f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack4hl ZA,LIMM,UIMM6_20 01011110011100001111xxxxxx111110 */
-{ "vpack4hl", 0x5e70f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack4hl", 0x5e70f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack4hl<.cc> ZA,LIMM,UIMM6_20 01011110111100001111xxxxxx1xxxxx */
-{ "vpack4hl", 0x5ef0f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vpack4hl", 0x5ef0f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vpack4hl ZA,LIMM,SIMM12_20 01011110101100001111xxxxxxxxxxxx */
-{ "vpack4hl", 0x5eb0f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vpack4hl", 0x5eb0f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vpack4hl RA,LIMM,LIMMdup 01011110001100001111111110xxxxxx */
-{ "vpack4hl", 0x5e30ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vpack4hl", 0x5e30ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack4hl ZA,LIMM,LIMMdup 01011110001100001111111110111110 */
-{ "vpack4hl", 0x5e30ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vpack4hl", 0x5e30ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack4hl<.cc> ZA,LIMM,LIMMdup 010111101111000011111111100xxxxx */
-{ "vpack4hl", 0x5ef0ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vpack4hl", 0x5ef0ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vpack4hm RA,RB,RC 01011xxx001100011xxxxxxxxxxxxxxx */
-{ "vpack4hm", 0x58318000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vpack4hm", 0x58318000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vpack4hm ZA,RB,RC 01011xxx001100011xxxxxxxxx111110 */
-{ "vpack4hm", 0x5831803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vpack4hm", 0x5831803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vpack4hm<.cc> RB,RBdup,RC 01011xxx111100011xxxxxxxxx0xxxxx */
-{ "vpack4hm", 0x58f18000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vpack4hm", 0x58f18000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vpack4hm RA,RB,UIMM6_20 01011xxx011100011xxxxxxxxxxxxxxx */
-{ "vpack4hm", 0x58718000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vpack4hm", 0x58718000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack4hm ZA,RB,UIMM6_20 01011xxx011100011xxxxxxxxx111110 */
-{ "vpack4hm", 0x5871803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vpack4hm", 0x5871803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack4hm<.cc> RB,RBdup,UIMM6_20 01011xxx111100011xxxxxxxxx1xxxxx */
-{ "vpack4hm", 0x58f18020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vpack4hm", 0x58f18020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vpack4hm RB,RBdup,SIMM12_20 01011xxx101100011xxxxxxxxxxxxxxx */
-{ "vpack4hm", 0x58b18000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vpack4hm", 0x58b18000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vpack4hm RA,LIMM,RC 01011110001100011111xxxxxxxxxxxx */
-{ "vpack4hm", 0x5e31f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vpack4hm", 0x5e31f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vpack4hm RA,RB,LIMM 01011xxx001100011xxx111110xxxxxx */
-{ "vpack4hm", 0x58318f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vpack4hm", 0x58318f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vpack4hm ZA,LIMM,RC 01011110001100011111xxxxxx111110 */
-{ "vpack4hm", 0x5e31f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vpack4hm", 0x5e31f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vpack4hm ZA,RB,LIMM 01011xxx001100011xxx111110111110 */
-{ "vpack4hm", 0x58318fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vpack4hm", 0x58318fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vpack4hm<.cc> ZA,LIMM,RC 01011110111100011111xxxxxx0xxxxx */
-{ "vpack4hm", 0x5ef1f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vpack4hm", 0x5ef1f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vpack4hm<.cc> RB,RBdup,LIMM 01011xxx111100011xxx1111100xxxxx */
-{ "vpack4hm", 0x58f18f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vpack4hm", 0x58f18f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vpack4hm RA,LIMM,UIMM6_20 01011110011100011111xxxxxxxxxxxx */
-{ "vpack4hm", 0x5e71f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack4hm", 0x5e71f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack4hm ZA,LIMM,UIMM6_20 01011110011100011111xxxxxx111110 */
-{ "vpack4hm", 0x5e71f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack4hm", 0x5e71f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack4hm<.cc> ZA,LIMM,UIMM6_20 01011110111100011111xxxxxx1xxxxx */
-{ "vpack4hm", 0x5ef1f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vpack4hm", 0x5ef1f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vpack4hm ZA,LIMM,SIMM12_20 01011110101100011111xxxxxxxxxxxx */
-{ "vpack4hm", 0x5eb1f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vpack4hm", 0x5eb1f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vpack4hm RA,LIMM,LIMMdup 01011110001100011111111110xxxxxx */
-{ "vpack4hm", 0x5e31ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vpack4hm", 0x5e31ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack4hm ZA,LIMM,LIMMdup 01011110001100011111111110111110 */
-{ "vpack4hm", 0x5e31ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vpack4hm", 0x5e31ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack4hm<.cc> ZA,LIMM,LIMMdup 010111101111000111111111100xxxxx */
-{ "vpack4hm", 0x5ef1ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vpack4hm", 0x5ef1ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vpack2wl RA,RB,RC 01011xxx001100101xxxxxxxxxxxxxxx */
-{ "vpack2wl", 0x58328000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vpack2wl", 0x58328000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vpack2wl ZA,RB,RC 01011xxx001100101xxxxxxxxx111110 */
-{ "vpack2wl", 0x5832803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vpack2wl", 0x5832803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vpack2wl<.cc> RB,RBdup,RC 01011xxx111100101xxxxxxxxx0xxxxx */
-{ "vpack2wl", 0x58f28000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vpack2wl", 0x58f28000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vpack2wl RA,RB,UIMM6_20 01011xxx011100101xxxxxxxxxxxxxxx */
-{ "vpack2wl", 0x58728000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vpack2wl", 0x58728000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack2wl ZA,RB,UIMM6_20 01011xxx011100101xxxxxxxxx111110 */
-{ "vpack2wl", 0x5872803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vpack2wl", 0x5872803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack2wl<.cc> RB,RBdup,UIMM6_20 01011xxx111100101xxxxxxxxx1xxxxx */
-{ "vpack2wl", 0x58f28020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vpack2wl", 0x58f28020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vpack2wl RB,RBdup,SIMM12_20 01011xxx101100101xxxxxxxxxxxxxxx */
-{ "vpack2wl", 0x58b28000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vpack2wl", 0x58b28000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vpack2wl RA,LIMM,RC 01011110001100101111xxxxxxxxxxxx */
-{ "vpack2wl", 0x5e32f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vpack2wl", 0x5e32f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vpack2wl RA,RB,LIMM 01011xxx001100101xxx111110xxxxxx */
-{ "vpack2wl", 0x58328f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vpack2wl", 0x58328f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vpack2wl ZA,LIMM,RC 01011110001100101111xxxxxx111110 */
-{ "vpack2wl", 0x5e32f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vpack2wl", 0x5e32f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vpack2wl ZA,RB,LIMM 01011xxx001100101xxx111110111110 */
-{ "vpack2wl", 0x58328fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vpack2wl", 0x58328fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vpack2wl<.cc> ZA,LIMM,RC 01011110111100101111xxxxxx0xxxxx */
-{ "vpack2wl", 0x5ef2f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vpack2wl", 0x5ef2f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vpack2wl<.cc> RB,RBdup,LIMM 01011xxx111100101xxx1111100xxxxx */
-{ "vpack2wl", 0x58f28f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vpack2wl", 0x58f28f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vpack2wl RA,LIMM,UIMM6_20 01011110011100101111xxxxxxxxxxxx */
-{ "vpack2wl", 0x5e72f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack2wl", 0x5e72f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2wl ZA,LIMM,UIMM6_20 01011110011100101111xxxxxx111110 */
-{ "vpack2wl", 0x5e72f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack2wl", 0x5e72f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2wl<.cc> ZA,LIMM,UIMM6_20 01011110111100101111xxxxxx1xxxxx */
-{ "vpack2wl", 0x5ef2f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vpack2wl", 0x5ef2f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vpack2wl ZA,LIMM,SIMM12_20 01011110101100101111xxxxxxxxxxxx */
-{ "vpack2wl", 0x5eb2f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vpack2wl", 0x5eb2f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vpack2wl RA,LIMM,LIMMdup 01011110001100101111111110xxxxxx */
-{ "vpack2wl", 0x5e32ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vpack2wl", 0x5e32ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack2wl ZA,LIMM,LIMMdup 01011110001100101111111110111110 */
-{ "vpack2wl", 0x5e32ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vpack2wl", 0x5e32ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack2wl<.cc> ZA,LIMM,LIMMdup 010111101111001011111111100xxxxx */
-{ "vpack2wl", 0x5ef2ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vpack2wl", 0x5ef2ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vpack2wm RA,RB,RC 01011xxx001100111xxxxxxxxxxxxxxx */
-{ "vpack2wm", 0x58338000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vpack2wm", 0x58338000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vpack2wm ZA,RB,RC 01011xxx001100111xxxxxxxxx111110 */
-{ "vpack2wm", 0x5833803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vpack2wm", 0x5833803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vpack2wm<.cc> RB,RBdup,RC 01011xxx111100111xxxxxxxxx0xxxxx */
-{ "vpack2wm", 0x58f38000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vpack2wm", 0x58f38000, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vpack2wm RA,RB,UIMM6_20 01011xxx011100111xxxxxxxxxxxxxxx */
-{ "vpack2wm", 0x58738000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vpack2wm", 0x58738000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack2wm ZA,RB,UIMM6_20 01011xxx011100111xxxxxxxxx111110 */
-{ "vpack2wm", 0x5873803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vpack2wm", 0x5873803e, 0xf8ff803f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack2wm<.cc> RB,RBdup,UIMM6_20 01011xxx111100111xxxxxxxxx1xxxxx */
-{ "vpack2wm", 0x58f38020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vpack2wm", 0x58f38020, 0xf8ff8020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vpack2wm RB,RBdup,SIMM12_20 01011xxx101100111xxxxxxxxxxxxxxx */
-{ "vpack2wm", 0x58b38000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vpack2wm", 0x58b38000, 0xf8ff8000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vpack2wm RA,LIMM,RC 01011110001100111111xxxxxxxxxxxx */
-{ "vpack2wm", 0x5e33f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vpack2wm", 0x5e33f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vpack2wm RA,RB,LIMM 01011xxx001100111xxx111110xxxxxx */
-{ "vpack2wm", 0x58338f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vpack2wm", 0x58338f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vpack2wm ZA,LIMM,RC 01011110001100111111xxxxxx111110 */
-{ "vpack2wm", 0x5e33f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vpack2wm", 0x5e33f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vpack2wm ZA,RB,LIMM 01011xxx001100111xxx111110111110 */
-{ "vpack2wm", 0x58338fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vpack2wm", 0x58338fbe, 0xf8ff8fff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vpack2wm<.cc> ZA,LIMM,RC 01011110111100111111xxxxxx0xxxxx */
-{ "vpack2wm", 0x5ef3f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vpack2wm", 0x5ef3f000, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vpack2wm<.cc> RB,RBdup,LIMM 01011xxx111100111xxx1111100xxxxx */
-{ "vpack2wm", 0x58f38f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vpack2wm", 0x58f38f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vpack2wm RA,LIMM,UIMM6_20 01011110011100111111xxxxxxxxxxxx */
-{ "vpack2wm", 0x5e73f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack2wm", 0x5e73f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2wm ZA,LIMM,UIMM6_20 01011110011100111111xxxxxx111110 */
-{ "vpack2wm", 0x5e73f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack2wm", 0x5e73f03e, 0xfffff03f, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2wm<.cc> ZA,LIMM,UIMM6_20 01011110111100111111xxxxxx1xxxxx */
-{ "vpack2wm", 0x5ef3f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vpack2wm", 0x5ef3f020, 0xfffff020, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vpack2wm ZA,LIMM,SIMM12_20 01011110101100111111xxxxxxxxxxxx */
-{ "vpack2wm", 0x5eb3f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vpack2wm", 0x5eb3f000, 0xfffff000, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vpack2wm RA,LIMM,LIMMdup 01011110001100111111111110xxxxxx */
-{ "vpack2wm", 0x5e33ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vpack2wm", 0x5e33ff80, 0xffffffc0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack2wm ZA,LIMM,LIMMdup 01011110001100111111111110111110 */
-{ "vpack2wm", 0x5e33ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vpack2wm", 0x5e33ffbe, 0xffffffff, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack2wm<.cc> ZA,LIMM,LIMMdup 010111101111001111111111100xxxxx */
-{ "vpack2wm", 0x5ef3ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vpack2wm", 0x5ef3ff80, 0xffffffe0, ARC_OPCODE_ARC64, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* vpack2hm RA,RB,RC 00101xxx001010011xxxxxxxxxxxxxxx */
-{ "vpack2hm", 0x28298000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vpack2hm", 0x28298000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vpack2hm ZA,RB,RC 00101xxx001010011xxxxxxxxx111110 */
-{ "vpack2hm", 0x2829803e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vpack2hm", 0x2829803e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vpack2hm<.cc> RB,RBdup,RC 00101xxx111010011xxxxxxxxx0xxxxx */
-{ "vpack2hm", 0x28e98000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vpack2hm", 0x28e98000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vpack2hm RA,RB,UIMM6_20 00101xxx011010011xxxxxxxxxxxxxxx */
-{ "vpack2hm", 0x28698000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vpack2hm", 0x28698000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack2hm ZA,RB,UIMM6_20 00101xxx011010011xxxxxxxxx111110 */
-{ "vpack2hm", 0x2869803e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vpack2hm", 0x2869803e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack2hm<.cc> RB,RBdup,UIMM6_20 00101xxx111010011xxxxxxxxx1xxxxx */
-{ "vpack2hm", 0x28e98020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vpack2hm", 0x28e98020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vpack2hm RB,RBdup,SIMM12_20 00101xxx101010011xxxxxxxxxxxxxxx */
-{ "vpack2hm", 0x28a98000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vpack2hm", 0x28a98000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vpack2hm RA,LIMM,RC 00101110001010011111xxxxxxxxxxxx */
-{ "vpack2hm", 0x2e29f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vpack2hm", 0x2e29f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vpack2hm RA,RB,LIMM 00101xxx001010011xxx111110xxxxxx */
-{ "vpack2hm", 0x28298f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vpack2hm", 0x28298f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vpack2hm ZA,LIMM,RC 00101110001010011111xxxxxx111110 */
-{ "vpack2hm", 0x2e29f03e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vpack2hm", 0x2e29f03e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vpack2hm ZA,RB,LIMM 00101xxx001010011xxx111110111110 */
-{ "vpack2hm", 0x28298fbe, 0xf8ff8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vpack2hm", 0x28298fbe, 0xf8ff8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vpack2hm<.cc> ZA,LIMM,RC 00101110111010011111xxxxxx0xxxxx */
-{ "vpack2hm", 0x2ee9f000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vpack2hm", 0x2ee9f000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vpack2hm<.cc> RB,RBdup,LIMM 00101xxx111010011xxx1111100xxxxx */
-{ "vpack2hm", 0x28e98f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vpack2hm", 0x28e98f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vpack2hm RA,LIMM,UIMM6_20 00101110011010011111xxxxxxxxxxxx */
-{ "vpack2hm", 0x2e69f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack2hm", 0x2e69f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2hm ZA,LIMM,UIMM6_20 00101110011010011111xxxxxx111110 */
-{ "vpack2hm", 0x2e69f03e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack2hm", 0x2e69f03e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2hm<.cc> ZA,LIMM,UIMM6_20 00101110111010011111xxxxxx1xxxxx */
-{ "vpack2hm", 0x2ee9f020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vpack2hm", 0x2ee9f020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vpack2hm ZA,LIMM,SIMM12_20 00101110101010011111xxxxxxxxxxxx */
-{ "vpack2hm", 0x2ea9f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vpack2hm", 0x2ea9f000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vpack2hm RA,LIMM,LIMMdup 00101110001010011111111110xxxxxx */
-{ "vpack2hm", 0x2e29ff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vpack2hm", 0x2e29ff80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack2hm ZA,LIMM,LIMMdup 00101110001010011111111110111110 */
-{ "vpack2hm", 0x2e29ffbe, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vpack2hm", 0x2e29ffbe, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack2hm<.cc> ZA,LIMM,LIMMdup 001011101110100111111111100xxxxx */
-{ "vpack2hm", 0x2ee9ff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vpack2hm", 0x2ee9ff80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
 /* mpyl RA,RB,RC 01011xxx001100000xxxxxxxxxxxxxxx */
-{ "mpyl", 0x58300000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 } }
+{ "mpyl", 0x58300000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* mpyl ZA,RB,RC 01011xxx001100000xxxxxxxxx111110 */
-{ "mpyl", 0x5830003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 } }
+{ "mpyl", 0x5830003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* mpyl<.cc> RB,RBdup,RC 01011xxx111100000xxxxxxxxx0xxxxx */
-{ "mpyl", 0x58f00000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "mpyl", 0x58f00000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* mpyl RA,RB,UIMM6_20 01011xxx011100000xxxxxxxxxxxxxxx */
-{ "mpyl", 0x58700000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "mpyl", 0x58700000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* mpyl ZA,RB,UIMM6_20 01011xxx011100000xxxxxxxxx111110 */
-{ "mpyl", 0x5870003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "mpyl", 0x5870003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* mpyl<.cc> RB,RBdup,UIMM6_20 01011xxx111100000xxxxxxxxx1xxxxx */
-{ "mpyl", 0x58f00020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "mpyl", 0x58f00020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* mpyl RB,RBdup,SIMM12_20 01011xxx101100000xxxxxxxxxxxxxxx */
-{ "mpyl", 0x58b00000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "mpyl", 0x58b00000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* mpyl RA,XIMM,RC 01011100001100000111xxxxxxxxxxxx */
-{ "mpyl", 0x5c307000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { 0 } }
+{ "mpyl", 0x5c307000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { 0 } }
 
 /* mpyl RA,RB,XIMM 01011xxx001100000xxx111100xxxxxx */
-{ "mpyl", 0x58300f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { 0 } }
+{ "mpyl", 0x58300f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { 0 } }
 
 /* mpyl<.cc> RB,RBdup,XIMM 01011xxx111100000xxx1111000xxxxx */
-{ "mpyl", 0x58f00f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_CC } }
+{ "mpyl", 0x58f00f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_CC } }
 
 /* mpyl RA,XIMM,UIMM6_20 01011100011100000111xxxxxxxxxxxx */
-{ "mpyl", 0x5c707000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { 0 } }
+{ "mpyl", 0x5c707000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { 0 } }
 
 /* mpyl RA,LIMM,RC 01011110001100000111xxxxxxxxxxxx */
-{ "mpyl", 0x5e307000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { 0 } }
+{ "mpyl", 0x5e307000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* mpyl RA,RB,LIMM 01011xxx001100000xxx111110xxxxxx */
-{ "mpyl", 0x58300f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { 0 } }
+{ "mpyl", 0x58300f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* mpyl<.cc> RB,RBdup,LIMM 01011xxx111100000xxx1111100xxxxx */
-{ "mpyl", 0x58f00f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "mpyl", 0x58f00f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* mpyl RA,LIMM,UIMM6_20 01011110011100000111xxxxxxxxxxxx */
-{ "mpyl", 0x5e707000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "mpyl", 0x5e707000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* mpyml RA,RB,RC 01011xxx001100010xxxxxxxxxxxxxxx */
-{ "mpyml", 0x58310000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 } }
+{ "mpyml", 0x58310000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* mpyml ZA,RB,RC 01011xxx001100010xxxxxxxxx111110 */
-{ "mpyml", 0x5831003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 } }
+{ "mpyml", 0x5831003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* mpyml<.cc> RB,RBdup,RC 01011xxx111100010xxxxxxxxx0xxxxx */
-{ "mpyml", 0x58f10000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "mpyml", 0x58f10000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* mpyml RA,RB,UIMM6_20 01011xxx011100010xxxxxxxxxxxxxxx */
-{ "mpyml", 0x58710000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "mpyml", 0x58710000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* mpyml ZA,RB,UIMM6_20 01011xxx011100010xxxxxxxxx111110 */
-{ "mpyml", 0x5871003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "mpyml", 0x5871003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* mpyml<.cc> RB,RBdup,UIMM6_20 01011xxx111100010xxxxxxxxx1xxxxx */
-{ "mpyml", 0x58f10020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "mpyml", 0x58f10020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* mpyml RB,RBdup,SIMM12_20 01011xxx101100010xxxxxxxxxxxxxxx */
-{ "mpyml", 0x58b10000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "mpyml", 0x58b10000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* mpyml RA,XIMM,RC 01011100001100010111xxxxxxxxxxxx */
-{ "mpyml", 0x5c317000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { 0 } }
+{ "mpyml", 0x5c317000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { 0 } }
 
 /* mpyml RA,RB,XIMM 01011xxx001100010xxx111100xxxxxx */
-{ "mpyml", 0x58310f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { 0 } }
+{ "mpyml", 0x58310f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { 0 } }
 
 /* mpyml<.cc> RB,RBdup,XIMM 01011xxx111100010xxx1111000xxxxx */
-{ "mpyml", 0x58f10f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_CC } }
+{ "mpyml", 0x58f10f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_CC } }
 
 /* mpyml RA,XIMM,UIMM6_20 01011100011100010111xxxxxxxxxxxx */
-{ "mpyml", 0x5c717000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { 0 } }
+{ "mpyml", 0x5c717000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { 0 } }
 
 /* mpyml RA,LIMM,RC 01011110001100010111xxxxxxxxxxxx */
-{ "mpyml", 0x5e317000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { 0 } }
+{ "mpyml", 0x5e317000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* mpyml RA,RB,LIMM 01011xxx001100010xxx111110xxxxxx */
-{ "mpyml", 0x58310f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { 0 } }
+{ "mpyml", 0x58310f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* mpyml<.cc> RB,RBdup,LIMM 01011xxx111100010xxx1111100xxxxx */
-{ "mpyml", 0x58f10f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "mpyml", 0x58f10f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* mpyml RA,LIMM,UIMM6_20 01011110011100010111xxxxxxxxxxxx */
-{ "mpyml", 0x5e717000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "mpyml", 0x5e717000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* mpymul RA,RB,RC 01011xxx001100100xxxxxxxxxxxxxxx */
-{ "mpymul", 0x58320000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 } }
+{ "mpymul", 0x58320000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* mpymul ZA,RB,RC 01011xxx001100100xxxxxxxxx111110 */
-{ "mpymul", 0x5832003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 } }
+{ "mpymul", 0x5832003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* mpymul<.cc> RB,RBdup,RC 01011xxx111100100xxxxxxxxx0xxxxx */
-{ "mpymul", 0x58f20000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "mpymul", 0x58f20000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* mpymul RA,RB,UIMM6_20 01011xxx011100100xxxxxxxxxxxxxxx */
-{ "mpymul", 0x58720000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "mpymul", 0x58720000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* mpymul ZA,RB,UIMM6_20 01011xxx011100100xxxxxxxxx111110 */
-{ "mpymul", 0x5872003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "mpymul", 0x5872003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* mpymul<.cc> RB,RBdup,UIMM6_20 01011xxx111100100xxxxxxxxx1xxxxx */
-{ "mpymul", 0x58f20020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "mpymul", 0x58f20020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* mpymul RB,RBdup,SIMM12_20 01011xxx101100100xxxxxxxxxxxxxxx */
-{ "mpymul", 0x58b20000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "mpymul", 0x58b20000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* mpymul RA,XIMM,RC 01011100001100100111xxxxxxxxxxxx */
-{ "mpymul", 0x5c327000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { 0 } }
+{ "mpymul", 0x5c327000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { 0 } }
 
 /* mpymul RA,RB,XIMM 01011xxx001100100xxx111100xxxxxx */
-{ "mpymul", 0x58320f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { 0 } }
+{ "mpymul", 0x58320f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { 0 } }
 
 /* mpymul<.cc> RB,RBdup,XIMM 01011xxx111100100xxx1111000xxxxx */
-{ "mpymul", 0x58f20f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_CC } }
+{ "mpymul", 0x58f20f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_CC } }
 
 /* mpymul RA,XIMM,UIMM6_20 01011100011100100111xxxxxxxxxxxx */
-{ "mpymul", 0x5c727000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { 0 } }
+{ "mpymul", 0x5c727000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { 0 } }
 
 /* mpymul RA,LIMM,RC 01011110001100100111xxxxxxxxxxxx */
-{ "mpymul", 0x5e327000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { 0 } }
+{ "mpymul", 0x5e327000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* mpymul RA,RB,LIMM 01011xxx001100100xxx111110xxxxxx */
-{ "mpymul", 0x58320f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { 0 } }
+{ "mpymul", 0x58320f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* mpymul<.cc> RB,RBdup,LIMM 01011xxx111100100xxx1111100xxxxx */
-{ "mpymul", 0x58f20f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "mpymul", 0x58f20f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* mpymul RA,LIMM,UIMM6_20 01011110011100100111xxxxxxxxxxxx */
-{ "mpymul", 0x5e727000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "mpymul", 0x5e727000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* mpymsul RA,RB,RC 01011xxx001100110xxxxxxxxxxxxxxx */
-{ "mpymsul", 0x58330000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 } }
+{ "mpymsul", 0x58330000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* mpymsul ZA,RB,RC 01011xxx001100110xxxxxxxxx111110 */
-{ "mpymsul", 0x5833003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 } }
+{ "mpymsul", 0x5833003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* mpymsul<.cc> RB,RBdup,RC 01011xxx111100110xxxxxxxxx0xxxxx */
-{ "mpymsul", 0x58f30000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "mpymsul", 0x58f30000, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* mpymsul RA,RB,UIMM6_20 01011xxx011100110xxxxxxxxxxxxxxx */
-{ "mpymsul", 0x58730000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "mpymsul", 0x58730000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* mpymsul ZA,RB,UIMM6_20 01011xxx011100110xxxxxxxxx111110 */
-{ "mpymsul", 0x5873003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "mpymsul", 0x5873003e, 0xf8ff803f, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* mpymsul<.cc> RB,RBdup,UIMM6_20 01011xxx111100110xxxxxxxxx1xxxxx */
-{ "mpymsul", 0x58f30020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "mpymsul", 0x58f30020, 0xf8ff8020, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* mpymsul RB,RBdup,SIMM12_20 01011xxx101100110xxxxxxxxxxxxxxx */
-{ "mpymsul", 0x58b30000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "mpymsul", 0x58b30000, 0xf8ff8000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* mpymsul RA,XIMM,RC 01011100001100110111xxxxxxxxxxxx */
-{ "mpymsul", 0x5c337000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { 0 } }
+{ "mpymsul", 0x5c337000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, RC }, { 0 } }
 
 /* mpymsul RA,RB,XIMM 01011xxx001100110xxx111100xxxxxx */
-{ "mpymsul", 0x58330f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { 0 } }
+{ "mpymsul", 0x58330f00, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, XIMM }, { 0 } }
 
 /* mpymsul<.cc> RB,RBdup,XIMM 01011xxx111100110xxx1111000xxxxx */
-{ "mpymsul", 0x58f30f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_CC } }
+{ "mpymsul", 0x58f30f00, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, XIMM }, { C_CC } }
 
 /* mpymsul RA,XIMM,UIMM6_20 01011100011100110111xxxxxxxxxxxx */
-{ "mpymsul", 0x5c737000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { 0 } }
+{ "mpymsul", 0x5c737000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, XIMM, UIMM6_20 }, { 0 } }
 
 /* mpymsul RA,LIMM,RC 01011110001100110111xxxxxxxxxxxx */
-{ "mpymsul", 0x5e337000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { 0 } }
+{ "mpymsul", 0x5e337000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* mpymsul RA,RB,LIMM 01011xxx001100110xxx111110xxxxxx */
-{ "mpymsul", 0x58330f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { 0 } }
+{ "mpymsul", 0x58330f80, 0xf8ff8fc0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* mpymsul<.cc> RB,RBdup,LIMM 01011xxx111100110xxx1111100xxxxx */
-{ "mpymsul", 0x58f30f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "mpymsul", 0x58f30f80, 0xf8ff8fe0, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* mpymsul RA,LIMM,UIMM6_20 01011110011100110111xxxxxxxxxxxx */
-{ "mpymsul", 0x5e737000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "mpymsul", 0x5e737000, 0xfffff000, ARC_OPCODE_ARC64, ARITH, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2hl RA,RB,RC 00101xxx001010010xxxxxxxxxxxxxxx */
-{ "vpack2hl", 0x28290000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, RC }, { 0 } }
+{ "vpack2hl", 0x28290000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, RC }, { 0 } }
 
 /* vpack2hl ZA,RB,RC 00101xxx001010010xxxxxxxxx111110 */
-{ "vpack2hl", 0x2829003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, RC }, { 0 } }
+{ "vpack2hl", 0x2829003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, RC }, { 0 } }
 
 /* vpack2hl<.cc> RB,RBdup,RC 00101xxx111010010xxxxxxxxx0xxxxx */
-{ "vpack2hl", 0x28e90000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, RC }, { C_CC } }
+{ "vpack2hl", 0x28e90000, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, RC }, { C_CC } }
 
 /* vpack2hl RA,RB,UIMM6_20 00101xxx011010010xxxxxxxxxxxxxxx */
-{ "vpack2hl", 0x28690000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, UIMM6_20 }, { 0 } }
+{ "vpack2hl", 0x28690000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack2hl ZA,RB,UIMM6_20 00101xxx011010010xxxxxxxxx111110 */
-{ "vpack2hl", 0x2869003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 } }
+{ "vpack2hl", 0x2869003e, 0xf8ff803f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, UIMM6_20 }, { 0 } }
 
 /* vpack2hl<.cc> RB,RBdup,UIMM6_20 00101xxx111010010xxxxxxxxx1xxxxx */
-{ "vpack2hl", 0x28e90020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
+{ "vpack2hl", 0x28e90020, 0xf8ff8020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, UIMM6_20 }, { C_CC } }
 
 /* vpack2hl RB,RBdup,SIMM12_20 00101xxx101010010xxxxxxxxxxxxxxx */
-{ "vpack2hl", 0x28a90000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
+{ "vpack2hl", 0x28a90000, 0xf8ff8000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, SIMM12_20 }, { 0 } }
 
 /* vpack2hl RA,LIMM,RC 00101110001010010111xxxxxxxxxxxx */
-{ "vpack2hl", 0x2e297000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, RC }, { 0 } }
+{ "vpack2hl", 0x2e297000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, RC }, { 0 } }
 
 /* vpack2hl RA,RB,LIMM 00101xxx001010010xxx111110xxxxxx */
-{ "vpack2hl", 0x28290f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, RB, LIMM }, { 0 } }
+{ "vpack2hl", 0x28290f80, 0xf8ff8fc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, RB, LIMM }, { 0 } }
 
 /* vpack2hl ZA,LIMM,RC 00101110001010010111xxxxxx111110 */
-{ "vpack2hl", 0x2e29703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, RC }, { 0 } }
+{ "vpack2hl", 0x2e29703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { 0 } }
 
 /* vpack2hl ZA,RB,LIMM 00101xxx001010010xxx111110111110 */
-{ "vpack2hl", 0x28290fbe, 0xf8ff8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, RB, LIMM }, { 0 } }
+{ "vpack2hl", 0x28290fbe, 0xf8ff8fff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, RB, LIMM }, { 0 } }
 
 /* vpack2hl<.cc> ZA,LIMM,RC 00101110111010010111xxxxxx0xxxxx */
-{ "vpack2hl", 0x2ee97000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, RC }, { C_CC } }
+{ "vpack2hl", 0x2ee97000, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, RC }, { C_CC } }
 
 /* vpack2hl<.cc> RB,RBdup,LIMM 00101xxx111010010xxx1111100xxxxx */
-{ "vpack2hl", 0x28e90f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RB, RBdup, LIMM }, { C_CC } }
+{ "vpack2hl", 0x28e90f80, 0xf8ff8fe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RB, RBdup, LIMM }, { C_CC } }
 
 /* vpack2hl RA,LIMM,UIMM6_20 00101110011010010111xxxxxxxxxxxx */
-{ "vpack2hl", 0x2e697000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack2hl", 0x2e697000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2hl ZA,LIMM,UIMM6_20 00101110011010010111xxxxxx111110 */
-{ "vpack2hl", 0x2e69703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
+{ "vpack2hl", 0x2e69703e, 0xfffff03f, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { 0 } }
 
 /* vpack2hl<.cc> ZA,LIMM,UIMM6_20 00101110111010010111xxxxxx1xxxxx */
-{ "vpack2hl", 0x2ee97020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
+{ "vpack2hl", 0x2ee97020, 0xfffff020, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, UIMM6_20 }, { C_CC } }
 
 /* vpack2hl ZA,LIMM,SIMM12_20 00101110101010010111xxxxxxxxxxxx */
-{ "vpack2hl", 0x2ea97000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
+{ "vpack2hl", 0x2ea97000, 0xfffff000, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, SIMM12_20 }, { 0 } }
 
 /* vpack2hl RA,LIMM,LIMMdup 00101110001010010111111110xxxxxx */
-{ "vpack2hl", 0x2e297f80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { RA, LIMM, LIMMdup }, { 0 } }
+{ "vpack2hl", 0x2e297f80, 0xffffffc0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { RA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack2hl ZA,LIMM,LIMMdup 00101110001010010111111110111110 */
-{ "vpack2hl", 0x2e297fbe, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 } }
+{ "vpack2hl", 0x2e297fbe, 0xffffffff, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { 0 } }
 
 /* vpack2hl<.cc> ZA,LIMM,LIMMdup 001011101110100101111111100xxxxx */
-{ "vpack2hl", 0x2ee97f80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
+{ "vpack2hl", 0x2ee97f80, 0xffffffe0, ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32, MOVE, ARC_INSN_SUBCLASS_NONE, { ZA, LIMM, LIMMdup }, { C_CC } }
 
diff --git a/target/arc/fpu-helper-v2.c b/target/arc/fpu-helper-v2.c
index 8f46fcd62cd..c83f1daecda 100644
--- a/target/arc/fpu-helper-v2.c
+++ b/target/arc/fpu-helper-v2.c
@@ -19,6 +19,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/error-report.h"
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
diff --git a/target/arc/fpu.c b/target/arc/fpu.c
index 58b5c00eec2..8544cb59421 100644
--- a/target/arc/fpu.c
+++ b/target/arc/fpu.c
@@ -19,6 +19,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/error-report.h"
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
diff --git a/target/arc/gdbstub.c b/target/arc/gdbstub.c
index e33c70ce247..03fd76075fc 100644
--- a/target/arc/gdbstub.c
+++ b/target/arc/gdbstub.c
@@ -25,6 +25,7 @@
 #include "irq.h"
 #include "gdbstub.h"
 #include "mpu.h"
+#include "gdbstub/helpers.h"
 #include "exec/helper-proto.h"
 #include "fpu.h"
 
diff --git a/target/arc/helper.c b/target/arc/helper.c
index 756f024f017..873da1469a4 100644
--- a/target/arc/helper.c
+++ b/target/arc/helper.c
@@ -66,7 +66,7 @@ void arc_cpu_do_interrupt(CPUState *cs)
      * semihosting enabled.
      */
     if (cs->exception_index == EXCP_SWI
-        && semihosting_enabled()) {
+        && semihosting_enabled(false)) {
         qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n");
         do_arc_semihosting(env);
         /* Return to the next instruction. */
@@ -333,7 +333,7 @@ void helper_debug(CPUARCState *env)
 G_NORETURN void arc_raise_exception(CPUARCState *env, uintptr_t host_pc, int32_t excp_idx)
 {
     CPUState *cs = env_cpu(env);
-    cpu_restore_state(cs, host_pc, true);
+    cpu_restore_state(cs, host_pc);
     cs->exception_index = excp_idx;
     env->causecode = env->param = 0x0;
     env->eret  = env->pc;
diff --git a/target/arc/mmu-v6.c b/target/arc/mmu-v6.c
index ce69657bfd3..0e9741d8f76 100644
--- a/target/arc/mmu-v6.c
+++ b/target/arc/mmu-v6.c
@@ -761,7 +761,7 @@ static G_NORETURN void raise_mem_exception(
 {
     CPUARCState *env = &(ARC_CPU(cs)->env);
     if (excp->number != EXCP_IMMU_FAULT) {
-        cpu_restore_state(cs, host_pc, true);
+        cpu_restore_state(cs, host_pc);
     }
 
     env->efa = addr;
diff --git a/target/arc/mmu.c b/target/arc/mmu.c
index de8e2ad4bdc..661df2d4bc0 100644
--- a/target/arc/mmu.c
+++ b/target/arc/mmu.c
@@ -603,7 +603,7 @@ static G_NORETURN void raise_mem_exception(
 {
     CPUARCState *env = &(ARC_CPU(cs)->env);
     if (excp->number != EXCP_TLB_MISS_I) {
-        cpu_restore_state(cs, host_pc, true);
+        cpu_restore_state(cs, host_pc);
     }
 
     env->efa = addr;
diff --git a/target/arc/op_helper.c b/target/arc/op_helper.c
index 932ab9fd81f..f1a26fe9e51 100644
--- a/target/arc/op_helper.c
+++ b/target/arc/op_helper.c
@@ -25,6 +25,7 @@
 #include "exec/helper-proto.h"
 #include "exec/cpu_ldst.h"
 #include "exec/ioport.h"
+#include "exec/tb-flush.h"
 #include "target/arc/regs.h"
 #include "mmu.h"
 #include "hw/arc/cpudevs.h"
diff --git a/target/arc/regs-detail.def b/target/arc/regs-detail.def
index cd7c4a82329..5914f07be8a 100644
--- a/target/arc/regs-detail.def
+++ b/target/arc/regs-detail.def
@@ -22,231 +22,231 @@
  * binary search of register information based on address.
  */
 
-DEF(0xffff,ARC_OPCODE_ARCALL,  NONE, unimp_bcr)
-DEF(0x1,   ARC_OPCODE_ARCV1,   NONE, semaphore)
-DEF(0x2,   ARC_OPCODE_ARCALL,  NONE, lp_start)
-DEF(0x3,   ARC_OPCODE_ARCALL,  NONE, lp_end)
-DEF(0x4,   ARC_OPCODE_ARCALL,  NONE, identity)
-DEF(0x5,   ARC_OPCODE_ARCALL,  NONE, debug)
-DEF(0x6,   ARC_OPCODE_ARCALL,  NONE, pc)
-DEF(0x7,   ARC_OPCODE_ARCv2HS, NONE, memseg)
-DEF(0x7,   ARC_OPCODE_ARCV1,   NONE, adcr)
-DEF(0x8,   ARC_OPCODE_ARCV1,   NONE, apcr)
-DEF(0x8,   ARC_OPCODE_ARCv2HS, NONE, exec_ctrl)
-DEF(0x8,   ARC_OPCODE_V3_ALL,  NONE, exec_ctrl)
-DEF(0x9,   ARC_OPCODE_ARCV1,   NONE, acr)
-DEF(0x9,   ARC_OPCODE_ARCv2EM, NONE, sec_stat)
-DEF(0xa,   ARC_OPCODE_ARCALL,  NONE, status32)
-DEF(0xb,   ARC_OPCODE_ARCV2,   NONE, status32_p0)
-DEF(0xc,   ARC_OPCODE_ARCv2EM, NONE, sec_extra)
-DEF(0xd,   ARC_OPCODE_ARCV2,   NONE, aux_user_sp)
-DEF(0xd,   ARC_OPCODE_V3_ALL,  NONE, aux_user_sp)
-DEF(0xe,   ARC_OPCODE_ARC700,  NONE, clk_enable)
-DEF(0xe,   ARC_OPCODE_ARCV2,   NONE, aux_irq_ctrl)
-DEF(0xe,   ARC_OPCODE_V3_ALL,  NONE, aux_irq_ctrl)
-DEF(0xf,   ARC_OPCODE_ARC700,  NONE, bpu_flush)
-DEF(0xf,   ARC_OPCODE_ARCv2HS, NONE, debugi)
-DEF(0x10,  ARC_OPCODE_ARCV1,   NONE, ivic)
-DEF(0x10,  ARC_OPCODE_ARCALL,  NONE, ic_ivic)
-DEF(0x11,  ARC_OPCODE_ARCV1,   NONE, che_mode)
-DEF(0x11,  ARC_OPCODE_ARCALL,  NONE, ic_ctrl)
-DEF(0x12,  ARC_OPCODE_ARC600,  NONE, mulhi)
-DEF(0x12,  ARC_OPCODE_ARCv2HS, NONE, ic_startr)
-DEF(0x13,  ARC_OPCODE_ARCV1,   NONE, lockline)
-DEF(0x13,  ARC_OPCODE_ARCV2,   NONE, ic_lil)
-DEF(0x14,  ARC_OPCODE_ARC600,  NONE, dmc_code_ram)
-DEF(0x15,  ARC_OPCODE_ARCV1,   NONE, tag_addr_mask)
-DEF(0x16,  ARC_OPCODE_ARCV1,   NONE, tag_data_mask)
-DEF(0x16,  ARC_OPCODE_ARCv2HS, NONE, ic_ivir)
-DEF(0x17,  ARC_OPCODE_ARCV1,   NONE, line_length_mask)
-DEF(0x17,  ARC_OPCODE_ARCv2HS, NONE, ic_endr)
-DEF(0x18,  ARC_OPCODE_ARC600,  NONE, aux_ldst_ram)
-DEF(0x18,  ARC_OPCODE_NONE,    NONE, aux_dccm)
-DEF(0x19,  ARC_OPCODE_ARCV1,   NONE, unlockline)
-DEF(0x19,  ARC_OPCODE_ARCALL,  NONE, ic_ivil)
-DEF(0x1a,  ARC_OPCODE_ARCALL,  NONE, ic_ram_address)
-DEF(0x1b,  ARC_OPCODE_ARCALL,  NONE, ic_tag)
-DEF(0x1c,  ARC_OPCODE_ARCALL,  NONE, ic_wp)
-DEF(0x1d,  ARC_OPCODE_ARCALL,  NONE, ic_data)
-DEF(0x1e,  ARC_OPCODE_ARCALL,  NONE, ic_ptag)
-DEF(0x1f,  ARC_OPCODE_ARCv2EM, NONE, debugi)
-DEF(0x1f,  ARC_OPCODE_HS_HS5X, NONE, ic_ptag_hi)
-DEF(0x20,  ARC_OPCODE_ARC600,  NONE, sram_seq)
-DEF(0x21,  ARC_OPCODE_ARCALL,  NONE, count0)
-DEF(0x22,  ARC_OPCODE_ARCALL,  NONE, control0)
-DEF(0x23,  ARC_OPCODE_ARCALL,  NONE, limit0)
-DEF(0x24,  ARC_OPCODE_ARCV1,   NONE, pcport)
-DEF(0x25,  ARC_OPCODE_ARC700,  NONE, int_vector_base)
-DEF(0x25,  ARC_OPCODE_ARCV2,   NONE, int_vector_base)
-DEF(0x25,  ARC_OPCODE_V3_ALL,  NONE, int_vector_base)
-DEF(0x26,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_mode)
-DEF(0x27,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_bm0)
-DEF(0x28,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_bm1)
-DEF(0x29,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_accu)
-DEF(0x2a,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_ofst)
-DEF(0x2b,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_intstat)
-DEF(0x2c,  ARC_OPCODE_ARC600,  NONE, aux_xmac0_24)
-DEF(0x2d,  ARC_OPCODE_ARC600,  NONE, aux_xmac1_24)
-DEF(0x2e,  ARC_OPCODE_ARC600,  NONE, aux_xmac2_24)
-DEF(0x2f,  ARC_OPCODE_ARC600,  NONE, aux_fbf_store_16)
-DEF(0x30,  ARC_OPCODE_ARCv2EM, NONE, acg_ctrl)
-DEF(0x30,  ARC_OPCODE_NONE,    NONE, ax0)
-DEF(0x31,  ARC_OPCODE_NONE,    NONE, ax1)
-DEF(0x32,  ARC_OPCODE_NONE,    NONE, aux_crc_poly)
-DEF(0x33,  ARC_OPCODE_NONE,    NONE, aux_crc_mode)
-DEF(0x34,  ARC_OPCODE_NONE,    NONE, mx0)
-DEF(0x35,  ARC_OPCODE_NONE,    NONE, mx1)
-DEF(0x36,  ARC_OPCODE_NONE,    NONE, my0)
-DEF(0x37,  ARC_OPCODE_NONE,    NONE, my1)
-DEF(0x38,  ARC_OPCODE_NONE,    NONE, xyconfig)
-DEF(0x38,  ARC_OPCODE_ARCv2EM, NONE, aux_kernel_sp)
-DEF(0x39,  ARC_OPCODE_NONE,    NONE, scratch_a)
-DEF(0x39,  ARC_OPCODE_ARCv2EM, NONE, aux_sec_u_sp)
+DEF(0xffff,ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x1,   ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, semaphore)
+DEF(0x2,   ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, lp_start)
+DEF(0x3,   ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, lp_end)
+DEF(0x4,   ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, identity)
+DEF(0x5,   ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, debug)
+DEF(0x6,   ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, pc)
+DEF(0x7,   ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, memseg)
+DEF(0x7,   ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, adcr)
+DEF(0x8,   ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, apcr)
+DEF(0x8,   ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, exec_ctrl)
+DEF(0x8,   ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, exec_ctrl)
+DEF(0x9,   ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, acr)
+DEF(0x9,   ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, sec_stat)
+DEF(0xa,   ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, status32)
+DEF(0xb,   ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, status32_p0)
+DEF(0xc,   ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, sec_extra)
+DEF(0xd,   ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, aux_user_sp)
+DEF(0xd,   ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, aux_user_sp)
+DEF(0xe,   ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, clk_enable)
+DEF(0xe,   ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, aux_irq_ctrl)
+DEF(0xe,   ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, aux_irq_ctrl)
+DEF(0xf,   ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, bpu_flush)
+DEF(0xf,   ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, debugi)
+DEF(0x10,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, ivic)
+DEF(0x10,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ic_ivic)
+DEF(0x11,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, che_mode)
+DEF(0x11,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ic_ctrl)
+DEF(0x12,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, mulhi)
+DEF(0x12,  ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, ic_startr)
+DEF(0x13,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, lockline)
+DEF(0x13,  ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, ic_lil)
+DEF(0x14,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, dmc_code_ram)
+DEF(0x15,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, tag_addr_mask)
+DEF(0x16,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, tag_data_mask)
+DEF(0x16,  ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, ic_ivir)
+DEF(0x17,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, line_length_mask)
+DEF(0x17,  ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, ic_endr)
+DEF(0x18,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_ldst_ram)
+DEF(0x18,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, aux_dccm)
+DEF(0x19,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, unlockline)
+DEF(0x19,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ic_ivil)
+DEF(0x1a,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ic_ram_address)
+DEF(0x1b,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ic_tag)
+DEF(0x1c,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ic_wp)
+DEF(0x1d,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ic_data)
+DEF(0x1e,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ic_ptag)
+DEF(0x1f,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, debugi)
+DEF(0x1f,  ARC_OPCODE_HS_HS5X, ARC_INSN_SUBCLASS_NONE, ic_ptag_hi)
+DEF(0x20,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, sram_seq)
+DEF(0x21,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, count0)
+DEF(0x22,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, control0)
+DEF(0x23,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, limit0)
+DEF(0x24,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, pcport)
+DEF(0x25,  ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, int_vector_base)
+DEF(0x25,  ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, int_vector_base)
+DEF(0x25,  ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, int_vector_base)
+DEF(0x26,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_vbfdw_mode)
+DEF(0x27,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_vbfdw_bm0)
+DEF(0x28,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_vbfdw_bm1)
+DEF(0x29,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_vbfdw_accu)
+DEF(0x2a,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_vbfdw_ofst)
+DEF(0x2b,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_vbfdw_intstat)
+DEF(0x2c,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_xmac0_24)
+DEF(0x2d,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_xmac1_24)
+DEF(0x2e,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_xmac2_24)
+DEF(0x2f,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_fbf_store_16)
+DEF(0x30,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, acg_ctrl)
+DEF(0x30,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, ax0)
+DEF(0x31,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, ax1)
+DEF(0x32,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, aux_crc_poly)
+DEF(0x33,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, aux_crc_mode)
+DEF(0x34,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, mx0)
+DEF(0x35,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, mx1)
+DEF(0x36,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, my0)
+DEF(0x37,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, my1)
+DEF(0x38,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, xyconfig)
+DEF(0x38,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, aux_kernel_sp)
+DEF(0x39,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, scratch_a)
+DEF(0x39,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, aux_sec_u_sp)
 /* TODO: The commented lines are repeated for specific configurations. */
 /*
-DEF (0x3a,  ARC_OPCODE_NONE,    NONE, burstsys)
-DEF (0x3a,  ARC_OPCODE_NONE,    NONE, tsch)
+DEF (0x3a,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, burstsys)
+DEF (0x3a,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, tsch)
 */
-DEF(0x3a,  ARC_OPCODE_ARCv2EM, NONE, aux_sec_k_sp)
-DEF(0x3b,  ARC_OPCODE_NONE,    NONE, burstxym)
-DEF(0x3c,  ARC_OPCODE_NONE,    NONE, burstsz)
-DEF(0x3d,  ARC_OPCODE_NONE,    NONE, burstval)
-DEF(0x3e,  ARC_OPCODE_ARCv2EM, NONE, aux_sec_ctrl)
-DEF(0x3f,  ARC_OPCODE_ARCv2EM, NONE, erp_control)
-DEF(0x40,  ARC_OPCODE_ARCv2EM, NONE, rferp_status0)
-DEF(0x41,  ARC_OPCODE_ARCv2EM, NONE, rferp_status1)
-DEF(0x40,  ARC_OPCODE_ARC600,  NONE, xtp_newval)
-DEF(0x41,  ARC_OPCODE_ARCV1,   NONE, aux_macmode)
-DEF(0x42,  ARC_OPCODE_ARC600,  NONE, lsp_newval)
-DEF(0x43,  ARC_OPCODE_ARCV1,   NONE, aux_irq_lv12)
-DEF(0x43,  ARC_OPCODE_ARCV2,   NONE, aux_irq_act)
-DEF(0x43,  ARC_OPCODE_V3_ALL,  NONE, aux_irq_act)
-DEF(0x44,  ARC_OPCODE_ARCV1,   NONE, aux_xmac0)
-DEF(0x45,  ARC_OPCODE_ARCV1,   NONE, aux_xmac1)
-DEF(0x46,  ARC_OPCODE_ARCV1,   NONE, aux_xmac2)
-DEF(0x47,  ARC_OPCODE_ARCALL,  NONE, dc_ivdc)
-DEF(0x48,  ARC_OPCODE_ARCALL,  NONE, dc_ctrl)
-DEF(0x49,  ARC_OPCODE_ARCALL,  NONE, dc_ldl)
-DEF(0x4a,  ARC_OPCODE_ARCALL,  NONE, dc_ivdl)
-DEF(0x4b,  ARC_OPCODE_ARCALL,  NONE, dc_flsh)
-DEF(0x4c,  ARC_OPCODE_ARCALL,  NONE, dc_fldl)
-DEF(0x4d,  ARC_OPCODE_ARCV2,   NONE, dc_startr)
-DEF(0x4d,  ARC_OPCODE_V3_ALL,  NONE, dc_startr)
-DEF(0x4e,  ARC_OPCODE_ARCV2,   NONE, dc_endr)
-DEF(0x4e,  ARC_OPCODE_V3_ALL,  NONE, dc_endr)
-DEF(0x50,  ARC_OPCODE_NONE,    NONE, hexdata)
-DEF(0x51,  ARC_OPCODE_NONE,    NONE, hexctrl)
-DEF(0x52,  ARC_OPCODE_NONE,    NONE, led)
-DEF(0x56,  ARC_OPCODE_NONE,    NONE, dilstat)
-DEF(0x57,  ARC_OPCODE_ARC600,  NONE, swstat)
-DEF(0x58,  ARC_OPCODE_ARCALL,  NONE, dc_ram_addr)
-DEF(0x59,  ARC_OPCODE_ARCALL,  NONE, dc_tag)
-DEF(0x5a,  ARC_OPCODE_ARCALL,  NONE, dc_wp)
-DEF(0x5b,  ARC_OPCODE_ARCALL,  NONE, dc_data)
-DEF(0x5c,  ARC_OPCODE_ARCALL,  NONE, dc_ptag)
-DEF(0x5e,  ARC_OPCODE_ARCv2HS, NONE, aux_volatile)
-DEF(0x5f,  ARC_OPCODE_ARCv2HS, NONE, dc_ptag_hi)
-DEF(0x80,  ARC_OPCODE_ARCALL,  NONE, ax0)
-DEF(0x81,  ARC_OPCODE_ARCALL,  NONE, ax1)
-DEF(0x82,  ARC_OPCODE_ARCALL,  NONE, ax2)
-DEF(0x83,  ARC_OPCODE_ARCALL,  NONE, ax3)
-DEF(0x84,  ARC_OPCODE_ARCALL,  NONE, ay0)
-DEF(0x85,  ARC_OPCODE_ARCALL,  NONE, ay1)
-DEF(0x86,  ARC_OPCODE_ARCALL,  NONE, ay2)
-DEF(0x87,  ARC_OPCODE_ARCALL,  NONE, ay3)
-DEF(0x88,  ARC_OPCODE_ARCALL,  NONE, mx00)
-DEF(0x89,  ARC_OPCODE_ARCALL,  NONE, mx01)
-DEF(0x8a,  ARC_OPCODE_ARCALL,  NONE, mx10)
-DEF(0x8b,  ARC_OPCODE_ARCALL,  NONE, mx11)
-DEF(0x8c,  ARC_OPCODE_ARCALL,  NONE, mx20)
-DEF(0x8d,  ARC_OPCODE_ARCALL,  NONE, mx21)
-DEF(0x8e,  ARC_OPCODE_ARCALL,  NONE, mx30)
-DEF(0x8f,  ARC_OPCODE_ARCALL,  NONE, mx31)
-DEF(0x90,  ARC_OPCODE_ARCALL,  NONE, my00)
-DEF(0x91,  ARC_OPCODE_ARCALL,  NONE, my01)
-DEF(0x92,  ARC_OPCODE_ARCALL,  NONE, my10)
-DEF(0x93,  ARC_OPCODE_ARCALL,  NONE, my11)
-DEF(0x94,  ARC_OPCODE_ARCALL,  NONE, my20)
-DEF(0x95,  ARC_OPCODE_ARCALL,  NONE, my21)
-DEF(0x96,  ARC_OPCODE_ARCALL,  NONE, my30)
-DEF(0x97,  ARC_OPCODE_ARCALL,  NONE, my31)
-DEF(0x98,  ARC_OPCODE_ARCALL,  NONE, xyconfig)
-DEF(0x99,  ARC_OPCODE_ARCALL,  NONE, burstsys)
-DEF(0x9a,  ARC_OPCODE_ARCALL,  NONE, burstxym)
-DEF(0x9b,  ARC_OPCODE_ARCALL,  NONE, burstsz)
-DEF(0x9c,  ARC_OPCODE_ARCALL,  NONE, burstval)
-DEF(0x9d,  ARC_OPCODE_ARCALL,  NONE, xylsbasex)
-DEF(0x9e,  ARC_OPCODE_ARCALL,  NONE, xylsbasey)
-DEF(0x9f,  ARC_OPCODE_ARCALL,  NONE, aux_xmaclw_h)
-DEF(0xa0,  ARC_OPCODE_ARCALL,  NONE, aux_xmaclw_l)
-DEF(0xa1,  ARC_OPCODE_ARCALL,  NONE, se_ctrl)
-DEF(0xa2,  ARC_OPCODE_ARCALL,  NONE, se_stat)
-DEF(0xa3,  ARC_OPCODE_ARCALL,  NONE, se_err)
-DEF(0xa4,  ARC_OPCODE_ARCALL,  NONE, se_eadr)
-DEF(0xa5,  ARC_OPCODE_ARCALL,  NONE, se_spc)
-DEF(0xa6,  ARC_OPCODE_ARCALL,  NONE, sdm_base)
-DEF(0xa7,  ARC_OPCODE_ARCALL,  NONE, scm_base)
-DEF(0xa8,  ARC_OPCODE_ARCALL,  NONE, se_dbg_ctrl)
-DEF(0xa9,  ARC_OPCODE_ARCALL,  NONE, se_dbg_data0)
-DEF(0xaa,  ARC_OPCODE_ARCALL,  NONE, se_dbg_data1)
-DEF(0xab,  ARC_OPCODE_ARCALL,  NONE, se_dbg_data2)
-DEF(0xac,  ARC_OPCODE_ARCALL,  NONE, se_dbg_data3)
-DEF(0xad,  ARC_OPCODE_ARCALL,  NONE, se_watch)
-DEF(0xc1,  ARC_OPCODE_ARCALL,  NONE, isa_config)
-DEF(0x100, ARC_OPCODE_ARCALL,  NONE, count1)
-DEF(0x101, ARC_OPCODE_ARCALL,  NONE, control1)
-DEF(0x102, ARC_OPCODE_ARCALL,  NONE, limit1)
-DEF(0x103, ARC_OPCODE_ARCV2,   NONE, aux_rtc_ctrl)
-DEF(0x103, ARC_OPCODE_V3_ALL,  NONE, aux_rtc_ctrl)
-DEF(0x104, ARC_OPCODE_ARCV2,   NONE, aux_rtc_low)
-DEF(0x104, ARC_OPCODE_V3_ALL,  NONE, aux_rtc_low)
-DEF(0x105, ARC_OPCODE_ARCV2,   NONE, aux_rtc_high)
-DEF(0x105, ARC_OPCODE_V3_ALL,  NONE, aux_rtc_high)
-DEF(0x200, ARC_OPCODE_ARCV1,   NONE, aux_irq_lev)
-DEF(0x200, ARC_OPCODE_ARCV2,   NONE, irq_priority_pending)
-DEF(0x201, ARC_OPCODE_ARCALL,  NONE, aux_irq_hint)
-DEF(0x202, ARC_OPCODE_ARC600,  NONE, aux_inter_core_interrupt)
-DEF(0x206, ARC_OPCODE_ARCV2,   NONE, irq_priority)
-DEF(0x206, ARC_OPCODE_V3_ALL,  NONE, irq_priority)
-DEF(0x210, ARC_OPCODE_ARC700,  NONE, aes_aux_0)
-DEF(0x211, ARC_OPCODE_ARC700,  NONE, aes_aux_1)
-DEF(0x212, ARC_OPCODE_ARC700,  NONE, aes_aux_2)
-DEF(0x213, ARC_OPCODE_ARC700,  NONE, aes_crypt_mode)
-DEF(0x214, ARC_OPCODE_ARC700,  NONE, aes_auxs)
-DEF(0x215, ARC_OPCODE_ARC700,  NONE, aes_auxi)
-DEF(0x216, ARC_OPCODE_ARC700,  NONE, aes_aux_3)
-DEF(0x217, ARC_OPCODE_ARC700,  NONE, aes_aux_4)
-DEF(0x218, ARC_OPCODE_ARC700,  NONE, arith_ctl_aux)
-DEF(0x219, ARC_OPCODE_ARC700,  NONE, des_aux)
-DEF(0x220, ARC_OPCODE_ARCALL,  NONE, ap_amv0)
-DEF(0x221, ARC_OPCODE_ARCALL,  NONE, ap_amm0)
-DEF(0x222, ARC_OPCODE_ARCALL,  NONE, ap_ac0)
-DEF(0x223, ARC_OPCODE_ARCALL,  NONE, ap_amv1)
-DEF(0x224, ARC_OPCODE_ARCALL,  NONE, ap_amm1)
-DEF(0x225, ARC_OPCODE_ARCALL,  NONE, ap_ac1)
-DEF(0x226, ARC_OPCODE_ARCALL,  NONE, ap_amv2)
-DEF(0x227, ARC_OPCODE_ARCALL,  NONE, ap_amm2)
-DEF(0x228, ARC_OPCODE_ARCALL,  NONE, ap_ac2)
-DEF(0x229, ARC_OPCODE_ARCALL,  NONE, ap_amv3)
-DEF(0x22a, ARC_OPCODE_ARCALL,  NONE, ap_amm3)
-DEF(0x22b, ARC_OPCODE_ARCALL,  NONE, ap_ac3)
-DEF(0x22c, ARC_OPCODE_ARCALL,  NONE, ap_amv4)
-DEF(0x22d, ARC_OPCODE_ARCALL,  NONE, ap_amm4)
-DEF(0x22e, ARC_OPCODE_ARCALL,  NONE, ap_ac4)
-DEF(0x22f, ARC_OPCODE_ARCALL,  NONE, ap_amv5)
-DEF(0x230, ARC_OPCODE_ARCALL,  NONE, ap_amm5)
-DEF(0x231, ARC_OPCODE_ARCALL,  NONE, ap_ac5)
-DEF(0x232, ARC_OPCODE_ARCALL,  NONE, ap_amv6)
-DEF(0x233, ARC_OPCODE_ARCALL,  NONE, ap_amm6)
-DEF(0x234, ARC_OPCODE_ARCALL,  NONE, ap_ac6)
-DEF(0x235, ARC_OPCODE_ARCALL,  NONE, ap_amv7)
-DEF(0x236, ARC_OPCODE_ARCALL,  NONE, ap_amm7)
-DEF(0x237, ARC_OPCODE_ARCALL,  NONE, ap_ac7)
-DEF(0x268, ARC_OPCODE_ARCv2EM, NONE, nsc_table_top)
-DEF(0x269, ARC_OPCODE_ARCv2EM, NONE, nsc_table_base)
-DEF(0x290, ARC_OPCODE_ARCV2,   NONE, jli_base)
-DEF(0x291, ARC_OPCODE_ARCV2,   NONE, ldi_base)
-DEF(0x292, ARC_OPCODE_ARCV2,   NONE, ei_base)
+DEF(0x3a,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, aux_sec_k_sp)
+DEF(0x3b,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, burstxym)
+DEF(0x3c,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, burstsz)
+DEF(0x3d,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, burstval)
+DEF(0x3e,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, aux_sec_ctrl)
+DEF(0x3f,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, erp_control)
+DEF(0x40,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, rferp_status0)
+DEF(0x41,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, rferp_status1)
+DEF(0x40,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, xtp_newval)
+DEF(0x41,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, aux_macmode)
+DEF(0x42,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, lsp_newval)
+DEF(0x43,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, aux_irq_lv12)
+DEF(0x43,  ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, aux_irq_act)
+DEF(0x43,  ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, aux_irq_act)
+DEF(0x44,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, aux_xmac0)
+DEF(0x45,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, aux_xmac1)
+DEF(0x46,  ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, aux_xmac2)
+DEF(0x47,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_ivdc)
+DEF(0x48,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_ctrl)
+DEF(0x49,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_ldl)
+DEF(0x4a,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_ivdl)
+DEF(0x4b,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_flsh)
+DEF(0x4c,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_fldl)
+DEF(0x4d,  ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, dc_startr)
+DEF(0x4d,  ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, dc_startr)
+DEF(0x4e,  ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, dc_endr)
+DEF(0x4e,  ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, dc_endr)
+DEF(0x50,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, hexdata)
+DEF(0x51,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, hexctrl)
+DEF(0x52,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, led)
+DEF(0x56,  ARC_OPCODE_NONE,    ARC_INSN_SUBCLASS_NONE, dilstat)
+DEF(0x57,  ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, swstat)
+DEF(0x58,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_ram_addr)
+DEF(0x59,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_tag)
+DEF(0x5a,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_wp)
+DEF(0x5b,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_data)
+DEF(0x5c,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dc_ptag)
+DEF(0x5e,  ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, aux_volatile)
+DEF(0x5f,  ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, dc_ptag_hi)
+DEF(0x80,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ax0)
+DEF(0x81,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ax1)
+DEF(0x82,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ax2)
+DEF(0x83,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ax3)
+DEF(0x84,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ay0)
+DEF(0x85,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ay1)
+DEF(0x86,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ay2)
+DEF(0x87,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ay3)
+DEF(0x88,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mx00)
+DEF(0x89,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mx01)
+DEF(0x8a,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mx10)
+DEF(0x8b,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mx11)
+DEF(0x8c,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mx20)
+DEF(0x8d,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mx21)
+DEF(0x8e,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mx30)
+DEF(0x8f,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mx31)
+DEF(0x90,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, my00)
+DEF(0x91,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, my01)
+DEF(0x92,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, my10)
+DEF(0x93,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, my11)
+DEF(0x94,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, my20)
+DEF(0x95,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, my21)
+DEF(0x96,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, my30)
+DEF(0x97,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, my31)
+DEF(0x98,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, xyconfig)
+DEF(0x99,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, burstsys)
+DEF(0x9a,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, burstxym)
+DEF(0x9b,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, burstsz)
+DEF(0x9c,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, burstval)
+DEF(0x9d,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, xylsbasex)
+DEF(0x9e,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, xylsbasey)
+DEF(0x9f,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, aux_xmaclw_h)
+DEF(0xa0,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, aux_xmaclw_l)
+DEF(0xa1,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_ctrl)
+DEF(0xa2,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_stat)
+DEF(0xa3,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_err)
+DEF(0xa4,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_eadr)
+DEF(0xa5,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_spc)
+DEF(0xa6,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, sdm_base)
+DEF(0xa7,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, scm_base)
+DEF(0xa8,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_dbg_ctrl)
+DEF(0xa9,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_dbg_data0)
+DEF(0xaa,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_dbg_data1)
+DEF(0xab,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_dbg_data2)
+DEF(0xac,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_dbg_data3)
+DEF(0xad,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, se_watch)
+DEF(0xc1,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, isa_config)
+DEF(0x100, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, count1)
+DEF(0x101, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, control1)
+DEF(0x102, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, limit1)
+DEF(0x103, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, aux_rtc_ctrl)
+DEF(0x103, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, aux_rtc_ctrl)
+DEF(0x104, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, aux_rtc_low)
+DEF(0x104, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, aux_rtc_low)
+DEF(0x105, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, aux_rtc_high)
+DEF(0x105, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, aux_rtc_high)
+DEF(0x200, ARC_OPCODE_ARCV1,   ARC_INSN_SUBCLASS_NONE, aux_irq_lev)
+DEF(0x200, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, irq_priority_pending)
+DEF(0x201, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, aux_irq_hint)
+DEF(0x202, ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, aux_inter_core_interrupt)
+DEF(0x206, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, irq_priority)
+DEF(0x206, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, irq_priority)
+DEF(0x210, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aes_aux_0)
+DEF(0x211, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aes_aux_1)
+DEF(0x212, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aes_aux_2)
+DEF(0x213, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aes_crypt_mode)
+DEF(0x214, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aes_auxs)
+DEF(0x215, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aes_auxi)
+DEF(0x216, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aes_aux_3)
+DEF(0x217, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aes_aux_4)
+DEF(0x218, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, arith_ctl_aux)
+DEF(0x219, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, des_aux)
+DEF(0x220, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amv0)
+DEF(0x221, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amm0)
+DEF(0x222, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_ac0)
+DEF(0x223, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amv1)
+DEF(0x224, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amm1)
+DEF(0x225, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_ac1)
+DEF(0x226, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amv2)
+DEF(0x227, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amm2)
+DEF(0x228, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_ac2)
+DEF(0x229, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amv3)
+DEF(0x22a, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amm3)
+DEF(0x22b, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_ac3)
+DEF(0x22c, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amv4)
+DEF(0x22d, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amm4)
+DEF(0x22e, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_ac4)
+DEF(0x22f, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amv5)
+DEF(0x230, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amm5)
+DEF(0x231, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_ac5)
+DEF(0x232, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amv6)
+DEF(0x233, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amm6)
+DEF(0x234, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_ac6)
+DEF(0x235, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amv7)
+DEF(0x236, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_amm7)
+DEF(0x237, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ap_ac7)
+DEF(0x268, ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, nsc_table_top)
+DEF(0x269, ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, nsc_table_base)
+DEF(0x290, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, jli_base)
+DEF(0x291, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, ldi_base)
+DEF(0x292, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, ei_base)
 DEF(0x300, ARC_OPCODE_ARCFPX,  DPX,  fp_status)
 /*
 DEF (0x301, ARC_OPCODE_ARCFPX,  DPX,  aux_dpfp1l)
@@ -269,489 +269,489 @@ DEF (0x304, ARC_OPCODE_ARCFPX,  DPX,  d2h)
 DEF(0x304, ARC_OPCODE_ARCv2EM, DPA,  d2l)
 DEF(0x305, ARC_OPCODE_ARCFPX,  DPX,  dpfp_status)
 DEF(0x305, ARC_OPCODE_ARCv2EM, DPA,  d2h)
-DEF(0x400, ARC_OPCODE_ARCALL,  NONE, eret)
-DEF(0x401, ARC_OPCODE_ARCALL,  NONE, erbta)
-DEF(0x402, ARC_OPCODE_ARCALL,  NONE, erstatus)
-DEF(0x403, ARC_OPCODE_ARCALL,  NONE, ecr)
-DEF(0x404, ARC_OPCODE_ARCALL,  NONE, efa)
-DEF(0x405, ARC_OPCODE_ARC700,  NONE, tlbpd0)
-DEF(0x406, ARC_OPCODE_ARC700,  NONE, tlbpd1)
-DEF(0x406, ARC_OPCODE_ARCv2EM, NONE, ersec_stat)
-DEF(0x407, ARC_OPCODE_ARCv2EM, NONE, aux_sec_except)
-DEF(0x407, ARC_OPCODE_ARC700,  NONE, tlbindex)
-DEF(0x408, ARC_OPCODE_ARC700,  NONE, tlbcommand)
-DEF(0x409, ARC_OPCODE_ARC700,  NONE, pid)
-DEF(0x409, ARC_OPCODE_ARCALL,  NONE, mpuen)
-DEF(0x40a, ARC_OPCODE_ARCV2,   NONE, icause)
-DEF(0x40a, ARC_OPCODE_V3_ALL,  NONE, icause)
-DEF(0x40b, ARC_OPCODE_ARCV2,   NONE, irq_select)
-DEF(0x40b, ARC_OPCODE_V3_ALL,  NONE, irq_select)
-DEF(0x40c, ARC_OPCODE_ARCV2,   NONE, irq_enable)
-DEF(0x40c, ARC_OPCODE_V3_ALL,  NONE, irq_enable)
-DEF(0x40d, ARC_OPCODE_ARCV2,   NONE, irq_trigger)
-DEF(0x40d, ARC_OPCODE_V3_ALL,  NONE, irq_trigger)
-DEF(0x40f, ARC_OPCODE_ARCV2,   NONE, irq_status)
-DEF(0x40f, ARC_OPCODE_V3_ALL,  NONE, irq_status)
-DEF(0x410, ARC_OPCODE_ARCALL,  NONE, xpu)
-DEF(0x412, ARC_OPCODE_ARCALL,  NONE, bta)
-DEF(0x413, ARC_OPCODE_ARC700,  NONE, bta_l1)
-DEF(0x414, ARC_OPCODE_ARC700,  NONE, bta_l2)
-DEF(0x415, ARC_OPCODE_ARCV2,   NONE, irq_pulse_cancel)
-DEF(0x416, ARC_OPCODE_ARCV2,   NONE, irq_pending)
-DEF(0x418, ARC_OPCODE_ARC700,  NONE, scratch_data0)
-DEF(0x420, ARC_OPCODE_ARCALL,  NONE, mpuic)
-DEF(0x421, ARC_OPCODE_ARCALL,  NONE, mpufa)
-DEF(0x422, ARC_OPCODE_ARCALL,  NONE, mpurdb0)
-DEF(0x423, ARC_OPCODE_ARCALL,  NONE, mpurdp0)
-DEF(0x424, ARC_OPCODE_ARCALL,  NONE, mpurdb1)
-DEF(0x425, ARC_OPCODE_ARCALL,  NONE, mpurdp1)
-DEF(0x426, ARC_OPCODE_ARCALL,  NONE, mpurdb2)
-DEF(0x427, ARC_OPCODE_ARCALL,  NONE, mpurdp2)
-DEF(0x428, ARC_OPCODE_ARCALL,  NONE, mpurdb3)
-DEF(0x429, ARC_OPCODE_ARCALL,  NONE, mpurdp3)
-DEF(0x42a, ARC_OPCODE_ARCALL,  NONE, mpurdb4)
-DEF(0x42b, ARC_OPCODE_ARCALL,  NONE, mpurdp4)
-DEF(0x42c, ARC_OPCODE_ARCALL,  NONE, mpurdb5)
-DEF(0x42d, ARC_OPCODE_ARCALL,  NONE, mpurdp5)
-DEF(0x42e, ARC_OPCODE_ARCALL,  NONE, mpurdb6)
-DEF(0x42f, ARC_OPCODE_ARCALL,  NONE, mpurdp6)
-DEF(0x430, ARC_OPCODE_ARCALL,  NONE, mpurdb7)
-DEF(0x431, ARC_OPCODE_ARCALL,  NONE, mpurdp7)
-DEF(0x432, ARC_OPCODE_ARCALL,  NONE, mpurdb8)
-DEF(0x433, ARC_OPCODE_ARCALL,  NONE, mpurdp8)
-DEF(0x434, ARC_OPCODE_ARCALL,  NONE, mpurdb9)
-DEF(0x435, ARC_OPCODE_ARCALL,  NONE, mpurdp9)
-DEF(0x436, ARC_OPCODE_ARCALL,  NONE, mpurdb10)
-DEF(0x437, ARC_OPCODE_ARCALL,  NONE, mpurdp10)
-DEF(0x438, ARC_OPCODE_ARCALL,  NONE, mpurdb11)
-DEF(0x439, ARC_OPCODE_ARCALL,  NONE, mpurdp11)
-DEF(0x43a, ARC_OPCODE_ARCALL,  NONE, mpurdb12)
-DEF(0x43b, ARC_OPCODE_ARCALL,  NONE, mpurdp12)
-DEF(0x43c, ARC_OPCODE_ARCALL,  NONE, mpurdb13)
-DEF(0x43d, ARC_OPCODE_ARCALL,  NONE, mpurdp13)
-DEF(0x43e, ARC_OPCODE_ARCALL,  NONE, mpurdb14)
-DEF(0x43f, ARC_OPCODE_ARCALL,  NONE, mpurdp14)
-DEF(0x440, ARC_OPCODE_ARCALL,  NONE, mpurdb15)
-DEF(0x441, ARC_OPCODE_ARCALL,  NONE, mpurdp15)
-DEF(0x450, ARC_OPCODE_ARC600,  NONE, pm_status)
-DEF(0x451, ARC_OPCODE_ARC600,  NONE, wake)
-DEF(0x452, ARC_OPCODE_ARC600,  NONE, dvfs_performance)
-DEF(0x453, ARC_OPCODE_ARC600,  NONE, pwr_ctrl)
-DEF(0x460, ARC_OPCODE_ARCv2HS, NONE, tlbpd0)
-DEF(0x461, ARC_OPCODE_ARCv2HS, NONE, tlbpd1)
-DEF(0x463, ARC_OPCODE_ARCv2HS, NONE, tlbpd1_hi)
-DEF(0x464, ARC_OPCODE_ARCv2HS, NONE, tlbindex)
-DEF(0x465, ARC_OPCODE_ARCv2HS, NONE, tlbcommand)
-DEF(0x468, ARC_OPCODE_ARCv2HS, NONE, pid)
-DEF(0x46a, ARC_OPCODE_ARCv2HS, NONE, sasid0)
-DEF(0x46b, ARC_OPCODE_ARCv2HS, NONE, sasid1)
-DEF(0x46c, ARC_OPCODE_ARCv2HS, NONE, scratch_data0)
-DEF(0x500, ARC_OPCODE_ARC700,  NONE, aux_vlc_buf_idx)
-DEF(0x501, ARC_OPCODE_ARC700,  NONE, aux_vlc_read_buf)
-DEF(0x502, ARC_OPCODE_ARC700,  NONE, aux_vlc_valid_bits)
-DEF(0x503, ARC_OPCODE_ARC700,  NONE, aux_vlc_buf_in)
-DEF(0x504, ARC_OPCODE_ARC700,  NONE, aux_vlc_buf_free)
-DEF(0x505, ARC_OPCODE_ARC700,  NONE, aux_vlc_ibuf_status)
-DEF(0x506, ARC_OPCODE_ARC700,  NONE, aux_vlc_setup)
-DEF(0x507, ARC_OPCODE_ARC700,  NONE, aux_vlc_bits)
-DEF(0x508, ARC_OPCODE_ARC700,  NONE, aux_vlc_table)
-DEF(0x509, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_symbol)
-DEF(0x50a, ARC_OPCODE_ARC700,  NONE, aux_vlc_read_symbol)
-DEF(0x510, ARC_OPCODE_ARC700,  NONE, aux_ucavlc_setup)
-DEF(0x511, ARC_OPCODE_ARC700,  NONE, aux_ucavlc_state)
-DEF(0x512, ARC_OPCODE_ARC700,  NONE, aux_cavlc_zero_left)
-DEF(0x514, ARC_OPCODE_ARC700,  NONE, aux_uvlc_i_state)
-DEF(0x51c, ARC_OPCODE_ARC700,  NONE, aux_vlc_dma_ptr)
-DEF(0x51d, ARC_OPCODE_ARC700,  NONE, aux_vlc_dma_end)
-DEF(0x51e, ARC_OPCODE_ARC700,  NONE, aux_vlc_dma_esc)
-DEF(0x51f, ARC_OPCODE_ARC700,  NONE, aux_vlc_dma_ctrl)
-DEF(0x520, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_0bit)
-DEF(0x521, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_1bit)
-DEF(0x522, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_2bit)
-DEF(0x523, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_3bit)
-DEF(0x524, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_4bit)
-DEF(0x525, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_5bit)
-DEF(0x526, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_6bit)
-DEF(0x527, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_7bit)
-DEF(0x528, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_8bit)
-DEF(0x529, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_9bit)
-DEF(0x52a, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_10bit)
-DEF(0x52b, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_11bit)
-DEF(0x52c, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_12bit)
-DEF(0x52d, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_13bit)
-DEF(0x52e, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_14bit)
-DEF(0x52f, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_15bit)
-DEF(0x530, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_16bit)
-DEF(0x531, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_17bit)
-DEF(0x532, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_18bit)
-DEF(0x533, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_19bit)
-DEF(0x534, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_20bit)
-DEF(0x535, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_21bit)
-DEF(0x536, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_22bit)
-DEF(0x537, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_23bit)
-DEF(0x538, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_24bit)
-DEF(0x539, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_25bit)
-DEF(0x53a, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_26bit)
-DEF(0x53b, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_27bit)
-DEF(0x53c, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_28bit)
-DEF(0x53d, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_29bit)
-DEF(0x53e, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_30bit)
-DEF(0x53f, ARC_OPCODE_ARC700,  NONE, aux_vlc_get_31bit)
-DEF(0x540, ARC_OPCODE_ARC700,  NONE, aux_cabac_ctrl)
-DEF(0x541, ARC_OPCODE_ARC700,  NONE, aux_cabac_ctx_state)
-DEF(0x542, ARC_OPCODE_ARC700,  NONE, aux_cabac_cod_param)
-DEF(0x543, ARC_OPCODE_ARC700,  NONE, aux_cabac_misc0)
-DEF(0x544, ARC_OPCODE_ARC700,  NONE, aux_cabac_misc1)
-DEF(0x545, ARC_OPCODE_ARC700,  NONE, aux_cabac_misc2)
+DEF(0x400, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, eret)
+DEF(0x401, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, erbta)
+DEF(0x402, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, erstatus)
+DEF(0x403, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ecr)
+DEF(0x404, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, efa)
+DEF(0x405, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, tlbpd0)
+DEF(0x406, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, tlbpd1)
+DEF(0x406, ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, ersec_stat)
+DEF(0x407, ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, aux_sec_except)
+DEF(0x407, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, tlbindex)
+DEF(0x408, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, tlbcommand)
+DEF(0x409, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, pid)
+DEF(0x409, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpuen)
+DEF(0x40a, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, icause)
+DEF(0x40a, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, icause)
+DEF(0x40b, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, irq_select)
+DEF(0x40b, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, irq_select)
+DEF(0x40c, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, irq_enable)
+DEF(0x40c, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, irq_enable)
+DEF(0x40d, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, irq_trigger)
+DEF(0x40d, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, irq_trigger)
+DEF(0x40f, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, irq_status)
+DEF(0x40f, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, irq_status)
+DEF(0x410, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, xpu)
+DEF(0x412, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, bta)
+DEF(0x413, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, bta_l1)
+DEF(0x414, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, bta_l2)
+DEF(0x415, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, irq_pulse_cancel)
+DEF(0x416, ARC_OPCODE_ARCV2,   ARC_INSN_SUBCLASS_NONE, irq_pending)
+DEF(0x418, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, scratch_data0)
+DEF(0x420, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpuic)
+DEF(0x421, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpufa)
+DEF(0x422, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb0)
+DEF(0x423, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp0)
+DEF(0x424, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb1)
+DEF(0x425, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp1)
+DEF(0x426, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb2)
+DEF(0x427, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp2)
+DEF(0x428, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb3)
+DEF(0x429, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp3)
+DEF(0x42a, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb4)
+DEF(0x42b, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp4)
+DEF(0x42c, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb5)
+DEF(0x42d, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp5)
+DEF(0x42e, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb6)
+DEF(0x42f, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp6)
+DEF(0x430, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb7)
+DEF(0x431, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp7)
+DEF(0x432, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb8)
+DEF(0x433, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp8)
+DEF(0x434, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb9)
+DEF(0x435, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp9)
+DEF(0x436, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb10)
+DEF(0x437, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp10)
+DEF(0x438, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb11)
+DEF(0x439, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp11)
+DEF(0x43a, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb12)
+DEF(0x43b, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp12)
+DEF(0x43c, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb13)
+DEF(0x43d, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp13)
+DEF(0x43e, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb14)
+DEF(0x43f, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp14)
+DEF(0x440, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdb15)
+DEF(0x441, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpurdp15)
+DEF(0x450, ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, pm_status)
+DEF(0x451, ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, wake)
+DEF(0x452, ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, dvfs_performance)
+DEF(0x453, ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, pwr_ctrl)
+DEF(0x460, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, tlbpd0)
+DEF(0x461, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, tlbpd1)
+DEF(0x463, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, tlbpd1_hi)
+DEF(0x464, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, tlbindex)
+DEF(0x465, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, tlbcommand)
+DEF(0x468, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, pid)
+DEF(0x46a, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, sasid0)
+DEF(0x46b, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, sasid1)
+DEF(0x46c, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, scratch_data0)
+DEF(0x500, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_buf_idx)
+DEF(0x501, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_read_buf)
+DEF(0x502, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_valid_bits)
+DEF(0x503, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_buf_in)
+DEF(0x504, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_buf_free)
+DEF(0x505, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_ibuf_status)
+DEF(0x506, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_setup)
+DEF(0x507, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_bits)
+DEF(0x508, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_table)
+DEF(0x509, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_symbol)
+DEF(0x50a, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_read_symbol)
+DEF(0x510, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_ucavlc_setup)
+DEF(0x511, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_ucavlc_state)
+DEF(0x512, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_cavlc_zero_left)
+DEF(0x514, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_uvlc_i_state)
+DEF(0x51c, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_dma_ptr)
+DEF(0x51d, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_dma_end)
+DEF(0x51e, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_dma_esc)
+DEF(0x51f, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_dma_ctrl)
+DEF(0x520, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_0bit)
+DEF(0x521, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_1bit)
+DEF(0x522, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_2bit)
+DEF(0x523, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_3bit)
+DEF(0x524, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_4bit)
+DEF(0x525, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_5bit)
+DEF(0x526, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_6bit)
+DEF(0x527, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_7bit)
+DEF(0x528, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_8bit)
+DEF(0x529, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_9bit)
+DEF(0x52a, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_10bit)
+DEF(0x52b, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_11bit)
+DEF(0x52c, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_12bit)
+DEF(0x52d, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_13bit)
+DEF(0x52e, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_14bit)
+DEF(0x52f, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_15bit)
+DEF(0x530, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_16bit)
+DEF(0x531, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_17bit)
+DEF(0x532, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_18bit)
+DEF(0x533, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_19bit)
+DEF(0x534, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_20bit)
+DEF(0x535, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_21bit)
+DEF(0x536, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_22bit)
+DEF(0x537, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_23bit)
+DEF(0x538, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_24bit)
+DEF(0x539, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_25bit)
+DEF(0x53a, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_26bit)
+DEF(0x53b, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_27bit)
+DEF(0x53c, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_28bit)
+DEF(0x53d, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_29bit)
+DEF(0x53e, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_30bit)
+DEF(0x53f, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_vlc_get_31bit)
+DEF(0x540, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_cabac_ctrl)
+DEF(0x541, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_cabac_ctx_state)
+DEF(0x542, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_cabac_cod_param)
+DEF(0x543, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_cabac_misc0)
+DEF(0x544, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_cabac_misc1)
+DEF(0x545, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, aux_cabac_misc2)
 
 /* ARConnect */
-DEF(0xd0, ARC_OPCODE_ARCALL,  NONE, mcip_bcr)
-DEF(0xd5, ARC_OPCODE_ARCALL,  NONE, mcip_idu_bcr)
-DEF(0xd6, ARC_OPCODE_ARCALL,  NONE, mcip_gfrc_bcr)
-DEF(0xe0, ARC_OPCODE_ARCALL,  NONE, mcip_ici_bcr)
-DEF(0x600, ARC_OPCODE_ARCALL,  NONE, mcip_cmd)
-DEF(0x601, ARC_OPCODE_ARCALL,  NONE, mcip_wdata)
-DEF(0x602, ARC_OPCODE_ARCALL,  NONE, mcip_readback)
+DEF(0xd0, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mcip_bcr)
+DEF(0xd5, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mcip_idu_bcr)
+DEF(0xd6, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mcip_gfrc_bcr)
+DEF(0xe0, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mcip_ici_bcr)
+DEF(0x600, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mcip_cmd)
+DEF(0x601, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mcip_wdata)
+DEF(0x602, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mcip_readback)
 
-DEF(0x700, ARC_OPCODE_ARCALL,  NONE, smart_control)
+DEF(0x700, ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, smart_control)
 /*
-DEF (0x701, ARC_OPCODE_ARC700,  NONE, smart_data_0)
-DEF (0x701, ARC_OPCODE_ARC600,  NONE, smart_data)
-DEF (0x701, ARC_OPCODE_ARC700,  NONE, smart_data_2)
-DEF (0x701, ARC_OPCODE_ARC700,  NONE, smart_data_3)
+DEF (0x701, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, smart_data_0)
+DEF (0x701, ARC_OPCODE_ARC600,  ARC_INSN_SUBCLASS_NONE, smart_data)
+DEF (0x701, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, smart_data_2)
+DEF (0x701, ARC_OPCODE_ARC700,  ARC_INSN_SUBCLASS_NONE, smart_data_3)
 */
 
 
 /* BCR aux registers */
-DEF(0x60, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x61, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x62, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x63, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x64, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x65, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x66, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x67, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x68, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x69, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x6a, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x6b, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x6c, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x6d, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x6e, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x6f, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x70, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x71, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x72, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x73, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x74, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x75, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x76, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x77, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x78, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x79, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x7a, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x7c, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x7d, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x7e, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0x7f, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc0, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xc9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xca, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xcb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xcc, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xcd, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xce, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xcf, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xd1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xd2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xd3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xd4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xd7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xd8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xd9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xda, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xdb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xdc, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xdd, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xde, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xdf, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xe9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xea, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xeb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xec, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xed, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xee, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xef, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf0, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
+DEF(0x60, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x61, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x62, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x63, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x64, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x65, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x66, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x67, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x68, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x69, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x6a, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x6b, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x6c, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x6d, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x6e, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x6f, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x70, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x71, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x72, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x73, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x74, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x75, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x76, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x77, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x78, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x79, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x7a, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x7c, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x7d, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x7e, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0x7f, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc0, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xc9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xca, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xcb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xcc, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xcd, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xce, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xcf, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xd1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xd2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xd3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xd4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xd7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xd8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xd9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xda, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xdb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xdc, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xdd, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xde, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xdf, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xe9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xea, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xeb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xec, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xed, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xee, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xef, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf0, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
 
-DEF(0xf60, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf61, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf62, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf63, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf64, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf65, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf66, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf67, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf68, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf69, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf6a, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf6b, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf6c, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf6d, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf6e, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf6f, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf70, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf71, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf72, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf73, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf74, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf75, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf76, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf77, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf78, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf79, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf7a, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf7b, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf7c, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf7d, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf7e, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf7f, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf80, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf81, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf82, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf83, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf84, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf85, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf86, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf87, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf88, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf89, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf8a, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf8b, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf8c, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf8d, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf8e, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf8f, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf90, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf91, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf92, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf93, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf94, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf95, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf96, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf97, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf98, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf99, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf9a, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf9b, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf9c, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf9d, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf9e, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xf9f, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa0, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfa9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfaa, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfab, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfac, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfad, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfae, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfaf, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb0, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfb9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfba, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfbb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfbc, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfbd, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfbe, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfbf, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc0, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfc9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfca, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfcb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfcc, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfcd, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfce, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfcf, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd0, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfd9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfda, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfdb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfdc, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfdd, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfde, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfdf, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe0, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfe9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfea, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfeb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfec, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfed, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfee, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfef, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff0, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff1, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff2, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff3, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff4, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff5, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff6, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff7, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff8, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xff9, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xffa, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xffb, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xffc, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xffd, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xffe, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
-DEF(0xfff, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
+DEF(0xf60, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf61, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf62, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf63, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf64, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf65, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf66, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf67, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf68, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf69, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf6a, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf6b, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf6c, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf6d, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf6e, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf6f, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf70, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf71, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf72, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf73, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf74, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf75, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf76, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf77, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf78, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf79, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf7a, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf7b, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf7c, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf7d, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf7e, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf7f, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf80, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf81, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf82, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf83, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf84, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf85, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf86, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf87, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf88, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf89, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf8a, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf8b, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf8c, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf8d, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf8e, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf8f, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf90, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf91, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf92, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf93, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf94, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf95, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf96, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf97, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf98, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf99, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf9a, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf9b, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf9c, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf9d, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf9e, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xf9f, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa0, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfa9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfaa, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfab, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfac, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfad, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfae, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfaf, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb0, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfb9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfba, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfbb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfbc, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfbd, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfbe, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfbf, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc0, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfc9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfca, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfcb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfcc, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfcd, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfce, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfcf, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd0, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfd9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfda, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfdb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfdc, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfdd, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfde, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfdf, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe0, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfe9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfea, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfeb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfec, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfed, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfee, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfef, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff0, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff1, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff2, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff3, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff4, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff5, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff6, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff7, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff8, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xff9, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xffa, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xffb, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xffc, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xffd, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xffe, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
+DEF(0xfff, ARC_OPCODE_DEFAULT,  ARC_INSN_SUBCLASS_NONE, unimp_bcr)
 
 /* Actual BCR implementations */
 
-DEF(0x6d, ARC_OPCODE_ARCv2EM, NONE, mpu_build)
-DEF(0x6d, ARC_OPCODE_ARCv2HS, NONE, mpu_build)
-DEF(0x6d, ARC_OPCODE_V3_ALL,  NONE, mpu_build)
-DEF(0x6f, ARC_OPCODE_ARCv2HS, NONE, mmu_build)
-DEF(0x75, ARC_OPCODE_ARCALL, NONE, timer_build)
-DEF(0xf3, ARC_OPCODE_ARCV2,  NONE, irq_build)
-DEF(0xf3, ARC_OPCODE_V3_ALL, NONE, irq_build)
-DEF(0x72, ARC_OPCODE_ARCV2,  NONE, dc_build)
-DEF(0x72, ARC_OPCODE_V3_ALL, NONE, dc_build)
-DEF(0x77, ARC_OPCODE_ARCV2,  NONE, ic_build)
-DEF(0x77, ARC_OPCODE_V3_ALL, NONE, ic_build)
-DEF(0x7b, ARC_OPCODE_ARCV2,  NONE, mpy_build)
-DEF(0x7b, ARC_OPCODE_V3_ALL, NONE, mpy_build)
-DEF(0x7c, ARC_OPCODE_ARCALL, NONE, swap_build)
-DEF(0x7d, ARC_OPCODE_ARCALL, NONE, norm_build)
-DEF(0x7f, ARC_OPCODE_ARCALL, NONE, barrel_build)
+DEF(0x6d, ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, mpu_build)
+DEF(0x6d, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, mpu_build)
+DEF(0x6d, ARC_OPCODE_V3_ALL,  ARC_INSN_SUBCLASS_NONE, mpu_build)
+DEF(0x6f, ARC_OPCODE_ARCv2HS, ARC_INSN_SUBCLASS_NONE, mmu_build)
+DEF(0x75, ARC_OPCODE_ARCALL, ARC_INSN_SUBCLASS_NONE, timer_build)
+DEF(0xf3, ARC_OPCODE_ARCV2,  ARC_INSN_SUBCLASS_NONE, irq_build)
+DEF(0xf3, ARC_OPCODE_V3_ALL, ARC_INSN_SUBCLASS_NONE, irq_build)
+DEF(0x72, ARC_OPCODE_ARCV2,  ARC_INSN_SUBCLASS_NONE, dc_build)
+DEF(0x72, ARC_OPCODE_V3_ALL, ARC_INSN_SUBCLASS_NONE, dc_build)
+DEF(0x77, ARC_OPCODE_ARCV2,  ARC_INSN_SUBCLASS_NONE, ic_build)
+DEF(0x77, ARC_OPCODE_V3_ALL, ARC_INSN_SUBCLASS_NONE, ic_build)
+DEF(0x7b, ARC_OPCODE_ARCV2,  ARC_INSN_SUBCLASS_NONE, mpy_build)
+DEF(0x7b, ARC_OPCODE_V3_ALL, ARC_INSN_SUBCLASS_NONE, mpy_build)
+DEF(0x7c, ARC_OPCODE_ARCALL, ARC_INSN_SUBCLASS_NONE, swap_build)
+DEF(0x7d, ARC_OPCODE_ARCALL, ARC_INSN_SUBCLASS_NONE, norm_build)
+DEF(0x7f, ARC_OPCODE_ARCALL, ARC_INSN_SUBCLASS_NONE, barrel_build)
 
 /* OLD BCR definitions */
 /*
-DEF (0x61,  ARC_OPCODE_ARCALL,  NONE, dccm_base_build)
-DEF (0x63,  ARC_OPCODE_ARCALL,  NONE, bta_link_build)
-DEF (0x64,  ARC_OPCODE_ARCALL,  NONE, vbfdw_build)
-DEF (0x65,  ARC_OPCODE_ARCALL,  NONE, ea_build)
-DEF (0x66,  ARC_OPCODE_ARCALL,  NONE, dataspace)
-DEF (0x67,  ARC_OPCODE_ARCALL,  NONE, memsubsys)
-DEF (0x68,  ARC_OPCODE_ARCALL,  NONE, vecbase_ac_build)
-DEF (0x69,  ARC_OPCODE_ARCALL,  NONE, p_base_addr)
-DEF (0x6a,  ARC_OPCODE_ARCALL,  NONE, data_uncached_build)
-DEF (0x6b,  ARC_OPCODE_ARCALL,  NONE, fp_build)
-DEF (0x6c,  ARC_OPCODE_ARCALL,  NONE, dpfp_build)
-DEF (0x6d,  ARC_OPCODE_ARCALL,  NONE, mpu_build)
-DEF (0x6e,  ARC_OPCODE_ARCALL,  NONE, rf_build)
-DEF (0x6f,  ARC_OPCODE_ARCALL,  NONE, mmu_build)
-DEF (0x70,  ARC_OPCODE_ARCv2EM, NONE, sec_vecbase_build)
-DEF (0x71,  ARC_OPCODE_ARCALL,  NONE, vecbase_build)
-DEF (0x73,  ARC_OPCODE_ARCALL,  NONE, madi_build)
+DEF (0x61,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dccm_base_build)
+DEF (0x63,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, bta_link_build)
+DEF (0x64,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, vbfdw_build)
+DEF (0x65,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ea_build)
+DEF (0x66,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dataspace)
+DEF (0x67,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, memsubsys)
+DEF (0x68,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, vecbase_ac_build)
+DEF (0x69,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, p_base_addr)
+DEF (0x6a,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, data_uncached_build)
+DEF (0x6b,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, fp_build)
+DEF (0x6c,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dpfp_build)
+DEF (0x6d,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mpu_build)
+DEF (0x6e,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, rf_build)
+DEF (0x6f,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, mmu_build)
+DEF (0x70,  ARC_OPCODE_ARCv2EM, ARC_INSN_SUBCLASS_NONE, sec_vecbase_build)
+DEF (0x71,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, vecbase_build)
+DEF (0x73,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, madi_build)
 
-DEF (0xf4,  ARC_OPCODE_ARCALL,  NONE, hwp_build)
-DEF (0xf5,  ARC_OPCODE_ARCALL,  NONE, pct_build)
-DEF (0xf6,  ARC_OPCODE_ARCALL,  NONE, cc_build)
-DEF (0xf7,  ARC_OPCODE_ARCALL,  NONE, pm_bcr)
-DEF (0xf8,  ARC_OPCODE_ARCALL,  NONE, scq_switch_build)
-DEF (0xf9,  ARC_OPCODE_ARCALL,  NONE, vraptor_build)
-DEF (0xfa,  ARC_OPCODE_ARCALL,  NONE, dma_config)
-DEF (0xfb,  ARC_OPCODE_ARCALL,  NONE, simd_config)
-DEF (0xfc,  ARC_OPCODE_ARCALL,  NONE, vlc_build)
-DEF (0xfd,  ARC_OPCODE_ARCALL,  NONE, simd_dma_build)
-DEF (0xfe,  ARC_OPCODE_ARCALL,  NONE, ifetch_queue_build)
+DEF (0xf4,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, hwp_build)
+DEF (0xf5,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, pct_build)
+DEF (0xf6,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, cc_build)
+DEF (0xf7,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, pm_bcr)
+DEF (0xf8,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, scq_switch_build)
+DEF (0xf9,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, vraptor_build)
+DEF (0xfa,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, dma_config)
+DEF (0xfb,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, simd_config)
+DEF (0xfc,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, vlc_build)
+DEF (0xfd,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, simd_dma_build)
+DEF (0xfe,  ARC_OPCODE_ARCALL,  ARC_INSN_SUBCLASS_NONE, ifetch_queue_build)
 */
 
 /* ARCV3 definitions. */
 
-DEF (0x7,   ARC_OPCODE_V3_ALL,   NONE, memseg)
-DEF (0x16,  ARC_OPCODE_V3_ALL,   NONE, ic_ivir)
-DEF (0x17,  ARC_OPCODE_V3_ALL,   NONE, ic_endr)
-DEF (0x460, ARC_OPCODE_V3_ALL,   NONE, mmu_rtp0)
-DEF (0x461, ARC_OPCODE_V3_ALL,   NONE, mmu_rtp0hi)
-DEF (0x462, ARC_OPCODE_V3_ALL,   NONE, mmu_rtp1)
-DEF (0x463, ARC_OPCODE_V3_ALL,   NONE, mmu_rtp1hi)
-DEF (0x464, ARC_OPCODE_V3_ALL,   NONE, tlbindex)
-DEF (0x465, ARC_OPCODE_V3_ALL,   NONE, mmuv6_tlbcommand)
-DEF (0x466, ARC_OPCODE_V3_ALL,   NONE, mmu_tlb_data0)
-DEF (0x467, ARC_OPCODE_V3_ALL,   NONE, mmu_tlb_data1)
-DEF (0x468, ARC_OPCODE_V3_ALL,   NONE, mmu_ctrl)
-DEF (0x469, ARC_OPCODE_V3_ALL,   NONE, mmu_ttbcr)
-DEF (0x46a, ARC_OPCODE_V3_ALL,   NONE, mmu_mem_attr_lo)
-DEF (0x46b, ARC_OPCODE_V3_ALL,   NONE, mmu_mem_attr_hi)
-DEF (0x46c, ARC_OPCODE_V3_ALL,   NONE, mmu_fault_status)
-DEF (0xc1,  ARC_OPCODE_V3_ALL,   NONE, isa_config)
-DEF (0x6f,  ARC_OPCODE_V3_ALL,   NONE, mmuv6_build)
-DEF (0x4f,  ARC_OPCODE_V3_ALL,   NONE, hw_pf_ctrl)
+DEF (0x7,   ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, memseg)
+DEF (0x16,  ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, ic_ivir)
+DEF (0x17,  ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, ic_endr)
+DEF (0x460, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_rtp0)
+DEF (0x461, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_rtp0hi)
+DEF (0x462, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_rtp1)
+DEF (0x463, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_rtp1hi)
+DEF (0x464, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, tlbindex)
+DEF (0x465, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmuv6_tlbcommand)
+DEF (0x466, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_tlb_data0)
+DEF (0x467, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_tlb_data1)
+DEF (0x468, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_ctrl)
+DEF (0x469, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_ttbcr)
+DEF (0x46a, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_mem_attr_lo)
+DEF (0x46b, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_mem_attr_hi)
+DEF (0x46c, ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmu_fault_status)
+DEF (0xc1,  ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, isa_config)
+DEF (0x6f,  ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, mmuv6_build)
+DEF (0x4f,  ARC_OPCODE_V3_ALL,   ARC_INSN_SUBCLASS_NONE, hw_pf_ctrl)
 
 /* Floating point defitions */
 
-DEF (0x300,  ARC_OPCODE_V2_V3,   NONE, fpu_ctrl)
-DEF (0x301,  ARC_OPCODE_V2_V3,   NONE, fpu_status)
-DEF (0xC8,  ARC_OPCODE_V2_V3,   NONE, fpu_build)
+DEF (0x300,  ARC_OPCODE_V2_V3,   ARC_INSN_SUBCLASS_NONE, fpu_ctrl)
+DEF (0x301,  ARC_OPCODE_V2_V3,   ARC_INSN_SUBCLASS_NONE, fpu_status)
+DEF (0xC8,  ARC_OPCODE_V2_V3,   ARC_INSN_SUBCLASS_NONE, fpu_build)
diff --git a/target/arc/semfunc-helper.c b/target/arc/semfunc-helper.c
index f55cb536d8b..9e06c496077 100644
--- a/target/arc/semfunc-helper.c
+++ b/target/arc/semfunc-helper.c
@@ -22,6 +22,7 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 #include "qemu/bitops.h"
+#include "tcg/tcg-temp-internal.h"
 #include "tcg/tcg.h"
 #include "semfunc-helper.h"
 #include "translate.h"
diff --git a/target/arc/semfunc-helper.h b/target/arc/semfunc-helper.h
index 794f4bf535a..15ec538934e 100644
--- a/target/arc/semfunc-helper.h
+++ b/target/arc/semfunc-helper.h
@@ -117,7 +117,7 @@ void arc_gen_set_debug(const DisasCtxt *ctx, bool value);
 #define setNFlag32(ELEM)  tcg_gen_shri_tl(cpu_Nf, ELEM, 31)
 #endif
 #define setNFlagByNum(ELEM, N) { \
-    TCGv _tmp = tcg_temp_local_new(); \
+    TCGv _tmp = tcg_temp_new(); \
     tcg_gen_shri_tl(_tmp, ELEM, (N - 1)); \
     tcg_gen_andi_tl(cpu_Nf, _tmp, 1); \
     tcg_temp_free(_tmp); \
@@ -131,7 +131,7 @@ void arc_gen_set_debug(const DisasCtxt *ctx, bool value);
 #define setZFlag(ELEM)  \
     tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, ELEM, 0);
 #define setZFlagByNum(ELEM, N) { \
-    TCGv _tmp = tcg_temp_local_new(); \
+    TCGv _tmp = tcg_temp_new(); \
     tcg_gen_andi_tl(_tmp, cpu_Zf, (1 << N) - 1); \
     tcg_gen_setcondi_tl(TCG_COND_EQ, _tmp, ELEM, 0); \
     tcg_temp_free(_tmp); \
@@ -243,7 +243,7 @@ void arc_gen_get_bit(TCGv ret, TCGv a, TCGv pos);
     do {                                                          \
         tcg_gen_movi_tl(cpu_pc, ctx->cpc);                        \
         gen_helper_leave(cpu_env, U7);                            \
-        TCGv jump_to_blink = tcg_temp_local_new();                \
+        TCGv jump_to_blink = tcg_temp_new();                \
         TCGLabel *done = gen_new_label();                         \
         tcg_gen_shri_tl(jump_to_blink, U7, 6);                    \
         tcg_gen_brcondi_tl(TCG_COND_EQ, jump_to_blink, 0, done);  \
diff --git a/target/arc/semfunc-v2.c b/target/arc/semfunc-v2.c
index 61d9530198c..dcf2238a601 100644
--- a/target/arc/semfunc-v2.c
+++ b/target/arc/semfunc-v2.c
@@ -22,7 +22,7 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 #include "target/arc/semfunc.h"
-#include "exec/gen-icount.h"
+#include "tcg/tcg-temp-internal.h"
 #include "tcg/tcg-op-gvec.h"
 
 /**
@@ -175,36 +175,36 @@ int
 arc_gen_FLAG(DisasCtxt *ctx, TCGv src)
 {
     int ret = DISAS_UPDATE;
-    TCGv temp_13 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_14 = tcg_temp_local_new();
-    TCGv status32 = tcg_temp_local_new();
-    TCGv temp_16 = tcg_temp_local_new();
-    TCGv temp_15 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_18 = tcg_temp_local_new();
-    TCGv temp_17 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_19 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_20 = tcg_temp_local_new();
-    TCGv temp_22 = tcg_temp_local_new();
-    TCGv temp_21 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_23 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
-    TCGv temp_12 = tcg_temp_local_new();
-    TCGv temp_24 = tcg_temp_local_new();
-    TCGv temp_25 = tcg_temp_local_new();
-    TCGv temp_26 = tcg_temp_local_new();
-    TCGv temp_27 = tcg_temp_local_new();
-    TCGv temp_28 = tcg_temp_local_new();
+    TCGv temp_13 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_14 = tcg_temp_new();
+    TCGv status32 = tcg_temp_new();
+    TCGv temp_16 = tcg_temp_new();
+    TCGv temp_15 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_18 = tcg_temp_new();
+    TCGv temp_17 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_19 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_20 = tcg_temp_new();
+    TCGv temp_22 = tcg_temp_new();
+    TCGv temp_21 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_23 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
+    TCGv temp_12 = tcg_temp_new();
+    TCGv temp_24 = tcg_temp_new();
+    TCGv temp_25 = tcg_temp_new();
+    TCGv temp_26 = tcg_temp_new();
+    TCGv temp_27 = tcg_temp_new();
+    TCGv temp_28 = tcg_temp_new();
     getCCFlag(temp_13);
     tcg_gen_mov_tl(cc_flag, temp_13);
     TCGLabel *done_1 = gen_new_label();
@@ -355,38 +355,38 @@ int
 arc_gen_KFLAG(DisasCtxt *ctx, TCGv src)
 {
     int ret = DISAS_UPDATE;
-    TCGv temp_13 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_14 = tcg_temp_local_new();
-    TCGv status32 = tcg_temp_local_new();
-    TCGv temp_16 = tcg_temp_local_new();
-    TCGv temp_15 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_18 = tcg_temp_local_new();
-    TCGv temp_17 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_19 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_20 = tcg_temp_local_new();
-    TCGv temp_22 = tcg_temp_local_new();
-    TCGv temp_21 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_23 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
-    TCGv temp_12 = tcg_temp_local_new();
-    TCGv temp_24 = tcg_temp_local_new();
-    TCGv temp_25 = tcg_temp_local_new();
-    TCGv temp_26 = tcg_temp_local_new();
-    TCGv temp_27 = tcg_temp_local_new();
-    TCGv temp_28 = tcg_temp_local_new();
-    TCGv temp_29 = tcg_temp_local_new();
-    TCGv temp_30 = tcg_temp_local_new();
+    TCGv temp_13 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_14 = tcg_temp_new();
+    TCGv status32 = tcg_temp_new();
+    TCGv temp_16 = tcg_temp_new();
+    TCGv temp_15 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_18 = tcg_temp_new();
+    TCGv temp_17 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_19 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_20 = tcg_temp_new();
+    TCGv temp_22 = tcg_temp_new();
+    TCGv temp_21 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_23 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
+    TCGv temp_12 = tcg_temp_new();
+    TCGv temp_24 = tcg_temp_new();
+    TCGv temp_25 = tcg_temp_new();
+    TCGv temp_26 = tcg_temp_new();
+    TCGv temp_27 = tcg_temp_new();
+    TCGv temp_28 = tcg_temp_new();
+    TCGv temp_29 = tcg_temp_new();
+    TCGv temp_30 = tcg_temp_new();
     getCCFlag(temp_13);
     tcg_gen_mov_tl(cc_flag, temp_13);
     TCGLabel *done_1 = gen_new_label();
@@ -606,16 +606,16 @@ int
 arc_gen_ADD1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -680,16 +680,16 @@ int
 arc_gen_ADD2(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -754,16 +754,16 @@ int
 arc_gen_ADD3(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -830,19 +830,19 @@ int
 arc_gen_ADC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -917,19 +917,19 @@ int
 arc_gen_SBC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -1002,17 +1002,17 @@ int
 arc_gen_NEG(DisasCtxt *ctx, TCGv b, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -1081,16 +1081,16 @@ int
 arc_gen_SUB(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -1157,16 +1157,16 @@ int
 arc_gen_SUB1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -1233,16 +1233,16 @@ int
 arc_gen_SUB2(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -1309,16 +1309,16 @@ int
 arc_gen_SUB3(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -1393,19 +1393,19 @@ int
 arc_gen_MAX(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv alu = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv alu = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     tcg_gen_mov_tl(lb, b);
@@ -1494,19 +1494,19 @@ int
 arc_gen_MIN(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv alu = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv alu = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     tcg_gen_mov_tl(lb, b);
@@ -1581,15 +1581,15 @@ int
 arc_gen_CMP(DisasCtxt *ctx, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv alu = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv alu = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -1646,11 +1646,11 @@ int
 arc_gen_AND(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -1702,11 +1702,11 @@ int
 arc_gen_OR(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -1758,11 +1758,11 @@ int
 arc_gen_XOR(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -1814,11 +1814,11 @@ int
 arc_gen_MOV(DisasCtxt *ctx, TCGv a, TCGv b)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -1894,32 +1894,32 @@ int
 arc_gen_ASL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_13 = tcg_temp_local_new();
-    TCGv temp_12 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_15 = tcg_temp_local_new();
-    TCGv temp_14 = tcg_temp_local_new();
-    TCGv t1 = tcg_temp_local_new();
-    TCGv temp_17 = tcg_temp_local_new();
-    TCGv temp_16 = tcg_temp_local_new();
-    TCGv t2 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_18 = tcg_temp_local_new();
-    TCGv temp_19 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_13 = tcg_temp_new();
+    TCGv temp_12 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_15 = tcg_temp_new();
+    TCGv temp_14 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv temp_17 = tcg_temp_new();
+    TCGv temp_16 = tcg_temp_new();
+    TCGv t2 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_18 = tcg_temp_new();
+    TCGv temp_19 = tcg_temp_new();
     getCCFlag(temp_9);
     tcg_gen_mov_tl(cc_flag, temp_9);
     TCGLabel *done_1 = gen_new_label();
@@ -2043,21 +2043,21 @@ int
 arc_gen_ASR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     TCGLabel *done_1 = gen_new_label();
@@ -2136,14 +2136,14 @@ int
 arc_gen_ASR8(DisasCtxt *ctx, TCGv b, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2202,14 +2202,14 @@ int
 arc_gen_ASR16(DisasCtxt *ctx, TCGv b, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2267,13 +2267,13 @@ int
 arc_gen_LSL16(DisasCtxt *ctx, TCGv b, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2329,13 +2329,13 @@ int
 arc_gen_LSL8(DisasCtxt *ctx, TCGv b, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2402,21 +2402,21 @@ int
 arc_gen_LSR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     TCGLabel *done_1 = gen_new_label();
@@ -2494,13 +2494,13 @@ int
 arc_gen_LSR16(DisasCtxt *ctx, TCGv b, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2556,13 +2556,13 @@ int
 arc_gen_LSR8(DisasCtxt *ctx, TCGv b, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2618,12 +2618,12 @@ int
 arc_gen_BIC(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2678,14 +2678,14 @@ int
 arc_gen_BCLR(DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv tmp = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv tmp = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2752,17 +2752,17 @@ int
 arc_gen_BMSK(DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv tmp1 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv tmp2 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv tmp1 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv tmp2 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
@@ -2843,18 +2843,18 @@ int
 arc_gen_BMSKN(DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv tmp1 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv tmp2 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv tmp1 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv tmp2 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
@@ -2929,13 +2929,13 @@ int
 arc_gen_BSET(DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv tmp = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv tmp = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2992,12 +2992,12 @@ int
 arc_gen_BXOR(DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv tmp = tcg_temp_local_new();
-    TCGv la = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv tmp = tcg_temp_new();
+    TCGv la = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3053,18 +3053,18 @@ int
 arc_gen_ROL (DisasCtxt *ctx, TCGv src, TCGv n, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lsrc = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lsrc = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     int f_flag;
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -3128,13 +3128,13 @@ int
 arc_gen_ROL8(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lsrc = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lsrc = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3193,18 +3193,18 @@ int
 arc_gen_ROR(DisasCtxt *ctx, TCGv src, TCGv n, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lsrc = tcg_temp_local_new();
-    TCGv ln = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lsrc = tcg_temp_new();
+    TCGv ln = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     int f_flag;
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -3268,13 +3268,13 @@ int
 arc_gen_ROR8(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lsrc = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lsrc = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3333,18 +3333,18 @@ int
 arc_gen_RLC(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lsrc = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lsrc = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     int f_flag;
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -3412,19 +3412,19 @@ int
 arc_gen_RRC(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv lsrc = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv lsrc = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     int f_flag;
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -3490,13 +3490,13 @@ int
 arc_gen_SEXB(DisasCtxt *ctx, TCGv dest, TCGv src)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3551,13 +3551,13 @@ int
 arc_gen_SEXH(DisasCtxt *ctx, TCGv dest, TCGv src)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3612,10 +3612,10 @@ int
 arc_gen_EXTB(DisasCtxt *ctx, TCGv dest, TCGv src)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3664,10 +3664,10 @@ int
 arc_gen_EXTH(DisasCtxt *ctx, TCGv dest, TCGv src)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
     int f_flag;
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3713,13 +3713,13 @@ int
 arc_gen_BTST(DisasCtxt *ctx, TCGv c, TCGv b)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv tmp = tcg_temp_local_new();
-    TCGv alu = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv tmp = tcg_temp_new();
+    TCGv alu = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -3765,11 +3765,11 @@ int
 arc_gen_TST(DisasCtxt *ctx, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv alu = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv alu = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -3817,22 +3817,22 @@ int
 arc_gen_XBFU(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv N = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv M = tcg_temp_local_new();
-    TCGv tmp1 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
-    TCGv tmp2 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv N = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv M = tcg_temp_new();
+    TCGv tmp1 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
+    TCGv tmp2 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -3898,12 +3898,12 @@ int
 arc_gen_AEX(DisasCtxt *ctx, TCGv src2, TCGv b)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv tmp = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv tmp = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -3942,11 +3942,9 @@ arc_gen_LR(DisasCtxt *ctx, TCGv dest, TCGv src)
 {
     int ret = DISAS_NORETURN;
 
-    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-        gen_io_start();
-    }
+    translator_io_start(&ctx->base);
 
-    TCGv temp_1 = tcg_temp_local_new();
+    TCGv temp_1 = tcg_temp_new();
     readAuxReg(temp_1, src);
     tcg_gen_mov_tl(dest, temp_1);
     tcg_temp_free(temp_1);
@@ -4051,7 +4049,7 @@ arc_gen_SETI(DisasCtxt *ctx, TCGv c)
     arc_gen_excp(ctx, EXCP_PRIVILEGEV, 0, 0);
 
     gen_set_label(cont);
-    one      = tcg_const_tl(1);
+    one      = tcg_constant_tl(1);
     c_4      = tcg_temp_new();
     c_5      = tcg_temp_new();
     ie       = tcg_temp_new();
@@ -4194,17 +4192,17 @@ int
 arc_gen_MPY(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv _b = tcg_temp_local_new();
-    TCGv _c = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv high_part = tcg_temp_local_new();
-    TCGv tmp1 = tcg_temp_local_new();
-    TCGv tmp2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv _b = tcg_temp_new();
+    TCGv _c = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv high_part = tcg_temp_new();
+    TCGv tmp1 = tcg_temp_new();
+    TCGv tmp2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -4265,12 +4263,12 @@ int
 arc_gen_MPYMU(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -4322,11 +4320,11 @@ int
 arc_gen_MPYM(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -4379,16 +4377,16 @@ int
 arc_gen_MPYU(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv _b = tcg_temp_local_new();
-    TCGv _c = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv high_part = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv _b = tcg_temp_new();
+    TCGv _c = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv high_part = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -4448,14 +4446,14 @@ int
 arc_gen_MPYUW(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -4513,19 +4511,19 @@ int
 arc_gen_MPYW(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_12 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_12 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -4597,18 +4595,18 @@ int
 arc_gen_DIV(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
     getCCFlag(temp_9);
     tcg_gen_mov_tl(cc_flag, temp_9);
     TCGLabel *done_1 = gen_new_label();
@@ -4686,15 +4684,15 @@ int
 arc_gen_DIVU(DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     TCGLabel *done_1 = gen_new_label();
@@ -4766,18 +4764,18 @@ int
 arc_gen_REM(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
     getCCFlag(temp_9);
     tcg_gen_mov_tl(cc_flag, temp_9);
     TCGLabel *done_1 = gen_new_label();
@@ -4855,15 +4853,15 @@ int
 arc_gen_REMU(DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     TCGLabel *done_1 = gen_new_label();
@@ -4934,21 +4932,21 @@ int
 arc_gen_MAC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv old_acchi = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv high_mul = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv new_acchi = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv old_acchi = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv high_mul = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv new_acchi = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     TCGLabel *done_1 = gen_new_label();
@@ -5025,21 +5023,21 @@ int
 arc_gen_MACU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv old_acchi = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv high_mul = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv new_acchi = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv old_acchi = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv high_mul = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv new_acchi = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     TCGLabel *done_1 = gen_new_label();
@@ -5119,23 +5117,23 @@ int
 arc_gen_MACD(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv old_acchi = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv high_mul = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv old_acchi = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv high_mul = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
     TCGv pair = NULL;
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv new_acchi = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_12 = tcg_temp_local_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv new_acchi = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_12 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     TCGLabel *done_1 = gen_new_label();
@@ -5219,23 +5217,23 @@ int
 arc_gen_MACDU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv old_acchi = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv high_mul = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv old_acchi = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv high_mul = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
     TCGv pair = NULL;
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv new_acchi = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_12 = tcg_temp_local_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv new_acchi = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_12 = tcg_temp_new();
     getCCFlag(temp_5);
     tcg_gen_mov_tl(cc_flag, temp_5);
     TCGLabel *done_1 = gen_new_label();
@@ -5318,13 +5316,13 @@ int
 arc_gen_ABS(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv lsrc = tcg_temp_local_new();
-    TCGv alu = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
+    TCGv lsrc = tcg_temp_new();
+    TCGv alu = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
     tcg_gen_mov_tl(lsrc, src);
     tcg_gen_subfi_tl(alu, 0, lsrc);
     TCGLabel *else_1 = gen_new_label();
@@ -5381,9 +5379,9 @@ int
 arc_gen_SWAP(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv tmp1 = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv tmp2 = tcg_temp_local_new();
+    TCGv tmp1 = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv tmp2 = tcg_temp_new();
     int f_flag;
     tcg_gen_shli_tl(tmp1, src, 16);
     tcg_gen_shri_tl(temp_1, src, 16);
@@ -5426,16 +5424,16 @@ int
 arc_gen_SWAPE(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv tmp1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv tmp2 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv tmp3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv tmp4 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv tmp1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv tmp2 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv tmp3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv tmp4 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
     int f_flag;
     tcg_gen_shli_tl(temp_1, src, 24);
     tcg_gen_andi_tl(tmp1, temp_1, 4278190080);
@@ -5513,10 +5511,10 @@ int
 arc_gen_BI(DisasCtxt *ctx, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
     tcg_gen_shli_tl(temp_4, c, 2);
     nextInsnAddress(temp_3);
     tcg_gen_mov_tl(temp_2, temp_3);
@@ -5539,8 +5537,8 @@ arc_gen_BI(DisasCtxt *ctx, TCGv c)
 int
 arc_gen_BIH(DisasCtxt *ctx, TCGv c)
 {
-    TCGv target = tcg_temp_local_new();
-    TCGv addendum = tcg_temp_local_new();
+    TCGv target = tcg_temp_new();
+    TCGv addendum = tcg_temp_new();
 
     tcg_gen_movi_tl(target, ctx->npc);
     tcg_gen_shli_tl(addendum, c, 1);
@@ -5567,7 +5565,7 @@ arc_gen_B(DisasCtxt *ctx, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[0].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -5627,7 +5625,7 @@ arc_gen_BBIT0(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
     TCGv _c = tcg_temp_new();
-    TCGv msk = tcg_const_tl(1);
+    TCGv msk = tcg_constant_tl(1);
     TCGv bit = tcg_temp_new();
 
     update_delay_flag(ctx);
@@ -5666,7 +5664,7 @@ arc_gen_BBIT1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
     TCGv _c = tcg_temp_new();
-    TCGv msk = tcg_const_tl(1);
+    TCGv msk = tcg_constant_tl(1);
     TCGv bit = tcg_temp_new();
 
     update_delay_flag(ctx);
@@ -5709,7 +5707,7 @@ arc_gen_BL(DisasCtxt *ctx, TCGv offset ATTRIBUTE_UNUSED)
     const target_ulong target = ctx->pcl + ctx->insn.operands[0].value;
     target_ulong save_addr = ctx->npc;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -5752,7 +5750,7 @@ int
 arc_gen_J(DisasCtxt *ctx, TCGv target)
 {
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -5788,7 +5786,7 @@ arc_gen_JL(DisasCtxt *ctx, TCGv target)
     target_ulong save_addr = ctx->npc;
     TCGLabel *do_not_branch = gen_new_label();
     TCGv _target = tcg_temp_new();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -5863,17 +5861,17 @@ int
 arc_gen_SETEQ(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv p_b = tcg_temp_local_new();
-    TCGv p_c = tcg_temp_local_new();
-    TCGv take_branch = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv p_b = tcg_temp_new();
+    TCGv p_c = tcg_temp_new();
+    TCGv take_branch = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_7);
     tcg_gen_mov_tl(cc_flag, temp_7);
     TCGLabel *done_1 = gen_new_label();
@@ -5934,7 +5932,7 @@ arc_gen_BREQ(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -5983,17 +5981,17 @@ int
 arc_gen_SETNE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv p_b = tcg_temp_local_new();
-    TCGv p_c = tcg_temp_local_new();
-    TCGv take_branch = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv p_b = tcg_temp_new();
+    TCGv p_c = tcg_temp_new();
+    TCGv take_branch = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_7);
     tcg_gen_mov_tl(cc_flag, temp_7);
     TCGLabel *done_1 = gen_new_label();
@@ -6054,7 +6052,7 @@ arc_gen_BRNE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6103,17 +6101,17 @@ int
 arc_gen_SETLT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv p_b = tcg_temp_local_new();
-    TCGv p_c = tcg_temp_local_new();
-    TCGv take_branch = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv p_b = tcg_temp_new();
+    TCGv p_c = tcg_temp_new();
+    TCGv take_branch = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_7);
     tcg_gen_mov_tl(cc_flag, temp_7);
     TCGLabel *done_1 = gen_new_label();
@@ -6175,7 +6173,7 @@ arc_gen_BRLT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6224,17 +6222,17 @@ int
 arc_gen_SETGE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv p_b = tcg_temp_local_new();
-    TCGv p_c = tcg_temp_local_new();
-    TCGv take_branch = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv p_b = tcg_temp_new();
+    TCGv p_c = tcg_temp_new();
+    TCGv take_branch = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_7);
     tcg_gen_mov_tl(cc_flag, temp_7);
     TCGLabel *done_1 = gen_new_label();
@@ -6295,7 +6293,7 @@ arc_gen_BRGE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6344,17 +6342,17 @@ int
 arc_gen_SETLE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv p_b = tcg_temp_local_new();
-    TCGv p_c = tcg_temp_local_new();
-    TCGv take_branch = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv p_b = tcg_temp_new();
+    TCGv p_c = tcg_temp_new();
+    TCGv take_branch = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_7);
     tcg_gen_mov_tl(cc_flag, temp_7);
     TCGLabel *done_1 = gen_new_label();
@@ -6436,17 +6434,17 @@ int
 arc_gen_SETGT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv p_b = tcg_temp_local_new();
-    TCGv p_c = tcg_temp_local_new();
-    TCGv take_branch = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv p_b = tcg_temp_new();
+    TCGv p_c = tcg_temp_new();
+    TCGv take_branch = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_7);
     tcg_gen_mov_tl(cc_flag, temp_7);
     TCGLabel *done_1 = gen_new_label();
@@ -6507,7 +6505,7 @@ arc_gen_BRLO(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6556,15 +6554,15 @@ int
 arc_gen_SETLO(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv p_b = tcg_temp_local_new();
-    TCGv p_c = tcg_temp_local_new();
-    TCGv take_branch = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv cc_temp_1 = tcg_temp_local_new();
+    TCGv p_b = tcg_temp_new();
+    TCGv p_c = tcg_temp_new();
+    TCGv take_branch = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv cc_temp_1 = tcg_temp_new();
     getCCFlag(cc_flag);
     TCGLabel *done_cc = gen_new_label();
     tcg_gen_setcond_tl(TCG_COND_EQ, cc_temp_1, cc_flag, arc_true);
@@ -6621,7 +6619,7 @@ arc_gen_BRHS(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6670,15 +6668,15 @@ int
 arc_gen_SETHS(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv p_b = tcg_temp_local_new();
-    TCGv p_c = tcg_temp_local_new();
-    TCGv take_branch = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv cc_temp_1 = tcg_temp_local_new();
+    TCGv p_b = tcg_temp_new();
+    TCGv p_c = tcg_temp_new();
+    TCGv take_branch = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv cc_temp_1 = tcg_temp_new();
     getCCFlag(cc_flag);
     TCGLabel *done_cc = gen_new_label();
     tcg_gen_setcond_tl(TCG_COND_EQ, cc_temp_1, cc_flag, arc_true);
@@ -6730,7 +6728,7 @@ int
 arc_gen_EX (DisasCtxt *ctx, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp = tcg_temp_local_new();
+  TCGv temp = tcg_temp_new();
   tcg_gen_mov_tl(temp, b);
   tcg_gen_atomic_xchg_tl(b, c, temp, ctx->mem_idx, MO_UL);
   tcg_temp_free(temp);
@@ -6775,8 +6773,8 @@ arc_gen_LLOCKD(DisasCtxt *ctx, TCGv dest, TCGv src)
     int ret = DISAS_NEXT;
     TCGv pair = nextReg (dest);
 
-    TCGv_i64 temp_1 = tcg_temp_local_new_i64();
-    TCGv_i64 temp_2 = tcg_temp_local_new_i64();
+    TCGv_i64 temp_1 = tcg_temp_new_i64();
+    TCGv_i64 temp_2 = tcg_temp_new_i64();
 
 #ifndef ARM_LIKE_LLOCK_SCOND
     gen_helper_llockd(temp_1, cpu_env, src);
@@ -6810,7 +6808,7 @@ arc_gen_SCOND(DisasCtxt *ctx, TCGv addr, TCGv value)
 {
     int ret = DISAS_NEXT;
 #ifndef ARM_LIKE_LLOCK_SCOND
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_4 = tcg_temp_new();
     gen_helper_scond(temp_4, cpu_env, addr, value);
     setZFlag(temp_4);
     tcg_temp_free(temp_4);
@@ -6853,12 +6851,12 @@ arc_gen_SCONDD(DisasCtxt *ctx, TCGv addr, TCGv value)
     TCGv pair = NULL;
     pair = nextReg (value);
 
-    TCGv_i64 temp_1 = tcg_temp_local_new_i64();
-    TCGv_i64 temp_2 = tcg_temp_local_new_i64();
+    TCGv_i64 temp_1 = tcg_temp_new_i64();
+    TCGv_i64 temp_2 = tcg_temp_new_i64();
 
-    TCGv_i64 temp_3 = tcg_temp_local_new_i64();
-    TCGv_i64 temp_4 = tcg_temp_local_new_i64();
-    TCGv_i64 exclusive_val = tcg_temp_local_new_i64();
+    TCGv_i64 temp_3 = tcg_temp_new_i64();
+    TCGv_i64 temp_4 = tcg_temp_new_i64();
+    TCGv_i64 exclusive_val = tcg_temp_new_i64();
 
     tcg_gen_ext_i32_i64(temp_1, pair);
     tcg_gen_extu_i32_i64(temp_2, value);
@@ -6866,7 +6864,7 @@ arc_gen_SCONDD(DisasCtxt *ctx, TCGv addr, TCGv value)
     tcg_gen_or_i64(temp_1, temp_1, temp_2);
 
 #ifndef ARM_LIKE_LLOCK_SCOND
-    TCGv temp_5 = tcg_temp_local_new();
+    TCGv temp_5 = tcg_temp_new();
     gen_helper_scondd(temp_5, cpu_env, addr, temp_1);
     setZFlag(temp_5);
     tcg_temp_free(temp_5);
@@ -7310,21 +7308,21 @@ int
 arc_gen_LP(DisasCtxt *ctx, TCGv rd)
 {
     int ret = DISAS_NORETURN;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv lp_start_index = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv lp_end_index = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_10 = tcg_temp_local_new();
-    TCGv temp_9 = tcg_temp_local_new();
-    TCGv temp_8 = tcg_temp_local_new();
-    TCGv temp_13 = tcg_temp_local_new();
-    TCGv temp_12 = tcg_temp_local_new();
-    TCGv temp_11 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv lp_start_index = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv lp_end_index = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_10 = tcg_temp_new();
+    TCGv temp_9 = tcg_temp_new();
+    TCGv temp_8 = tcg_temp_new();
+    TCGv temp_13 = tcg_temp_new();
+    TCGv temp_12 = tcg_temp_new();
+    TCGv temp_11 = tcg_temp_new();
     TCGLabel *else_1 = gen_new_label();
     TCGLabel *done_1 = gen_new_label();
     getCCFlag(temp_3);
@@ -7390,7 +7388,7 @@ int
 arc_gen_NORM(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
     tcg_gen_mov_tl(psrc, src);
     tcg_gen_clrsb_tl(dest, psrc);
     if ((getFFlag () == true)) {
@@ -7425,7 +7423,7 @@ int
 arc_gen_NORMH(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
     tcg_gen_andi_tl(psrc, src, 65535);
     tcg_gen_ext16s_tl(psrc, psrc);
     tcg_gen_clrsb_tl(dest, psrc);
@@ -7467,12 +7465,12 @@ int
 arc_gen_FLS(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
     tcg_gen_mov_tl(psrc, src);
     TCGLabel *else_1 = gen_new_label();
     TCGLabel *done_1 = gen_new_label();
@@ -7530,11 +7528,11 @@ int
 arc_gen_FFS(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
     tcg_gen_mov_tl(psrc, src);
     TCGLabel *else_1 = gen_new_label();
     TCGLabel *done_1 = gen_new_label();
@@ -7663,7 +7661,7 @@ arc_gen_vmac2h_i32(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c,
 int
 arc_gen_VMAC2H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 {
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   getCCFlag(cc_temp);
@@ -7680,7 +7678,7 @@ arc_gen_VMAC2H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 int
 arc_gen_VMAC2HU(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 {
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   getCCFlag(cc_temp);
@@ -7882,7 +7880,7 @@ VEC_VADDSUB_VSUBADD_OP(vsubadd4h, H0_H2_I64, add16, i64)
 int
 arc_gen_VADDSUB(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 {
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   getCCFlag(cc_temp);
@@ -7900,7 +7898,7 @@ arc_gen_VADDSUB(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 int
 arc_gen_VADDSUB2H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 {
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   getCCFlag(cc_temp);
@@ -7917,7 +7915,7 @@ arc_gen_VADDSUB2H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 int
 arc_gen_VADDSUB4H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 {
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   getCCFlag(cc_temp);
@@ -7939,7 +7937,7 @@ arc_gen_VADDSUB4H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 int
 arc_gen_VSUBADD(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 {
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   getCCFlag(cc_temp);
@@ -7957,7 +7955,7 @@ arc_gen_VSUBADD(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 int
 arc_gen_VSUBADD2H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 {
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   getCCFlag(cc_temp);
@@ -7974,7 +7972,7 @@ arc_gen_VSUBADD2H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 int
 arc_gen_VSUBADD4H(DisasCtxt *ctx, TCGv dest, TCGv b, TCGv c)
 {
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   getCCFlag(cc_temp);
diff --git a/target/arc/semfunc-v3.c b/target/arc/semfunc-v3.c
index 854f8506b4d..c0cdcec1651 100644
--- a/target/arc/semfunc-v3.c
+++ b/target/arc/semfunc-v3.c
@@ -72,36 +72,36 @@ int
 arc_gen_FLAG (DisasCtxt *ctx, TCGv src)
 {
   int ret = DISAS_UPDATE;
-  TCGv temp_13 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_14 = tcg_temp_local_new();
-  TCGv status32 = tcg_temp_local_new();
-  TCGv temp_16 = tcg_temp_local_new();
-  TCGv temp_15 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_18 = tcg_temp_local_new();
-  TCGv temp_17 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_19 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_20 = tcg_temp_local_new();
-  TCGv temp_22 = tcg_temp_local_new();
-  TCGv temp_21 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_23 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_12 = tcg_temp_local_new();
-  TCGv temp_24 = tcg_temp_local_new();
-  TCGv temp_25 = tcg_temp_local_new();
-  TCGv temp_26 = tcg_temp_local_new();
-  TCGv temp_27 = tcg_temp_local_new();
-  TCGv temp_28 = tcg_temp_local_new();
+  TCGv temp_13 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_14 = tcg_temp_new();
+  TCGv status32 = tcg_temp_new();
+  TCGv temp_16 = tcg_temp_new();
+  TCGv temp_15 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_18 = tcg_temp_new();
+  TCGv temp_17 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_19 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_20 = tcg_temp_new();
+  TCGv temp_22 = tcg_temp_new();
+  TCGv temp_21 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_23 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_12 = tcg_temp_new();
+  TCGv temp_24 = tcg_temp_new();
+  TCGv temp_25 = tcg_temp_new();
+  TCGv temp_26 = tcg_temp_new();
+  TCGv temp_27 = tcg_temp_new();
+  TCGv temp_28 = tcg_temp_new();
   getCCFlag(temp_13);
   tcg_gen_mov_tl(cc_flag, temp_13);
   TCGLabel *done_1 = gen_new_label();
@@ -267,38 +267,38 @@ int
 arc_gen_KFLAG (DisasCtxt *ctx, TCGv src)
 {
   int ret = DISAS_UPDATE;
-  TCGv temp_13 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_14 = tcg_temp_local_new();
-  TCGv status32 = tcg_temp_local_new();
-  TCGv temp_16 = tcg_temp_local_new();
-  TCGv temp_15 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_18 = tcg_temp_local_new();
-  TCGv temp_17 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_19 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_20 = tcg_temp_local_new();
-  TCGv temp_22 = tcg_temp_local_new();
-  TCGv temp_21 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_23 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_12 = tcg_temp_local_new();
-  TCGv temp_24 = tcg_temp_local_new();
-  TCGv temp_25 = tcg_temp_local_new();
-  TCGv temp_26 = tcg_temp_local_new();
-  TCGv temp_27 = tcg_temp_local_new();
-  TCGv temp_28 = tcg_temp_local_new();
-  TCGv temp_29 = tcg_temp_local_new();
-  TCGv temp_30 = tcg_temp_local_new();
+  TCGv temp_13 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_14 = tcg_temp_new();
+  TCGv status32 = tcg_temp_new();
+  TCGv temp_16 = tcg_temp_new();
+  TCGv temp_15 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_18 = tcg_temp_new();
+  TCGv temp_17 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_19 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_20 = tcg_temp_new();
+  TCGv temp_22 = tcg_temp_new();
+  TCGv temp_21 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_23 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_12 = tcg_temp_new();
+  TCGv temp_24 = tcg_temp_new();
+  TCGv temp_25 = tcg_temp_new();
+  TCGv temp_26 = tcg_temp_new();
+  TCGv temp_27 = tcg_temp_new();
+  TCGv temp_28 = tcg_temp_new();
+  TCGv temp_29 = tcg_temp_new();
+  TCGv temp_30 = tcg_temp_new();
   getCCFlag(temp_13);
   tcg_gen_mov_tl(cc_flag, temp_13);
   TCGLabel *done_1 = gen_new_label();
@@ -448,19 +448,19 @@ int
 arc_gen_ADD (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   se32to64(temp_4, b);
@@ -539,16 +539,16 @@ int
 arc_gen_ADD1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     se32to64(lb, b);
@@ -614,16 +614,16 @@ int
 arc_gen_ADD2(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     se32to64(lb, b);
@@ -690,16 +690,16 @@ int
 arc_gen_ADD3(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     se32to64(lb, b);
@@ -769,21 +769,21 @@ int
 arc_gen_ADC (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_12 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_12 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   se32to64(temp_4, b);
@@ -868,21 +868,21 @@ int
 arc_gen_SBC (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_12 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_12 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   se32to64(temp_4, b);
@@ -965,18 +965,18 @@ int
 arc_gen_NEG (DisasCtxt *ctx, TCGv b, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   se32to64(temp_4, b);
@@ -1053,19 +1053,19 @@ int
 arc_gen_SUB (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   se32to64(temp_4, b);
@@ -1144,20 +1144,20 @@ int
 arc_gen_SUB1 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   se32to64(temp_4, b);
@@ -1238,20 +1238,20 @@ int
 arc_gen_SUB2 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   se32to64(temp_4, b);
@@ -1332,20 +1332,20 @@ int
 arc_gen_SUB3 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   se32to64(temp_4, b);
@@ -1434,21 +1434,21 @@ int
 arc_gen_MAX (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   se32to64(temp_6, b);
@@ -1546,21 +1546,21 @@ int
 arc_gen_MIN (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   se32to64(temp_6, b);
@@ -1648,18 +1648,18 @@ int
 arc_gen_CMP (DisasCtxt *ctx, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv v = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv v = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -1724,10 +1724,10 @@ int
 arc_gen_AND (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -1785,10 +1785,10 @@ int
 arc_gen_OR (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -1846,10 +1846,10 @@ int
 arc_gen_XOR (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -1907,10 +1907,10 @@ int
 arc_gen_MOV (DisasCtxt *ctx, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -1993,32 +1993,32 @@ int
 arc_gen_ASL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv la = tcg_temp_local_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv la = tcg_temp_new();
   int f_flag;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_13 = tcg_temp_local_new();
-  TCGv temp_12 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_15 = tcg_temp_local_new();
-  TCGv temp_14 = tcg_temp_local_new();
-  TCGv t1 = tcg_temp_local_new();
-  TCGv temp_17 = tcg_temp_local_new();
-  TCGv temp_16 = tcg_temp_local_new();
-  TCGv t2 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_18 = tcg_temp_local_new();
-  TCGv temp_19 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_13 = tcg_temp_new();
+  TCGv temp_12 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_15 = tcg_temp_new();
+  TCGv temp_14 = tcg_temp_new();
+  TCGv t1 = tcg_temp_new();
+  TCGv temp_17 = tcg_temp_new();
+  TCGv temp_16 = tcg_temp_new();
+  TCGv t2 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_18 = tcg_temp_new();
+  TCGv temp_19 = tcg_temp_new();
   getCCFlag(temp_9);
   tcg_gen_mov_tl(cc_flag, temp_9);
   TCGLabel *done_1 = gen_new_label();
@@ -2147,20 +2147,20 @@ int
 arc_gen_ASR (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   int f_flag;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -2244,13 +2244,13 @@ int
 arc_gen_ASR8 (DisasCtxt *ctx, TCGv b, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2315,13 +2315,13 @@ int
 arc_gen_ASR16 (DisasCtxt *ctx, TCGv b, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2386,13 +2386,13 @@ int
 arc_gen_LSL16 (DisasCtxt *ctx, TCGv b, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2457,13 +2457,13 @@ int
 arc_gen_LSL8 (DisasCtxt *ctx, TCGv b, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2537,20 +2537,20 @@ int
 arc_gen_LSR (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   int f_flag;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -2634,13 +2634,13 @@ int
 arc_gen_LSR16 (DisasCtxt *ctx, TCGv b, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2705,13 +2705,13 @@ int
 arc_gen_LSR8 (DisasCtxt *ctx, TCGv b, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2775,11 +2775,11 @@ int
 arc_gen_BIC (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2840,13 +2840,13 @@ int
 arc_gen_BCLR (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -2919,16 +2919,16 @@ int
 arc_gen_BMSK (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv tmp1 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp2 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv tmp1 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp2 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
@@ -3014,17 +3014,17 @@ int
 arc_gen_BMSKN (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv tmp1 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp2 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv tmp1 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp2 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
@@ -3104,12 +3104,12 @@ int
 arc_gen_BSET (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3172,11 +3172,11 @@ int
 arc_gen_BXOR (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3239,18 +3239,18 @@ int
 arc_gen_ROL (DisasCtxt *ctx, TCGv src, TCGv n, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv ln = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv ln = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -3323,13 +3323,13 @@ int
 arc_gen_ROL8 (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3396,18 +3396,18 @@ int
 arc_gen_ROR (DisasCtxt *ctx, TCGv src, TCGv n, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv ln = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv ln = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -3480,13 +3480,13 @@ int
 arc_gen_ROR8 (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3553,18 +3553,18 @@ int
 arc_gen_RLC (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -3640,19 +3640,19 @@ int
 arc_gen_RRC (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -3727,13 +3727,13 @@ int
 arc_gen_SEXB (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3797,13 +3797,13 @@ int
 arc_gen_SEXH (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3867,10 +3867,10 @@ int
 arc_gen_EXTB (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3928,10 +3928,10 @@ int
 arc_gen_EXTH (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -3986,13 +3986,13 @@ int
 arc_gen_BTST (DisasCtxt *ctx, TCGv c, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4041,11 +4041,11 @@ int
 arc_gen_TST (DisasCtxt *ctx, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4096,22 +4096,22 @@ int
 arc_gen_XBFU (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv N = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv M = tcg_temp_local_new();
-  TCGv tmp1 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv tmp2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv N = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv M = tcg_temp_new();
+  TCGv tmp1 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv tmp2 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4185,12 +4185,12 @@ int
 arc_gen_AEX (DisasCtxt *ctx, TCGv src2, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4230,11 +4230,9 @@ arc_gen_LR (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NORETURN;
 
-  if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-      gen_io_start();
-  }
+  translator_io_start(&ctx->base);
 
-  TCGv temp_1 = tcg_temp_local_new();
+  TCGv temp_1 = tcg_temp_new();
   readAuxReg(temp_1, src);
   tcg_gen_andi_tl(temp_1, temp_1, 0xffffffff);
   tcg_gen_mov_tl(dest, temp_1);
@@ -4340,7 +4338,7 @@ arc_gen_SETI(DisasCtxt *ctx, TCGv c)
     arc_gen_excp(ctx, EXCP_PRIVILEGEV, 0, 0);
 
     gen_set_label(cont);
-    one      = tcg_const_tl(1);
+    one      = tcg_constant_tl(1);
     c_4      = tcg_temp_new();
     c_5      = tcg_temp_new();
     ie       = tcg_temp_new();
@@ -4475,17 +4473,17 @@ int
 arc_gen_MPY(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv _b = tcg_temp_local_new();
-    TCGv _c = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv high_part = tcg_temp_local_new();
-    TCGv tmp1 = tcg_temp_local_new();
-    TCGv tmp2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv _b = tcg_temp_new();
+    TCGv _c = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv high_part = tcg_temp_new();
+    TCGv tmp1 = tcg_temp_new();
+    TCGv tmp2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     TCGLabel *done_1 = gen_new_label();
@@ -4551,12 +4549,12 @@ int
 arc_gen_MPYMU (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4617,11 +4615,11 @@ int
 arc_gen_MPYM (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4683,16 +4681,16 @@ int
 arc_gen_MPYU (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv _b = tcg_temp_local_new();
-  TCGv _c = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv high_part = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv _b = tcg_temp_new();
+  TCGv _c = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv high_part = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4761,14 +4759,14 @@ int
 arc_gen_MPYUW (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4833,19 +4831,19 @@ int
 arc_gen_MPYW (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_12 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_12 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -4925,18 +4923,18 @@ int
 arc_gen_DIV (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
   getCCFlag(temp_9);
   tcg_gen_mov_tl(cc_flag, temp_9);
   TCGLabel *done_1 = gen_new_label();
@@ -5019,15 +5017,15 @@ int
 arc_gen_DIVU (DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -5104,18 +5102,18 @@ int
 arc_gen_REM (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
   getCCFlag(temp_9);
   tcg_gen_mov_tl(cc_flag, temp_9);
   TCGLabel *done_1 = gen_new_label();
@@ -5198,15 +5196,15 @@ int
 arc_gen_REMU (DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -5283,7 +5281,7 @@ arc_gen_MAC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     TCGv old_acc, mul_bc;
 
-    TCGv cc_temp = tcg_temp_local_new();
+    TCGv cc_temp = tcg_temp_new();
     TCGLabel *cc_done = gen_new_label();
 
     /* Conditional execution */
@@ -5331,7 +5329,7 @@ arc_gen_MACU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     TCGv old_acc, mul_bc;
 
-    TCGv cc_temp = tcg_temp_local_new();
+    TCGv cc_temp = tcg_temp_new();
     TCGLabel *cc_done = gen_new_label();
 
     /* Conditional execution */
@@ -5377,7 +5375,7 @@ arc_gen_MACD(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     TCGv old_acc, mul_bc;
 
-    TCGv cc_temp = tcg_temp_local_new();
+    TCGv cc_temp = tcg_temp_new();
     TCGLabel *cc_done = gen_new_label();
 
     /* Conditional execution */
@@ -5425,7 +5423,7 @@ arc_gen_MACDU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     TCGv old_acc, mul_bc;
 
-    TCGv cc_temp = tcg_temp_local_new();
+    TCGv cc_temp = tcg_temp_new();
     TCGLabel *cc_done = gen_new_label();
 
     /* Conditional execution */
@@ -5492,14 +5490,14 @@ int
 arc_gen_ABS (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   se32to64(temp_3, src);
   tcg_gen_mov_tl(lsrc, temp_3);
   tcg_gen_subfi_tl(alu, 0, lsrc);
@@ -5567,9 +5565,9 @@ int
 arc_gen_SWAP (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv tmp1 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv tmp2 = tcg_temp_local_new();
+  TCGv tmp1 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv tmp2 = tcg_temp_new();
   int f_flag;
   tcg_gen_shli_tl(tmp1, src, 16);
   tcg_gen_shri_tl(temp_1, src, 16);
@@ -5622,16 +5620,16 @@ int
 arc_gen_SWAPE (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv tmp1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv tmp2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv tmp3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv tmp1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv tmp2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv tmp3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
   int f_flag;
   tcg_gen_shli_tl(temp_1, src, 24);
   tcg_gen_andi_tl(tmp1, temp_1, 4278190080);
@@ -5729,10 +5727,10 @@ int
 arc_gen_BI (DisasCtxt *ctx, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
   tcg_gen_shli_tl(temp_4, c, 2);
   nextInsnAddress(temp_3);
   tcg_gen_mov_tl(temp_2, temp_3);
@@ -5755,8 +5753,8 @@ arc_gen_BI (DisasCtxt *ctx, TCGv c)
 int
 arc_gen_BIH(DisasCtxt *ctx, TCGv c)
 {
-    TCGv target = tcg_temp_local_new();
-    TCGv addendum = tcg_temp_local_new();
+    TCGv target = tcg_temp_new();
+    TCGv addendum = tcg_temp_new();
 
     tcg_gen_movi_tl(target, ctx->npc);
     tcg_gen_shli_tl(addendum, c, 1);
@@ -5783,7 +5781,7 @@ arc_gen_B(DisasCtxt *ctx, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[0].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -5816,7 +5814,7 @@ arc_gen_BBIT0(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
     TCGv _c = tcg_temp_new();
-    TCGv msk = tcg_const_tl(1);
+    TCGv msk = tcg_constant_tl(1);
     TCGv bit = tcg_temp_new();
 
     update_delay_flag(ctx);
@@ -5855,7 +5853,7 @@ arc_gen_BBIT1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
     TCGv _c = tcg_temp_new();
-    TCGv msk = tcg_const_tl(1);
+    TCGv msk = tcg_constant_tl(1);
     TCGv bit = tcg_temp_new();
 
     update_delay_flag(ctx);
@@ -5898,7 +5896,7 @@ arc_gen_BL(DisasCtxt *ctx, TCGv offset ATTRIBUTE_UNUSED)
     target_ulong target;
     target_ulong save_addr = ctx->npc;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -5954,7 +5952,7 @@ int
 arc_gen_J(DisasCtxt *ctx, TCGv target)
 {
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -5990,7 +5988,7 @@ arc_gen_JL(DisasCtxt *ctx, TCGv target)
     target_ulong save_addr = ctx->npc;
     TCGLabel *do_not_branch = gen_new_label();
     TCGv _target = tcg_temp_new();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6066,19 +6064,19 @@ int
 arc_gen_SETEQ (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv take_branch = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv take_branch = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_7);
   tcg_gen_mov_tl(cc_flag, temp_7);
   TCGLabel *done_1 = gen_new_label();
@@ -6146,7 +6144,7 @@ arc_gen_BREQ(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     TCGLabel *do_not_branch = gen_new_label();
     TCGv b32 = tcg_temp_new();
     TCGv c32 = tcg_temp_new();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6202,19 +6200,19 @@ int
 arc_gen_SETNE (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv take_branch = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv take_branch = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_7);
   tcg_gen_mov_tl(cc_flag, temp_7);
   TCGLabel *done_1 = gen_new_label();
@@ -6282,7 +6280,7 @@ arc_gen_BRNE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     TCGLabel *do_not_branch = gen_new_label();
     TCGv b32 = tcg_temp_new();
     TCGv c32 = tcg_temp_new();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6337,19 +6335,19 @@ int
 arc_gen_SETLT (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv take_branch = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv take_branch = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_7);
   tcg_gen_mov_tl(cc_flag, temp_7);
   TCGLabel *done_1 = gen_new_label();
@@ -6418,7 +6416,7 @@ arc_gen_BRLT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     TCGLabel *do_not_branch = gen_new_label();
     TCGv b32 = tcg_temp_new();
     TCGv c32 = tcg_temp_new();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6472,19 +6470,19 @@ int
 arc_gen_SETGE (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv take_branch = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv take_branch = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_7);
   tcg_gen_mov_tl(cc_flag, temp_7);
   TCGLabel *done_1 = gen_new_label();
@@ -6552,7 +6550,7 @@ arc_gen_BRGE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     TCGLabel *do_not_branch = gen_new_label();
     TCGv b32 = tcg_temp_new();
     TCGv c32 = tcg_temp_new();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6607,19 +6605,19 @@ int
 arc_gen_SETLE (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv take_branch = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv take_branch = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_7);
   tcg_gen_mov_tl(cc_flag, temp_7);
   TCGLabel *done_1 = gen_new_label();
@@ -6708,19 +6706,19 @@ int
 arc_gen_SETGT (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv take_branch = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv take_branch = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_7);
   tcg_gen_mov_tl(cc_flag, temp_7);
   TCGLabel *done_1 = gen_new_label();
@@ -6787,7 +6785,7 @@ arc_gen_BRLO(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     TCGLabel *do_not_branch = gen_new_label();
     TCGv b32 = tcg_temp_new();
     TCGv c32 = tcg_temp_new();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6840,17 +6838,17 @@ int
 arc_gen_SETLO (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv take_branch = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv cc_temp_1 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv take_branch = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv cc_temp_1 = tcg_temp_new();
   getCCFlag(cc_flag);
   TCGLabel *done_cc = gen_new_label();
   tcg_gen_setcond_tl(TCG_COND_EQ, cc_temp_1, cc_flag, arc_true);
@@ -6913,7 +6911,7 @@ arc_gen_BRHS(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     TCGLabel *do_not_branch = gen_new_label();
     TCGv b32 = tcg_temp_new();
     TCGv c32 = tcg_temp_new();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -6966,17 +6964,17 @@ int
 arc_gen_SETHS (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv take_branch = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv cc_temp_1 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv take_branch = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv cc_temp_1 = tcg_temp_new();
   getCCFlag(cc_flag);
   TCGLabel *done_cc = gen_new_label();
   tcg_gen_setcond_tl(TCG_COND_EQ, cc_temp_1, cc_flag, arc_true);
@@ -7033,7 +7031,7 @@ int
 arc_gen_EX (DisasCtxt *ctx, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp = tcg_temp_local_new();
+  TCGv temp = tcg_temp_new();
   tcg_gen_mov_tl(temp, b);
   tcg_gen_atomic_xchg_tl(b, c, temp, ctx->mem_idx, MO_UL);
   tcg_temp_free(temp);
@@ -7095,7 +7093,7 @@ arc_gen_SCOND(DisasCtxt *ctx, TCGv addr, TCGv value)
 {
     int ret = DISAS_NEXT;
 #ifndef ARM_LIKE_LLOCK_SCOND
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_4 = tcg_temp_new();
     gen_helper_scond(temp_4, cpu_env, addr, value);
     setZFlag(temp_4);
     tcg_temp_free(temp_4);
@@ -7136,7 +7134,7 @@ arc_gen_SCONDL(DisasCtxt *ctx, TCGv addr, TCGv value)
 {
     int ret = DISAS_NEXT;
 #ifndef ARM_LIKE_LLOCK_SCOND
-    TCGv temp_4 = tcg_temp_local_new();
+    TCGv temp_4 = tcg_temp_new();
     gen_helper_scondl(temp_4, cpu_env, addr, value);
     setZFlag(temp_4);
     tcg_temp_free(temp_4);
@@ -7581,21 +7579,21 @@ int
 arc_gen_LP (DisasCtxt *ctx, TCGv rd)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv lp_start_index = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv lp_end_index = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_13 = tcg_temp_local_new();
-  TCGv temp_12 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv lp_start_index = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv lp_end_index = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_13 = tcg_temp_new();
+  TCGv temp_12 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
   TCGLabel *else_1 = gen_new_label();
   TCGLabel *done_1 = gen_new_label();
   getCCFlag(temp_3);
@@ -7663,7 +7661,7 @@ int
 arc_gen_NORM(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
     tcg_gen_mov_tl(psrc, src);
     tcg_gen_ext32s_tl(psrc, psrc);
     tcg_gen_clrsb_tl(dest, psrc);
@@ -7700,7 +7698,7 @@ int
 arc_gen_NORMH(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
     tcg_gen_andi_tl(psrc, src, 65535);
     tcg_gen_ext16s_tl(psrc, psrc);
     tcg_gen_clrsb_tl(dest, psrc);
@@ -7742,12 +7740,12 @@ int
 arc_gen_FLS(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
     tcg_gen_andi_tl(psrc, src, 0xffffffff);
     TCGLabel *else_1 = gen_new_label();
     TCGLabel *done_1 = gen_new_label();
@@ -7808,11 +7806,11 @@ int
 arc_gen_FFS(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
     tcg_gen_andi_tl(psrc, src, 0xffffffff);
     TCGLabel *else_1 = gen_new_label();
     TCGLabel *done_1 = gen_new_label();
@@ -7875,16 +7873,16 @@ int
 arc_gen_ADDL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   tcg_gen_mov_tl(lb, b);
@@ -7958,16 +7956,16 @@ int
 arc_gen_ADD1L(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -8030,16 +8028,16 @@ int
 arc_gen_ADD2L(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -8106,16 +8104,16 @@ int
 arc_gen_ADD3L(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
     int ret = DISAS_NEXT;
-    TCGv temp_3 = tcg_temp_local_new();
-    TCGv cc_flag = tcg_temp_local_new();
-    TCGv lb = tcg_temp_local_new();
-    TCGv lc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_7 = tcg_temp_local_new();
-    TCGv temp_6 = tcg_temp_local_new();
+    TCGv temp_3 = tcg_temp_new();
+    TCGv cc_flag = tcg_temp_new();
+    TCGv lb = tcg_temp_new();
+    TCGv lc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_7 = tcg_temp_new();
+    TCGv temp_6 = tcg_temp_new();
     getCCFlag(temp_3);
     tcg_gen_mov_tl(cc_flag, temp_3);
     tcg_gen_mov_tl(lb, b);
@@ -8184,19 +8182,19 @@ int
 arc_gen_ADCL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   tcg_gen_mov_tl(lb, b);
@@ -8277,19 +8275,19 @@ int
 arc_gen_SBCL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   tcg_gen_mov_tl(lb, b);
@@ -8369,16 +8367,16 @@ int
 arc_gen_SUBL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   tcg_gen_mov_tl(lb, b);
@@ -8451,16 +8449,16 @@ int
 arc_gen_SUB1L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   tcg_gen_mov_tl(lb, b);
@@ -8533,16 +8531,16 @@ int
 arc_gen_SUB2L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   tcg_gen_mov_tl(lb, b);
@@ -8615,16 +8613,16 @@ int
 arc_gen_SUB3L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   tcg_gen_mov_tl(lb, b);
@@ -8705,19 +8703,19 @@ int
 arc_gen_MAXL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   tcg_gen_mov_tl(lb, b);
@@ -8811,19 +8809,19 @@ int
 arc_gen_MINL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   tcg_gen_mov_tl(lb, b);
@@ -8903,15 +8901,15 @@ int
 arc_gen_CMPL (DisasCtxt *ctx, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -8968,10 +8966,10 @@ int
 arc_gen_ANDL (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -9027,10 +9025,10 @@ int
 arc_gen_ORL (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -9086,10 +9084,10 @@ int
 arc_gen_XORL (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -9145,10 +9143,10 @@ int
 arc_gen_MOVL (DisasCtxt *ctx, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -9201,11 +9199,11 @@ int
 arc_gen_MOVHL (DisasCtxt *ctx, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -9277,19 +9275,19 @@ int
 arc_gen_ASLL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
   int f_flag;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -9378,20 +9376,20 @@ int
 arc_gen_ASRL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   int f_flag;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -9482,20 +9480,20 @@ int
 arc_gen_LSRL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lb = tcg_temp_local_new();
-  TCGv lc = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lb = tcg_temp_new();
+  TCGv lc = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   int f_flag;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -9577,11 +9575,11 @@ int
 arc_gen_BICL (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -9640,13 +9638,13 @@ int
 arc_gen_BCLRL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -9717,16 +9715,16 @@ int
 arc_gen_BMSKL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv tmp1 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp2 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv tmp1 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp2 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
@@ -9810,17 +9808,17 @@ int
 arc_gen_BMSKNL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv tmp1 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp2 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv tmp1 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp2 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
@@ -9898,12 +9896,12 @@ int
 arc_gen_BSETL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -9964,11 +9962,11 @@ int
 arc_gen_BXORL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -10028,18 +10026,18 @@ int
 arc_gen_ROLL (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -10109,13 +10107,13 @@ int
 arc_gen_SEXBL (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -10177,13 +10175,13 @@ int
 arc_gen_SEXHL (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -10242,13 +10240,13 @@ int
 arc_gen_SEXWL (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   int f_flag;
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
@@ -10307,13 +10305,13 @@ int
 arc_gen_BTSTL (DisasCtxt *ctx, TCGv c, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -10360,11 +10358,11 @@ int
 arc_gen_TSTL (DisasCtxt *ctx, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -10413,22 +10411,22 @@ int
 arc_gen_XBFUL (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv N = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv M = tcg_temp_local_new();
-  TCGv tmp1 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
-  TCGv tmp2 = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv N = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv M = tcg_temp_new();
+  TCGv tmp1 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
+  TCGv tmp2 = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -10501,12 +10499,12 @@ int
 arc_gen_AEXL (DisasCtxt *ctx, TCGv src2, TCGv b)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv tmp = tcg_temp_local_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv tmp = tcg_temp_new();
   getCCFlag(temp_3);
   tcg_gen_mov_tl(cc_flag, temp_3);
   TCGLabel *done_1 = gen_new_label();
@@ -10546,11 +10544,9 @@ arc_gen_LRL (DisasCtxt *ctx, TCGv dest, TCGv src)
 {
   int ret = DISAS_NORETURN;
 
-  if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-      gen_io_start();
-  }
+  translator_io_start(&ctx->base);
 
-  TCGv temp_1 = tcg_temp_local_new();
+  TCGv temp_1 = tcg_temp_new();
   readAuxReg(temp_1, src);
   tcg_gen_mov_tl(dest, temp_1);
   tcg_temp_free(temp_1);
@@ -10591,18 +10587,18 @@ int
 arc_gen_DIVL (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
   getCCFlag(temp_9);
   tcg_gen_mov_tl(cc_flag, temp_9);
   TCGLabel *done_1 = gen_new_label();
@@ -10685,15 +10681,15 @@ int
 arc_gen_DIVUL (DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -10770,18 +10766,18 @@ int
 arc_gen_REML (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv temp_10 = tcg_temp_local_new();
-  TCGv temp_11 = tcg_temp_local_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv temp_10 = tcg_temp_new();
+  TCGv temp_11 = tcg_temp_new();
   getCCFlag(temp_9);
   tcg_gen_mov_tl(cc_flag, temp_9);
   TCGLabel *done_1 = gen_new_label();
@@ -10864,15 +10860,15 @@ int
 arc_gen_REMUL (DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -10949,13 +10945,13 @@ int
 arc_gen_ABSL (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv lsrc = tcg_temp_local_new();
-  TCGv alu = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
-  TCGv temp_5 = tcg_temp_local_new();
+  TCGv lsrc = tcg_temp_new();
+  TCGv alu = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
+  TCGv temp_5 = tcg_temp_new();
   tcg_gen_mov_tl(lsrc, src);
   tcg_gen_subfi_tl(alu, 0, lsrc);
   TCGLabel *else_1 = gen_new_label();
@@ -11019,8 +11015,8 @@ int
 arc_gen_SWAPL (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     const int ret = DISAS_NEXT;
-    TCGv hi = tcg_temp_local_new();
-    TCGv lo = tcg_temp_local_new();
+    TCGv hi = tcg_temp_new();
+    TCGv lo = tcg_temp_new();
 
     tcg_gen_shli_tl(lo, src, 32);
     tcg_gen_shri_tl(hi, src, 32);
@@ -11142,14 +11138,14 @@ int
 arc_gen_SETEQL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -11195,7 +11191,7 @@ arc_gen_BREQL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -11237,14 +11233,14 @@ int
 arc_gen_SETNEL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -11290,7 +11286,7 @@ arc_gen_BRNEL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -11332,14 +11328,14 @@ int
 arc_gen_SETLTL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -11386,7 +11382,7 @@ arc_gen_BRLTL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -11427,19 +11423,19 @@ int
 arc_gen_SETGEL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv v = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv v = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -11490,7 +11486,7 @@ arc_gen_BRGEL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -11532,19 +11528,19 @@ int
 arc_gen_SETLEL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv v = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv v = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -11611,19 +11607,19 @@ int
 arc_gen_SETGTL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv temp_5 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv v = tcg_temp_local_new();
-  TCGv temp_7 = tcg_temp_local_new();
-  TCGv temp_6 = tcg_temp_local_new();
-  TCGv p_b = tcg_temp_local_new();
-  TCGv temp_9 = tcg_temp_local_new();
-  TCGv temp_8 = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_3 = tcg_temp_local_new();
-  TCGv temp_4 = tcg_temp_local_new();
+  TCGv temp_5 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv v = tcg_temp_new();
+  TCGv temp_7 = tcg_temp_new();
+  TCGv temp_6 = tcg_temp_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv temp_9 = tcg_temp_new();
+  TCGv temp_8 = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_3 = tcg_temp_new();
+  TCGv temp_4 = tcg_temp_new();
   getCCFlag(temp_5);
   tcg_gen_mov_tl(cc_flag, temp_5);
   TCGLabel *done_1 = gen_new_label();
@@ -11674,7 +11670,7 @@ arc_gen_BRLOL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -11715,12 +11711,12 @@ int
 arc_gen_SETLOL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv cc_temp_1 = tcg_temp_local_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv cc_temp_1 = tcg_temp_new();
   getCCFlag(cc_flag);
   TCGLabel *done_cc = gen_new_label();
   tcg_gen_setcond_tl(TCG_COND_EQ, cc_temp_1, cc_flag, arc_true);
@@ -11763,7 +11759,7 @@ arc_gen_BRHSL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
 {
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
-    TCGv cond = tcg_temp_local_new();
+    TCGv cond = tcg_temp_new();
 
     update_delay_flag(ctx);
 
@@ -11804,12 +11800,12 @@ int
 arc_gen_SETHSL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
 {
   int ret = DISAS_NEXT;
-  TCGv p_b = tcg_temp_local_new();
-  TCGv p_c = tcg_temp_local_new();
-  TCGv temp_2 = tcg_temp_local_new();
-  TCGv temp_1 = tcg_temp_local_new();
-  TCGv cc_flag = tcg_temp_local_new();
-  TCGv cc_temp_1 = tcg_temp_local_new();
+  TCGv p_b = tcg_temp_new();
+  TCGv p_c = tcg_temp_new();
+  TCGv temp_2 = tcg_temp_new();
+  TCGv temp_1 = tcg_temp_new();
+  TCGv cc_flag = tcg_temp_new();
+  TCGv cc_temp_1 = tcg_temp_new();
   getCCFlag(cc_flag);
   TCGLabel *done_cc = gen_new_label();
   tcg_gen_setcond_tl(TCG_COND_EQ, cc_temp_1, cc_flag, arc_true);
@@ -11850,7 +11846,7 @@ int
 arc_gen_EXL (DisasCtxt *ctx, TCGv b, TCGv c)
 {
   int ret = DISAS_NEXT;
-  TCGv temp = tcg_temp_local_new();
+  TCGv temp = tcg_temp_new();
   tcg_gen_mov_tl(temp, b);
   tcg_gen_atomic_xchg_tl(b, c, temp, ctx->mem_idx, MO_UQ);
   tcg_temp_free(temp);
@@ -12137,8 +12133,8 @@ int
 arc_gen_NORML (DisasCtxt *ctx, TCGv src, TCGv dest)
 {
   int ret = DISAS_NEXT;
-  TCGv psrc = tcg_temp_local_new();
-  TCGv i = tcg_temp_local_new();
+  TCGv psrc = tcg_temp_new();
+  TCGv i = tcg_temp_new();
   tcg_gen_mov_tl(psrc, src);
   ARC_HELPER(norml, i, psrc);
   tcg_gen_subfi_tl(dest, 63, i);
@@ -12189,12 +12185,12 @@ int
 arc_gen_FLSL(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_5 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_5 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
     tcg_gen_mov_tl(psrc, src);
     TCGLabel *else_1 = gen_new_label();
     TCGLabel *done_1 = gen_new_label();
@@ -12255,11 +12251,11 @@ int
 arc_gen_FFSL(DisasCtxt *ctx, TCGv src, TCGv dest)
 {
     int ret = DISAS_NEXT;
-    TCGv psrc = tcg_temp_local_new();
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_2 = tcg_temp_local_new();
-    TCGv temp_4 = tcg_temp_local_new();
-    TCGv temp_3 = tcg_temp_local_new();
+    TCGv psrc = tcg_temp_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_2 = tcg_temp_new();
+    TCGv temp_4 = tcg_temp_new();
+    TCGv temp_3 = tcg_temp_new();
     tcg_gen_mov_tl(psrc, src);
     TCGLabel *else_1 = gen_new_label();
     TCGLabel *done_1 = gen_new_label();
@@ -12336,7 +12332,7 @@ arc_gen_BBIT0L(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
     TCGv _c = tcg_temp_new();
-    TCGv msk = tcg_const_tl(1);
+    TCGv msk = tcg_constant_tl(1);
     TCGv bit = tcg_temp_new();
 
     update_delay_flag(ctx);
@@ -12375,7 +12371,7 @@ arc_gen_BBIT1L(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset ATTRIBUTE_UNUSED)
     const target_ulong target = ctx->pcl + ctx->insn.operands[2].value;
     TCGLabel *do_not_branch = gen_new_label();
     TCGv _c = tcg_temp_new();
-    TCGv msk = tcg_const_tl(1);
+    TCGv msk = tcg_constant_tl(1);
     TCGv bit = tcg_temp_new();
 
     update_delay_flag(ctx);
@@ -12404,7 +12400,7 @@ arc_gen_VPACK4HL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
   TCGv c_h0 = tcg_temp_new();
   TCGv c_h2 = tcg_temp_new();
 
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   /* Conditional execution */
@@ -12443,7 +12439,7 @@ arc_gen_VPACK4HM(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
   TCGv c_h1 = tcg_temp_new();
   TCGv c_h3 = tcg_temp_new();
 
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   /* Conditional execution */
@@ -12480,7 +12476,7 @@ arc_gen_VPACK2WL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
   TCGv b_w0 = tcg_temp_new();
   TCGv c_w0 = tcg_temp_new();
 
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   /* Conditional execution */
@@ -12511,7 +12507,7 @@ arc_gen_VPACK2WM(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
   TCGv b_w1 = tcg_temp_new();
   TCGv c_w1 = tcg_temp_new();
 
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   /* Conditional execution */
@@ -13198,10 +13194,10 @@ arc_gen_FLD16(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest)
 {
     int ret = DISAS_NEXT;
     int ZZ = 2; /* 16bit */
-    TCGv address = tcg_temp_local_new();
-    TCGv l_src1 = tcg_temp_local_new();
-    TCGv l_src2 = tcg_temp_local_new();
-    TCGv new_dest = tcg_temp_local_new();
+    TCGv address = tcg_temp_new();
+    TCGv l_src1 = tcg_temp_new();
+    TCGv l_src2 = tcg_temp_new();
+    TCGv new_dest = tcg_temp_new();
 
     arc_gen_ldst_pre(ctx, address, src1, src2, ZZ);
 
@@ -13237,9 +13233,9 @@ arc_gen_FST16(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest)
 {
     int ret = DISAS_NEXT;
     int ZZ = 2; /* 32bit */
-    TCGv address = tcg_temp_local_new();
-    TCGv l_src1 = tcg_temp_local_new();
-    TCGv l_src2 = tcg_temp_local_new();
+    TCGv address = tcg_temp_new();
+    TCGv l_src1 = tcg_temp_new();
+    TCGv l_src2 = tcg_temp_new();
 
     arc_gen_ldst_pre(ctx, address, src1, src2, ZZ);
 
@@ -13272,10 +13268,10 @@ arc_gen_FLD32(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest)
 {
     int ret = DISAS_NEXT;
     int ZZ = 0; /* 32bit */
-    TCGv address = tcg_temp_local_new();
-    TCGv l_src1 = tcg_temp_local_new();
-    TCGv l_src2 = tcg_temp_local_new();
-    TCGv new_dest = tcg_temp_local_new();
+    TCGv address = tcg_temp_new();
+    TCGv l_src1 = tcg_temp_new();
+    TCGv l_src2 = tcg_temp_new();
+    TCGv new_dest = tcg_temp_new();
 
     arc_gen_ldst_pre(ctx, address, src1, src2, ZZ);
 
@@ -13311,9 +13307,9 @@ arc_gen_FST32(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest)
 {
     int ret = DISAS_NEXT;
     int ZZ = 0; /* 32bit */
-    TCGv address = tcg_temp_local_new();
-    TCGv l_src1 = tcg_temp_local_new();
-    TCGv l_src2 = tcg_temp_local_new();
+    TCGv address = tcg_temp_new();
+    TCGv l_src1 = tcg_temp_new();
+    TCGv l_src2 = tcg_temp_new();
 
     arc_gen_ldst_pre(ctx, address, src1, src2, ZZ);
 
@@ -13346,10 +13342,10 @@ arc_gen_FLD64(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest)
 {
     int ret = DISAS_NEXT;
     int ZZ = 3; /* 64 bit */
-    TCGv address = tcg_temp_local_new();
-    TCGv l_src1 = tcg_temp_local_new();
-    TCGv l_src2 = tcg_temp_local_new();
-    TCGv new_dest = tcg_temp_local_new();
+    TCGv address = tcg_temp_new();
+    TCGv l_src1 = tcg_temp_new();
+    TCGv l_src2 = tcg_temp_new();
+    TCGv new_dest = tcg_temp_new();
 
     arc_gen_ldst_pre(ctx, address, src1, src2, ZZ);
 
@@ -13385,9 +13381,9 @@ arc_gen_FST64(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest)
 {
     int ret = DISAS_NEXT;
     int ZZ = 3; /* 64 bit */
-    TCGv address = tcg_temp_local_new();
-    TCGv l_src1 = tcg_temp_local_new();
-    TCGv l_src2 = tcg_temp_local_new();
+    TCGv address = tcg_temp_new();
+    TCGv l_src1 = tcg_temp_new();
+    TCGv l_src2 = tcg_temp_new();
 
     arc_gen_ldst_pre(ctx, address, src1, src2, ZZ);
 
@@ -13422,12 +13418,12 @@ arc_gen_FLDD64(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest)
 {
     int ret = DISAS_NEXT;
     int ZZ = 3; /* 64 bit */
-    TCGv address = tcg_temp_local_new();
-    TCGv l_src1 = tcg_temp_local_new();
-    TCGv l_src2 = tcg_temp_local_new();
-    TCGv new_dest = tcg_temp_local_new();
-    TCGv new_dest_hi = tcg_temp_local_new();
-    TCGv address_high = tcg_temp_local_new();
+    TCGv address = tcg_temp_new();
+    TCGv l_src1 = tcg_temp_new();
+    TCGv l_src2 = tcg_temp_new();
+    TCGv new_dest = tcg_temp_new();
+    TCGv new_dest_hi = tcg_temp_new();
+    TCGv address_high = tcg_temp_new();
 
     arc_gen_ldst_pre(ctx, address, src1, src2, ZZ);
 
@@ -13471,10 +13467,10 @@ arc_gen_FSTD64(DisasCtxt *ctx, TCGv data_reg, TCGv dest, TCGv offset)
 {
     int ret = DISAS_NEXT;
     int ZZ = 3; /* 64 bit */
-    TCGv address = tcg_temp_local_new();
-    TCGv l_dest = tcg_temp_local_new();
-    TCGv l_offset = tcg_temp_local_new();
-    TCGv address_high = tcg_temp_local_new();
+    TCGv address = tcg_temp_new();
+    TCGv l_dest = tcg_temp_new();
+    TCGv l_offset = tcg_temp_new();
+    TCGv address_high = tcg_temp_new();
 
     arc_gen_ldst_pre(ctx, address, dest, offset, ZZ);
 
@@ -13834,7 +13830,7 @@ int arc_gen_VF##TYPE##INS(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) \
                                                                   \
     tcg_gen_brcondi_tl(TCG_COND_GE, b, mid_index, do_next_reg);   \
                                                                   \
-    TCGv size = tcg_const_tl(SIZE);                               \
+    TCGv size = tcg_constant_tl(SIZE);                               \
     gen_helper_vfins(a, cpu_env, a, b, c, size);                  \
     tcg_temp_free(size);                                          \
                                                                   \
@@ -13845,7 +13841,7 @@ int arc_gen_VF##TYPE##INS(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) \
     tcg_gen_subi_tl(index, b, mid_index);                         \
                                                                   \
     TCGv reg = nextFPURegWithNull(ctx, a);                        \
-    TCGv size1 = tcg_const_tl(SIZE);                              \
+    TCGv size1 = tcg_constant_tl(SIZE);                              \
                                                                   \
     gen_helper_vfins(reg, cpu_env, reg, index, c, size1);         \
                                                                   \
@@ -13891,7 +13887,7 @@ int arc_gen_VF##TYPE##EXT(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) \
                                                                   \
     tcg_gen_brcondi_tl(TCG_COND_GE, c, mid_index, do_next_reg);   \
                                                                   \
-    TCGv size = tcg_const_tl(SIZE);                               \
+    TCGv size = tcg_constant_tl(SIZE);                               \
     gen_helper_vfext(a, cpu_env, b, c, size);                     \
     tcg_temp_free(size);                                          \
                                                                   \
@@ -13902,7 +13898,7 @@ int arc_gen_VF##TYPE##EXT(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) \
     tcg_gen_subi_tl(index, c, mid_index);                         \
                                                                   \
     TCGv reg = nextFPUReg(ctx, b);                                \
-    TCGv size1 = tcg_const_tl(SIZE);                              \
+    TCGv size1 = tcg_constant_tl(SIZE);                              \
                                                                   \
     gen_helper_vfext(a, cpu_env, reg, index, size1);              \
                                                                   \
@@ -13939,7 +13935,7 @@ int arc_gen_VF##TYPE##REP(DisasCtxt *ctx, TCGv a, TCGv b) \
 {                                                         \
     int ret = DISAS_NEXT;                                 \
                                                           \
-    TCGv size = tcg_const_tl(SIZE);                       \
+    TCGv size = tcg_constant_tl(SIZE);                       \
     gen_helper_vfrep(a, cpu_env, b, size);                \
                                                           \
     if (vfp_width > 64) {                                 \
@@ -14269,9 +14265,9 @@ VEC_FLOAT4_SCALARD(VFDNMSUBS, vfdnmsubs)
 int arc_gen_##NAME(DisasCtxt *ctx, TCGv a, TCGv b)                             \
 {                                                                              \
     int ret = DISAS_NEXT;                                                      \
-    TCGv zero = tcg_const_tl(0);                                               \
-    TCGv one = tcg_const_tl(1);                                                \
-    TCGv type = tcg_const_tl(TYPE);                                            \
+    TCGv zero = tcg_constant_tl(0);                                               \
+    TCGv one = tcg_constant_tl(1);                                                \
+    TCGv type = tcg_constant_tl(TYPE);                                            \
     if (vfp_width > 64) {                                                      \
         TCGv tmp = tcg_temp_new();                                             \
         TCGv na = nextFPURegWithNull(ctx, a);                                  \
@@ -14329,9 +14325,9 @@ VEC_SHUFFLE2_INSN(VFDEXCH, DEXCH)
 int arc_gen_##NAME(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)                    \
 {                                                                             \
     int ret = DISAS_NEXT;                                                     \
-    TCGv zero = tcg_const_tl(0);                                              \
-    TCGv one = tcg_const_tl(1);                                               \
-    TCGv type = tcg_const_tl(TYPE);                                           \
+    TCGv zero = tcg_constant_tl(0);                                              \
+    TCGv one = tcg_constant_tl(1);                                               \
+    TCGv type = tcg_constant_tl(TYPE);                                           \
     if (vfp_width > 64) {                                                     \
         TCGv tmp = tcg_temp_new();                                            \
         TCGv na = nextFPURegWithNull(ctx, a);                                 \
diff --git a/target/arc/semfunc.c b/target/arc/semfunc.c
index 27f49c0c94f..ac21279608f 100644
--- a/target/arc/semfunc.c
+++ b/target/arc/semfunc.c
@@ -22,7 +22,7 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 #include "target/arc/semfunc.h"
-#include "exec/gen-icount.h"
+#include "tcg/tcg-temp-internal.h"
 #include "tcg/tcg-op-gvec.h"
 
 void
@@ -627,8 +627,8 @@ void
 arc_gen_except_no_wait_instructions(DisasCtxt *ctx)
 {
     TCGLabel *done = gen_new_label();
-    TCGv in_kernel_mode = tcg_temp_local_new();
-    TCGv usermode_sleep_enabled = tcg_temp_local_new();
+    TCGv in_kernel_mode = tcg_temp_new();
+    TCGv usermode_sleep_enabled = tcg_temp_new();
 
     inKernelMode(in_kernel_mode);
     getUsermodeSleep(usermode_sleep_enabled);
@@ -654,7 +654,7 @@ arc_gen_VPACK2HL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
   TCGv b_h0 = tcg_temp_new();
   TCGv c_h0 = tcg_temp_new();
 
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   /* Conditional execution */
@@ -688,7 +688,7 @@ arc_gen_VPACK2HM(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
   TCGv b_h1 = tcg_temp_new();
   TCGv c_h1 = tcg_temp_new();
 
-  TCGv cc_temp = tcg_temp_local_new();
+  TCGv cc_temp = tcg_temp_new();
   TCGLabel *cc_done = gen_new_label();
 
   /* Conditional execution */
@@ -772,4 +772,4 @@ arc_gen_atld_op(DisasCtxt *ctx, TCGv_i32 b, TCGv c)
     }
 
     return mop;
-}
\ No newline at end of file
+}
diff --git a/target/arc/semfunc.h b/target/arc/semfunc.h
index 2bbc5b44f76..f9e6049612f 100644
--- a/target/arc/semfunc.h
+++ b/target/arc/semfunc.h
@@ -360,7 +360,7 @@ arc_gen_atld_op(DisasCtxt *ctx, TCGv_i32 b, TCGv c);
  * evaluating the cc flag
  */
 #define ARC_GEN_SEMFUNC_INIT()                                          \
-    TCGv cc_temp = tcg_temp_local_new();                                \
+    TCGv cc_temp = tcg_temp_new();                                \
     TCGLabel *cc_done  = gen_new_label();                               \
     if (ctx->insn.cc != ARC_COND_AL && ctx->insn.cc != ARC_COND_RA) {   \
         getCCFlag(cc_temp);                                             \
diff --git a/target/arc/translate.c b/target/arc/translate.c
index 2db7e5787dc..9a9fc1c2f7b 100644
--- a/target/arc/translate.c
+++ b/target/arc/translate.c
@@ -21,10 +21,14 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 #include "qemu/qemu-print.h"
+#include "tcg/tcg-temp-internal.h"
 #include "tcg/tcg-op-gvec.h"
 #include "target/arc/semfunc.h"
 #include "target/arc/arc-common.h"
 
+#define HELPER_H "helper.h"
+#include "exec/helper-info.c.inc"
+#undef  HELPER_H
 
 /* Globals */
 TCGv    cpu_pstate;
@@ -61,7 +65,6 @@ TCGv cpu_exclusive_val_hi;
 
 /* Macros */
 
-#include "exec/gen-icount.h"
 #define REG(x)  (cpu_r[x])
 
 /* macro used to fix middle-endianess. */
@@ -215,7 +218,7 @@ static void arc_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 
     if (dc->base.num_insns == dc->base.max_insns &&
         (dc->base.tb->cflags & CF_LAST_IO)) {
-        gen_io_start();
+        translator_io_start(&dc->base);
     }
 }
 
@@ -443,7 +446,7 @@ static TCGv arc_decode_operand(const struct arc_opcode *opcode,
     if (nop >= ctx->insn.n_ops) {
         struct constant_operands *co = constant_entry_for(mapping, nop);
         assert(co != NULL);
-        ret = tcg_const_local_tl(co->default_value);
+        ret = tcg_constant_tl(co->default_value);
         return ret;
     } else {
         operand_t operand = ctx->insn.operands[nop];
@@ -466,7 +469,7 @@ static TCGv arc_decode_operand(const struct arc_opcode *opcode,
                 tcg_gen_movi_tl(cpu_limm, limm);
                 ret = cpu_r[62];
             } else {
-                ret = tcg_const_local_tl(limm);
+                ret = tcg_constant_tl(limm);
             }
         }
     }
@@ -480,9 +483,9 @@ void arc_gen_excp(const DisasCtxt *ctx,
                   target_ulong causecode,
                   target_ulong param)
 {
-    TCGv tcg_index = tcg_const_tl(index);
-    TCGv tcg_cause = tcg_const_tl(causecode);
-    TCGv tcg_param = tcg_const_tl(param);
+    TCGv tcg_index = tcg_constant_tl(index);
+    TCGv tcg_cause = tcg_constant_tl(causecode);
+    TCGv tcg_param = tcg_constant_tl(param);
 
     tcg_gen_movi_tl(cpu_pc, ctx->cpc);
     tcg_gen_movi_tl(cpu_eret, ctx->cpc);
@@ -516,9 +519,9 @@ static bool check_enter_leave_nr_regs(const DisasCtxt *ctx,
     if ((rgf_num_regs == 32 && regs > 14) ||
         (rgf_num_regs == 16 && regs >  3)) {
 
-        TCGv tcg_index = tcg_const_tl(EXCP_INST_ERROR);
-        TCGv tcg_cause = tcg_const_tl(0);
-        TCGv tcg_param = tcg_const_tl(0);
+        TCGv tcg_index = tcg_constant_tl(EXCP_INST_ERROR);
+        TCGv tcg_cause = tcg_constant_tl(0);
+        TCGv tcg_param = tcg_constant_tl(0);
 
         tcg_gen_movi_tl(cpu_eret, ctx->cpc);
         tcg_gen_mov_tl(cpu_erbta, cpu_bta);
@@ -540,9 +543,9 @@ static bool check_enter_leave_nr_regs(const DisasCtxt *ctx,
 static bool check_delay_or_execution_slot(const DisasCtxt *ctx)
 {
     if (ctx->env->stat.pstate & STATUS32_DE) {
-        TCGv tcg_index = tcg_const_tl(EXCP_INST_ERROR);
-        TCGv tcg_cause = tcg_const_tl(0x1);
-        TCGv tcg_param = tcg_const_tl(0x0);
+        TCGv tcg_index = tcg_constant_tl(EXCP_INST_ERROR);
+        TCGv tcg_cause = tcg_constant_tl(0x1);
+        TCGv tcg_param = tcg_constant_tl(0x0);
 
         tcg_gen_movi_tl(cpu_efa,  ctx->cpc);
         tcg_gen_movi_tl(cpu_eret, ctx->cpc);
@@ -566,7 +569,7 @@ static void check_addr_is_word_aligned(const DisasCtxt *ctx,
                                        TCGv addr)
 {
     TCGLabel *l1 = gen_new_label();
-    TCGv tmp = tcg_temp_local_new();
+    TCGv tmp = tcg_temp_new();
 
     tcg_gen_andi_tl(tmp, addr, 0x3);
     tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, l1);
@@ -575,9 +578,9 @@ static void check_addr_is_word_aligned(const DisasCtxt *ctx,
     tcg_gen_movi_tl(cpu_eret, ctx->cpc);
     tcg_gen_mov_tl(cpu_erbta, cpu_bta);
 
-    TCGv tcg_index = tcg_const_tl(EXCP_MISALIGNED);
-    TCGv tcg_cause = tcg_const_tl(0x0);
-    TCGv tcg_param = tcg_const_tl(0x0);
+    TCGv tcg_index = tcg_constant_tl(EXCP_MISALIGNED);
+    TCGv tcg_cause = tcg_constant_tl(0x0);
+    TCGv tcg_param = tcg_constant_tl(0x0);
 
     gen_helper_raise_exception(cpu_env, tcg_index, tcg_cause, tcg_param);
 
@@ -627,8 +630,8 @@ int arc_gen_ENTER(DisasCtxt *ctx)
         return ret;
     }
 
-    TCGv temp_1 = tcg_temp_local_new();
-    TCGv temp_sp = tcg_temp_local_new();
+    TCGv temp_1 = tcg_temp_new();
+    TCGv temp_sp = tcg_temp_new();
 
     /* stack must be a multiple of 4 (32 bit aligned) */
     tcg_gen_subi_tl(temp_1, cpu_sp, stack_size);
@@ -706,7 +709,7 @@ int arc_gen_LEAVE(DisasContext *ctx)
         return ret;
     }
 
-    TCGv temp_1 = tcg_temp_local_new();
+    TCGv temp_1 = tcg_temp_new();
     /*
      * stack must be a multiple of 4 (32 bit aligned). we must take into
      * account if sp is going to use fp's value or not.
@@ -718,7 +721,7 @@ int arc_gen_LEAVE(DisasContext *ctx)
     }
     check_addr_is_word_aligned(ctx, temp_1);
 
-    TCGv temp_sp = tcg_temp_local_new();
+    TCGv temp_sp = tcg_temp_new();
     /*
      * if fp is in the picture, then first we have to use the current
      * fp as the stack pointer for restoring.
@@ -764,14 +767,12 @@ arc_gen_SR(DisasCtxt *ctx, TCGv src2, TCGv src1)
 {
     int ret = DISAS_NEXT;
 
-    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-	    gen_io_start();
-    }
+    translator_io_start(&ctx->base);
 
 #if defined(TARGET_ARC32)
     writeAuxReg(src2, src1);
 #elif defined(TARGET_ARC64)
-    TCGv temp = tcg_temp_local_new();
+    TCGv temp = tcg_temp_new();
     tcg_gen_andi_tl(temp, src1, 0xffffffff);
     writeAuxReg(src2, src1);
     tcg_temp_free(temp);
@@ -783,9 +784,7 @@ arc_gen_SRL(DisasCtxt *ctx, TCGv src2, TCGv src1)
 {
     int ret = DISAS_NORETURN;
 
-    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-	    gen_io_start();
-    }
+    translator_io_start(&ctx->base);
 
     writeAuxReg(src2, src1);
     return ret;
@@ -818,7 +817,7 @@ arc_gen_DSYNC(DisasCtxt *ctx)
 int
 arc_gen_HALT(DisasCtxt *ctx)
 {
-    TCGv npc = tcg_const_local_tl(ctx->cpc);
+    TCGv npc = tcg_constant_tl(ctx->cpc);
     gen_helper_halt(cpu_env, npc);
     tcg_temp_free(npc);
     return DISAS_NORETURN;
@@ -840,14 +839,14 @@ arc_gen_MPYL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
     TCGLabel *done = gen_new_label();
 
     if (ctx->insn.cc) {
-        TCGv cc = tcg_temp_local_new();
+        TCGv cc = tcg_temp_new();
         arc_gen_verifyCCFlag(ctx, cc);
         tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done);
         tcg_temp_free(cc);
     }
 
-    TCGv_i64 lo = tcg_temp_local_new_i64();
-    TCGv_i64 hi = tcg_temp_local_new_i64();
+    TCGv_i64 lo = tcg_temp_new_i64();
+    TCGv_i64 hi = tcg_temp_new_i64();
 
     tcg_gen_muls2_i64(lo, hi, b, c);
     tcg_gen_mov_tl(a, lo);
@@ -874,14 +873,14 @@ arc_gen_MPYML(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
     TCGLabel *done = gen_new_label();
 
     if (ctx->insn.cc) {
-        TCGv cc = tcg_temp_local_new();
+        TCGv cc = tcg_temp_new();
         arc_gen_verifyCCFlag(ctx, cc);
         tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done);
         tcg_temp_free(cc);
     }
 
-    TCGv lo = tcg_temp_local_new();
-    TCGv hi = tcg_temp_local_new();
+    TCGv lo = tcg_temp_new();
+    TCGv hi = tcg_temp_new();
     tcg_gen_muls2_i64(lo, hi, b, c);
     tcg_gen_mov_tl(a, hi);
 
@@ -907,14 +906,14 @@ arc_gen_MPYMUL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
     TCGLabel *done = gen_new_label();
 
     if (ctx->insn.cc) {
-        TCGv cc = tcg_temp_local_new();
+        TCGv cc = tcg_temp_new();
         arc_gen_verifyCCFlag(ctx, cc);
         tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done);
         tcg_temp_free(cc);
     }
 
-    TCGv lo = tcg_temp_local_new();
-    TCGv hi = tcg_temp_local_new();
+    TCGv lo = tcg_temp_new();
+    TCGv hi = tcg_temp_new();
 
     tcg_gen_mulu2_i64(lo, hi, b, c);
     tcg_gen_mov_tl(a, hi);
@@ -941,14 +940,14 @@ arc_gen_MPYMSUL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
     TCGLabel *done = gen_new_label();
 
     if (ctx->insn.cc) {
-        TCGv cc = tcg_temp_local_new();
+        TCGv cc = tcg_temp_new();
         arc_gen_verifyCCFlag(ctx, cc);
         tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done);
         tcg_temp_free(cc);
     }
 
-    TCGv lo = tcg_temp_local_new();
-    TCGv hi = tcg_temp_local_new();
+    TCGv lo = tcg_temp_new();
+    TCGv hi = tcg_temp_new();
     tcg_gen_mulsu2_tl(lo, hi, b, c);
     tcg_gen_mov_tl(a, hi);
 
@@ -968,13 +967,13 @@ arc_gen_ADDHL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c)
     TCGLabel *done = gen_new_label();
 
     if (ctx->insn.cc) {
-        TCGv cc = tcg_temp_local_new();
+        TCGv cc = tcg_temp_new();
         arc_gen_verifyCCFlag(ctx, cc);
         tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done);
         tcg_temp_free(cc);
     }
 
-    TCGv shifted = tcg_temp_local_new();
+    TCGv shifted = tcg_temp_new();
     tcg_gen_shli_tl(shifted, c, 32);
     tcg_gen_add_tl(a, b, shifted);
 
@@ -1027,9 +1026,9 @@ arc_gen_LDDL(DisasCtxt *ctx, TCGv base, TCGv offset, TCGv dest_lo)
     }
 
     /* Only defined after possible exception routine codes. */
-    TCGv addr = tcg_temp_local_new();
-    TCGv data_hi = tcg_temp_local_new();
-    TCGv data_lo = tcg_temp_local_new();
+    TCGv addr = tcg_temp_new();
+    TCGv data_hi = tcg_temp_new();
+    TCGv data_lo = tcg_temp_new();
 
     switch (ctx->insn.aa) {
     case 0:  /* Simple base+offset access. */
@@ -1124,7 +1123,7 @@ arc_gen_STDL(DisasCtxt *ctx, TCGv base, TCGv offset, TCGv src)
     } else if (ctx->insn.operands[0].type & ARC_OPERAND_LIMM
                || ctx->insn.operands[0].type & ARC_OPERAND_SIGNED) { /* w6 */
         /* Dealing with an immediate to store. */
-        data_hi = tcg_temp_local_new();
+        data_hi = tcg_temp_new();
         free_data_hi = true;
 
         if (ctx->insn.operands[0].type & ARC_OPERAND_SIGNED) {
@@ -1140,8 +1139,8 @@ arc_gen_STDL(DisasCtxt *ctx, TCGv base, TCGv offset, TCGv src)
     }
 
     /* Only defined after possible exception routine codes. */
-    TCGv data_lo = tcg_temp_local_new();
-    TCGv addr = tcg_temp_local_new();
+    TCGv data_lo = tcg_temp_new();
+    TCGv addr = tcg_temp_new();
     /* Caputre the data before it possibly changes (src = base). */
     tcg_gen_mov_tl(data_lo, src);
 
@@ -1188,8 +1187,8 @@ arc_gen_STDL(DisasCtxt *ctx, TCGv base, TCGv offset, TCGv src)
 int
 arc_gen_SWI(DisasCtxt *ctx, TCGv a)
 {
-    TCGv tcg_index = tcg_const_tl(EXCP_SWI);
-    TCGv tcg_cause = tcg_const_tl(0);
+    TCGv tcg_index = tcg_constant_tl(EXCP_SWI);
+    TCGv tcg_cause = tcg_constant_tl(0);
 
     tcg_gen_movi_tl(cpu_pc, ctx->cpc);
     tcg_gen_movi_tl(cpu_eret, ctx->cpc);
@@ -1204,8 +1203,8 @@ arc_gen_SWI(DisasCtxt *ctx, TCGv a)
 int
 arc_gen_TRAP(DisasCtxt *ctx, TCGv a)
 {
-    TCGv tcg_index = tcg_const_tl(EXCP_TRAP);
-    TCGv tcg_cause = tcg_const_tl(0);
+    TCGv tcg_index = tcg_constant_tl(EXCP_TRAP);
+    TCGv tcg_cause = tcg_constant_tl(0);
 
     tcg_gen_movi_tl(cpu_pc, ctx->cpc);
     tcg_gen_movi_tl(cpu_eret, ctx->npc);
@@ -1221,9 +1220,7 @@ arc_gen_TRAP(DisasCtxt *ctx, TCGv a)
 int
 arc_gen_RTIE(DisasCtxt *ctx)
 {
-    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-	    gen_io_start();
-    }
+    translator_io_start(&ctx->base);
 
     tcg_gen_movi_tl(cpu_pc, ctx->cpc);
     gen_helper_rtie(cpu_env);
@@ -1276,8 +1273,8 @@ arc_gen_sleep(DisasCtxt *ctx, TCGv a)
     uint32_t param = 0;
 
     if (ctx->insn.operands[0].type & ARC_OPERAND_IR) {
-        TCGv tmp3 = tcg_temp_local_new();
-        TCGv tmp4 = tcg_temp_local_new();
+        TCGv tmp3 = tcg_temp_new();
+        TCGv tmp4 = tcg_temp_new();
         TCGLabel *done_L = gen_new_label();
 
         tcg_gen_andi_tl(tmp3, a, 0x10);
@@ -1299,7 +1296,7 @@ arc_gen_sleep(DisasCtxt *ctx, TCGv a)
     }
     /* FIXME: setup debug registers as well. */
 
-    TCGv npc = tcg_temp_local_new();
+    TCGv npc = tcg_temp_new();
     tcg_gen_movi_tl(npc, ctx->npc);
     gen_helper_halt(cpu_env, npc);
     tcg_temp_free(npc);
@@ -1384,7 +1381,7 @@ arc_gen_WLFC(DisasCtxt *ctx, TCGv c)
      * also wakeup WLFC induced sleep
      */
     TCGLabel *dont_stop = gen_new_label();
-    TCGv lf_set = tcg_temp_local_new();
+    TCGv lf_set = tcg_temp_new();
 
     gen_helper_getlf(lf_set, cpu_env);
     tcg_gen_brcondi_tl(TCG_COND_NE, lf_set, 0x1, dont_stop);
@@ -1515,7 +1512,7 @@ void decode_opc(CPUARCState *env, DisasContext *ctx)
     if (env->lpe == ctx->npc) {
         TCGLabel *zol_end = gen_new_label();
         TCGLabel *zol_else = gen_new_label();
-        TCGv lps = tcg_temp_local_new();
+        TCGv lps = tcg_temp_new();
 
         tcg_gen_brcondi_tl(TCG_COND_GTU, cpu_lpc, 1, zol_else);
           tcg_gen_movi_tl(cpu_lpc, 0);
@@ -1540,8 +1537,8 @@ static void arc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     CPUARCState *env = cpu->env_ptr;
 
     /* TODO (issue #62): these must be removed */
-    dc->zero = tcg_const_local_tl(0);
-    dc->one  = tcg_const_local_tl(1);
+    dc->zero = tcg_constant_tl(0);
+    dc->one  = tcg_constant_tl(1);
 
     dc->cpc = dc->base.pc_next;
     decode_opc(env, dc);
@@ -1565,9 +1562,6 @@ static void arc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     /* TODO (issue #62): these must be removed. */
     tcg_temp_free(dc->zero);
     tcg_temp_free(dc->one);
-
-    /* verify if there is any TCG temporaries leakge */
-    translator_loop_temp_check(dcbase);
 }
 
 static void arc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
@@ -1592,39 +1586,21 @@ static void arc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
     }
 }
 
-static void arc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
-{
-    DisasContext *dc = container_of(dcbase, DisasContext, base);
-
-    qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
-    log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size);
-}
-
-
 static const TranslatorOps arc_translator_ops = {
     .init_disas_context = arc_tr_init_disas_context,
     .tb_start           = arc_tr_tb_start,
     .insn_start         = arc_tr_insn_start,
     .translate_insn     = arc_tr_translate_insn,
     .tb_stop            = arc_tr_tb_stop,
-    .disas_log          = arc_tr_disas_log,
 };
 
 /* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUState *cpu,
-                           TranslationBlock *tb,
-                           int max_insns)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
+                           target_ulong pc, void *host_pc)
 {
     DisasContext dc;
     const TranslatorOps *ops = &arc_translator_ops;
-    translator_loop(ops, &dc.base, cpu, tb, max_insns);
-}
-
-void restore_state_to_opc(CPUARCState *env,
-                          TranslationBlock *tb,
-                          target_ulong *data)
-{
-    env->pc = data[0];
+    translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);
 }
 
 void arc_cpu_dump_state(CPUState *cs, FILE *f, int flags)