Add cores for AXI/AHB/APB/Avalon/Wishbone

[fischermoseley]

While it's possible for users to cobble together on-chip interfaces with IO cores and memory cores, it'd be rather convenient if Manta provided those out of the box.

Some use of open-source verification IP should probably be used here, although that might be slightly difficult to integrate into the Amaranth testbenches. Porting existing SystemVerilog VIP to Amaranth would be a super useful project, but that be a little much for Manta's needs.