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luac_proc.py
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luac_proc.py
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# ----------------------------------------------------------------------
# Lua 5.2 bytecode processor module
# Copyright (c) 2018 [email protected]
# ALL RIGHTS RESERVED.
import sys
from ida_bytes import *
from ida_ua import *
from ida_idp import *
from ida_auto import *
from ida_nalt import *
import ida_frame
from ida_funcs import *
from ida_lines import *
from ida_problems import *
import ida_offset
from ida_segment import *
from ida_name import *
from ida_netnode import *
import idautils
import idc
# extract bitfield occupying bits high..low from val (inclusive, start from 0)
def GET_BITS(val, low, high):
return (val>>low) & ((1<<(high-low+1)) - 1)
# extract one bit
def BIT(val, bit):
return (val>>bit) & 1
# sign extend b low bits in x
# from "Bit Twiddling Hacks"
def SIGNEXT(x, b):
m = 1 << (b - 1)
x = x & ((1 << b) - 1)
return (x ^ m) - m
# check if operand is register reg
def is_reg(op, reg):
return op.type == o_reg and op.reg == reg
# check if operand is immediate value val
def is_imm(op, val):
return op.type == o_imm and op.value == val
SIZE_C = 9
SIZE_B = 9
SIZE_Bx = (SIZE_C + SIZE_B)
SIZE_A = 8
SIZE_Ax = (SIZE_C + SIZE_B + SIZE_A)
BITRK = (1 << (SIZE_B - 1))
def ISK(x):
return (x & BITRK)
def INDEXK(r):
return ((r) & ~BITRK)
def CC(r):
if ISK(r):
return 'K'
else:
return 'R'
def CV(r):
if ISK(r):
return INDEXK(r)
else:
return r
PLFM_LUAC = 99
# ----------------------------------------------------------------------
class lua_processor_t(processor_t):
# IDP id ( Numbers above 0x8000 are reserved for the third-party modules)
id = PLFM_LUAC
# Processor features
flag = PR_SEGS | PR_DEFSEG32 | PR_USE64 | PRN_HEX | PR_RNAMESOK | PR_NO_SEGMOVE | PR_TYPEINFO
# Number of bits in a byte for code segments (usually 8)
# IDA supports values up to 32 bits
cnbits = 8
# Number of bits in a byte for non-code segments (usually 8)
# IDA supports values up to 32 bits
dnbits = 8
# short processor names
# Each name should be shorter than 9 characters
psnames = ['Luac']
# long processor names
# No restriction on name lengthes.
plnames = ['Lua Byte code']
# size of a segment register in bytes
segreg_size = 0
# Array of typical code start sequences (optional)
# codestart = ['\x60\x00'] # 60 00 xx xx: MOVqw SP, SP-delta
# Array of 'return' instruction opcodes (optional)
# retcodes = ['\x04\x00'] # 04 00: RET
# You should define 2 virtual segment registers for CS and DS.
# Let's call them rVcs and rVds.
# icode of the first instruction
instruc_start = 0
#
# Size of long double (tbyte) for this processor
# (meaningful only if ash.a_tbyte != NULL)
#
tbyte_size = 0
segstarts = {}
segends = {}
# only one assembler is supported
assembler = {
# flag
'flag' : ASH_HEXF3 | AS_UNEQU | AS_COLON | ASB_BINF4 | AS_N2CHR,
# user defined flags (local only for IDP)
# you may define and use your own bits
'uflag' : 0,
# Assembler name (displayed in menus)
'name': "Lua bytecode assembler",
# org directive
'origin': "org",
# end directive
'end': "end",
# comment string (see also cmnt2)
'cmnt': ";",
# ASCII string delimiter
'ascsep': "\"",
# ASCII char constant delimiter
'accsep': "'",
# ASCII special chars (they can't appear in character and ascii constants)
'esccodes': "\"'",
#
# Data representation (db,dw,...):
#
# ASCII string directive
'a_ascii': "db",
# byte directive
'a_byte': "db",
# word directive
'a_word': "dw",
# remove if not allowed
'a_dword': "dd",
# remove if not allowed
'a_qword': "dq",
# remove if not allowed
'a_oword': "xmmword",
# float; 4bytes; remove if not allowed
'a_float': "dd",
# double; 8bytes; NULL if not allowed
'a_double': "dq",
# long double; NULL if not allowed
'a_tbyte': "dt",
# array keyword. the following
# sequences may appear:
# #h - header
# #d - size
# #v - value
# #s(b,w,l,q,f,d,o) - size specifiers
# for byte,word,
# dword,qword,
# float,double,oword
'a_dups': "#d dup(#v)",
# uninitialized data directive (should include '%s' for the size of data)
'a_bss': "%s dup ?",
# 'seg ' prefix (example: push seg seg001)
'a_seg': "seg",
# current IP (instruction pointer) symbol in assembler
'a_curip': "$",
# "public" name keyword. NULL-gen default, ""-do not generate
'a_public': "public",
# "weak" name keyword. NULL-gen default, ""-do not generate
'a_weak': "weak",
# "extrn" name keyword
'a_extrn': "extrn",
# "comm" (communal variable)
'a_comdef': "",
# "align" keyword
'a_align': "align",
# Left and right braces used in complex expressions
'lbrace': "(",
'rbrace': ")",
# % mod assembler time operation
'a_mod': "%",
# & bit and assembler time operation
'a_band': "&",
# | bit or assembler time operation
'a_bor': "|",
# ^ bit xor assembler time operation
'a_xor': "^",
# ~ bit not assembler time operation
'a_bnot': "~",
# << shift left assembler time operation
'a_shl': "<<",
# >> shift right assembler time operation
'a_shr': ">>",
# size of type (format string)
'a_sizeof_fmt': "size %s",
} # Assembler
# ----------------------------------------------------------------------
def dt_to_width(self, dt):
"""Returns OOFW_xxx flag given a dt_xxx"""
if dt == dt_byte: return OOFW_8
elif dt == dt_word: return OOFW_16
elif dt == dt_dword: return OOFW_32
elif dt == dt_qword: return OOFW_64
# ----------------------------------------------------------------------
# Instruction decoding
# R(x) - register
# Kst(x) - constant (in constant table)
# RK(x) == if ISK(x) then Kst(INDEXK(x)) else R(x)
# ----------------------------------------------------------------------
def decode_MOVE(self, insn, a, b, c, ax, bx, sbx):
"""
OP_MOVE,/* A B R(A) := R(B) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
return True
def decode_LOADK(self, insn, a, b, c, ax, bx, sbx):
"""
OP_LOADK,/* A Bx R(A) := Kst(Bx) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_displ
insn.Op2.reg = bx
insn.Op2.dtype = dt_dword
return True
def cmt_LOADK(self, insn):
return "hello LOADK"
def decode_LOADKX(self, insn, a, b, c, ax, bx, sbx):
"""
OP_LOADKX,/* A R(A) := Kst(extra arg) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
return True
def decode_LOADBOOL(self, insn, a, b, c, ax, bx, sbx):
"""
OP_LOADBOOL,/* A B C R(A) := (Bool)B; if (C) pc++ */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = b
insn.Op2.dtype = dt_dword
insn.Op3.type = o_imm
insn.Op3.value = b
insn.Op3.dtype = dt_dword
return True
def decode_LOADNIL(self, insn, a, b, c, ax, bx, sbx):
"""
OP_LOADNIL,/* A B R(A), R(A+1), ..., R(A+B) := nil */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = b
insn.Op2.dtype = dt_dword
return True
def decode_GETUPVAL(self, insn, a, b, c, ax, bx, sbx):
"""
OP_GETUPVAL,/* A B R(A) := UpValue[B] */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_displ
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
insn.Op2.specval = 1
return True
def decode_GETTABUP(self, insn, a, b, c, ax, bx, sbx):
"""
A B C R(A) := UpValue[B][RK(C)]
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_displ
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
insn.Op2.specval = 1
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_GETTABLE(self, insn, a, b, c, ax, bx, sbx):
"""
OP_GETTABLE,/* A B C R(A) := R(B)[RK(C)] */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_SETTABUP(self, insn, a, b, c, ax, bx, sbx):
"""
OP_SETTABUP,/* A B C UpValue[A][RK(B)] := RK(C) */
"""
insn.Op1.type = o_displ
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op1.specval = 1
if (ISK(b)):
insn.Op2.type = o_displ
insn.Op2.reg = CV(b)
else:
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_SETUPVAL(self, insn, a, b, c, ax, bx, sbx):
"""
OP_SETUPVAL,/* A B UpValue[B] := R(A) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_displ
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
insn.Op2.specval = 1
return True
def decode_SETTABLE(self, insn, a, b, c, ax, bx, sbx):
"""
OP_SETTABLE,/* A B C R(A)[RK(B)] := RK(C) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
if (ISK(b)):
insn.Op2.type = o_displ
insn.Op2.reg = CV(b)
else:
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_NEWTABLE(self, insn, a, b, c, ax, bx, sbx):
"""
OP_NEWTABLE,/* A B C R(A) := {} (size = B,C) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = b
insn.Op2.dtype = dt_dword
insn.Op3.type = o_imm
insn.Op3.value = c
insn.Op3.dtype = dt_dword
return True
def decode_SELF(self, insn, a, b, c, ax, bx, sbx):
"""
OP_SELF,/* A B C R(A+1) := R(B); R(A) := R(B)[RK(C)] */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a + 1
insn.Op1.dtype = dt_dword
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_MATH(self, insn, a, b, c, ax, bx, sbx):
"""
OP_ADD,/* A B C R(A) := RK(B) + RK(C) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
if (ISK(b)):
insn.Op2.type = o_displ
insn.Op2.reg = CV(b)
else:
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_UNM(self, insn, a, b, c, ax, bx, sbx):
"""
OP_UNM,/* A B R(A) := -R(B) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
return True
def decode_NOT(self, insn, a, b, c, ax, bx, sbx):
"""
OP_NOT,/* A B R(A) := not R(B) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
return True
def decode_LEN(self, insn, a, b, c, ax, bx, sbx):
"""
OP_LEN,/* A B R(A) := length of R(B) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
return True
def decode_CONCAT(self, insn, a, b, c, ax, bx, sbx):
"""
OP_CONCAT,/* A B C R(A) := R(B).. ... ..R(C) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_JMP(self, insn, a, b, c, ax, bx, sbx):
"""
OP_JMP,/* A sBx pc+=sBx; if (A) close all upvalues >= R(A - 1) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = sbx
insn.Op2.dtype = dt_dword
return True
def decode_EQ(self, insn, a, b, c, ax, bx, sbx):
"""
OP_EQ,/* A B C if ((RK(B) == RK(C)) ~= A) then pc++ */
"""
insn.Op1.type = o_imm
insn.Op1.value = a
insn.Op1.dtype = dt_dword
if (ISK(b)):
insn.Op2.type = o_displ
insn.Op2.reg = CV(b)
else:
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_LT(self, insn, a, b, c, ax, bx, sbx):
"""
OP_LT,/* A B C if ((RK(B) < RK(C)) ~= A) then pc++ */
"""
insn.Op1.type = o_imm
insn.Op1.value = a
insn.Op1.dtype = dt_dword
if (ISK(b)):
insn.Op2.type = o_displ
insn.Op2.reg = CV(b)
else:
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_LE(self, insn, a, b, c, ax, bx, sbx):
"""
OP_LE,/* A B C if ((RK(B) <= RK(C)) ~= A) then pc++ */
"""
insn.Op1.type = o_imm
insn.Op1.value = a
insn.Op1.dtype = dt_dword
if (ISK(b)):
insn.Op2.type = o_displ
insn.Op2.reg = CV(b)
else:
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
if (ISK(c)):
insn.Op3.type = o_displ
insn.Op3.reg = CV(c)
else:
insn.Op3.type = o_reg
insn.Op3.reg = c
insn.Op3.dtype = dt_dword
return True
def decode_TEST(self, insn, a, b, c, ax, bx, sbx):
"""
OP_TEST,/* A C if not (R(A) <=> C) then pc++ */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = c
insn.Op2.dtype = dt_dword
return True
def decode_TESTSET(self, insn, a, b, c, ax, bx, sbx):
"""
OP_TESTSET,/* A B C if (R(B) <=> C) then R(A) := R(B) else pc++ */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_reg
insn.Op2.reg = b
insn.Op2.dtype = dt_dword
insn.Op3.type = o_imm
insn.Op3.value = c
insn.Op3.dtype = dt_dword
return True
def decode_CALL(self, insn, a, b, c, ax, bx, sbx):
"""
OP_CALL,/* A B C R(A), ... ,R(A+C-2) := R(A)(R(A+1), ... ,R(A+B-1)) */
OP_TAILCALL,/* A B C return R(A)(R(A+1), ... ,R(A+B-1)) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = b
insn.Op2.dtype = dt_dword
insn.Op3.type = o_imm
insn.Op3.value = c
insn.Op3.dtype = dt_dword
return True
def decode_RETURN(self, insn, a, b, c, ax, bx, sbx):
"""
OP_RETURN,/* A B return R(A), ... ,R(A+B-2) (see note) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = b
insn.Op2.dtype = dt_dword
return True
def decode_FORLOOP(self, insn, a, b, c, ax, bx, sbx):
"""
OP_FORLOOP,/* A sBx R(A)+=R(A+2);
if R(A) <?= R(A+1) then { pc+=sBx; R(A+3)=R(A) }*/
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = sbx
insn.Op2.dtype = dt_dword
return True
def decode_FORPREP(self, insn, a, b, c, ax, bx, sbx):
"""
OP_FORPREP,/* A sBx R(A)-=R(A+2); pc+=sBx */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = sbx
insn.Op2.dtype = dt_dword
return True
def decode_TFORCALL(self, insn, a, b, c, ax, bx, sbx):
"""
OP_TFORCALL,/* A C R(A+3), ... ,R(A+2+C) := R(A)(R(A+1), R(A+2)); */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = c
insn.Op2.dtype = dt_dword
return True
def decode_TFORLOOP(self, insn, a, b, c, ax, bx, sbx):
"""
OP_TFORLOOP,/* A sBx if R(A+1) ~= nil then { R(A)=R(A+1); pc += sBx }*/
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = sbx
insn.Op2.dtype = dt_dword
return True
def decode_SETLIST(self, insn, a, b, c, ax, bx, sbx):
"""
OP_SETLIST,/* A B C R(A)[(C-1)*FPF+i] := R(A+i), 1 <= i <= B */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = b
insn.Op2.dtype = dt_dword
insn.Op3.type = o_imm
insn.Op3.value = c
insn.Op3.dtype = dt_dword
return True
def decode_CLOSURE(self, insn, a, b, c, ax, bx, sbx):
"""
OP_CLOSURE,/* A Bx R(A) := closure(KPROTO[Bx]) */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = bx
insn.Op2.dtype = dt_dword
return True
def decode_VARARG(self, insn, a, b, c, ax, bx, sbx):
"""
OP_VARARG,/* A B R(A), R(A+1), ..., R(A+B-2) = vararg */
"""
insn.Op1.type = o_reg
insn.Op1.reg = a
insn.Op1.dtype = dt_dword
insn.Op2.type = o_imm
insn.Op2.value = b
insn.Op2.dtype = dt_dword
return True
def decode_EXTRAARG(self, insn, a, b, c, ax, bx, sbx):
"""
OP_EXTRAARG/* Ax extra (larger) argument for previous opcode */
"""
insn.Op1.type = o_imm
insn.Op1.value = ax
insn.Op1.dtype = dt_dword
return True
# ----------------------------------------------------------------------
# Processor module callbacks
#
# ----------------------------------------------------------------------
def notify_get_frame_retsize(self, func_ea):
"""
Get size of function return address in bytes
for EBC it's 8 bytes of the actual return address
plus 8 bytes of the saved frame address
"""
return 16
def notify_may_be_func(self, insn, state):
"""
can a function start here?
the instruction is in 'cmd'
arg: state -- autoanalysis phase
state == 0: creating functions
== 1: creating chunks
returns: probability 0..100
"""
print("notify_may_be_func called. ea:%x, state:%d" % (insn.ea, state))
if self.check_is_segstart(insn.ea):
return 100
else:
return 10
def notify_add_func(self, func_ea):
"""
The kernel has added a function.
@param func_ea: function start EA
@return: Nothing
"""
print("notify_add_func called. func_ea:%x" % func_ea)
# ----------------------------------------------------------------------
def notify_get_autocmt(self, insn):
"""
Get instruction comment. 'insn' describes the instruction in question
@return: None or the comment string
"""
print("notify_get_autocmt called:%x ea:%x" % insn.ea)
if 'cmt' in self.instruc[insn.itype]:
return self.instruc[insn.itype]['cmt'](insn)
# ----------------------------------------------------------------------
def notify_can_have_type(self, op):
"""
Can the operand have a type as offset, segment, decimal, etc.
(for example, a register AX can't have a type, meaning that the user can't
change its representation. see bytes.hpp for information about types and flags)
Returns: bool
"""
return op.type in [o_imm, o_displ, o_mem]
# ----------------------------------------------------------------------
def notify_is_align_insn(self, ea):
"""
Is the instruction created only for alignment purposes?
Returns: number of bytes in the instruction
"""
#print("notify_is_align_insn called\n")
return 0
# ----------------------------------------------------------------------
def notify_newfile(self, filename):
print("notify_newfile called\n")
self.init_seginfo()
# ----------------------------------------------------------------------
def notify_oldfile(self, filename):
pass
# ----------------------------------------------------------------------
def notify_out_header(self, ctx):
"""function to produce start of disassembled text"""
ctx.out_line("; Lua 52, unit size: %d bits" % (self.PTRSZ*8))
ctx.flush_outbuf(0)
def init_seginfo(self):
#print("seg len:%d\n" % len(list(idautils.Segments())))
for seg in idautils.Segments():
segname = idc.SegName(seg)
if segname.startswith('func_'):
self.segstarts[idc.SegStart(seg)] = segname
self.segends[idc.SegEnd(seg)] = segname
#print("segname:%s\n" % segname)
#print("add_func() called ret:%d" % add_func(idc.SegStart(seg), idc.SegEnd(seg)))
def check_is_segstart(self, ea):
return ea in self.segstarts
def check_is_segend(self, ea):
return ea in self.segends
# ----------------------------------------------------------------------
def notify_emu(self, insn):
"""
Emulate instruction, create cross-references, plan to analyze
subsequent instructions, modify flags etc. Upon entrance to this function
all information about the instruction is in 'insn' structure.
If zero is returned, the kernel will delete the instruction.
"""
print("notify_emu called. ea:%x" % insn.ea)
# for k in self.segstarts.keys():
# print(self.segstarts[k])
return 1
def notify_setup_til(self):
"""Setup default type libraries (called after loading a new file into the database)
The processor module may load tils, setup memory model and perform other actions required to set up the type system
@return: None
"""
print("notify_setup_til called.")
# ----------------------------------------------------------------------
def notify_out_operand(self, ctx, op):
"""
Generate text representation of an instructon operand.
This function shouldn't change the database, flags or anything else.
All these actions should be performed only by u_emu() function.
The output text is placed in the output buffer initialized with init_output_buffer()
This function uses out_...() functions from ua.hpp to generate the operand text
Returns: 1-ok, 0-operand is hidden.
"""
#print("notify_out_operand called. op:%x" % op.type)
optype = op.type
fl = op.specval
def_arg = is_defarg(get_flags(ctx.insn.ea), op.n)
if optype == o_reg:
ctx.out_register(self.reg_names[op.reg])
elif optype == o_imm:
# for immediate loads, use the transfer width (type of first operand)
if op.n == 1:
width = self.dt_to_width(ctx.insn.Op1.dtype)
else:
width = OOFW_32 if self.PTRSZ == 4 else OOFW_64
ctx.out_value(op, OOFW_IMM | width)