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chapter6.tex
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% Free range VHDL
% Authors: Bryan Mealy, Fabrizio Tappero
% Date: January, 2023
% URL: https://github.com/fabriziotappero/Free-Range-VHDL-book
% (C) 2018-2023 B. Mealy, F. Tappero
%
% !TEX root = master.tex
%
\chapter{VHDL Operators}
So far we have only implicitly mentioned the operators available in VHDL. This section presents a complete list of operators as well as a few examples of their use. A complete list of operators is shown in Table \ref{vhdl_operators_table}. This is followed by brief descriptions of some of the less obvious operators. Although you may not have an immediate need to use some of these operators, you should be aware that they exist. And although there are some special things you should know about some of these operators, not too much information is presented in this section.
\begin{table}
\centering
\footnotesize\textsf{\begin{tabular}{l|lllllll}
Operator type\\
\hline
\rowcolor{light-gray} logical & and & or & nand & nor & xor & xnor \\
relational & = & /= & $<$ & $<=$ & $>$ & $>=$ \\
\rowcolor{light-gray} shift & sll & srl & sla & sra & rol & ror \\
adding & $+$ & $-$ & \& & & & \\
\rowcolor{light-gray} sign & $+$ & $-$ & & & & \\
multiplying & * & / & mod & rem \\
\rowcolor{light-gray} miscellaneous & ** & abs & not & & & \\
\hline
\end{tabular}}
\caption{VHDL operators.}
\label{vhdl_operators_table}
\end{table}
Operators in VHDL are grouped into seven different types: logical, relational, shift, adding, sign, multiplying, and miscellaneous. The ordering of this list is somewhat important because it presents the operators in order of increasing precedence. We said "somewhat" because your VHDL code should never rely on operator precedence to describe circuit behavior. Reliance on obscure precedence rules tends to make the VHDL code cryptic and hard to understand. A liberal use of parentheses is a better approach to VHDL coding.
The first column of Table \ref{vhdl_operators_table} lists the operators from lowest to highest precedence, where logical operators have the lowest precedence. Although there is a precedence order for the types of operators, there is no precedence order within each type of operator. In other words, the operators appearing in the rows are presented in no particular order. This means that the operators are applied to the given operands in the order they appear in the associated VHDL code.
\section{Logical Operators}
The logical operators are generally self-explanatory in nature. They have also been used throughout this book. The only thing worthy of note is that the \texttt{not} operator is not technically a logical operator and is grouped among the miscellaneous operators, which have the highest precedence.
\section{Relational Operators}
The relational operators are generally self-explanatory in nature too. Many of them have been used in this book. A complete list of relational operators is provided in Table \ref{relational_operators_table}.
\begin{table}
\centering
\footnotesize\textsf{\begin{tabular}{l|l|l}
Operator & Name & Explanation\\
\hline
\rowcolor{light-gray} \texttt{A = B} & equivalence & is A equivalent to B? \\
\texttt{A /= B} & non-equivalence & is A not equivalent to B? \\
\rowcolor{light-gray} \texttt{A < B} & less than & is A less than B? \\
\texttt{A <= B} &less than or equal & is A less than or equal to B? \\
\rowcolor{light-gray} \texttt{A > B} & greater than & is A greater than B? \\
\texttt{A >= B} & greater than or equal & is A greater than or equal to B? \\
\hline
\end{tabular}}
\caption{VHDL relational operators with brief explanations.}
\label{relational_operators_table}
\end{table}
\section{Shift Operator}
Available from \texttt{ieee.numeric\_std} or \texttt{ieee.numeric\_bit}, there are three types of shift operators: logical shift, arithmetic shift, and rotations. Although these operators basically shift bits either left-to-right or right-to-left, there are a few basic differences which are listed below. The shift operators are listed in Table \ref{shift_operators_table}.
\begin{my_list}
\item Both logical shifts introduce zeros into one end of the operand that is affected by the shift operation. In other words, zeros are fed into one end of the operand while bits are essentially lost from the other end. The difference between logical and arithmetic shifts is that in arithmetic shift, the sign-bit is never changed and the bit that is fed into one end can differ. Hence, for arithmetic shift lefts, the last right bit is stuffed to the right end of the operand. For arithmetic shift rights, the sign-bit (the left-most bit) is propagated right (the value of the left-most bit is fed into the left end of the operand).
\item Rotate operators grab a bit from one end of the word and stuff it into the other end. This operation is done independently of the value of the individual bits in the operand.
\end{my_list}
\begin{table}
\centering
\footnotesize\textsf{\begin{tabular}{l|l|l|l|l}
Operator & \multicolumn{2}{c|}{Name} & Example~& Result \\
\hline
\multirow{2}{*}{logical} & sll & shift left logical & result $<=$ "10010101" sll 2 & "01010100" \\
& srl & shift right logical & result $<=$ "10010101" srl 3 & "00010010" \\
\hline
\multirow{2}{*}{arithmetic} & sla & shift left arithmetic & result $<=$ "10010101" sla 3 & "10101111" \\
& sra & shift right arithmetic & result $<=$ "10010101" sra 2 & "11100101" \\
\hline
\multirow{2}{*}{rotate} & rol & rotate left & result $<=$ "10100011" rol 2 & "10001110" \\
& ror & rotate right & result $<=$ "10100011" ror 2 & "11101000" \\
\hline
\end{tabular}}
\caption{VHDL shift operators with examples.}
\label{shift_operators_table}
\end{table}
\section{Other Operators}
The other groups of operators are generally used with numeric types. Since this section does not present numerical operations in detail, the operators are briefly listed below in Table \ref{shift_other_operators_table}. Special attention is given to the \texttt{\&}, \texttt{mod}, and \texttt{rem} operators. These operators are also limited to operating on specific types, which are also not listed here.
\begin{table}[!b]
\centering
\footnotesize\textsf{\begin{tabular}{l|l|l|l}
\multicolumn{2}{c|}{Operator} & Name & Comment \\
\hline
\multirow{3}{*}{adding} & \texttt{+} & addition & \\
& \texttt{-} & subtraction & \\
& \texttt{\&} & concatenation & can operate only on specific types\\
\hline
\multirow{2}{*}{sign} & \texttt{+} & identity & unary operator\\
& \texttt{-} & negation & unary operator \\
\hline
\multirow{4}{*}{multiplying} & \texttt{*} & multiplication &\\
& \texttt{/} & division & often limited to powers of two\\
& \texttt{mod} & modulus & can operate only on specific types\\
& \texttt{rem} & remainder & can operate only on specific types\\
\hline
\multirow{2}{*}{miscellaneous} & \texttt{**} & exponentiation & often limited to powers of two\\
& \texttt{abs} & absolute value & \\
\hline
\end{tabular}}
\caption{All the other VHDL operators not listed so far.}
\label{shift_other_operators_table}
\end{table}
\section{Concatenation Operator}
The concatenation operator \texttt{\&} is often a useful operator when dealing with digital circuits. There are many times when you will find a need to tack together two separate values. The concatenation operator has been seen in some previous example solutions. Some more examples of the concatenation operators are presented in Listing~\ref{concat_operator}.
\noindent
\begin{minipage}{0.99\linewidth}
\begin{lstlisting}[label=concat_operator, caption=Examples of the concatenation operator.]
signal A_val, B_val : std_logic_vector(3 downto 0);
signal C_val : std_logic_vector(5 downto 0);
signal D_val : std_logic_vector(7 downto 0);
------
C_val <= A_val & "00";
C_val <= "11" & B_val;
C_val <= '1' & A_val & '0';
D_val <= "0001" & C_val(3 downto 0);
D_val <= A_val & B_val;
\end{lstlisting}
\end{minipage}
\section{Modulus and Remainder Operators}
Both the remainder operator \texttt{rem} and the modulus operator \texttt{mod} are applied to integers types and both give back an integer type. There is often confusion about the differences between the two operators and the difference in their operation on negative and positive numbers. The definitions that VHDL uses for these operators are shown in Table \ref{rem_mod_def} while a few examples of these operators are provided in Table \ref{rem_mod_example}. A general rule followed by many programmers is to avoid using the \texttt{mod} operator when dealing with negative numbers. As you can see from the examples below, answers are sometime counter-intuitive.
\begin{table}
\centering
\footnotesize\textsf{\begin{tabular}{l|l|l}
Operator & Name & Satisfies this Conditions \\
\hline
\multicolumn{1}{c|}{\texttt{rem}} & \multicolumn{1}{c|}{remainder} & 1. sign of (X \texttt{rem} Y) is the same as X \\
&& 2. abs (X \texttt{rem} Y) $<$ \texttt{abs} (Y) \\
&& 3. (X \texttt{rem} Y) = (X - (X / Y) * Y) \\
\hline
\multicolumn{1}{c|}{\texttt{mod}} & \multicolumn{1}{c|}{modulus} & 1. sign of (X \texttt{mod} Y) is the same as Y \\
&& 2. abs (X \texttt{mod} Y) $<$ \texttt{abs} (Y) \\
&& 3. (X \texttt{mod} Y) = ( X * ( Y - N )) \\
&& for some integer N\\
\hline
\end{tabular}}
\caption{Definitions of \texttt{rem} and \texttt{mod} operators. (\texttt{abs} = absolute value)}
\label{rem_mod_def}
\end{table}
\begin{table}[!b]
\centering
\footnotesize\textsf{\begin{tabular}{c|c}
\texttt\textbf{rem} & \texttt\textbf{mod}\\
\hline
\rowcolor{light-gray} 8 rem 5 = 3 & 8 mod 5 = 3\\
\hline
-8 rem 5 = -3 & -8 mod 5 = 2 \\
\hline
\rowcolor{light-gray} 8 rem -5 = 3 & 8 mod -5 = -2 \\
\hline
-8 rem -5 = -3 & -8 mod -5 = -3 \\
\hline
\end{tabular}}
\caption{Example~of \texttt{rem} and \texttt{mod} operators.}
\label{rem_mod_example}
\end{table}
\section{Review of Almost Everything Up to Now}
VHDL is a language used to design, test and implement digital circuits. The basic design units in VHDL are the entity and the architecture which exemplify the general hierarchical approach of VHDL. The entity represents the black-box diagram of the circuit or the interface of the circuit to the outside world while the architecture encompasses all the other details of how the circuit behaves.
The VHDL architecture is made of statements that describe the behavior of the digital circuit. Because this is a hardware description language, statements in VHDL are primarily considered to execute concurrently. The idea of concurrency is one of the main themes of VHDL as one would expect since a digital circuit can be modeled as a set of logic gates that operate concurrently.
The main concurrent statement types in VHDL are the concurrent signal assignment statement, the conditional signal assignment statement, the selected signal assignment statement and the process statement. The process statement is a concurrent statement which is constituted of sequential statements exclusively. The main types of sequential statements are the signal assignment statement, the \texttt{if} statement and the \texttt{case} statement. The \texttt{if} statement is a sequential version of conditional signal assignment statement while the \texttt{case} statement is a sequential version of the selected signal assignment statement.
Coding styles in VHDL fall under the category of data-flow, behavioral and structural models. Exclusive use of process statements indicates a behavioral model. The use of concurrent, conditional and selective signal assignment indicate the use of a data-flow model. VHDL code describing more complex digital circuits will generally contain both features of all of these types of modeling.
Since you should make no effort whatsoever to memorize VHDL syntax, it is recommended that a cheat sheet always be kept next to you as you perform VHDL modeling. Developing a true understanding of VHDL is what is going to make you into a good hardware designer. The ability to memorize VHDL syntax proves almost nothing.