cornigera.core

CAPI=2:
name: mutalabs:processor:cornigera:0.1
description: Risc V implementation

filesets:
  common:
    files:
      - rtl/cornigera_pkg.sv
    file_type: systemVerilogSource

  registers:
    files:
      - rtl/registers.sv
    file_type: systemVerilogSource

  rtl:
    files:
      - rtl/cornigera.sv
    file_type: systemVerilogSource

  verilator_tb:
    files: [tb/tb.cpp : {file_type : cppSource}]

  registers_tb:
    files: 
      - tb/registers_tb.cpp
    depend: [mutalabs:test:tbpp:0.1]
    file_type : cppSource

parameters:
  XLEN:
    datatype: int
    default: 32
    paramtype: vlogdefine

targets:
  sim:
    default_tool: verilator
    tools:
      verilator:
        verilator_options : [-sv, --trace, -Wno-fatal]
    toplevel : cornigera

  sim_register_file:
    default_tool: verilator
    parameters: [XLEN]
    filesets: [common, registers, registers_tb]
    tools:
      verilator:
        verilator_options : [-sv, -Wall, -Wno-fatal, --trace,  -CFLAGS -std=c++17]
    toplevel: registers 


  default:
    filesets: [rtl]