From 89057c566a13846543b4ff156cabe693d8245e2b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:21 +0300 Subject: [PATCH 001/261] [Xtensa] Initial support of the ALU operations. Initial codegen support for simple ALU operations. --- llvm/lib/Target/Xtensa/CMakeLists.txt | 11 + llvm/lib/Target/Xtensa/Xtensa.h | 30 ++ llvm/lib/Target/Xtensa/Xtensa.td | 6 + llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 41 +++ llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 42 +++ llvm/lib/Target/Xtensa/XtensaCallingConv.td | 34 ++ .../lib/Target/Xtensa/XtensaFrameLowering.cpp | 44 +++ llvm/lib/Target/Xtensa/XtensaFrameLowering.h | 34 ++ llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 86 +++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 314 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 65 ++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 27 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 43 +++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 3 +- llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp | 63 ++++ llvm/lib/Target/Xtensa/XtensaMCInstLower.h | 43 +++ llvm/lib/Target/Xtensa/XtensaOperators.td | 15 + llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 70 ++++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.h | 56 ++++ llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 46 +++ llvm/lib/Target/Xtensa/XtensaSubtarget.h | 66 ++++ .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 30 +- llvm/lib/Target/Xtensa/XtensaTargetMachine.h | 6 + 23 files changed, 1172 insertions(+), 3 deletions(-) create mode 100644 llvm/lib/Target/Xtensa/Xtensa.h create mode 100644 llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaAsmPrinter.h create mode 100644 llvm/lib/Target/Xtensa/XtensaCallingConv.td create mode 100644 llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaFrameLowering.h create mode 100644 llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaISelLowering.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaISelLowering.h create mode 100644 llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaInstrInfo.h create mode 100644 llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaMCInstLower.h create mode 100644 llvm/lib/Target/Xtensa/XtensaOperators.td create mode 100644 llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaRegisterInfo.h create mode 100644 llvm/lib/Target/Xtensa/XtensaSubtarget.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaSubtarget.h diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index 7192f7392072b3..bb1e09cb0652ec 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -4,6 +4,8 @@ set(LLVM_TARGET_DEFINITIONS Xtensa.td) tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer) +tablegen(LLVM XtensaGenCallingConv.inc -gen-callingconv) +tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel) tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info) tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter) @@ -13,6 +15,14 @@ tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget) add_public_tablegen_target(XtensaCommonTableGen) add_llvm_target(XtensaCodeGen + XtensaAsmPrinter.cpp + XtensaFrameLowering.cpp + XtensaInstrInfo.cpp + XtensaISelDAGToDAG.cpp + XtensaISelLowering.cpp + XtensaMCInstLower.cpp + XtensaRegisterInfo.cpp + XtensaSubtarget.cpp XtensaTargetMachine.cpp LINK_COMPONENTS @@ -20,6 +30,7 @@ add_llvm_target(XtensaCodeGen CodeGen Core MC + SelectionDAG Support Target XtensaDesc diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h new file mode 100644 index 00000000000000..6f258654bd6cec --- /dev/null +++ b/llvm/lib/Target/Xtensa/Xtensa.h @@ -0,0 +1,30 @@ +//===- Xtensa.h - Top-level interface for Xtensa representation -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the entry points for global functions defined in +// the LLVM Xtensa back-end. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSA_H +#define LLVM_LIB_TARGET_XTENSA_XTENSA_H + +#include "MCTargetDesc/XtensaMCTargetDesc.h" +#include "llvm/PassRegistry.h" +#include "llvm/Support/CodeGen.h" + +namespace llvm { +class XtensaTargetMachine; +class FunctionPass; + +FunctionPass *createXtensaISelDag(XtensaTargetMachine &TM, + CodeGenOptLevel OptLevel); +} // namespace llvm +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSA_H */ diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index b953540be94de0..460a15e808b3a4 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -35,6 +35,12 @@ def : Proc<"generic", []>; include "XtensaRegisterInfo.td" +//===----------------------------------------------------------------------===// +// Calling Convention Description +//===----------------------------------------------------------------------===// + +include "XtensaCallingConv.td" + //===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp new file mode 100644 index 00000000000000..e633b77ff62078 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -0,0 +1,41 @@ +//===- XtensaAsmPrinter.cpp Xtensa LLVM Assembly Printer ------------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains a printer that converts from our internal representation +// of machine-dependent LLVM code to GAS-format Xtensa assembly language. +// +//===----------------------------------------------------------------------===// + +#include "XtensaAsmPrinter.h" +#include "XtensaMCInstLower.h" +#include "TargetInfo/XtensaTargetInfo.h" +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/CodeGen/MachineModuleInfoImpls.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCSymbolELF.h" +#include "llvm/MC/TargetRegistry.h" + +using namespace llvm; + +void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) { + XtensaMCInstLower Lower(MF->getContext(), *this); + MCInst LoweredMI; + Lower.lower(MI, LoweredMI); + EmitToStreamer(*OutStreamer, LoweredMI); +} + +// Force static initialization. +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmPrinter() { + RegisterAsmPrinter A(getTheXtensaTarget()); +} diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h new file mode 100644 index 00000000000000..d23fa5dbeadb21 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h @@ -0,0 +1,42 @@ +//===- XtensaAsmPrinter.h - Xtensa LLVM Assembly Printer --------*- C++-*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Xtensa Assembly printer class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H +#define LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H + +#include "XtensaTargetMachine.h" +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/Support/Compiler.h" + +namespace llvm { +class MCStreamer; +class MachineBasicBlock; +class MachineInstr; +class Module; +class raw_ostream; + +class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter { + const MCSubtargetInfo *STI; +public: + explicit XtensaAsmPrinter(TargetMachine &TM, + std::unique_ptr Streamer) + : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {} + + // Override AsmPrinter. + StringRef getPassName() const override { return "Xtensa Assembly Printer"; } + void emitInstruction(const MachineInstr *MI) override; +}; +} // end namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaCallingConv.td b/llvm/lib/Target/Xtensa/XtensaCallingConv.td new file mode 100644 index 00000000000000..c39eb665b4d33c --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaCallingConv.td @@ -0,0 +1,34 @@ +//===- XtensaCallingConv.td - Xtensa Calling Conventions -*- tablegen ---*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// This describes the calling conventions for the Xtensa ABI. +//===----------------------------------------------------------------------===// + +/// CCIfAlign - Match of the original alignment of the arg +class CCIfAlign + : CCIf; + +//===----------------------------------------------------------------------===// +// Xtensa return value calling convention +//===----------------------------------------------------------------------===// +def RetCC_Xtensa : CallingConv<[ + CCIfType<[i1, i8, i16], CCPromoteToType>, + CCIfType<[f32], CCBitConvertToType>, + + //First two return values go in a2, a3, a4, a5 + CCIfType<[i32], CCAssignToReg<[A2, A3, A4, A5]>>, + CCIfType<[f32], CCAssignToReg<[A2, A3, A4, A5]>>, + CCIfType<[i64], CCAssignToRegWithShadow<[A2, A4], [A3, A5]>> +]>; + +//===----------------------------------------------------------------------===// +// Callee-saved register lists. +//===----------------------------------------------------------------------===// + +def CSR_Xtensa : CalleeSavedRegs<(add A0, A12, A13, A14, A15)>; diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp new file mode 100644 index 00000000000000..b201b99813ced1 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -0,0 +1,44 @@ +//===- XtensaFrameLowering.cpp - Xtensa Frame Information -----------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the Xtensa implementation of TargetFrameLowering class. +// +//===----------------------------------------------------------------------===// + +#include "XtensaFrameLowering.h" +#include "XtensaInstrInfo.h" +#include "XtensaSubtarget.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/IR/Function.h" + +using namespace llvm; + +XtensaFrameLowering::XtensaFrameLowering() + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 0, + Align(4)) {} + +// hasFP - Return true if the specified function should have a dedicated frame +// pointer register. This is true if the function has variable sized allocas or +// if frame pointer elimination is disabled. +bool XtensaFrameLowering::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + return MF.getTarget().Options.DisableFramePointerElim(MF) || + MFI.hasVarSizedObjects(); +} + +void XtensaFrameLowering::emitPrologue(MachineFunction &MF, + MachineBasicBlock &MBB) const {} + +void XtensaFrameLowering::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const {} diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h new file mode 100644 index 00000000000000..a5dfc83b940597 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h @@ -0,0 +1,34 @@ +//===- XtensaFrameLowering.h - Define frame lowering for Xtensa --*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===-----------------------------------------------------------------------==// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H +#define LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H + +#include "llvm/CodeGen/TargetFrameLowering.h" + +namespace llvm { +class XtensaTargetMachine; +class XtensaSubtarget; + +class XtensaFrameLowering : public TargetFrameLowering { +public: + XtensaFrameLowering(); + + bool hasFP(const MachineFunction &MF) const override; + + /// emitProlog/emitEpilog - These methods insert prolog and epilog code into + /// the function. + void emitPrologue(MachineFunction &, MachineBasicBlock &) const override; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; +}; + +} // namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp new file mode 100644 index 00000000000000..7250a00f82ce21 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -0,0 +1,86 @@ +//===- XtensaISelDAGToDAG.cpp - A dag to dag inst selector for Xtensa -----===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines an instruction selector for the Xtensa target. +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "XtensaTargetMachine.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SelectionDAGISel.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +#define DEBUG_TYPE "xtensa-isel" + +namespace { + +class XtensaDAGToDAGISel : public SelectionDAGISel { +public: + static char ID; + + XtensaDAGToDAGISel(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel) + : SelectionDAGISel(ID, TM, OptLevel) {} + + // Override MachineFunctionPass. + StringRef getPassName() const override { + return "Xtensa DAG->DAG Pattern Instruction Selection"; + } + + // Override SelectionDAGISel. + void Select(SDNode *Node) override; + + bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset, + int Scale) { + report_fatal_error("MemReg address is not implemented yet"); + return true; + } + + bool selectMemRegAddrISH1(SDValue Addr, SDValue &Base, SDValue &Offset) { + return selectMemRegAddr(Addr, Base, Offset, 1); + } + + bool selectMemRegAddrISH2(SDValue Addr, SDValue &Base, SDValue &Offset) { + return selectMemRegAddr(Addr, Base, Offset, 2); + } + + bool selectMemRegAddrISH4(SDValue Addr, SDValue &Base, SDValue &Offset) { + return selectMemRegAddr(Addr, Base, Offset, 4); + } + +// Include the pieces autogenerated from the target description. +#include "XtensaGenDAGISel.inc" +}; // namespace +} // end anonymous namespace + +char XtensaDAGToDAGISel::ID = 0; + +FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM, + CodeGenOptLevel OptLevel) { + return new XtensaDAGToDAGISel(TM, OptLevel); +} + +void XtensaDAGToDAGISel::Select(SDNode *Node) { + SDLoc DL(Node); + // Dump information about the Node being selected + LLVM_DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); + + // If we have a custom node, we already have selected! + if (Node->isMachineOpcode()) { + LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); + return; + } + + SelectCode(Node); +} diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp new file mode 100644 index 00000000000000..a9ab9e407a4a70 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -0,0 +1,314 @@ +//===- XtensaISelLowering.cpp - Xtensa DAG Lowering Implementation --------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the interfaces that Xtensa uses to lower LLVM code into a +// selection DAG. +// +//===----------------------------------------------------------------------===// + +#include "XtensaISelLowering.h" +#include "XtensaSubtarget.h" +#include "XtensaTargetMachine.h" +#include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +#define DEBUG_TYPE "xtensa-lower" + +XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, + const XtensaSubtarget &STI) + : TargetLowering(tm), Subtarget(STI) { + // Set up the register classes. + addRegisterClass(MVT::i32, &Xtensa::ARRegClass); + + // Set up special registers. + setStackPointerRegisterToSaveRestore(Xtensa::SP); + + setSchedulingPreference(Sched::RegPressure); + + setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrOneBooleanContent); + + setMinFunctionAlignment(Align(4)); + + // Compute derived properties from the register classes + computeRegisterProperties(STI.getRegisterInfo()); +} + +//===----------------------------------------------------------------------===// +// Calling conventions +//===----------------------------------------------------------------------===// + +#include "XtensaGenCallingConv.inc" + +static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State) { + static const MCPhysReg IntRegs[] = {Xtensa::A2, Xtensa::A3, Xtensa::A4, + Xtensa::A5, Xtensa::A6, Xtensa::A7}; + + if (ArgFlags.isByVal()) { + Align ByValAlign = ArgFlags.getNonZeroByValAlign(); + unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), ByValAlign); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); + // Allocate rest of registers, because rest part is not used to pass + // arguments + while (State.AllocateReg(IntRegs)) { + } + return false; + } + + // Promote i8 and i16 + if (LocVT == MVT::i8 || LocVT == MVT::i16) { + LocVT = MVT::i32; + if (ArgFlags.isSExt()) + LocInfo = CCValAssign::SExt; + else if (ArgFlags.isZExt()) + LocInfo = CCValAssign::ZExt; + else + LocInfo = CCValAssign::AExt; + } + + unsigned Reg; + + Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); + bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8)); + + if (ValVT == MVT::i32 || ValVT == MVT::f32) { + Reg = State.AllocateReg(IntRegs); + // If this is the first part of an i64 arg, + // the allocated register must be either A2, A4 or A6. + if (isI64 && (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7)) + Reg = State.AllocateReg(IntRegs); + LocVT = MVT::i32; + } else if (ValVT == MVT::f64) { + // Allocate int register and shadow next int register. + Reg = State.AllocateReg(IntRegs); + if (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7) + Reg = State.AllocateReg(IntRegs); + State.AllocateReg(IntRegs); + LocVT = MVT::i32; + } else + llvm_unreachable("Cannot handle this ValVT."); + + if (!Reg) { + unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); + } else + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + + return false; +} + +CCAssignFn *XtensaTargetLowering::CCAssignFnForCall(CallingConv::ID CC, + bool IsVarArg) const { + return CC_Xtensa_Custom; +} + +// Value is a value of type VA.getValVT() that we need to copy into +// the location described by VA. Return a copy of Value converted to +// VA.getValVT(). The caller is responsible for handling indirect values. +static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, + SDValue Value) { + switch (VA.getLocInfo()) { + case CCValAssign::SExt: + return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); + case CCValAssign::ZExt: + return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value); + case CCValAssign::AExt: + return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); + case CCValAssign::BCvt: + return DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Value); + case CCValAssign::Full: + return Value; + default: + llvm_unreachable("Unhandled getLocInfo()"); + } +} + +SDValue XtensaTargetLowering::LowerFormalArguments( + SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, + const SmallVectorImpl &Ins, const SDLoc &DL, + SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + + // Used with vargs to acumulate store chains. + std::vector OutChains; + + if (IsVarArg) { + llvm_unreachable("Var arg not supported by FormalArguments Lowering"); + } + + // Assign locations to all of the incoming arguments. + SmallVector ArgLocs; + CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); + + CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg)); + + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + // Arguments stored on registers + if (VA.isRegLoc()) { + EVT RegVT = VA.getLocVT(); + const TargetRegisterClass *RC; + + if (RegVT == MVT::i32) { + RC = &Xtensa::ARRegClass; + } else + llvm_unreachable("RegVT not supported by FormalArguments Lowering"); + + // Transform the arguments stored on + // physical registers into virtual ones + unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); + + // If this is an 8 or 16-bit value, it has been passed promoted + // to 32 bits. Insert an assert[sz]ext to capture this, then + // truncate to the right size. + if (VA.getLocInfo() != CCValAssign::Full) { + unsigned Opcode = 0; + if (VA.getLocInfo() == CCValAssign::SExt) + Opcode = ISD::AssertSext; + else if (VA.getLocInfo() == CCValAssign::ZExt) + Opcode = ISD::AssertZext; + if (Opcode) + ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, + DAG.getValueType(VA.getValVT())); + if (VA.getValVT() == MVT::f32) + ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue); + else + ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); + } + + InVals.push_back(ArgValue); + + } else { // !VA.isRegLoc() + // sanity check + assert(VA.isMemLoc()); + + EVT ValVT = VA.getValVT(); + + // The stack pointer offset is relative to the caller stack frame. + int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, + VA.getLocMemOffset(), true); + + if (Ins[VA.getValNo()].Flags.isByVal()) { + // Assume that in this case load operation is created + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + InVals.push_back(FIN); + } else { + // Create load nodes to retrieve arguments from the stack + SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + InVals.push_back(DAG.getLoad( + ValVT, DL, Chain, FIN, + MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI))); + } + } + } + + // All stores are grouped in one node to allow the matching between + // the size of Ins and InVals. This only happens when on varg functions + if (!OutChains.empty()) { + OutChains.push_back(Chain); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); + } + + return Chain; +} + +bool XtensaTargetLowering::CanLowerReturn( + CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, + const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + return CCInfo.CheckReturn(Outs, RetCC_Xtensa); +} + +SDValue +XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, + bool IsVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &OutVals, + const SDLoc &DL, SelectionDAG &DAG) const { + if (IsVarArg) { + report_fatal_error("VarArg not supported"); + } + + MachineFunction &MF = DAG.getMachineFunction(); + + // Assign locations to each returned value. + SmallVector RetLocs; + CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext()); + RetCCInfo.AnalyzeReturn(Outs, RetCC_Xtensa); + + SDValue Glue; + // Quick exit for void returns + if (RetLocs.empty()) + return DAG.getNode(XtensaISD::RET_FLAG, DL, MVT::Other, Chain); + + // Copy the result values into the output registers. + SmallVector RetOps; + RetOps.push_back(Chain); + for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) { + CCValAssign &VA = RetLocs[I]; + SDValue RetValue = OutVals[I]; + + // Make the return register live on exit. + assert(VA.isRegLoc() && "Can only return in registers!"); + + // Promote the value as required. + RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue); + + // Chain and glue the copies together. + unsigned Reg = VA.getLocReg(); + Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue); + Glue = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT())); + } + + // Update chain and glue. + RetOps[0] = Chain; + if (Glue.getNode()) + RetOps.push_back(Glue); + + return DAG.getNode(XtensaISD::RET_FLAG, DL, MVT::Other, RetOps); +} + +SDValue XtensaTargetLowering::LowerOperation(SDValue Op, + SelectionDAG &DAG) const { + switch (Op.getOpcode()) { + default: + llvm_unreachable("Unexpected node to lower"); + } +} + +const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { +#define OPCODE(NAME) \ + case XtensaISD::NAME: \ + return "XtensaISD::" #NAME + switch (Opcode) { + case XtensaISD::FIRST_NUMBER: + break; + case XtensaISD::RET_FLAG: + return "XtensaISD::RET_FLAG"; + } + return NULL; +#undef OPCODE +} diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h new file mode 100644 index 00000000000000..2df2a074fe25fd --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -0,0 +1,65 @@ +//===- XtensaISelLowering.h - Xtensa DAG Lowering Interface -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the interfaces that Xtensa uses to lower LLVM code into a +// selection DAG. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H +#define LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H + +#include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/TargetLowering.h" + +namespace llvm { +namespace XtensaISD { +enum { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + // Return with a flag operand. Operand 0 is the chain operand. + RET_FLAG +}; +} + +class XtensaSubtarget; + +class XtensaTargetLowering : public TargetLowering { +public: + explicit XtensaTargetLowering(const TargetMachine &TM, + const XtensaSubtarget &STI); + + const char *getTargetNodeName(unsigned Opcode) const override; + SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; + SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl &Ins, + const SDLoc &DL, SelectionDAG &DAG, + SmallVectorImpl &InVals) const override; + + bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, + bool isVarArg, + const SmallVectorImpl &Outs, + LLVMContext &Context) const override; + + SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &OutVals, const SDLoc &DL, + SelectionDAG &DAG) const override; + +private: + const XtensaSubtarget &Subtarget; + + CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; +}; + +} // end namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp new file mode 100644 index 00000000000000..52a87fe4b93438 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -0,0 +1,27 @@ +//===- XtensaInstrInfo.cpp - Xtensa Instruction Information ---------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the Xtensa implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#include "XtensaInstrInfo.h" +#include "XtensaTargetMachine.h" +#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" + +#define GET_INSTRINFO_CTOR_DTOR +#include "XtensaGenInstrInfo.inc" + +using namespace llvm; + +XtensaInstrInfo::XtensaInstrInfo(XtensaSubtarget &sti) + : XtensaGenInstrInfo(), RI(sti), STI(sti) {} diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h new file mode 100644 index 00000000000000..7225886b2ce119 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h @@ -0,0 +1,43 @@ +//===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the Xtensa implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H +#define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H + +#include "Xtensa.h" +#include "XtensaRegisterInfo.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" + +#define GET_INSTRINFO_HEADER + +#include "XtensaGenInstrInfo.inc" + +namespace llvm { + +class XtensaTargetMachine; +class XtensaSubtarget; +class XtensaInstrInfo : public XtensaGenInstrInfo { + const XtensaRegisterInfo RI; + XtensaSubtarget &STI; + +public: + XtensaInstrInfo(XtensaSubtarget &STI); + + // Return the XtensaRegisterInfo, which this class owns. + const XtensaRegisterInfo &getRegisterInfo() const { return RI; } +}; +} // end namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 268a9943d8c160..5a0f3f8d033dbe 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -14,6 +14,7 @@ include "XtensaInstrFormats.td" include "XtensaOperands.td" +include "XtensaOperators.td" //===----------------------------------------------------------------------===// // Arithmetic & Logical instructions @@ -426,7 +427,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, Uses = [A0] in { def RET : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins), - "ret", []> { + "ret", [(Xtensa_retflag)]> { let m = 0x2; let n = 0x0; let s = 0; diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp new file mode 100644 index 00000000000000..114c562b6f4ef7 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp @@ -0,0 +1,63 @@ +//===- XtensaMCInstLower.cpp - Convert Xtensa MachineInstr to MCInst ------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains code to lower Xtensa MachineInstrs to their corresponding +// MCInst records. +// +//===----------------------------------------------------------------------===// + +#include "XtensaMCInstLower.h" +#include "MCTargetDesc/XtensaMCExpr.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/IR/Mangler.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCStreamer.h" + +using namespace llvm; + +XtensaMCInstLower::XtensaMCInstLower(MCContext &ctx, + XtensaAsmPrinter &asmPrinter) + : Ctx(ctx), Printer(asmPrinter) {} + + +MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO, + unsigned Offset) const { + MachineOperand::MachineOperandType MOTy = MO.getType(); + + switch (MOTy) { + case MachineOperand::MO_Register: + // Ignore all implicit register operands. + if (MO.isImplicit()) + break; + return MCOperand::createReg(MO.getReg()); + case MachineOperand::MO_Immediate: + return MCOperand::createImm(MO.getImm() + Offset); + case MachineOperand::MO_RegisterMask: + break; + default: + llvm_unreachable("unknown operand type"); + } + + return MCOperand(); +} + +void XtensaMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { + OutMI.setOpcode(MI->getOpcode()); + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + MCOperand MCOp = lowerOperand(MO); + + if (MCOp.isValid()) + OutMI.addOperand(MCOp); + } +} diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h new file mode 100644 index 00000000000000..2b238417ae3eba --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h @@ -0,0 +1,43 @@ +//===- XtensaMCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H +#define LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H + +#include "XtensaAsmPrinter.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/DataTypes.h" + +namespace llvm { +class MCContext; +class MCInst; +class MCOperand; +class MCSymbol; +class MachineInstr; +class MachineOperand; +class XtensaAsmPrinter; + +class LLVM_LIBRARY_VISIBILITY XtensaMCInstLower { + MCContext &Ctx; + XtensaAsmPrinter &Printer; + +public: + XtensaMCInstLower(MCContext &ctx, XtensaAsmPrinter &asmPrinter); + + // Lower MachineInstr MI to MCInst OutMI. + void lower(const MachineInstr *MI, MCInst &OutMI) const; + + // Return an MCOperand for MO. Return an empty operand if MO is implicit. + MCOperand lowerOperand(const MachineOperand &MO, unsigned Offset = 0) const; +}; +} // end namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td new file mode 100644 index 00000000000000..6b1f8e4f9b08e2 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -0,0 +1,15 @@ +//===- XtensaOperators.td - Xtensa-specific operators ---------*- tblgen-*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Node definitions +//===----------------------------------------------------------------------===// +def Xtensa_retflag: SDNode<"XtensaISD::RET_FLAG", SDTNone, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp new file mode 100644 index 00000000000000..5cebe4a3346b25 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -0,0 +1,70 @@ +//===- XtensaRegisterInfo.cpp - Xtensa Register Information ---------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the Xtensa implementation of the TargetRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#include "XtensaRegisterInfo.h" +#include "XtensaInstrInfo.h" +#include "XtensaSubtarget.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" + +#define DEBUG_TYPE "xtensa-reg-info" + +#define GET_REGINFO_TARGET_DESC +#include "XtensaGenRegisterInfo.inc" + +using namespace llvm; + +XtensaRegisterInfo::XtensaRegisterInfo(const XtensaSubtarget &STI) + : XtensaGenRegisterInfo(Xtensa::A0), Subtarget(STI) {} + +const uint16_t * +XtensaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + return CSR_Xtensa_SaveList; +} + +const uint32_t * +XtensaRegisterInfo::getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID) const { + return CSR_Xtensa_RegMask; +} + +BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); + + Reserved.set(Xtensa::A0); + if (TFI->hasFP(MF)) { + // Reserve frame pointer. + Reserved.set(getFrameRegister(MF)); + } + + // Reserve stack pointer. + Reserved.set(Xtensa::SP); + return Reserved; +} + +bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, unsigned FIOperandNum, + RegScavenger *RS) const { + report_fatal_error("Eliminate frame index not supported yet"); + return false; +} + +Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); + return TFI->hasFP(MF) ? (Xtensa::A15) : Xtensa::SP; +} diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h new file mode 100644 index 00000000000000..4f5426acf7a559 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h @@ -0,0 +1,56 @@ +//===-- XtensaRegisterInfo.h - Xtensa Register Information Impl -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the Xtensa implementation of the TargetRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAREGISTERINFO_H +#define LLVM_LIB_TARGET_XTENSA_XTENSAREGISTERINFO_H + +#include "Xtensa.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" + +#define GET_REGINFO_HEADER +#include "XtensaGenRegisterInfo.inc" + +namespace llvm { +class TargetRegisterClass; +class XtensaInstrInfo; +class XtensaSubtarget; + +struct XtensaRegisterInfo : public XtensaGenRegisterInfo { +public: + const XtensaSubtarget &Subtarget; + + XtensaRegisterInfo(const XtensaSubtarget &STI); + + bool requiresRegisterScavenging(const MachineFunction &MF) const override { + return true; + } + + bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { + return true; + } + + const uint16_t * + getCalleeSavedRegs(const MachineFunction *MF = 0) const override; + const uint32_t *getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID) const override; + BitVector getReservedRegs(const MachineFunction &MF) const override; + bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, + unsigned FIOperandNum, + RegScavenger *RS = nullptr) const override; + Register getFrameRegister(const MachineFunction &MF) const override; +}; + +} // end namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_REGISTERINFO_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp new file mode 100644 index 00000000000000..f76af66cac1efd --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -0,0 +1,46 @@ +//===- XtensaSubtarget.cpp - Xtensa Subtarget Information -----------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the Xtensa specific subclass of TargetSubtargetInfo. +// +//===----------------------------------------------------------------------===// + +#include "XtensaSubtarget.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "xtensa-subtarget" + +#define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR +#include "XtensaGenSubtargetInfo.inc" + +using namespace llvm; + +XtensaSubtarget & +XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { + StringRef CPUName = CPU; + if (CPUName.empty()) { + // set default cpu name + CPUName = "generic"; + } + + HasDensity = false; + + // Parse features string. + ParseSubtargetFeatures(CPUName, CPUName, FS); + return *this; +} + +XtensaSubtarget::XtensaSubtarget(const Triple &TT, const std::string &CPU, + const std::string &FS, const TargetMachine &TM) + : XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT), + InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), + TSInfo(), FrameLowering() {} diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h new file mode 100644 index 00000000000000..476f1f943a9ea7 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -0,0 +1,66 @@ +//===-- XtensaSubtarget.h - Define Subtarget for the Xtensa ----*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file declares the Xtensa specific subclass of TargetSubtargetInfo. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H +#define LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H + +#include "XtensaFrameLowering.h" +#include "XtensaISelLowering.h" +#include "XtensaInstrInfo.h" +#include "XtensaRegisterInfo.h" +#include "llvm/CodeGen/SelectionDAGTargetInfo.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/Target/TargetMachine.h" + +#define GET_SUBTARGETINFO_HEADER +#include "XtensaGenSubtargetInfo.inc" + +namespace llvm { +class StringRef; + +class XtensaSubtarget : public XtensaGenSubtargetInfo { +private: + Triple TargetTriple; + XtensaInstrInfo InstrInfo; + XtensaTargetLowering TLInfo; + SelectionDAGTargetInfo TSInfo; + XtensaFrameLowering FrameLowering; + + // Enabled Xtensa Density extension + bool HasDensity; + + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); + +public: + XtensaSubtarget(const Triple &TT, const std::string &CPU, + const std::string &FS, const TargetMachine &TM); + + const TargetFrameLowering *getFrameLowering() const override { return &FrameLowering; } + const XtensaInstrInfo *getInstrInfo() const override { return &InstrInfo; } + const XtensaRegisterInfo *getRegisterInfo() const override { + return &InstrInfo.getRegisterInfo(); + } + + const XtensaTargetLowering *getTargetLowering() const override { return &TLInfo; } + const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { return &TSInfo; } + + bool hasDensity() const { return HasDensity; } + + // Automatically generated by tblgen. + void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); +}; +} // end namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index c891ecd9c0c3fc..5ee24c701f074e 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -52,7 +52,8 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT, : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT, CPU, FS, Options, getEffectiveRelocModel(JIT, RM), getEffectiveCodeModel(CM, CodeModel::Small), OL), - TLOF(std::make_unique()) { + TLOF(std::make_unique()), + Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); } @@ -64,6 +65,31 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT, CodeGenOptLevel OL, bool JIT) : XtensaTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} +const XtensaSubtarget * +XtensaTargetMachine::getSubtargetImpl(const Function &F) const { + return &Subtarget; +} + +namespace { +/// Xtensa Code Generator Pass Configuration Options. +class XtensaPassConfig : public TargetPassConfig { +public: + XtensaPassConfig(XtensaTargetMachine &TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + XtensaTargetMachine &getXtensaTargetMachine() const { + return getTM(); + } + + bool addInstSelector() override; +}; +} // end anonymous namespace + +bool XtensaPassConfig::addInstSelector() { + addPass(createXtensaISelDag(getXtensaTargetMachine(), getOptLevel())); + return false; +} + TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) { - return new TargetPassConfig(*this, PM); + return new XtensaPassConfig(*this, PM); } diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h index dd76f45b3bb717..be0886f2a9b0fe 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h @@ -15,6 +15,7 @@ #ifndef LLVM_LIB_TARGET_XTENSA_XTENSATARGETMACHINE_H #define LLVM_LIB_TARGET_XTENSA_XTENSATARGETMACHINE_H +#include "XtensaSubtarget.h" #include "llvm/Target/TargetMachine.h" #include @@ -36,10 +37,15 @@ class XtensaTargetMachine : public LLVMTargetMachine { std::optional CM, CodeGenOptLevel OL, bool JIT); + const XtensaSubtarget *getSubtargetImpl() const { return &Subtarget; } + const XtensaSubtarget *getSubtargetImpl(const Function &F) const override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + +protected: + XtensaSubtarget Subtarget; }; } // end namespace llvm From 9a15e1203cd0d7ea8a1ab4d442bb7118011c15f2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:22 +0300 Subject: [PATCH 002/261] [Xtensa] Codegen support for memory operations --- llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 57 ++++++++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 7 +++ 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 7250a00f82ce21..c16bf8b932c8ff 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -43,7 +43,62 @@ class XtensaDAGToDAGISel : public SelectionDAGISel { bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset, int Scale) { - report_fatal_error("MemReg address is not implemented yet"); + EVT ValTy = Addr.getValueType(); + + // if Address is FI, get the TargetFrameIndex. + if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy); + + return true; + } + + if (TM.isPositionIndependent()) + report_fatal_error("PIC relocations is not supported"); + + if ((Addr.getOpcode() == ISD::TargetExternalSymbol || + Addr.getOpcode() == ISD::TargetGlobalAddress)) + return false; + + // Addresses of the form FI+const or FI|const + bool Valid = false; + if (CurDAG->isBaseWithConstantOffset(Addr)) { + ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); + int64_t OffsetVal = CN->getSExtValue(); + + switch (Scale) { + case 1: + Valid = (OffsetVal >= 0 && OffsetVal <= 255); + break; + case 2: + Valid = + (OffsetVal >= 0 && OffsetVal <= 510) && ((OffsetVal & 0x1) == 0); + break; + case 4: + Valid = + (OffsetVal >= 0 && OffsetVal <= 1020) && ((OffsetVal & 0x3) == 0); + break; + default: + break; + } + + if (Valid) { + // If the first operand is a FI, get the TargetFI Node + if (FrameIndexSDNode *FIN = + dyn_cast(Addr.getOperand(0))) + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); + else + Base = Addr.getOperand(0); + + Offset = + CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), ValTy); + return true; + } + } + + // Last case + Base = Addr; + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType()); return true; } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index a9ab9e407a4a70..4b4b9626ce28e6 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -45,6 +45,13 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setBooleanVectorContents(ZeroOrOneBooleanContent); setMinFunctionAlignment(Align(4)); + + // No sign extend instructions for i1 + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); + } // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); From f6b4ac8a025d21e73bca1b0e6b1ebc2b46825262 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:22 +0300 Subject: [PATCH 003/261] [Xtensa] Add Constant Pool --- llvm/lib/Target/Xtensa/CMakeLists.txt | 1 + .../Target/Xtensa/XtensaConstantPoolValue.cpp | 234 +++++++++++++++ .../Target/Xtensa/XtensaConstantPoolValue.h | 282 ++++++++++++++++++ 3 files changed, 517 insertions(+) create mode 100644 llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index bb1e09cb0652ec..d4300678a0434f 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -16,6 +16,7 @@ add_public_tablegen_target(XtensaCommonTableGen) add_llvm_target(XtensaCodeGen XtensaAsmPrinter.cpp + XtensaConstantPoolValue.cpp XtensaFrameLowering.cpp XtensaInstrInfo.cpp XtensaISelDAGToDAG.cpp diff --git a/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp new file mode 100644 index 00000000000000..b7502eabbf716b --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp @@ -0,0 +1,234 @@ +//===- XtensaConstantPoolValue.cpp - Xtensa constantpool value ------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the Xtensa specific constantpool value class. +// +//===----------------------------------------------------------------------===// + +#include "XtensaConstantPoolValue.h" +#include "llvm/ADT/FoldingSet.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/IR/Constant.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/IR/Type.h" +#include "llvm/Support/raw_ostream.h" +#include +using namespace llvm; + +XtensaConstantPoolValue::XtensaConstantPoolValue( + Type *Ty, unsigned id, XtensaCP::XtensaCPKind kind, bool addCurrentAddress, + XtensaCP::XtensaCPModifier modifier) + : MachineConstantPoolValue(Ty), LabelId(id), Kind(kind), Modifier(modifier), + AddCurrentAddress(addCurrentAddress) {} + +XtensaConstantPoolValue::XtensaConstantPoolValue( + LLVMContext &C, unsigned id, XtensaCP::XtensaCPKind kind, + bool addCurrentAddress, XtensaCP::XtensaCPModifier modifier) + : MachineConstantPoolValue((Type *)Type::getInt32Ty(C)), LabelId(id), + Kind(kind), Modifier(modifier), AddCurrentAddress(addCurrentAddress) {} + +XtensaConstantPoolValue::~XtensaConstantPoolValue() {} + +StringRef XtensaConstantPoolValue::getModifierText() const { + switch (Modifier) { + case XtensaCP::no_modifier: + return ""; + case XtensaCP::TPOFF: + return "@TPOFF"; + } + llvm_unreachable("Unknown modifier!"); +} + +int XtensaConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) { + llvm_unreachable("Shouldn't be calling this directly!"); +} + +void XtensaConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddInteger(LabelId); +} + +bool XtensaConstantPoolValue::hasSameValue(XtensaConstantPoolValue *ACPV) { + if (ACPV->Kind == Kind) { + if (ACPV->LabelId == LabelId) + return true; + // Two PC relative constpool entries containing the same GV address or + // external symbols. FIXME: What about blockaddress? + if (Kind == XtensaCP::CPValue || Kind == XtensaCP::CPExtSymbol) + return true; + } + return false; +} + +void XtensaConstantPoolValue::dump() const { errs() << " " << *this; } + +void XtensaConstantPoolValue::print(raw_ostream &O) const {} + +//===----------------------------------------------------------------------===// +// XtensaConstantPoolConstant +//===----------------------------------------------------------------------===// + +XtensaConstantPoolConstant::XtensaConstantPoolConstant( + Type *Ty, const Constant *C, unsigned ID, XtensaCP::XtensaCPKind Kind, + bool AddCurrentAddress) + : XtensaConstantPoolValue((Type *)C->getType(), ID, Kind, + AddCurrentAddress), + CVal(C) {} + +XtensaConstantPoolConstant::XtensaConstantPoolConstant( + const Constant *C, unsigned ID, XtensaCP::XtensaCPKind Kind, + bool AddCurrentAddress) + : XtensaConstantPoolValue((Type *)C->getType(), ID, Kind, + AddCurrentAddress), + CVal(C) {} + +XtensaConstantPoolConstant * +XtensaConstantPoolConstant::Create(const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind) { + return new XtensaConstantPoolConstant(C, ID, Kind, false); +} + +XtensaConstantPoolConstant * +XtensaConstantPoolConstant::Create(const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind, + bool AddCurrentAddress) { + return new XtensaConstantPoolConstant(C, ID, Kind, AddCurrentAddress); +} + +const GlobalValue *XtensaConstantPoolConstant::getGV() const { + return dyn_cast_or_null(CVal); +} + +const BlockAddress *XtensaConstantPoolConstant::getBlockAddress() const { + return dyn_cast_or_null(CVal); +} + +int XtensaConstantPoolConstant::getExistingMachineCPValue( + MachineConstantPool *CP, Align Alignment) { + return getExistingMachineCPValueImpl(CP, + Alignment); +} + +bool XtensaConstantPoolConstant::hasSameValue(XtensaConstantPoolValue *ACPV) { + const XtensaConstantPoolConstant *ACPC = + dyn_cast(ACPV); + return ACPC && ACPC->CVal == CVal && + XtensaConstantPoolValue::hasSameValue(ACPV); +} + +void XtensaConstantPoolConstant::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddPointer(CVal); + XtensaConstantPoolValue::addSelectionDAGCSEId(ID); +} + +void XtensaConstantPoolConstant::print(raw_ostream &O) const { + O << CVal->getName(); + XtensaConstantPoolValue::print(O); +} + +XtensaConstantPoolSymbol::XtensaConstantPoolSymbol( + LLVMContext &C, const char *s, unsigned id, bool AddCurrentAddress, + bool PrivLinkage, XtensaCP::XtensaCPModifier Modifier) + : XtensaConstantPoolValue(C, id, XtensaCP::CPExtSymbol, AddCurrentAddress, + Modifier), + S(s), PrivateLinkage(PrivLinkage) {} + +XtensaConstantPoolSymbol * +XtensaConstantPoolSymbol::Create(LLVMContext &C, const char *s, unsigned ID, + bool PrivLinkage, + XtensaCP::XtensaCPModifier Modifier) + +{ + return new XtensaConstantPoolSymbol(C, s, ID, false, PrivLinkage, Modifier); +} + +int XtensaConstantPoolSymbol::getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) { + return getExistingMachineCPValueImpl(CP, Alignment); +} + +bool XtensaConstantPoolSymbol::hasSameValue(XtensaConstantPoolValue *ACPV) { + const XtensaConstantPoolSymbol *ACPS = + dyn_cast(ACPV); + return ACPS && ACPS->S == S && XtensaConstantPoolValue::hasSameValue(ACPV); +} + +void XtensaConstantPoolSymbol::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddString(S); + XtensaConstantPoolValue::addSelectionDAGCSEId(ID); +} + +void XtensaConstantPoolSymbol::print(raw_ostream &O) const { + O << S; + XtensaConstantPoolValue::print(O); +} + +XtensaConstantPoolMBB::XtensaConstantPoolMBB(LLVMContext &C, + const MachineBasicBlock *mbb, + unsigned id) + : XtensaConstantPoolValue(C, 0, XtensaCP::CPMachineBasicBlock, false), + MBB(mbb) {} + +XtensaConstantPoolMBB * +XtensaConstantPoolMBB::Create(LLVMContext &C, const MachineBasicBlock *mbb, + unsigned idx) { + return new XtensaConstantPoolMBB(C, mbb, idx); +} + +int XtensaConstantPoolMBB::getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) { + return getExistingMachineCPValueImpl(CP, Alignment); +} + +bool XtensaConstantPoolMBB::hasSameValue(XtensaConstantPoolValue *ACPV) { + const XtensaConstantPoolMBB *ACPMBB = dyn_cast(ACPV); + return ACPMBB && ACPMBB->MBB == MBB && + XtensaConstantPoolValue::hasSameValue(ACPV); +} + +void XtensaConstantPoolMBB::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddPointer(MBB); + XtensaConstantPoolValue::addSelectionDAGCSEId(ID); +} + +void XtensaConstantPoolMBB::print(raw_ostream &O) const { + O << "BB#" << MBB->getNumber(); + XtensaConstantPoolValue::print(O); +} + +XtensaConstantPoolJumpTable::XtensaConstantPoolJumpTable(LLVMContext &C, + unsigned idx) + : XtensaConstantPoolValue(C, 0, XtensaCP::CPJumpTable, false), IDX(idx) {} + +XtensaConstantPoolJumpTable *XtensaConstantPoolJumpTable::Create(LLVMContext &C, + unsigned idx) { + return new XtensaConstantPoolJumpTable(C, idx); +} + +int XtensaConstantPoolJumpTable::getExistingMachineCPValue( + MachineConstantPool *CP, Align Alignment) { + return getExistingMachineCPValueImpl(CP, + Alignment); +} + +bool XtensaConstantPoolJumpTable::hasSameValue(XtensaConstantPoolValue *ACPV) { + const XtensaConstantPoolJumpTable *ACPJT = + dyn_cast(ACPV); + return ACPJT && ACPJT->IDX == IDX && + XtensaConstantPoolValue::hasSameValue(ACPV); +} + +void XtensaConstantPoolJumpTable::addSelectionDAGCSEId(FoldingSetNodeID &ID) {} + +void XtensaConstantPoolJumpTable::print(raw_ostream &O) const { + O << "JT" << IDX; + XtensaConstantPoolValue::print(O); +} diff --git a/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h new file mode 100644 index 00000000000000..c201508ceea4f9 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h @@ -0,0 +1,282 @@ +//===- XtensaConstantPoolValue.h - Xtensa constantpool value ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the Xtensa specific constantpool value class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H +#define LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H + +#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/ErrorHandling.h" +#include +#include +#include + +namespace llvm { + +class BlockAddress; +class Constant; +class GlobalValue; +class LLVMContext; +class MachineBasicBlock; + +namespace XtensaCP { +enum XtensaCPKind { + CPValue, + CPExtSymbol, + CPBlockAddress, + CPMachineBasicBlock, + CPJumpTable +}; + +enum XtensaCPModifier { + no_modifier, // None + TPOFF // Thread Pointer Offset +}; +} // namespace XtensaCP + +/// XtensaConstantPoolValue - Xtensa specific constantpool value. This is used +/// to represent PC-relative displacement between the address of the load +/// instruction and the constant being loaded, i.e. (&GV-(LPIC+8)). +class XtensaConstantPoolValue : public MachineConstantPoolValue { + unsigned LabelId; // Label id of the load. + XtensaCP::XtensaCPKind Kind; // Kind of constant. + XtensaCP::XtensaCPModifier Modifier; // GV modifier + bool AddCurrentAddress; + +protected: + XtensaConstantPoolValue( + Type *Ty, unsigned id, XtensaCP::XtensaCPKind Kind, + bool AddCurrentAddress, + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier); + + XtensaConstantPoolValue( + LLVMContext &C, unsigned id, XtensaCP::XtensaCPKind Kind, + bool AddCurrentAddress, + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier); + + template + int getExistingMachineCPValueImpl(MachineConstantPool *CP, + Align Alignment) { + const std::vector &Constants = CP->getConstants(); + for (unsigned i = 0, e = Constants.size(); i != e; ++i) { + if (Constants[i].isMachineConstantPoolEntry() && + (Constants[i].getAlign() >= Alignment)) { + XtensaConstantPoolValue *CPV = + (XtensaConstantPoolValue *)Constants[i].Val.MachineCPVal; + if (Derived *APC = dyn_cast(CPV)) + if (cast(this)->equals(APC)) + return i; + } + } + + return -1; + } + +public: + ~XtensaConstantPoolValue() override; + + XtensaCP::XtensaCPModifier getModifier() const { return Modifier; } + bool hasModifier() const { return Modifier != XtensaCP::no_modifier; } + StringRef getModifierText() const; + + bool mustAddCurrentAddress() const { return AddCurrentAddress; } + + unsigned getLabelId() const { return LabelId; } + void setLabelId(unsigned id) { LabelId = id; } + + bool isGlobalValue() const { return Kind == XtensaCP::CPValue; } + bool isExtSymbol() const { return Kind == XtensaCP::CPExtSymbol; } + bool isBlockAddress() const { return Kind == XtensaCP::CPBlockAddress; } + bool isMachineBasicBlock() const { + return Kind == XtensaCP::CPMachineBasicBlock; + } + bool isJumpTable() const { return Kind == XtensaCP::CPJumpTable; } + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + virtual bool hasSameValue(XtensaConstantPoolValue *ACPV); + + bool equals(const XtensaConstantPoolValue *A) const { + return this->LabelId == A->LabelId && this->Modifier == A->Modifier; + } + + void print(raw_ostream &O) const override; + void print(raw_ostream *O) const { + if (O) + print(*O); + } + void dump() const; +}; + +inline raw_ostream &operator<<(raw_ostream &O, + const XtensaConstantPoolValue &V) { + V.print(O); + return O; +} + +/// XtensaConstantPoolConstant - Xtensa-specific constant pool values for +/// Constants, Functions, and BlockAddresses. +class XtensaConstantPoolConstant : public XtensaConstantPoolValue { + const Constant *CVal; // Constant being loaded. + + XtensaConstantPoolConstant(const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind, + bool AddCurrentAddress); + XtensaConstantPoolConstant(Type *Ty, const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind, + bool AddCurrentAddress); + +public: + static XtensaConstantPoolConstant *Create(const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind); + static XtensaConstantPoolConstant *Create(const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind, + bool AddCurrentAddress); + + const GlobalValue *getGV() const; + const BlockAddress *getBlockAddress() const; + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + bool hasSameValue(XtensaConstantPoolValue *ACPV) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + void print(raw_ostream &O) const override; + static bool classof(const XtensaConstantPoolValue *APV) { + return APV->isGlobalValue() || APV->isBlockAddress(); + } + + bool equals(const XtensaConstantPoolConstant *A) const { + return CVal == A->CVal && XtensaConstantPoolValue::equals(A); + } +}; + +/// XtensaConstantPoolSymbol - Xtensa-specific constantpool values for external +/// symbols. +class XtensaConstantPoolSymbol : public XtensaConstantPoolValue { + const std::string S; // ExtSymbol being loaded. + bool PrivateLinkage; + + XtensaConstantPoolSymbol( + LLVMContext &C, const char *s, unsigned id, bool AddCurrentAddress, + bool PrivLinkage, + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier); + +public: + static XtensaConstantPoolSymbol * + Create(LLVMContext &C, const char *s, unsigned ID, bool PrivLinkage, + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier); + + const char *getSymbol() const { return S.c_str(); } + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + bool hasSameValue(XtensaConstantPoolValue *ACPV) override; + + bool isPrivateLinkage() { return PrivateLinkage; } + + void print(raw_ostream &O) const override; + + static bool classof(const XtensaConstantPoolValue *ACPV) { + return ACPV->isExtSymbol(); + } + + bool equals(const XtensaConstantPoolSymbol *A) const { + return S == A->S && XtensaConstantPoolValue::equals(A); + } +}; + +/// XtensaConstantPoolMBB - Xtensa-specific constantpool value of a machine +/// basic block. +class XtensaConstantPoolMBB : public XtensaConstantPoolValue { + const MachineBasicBlock *MBB; // Machine basic block. + + XtensaConstantPoolMBB(LLVMContext &C, const MachineBasicBlock *mbb, + unsigned id); + +public: + static XtensaConstantPoolMBB * + Create(LLVMContext &C, const MachineBasicBlock *mbb, unsigned ID); + + const MachineBasicBlock *getMBB() const { return MBB; } + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + bool hasSameValue(XtensaConstantPoolValue *ACPV) override; + + void print(raw_ostream &O) const override; + + static bool classof(const XtensaConstantPoolValue *ACPV) { + return ACPV->isMachineBasicBlock(); + } + + bool equals(const XtensaConstantPoolMBB *A) const { + return MBB == A->MBB && XtensaConstantPoolValue::equals(A); + } +}; + +/// XtensaConstantPoolJumpTable - Xtensa-specific constantpool values for Jump +/// Table symbols. +class XtensaConstantPoolJumpTable : public XtensaConstantPoolValue { + unsigned IDX; // Jump Table Index. + + XtensaConstantPoolJumpTable(LLVMContext &C, unsigned idx); + +public: + static XtensaConstantPoolJumpTable *Create(LLVMContext &C, unsigned idx); + + unsigned getIndex() const { return IDX; } + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + bool hasSameValue(XtensaConstantPoolValue *ACPV) override; + + void print(raw_ostream &O) const override; + + static bool classof(const XtensaConstantPoolValue *ACPV) { + return ACPV->isJumpTable(); + } + + bool equals(const XtensaConstantPoolJumpTable *A) const { + return IDX == A->IDX && XtensaConstantPoolValue::equals(A); + } +}; + +} // namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H */ From ad405c2f7d07b96c407b394eaac02f1457c6fe86 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:23 +0300 Subject: [PATCH 004/261] [Xtensa] Implement assembler representation of the Constant Pool. --- llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 171 ++++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 2 + 2 files changed, 173 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index e633b77ff62078..63a0aa1633378e 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -14,8 +14,10 @@ //===----------------------------------------------------------------------===// #include "XtensaAsmPrinter.h" +#include "XtensaConstantPoolValue.h" #include "XtensaMCInstLower.h" #include "TargetInfo/XtensaTargetInfo.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -28,6 +30,17 @@ using namespace llvm; +static MCSymbolRefExpr::VariantKind +getModifierVariantKind(XtensaCP::XtensaCPModifier Modifier) { + switch (Modifier) { + case XtensaCP::no_modifier: + return MCSymbolRefExpr::VK_None; + case XtensaCP::TPOFF: + return MCSymbolRefExpr::VK_TPOFF; + } + llvm_unreachable("Invalid XtensaCPModifier!"); +} + void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) { XtensaMCInstLower Lower(MF->getContext(), *this); MCInst LoweredMI; @@ -35,6 +48,164 @@ void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) { EmitToStreamer(*OutStreamer, LoweredMI); } +/// EmitConstantPool - Print to the current output stream assembly +/// representations of the constants in the constant pool MCP. This is +/// used to print out constants which have been "spilled to memory" by +/// the code generator. +void XtensaAsmPrinter::emitConstantPool() { + const Function &F = MF->getFunction(); + const MachineConstantPool *MCP = MF->getConstantPool(); + const std::vector &CP = MCP->getConstants(); + if (CP.empty()) + return; + + for (unsigned i = 0, e = CP.size(); i != e; ++i) { + const MachineConstantPoolEntry &CPE = CP[i]; + + if (i == 0) { + if (OutStreamer->hasRawTextSupport()) { + OutStreamer->switchSection( + getObjFileLowering().SectionForGlobal(&F, TM)); + OutStreamer->emitRawText(StringRef("\t.literal_position\n")); + } else { + MCSectionELF *CS = + (MCSectionELF *)getObjFileLowering().SectionForGlobal(&F, TM); + std::string CSectionName = CS->getName().str(); + std::size_t Pos = CSectionName.find(".text"); + std::string SectionName; + if (Pos != std::string::npos) { + if (Pos > 0) + SectionName = CSectionName.substr(0, Pos + 5); + else + SectionName = ""; + SectionName += ".literal"; + SectionName += CSectionName.substr(Pos + 5); + } else { + SectionName = CSectionName; + SectionName += ".literal"; + } + + MCSectionELF *S = + OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, + ELF::SHF_EXECINSTR | ELF::SHF_ALLOC); + S->setAlignment(Align(4)); + OutStreamer->switchSection(S); + } + } + + if (CPE.isMachineConstantPoolEntry()) { + XtensaConstantPoolValue *ACPV = + static_cast(CPE.Val.MachineCPVal); + ACPV->setLabelId(i); + emitMachineConstantPoolValue(CPE.Val.MachineCPVal); + } else { + MCSymbol *LblSym = GetCPISymbol(i); + // TODO find a better way to check whether we emit data to .s file + if (OutStreamer->hasRawTextSupport()) { + std::string str("\t.literal "); + str += LblSym->getName(); + str += ", "; + const Constant *C = CPE.Val.ConstVal; + + Type *Ty = C->getType(); + if (const auto *CFP = dyn_cast(C)) { + str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true); + } else if (const auto *CI = dyn_cast(C)) { + str += toString(CI->getValue(), 10, true); + } else if (isa(Ty)) { + const MCExpr *ME = lowerConstant(C); + const MCSymbolRefExpr &SRE = cast(*ME); + const MCSymbol &Sym = SRE.getSymbol(); + str += Sym.getName(); + } else { + unsigned NumElements; + if (isa(Ty)) + NumElements = (cast(Ty))->getNumElements(); + else + NumElements = Ty->getArrayNumElements(); + + for (unsigned I = 0; I < NumElements; I++) { + const Constant *CAE = C->getAggregateElement(I); + if (I > 0) + str += ", "; + if (const auto *CFP = dyn_cast(CAE)) { + str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true); + } else if (const auto *CI = dyn_cast(CAE)) { + str += toString(CI->getValue(), 10, true); + } + } + } + + OutStreamer->emitRawText(StringRef(str)); + } else { + OutStreamer->emitLabel(LblSym); + emitGlobalConstant(getDataLayout(), CPE.Val.ConstVal); + } + } + } +} + +void XtensaAsmPrinter::emitMachineConstantPoolValue( + MachineConstantPoolValue *MCPV) { + XtensaConstantPoolValue *ACPV = static_cast(MCPV); + + MCSymbol *MCSym; + if (ACPV->isBlockAddress()) { + const BlockAddress *BA = + cast(ACPV)->getBlockAddress(); + MCSym = GetBlockAddressSymbol(BA); + } else if (ACPV->isGlobalValue()) { + const GlobalValue *GV = cast(ACPV)->getGV(); + // TODO some modifiers + MCSym = getSymbol(GV); + } else if (ACPV->isMachineBasicBlock()) { + const MachineBasicBlock *MBB = cast(ACPV)->getMBB(); + MCSym = MBB->getSymbol(); + } else if (ACPV->isJumpTable()) { + unsigned idx = cast(ACPV)->getIndex(); + MCSym = this->GetJTISymbol(idx, false); + } else { + assert(ACPV->isExtSymbol() && "unrecognized constant pool value"); + XtensaConstantPoolSymbol *XtensaSym = cast(ACPV); + const char *Sym = XtensaSym->getSymbol(); + // TODO it's a trick to distinguish static references and generated rodata + // references Some clear method required + { + std::string SymName(Sym); + if (XtensaSym->isPrivateLinkage()) + SymName = ".L" + SymName; + MCSym = GetExternalSymbolSymbol(StringRef(SymName)); + } + } + + MCSymbol *LblSym = GetCPISymbol(ACPV->getLabelId()); + // TODO find a better way to check whether we emit data to .s file + if (OutStreamer->hasRawTextSupport()) { + std::string SymName("\t.literal "); + SymName += LblSym->getName(); + SymName += ", "; + SymName += MCSym->getName(); + + StringRef Modifier = ACPV->getModifierText(); + SymName += Modifier; + + OutStreamer->emitRawText(StringRef(SymName)); + } else { + MCSymbolRefExpr::VariantKind VK = + getModifierVariantKind(ACPV->getModifier()); + + if (ACPV->getModifier() != XtensaCP::no_modifier) { + std::string SymName(MCSym->getName()); + MCSym = GetExternalSymbolSymbol(StringRef(SymName)); + } + + const MCExpr *Expr = MCSymbolRefExpr::create(MCSym, VK, OutContext); + uint64_t Size = getDataLayout().getTypeAllocSize(ACPV->getType()); + OutStreamer->emitLabel(LblSym); + OutStreamer->emitValue(Expr, Size); + } +} + // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmPrinter() { RegisterAsmPrinter A(getTheXtensaTarget()); diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h index d23fa5dbeadb21..0ba80bc18c1c2d 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h @@ -36,6 +36,8 @@ class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter { // Override AsmPrinter. StringRef getPassName() const override { return "Xtensa Assembly Printer"; } void emitInstruction(const MachineInstr *MI) override; + void emitConstantPool() override; + void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; }; } // end namespace llvm From 470785b78a49938390866c27a65e23f349eb44ca Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:23 +0300 Subject: [PATCH 005/261] [Xtensa] Implement lowering constants. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 48 ++++++++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 5 ++ 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 4b4b9626ce28e6..05d3a2524bcc4b 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -45,7 +45,12 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setBooleanVectorContents(ZeroOrOneBooleanContent); setMinFunctionAlignment(Align(4)); - + + setOperationAction(ISD::Constant, MVT::i32, Custom); + setOperationAction(ISD::Constant, MVT::i64, Expand); + setOperationAction(ISD::ConstantFP, MVT::f32, Custom); + setOperationAction(ISD::ConstantFP, MVT::f64, Expand); + // No sign extend instructions for i1 for (MVT VT : MVT::integer_valuetypes()) { setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); @@ -57,6 +62,11 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, computeRegisterProperties(STI.getRegisterInfo()); } +bool XtensaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const { + return false; +} + //===----------------------------------------------------------------------===// // Calling conventions //===----------------------------------------------------------------------===// @@ -298,9 +308,45 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, return DAG.getNode(XtensaISD::RET_FLAG, DL, MVT::Other, RetOps); } +SDValue XtensaTargetLowering::LowerImmediate(SDValue Op, + SelectionDAG &DAG) const { + const ConstantSDNode *CN = cast(Op); + SDLoc DL(CN); + APInt apval = CN->getAPIntValue(); + int64_t value = apval.getSExtValue(); + if (Op.getValueType() == MVT::i32) { + if (value > -2048 && value <= 2047) + return Op; + Type *Ty = Type::getInt32Ty(*DAG.getContext()); + Constant *CV = ConstantInt::get(Ty, value); + SDValue CP = DAG.getConstantPool(CV, MVT::i32); + return CP; + } + return Op; +} + +SDValue XtensaTargetLowering::LowerImmediateFP(SDValue Op, + SelectionDAG &DAG) const { + const ConstantFPSDNode *CN = cast(Op); + SDLoc DL(CN); + APFloat apval = CN->getValueAPF(); + int64_t value = llvm::bit_cast(CN->getValueAPF().convertToFloat()); + if (Op.getValueType() == MVT::f32) { + Type *Ty = Type::getInt32Ty(*DAG.getContext()); + Constant *CV = ConstantInt::get(Ty, value); + SDValue CP = DAG.getConstantPool(CV, MVT::i32); + return DAG.getNode(ISD::BITCAST, DL, MVT::f32, CP); + } + return Op; +} + SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { + case ISD::Constant: + return LowerImmediate(Op, DAG); + case ISD::ConstantFP: + return LowerImmediateFP(Op, DAG); default: llvm_unreachable("Unexpected node to lower"); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 2df2a074fe25fd..e2ed301e45ebef 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -36,6 +36,8 @@ class XtensaTargetLowering : public TargetLowering { explicit XtensaTargetLowering(const TargetMachine &TM, const XtensaSubtarget &STI); + bool isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const override; const char *getTargetNodeName(unsigned Opcode) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, @@ -57,6 +59,9 @@ class XtensaTargetLowering : public TargetLowering { private: const XtensaSubtarget &Subtarget; + SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const; + CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; }; From bd48abd762596c14125cd4e4ef29c7e620f53fb3 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:23 +0300 Subject: [PATCH 006/261] [Xtensa] Add support of the Xtensa function calls --- .../lib/Target/Xtensa/XtensaFrameLowering.cpp | 20 ++ llvm/lib/Target/Xtensa/XtensaFrameLowering.h | 4 + llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 240 +++++++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 14 + llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 135 +++++++++- llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 27 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 47 ++++ llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp | 50 ++++ llvm/lib/Target/Xtensa/XtensaMCInstLower.h | 7 + llvm/lib/Target/Xtensa/XtensaOperands.td | 2 +- llvm/lib/Target/Xtensa/XtensaOperators.td | 26 +- llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 111 +++++++- llvm/lib/Target/Xtensa/XtensaRegisterInfo.h | 5 + 13 files changed, 678 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index b201b99813ced1..71941e7671930e 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -42,3 +42,23 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF, void XtensaFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {} + +// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions +MachineBasicBlock::iterator XtensaFrameLowering::eliminateCallFramePseudoInstr( + MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + const XtensaInstrInfo &TII = + *static_cast(MF.getSubtarget().getInstrInfo()); + + if (!hasReservedCallFrame(MF)) { + int64_t Amount = I->getOperand(0).getImm(); + + if (I->getOpcode() == Xtensa::ADJCALLSTACKDOWN) + Amount = -Amount; + + unsigned SP = Xtensa::SP; + TII.adjustStackPtr(SP, Amount, MBB, I); + } + + return MBB.erase(I); +} diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h index a5dfc83b940597..584438d179bb8a 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h @@ -27,6 +27,10 @@ class XtensaFrameLowering : public TargetFrameLowering { /// the function. void emitPrologue(MachineFunction &, MachineBasicBlock &) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + + MachineBasicBlock::iterator + eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const override; }; } // namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 05d3a2524bcc4b..48b67b8a62f2cb 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -14,6 +14,7 @@ //===----------------------------------------------------------------------===// #include "XtensaISelLowering.h" +#include "XtensaConstantPoolValue.h" #include "XtensaSubtarget.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/CallingConvLower.h" @@ -25,11 +26,20 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; #define DEBUG_TYPE "xtensa-lower" +// Return true if we must use long (in fact, indirect) function call. +// It's simplified version, production implimentation must +// resolve a functions in ROM (usually glibc functions) +static bool isLongCall(const char *str) { + // Currently always use long calls + return true; +} + XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, const XtensaSubtarget &STI) : TargetLowering(tm), Subtarget(STI) { @@ -137,6 +147,32 @@ CCAssignFn *XtensaTargetLowering::CCAssignFnForCall(CallingConv::ID CC, return CC_Xtensa_Custom; } +// Value is a value that has been passed to us in the location described by VA +// (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining +// any loads onto Chain. +static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, + CCValAssign &VA, SDValue Chain, + SDValue Value) { + // If the argument has been promoted from a smaller type, insert an + // assertion to capture this. + if (VA.getLocInfo() == CCValAssign::SExt) + Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, + DAG.getValueType(VA.getValVT())); + else if (VA.getLocInfo() == CCValAssign::ZExt) + Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, + DAG.getValueType(VA.getValVT())); + + if (VA.isExtInLoc()) + Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); + else if (VA.getLocInfo() == CCValAssign::Indirect) + Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value, MachinePointerInfo()); + else if (VA.getValVT() == MVT::f32) + Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); + else + assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo"); + return Value; +} + // Value is a value of type VA.getValVT() that we need to copy into // the location described by VA. Return a copy of Value converted to // VA.getValVT(). The caller is responsible for handling indirect values. @@ -250,8 +286,203 @@ SDValue XtensaTargetLowering::LowerFormalArguments( return Chain; } +SDValue XtensaTargetLowering::getAddrPCRel(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT Ty = Op.getValueType(); + return DAG.getNode(XtensaISD::PCREL_WRAPPER, DL, Ty, Op); +} + +SDValue +XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, + SmallVectorImpl &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc &DL = CLI.DL; + SmallVector &Outs = CLI.Outs; + SmallVector &OutVals = CLI.OutVals; + SmallVector &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &IsTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool IsVarArg = CLI.IsVarArg; + + MachineFunction &MF = DAG.getMachineFunction(); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); + + // TODO: Support tail call optimization. + IsTailCall = false; + + // Analyze the operands of the call, assigning locations to each operand. + SmallVector ArgLocs; + CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); + + CCAssignFn *CC = CCAssignFnForCall(CallConv, IsVarArg); + + CCInfo.AnalyzeCallOperands(Outs, CC); + + // Get a count of how many bytes are to be pushed on the stack. + unsigned NumBytes = CCInfo.getStackSize(); + + unsigned StackAlignment = TFL->getStackAlignment(); + unsigned NextStackOffset = alignTo(NumBytes, StackAlignment); + + Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); + + // Copy argument values to their designated locations. + std::deque> RegsToPass; + SmallVector MemOpChains; + SDValue StackPtr; + for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { + CCValAssign &VA = ArgLocs[I]; + SDValue ArgValue = OutVals[I]; + ISD::ArgFlagsTy Flags = Outs[I].Flags; + + ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue); + + if (VA.isRegLoc()) + // Queue up the argument copies and emit them at the end. + RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); + else if (Flags.isByVal()) { + assert(VA.isMemLoc()); + assert(Flags.getByValSize() && + "ByVal args of size 0 should have been ignored by front-end."); + assert(!IsTailCall && + "Do not tail-call optimize if there is a byval argument."); + + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, DL, Xtensa::SP, PtrVT); + unsigned Offset = VA.getLocMemOffset(); + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, + DAG.getIntPtrConstant(Offset, DL)); + SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32); + SDValue Memcpy = DAG.getMemcpy( + Chain, DL, Address, ArgValue, SizeNode, Flags.getNonZeroByValAlign(), + /*isVolatile=*/false, /*AlwaysInline=*/false, + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); + MemOpChains.push_back(Memcpy); + } else { + assert(VA.isMemLoc() && "Argument not register or memory"); + + // Work out the address of the stack slot. Unpromoted ints and + // floats are passed as right-justified 8-byte values. + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, DL, Xtensa::SP, PtrVT); + unsigned Offset = VA.getLocMemOffset(); + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, + DAG.getIntPtrConstant(Offset, DL)); + + // Emit the store. + MemOpChains.push_back( + DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo())); + } + } + + // Join the stores, which are independent of one another. + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); + + // Build a sequence of copy-to-reg nodes, chained and glued together. + SDValue Glue; + for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) { + unsigned Reg = RegsToPass[I].first; + Chain = DAG.getCopyToReg(Chain, DL, Reg, RegsToPass[I].second, Glue); + Glue = Chain.getValue(1); + } + + std::string name; + unsigned char TF = 0; + + // Accept direct calls by converting symbolic call addresses to the + // associated Target* opcodes. + if (ExternalSymbolSDNode *E = dyn_cast(Callee)) { + name = E->getSymbol(); + TF = E->getTargetFlags(); + if (isPositionIndependent()) { + report_fatal_error("PIC relocations is not supported"); + } else + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF); + } else if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + // TODO replace GlobalAddress to some special operand instead of + // ExternalSymbol + // Callee = + // DAG.getTargetExternalSymbol(strdup(G->getGlobal()->getName().str().c_str()), + // PtrVT); + + const GlobalValue *GV = G->getGlobal(); + name = GV->getName().str(); + } + + if ((!name.empty()) && isLongCall(name.c_str())) { + // Create a constant pool entry for the callee address + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier; + + XtensaConstantPoolValue *CPV = XtensaConstantPoolSymbol::Create( + *DAG.getContext(), name.c_str(), 0 /* XtensaCLabelIndex */, false, + Modifier); + + // Get the address of the callee into a register + SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4), 0, TF); + SDValue CPWrap = getAddrPCRel(CPAddr, DAG); + Callee = CPWrap; + } + + // The first call operand is the chain and the second is the target address. + SmallVector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + + // Add a register mask operand representing the call-preserved registers. + const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); + const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); + assert(Mask && "Missing call preserved mask for calling convention"); + Ops.push_back(DAG.getRegisterMask(Mask)); + + // Add argument registers to the end of the list so that they are + // known live into the call. + for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) { + unsigned Reg = RegsToPass[I].first; + Ops.push_back(DAG.getRegister(Reg, RegsToPass[I].second.getValueType())); + } + + // Glue the call to the argument copies, if any. + if (Glue.getNode()) + Ops.push_back(Glue); + + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + Chain = DAG.getNode(XtensaISD::CALL, DL, NodeTys, Ops); + Glue = Chain.getValue(1); + + // Mark the end of the call, which is glued to the call itself. + Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, DL, PtrVT, true), + DAG.getConstant(0, DL, PtrVT, true), Glue, DL); + Glue = Chain.getValue(1); + + // Assign locations to each value returned by this call. + SmallVector RetLocs; + CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext()); + RetCCInfo.AnalyzeCallResult(Ins, RetCC_Xtensa); + + // Copy all of the result registers out of their specified physreg. + for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) { + CCValAssign &VA = RetLocs[I]; + + // Copy the value out, gluing the copy to the end of the call sequence. + unsigned Reg = VA.getLocReg(); + SDValue RetValue = DAG.getCopyFromReg(Chain, DL, Reg, VA.getLocVT(), Glue); + Chain = RetValue.getValue(1); + Glue = RetValue.getValue(2); + + // Convert the value of the return register into the value that's + // being returned. + InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue)); + } + return Chain; +} + bool XtensaTargetLowering::CanLowerReturn( - CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, + CallingConv::ID CallConv, MachineFunction & MF, bool IsVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { SmallVector RVLocs; CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); @@ -357,10 +588,9 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { case XtensaISD::NAME: \ return "XtensaISD::" #NAME switch (Opcode) { - case XtensaISD::FIRST_NUMBER: - break; - case XtensaISD::RET_FLAG: - return "XtensaISD::RET_FLAG"; + OPCODE(RET_FLAG); + OPCODE(CALL); + OPCODE(PCREL_WRAPPER); } return NULL; #undef OPCODE diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index e2ed301e45ebef..18c7772a43451a 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -24,6 +24,16 @@ namespace llvm { namespace XtensaISD { enum { FIRST_NUMBER = ISD::BUILTIN_OP_END, + + // Calls a function. Operand 0 is the chain operand and operand 1 + // is the target address. The arguments start at operand 2. + // There is an optional glue operand at the end. + CALL, + + // Wraps a TargetGlobalAddress that should be loaded using PC-relative + // accesses. Operand 0 is the address. + PCREL_WRAPPER, + // Return with a flag operand. Operand 0 is the chain operand. RET_FLAG }; @@ -45,6 +55,8 @@ class XtensaTargetLowering : public TargetLowering { const SmallVectorImpl &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl &InVals) const override; + SDValue LowerCall(CallLoweringInfo &CLI, + SmallVectorImpl &InVals) const override; bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, @@ -62,6 +74,8 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const; SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const; + SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; + CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; }; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 52a87fe4b93438..30134c9612fdb6 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -15,6 +15,7 @@ #include "XtensaInstrInfo.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -23,5 +24,137 @@ using namespace llvm; +static inline const MachineInstrBuilder & +addFrameReference(const MachineInstrBuilder &MIB, int FI) { + MachineInstr *MI = MIB; + MachineFunction &MF = *MI->getParent()->getParent(); + MachineFrameInfo &MFFrame = MF.getFrameInfo(); + const MCInstrDesc &MCID = MI->getDesc(); + MachineMemOperand::Flags Flags = MachineMemOperand::MONone; + if (MCID.mayLoad()) + Flags |= MachineMemOperand::MOLoad; + if (MCID.mayStore()) + Flags |= MachineMemOperand::MOStore; + int64_t Offset = 0; + Align Alignment = MFFrame.getObjectAlign(FI); + + MachineMemOperand *MMO = + MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI, Offset), + Flags, MFFrame.getObjectSize(FI), Alignment); + return MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); +} + XtensaInstrInfo::XtensaInstrInfo(XtensaSubtarget &sti) - : XtensaGenInstrInfo(), RI(sti), STI(sti) {} + : XtensaGenInstrInfo(Xtensa::ADJCALLSTACKDOWN, Xtensa::ADJCALLSTACKUP), RI(sti), STI(sti) {} + +/// Adjust SP by Amount bytes. +void XtensaInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); + + if (Amount == 0) + return; + + MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); + const TargetRegisterClass *RC = &Xtensa::ARRegClass; + + // create virtual reg to store immediate + unsigned Reg = RegInfo.createVirtualRegister(RC); + + if (isInt<8>(Amount)) // addi sp, sp, amount + BuildMI(MBB, I, DL, get(Xtensa::ADDI), Reg).addReg(SP).addImm(Amount); + else { // Expand immediate that doesn't fit in 12-bit. + unsigned Reg1; + loadImmediate(MBB, I, &Reg1, Amount); + BuildMI(MBB, I, DL, get(Xtensa::ADD), Reg) + .addReg(SP) + .addReg(Reg1, RegState::Kill); + } + + BuildMI(MBB, I, DL, get(Xtensa::OR), SP).addReg(Reg, RegState::Kill).addReg(Reg, RegState::Kill); +} + +void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, MCRegister DestReg, + MCRegister SrcReg, bool KillSrc) const { + // when we are copying a phys reg we want the bits for fp + if (Xtensa::ARRegClass.contains(DestReg, SrcReg)) + BuildMI(MBB, MBBI, DL, get(Xtensa::OR), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addReg(SrcReg, getKillRegState(KillSrc)); + else + llvm_unreachable("Impossible reg-to-reg copy"); +} + +void XtensaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + Register SrcReg, bool isKill, + int FrameIdx, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + Register VReg) const { + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + unsigned LoadOpcode, StoreOpcode; + getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx); + addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode)) + .addReg(SrcReg, getKillRegState(isKill)), + FrameIdx); +} + +void XtensaInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + Register VReg) const { + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + unsigned LoadOpcode, StoreOpcode; + getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx); + addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg), FrameIdx); +} + +void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, + unsigned &LoadOpcode, + unsigned &StoreOpcode, + int64_t offset) const { + if (RC == &Xtensa::ARRegClass) { + LoadOpcode = Xtensa::L32I; + StoreOpcode = Xtensa::S32I; + } else + llvm_unreachable("Unsupported regclass to load or store"); +} + +void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned *Reg, int64_t Value) const { + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); + const TargetRegisterClass *RC = &Xtensa::ARRegClass; + + // create virtual reg to store immediate + *Reg = RegInfo.createVirtualRegister(RC); + if (Value >= -2048 && Value <= 2047) { + BuildMI(MBB, MBBI, DL, get(Xtensa::MOVI), *Reg).addImm(Value); + } else if (Value >= -32768 && Value <= 32767) { + int Low = Value & 0xFF; + int High = Value & ~0xFF; + + BuildMI(MBB, MBBI, DL, get(Xtensa::MOVI), *Reg).addImm(Low); + BuildMI(MBB, MBBI, DL, get(Xtensa::ADDMI), *Reg).addReg(*Reg).addImm(High); + } else if (Value >= -4294967296LL && Value <= 4294967295LL) { + // 32 bit arbirary constant + MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); + uint64_t UVal = ((uint64_t)Value) & 0xFFFFFFFFLL; + const Constant *CVal = ConstantInt::get( + Type::getInt32Ty(MBB.getParent()->getFunction().getContext()), UVal, + false); + unsigned Idx = MCP->getConstantPoolIndex(CVal, Align(2U)); + // MCSymbol MSym + BuildMI(MBB, MBBI, DL, get(Xtensa::L32R), *Reg).addConstantPoolIndex(Idx); + } else { + // use L32R to let assembler load immediate best + // TODO replace to L32R + llvm_unreachable("Unsupported load immediate value"); + } +} diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h index 7225886b2ce119..ddd5392d7ce64b 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h @@ -35,8 +35,35 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { public: XtensaInstrInfo(XtensaSubtarget &STI); + void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; + // Return the XtensaRegisterInfo, which this class owns. const XtensaRegisterInfo &getRegisterInfo() const { return RI; } + + void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, + bool KillSrc) const override; + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + Register VReg) const override; + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + Register VReg) const override; + + // Get the load and store opcodes for a given register class and offset. + void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, + unsigned &StoreOpcode, int64_t offset) const; + + // Emit code before MBBI in MI to move immediate value Value into + // physical register Reg. + void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + unsigned *Reg, int64_t Value) const; }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 5a0f3f8d033dbe..7722f304da1ae9 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -239,6 +239,29 @@ def L32R : RI16_Inst<0x01, (outs AR:$t), (ins L32Rtarget:$label), let imm16 = label; } +//pcrel addr loading using L32R +def : Pat<(Xtensa_pcrel_wrapper tconstpool:$in), (L32R tconstpool:$in)>; + +// FrameIndexes are legalized when they are operands from load/store +// instructions. The same not happens for stack address copies, so an +// add op with mem ComplexPattern is used and the stack address copy +// can be matched. +// Setting of attribute mayLoad is trick to process instruction operands +// in function XtensaRegisterInfo::eliminateFI + +let isCodeGenOnly = 1, mayLoad = 1 in { + + def LEA_ADD : RRI8_Inst<0x02, (outs AR:$t), (ins mem32:$addr), + "addi\t$t, $addr", + [(set AR:$t, addr_ish4:$addr)]> { + bits<12> addr; + + let r = 0x0C; + let imm8{7-0} = addr{11-4}; + let s{3-0} = addr{3-0}; + } +} + //===----------------------------------------------------------------------===// // Conditional branch instructions //===----------------------------------------------------------------------===// @@ -435,6 +458,14 @@ let isReturn = 1, isTerminator = 1, } } +// Call patterns +def : Pat<(Xtensa_call (i32 tglobaladdr:$dst)), + (CALL0 tglobaladdr:$dst)>; +def : Pat<(Xtensa_call (i32 texternalsym:$dst)), + (CALL0 texternalsym:$dst)>; +def : Pat<(Xtensa_call AR:$dst), + (CALLX0 AR:$dst)>; + //===----------------------------------------------------------------------===// // Mem barrier instructions //===----------------------------------------------------------------------===// @@ -507,3 +538,19 @@ def XSR : RSR_Inst<0x00, 0x01, 0x06, (outs AR:$ard, SR:$srd), (ins AR:$t, SR:$sr "xsr\t$t, $sr", []> { let Constraints = "$ard = $t, $srd = $sr"; } + +//===----------------------------------------------------------------------===// +// Stack allocation +//===----------------------------------------------------------------------===// + +// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into +// a stack adjustment and the codegen must know that they may modify the stack +// pointer before prolog-epilog rewriting occurs. +let Defs = [SP], Uses = [SP] in { + def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKDOWN", + [(Xtensa_callseq_start timm:$amt1, timm:$amt2)]>; + def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKUP", + [(Xtensa_callseq_end timm:$amt1, timm:$amt2)]>; +} diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp index 114c562b6f4ef7..4688091a26bb77 100644 --- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp +++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp @@ -28,6 +28,54 @@ XtensaMCInstLower::XtensaMCInstLower(MCContext &ctx, XtensaAsmPrinter &asmPrinter) : Ctx(ctx), Printer(asmPrinter) {} +MCSymbol * +XtensaMCInstLower::GetConstantPoolIndexSymbol(const MachineOperand &MO) const { + // Create a symbol for the name. + return Printer.GetCPISymbol(MO.getIndex()); +} + +MCOperand +XtensaMCInstLower::LowerSymbolOperand(const MachineOperand &MO, + MachineOperand::MachineOperandType MOTy, + unsigned Offset) const { + const MCSymbol *Symbol; + XtensaMCExpr::VariantKind Kind = XtensaMCExpr::VK_Xtensa_None; + + switch (MOTy) { + case MachineOperand::MO_MachineBasicBlock: + Symbol = MO.getMBB()->getSymbol(); + break; + case MachineOperand::MO_GlobalAddress: + Symbol = Printer.getSymbol(MO.getGlobal()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_BlockAddress: + Symbol = Printer.GetBlockAddressSymbol(MO.getBlockAddress()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_ConstantPoolIndex: + Symbol = GetConstantPoolIndexSymbol(MO); + Offset += MO.getOffset(); + break; + default: + llvm_unreachable(""); + } + + const MCExpr *ME = + MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, Ctx); + + ME = XtensaMCExpr::create(ME, Kind, Ctx); + + if (Offset) { + // Assume offset is never negative. + assert(Offset > 0); + + const MCConstantExpr *OffsetExpr = MCConstantExpr::create(Offset, Ctx); + ME = MCBinaryExpr::createAdd(ME, OffsetExpr, Ctx); + } + + return MCOperand::createExpr(ME); +} MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO, unsigned Offset) const { @@ -43,6 +91,8 @@ MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO, return MCOperand::createImm(MO.getImm() + Offset); case MachineOperand::MO_RegisterMask: break; + case MachineOperand::MO_ConstantPoolIndex: + return LowerSymbolOperand(MO, MOTy, Offset); default: llvm_unreachable("unknown operand type"); } diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h index 2b238417ae3eba..32a0ad86a38509 100644 --- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h +++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h @@ -37,6 +37,13 @@ class LLVM_LIBRARY_VISIBILITY XtensaMCInstLower { // Return an MCOperand for MO. Return an empty operand if MO is implicit. MCOperand lowerOperand(const MachineOperand &MO, unsigned Offset = 0) const; + +private: + MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const; + + MCOperand LowerSymbolOperand(const MachineOperand &MO, + MachineOperand::MachineOperandType MOTy, + unsigned Offset) const; }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 7a1a2e86e8c20f..034aef55f76350 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -195,7 +195,7 @@ def jumptarget : Operand { let ParserMatchClass = XtensaPCRelTargetAsmOperand; } -def L32Rtarget : Operand { +def L32Rtarget: Operand { let PrintMethod = "printL32RTarget"; let EncoderMethod = "getL32RTargetEncoding"; let DecoderMethod = "decodeL32ROperand"; diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index 6b1f8e4f9b08e2..bb764d2c9247b5 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -8,8 +8,32 @@ // //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// Type profiles +//===----------------------------------------------------------------------===// + +def SDT_XtensaCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_XtensaCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_XtensaCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; +def SDT_XtensaWrapPtr : SDTypeProfile<1, 1, + [SDTCisSameAs<0, 1>, + SDTCisPtrTy<0>]>; + //===----------------------------------------------------------------------===// // Node definitions //===----------------------------------------------------------------------===// + +def Xtensa_call: SDNode<"XtensaISD::CALL", SDT_XtensaCall, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; + def Xtensa_retflag: SDNode<"XtensaISD::RET_FLAG", SDTNone, - [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + + +def Xtensa_callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_XtensaCallSeqStart, + [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; +def Xtensa_callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XtensaCallSeqEnd, + [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, + SDNPOutGlue]>; + +def Xtensa_pcrel_wrapper: SDNode<"XtensaISD::PCREL_WRAPPER", SDT_XtensaWrapPtr, []>; diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index 5cebe4a3346b25..559443f07fbb87 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -15,6 +15,7 @@ #include "XtensaRegisterInfo.h" #include "XtensaInstrInfo.h" #include "XtensaSubtarget.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/Debug.h" @@ -57,11 +58,117 @@ BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { return Reserved; } +bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II, + unsigned OpNo, int FrameIndex, + uint64_t StackSize, + int64_t SPOffset) const { + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + + const std::vector &CSI = MFI.getCalleeSavedInfo(); + int MinCSFI = 0; + int MaxCSFI = -1; + + if (CSI.size()) { + MinCSFI = CSI[0].getFrameIdx(); + MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); + } + + // The following stack frame objects are always referenced relative to $sp: + // 1. Outgoing arguments. + // 2. Pointer to dynamically allocated stack space. + // 3. Locations for callee-saved registers. + // 4. Locations for eh data registers. + // Everything else is referenced relative to whatever register + // getFrameRegister() returns. + unsigned FrameReg; + + if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)) + FrameReg = Xtensa::SP; + else + FrameReg = getFrameRegister(MF); + + // Calculate final offset. + // - There is no need to change the offset if the frame object is one of the + // following: an outgoing argument, pointer to a dynamically allocated + // stack space or a $gp restore location, + // - If the frame object is any of the following, its offset must be adjusted + // by adding the size of the stack: + // incoming argument, callee-saved register location or local variable. + bool IsKill = false; + int64_t Offset; + + Offset = SPOffset + (int64_t)StackSize; + Offset += MI.getOperand(OpNo + 1).getImm(); + + LLVM_DEBUG(errs() << "Offset : " << Offset << "\n" + << "<--------->\n"); + + bool Valid = false; + switch (MI.getOpcode()) { + case Xtensa::L8UI: + case Xtensa::S8I: + Valid = (Offset >= 0 && Offset <= 255); + break; + case Xtensa::L16SI: + case Xtensa::L16UI: + case Xtensa::S16I: + Valid = (Offset >= 0 && Offset <= 510); + break; + case Xtensa::LEA_ADD: + Valid = (Offset >= -128 && Offset <= 127); + break; + default: + Valid = (Offset >= 0 && Offset <= 1020); + break; + } + + // If MI is not a debug value, make sure Offset fits in the 16-bit immediate + // field. + if (!MI.isDebugValue() && !Valid) { + MachineBasicBlock &MBB = *MI.getParent(); + DebugLoc DL = II->getDebugLoc(); + unsigned ADD = Xtensa::ADD; + unsigned Reg; + const XtensaInstrInfo &TII = *static_cast( + MBB.getParent()->getSubtarget().getInstrInfo()); + + TII.loadImmediate(MBB, II, &Reg, Offset); + BuildMI(MBB, II, DL, TII.get(ADD), Reg) + .addReg(FrameReg) + .addReg(Reg, RegState::Kill); + + FrameReg = Reg; + Offset = 0; + IsKill = true; + } + + MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); + MI.getOperand(OpNo + 1).ChangeToImmediate(Offset); + + return false; +} + bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { - report_fatal_error("Eliminate frame index not supported yet"); - return false; + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + + LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; + errs() << "<--------->\n" + << MI); + + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); + uint64_t stackSize = MF.getFrameInfo().getStackSize(); + int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex); + + LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" + << "spOffset : " << spOffset << "\n" + << "stackSize : " << stackSize << "\n"); + + return eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); } Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const { diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h index 4f5426acf7a559..ba5557c446b637 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h @@ -49,6 +49,11 @@ struct XtensaRegisterInfo : public XtensaGenRegisterInfo { unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; Register getFrameRegister(const MachineFunction &MF) const override; + +private: + bool eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, + int FrameIndex, uint64_t StackSize, + int64_t SPOffset) const; }; } // end namespace llvm From f021fe2b0120acb7c2a7652c2688b7d6b126d905 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:24 +0300 Subject: [PATCH 007/261] [Xtensa] Implement lowering ConstantPool and address operations. Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 103 +++++++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 5 + llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp | 22 ++++ llvm/lib/Target/Xtensa/XtensaMCInstLower.h | 4 + 4 files changed, 133 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 48b67b8a62f2cb..58f2b6d7a4ae16 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -43,6 +43,7 @@ static bool isLongCall(const char *str) { XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, const XtensaSubtarget &STI) : TargetLowering(tm), Subtarget(STI) { + MVT PtrVT = MVT::i32; // Set up the register classes. addRegisterClass(MVT::i32, &Xtensa::ARRegClass); @@ -68,10 +69,22 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); } + // Handle the various types of symbolic address. + setOperationAction(ISD::ConstantPool, PtrVT, Custom); + setOperationAction(ISD::GlobalAddress, PtrVT, Custom); + setOperationAction(ISD::BlockAddress, PtrVT, Custom); + setOperationAction(ISD::JumpTable, PtrVT, Custom); + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); } +bool XtensaTargetLowering::isOffsetFoldingLegal( + const GlobalAddressSDNode *GA) const { + // The Xtensa target isn't yet aware of offsets. + return false; +} + bool XtensaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const { return false; @@ -482,7 +495,7 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, } bool XtensaTargetLowering::CanLowerReturn( - CallingConv::ID CallConv, MachineFunction & MF, bool IsVarArg, + CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { SmallVector RVLocs; CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); @@ -571,6 +584,86 @@ SDValue XtensaTargetLowering::LowerImmediateFP(SDValue Op, return Op; } +SDValue XtensaTargetLowering::LowerGlobalAddress(SDValue Op, + SelectionDAG &DAG) const { + // Reloc::Model RM = DAG.getTarget().getRelocationModel(); + SDLoc DL(Op); + + if (GlobalAddressSDNode *G = dyn_cast(Op)) { + auto PtrVt = getPointerTy(DAG.getDataLayout()); + const GlobalValue *GV = G->getGlobal(); + + // Check Op SDNode users + // If there are only CALL nodes, don't expand Global Address + SDNode &OpNode = *Op.getNode(); + bool Val = false; + for (SDNode::use_iterator UI = OpNode.use_begin(); UI != OpNode.use_end(); + ++UI) { + SDNode &User = *UI.getUse().getUser(); + unsigned OpCode = User.getOpcode(); + if (OpCode != XtensaISD::CALL) { + Val = true; + break; + } + } + if (!Val) { + SDValue TargAddr = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVt, + 0, 0 /* TargetFlags */); + return TargAddr; + } + + SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVt, Align(4)); + SDValue CPWrap = getAddrPCRel(CPAddr, DAG); + + return CPWrap; + } + llvm_unreachable("invalid global addresses to lower"); +} + +SDValue XtensaTargetLowering::LowerBlockAddress(BlockAddressSDNode *Node, + SelectionDAG &DAG) const { + const BlockAddress *BA = Node->getBlockAddress(); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + + XtensaConstantPoolValue *CPV = + XtensaConstantPoolConstant::Create(BA, 0, XtensaCP::CPBlockAddress, 0); + SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4)); + + SDValue CPWrap = getAddrPCRel(CPAddr, DAG); + return CPWrap; +} + +SDValue XtensaTargetLowering::LowerJumpTable(JumpTableSDNode *JT, + SelectionDAG &DAG) const { + SDLoc DL(JT); + EVT PtrVt = getPointerTy(DAG.getDataLayout()); + + // Create a constant pool entry for the callee address + XtensaConstantPoolValue *CPV = + XtensaConstantPoolJumpTable::Create(*DAG.getContext(), JT->getIndex()); + + // Get the address of the callee into a register + SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4)); + SDValue CPWrap = getAddrPCRel(CPAddr, DAG); + + return CPWrap; +} + +SDValue XtensaTargetLowering::LowerConstantPool(ConstantPoolSDNode *CP, + SelectionDAG &DAG) const { + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + + SDValue Result; + if (CP->isMachineConstantPoolEntry()) + Result = + DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign()); + else + Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(), + CP->getOffset()); + + return getAddrPCRel(Result, DAG); +} + SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -578,6 +671,14 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerImmediate(Op, DAG); case ISD::ConstantFP: return LowerImmediateFP(Op, DAG); + case ISD::GlobalAddress: + return LowerGlobalAddress(Op, DAG); + case ISD::BlockAddress: + return LowerBlockAddress(cast(Op), DAG); + case ISD::JumpTable: + return LowerJumpTable(cast(Op), DAG); + case ISD::ConstantPool: + return LowerConstantPool(cast(Op), DAG); default: llvm_unreachable("Unexpected node to lower"); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 18c7772a43451a..0fbfffe34d43f2 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -46,6 +46,7 @@ class XtensaTargetLowering : public TargetLowering { explicit XtensaTargetLowering(const TargetMachine &TM, const XtensaSubtarget &STI); + bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; const char *getTargetNodeName(unsigned Opcode) const override; @@ -73,6 +74,10 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const; SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerBlockAddress(BlockAddressSDNode *Node, SelectionDAG &DAG) const; + SDValue LowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; + SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp index 4688091a26bb77..d3dc082617e159 100644 --- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp +++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp @@ -28,6 +28,16 @@ XtensaMCInstLower::XtensaMCInstLower(MCContext &ctx, XtensaAsmPrinter &asmPrinter) : Ctx(ctx), Printer(asmPrinter) {} +MCSymbol * +XtensaMCInstLower::GetExternalSymbolSymbol(const MachineOperand &MO) const { + return Printer.GetExternalSymbolSymbol(MO.getSymbolName()); +} + +MCSymbol * +XtensaMCInstLower::GetJumpTableSymbol(const MachineOperand &MO) const { + return Printer.GetJTISymbol(MO.getIndex()); +} + MCSymbol * XtensaMCInstLower::GetConstantPoolIndexSymbol(const MachineOperand &MO) const { // Create a symbol for the name. @@ -53,6 +63,13 @@ XtensaMCInstLower::LowerSymbolOperand(const MachineOperand &MO, Symbol = Printer.GetBlockAddressSymbol(MO.getBlockAddress()); Offset += MO.getOffset(); break; + case MachineOperand::MO_ExternalSymbol: + Symbol = GetExternalSymbolSymbol(MO); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_JumpTableIndex: + Symbol = GetJumpTableSymbol(MO); + break; case MachineOperand::MO_ConstantPoolIndex: Symbol = GetConstantPoolIndexSymbol(MO); Offset += MO.getOffset(); @@ -91,7 +108,12 @@ MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO, return MCOperand::createImm(MO.getImm() + Offset); case MachineOperand::MO_RegisterMask: break; + case MachineOperand::MO_MachineBasicBlock: + case MachineOperand::MO_GlobalAddress: + case MachineOperand::MO_ExternalSymbol: + case MachineOperand::MO_JumpTableIndex: case MachineOperand::MO_ConstantPoolIndex: + case MachineOperand::MO_BlockAddress: return LowerSymbolOperand(MO, MOTy, Offset); default: llvm_unreachable("unknown operand type"); diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h index 32a0ad86a38509..344c28058adcf8 100644 --- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h +++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h @@ -39,6 +39,10 @@ class LLVM_LIBRARY_VISIBILITY XtensaMCInstLower { MCOperand lowerOperand(const MachineOperand &MO, unsigned Offset = 0) const; private: + MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const; + + MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const; + MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const; MCOperand LowerSymbolOperand(const MachineOperand &MO, From 4467c82706edb882d4db0124e694bf601d254455 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:24 +0300 Subject: [PATCH 008/261] [Xtensa] Implement emitPrologue/emitEpilogue --- .../lib/Target/Xtensa/XtensaFrameLowering.cpp | 223 +++++++++++++++++- llvm/lib/Target/Xtensa/XtensaFrameLowering.h | 13 + 2 files changed, 234 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index 71941e7671930e..e87f2809a51eef 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -28,6 +28,48 @@ XtensaFrameLowering::XtensaFrameLowering() : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 0, Align(4)) {} +/* Xtensa stack frames look like: + + +-------------------------------+ + | incoming stack arguments | + +-------------------------------+ + A | caller-allocated save area | + | for register arguments | + +-------------------------------+ <-- incoming stack pointer + B | CALL0 ABI: | + | callee-allocated save area | + | for arguments that are | + | split between registers and | + | the stack (Register-Spill | + | Area) | + | | + | Win ABI: | + | Register-Spill Overflow | + | 8 words for CALL8/CALLX8 | + +-------------------------------+ <-- arg_pointer_rtx + C | callee-allocated save area | + | for register varargs | + +-------------------------------+ <-- hard_frame_pointer_rtx; + | | stack_pointer_rtx + gp_sp_offset + | GPR save area | + UNITS_PER_WORD + +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset + | | + UNITS_PER_HWVALUE + | FPR save area | + +-------------------------------+ <-- frame_pointer_rtx (virtual) + | local variables | + P +-------------------------------+ + | outgoing stack arguments | + +-------------------------------+ + | caller-allocated save area | + | for register arguments | + +-------------------------------+ <-- stack_pointer_rtx + + At least two of A, B and C will be empty. + + Dynamic stack allocations such as alloca insert data at point P. + They decrease stack_pointer_rtx but leave frame_pointer_rtx and + hard_frame_pointer_rtx unchanged. */ + // hasFP - Return true if the specified function should have a dedicated frame // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. @@ -38,10 +80,159 @@ bool XtensaFrameLowering::hasFP(const MachineFunction &MF) const { } void XtensaFrameLowering::emitPrologue(MachineFunction &MF, - MachineBasicBlock &MBB) const {} + MachineBasicBlock &MBB) const { + assert(&MBB == &MF.front() && "Shrink-wrapping not yet implemented"); + MachineFrameInfo &MFI = MF.getFrameInfo(); + const XtensaRegisterInfo *RegInfo = static_cast( + MF.getSubtarget().getRegisterInfo()); + const XtensaInstrInfo &TII = + *static_cast(MF.getSubtarget().getInstrInfo()); + MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + unsigned SP = Xtensa::SP; + unsigned FP = RegInfo->getFrameRegister(MF); + MachineModuleInfo &MMI = MF.getMMI(); + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + + // First, compute final stack size. + uint64_t StackSize = MFI.getStackSize(); + uint64_t PrevStackSize = StackSize; + + // Round up StackSize to 16*N + StackSize += (16 - StackSize) & 0xf; + + // No need to allocate space on the stack. + if (StackSize == 0 && !MFI.adjustsStack()) + return; + + // Adjust stack. + TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); + + // emit ".cfi_def_cfa_offset StackSize" + unsigned CFIIndex = MF.addFrameInst( + MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + + const std::vector &CSI = MFI.getCalleeSavedInfo(); + + if (CSI.size()) { + // Find the instruction past the last instruction that saves a + // callee-saved register to the stack. + for (unsigned i = 0; i < CSI.size(); ++i) + ++MBBI; + + // Iterate over list of callee-saved registers and emit .cfi_offset + // directives. + for (const auto &I : CSI) { + int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); + unsigned Reg = I.getReg(); + + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( + nullptr, MRI->getDwarfRegNum(Reg, 1), Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + } + } + + // if framepointer enabled, set it to point to the stack pointer. + if (hasFP(MF)) { + // Insert instruction "move $fp, $sp" at this location. + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::OR), FP) + .addReg(SP) + .addReg(SP) + .setMIFlag(MachineInstr::FrameSetup); + + // emit ".cfi_def_cfa_register $fp" + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( + nullptr, MRI->getDwarfRegNum(FP, true))); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + } + + if (StackSize != PrevStackSize) { + MFI.setStackSize(StackSize); + + for (int i = MFI.getObjectIndexBegin(); i < MFI.getObjectIndexEnd(); i++) { + if (!MFI.isDeadObjectIndex(i)) { + int64_t SPOffset = MFI.getObjectOffset(i); + + if (SPOffset < 0) + MFI.setObjectOffset(i, SPOffset - StackSize + PrevStackSize); + } + } + } +} void XtensaFrameLowering::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const {} + MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + const XtensaRegisterInfo *RegInfo = static_cast( + MF.getSubtarget().getRegisterInfo()); + const XtensaInstrInfo &TII = + *static_cast(MF.getSubtarget().getInstrInfo()); + DebugLoc dl = MBBI->getDebugLoc(); + unsigned SP = Xtensa::SP; + unsigned FP = RegInfo->getFrameRegister(MF); + + // if framepointer enabled, restore the stack pointer. + if (hasFP(MF)) { + // Find the first instruction that restores a callee-saved register. + MachineBasicBlock::iterator I = MBBI; + + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) + --I; + + BuildMI(MBB, I, dl, TII.get(Xtensa::OR), SP).addReg(FP).addReg(FP); + } + + // Get the number of bytes from FrameInfo + uint64_t StackSize = MFI.getStackSize(); + + if (!StackSize) + return; + + // Adjust stack. + TII.adjustStackPtr(SP, StackSize, MBB, MBBI); +} + +bool XtensaFrameLowering::spillCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + ArrayRef CSI, const TargetRegisterInfo *TRI) const { + MachineFunction *MF = MBB.getParent(); + + MachineBasicBlock &EntryBlock = *(MF->begin()); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + // Add the callee-saved register as live-in. Do not add if the register is + // A0 and return address is taken, because it will be implemented in + // method XtensaTargetLowering::LowerRETURNADDR. + // It's killed at the spill, unless the register is RA and return address + // is taken. + unsigned Reg = CSI[i].getReg(); + bool IsA0AndRetAddrIsTaken = + (Reg == Xtensa::A0) && MF->getFrameInfo().isReturnAddressTaken(); + if (!IsA0AndRetAddrIsTaken) + EntryBlock.addLiveIn(Reg); + + // Insert the spill to the stack frame. + bool IsKill = !IsA0AndRetAddrIsTaken; + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), + RC, TRI, Register()); + } + + return true; +} + +bool XtensaFrameLowering::restoreCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + MutableArrayRef CSI, + const TargetRegisterInfo *TRI) const { + return TargetFrameLowering::restoreCalleeSavedRegisters(MBB, MI, CSI, TRI); +} // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions MachineBasicBlock::iterator XtensaFrameLowering::eliminateCallFramePseudoInstr( @@ -62,3 +253,31 @@ MachineBasicBlock::iterator XtensaFrameLowering::eliminateCallFramePseudoInstr( return MBB.erase(I); } + +void XtensaFrameLowering::determineCalleeSaves(MachineFunction &MF, + BitVector &SavedRegs, + RegScavenger *RS) const { + MachineFrameInfo &MFI = MF.getFrameInfo(); + const XtensaRegisterInfo *RegInfo = static_cast( + MF.getSubtarget().getRegisterInfo()); + unsigned FP = RegInfo->getFrameRegister(MF); + + TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); + + // Mark $fp as used if function has dedicated frame pointer. + if (hasFP(MF)) + SavedRegs.set(FP); + + // Set scavenging frame index if necessary. + uint64_t MaxSPOffset = MFI.estimateStackSize(MF); + + if (isInt<12>(MaxSPOffset)) + return; + + const TargetRegisterClass &RC = Xtensa::ARRegClass; + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + unsigned Size = TRI->getSpillSize(RC); + Align Alignment = TRI->getSpillAlign(RC); + int FI = MF.getFrameInfo().CreateStackObject(Size, Alignment, false); + RS->addScavengingFrameIndex(FI); +} diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h index 584438d179bb8a..b112f069cd618a 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h @@ -31,6 +31,19 @@ class XtensaFrameLowering : public TargetFrameLowering { MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override; + + bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + ArrayRef CSI, + const TargetRegisterInfo *TRI) const override; + bool + restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + MutableArrayRef CSI, + const TargetRegisterInfo *TRI) const override; + + void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, + RegScavenger *RS) const override; }; } // namespace llvm From 58fad1a3d1c6d4d3a7df3f06f0230a55312dddd2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:25 +0300 Subject: [PATCH 009/261] [Xtensa] Lower stack operations Implement lowering of dynamic_stackalloc, stacksave, stackrestore. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 49 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 4 ++ 2 files changed, 53 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 58f2b6d7a4ae16..6ef6471cef9d03 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -75,6 +75,12 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::BlockAddress, PtrVT, Custom); setOperationAction(ISD::JumpTable, PtrVT, Custom); + // Implement custom stack allocations + setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom); + // Implement custom stack save and restore + setOperationAction(ISD::STACKSAVE, MVT::Other, Custom); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom); + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); } @@ -664,6 +670,43 @@ SDValue XtensaTargetLowering::LowerConstantPool(ConstantPoolSDNode *CP, return getAddrPCRel(Result, DAG); } +SDValue XtensaTargetLowering::LowerSTACKSAVE(SDValue Op, + SelectionDAG &DAG) const { + unsigned sp = Xtensa::SP; + return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op), sp, Op.getValueType()); +} + +SDValue XtensaTargetLowering::LowerSTACKRESTORE(SDValue Op, + SelectionDAG &DAG) const { + unsigned sp = Xtensa::SP; + return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op), sp, Op.getOperand(1)); +} + +SDValue XtensaTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, + SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); // Legalize the chain. + SDValue Size = Op.getOperand(1); // Legalize the size. + EVT VT = Size->getValueType(0); + SDLoc DL(Op); + + // Round up Size to 32 + SDValue Size1 = + DAG.getNode(ISD::ADD, DL, VT, Size, DAG.getConstant(31, DL, MVT::i32)); + SDValue SizeRoundUp = + DAG.getNode(ISD::AND, DL, VT, Size1, DAG.getConstant(~31, DL, MVT::i32)); + + unsigned SPReg = Xtensa::SP; + SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT); + SDValue NewSP = DAG.getNode(ISD::SUB, DL, VT, SP, SizeRoundUp); // Value + Chain = DAG.getCopyToReg(SP.getValue(1), DL, SPReg, NewSP); // Output chain + + SDValue NewVal = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32); + Chain = NewVal.getValue(1); + + SDValue Ops[2] = {NewVal, Chain}; + return DAG.getMergeValues(Ops, DL); +} + SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -679,6 +722,12 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerJumpTable(cast(Op), DAG); case ISD::ConstantPool: return LowerConstantPool(cast(Op), DAG); + case ISD::STACKSAVE: + return LowerSTACKSAVE(Op, DAG); + case ISD::STACKRESTORE: + return LowerSTACKRESTORE(Op, DAG); + case ISD::DYNAMIC_STACKALLOC: + return LowerDYNAMIC_STACKALLOC(Op, DAG); default: llvm_unreachable("Unexpected node to lower"); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 0fbfffe34d43f2..f2435cc1883462 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -79,6 +79,10 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; + SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; + SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; From 607bf2a183fbb360fe9886bcb25d781f3dac4f37 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:25 +0300 Subject: [PATCH 010/261] [Xtensa] Implement lowering SELECT_CC, SETCC --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 208 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 27 ++- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 41 ++++ llvm/lib/Target/Xtensa/XtensaOperators.td | 8 + 4 files changed, 283 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 6ef6471cef9d03..77aebe942a312c 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -75,6 +75,27 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::BlockAddress, PtrVT, Custom); setOperationAction(ISD::JumpTable, PtrVT, Custom); + // Used by legalize types to correctly generate the setcc result. + // AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); + setOperationPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); + setOperationPromotedToType(ISD::BR_CC, MVT::i1, MVT::i32); + + setOperationAction(ISD::BR_CC, MVT::i32, Legal); + setOperationAction(ISD::BR_CC, MVT::i64, Expand); + + setOperationAction(ISD::SELECT, MVT::i32, Expand); + setOperationAction(ISD::SELECT, MVT::i64, Expand); + + setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); + + setOperationAction(ISD::SETCC, MVT::i32, + Custom); // folds into brcond + setOperationAction(ISD::SETCC, MVT::i64, Expand); + + // make BRCOND legal, its actually only legal for a subset of conds + setOperationAction(ISD::BRCOND, MVT::Other, Legal); + // Implement custom stack allocations setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom); // Implement custom stack save and restore @@ -558,6 +579,56 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, return DAG.getNode(XtensaISD::RET_FLAG, DL, MVT::Other, RetOps); } +SDValue XtensaTargetLowering::LowerSELECT_CC(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT Ty = Op.getOperand(0).getValueType(); + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + SDValue TrueV = Op.getOperand(2); + SDValue FalseV = Op.getOperand(3); + ISD::CondCode CC = cast(Op->getOperand(4))->get(); + SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32); + + // Wrap select nodes + return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueV, FalseV, + TargetCC); +} + +SDValue XtensaTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT Ty = Op.getOperand(0).getValueType(); + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + ISD::CondCode CC = cast(Op.getOperand(2))->get(); + SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32); + + // Check Op SDNode users + // If there are only CALL/CALLW nodes, don't expand Global Address + SDNode &OpNode = *Op.getNode(); + bool Val = false; + for (SDNode::use_iterator UI = OpNode.use_begin(); UI != OpNode.use_end(); + ++UI) { + SDNode &User = *UI.getUse().getUser(); + unsigned OpCode = User.getOpcode(); + if (OpCode == ISD::BRCOND) { + Val = true; + break; + } + } + + // SETCC has BRCOND predecessor, return original operation + if (Val) + return Op; + + // Expand to target SELECT_CC + SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType()); + SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType()); + + return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueV, FalseV, + TargetCC); +} + SDValue XtensaTargetLowering::LowerImmediate(SDValue Op, SelectionDAG &DAG) const { const ConstantSDNode *CN = cast(Op); @@ -714,6 +785,10 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerImmediate(Op, DAG); case ISD::ConstantFP: return LowerImmediateFP(Op, DAG); + case ISD::SETCC: + return LowerSETCC(Op, DAG); + case ISD::SELECT_CC: + return LowerSELECT_CC(Op, DAG); case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); case ISD::BlockAddress: @@ -741,7 +816,140 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(RET_FLAG); OPCODE(CALL); OPCODE(PCREL_WRAPPER); + OPCODE(SELECT); + OPCODE(SELECT_CC); } return NULL; #undef OPCODE } + +//===----------------------------------------------------------------------===// +// Custom insertion +//===----------------------------------------------------------------------===// + +static int GetBranchKind(int Cond, bool &BrInv) { + switch (Cond) { + case ISD::SETEQ: + case ISD::SETOEQ: + case ISD::SETUEQ: + return Xtensa::BEQ; + case ISD::SETNE: + case ISD::SETONE: + case ISD::SETUNE: + return Xtensa::BNE; + case ISD::SETLT: + case ISD::SETOLT: + return Xtensa::BLT; + case ISD::SETLE: + case ISD::SETOLE: + BrInv = true; + return Xtensa::BGE; + case ISD::SETGT: + case ISD::SETOGT: + BrInv = true; + return Xtensa::BLT; + case ISD::SETGE: + case ISD::SETOGE: + return Xtensa::BGE; + case ISD::SETULT: + return Xtensa::BLTU; + case ISD::SETULE: + BrInv = true; + return Xtensa::BGEU; + case ISD::SETUGT: + BrInv = true; + return Xtensa::BLTU; + case ISD::SETUGE: + return Xtensa::BGEU; + default: + return -1; + } +} + +MachineBasicBlock * +XtensaTargetLowering::emitSelectCC(MachineInstr &MI, + MachineBasicBlock *BB) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + MachineOperand &LHS = MI.getOperand(1); + MachineOperand &RHS = MI.getOperand(2); + MachineOperand &TrueV = MI.getOperand(3); + MachineOperand &FalseV = MI.getOperand(4); + MachineOperand &Cond = MI.getOperand(5); + + // To "insert" a SELECT_CC instruction, we actually have to insert the + // diamond control-flow pattern. The incoming instruction knows the + // destination vreg to set, the condition code register to branch on, the + // true/false values to select between, and a branch opcode to use. + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + // thisMBB: + // ... + // TrueVal = ... + // cmpTY ccX, r1, r2 + // bCC copy1MBB + // fallthrough --> copy0MBB + MachineBasicBlock *thisMBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); + + // Transfer the remainder of BB and its successor edges to sinkMBB. + sinkMBB->splice(sinkMBB->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + sinkMBB->transferSuccessorsAndUpdatePHIs(BB); + + // Next, add the true and fallthrough blocks as its successors. + BB->addSuccessor(copy0MBB); + BB->addSuccessor(sinkMBB); + + bool BrInv = false; + int BrKind = GetBranchKind(Cond.getImm(), BrInv); + if (BrInv) { + BuildMI(BB, DL, TII.get(BrKind)) + .addReg(RHS.getReg()) + .addReg(LHS.getReg()) + .addMBB(sinkMBB); + } else { + BuildMI(BB, DL, TII.get(BrKind)) + .addReg(LHS.getReg()) + .addReg(RHS.getReg()) + .addMBB(sinkMBB); + } + // copy0MBB: + // %FalseValue = ... + // # fallthrough to sinkMBB + BB = copy0MBB; + + // Update machine-CFG edges + BB->addSuccessor(sinkMBB); + + // sinkMBB: + // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] + // ... + BB = sinkMBB; + + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), MI.getOperand(0).getReg()) + .addReg(FalseV.getReg()) + .addMBB(copy0MBB) + .addReg(TrueV.getReg()) + .addMBB(thisMBB); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *MBB) const { + switch (MI.getOpcode()) { + case Xtensa::SELECT: + return emitSelectCC(MI, MBB); + default: + llvm_unreachable("Unexpected instr type to insert"); + } +} diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index f2435cc1883462..f8da0ab75913ad 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -35,7 +35,14 @@ enum { PCREL_WRAPPER, // Return with a flag operand. Operand 0 is the chain operand. - RET_FLAG + RET_FLAG, + + // Selects between operand 0 and operand 1. Operand 2 is the + // mask of condition-code values for which operand 0 should be + // chosen over operand 1; it has the same form as BR_CCMASK. + // Operand 3 is the flag operand. + SELECT, + SELECT_CC }; } @@ -46,6 +53,13 @@ class XtensaTargetLowering : public TargetLowering { explicit XtensaTargetLowering(const TargetMachine &TM, const XtensaSubtarget &STI); + EVT getSetCCResultType(const DataLayout &, LLVMContext &, + EVT VT) const override { + if (!VT.isVector()) + return MVT::i32; + return VT.changeVectorElementTypeToInteger(); + } + bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; @@ -69,6 +83,10 @@ class XtensaTargetLowering : public TargetLowering { const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override; + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const override; + private: const XtensaSubtarget &Subtarget; @@ -79,6 +97,9 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; + SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; @@ -86,6 +107,10 @@ class XtensaTargetLowering : public TargetLowering { SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; + + // Implement EmitInstrWithCustomInserter for individual operation types. + MachineBasicBlock *emitSelectCC(MachineInstr &MI, + MachineBasicBlock *BB) const; }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 7722f304da1ae9..88771588d1b9a4 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -411,6 +411,38 @@ def BBSI : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : Pat<(brcc SETGT, AR:$s, AR:$t, bb:$target), + (BLT AR:$t, AR:$s, bb:$target)>; +def : Pat<(brcc SETUGT, AR:$s, AR:$t, bb:$target), + (BLTU AR:$t, AR:$s, bb:$target)>; +def : Pat<(brcc SETLE, AR:$s, AR:$t, bb:$target), + (BGE AR:$t, AR:$s, bb:$target)>; +def : Pat<(brcc SETULE, AR:$s, AR:$t, bb:$target), + (BGEU AR:$t, AR:$s, bb:$target)>; + +def : Pat<(brcond (i32 (seteq AR:$s, AR:$t)), bb:$target), + (BEQ AR:$s, AR:$t, bb:$target)>; +def : Pat<(brcond (i32 (setne AR:$s, AR:$t)), bb:$target), + (BNE AR:$s, AR:$t, bb:$target)>; +def : Pat<(brcond (i32 (setge AR:$s, AR:$t)), bb:$target), + (BGE AR:$s, AR:$t, bb:$target)>; +def : Pat<(brcond (i32 (setle AR:$s, AR:$t)), bb:$target), + (BLT AR:$s, AR:$t, bb:$target)>; +def : Pat<(brcond (i32 (setuge AR:$s, AR:$t)), bb:$target), + (BGEU AR:$s, AR:$t, bb:$target)>; +def : Pat<(brcond (i32 (setult AR:$s, AR:$t)), bb:$target), + (BLTU AR:$s, AR:$t, bb:$target)>; +def : Pat<(brcond (i32 (setgt AR:$s, AR:$t)), bb:$target), + (BLT AR:$t, AR:$s, bb:$target)>; +def : Pat<(brcond (i32 (setugt AR:$s, AR:$t)), bb:$target), + (BLTU AR:$t, AR:$s, bb:$target)>; +def : Pat<(brcond (i32 (setle AR:$s, AR:$t)), bb:$target), + (BGE AR:$t, AR:$s, bb:$target)>; +def : Pat<(brcond (i32 (setule AR:$s, AR:$t)), bb:$target), + (BGEU AR:$t, AR:$s, bb:$target)>; + +def : Pat<(brcond AR:$s, bb:$target), (BNEZ AR:$s, bb:$target)>; + //===----------------------------------------------------------------------===// // Call and jump instructions //===----------------------------------------------------------------------===// @@ -554,3 +586,12 @@ let Defs = [SP], Uses = [SP] in { "#ADJCALLSTACKUP", [(Xtensa_callseq_end timm:$amt1, timm:$amt2)]>; } + +//===----------------------------------------------------------------------===// +// Generic select instruction +//===----------------------------------------------------------------------===// +let usesCustomInserter = 1 in { + def SELECT : Pseudo<(outs AR:$dst), (ins AR:$lhs, AR:$rhs, AR:$t, AR:$f, i32imm:$cond), + "!select $dst, $lhs, $rhs, $t, $f, $cond", + [(set AR:$dst, (Xtensa_select_cc AR:$lhs, AR:$rhs, AR:$t, AR:$f, imm:$cond))]>; +} diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index bb764d2c9247b5..a85550c46531ed 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -19,6 +19,10 @@ def SDT_XtensaWrapPtr : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; +def SDT_XtensaSelectCC : SDTypeProfile<1, 5, + [SDTCisSameAs<0, 1>, + SDTCisSameAs<2, 3>, + SDTCisVT<5, i32>]>; //===----------------------------------------------------------------------===// // Node definitions //===----------------------------------------------------------------------===// @@ -37,3 +41,7 @@ def Xtensa_callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XtensaCallSeqEnd, SDNPOutGlue]>; def Xtensa_pcrel_wrapper: SDNode<"XtensaISD::PCREL_WRAPPER", SDT_XtensaWrapPtr, []>; + +def Xtensa_select : SDNode<"XtensaISD::SELECT", SDTSelect>; +def Xtensa_select_cc: SDNode<"XtensaISD::SELECT_CC", SDT_XtensaSelectCC, + [SDNPInGlue]>; From 40faf087ac8041dfa7c7b9237e4fe3f4e28318dd Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:26 +0300 Subject: [PATCH 011/261] [Xtensa] Support for a variety of additional LLVM IR constructs. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 77aebe942a312c..a8c24a7f9bf646 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -96,6 +96,64 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, // make BRCOND legal, its actually only legal for a subset of conds setOperationAction(ISD::BRCOND, MVT::Other, Legal); + // Handle integer types. + for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE; + I <= MVT::LAST_INTEGER_VALUETYPE; ++I) { + MVT VT = MVT::SimpleValueType(I); + if (isTypeLegal(VT)) { + // No support at all + setOperationAction(ISD::SDIVREM, VT, Expand); + setOperationAction(ISD::UDIVREM, VT, Expand); + } + } + + setOperationAction(ISD::MUL, MVT::i32, Expand); + setOperationAction(ISD::MULHU, MVT::i32, Expand); + setOperationAction(ISD::MULHS, MVT::i32, Expand); + setOperationAction(ISD::MUL, MVT::i64, Expand); + setOperationAction(ISD::MULHS, MVT::i64, Expand); + setOperationAction(ISD::MULHU, MVT::i64, Expand); + + setOperationAction(ISD::SDIV, MVT::i32, Expand); + setOperationAction(ISD::UDIV, MVT::i32, Expand); + setOperationAction(ISD::SREM, MVT::i32, Expand); + setOperationAction(ISD::UREM, MVT::i32, Expand); + + setOperationAction(ISD::SDIV, MVT::i64, Expand); + setOperationAction(ISD::UDIV, MVT::i64, Expand); + setOperationAction(ISD::SREM, MVT::i64, Expand); + setOperationAction(ISD::UREM, MVT::i64, Expand); + + // Xtensa doesn't support [ADD,SUB][E,C] + setOperationAction(ISD::ADDC, MVT::i32, Expand); + setOperationAction(ISD::ADDE, MVT::i32, Expand); + setOperationAction(ISD::SUBC, MVT::i32, Expand); + setOperationAction(ISD::SUBE, MVT::i32, Expand); + + setOperationAction(ISD::ADD, MVT::i64, Expand); + setOperationAction(ISD::SUB, MVT::i64, Expand); + + // Bit Manipulation + setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::BSWAP, MVT::i64, Expand); + setOperationAction(ISD::ROTL, MVT::i32, Expand); + setOperationAction(ISD::ROTR, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTTZ, MVT::i32, Expand); + setOperationAction(ISD::CTLZ, MVT::i32, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); + + setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); + + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); + // Implement custom stack allocations setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom); // Implement custom stack save and restore From a4b7994c2b714bbe63e9b74f556ffcb3b9ba4a57 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:26 +0300 Subject: [PATCH 012/261] [Xtensa] Lower SHIFT PARTS and shift operations. Also lower SHL, SRA, SRL with register operands. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 129 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 17 ++- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 34 ++++- llvm/lib/Target/Xtensa/XtensaOperators.td | 16 +++ 4 files changed, 189 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index a8c24a7f9bf646..bbdd408a300a9c 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -133,6 +133,11 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::ADD, MVT::i64, Expand); setOperationAction(ISD::SUB, MVT::i64, Expand); + // Xtensa doesn't support s[hl,rl,ra]_parts + setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); + // Bit Manipulation setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i64, Expand); @@ -836,6 +841,83 @@ SDValue XtensaTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, return DAG.getMergeValues(Ops, DL); } +SDValue XtensaTargetLowering::LowerShiftLeftParts(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + MVT VT = MVT::i32; + + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + + SDValue SetShiftLeft = DAG.getNode(XtensaISD::SSL, DL, MVT::Glue, Shamt); + SDValue ShiftLeftHi = + DAG.getNode(XtensaISD::SRC, DL, VT, Hi, Lo, SetShiftLeft); + SDValue SetShiftLeft1 = DAG.getNode(XtensaISD::SSL, DL, MVT::Glue, Shamt); + SDValue ShiftLeftLo = DAG.getNode(XtensaISD::SHL, DL, VT, Lo, SetShiftLeft1); + SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, + DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, DAG.getConstant(0, DL, VT), + ShiftLeftLo); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, ShiftLeftHi); + + SDValue Ops[2] = {Lo, Hi}; + return DAG.getMergeValues(Ops, DL); +} + +SDValue XtensaTargetLowering::LowerShiftRightParts(SDValue Op, + SelectionDAG &DAG, + bool IsSRA) const { + SDLoc DL(Op); + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + MVT VT = MVT::i32; + + if (IsSRA) { + SDValue SetShiftRight1 = DAG.getNode(XtensaISD::SSR, DL, MVT::Glue, Shamt); + SDValue ShiftRightLo1 = + DAG.getNode(XtensaISD::SRC, DL, VT, Hi, Lo, SetShiftRight1); + + SDValue SetShiftRight2 = DAG.getNode(XtensaISD::SSR, DL, MVT::Glue, Shamt); + SDValue ShiftRightHi1 = + DAG.getNode(XtensaISD::SRA, DL, VT, Hi, SetShiftRight2); + + SDValue SetShiftRight3 = DAG.getNode(XtensaISD::SSR, DL, MVT::Glue, Shamt); + SDValue ShiftRightLo2 = + DAG.getNode(XtensaISD::SRA, DL, VT, Hi, SetShiftRight3); + + SDValue ShiftRightHi2 = + DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, DL, VT)); + + SDValue Cond = + DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, + DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi2, ShiftRightHi1); + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightLo2, ShiftRightLo1); + } else { + SDValue SetShiftRight1 = DAG.getNode(XtensaISD::SSR, DL, MVT::Glue, Shamt); + SDValue ShiftRightLo1 = + DAG.getNode(XtensaISD::SRC, DL, VT, Hi, Lo, SetShiftRight1); + + SDValue SetShiftRight2 = DAG.getNode(XtensaISD::SSR, DL, MVT::Glue, Shamt); + SDValue ShiftRightHi1 = + DAG.getNode(XtensaISD::SRL, DL, VT, Hi, SetShiftRight2); + + SDValue SetShiftRight3 = DAG.getNode(XtensaISD::SSR, DL, MVT::Glue, Shamt); + SDValue ShiftRightLo2 = + DAG.getNode(XtensaISD::SRL, DL, VT, Hi, SetShiftRight3); + + SDValue Cond = + DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, + DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, DAG.getConstant(0, DL, VT), + ShiftRightHi1); + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightLo2, ShiftRightLo1); + } + + SDValue Ops[2] = {Lo, Hi}; + return DAG.getMergeValues(Ops, DL); +} + SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -861,6 +943,12 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerSTACKRESTORE(Op, DAG); case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); + case ISD::SHL_PARTS: + return LowerShiftLeftParts(Op, DAG); + case ISD::SRA_PARTS: + return LowerShiftRightParts(Op, DAG, true); + case ISD::SRL_PARTS: + return LowerShiftRightParts(Op, DAG, false); default: llvm_unreachable("Unexpected node to lower"); } @@ -876,6 +964,12 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(PCREL_WRAPPER); OPCODE(SELECT); OPCODE(SELECT_CC); + OPCODE(SHL); + OPCODE(SRA); + OPCODE(SRL); + OPCODE(SRC); + OPCODE(SSL); + OPCODE(SSR); } return NULL; #undef OPCODE @@ -1004,9 +1098,44 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *MBB) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + switch (MI.getOpcode()) { case Xtensa::SELECT: return emitSelectCC(MI, MBB); + + case Xtensa::SLL_P: { + MachineOperand &R = MI.getOperand(0); + MachineOperand &S = MI.getOperand(1); + MachineOperand &SA = MI.getOperand(2); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SSL)).addReg(SA.getReg()); + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SLL), R.getReg()).addReg(S.getReg()); + MI.eraseFromParent(); + return MBB; + } + case Xtensa::SRA_P: { + MachineOperand &R = MI.getOperand(0); + MachineOperand &T = MI.getOperand(1); + MachineOperand &SA = MI.getOperand(2); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SSR)).addReg(SA.getReg()); + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRA), R.getReg()).addReg(T.getReg()); + MI.eraseFromParent(); + return MBB; + } + case Xtensa::SRL_P: { + MachineOperand &R = MI.getOperand(0); + MachineOperand &T = MI.getOperand(1); + MachineOperand &SA = MI.getOperand(2); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SSR)).addReg(SA.getReg()); + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRL), R.getReg()).addReg(T.getReg()); + MI.eraseFromParent(); + return MBB; + } + default: llvm_unreachable("Unexpected instr type to insert"); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index f8da0ab75913ad..00222e9bee3914 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -42,7 +42,15 @@ enum { // chosen over operand 1; it has the same form as BR_CCMASK. // Operand 3 is the flag operand. SELECT, - SELECT_CC + SELECT_CC, + + // Shift + SHL, + SRA, + SRL, + SRC, + SSL, + SSR }; } @@ -53,6 +61,10 @@ class XtensaTargetLowering : public TargetLowering { explicit XtensaTargetLowering(const TargetMachine &TM, const XtensaSubtarget &STI); + MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override { + return LHSTy.getSizeInBits() <= 32 ? MVT::i32 : MVT::i64; + } + EVT getSetCCResultType(const DataLayout &, LLVMContext &, EVT VT) const override { if (!VT.isVector()) @@ -104,6 +116,9 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; + SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 88771588d1b9a4..6f91d2fdc21b0c 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -105,33 +105,39 @@ def MOVGEZ : RRR_Inst<0x00, 0x03, 0x0B, (outs AR:$r), (ins AR:$s, AR:$t), let Uses = [SAR] in { def SLL : RRR_Inst<0x00, 0x01, 0x0A, (outs AR:$r), (ins AR:$s), - "sll\t$r, $s", []> { + "sll\t$r, $s", + [(set AR:$r, (Xtensa_shl AR:$s))]> { let t = 0x00; } def SRA : RRR_Inst<0x00, 0x01, 0x0B, (outs AR:$r), (ins AR:$t), - "sra\t$r, $t", []> { + "sra\t$r, $t", + [(set AR:$r, (Xtensa_sra AR:$t))]> { let s = 0x00; } def SRC : RRR_Inst<0x00, 0x01, 0x08, (outs AR:$r), (ins AR:$s, AR:$t), - "src\t$r, $s, $t", []>; + "src\t$r, $s, $t", + [(set AR:$r, (Xtensa_src AR:$s, AR:$t))]>; def SRL : RRR_Inst<0x00, 0x01, 0x09, (outs AR:$r), (ins AR:$t), - "srl\t$r, $t", []> { + "srl\t$r, $t", + [(set AR:$r, (Xtensa_srl AR:$t))]> { let s = 0x00; } } let Defs = [SAR] in { def SSL : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins AR:$s), - "ssl\t$s", []> { + "ssl\t$s", + [(Xtensa_ssl AR:$s)]> { let r = 0x01; let t = 0x00; } def SSR : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins AR:$s), - "ssr\t$s", []> { + "ssr\t$s", + [(Xtensa_ssr AR:$s)]> { let r = 0x00; let t = 0x00; } @@ -189,6 +195,22 @@ def SSAI : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins uimm5:$imm), let t{0} = imm{4}; } +// Shift Pseudo instructions: +// SSL/SSR + Shift combination +let usesCustomInserter = 1 in { + def SLL_P : Pseudo<(outs AR:$r), (ins AR:$s, AR:$sa), + "# SLL_P $r, $s, $sa", + [(set AR:$r, (shl AR:$s, AR:$sa))]>; + + def SRA_P : Pseudo<(outs AR:$r), (ins AR:$t, AR:$sa), + "# SRA_P $r, $t, $sa", + [(set AR:$r, (sra AR:$t, AR:$sa))]>; + + def SRL_P : Pseudo<(outs AR:$r), (ins AR:$t, AR:$sa), + "# SRL_P $r, $t, $sa", + [(set AR:$r, (srl AR:$t, AR:$sa))]>; +} + //===----------------------------------------------------------------------===// // Load and store instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index a85550c46531ed..3ed6b9791cf9f9 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -23,6 +23,15 @@ def SDT_XtensaSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, SDTCisSameAs<2, 3>, SDTCisVT<5, i32>]>; + +def SDT_XtensaSHL : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_XtensaSRA : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_XtensaSRL : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_XtensaSRC : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, + SDTCisVT<2, i32>]>; +def SDT_XtensaSSL : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; +def SDT_XtensaSSR : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; + //===----------------------------------------------------------------------===// // Node definitions //===----------------------------------------------------------------------===// @@ -45,3 +54,10 @@ def Xtensa_pcrel_wrapper: SDNode<"XtensaISD::PCREL_WRAPPER", SDT_XtensaWrapPtr, def Xtensa_select : SDNode<"XtensaISD::SELECT", SDTSelect>; def Xtensa_select_cc: SDNode<"XtensaISD::SELECT_CC", SDT_XtensaSelectCC, [SDNPInGlue]>; + +def Xtensa_shl: SDNode<"XtensaISD::SHL", SDT_XtensaSHL, [SDNPInGlue]>; +def Xtensa_sra: SDNode<"XtensaISD::SRA", SDT_XtensaSRA, [SDNPInGlue]>; +def Xtensa_srl: SDNode<"XtensaISD::SRL", SDT_XtensaSRL, [SDNPInGlue]>; +def Xtensa_src: SDNode<"XtensaISD::SRC", SDT_XtensaSRC, [SDNPInGlue]>; +def Xtensa_ssl: SDNode<"XtensaISD::SSL", SDT_XtensaSSL, [SDNPOutGlue]>; +def Xtensa_ssr: SDNode<"XtensaISD::SSR", SDT_XtensaSSR, [SDNPOutGlue]>; From 044c8ec3aa67d92838a142a3e95392ba05d30bd2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:27 +0300 Subject: [PATCH 013/261] [Xtensa] Implement load pseudo operations and patterns. Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 20 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 12 +++++++++++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 1 + 3 files changed, 33 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index bbdd408a300a9c..bf0bfccb8820dd 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -1099,6 +1099,8 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *MBB) const { const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + MachineFunction *MF = MBB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); DebugLoc DL = MI.getDebugLoc(); switch (MI.getOpcode()) { @@ -1136,6 +1138,24 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( return MBB; } + case Xtensa::L8I_P: { + MachineOperand &R = MI.getOperand(0); + MachineOperand &Op1 = MI.getOperand(1); + MachineOperand &Op2 = MI.getOperand(2); + + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::L8UI), R1).add(Op1).add(Op2); + + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SLLI), R2).addReg(R1).addImm(24); + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRAI), R.getReg()) + .addReg(R2) + .addImm(24); + MI.eraseFromParent(); + return MBB; + } default: llvm_unreachable("Unexpected instr type to insert"); } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 6f91d2fdc21b0c..a8251f5af559f6 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -284,6 +284,18 @@ let isCodeGenOnly = 1, mayLoad = 1 in { } } +// Xtensa missed L8I load operation, use pseudo operation +let usesCustomInserter = 1 in +def L8I_P: Pseudo<(outs AR:$t), (ins mem8:$addr), + "!L8I_P $t, $addr", + [(set AR:$t, (sextloadi8 + addr_ish1:$addr))]>; + +//extending loads +def : Pat<(i32 (extloadi1 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>; +def : Pat<(i32 (extloadi8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>; +def : Pat<(i32 (extloadi16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>; + //===----------------------------------------------------------------------===// // Conditional branch instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index 559443f07fbb87..dc77c614f97e10 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -107,6 +107,7 @@ bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II, bool Valid = false; switch (MI.getOpcode()) { + case Xtensa::L8I_P: case Xtensa::L8UI: case Xtensa::S8I: Valid = (Offset >= 0 && Offset <= 255); From 464a19074aff88ad9bf9e06e6c269bb42a38240c Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:27 +0300 Subject: [PATCH 014/261] [Xtensa] Support for variable arguments --- llvm/lib/Target/Xtensa/CMakeLists.txt | 1 + .../lib/Target/Xtensa/XtensaFrameLowering.cpp | 2 +- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 191 +++++++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 7 + llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 2 +- .../Xtensa/XtensaMachineFunctionInfo.cpp | 19 ++ .../Target/Xtensa/XtensaMachineFunctionInfo.h | 46 +++++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 2 +- .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 7 + llvm/lib/Target/Xtensa/XtensaTargetMachine.h | 3 + 10 files changed, 268 insertions(+), 12 deletions(-) create mode 100644 llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index d4300678a0434f..2208428f4c10c1 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -21,6 +21,7 @@ add_llvm_target(XtensaCodeGen XtensaInstrInfo.cpp XtensaISelDAGToDAG.cpp XtensaISelLowering.cpp + XtensaMachineFunctionInfo.cpp XtensaMCInstLower.cpp XtensaRegisterInfo.cpp XtensaSubtarget.cpp diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index e87f2809a51eef..53d180cc0e58d6 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -14,8 +14,8 @@ #include "XtensaFrameLowering.h" #include "XtensaInstrInfo.h" +#include "XtensaMachineFunctionInfo.h" #include "XtensaSubtarget.h" -#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index bf0bfccb8820dd..8565bb3f32d170 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -15,10 +15,10 @@ #include "XtensaISelLowering.h" #include "XtensaConstantPoolValue.h" +#include "XtensaMachineFunctionInfo.h" #include "XtensaSubtarget.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/CallingConvLower.h" -#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -32,6 +32,9 @@ using namespace llvm; #define DEBUG_TYPE "xtensa-lower" +static const MCPhysReg XtensaArgRegs[6] = {Xtensa::A2, Xtensa::A3, Xtensa::A4, + Xtensa::A5, Xtensa::A6, Xtensa::A7}; + // Return true if we must use long (in fact, indirect) function call. // It's simplified version, production implimentation must // resolve a functions in ROM (usually glibc functions) @@ -165,6 +168,14 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::STACKSAVE, MVT::Other, Custom); setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom); + // VASTART and VACOPY need to deal with the Xtensa-specific varargs + // structure, but VAEND is a no-op. + setOperationAction(ISD::VASTART, MVT::Other, Custom); + // we use special va_list structure so we have to customize this + setOperationAction(ISD::VAARG, MVT::Other, Expand); + setOperationAction(ISD::VACOPY, MVT::Other, Custom); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); } @@ -180,6 +191,11 @@ bool XtensaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, return false; } +unsigned XtensaTargetLowering::getVaListSizeInBits(const DataLayout &DL) const { + // 2 * sizeof(int*) + sizeof(int) + return 3 * 4; +} + //===----------------------------------------------------------------------===// // Calling conventions //===----------------------------------------------------------------------===// @@ -303,14 +319,14 @@ SDValue XtensaTargetLowering::LowerFormalArguments( SelectionDAG &DAG, SmallVectorImpl &InVals) const { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo &MFI = MF.getFrameInfo(); + XtensaFunctionInfo *XtensaFI = MF.getInfo(); + EVT PtrVT = getPointerTy(MF.getDataLayout()); + + XtensaFI->setVarArgsFrameIndex(0); // Used with vargs to acumulate store chains. std::vector OutChains; - if (IsVarArg) { - llvm_unreachable("Var arg not supported by FormalArguments Lowering"); - } - // Assign locations to all of the incoming arguments. SmallVector ArgLocs; CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, @@ -379,6 +395,66 @@ SDValue XtensaTargetLowering::LowerFormalArguments( } } + if (IsVarArg) { + ArrayRef ArgRegs = ArrayRef(XtensaArgRegs); + unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); + const TargetRegisterClass *RC = &Xtensa::ARRegClass; + MachineFrameInfo &MFI = MF.getFrameInfo(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + unsigned RegSize = 4; + MVT RegTy = MVT::getIntegerVT(RegSize * 8); + + XtensaFI->setVarArgsFirstGPR(Idx + 2); // 2 - number of a2 register + + XtensaFI->setVarArgsStackOffset(MFI.CreateFixedObject( + PtrVT.getSizeInBits() / 8, CCInfo.getStackSize(), true)); + + // Offset of the first variable argument from stack pointer, and size of + // the vararg save area. For now, the varargs save area is either zero or + // large enough to hold a0-a7. + int VaArgOffset, VarArgsSaveSize; + + // If all registers are allocated, then all varargs must be passed on the + // stack and we don't need to save any argregs. + if (ArgRegs.size() == Idx) { + VaArgOffset = CCInfo.getStackSize(); + VarArgsSaveSize = 0; + } else { + VarArgsSaveSize = RegSize * (ArgRegs.size() - Idx); + VaArgOffset = -VarArgsSaveSize; + } + + // Record the frame index of the first variable argument + // which is a value necessary to VASTART. + int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); + XtensaFI->setVarArgsFrameIndex(FI); + + // Copy the integer registers that may have been used for passing varargs + // to the vararg save area. + for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { + const unsigned Reg = RegInfo.createVirtualRegister(RC); + unsigned FrameReg = Subtarget.getRegisterInfo()->getFrameRegister(MF); + + // Argument passed in FrameReg we save in A8 (in emitPrologue), + // so load argument from A8 + if (ArgRegs[I] == FrameReg) { + RegInfo.addLiveIn(Xtensa::A8, Reg); + } else { + RegInfo.addLiveIn(ArgRegs[I], Reg); + } + + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); + FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); + SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, + MachinePointerInfo::getFixedStack(MF, FI)); + cast(Store.getNode()) + ->getMemOperand() + ->setValue((Value *)nullptr); + OutChains.push_back(Store); + } + } + // All stores are grouped in one node to allow the matching between // the size of Ins and InVals. This only happens when on varg functions if (!OutChains.empty()) { @@ -598,10 +674,6 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { - if (IsVarArg) { - report_fatal_error("VarArg not supported"); - } - MachineFunction &MF = DAG.getMachineFunction(); // Assign locations to each returned value. @@ -841,6 +913,103 @@ SDValue XtensaTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, return DAG.getMergeValues(Ops, DL); } +SDValue XtensaTargetLowering::LowerVASTART(SDValue Op, + SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + XtensaFunctionInfo *XtensaFI = MF.getInfo(); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + SDLoc DL(Op); + + SDValue Chain = Op.getOperand(0); + SDValue Addr = Op.getOperand(1); + + // typedef struct __va_list_tag { + // int32_t *__va_stk; /* Initialized to point to the position of the + // * first argument in memory offset to account for + // the + // * arguments passed in registers and to account for + // * the size of the argument registers not being + // 16-byte + // * aligned. E.G., there are 6 argument registers + // * of 4 bytes each, but we want the __va_ndx for the + // * first stack argument to have the maximal + // * alignment of 16 bytes, so we offset the __va_stk + // address by + // * 32 bytes so that __va_stk[32] references the + // first + // * argument on the stack. + // */ + // int32_t *__va_reg; /* Points to a stack-allocated region holding the + // * contents + // * of the incoming argument registers + // */ + // int32_t __va_ndx; /* Index initialized to the position of the first + // * unnamed (variable) argument. This same index is + // also + // * used to address the arguments passed in memory. + // */ + // } __va_list_tag[1]; + + SDValue ArgAR; + SDValue OverflowPtrAdvance; + SDValue StackOffsetFI = + DAG.getFrameIndex(XtensaFI->getVarArgsStackOffset(), PtrVT); + + if (XtensaFI->getVarArgsFirstGPR() < 8) { + ArgAR = + DAG.getConstant(XtensaFI->getVarArgsFirstGPR() * 4 - 8, DL, MVT::i32); + OverflowPtrAdvance = DAG.getConstant(32, DL, PtrVT); + } else { + OverflowPtrAdvance = DAG.getNode(ISD::AND, DL, PtrVT, StackOffsetFI, + DAG.getConstant(0xf, DL, PtrVT)); + OverflowPtrAdvance = DAG.getNode(ISD::ADD, DL, PtrVT, OverflowPtrAdvance, + DAG.getConstant(32, DL, PtrVT)); + ArgAR = OverflowPtrAdvance; + } + + SDValue FR = DAG.getFrameIndex(XtensaFI->getVarArgsFrameIndex(), PtrVT); + + uint64_t FrameOffset = PtrVT.getSizeInBits() / 8; + SDValue ConstFrameOffset1 = DAG.getConstant(FrameOffset, DL, PtrVT); + SDValue ConstFrameOffset2 = DAG.getConstant(FrameOffset * 2, DL, PtrVT); + + const Value *SV = cast(Op.getOperand(2))->getValue(); + + // Store first word : arguments given in stack (__va_stk) + // Advance Argument Overflow pointer down, lest it will point to start + // after register argument va_arg finished + SDValue StackOffsetFICorr = + DAG.getNode(ISD::SUB, DL, PtrVT, StackOffsetFI, OverflowPtrAdvance); + SDValue firstStore = + DAG.getStore(Chain, DL, StackOffsetFICorr, Addr, MachinePointerInfo(SV)); + + uint64_t nextOffset = FrameOffset; + SDValue nextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Addr, ConstFrameOffset1); + + // Store second word : arguments given on registers (__va_reg) + SDValue FRAdvance = + DAG.getConstant(XtensaFI->getVarArgsFirstGPR() * 4 - 8, DL, PtrVT); + SDValue FRDecr = DAG.getNode(ISD::SUB, DL, PtrVT, FR, FRAdvance); + SDValue secondStore = DAG.getStore(firstStore, DL, FRDecr, nextPtr, + MachinePointerInfo(SV, nextOffset)); + nextOffset += FrameOffset; + nextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Addr, ConstFrameOffset2); + + // Store first word : number of int regs (__va_ndx) + return DAG.getStore(secondStore, DL, ArgAR, nextPtr, + MachinePointerInfo(SV, nextOffset)); +} + +SDValue XtensaTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { + // We have to copy the entire va_list struct: + // 2*sizeof(int*) + sizeof(int) = 12 Byte + unsigned VAListSize = 12; + return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2), + DAG.getConstant(VAListSize, SDLoc(Op), MVT::i32), Align(8), + false, true, false, MachinePointerInfo(), + MachinePointerInfo()); +} + SDValue XtensaTargetLowering::LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); @@ -943,6 +1112,10 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerSTACKRESTORE(Op, DAG); case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); + case ISD::VASTART: + return LowerVASTART(Op, DAG); + case ISD::VACOPY: + return LowerVACOPY(Op, DAG); case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); case ISD::SRA_PARTS: diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 00222e9bee3914..e56cab673c59ff 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -76,6 +76,10 @@ class XtensaTargetLowering : public TargetLowering { bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; const char *getTargetNodeName(unsigned Opcode) const override; + + /// Returns the size of the platform's va_list object. + unsigned getVaListSizeInBits(const DataLayout &DL) const override; + SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, @@ -112,6 +116,9 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 30134c9612fdb6..1bfd18b7ef3eab 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -13,9 +13,9 @@ //===----------------------------------------------------------------------===// #include "XtensaInstrInfo.h" +#include "XtensaMachineFunctionInfo.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" diff --git a/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.cpp b/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.cpp new file mode 100644 index 00000000000000..1a285b2aa53101 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.cpp @@ -0,0 +1,19 @@ +//===- XtensaMachineFunctionInfo.cpp - Private data used for Xtensa -------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "XtensaMachineFunctionInfo.h" +//#include "MCTargetDesc/XtensaBaseInfo.h" +#include "XtensaInstrInfo.h" +#include "XtensaSubtarget.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/IR/Function.h" + +using namespace llvm; diff --git a/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h b/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h new file mode 100644 index 00000000000000..ebc99f912ba0e7 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h @@ -0,0 +1,46 @@ +//==- XtensaMachineFunctionInfo.h - Xtensa machine function info --*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file declares Xtensa-specific per-machine-function information. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAMACHINEFUNCTIONINFO_H +#define LLVM_LIB_TARGET_XTENSA_XTENSAMACHINEFUNCTIONINFO_H + +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/Target/TargetMachine.h" + +namespace llvm { + +class XtensaFunctionInfo : public MachineFunctionInfo { + unsigned VarArgsFirstGPR; + int VarArgsStackOffset; + unsigned VarArgsFrameIndex; + +public: + explicit XtensaFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) + : VarArgsFirstGPR(0), VarArgsStackOffset(0), VarArgsFrameIndex(0) {} + + unsigned getVarArgsFirstGPR() const { return VarArgsFirstGPR; } + void setVarArgsFirstGPR(unsigned GPR) { VarArgsFirstGPR = GPR; } + + int getVarArgsStackOffset() const { return VarArgsStackOffset; } + void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; } + + // Get and set the frame index of the first stack vararg. + unsigned getVarArgsFrameIndex() const { return VarArgsFrameIndex; } + void setVarArgsFrameIndex(unsigned FI) { VarArgsFrameIndex = FI; } +}; + +} // namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAMACHINEFUNCTIONINFO_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index dc77c614f97e10..011bd55c7de40e 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -14,8 +14,8 @@ #include "XtensaRegisterInfo.h" #include "XtensaInstrInfo.h" +#include "XtensaMachineFunctionInfo.h" #include "XtensaSubtarget.h" -#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/Debug.h" diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 5ee24c701f074e..c9a18c3728e78d 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -12,6 +12,7 @@ // //===----------------------------------------------------------------------===// +#include "XtensaMachineFunctionInfo.h" #include "XtensaTargetMachine.h" #include "TargetInfo/XtensaTargetInfo.h" #include "llvm/CodeGen/Passes.h" @@ -70,6 +71,12 @@ XtensaTargetMachine::getSubtargetImpl(const Function &F) const { return &Subtarget; } +MachineFunctionInfo *XtensaTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return XtensaFunctionInfo::create(Allocator, F, STI); +} + namespace { /// Xtensa Code Generator Pass Configuration Options. class XtensaPassConfig : public TargetPassConfig { diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h index be0886f2a9b0fe..eea7c7b5be7c66 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h @@ -43,6 +43,9 @@ class XtensaTargetMachine : public LLVMTargetMachine { TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; protected: XtensaSubtarget Subtarget; From c3327768db3060ecf6e040e8da7078c097ec05d1 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:28 +0300 Subject: [PATCH 015/261] [Xtensa] Implement lowering BR_JT operation --- llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 11 ++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 36 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 3 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 6 ++++ llvm/lib/Target/Xtensa/XtensaOperators.td | 4 +++ 5 files changed, 60 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index 63a0aa1633378e..fed1777b118e6b 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -22,6 +22,7 @@ #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInstBuilder.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" @@ -44,6 +45,16 @@ getModifierVariantKind(XtensaCP::XtensaCPModifier Modifier) { void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) { XtensaMCInstLower Lower(MF->getContext(), *this); MCInst LoweredMI; + unsigned Opc = MI->getOpcode(); + + switch (Opc) { + case Xtensa::BR_JT: { + EmitToStreamer( + *OutStreamer, + MCInstBuilder(Xtensa::JX).addReg(MI->getOperand(0).getReg())); + return; + } + } Lower.lower(MI, LoweredMI); EmitToStreamer(*OutStreamer, LoweredMI); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 8565bb3f32d170..1d502728217a5f 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -95,6 +95,10 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::SETCC, MVT::i32, Custom); // folds into brcond setOperationAction(ISD::SETCC, MVT::i64, Expand); + + // Expand jump table branches as address arithmetic followed by an + // indirect jump. + setOperationAction(ISD::BR_JT, MVT::Other, Custom); // make BRCOND legal, its actually only legal for a subset of conds setOperationAction(ISD::BRCOND, MVT::Other, Legal); @@ -845,6 +849,35 @@ SDValue XtensaTargetLowering::LowerBlockAddress(BlockAddressSDNode *Node, return CPWrap; } +SDValue XtensaTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); + SDValue Table = Op.getOperand(1); + SDValue Index = Op.getOperand(2); + SDLoc DL(Op); + JumpTableSDNode *JT = cast(Table); + MachineFunction &MF = DAG.getMachineFunction(); + const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); + + SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); + + const DataLayout &TD = DAG.getDataLayout(); + EVT PTy = getPointerTy(TD); + + unsigned EntrySize = MJTI->getEntrySize(TD); + + Index = DAG.getNode(ISD::MUL, DL, Index.getValueType(), Index, + DAG.getConstant(EntrySize, DL, Index.getValueType())); + SDValue Addr = DAG.getNode(ISD::ADD, DL, Index.getValueType(), Index, Table); + + EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); + SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, + MachinePointerInfo::getJumpTable(MF), MemVT); + Addr = LD; + + return DAG.getNode(XtensaISD::BR_JT, DL, MVT::Other, LD.getValue(1), Addr, + TargetJT); +} + SDValue XtensaTargetLowering::LowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const { SDLoc DL(JT); @@ -1090,6 +1123,8 @@ SDValue XtensaTargetLowering::LowerShiftRightParts(SDValue Op, SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { + case ISD::BR_JT: + return LowerBR_JT(Op, DAG); case ISD::Constant: return LowerImmediate(Op, DAG); case ISD::ConstantFP: @@ -1137,6 +1172,7 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(PCREL_WRAPPER); OPCODE(SELECT); OPCODE(SELECT_CC); + OPCODE(BR_JT); OPCODE(SHL); OPCODE(SRA); OPCODE(SRL); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index e56cab673c59ff..99febf0d453be8 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -25,6 +25,8 @@ namespace XtensaISD { enum { FIRST_NUMBER = ISD::BUILTIN_OP_END, + BR_JT, + // Calls a function. Operand 0 is the chain operand and operand 1 // is the target address. The arguments start at operand 2. // There is an optional glue operand at the end. @@ -106,6 +108,7 @@ class XtensaTargetLowering : public TargetLowering { private: const XtensaSubtarget &Subtarget; + SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const; SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index a8251f5af559f6..d21100181cf0b6 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -532,6 +532,12 @@ def : Pat<(Xtensa_call (i32 texternalsym:$dst)), def : Pat<(Xtensa_call AR:$dst), (CALLX0 AR:$dst)>; +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1, Size = 3 in { + def BR_JT: Pseudo<(outs), (ins AR:$s, i32imm:$jt), + "!br_jt_p, $s, $jt", + [(Xtensa_brjt AR:$s, tjumptable:$jt)]>; +} + //===----------------------------------------------------------------------===// // Mem barrier instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index 3ed6b9791cf9f9..ca8ec55c56709c 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -23,6 +23,8 @@ def SDT_XtensaSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, SDTCisSameAs<2, 3>, SDTCisVT<5, i32>]>; +def SDT_XtensaBrJT : SDTypeProfile<0, 2, + [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; def SDT_XtensaSHL : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; def SDT_XtensaSRA : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; @@ -61,3 +63,5 @@ def Xtensa_srl: SDNode<"XtensaISD::SRL", SDT_XtensaSRL, [SDNPInGlue]>; def Xtensa_src: SDNode<"XtensaISD::SRC", SDT_XtensaSRC, [SDNPInGlue]>; def Xtensa_ssl: SDNode<"XtensaISD::SSL", SDT_XtensaSSL, [SDNPOutGlue]>; def Xtensa_ssr: SDNode<"XtensaISD::SSR", SDT_XtensaSSR, [SDNPOutGlue]>; + +def Xtensa_brjt: SDNode<"XtensaISD::BR_JT", SDT_XtensaBrJT, [SDNPHasChain]>; From 46904313618329a9170fba691676877b2f41d3f4 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:28 +0300 Subject: [PATCH 016/261] [Xtensa] Support for address intrinsics. Add support for llvm.{frameaddress,returnaddress} intrinsics. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 41 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 2 + 2 files changed, 43 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 1d502728217a5f..3d0a008d5ad13c 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -768,6 +768,26 @@ SDValue XtensaTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { TargetCC); } +SDValue XtensaTargetLowering::LowerRETURNADDR(SDValue Op, + SelectionDAG &DAG) const { + // check the depth + // TODO: xtensa-gcc can handle this, by navigating through the stack, we + // should be able to do this too + assert((cast(Op.getOperand(0))->getZExtValue() == 0) && + "Return address can be determined only for current frame."); + + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MVT VT = Op.getSimpleValueType(); + unsigned RA = Xtensa::A0; + MFI.setReturnAddressIsTaken(true); + + // Return RA, which contains the return address. Mark it an implicit + // live-in. + unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); + return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); +} + SDValue XtensaTargetLowering::LowerImmediate(SDValue Op, SelectionDAG &DAG) const { const ConstantSDNode *CN = cast(Op); @@ -921,6 +941,23 @@ SDValue XtensaTargetLowering::LowerSTACKRESTORE(SDValue Op, return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op), sp, Op.getOperand(1)); } +SDValue XtensaTargetLowering::LowerFRAMEADDR(SDValue Op, + SelectionDAG &DAG) const { + // check the depth + assert((cast(Op.getOperand(0))->getZExtValue() == 0) && + "Frame address can only be determined for current frame."); + + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MFI.setFrameAddressIsTaken(true); + EVT VT = Op.getValueType(); + SDLoc DL(Op); + + unsigned FrameReg = Subtarget.getRegisterInfo()->getFrameRegister(MF); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT); + return FrameAddr; +} + SDValue XtensaTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { SDValue Chain = Op.getOperand(0); // Legalize the chain. @@ -1129,6 +1166,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerImmediate(Op, DAG); case ISD::ConstantFP: return LowerImmediateFP(Op, DAG); + case ISD::RETURNADDR: + return LowerRETURNADDR(Op, DAG); case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::SELECT_CC: @@ -1145,6 +1184,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerSTACKSAVE(Op, DAG); case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG); + case ISD::FRAMEADDR: + return LowerFRAMEADDR(Op, DAG); case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); case ISD::VASTART: diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 99febf0d453be8..af8cc64b730a7d 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -118,6 +118,7 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; @@ -125,6 +126,7 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; From 0c09ff543e7a769beaaf9594760178f1b7f3e432 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:28 +0300 Subject: [PATCH 017/261] [Xtensa] Add basic support for inline asm constraints --- .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 9 +++ .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 3 + llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 55 ++++++++++++++ llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 6 ++ llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 27 +++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 76 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 22 ++++++ 7 files changed, 198 insertions(+) diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index fe1dc0e2e483e7..10becc9e8c83b3 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -27,6 +27,15 @@ using namespace llvm; #include "XtensaGenAsmWriter.inc" +void XtensaInstPrinter::printAddress(unsigned Base, int64_t Disp, + raw_ostream &O) { + O << Disp; + if (Base) { + O << '('; + O << getRegisterName(Base) << ')'; + } +} + static void printExpr(const MCExpr *Expr, raw_ostream &OS) { int Offset = 0; const MCSymbolRefExpr *SRE; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index 46a35ae6f4e3fa..34d03569b9bce6 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -35,6 +35,9 @@ class XtensaInstPrinter : public MCInstPrinter { // Print the given operand. static void printOperand(const MCOperand &MO, raw_ostream &O); + // Print an address + static void printAddress(unsigned Base, int64_t Disp, raw_ostream &O); + // Override MCInstPrinter. void printRegName(raw_ostream &O, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index fed1777b118e6b..be2b943d4ff98a 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -14,6 +14,7 @@ //===----------------------------------------------------------------------===// #include "XtensaAsmPrinter.h" +#include "MCTargetDesc/XtensaInstPrinter.h" #include "XtensaConstantPoolValue.h" #include "XtensaMCInstLower.h" #include "TargetInfo/XtensaTargetInfo.h" @@ -217,6 +218,60 @@ void XtensaAsmPrinter::emitMachineConstantPoolValue( } } +void XtensaAsmPrinter::printOperand(const MachineInstr *MI, int OpNo, + raw_ostream &O) { + const MachineOperand &MO = MI->getOperand(OpNo); + + switch (MO.getType()) { + case MachineOperand::MO_Register: + case MachineOperand::MO_Immediate: { + XtensaMCInstLower Lower(MF->getContext(), *this); + MCOperand MC(Lower.lowerOperand(MI->getOperand(OpNo))); + XtensaInstPrinter::printOperand(MC, O); + break; + } + case MachineOperand::MO_GlobalAddress: + O << *getSymbol(MO.getGlobal()); + break; + default: + llvm_unreachable(""); + } + + if (MO.getTargetFlags()) { + O << ")"; + } +} + +bool XtensaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, + const char *ExtraCode, raw_ostream &O) { + if (ExtraCode && *ExtraCode == 'n') { + if (!MI->getOperand(OpNo).isImm()) + return true; + O << -int64_t(MI->getOperand(OpNo).getImm()); + } else { + printOperand(MI, OpNo, O); + } + return false; +} + +bool XtensaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, + unsigned OpNo, + const char *ExtraCode, + raw_ostream &OS) { + XtensaInstPrinter::printAddress(MI->getOperand(OpNo).getReg(), + MI->getOperand(OpNo + 1).getImm(), OS); + return false; +} + +void XtensaAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, + raw_ostream &OS) { + OS << '%' + << XtensaInstPrinter::getRegisterName(MI->getOperand(opNum).getReg()); + OS << "("; + OS << MI->getOperand(opNum + 1).getImm(); + OS << ")"; +} + // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmPrinter() { RegisterAsmPrinter A(getTheXtensaTarget()); diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h index 0ba80bc18c1c2d..50feaa0fcd2c0d 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h @@ -38,6 +38,12 @@ class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter { void emitInstruction(const MachineInstr *MI) override; void emitConstantPool() override; void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, + const char *ExtraCode, raw_ostream &O) override; + bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, + const char *ExtraCode, raw_ostream &OS) override; + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index c16bf8b932c8ff..5d27c0dadff8e7 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -41,6 +41,10 @@ class XtensaDAGToDAGISel : public SelectionDAGISel { // Override SelectionDAGISel. void Select(SDNode *Node) override; + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) override; + bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset, int Scale) { EVT ValTy = Addr.getValueType(); @@ -139,3 +143,26 @@ void XtensaDAGToDAGISel::Select(SDNode *Node) { SelectCode(Node); } + +bool XtensaDAGToDAGISel::SelectInlineAsmMemoryOperand( + const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) { + switch (ConstraintID) { + default: + llvm_unreachable("Unexpected asm memory constraint"); + case InlineAsm::ConstraintCode::m: { + SDValue Base, Offset; + // TODO + selectMemRegAddr(Op, Base, Offset, 4); + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + case InlineAsm::ConstraintCode::i: + case InlineAsm::ConstraintCode::R: + case InlineAsm::ConstraintCode::ZC: + OutOps.push_back(Op); + return false; + } + return false; +} diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 3d0a008d5ad13c..cd750be6fbf90e 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -200,6 +200,82 @@ unsigned XtensaTargetLowering::getVaListSizeInBits(const DataLayout &DL) const { return 3 * 4; } +//===----------------------------------------------------------------------===// +// Inline asm support +//===----------------------------------------------------------------------===// +TargetLowering::ConstraintType +XtensaTargetLowering::getConstraintType(StringRef Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + case 'a': + case 'd': + case 'r': + return C_RegisterClass; + + default: + break; + } + } + return TargetLowering::getConstraintType(Constraint); +} + +TargetLowering::ConstraintWeight +XtensaTargetLowering::getSingleConstraintMatchWeight( + AsmOperandInfo &info, const char *constraint) const { + ConstraintWeight weight = CW_Invalid; + Value *CallOperandVal = info.CallOperandVal; + // If we don't have a value, we can't do a match, + // but allow it at the lowest weight. + if (CallOperandVal == NULL) + return CW_Default; + + // Look at the constraint type. + switch (*constraint) { + default: + weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); + break; + + case 'a': + case 'd': + case 'r': + if (CallOperandVal->getType()->isIntegerTy()) + weight = CW_Register; + break; + } + return weight; +} + +std::pair +XtensaTargetLowering::getRegForInlineAsmConstraint( + const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { + if (Constraint.size() == 1) { + // GCC Constraint Letters + switch (Constraint[0]) { + default: + break; + case 'a': // Address register + case 'd': // Data register (equivalent to 'r') + case 'r': // General-purpose register + return std::make_pair(0U, &Xtensa::ARRegClass); + } + } + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); +} + +/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops +/// vector. If it is invalid, don't add anything to Ops. +void XtensaTargetLowering::LowerAsmOperandForConstraint( + SDValue Op, StringRef Constraint, std::vector &Ops, + SelectionDAG &DAG) const { + SDLoc DL(Op); + + // Only support length 1 constraints for now. + if (Constraint.size() > 1) + return; + + TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); +} + //===----------------------------------------------------------------------===// // Calling conventions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index af8cc64b730a7d..e9dd80709bb1cb 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -82,6 +82,19 @@ class XtensaTargetLowering : public TargetLowering { /// Returns the size of the platform's va_list object. unsigned getVaListSizeInBits(const DataLayout &DL) const override; + std::pair + getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, + StringRef Constraint, MVT VT) const override; + TargetLowering::ConstraintType + getConstraintType(StringRef Constraint) const override; + TargetLowering::ConstraintWeight + getSingleConstraintMatchWeight(AsmOperandInfo &info, + const char *constraint) const override; + + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, + std::vector &Ops, + SelectionDAG &DAG) const override; + SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, @@ -138,6 +151,15 @@ class XtensaTargetLowering : public TargetLowering { // Implement EmitInstrWithCustomInserter for individual operation types. MachineBasicBlock *emitSelectCC(MachineInstr &MI, MachineBasicBlock *BB) const; + + InlineAsm::ConstraintCode + getInlineAsmMemConstraint(StringRef ConstraintCode) const override { + if (ConstraintCode == "R") + return InlineAsm::ConstraintCode::R; + else if (ConstraintCode == "ZC") + return InlineAsm::ConstraintCode::ZC; + return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); + } }; } // end namespace llvm From db75848043123cc4d9a2f7084b940ee785eee526 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:29 +0300 Subject: [PATCH 018/261] [Xtensa] Implement volatile load/store. Implement volatile load/store from/to volatile memory location. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 20 ++++++++++++++++++- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 4 ++-- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index cd750be6fbf90e..fab06277d59c49 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -95,7 +95,7 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::SETCC, MVT::i32, Custom); // folds into brcond setOperationAction(ISD::SETCC, MVT::i64, Expand); - + // Expand jump table branches as address arithmetic followed by an // indirect jump. setOperationAction(ISD::BR_JT, MVT::Other, Custom); @@ -1472,6 +1472,11 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( const TargetRegisterClass *RC = getRegClassFor(MVT::i32); unsigned R1 = MRI.createVirtualRegister(RC); + const MachineMemOperand &MMO = **MI.memoperands_begin(); + if (MMO.isVolatile()) { + BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW)); + } + BuildMI(*MBB, MI, DL, TII.get(Xtensa::L8UI), R1).add(Op1).add(Op2); unsigned R2 = MRI.createVirtualRegister(RC); @@ -1482,6 +1487,19 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MI.eraseFromParent(); return MBB; } + case Xtensa::S8I: + case Xtensa::S16I: + case Xtensa::S32I: + case Xtensa::L8UI: + case Xtensa::L16SI: + case Xtensa::L16UI: + case Xtensa::L32I: { + const MachineMemOperand &MMO = **MI.memoperands_begin(); + if (MMO.isVolatile()) { + BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW)); + } + return MBB; + } default: llvm_unreachable("Unexpected instr type to insert"); } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index d21100181cf0b6..316c660dfffb2a 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -216,7 +216,7 @@ let usesCustomInserter = 1 in { //===----------------------------------------------------------------------===// // Load instructions -let mayLoad = 1 in { +let mayLoad = 1, usesCustomInserter = 1 in { class Load_RRI8 oper, string instrAsm, SDPatternOperator opNode, ComplexPattern addrOp, Operand memOp> @@ -237,7 +237,7 @@ def L16UI : Load_RRI8<0x01, "l16ui", zextloadi16, addr_ish2, mem16>; def L32I : Load_RRI8<0x02, "l32i", load, addr_ish4, mem32>; // Store instructions -let mayStore = 1 in { +let mayStore = 1, usesCustomInserter = 1 in { class Store_II8 oper, string instrAsm, SDPatternOperator opNode, ComplexPattern addrOp, Operand memOp> : RRI8_Inst<0x02, (outs), (ins AR:$t, memOp:$addr), From 57ad6f63ea099f263da2948762f0f99e9a431cb1 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:29 +0300 Subject: [PATCH 019/261] [Xtensa] Implement branch analysis --- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 305 ++++++++++++++++++++- llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 27 ++ 2 files changed, 330 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 1bfd18b7ef3eab..ded4df096d94ce 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -45,7 +45,8 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI) { } XtensaInstrInfo::XtensaInstrInfo(XtensaSubtarget &sti) - : XtensaGenInstrInfo(Xtensa::ADJCALLSTACKDOWN, Xtensa::ADJCALLSTACKUP), RI(sti), STI(sti) {} + : XtensaGenInstrInfo(Xtensa::ADJCALLSTACKDOWN, Xtensa::ADJCALLSTACKUP), + RI(sti), STI(sti) {} /// Adjust SP by Amount bytes. void XtensaInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, @@ -72,7 +73,9 @@ void XtensaInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, .addReg(Reg1, RegState::Kill); } - BuildMI(MBB, I, DL, get(Xtensa::OR), SP).addReg(Reg, RegState::Kill).addReg(Reg, RegState::Kill); + BuildMI(MBB, I, DL, get(Xtensa::OR), SP) + .addReg(Reg, RegState::Kill) + .addReg(Reg, RegState::Kill); } void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB, @@ -158,3 +161,301 @@ void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB, llvm_unreachable("Unsupported load immediate value"); } } + +bool XtensaInstrInfo::reverseBranchCondition( + SmallVectorImpl &Cond) const { + assert(Cond.size() <= 4 && "Invalid branch condition!"); + + switch (Cond[0].getImm()) { + case Xtensa::BEQ: + Cond[0].setImm(Xtensa::BNE); + return false; + case Xtensa::BNE: + Cond[0].setImm(Xtensa::BEQ); + return false; + case Xtensa::BLT: + Cond[0].setImm(Xtensa::BGE); + return false; + case Xtensa::BGE: + Cond[0].setImm(Xtensa::BLT); + return false; + case Xtensa::BLTU: + Cond[0].setImm(Xtensa::BGEU); + return false; + case Xtensa::BGEU: + Cond[0].setImm(Xtensa::BLTU); + return false; + + case Xtensa::BEQI: + Cond[0].setImm(Xtensa::BNEI); + return false; + case Xtensa::BNEI: + Cond[0].setImm(Xtensa::BEQI); + return false; + case Xtensa::BGEI: + Cond[0].setImm(Xtensa::BLTI); + return false; + case Xtensa::BLTI: + Cond[0].setImm(Xtensa::BGEI); + return false; + case Xtensa::BGEUI: + Cond[0].setImm(Xtensa::BLTUI); + return false; + case Xtensa::BLTUI: + Cond[0].setImm(Xtensa::BGEUI); + return false; + + case Xtensa::BEQZ: + Cond[0].setImm(Xtensa::BNEZ); + return false; + case Xtensa::BNEZ: + Cond[0].setImm(Xtensa::BEQZ); + return false; + case Xtensa::BLTZ: + Cond[0].setImm(Xtensa::BGEZ); + return false; + case Xtensa::BGEZ: + Cond[0].setImm(Xtensa::BLTZ); + return false; + + default: + llvm_unreachable("Invalid branch condition!"); + } +} + +bool XtensaInstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify = false) const { + // Most of the code and comments here are boilerplate. + + // Start from the bottom of the block and work up, examining the + // terminator instructions. + MachineBasicBlock::iterator I = MBB.end(); + while (I != MBB.begin()) { + --I; + if (I->isDebugValue()) + continue; + + // Working from the bottom, when we see a non-terminator instruction, we're + // done. + if (!isUnpredicatedTerminator(*I)) + break; + + // A terminator that isn't a branch can't easily be handled by this + // analysis. + SmallVector ThisCond; + ThisCond.push_back(MachineOperand::CreateImm(0)); + const MachineOperand *ThisTarget; + if (!isBranch(I, ThisCond, ThisTarget)) + return true; + + // Can't handle indirect branches. + if (!ThisTarget->isMBB()) + return true; + + if (ThisCond[0].getImm() == Xtensa::J) { + // Handle unconditional branches. + if (!AllowModify) { + TBB = ThisTarget->getMBB(); + continue; + } + + // If the block has any instructions after a JMP, delete them. + while (std::next(I) != MBB.end()) + std::next(I)->eraseFromParent(); + + Cond.clear(); + FBB = 0; + + // TBB is used to indicate the unconditinal destination. + TBB = ThisTarget->getMBB(); + continue; + } + + // Working from the bottom, handle the first conditional branch. + if (Cond.empty()) { + // FIXME: add X86-style branch swap + FBB = TBB; + TBB = ThisTarget->getMBB(); + Cond.push_back(MachineOperand::CreateImm(ThisCond[0].getImm())); + + // push remaining operands + for (unsigned int i = 0; i < (I->getNumExplicitOperands() - 1); i++) + Cond.push_back(I->getOperand(i)); + + continue; + } + + // Handle subsequent conditional branches. + assert(Cond.size() <= 4); + assert(TBB); + + // Only handle the case where all conditional branches branch to the same + // destination. + if (TBB != ThisTarget->getMBB()) + return true; + + // If the conditions are the same, we can leave them alone. + unsigned OldCond = Cond[0].getImm(); + if (OldCond == ThisCond[0].getImm()) + continue; + } + + return false; +} + +unsigned XtensaInstrInfo::removeBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + // Most of the code and comments here are boilerplate. + MachineBasicBlock::iterator I = MBB.end(); + unsigned Count = 0; + if (BytesRemoved) + *BytesRemoved = 0; + + while (I != MBB.begin()) { + --I; + SmallVector Cond; + Cond.push_back(MachineOperand::CreateImm(0)); + const MachineOperand *Target; + if (!isBranch(I, Cond, Target)) + break; + if (!Target->isMBB()) + break; + // Remove the branch. + if (BytesRemoved) + *BytesRemoved += getInstSizeInBytes(*I); + I->eraseFromParent(); + I = MBB.end(); + ++Count; + } + return Count; +} + +unsigned XtensaInstrInfo::insertBranch( + MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, + ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + unsigned Count = 0; + if (BytesAdded) + *BytesAdded = 0; + if (FBB) { + // Need to build two branches then + // one to branch to TBB on Cond + // and a second one immediately after to unconditionally jump to FBB + Count = InsertBranchAtInst(MBB, MBB.end(), TBB, Cond, DL, BytesAdded); + auto &MI = *BuildMI(&MBB, DL, get(Xtensa::J)).addMBB(FBB); + Count++; + if (BytesAdded) + *BytesAdded += getInstSizeInBytes(MI); + return Count; + } + // This function inserts the branch at the end of the MBB + Count += InsertBranchAtInst(MBB, MBB.end(), TBB, Cond, DL, BytesAdded); + return Count; +} + +unsigned XtensaInstrInfo::InsertBranchAtInst(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + MachineBasicBlock *TBB, + ArrayRef Cond, + const DebugLoc &DL, + int *BytesAdded) const { + // Shouldn't be a fall through. + assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert(Cond.size() <= 4 && + "Xtensa branch conditions have less than four components!"); + + if (Cond.empty() || (Cond[0].getImm() == Xtensa::J)) { + // Unconditional branch + MachineInstr *MI = BuildMI(MBB, I, DL, get(Xtensa::J)).addMBB(TBB); + if (BytesAdded && MI) + *BytesAdded += getInstSizeInBytes(*MI); + return 1; + } + + unsigned Count = 0; + unsigned BR_C = Cond[0].getImm(); + MachineInstr *MI = nullptr; + switch (BR_C) { + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + MI = BuildMI(MBB, I, DL, get(BR_C)) + .addReg(Cond[1].getReg()) + .addReg(Cond[2].getReg()) + .addMBB(TBB); + break; + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + MI = BuildMI(MBB, I, DL, get(BR_C)) + .addReg(Cond[1].getReg()) + .addImm(Cond[2].getImm()) + .addMBB(TBB); + break; + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + MI = BuildMI(MBB, I, DL, get(BR_C)).addReg(Cond[1].getReg()).addMBB(TBB); + break; + default: + llvm_unreachable("Invalid branch type!"); + } + if (BytesAdded && MI) + *BytesAdded += getInstSizeInBytes(*MI); + ++Count; + return Count; +} + +bool XtensaInstrInfo::isBranch(const MachineBasicBlock::iterator &MI, + SmallVectorImpl &Cond, + const MachineOperand *&Target) const { + unsigned OpCode = MI->getOpcode(); + switch (OpCode) { + case Xtensa::J: + case Xtensa::JX: + case Xtensa::BR_JT: + Cond[0].setImm(OpCode); + Target = &MI->getOperand(0); + return true; + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + Cond[0].setImm(OpCode); + Target = &MI->getOperand(2); + return true; + + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + Cond[0].setImm(OpCode); + Target = &MI->getOperand(2); + return true; + + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + Cond[0].setImm(OpCode); + Target = &MI->getOperand(1); + return true; + + default: + assert(!MI->getDesc().isBranch() && "Unknown branch opcode"); + return false; + } +} diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h index ddd5392d7ce64b..09c40487dd3889 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h @@ -64,6 +64,33 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { // physical register Reg. void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned *Reg, int64_t Value) const; + bool + reverseBranchCondition(SmallVectorImpl &Cond) const override; + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const override; + unsigned removeBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; + unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + MachineBasicBlock *FBB, ArrayRef Cond, + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; + + unsigned InsertBranchAtInst(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + MachineBasicBlock *TBB, + ArrayRef Cond, const DebugLoc &DL, + int *BytesAdded) const; + + // Return true if MI is a conditional or unconditional branch. + // When returning true, set Cond to the mask of condition-code + // values on which the instruction will branch, and set Target + // to the operand that contains the branch target. This target + // can be a register or a basic block. + bool isBranch(const MachineBasicBlock::iterator &MI, + SmallVectorImpl &Cond, + const MachineOperand *&Target) const; }; } // end namespace llvm From 57d18b002fc94df9243e1e96ae7ebb229f3a2179 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:30 +0300 Subject: [PATCH 020/261] [Xtensa] Implement support for the BranchRelaxation --- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 181 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 16 +- llvm/lib/Target/Xtensa/XtensaRegisterInfo.h | 4 + .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 3 + 4 files changed, 202 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index ded4df096d94ce..9d37a866cf9a4d 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -13,11 +13,13 @@ //===----------------------------------------------------------------------===// #include "XtensaInstrInfo.h" +#include "XtensaConstantPoolValue.h" #include "XtensaMachineFunctionInfo.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterScavenging.h" #define GET_INSTRINFO_CTOR_DTOR #include "XtensaGenInstrInfo.inc" @@ -162,6 +164,18 @@ void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB, } } +unsigned XtensaInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { + switch (MI.getOpcode()) { + case TargetOpcode::INLINEASM: { // Inline Asm: Variable size. + const MachineFunction *MF = MI.getParent()->getParent(); + const char *AsmStr = MI.getOperand(0).getSymbolName(); + return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); + } + default: + return MI.getDesc().getSize(); + } +} + bool XtensaInstrInfo::reverseBranchCondition( SmallVectorImpl &Cond) const { assert(Cond.size() <= 4 && "Invalid branch condition!"); @@ -223,6 +237,77 @@ bool XtensaInstrInfo::reverseBranchCondition( } } +MachineBasicBlock * +XtensaInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { + unsigned OpCode = MI.getOpcode(); + switch (OpCode) { + case Xtensa::BR_JT: + case Xtensa::JX: + return nullptr; + case Xtensa::J: + return MI.getOperand(0).getMBB(); + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + return MI.getOperand(2).getMBB(); + + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + return MI.getOperand(2).getMBB(); + + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + return MI.getOperand(1).getMBB(); + + default: + llvm_unreachable("Unknown branch opcode"); + } +} + +bool XtensaInstrInfo::isBranchOffsetInRange(unsigned BranchOp, + int64_t BrOffset) const { + switch (BranchOp) { + case Xtensa::J: + BrOffset -= 4; + return isIntN(18, BrOffset); + case Xtensa::JX: + return true; + case Xtensa::BR_JT: + return true; + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + BrOffset -= 4; + return isIntN(8, BrOffset); + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + BrOffset -= 4; + return isIntN(12, BrOffset); + default: + llvm_unreachable("Unknown branch opcode"); + } +} + bool XtensaInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, @@ -355,6 +440,102 @@ unsigned XtensaInstrInfo::insertBranch( return Count; } +void XtensaInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, + MachineBasicBlock &DestBB, + MachineBasicBlock &RestoreBB, + const DebugLoc &DL, + int64_t BrOffset, + RegScavenger *RS) const { + assert(RS && "RegScavenger required for long branching"); + assert(MBB.empty() && + "new block should be inserted for expanding unconditional branch"); + assert(MBB.pred_size() == 1); + + MachineFunction *MF = MBB.getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + MachineConstantPool *ConstantPool = MF->getConstantPool(); + + if (!isInt<32>(BrOffset)) + report_fatal_error( + "Branch offsets outside of the signed 32-bit range not supported"); + XtensaConstantPoolValue *C = + XtensaConstantPoolMBB::Create(MF->getFunction().getContext(), &DestBB, 0); + unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4)); + + // FIXME: A virtual register must be used initially, as the register + // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch + // uses the same workaround). + Register ScratchReg = MRI.createVirtualRegister(&Xtensa::ARRegClass); + auto II = MBB.end(); + + MachineInstr &L32R = *BuildMI(MBB, II, DL, get(Xtensa::L32R), ScratchReg) + .addConstantPoolIndex(Idx); + BuildMI(MBB, II, DL, get(Xtensa::JX)).addReg(ScratchReg, RegState::Kill); + RS->enterBasicBlockEnd(MBB); + unsigned Scav = RS->scavengeRegisterBackwards(Xtensa::ARRegClass, + L32R.getIterator(), false, 0); + MRI.replaceRegWith(ScratchReg, Scav); + MRI.clearVirtRegs(); + RS->setRegUsed(Scav); +} + +unsigned XtensaInstrInfo::InsertConstBranchAtInst( + MachineBasicBlock &MBB, MachineInstr *I, int64_t offset, + ArrayRef Cond, DebugLoc DL, int *BytesAdded) const { + // Shouldn't be a fall through. + assert(&MBB && "InsertBranch must not be told to insert a fallthrough"); + assert(Cond.size() <= 4 && + "Xtensa branch conditions have less than four components!"); + + if (Cond.empty() || (Cond[0].getImm() == Xtensa::J)) { + // Unconditional branch + MachineInstr *MI = BuildMI(MBB, I, DL, get(Xtensa::J)).addImm(offset); + if (BytesAdded && MI) + *BytesAdded += getInstSizeInBytes(*MI); + return 1; + } + + unsigned Count = 0; + unsigned BR_C = Cond[0].getImm(); + MachineInstr *MI = nullptr; + switch (BR_C) { + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + MI = BuildMI(MBB, I, DL, get(BR_C)) + .addImm(offset) + .addReg(Cond[1].getReg()) + .addReg(Cond[2].getReg()); + break; + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + MI = BuildMI(MBB, I, DL, get(BR_C)) + .addImm(offset) + .addReg(Cond[1].getReg()) + .addImm(Cond[2].getImm()); + break; + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + MI = BuildMI(MBB, I, DL, get(BR_C)).addImm(offset).addReg(Cond[1].getReg()); + break; + default: + llvm_unreachable("Invalid branch type!"); + } + if (BytesAdded && MI) + *BytesAdded += getInstSizeInBytes(*MI); + ++Count; + return Count; +} + unsigned XtensaInstrInfo::InsertBranchAtInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TBB, diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h index 09c40487dd3889..d9092c63c37133 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h @@ -37,6 +37,7 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; + unsigned getInstSizeInBytes(const MachineInstr &MI) const override; // Return the XtensaRegisterInfo, which this class owns. const XtensaRegisterInfo &getRegisterInfo() const { return RI; } @@ -66,6 +67,10 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { unsigned *Reg, int64_t Value) const; bool reverseBranchCondition(SmallVectorImpl &Cond) const override; + MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; + + bool isBranchOffsetInRange(unsigned BranchOpc, + int64_t BrOffset) const override; bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, @@ -76,13 +81,20 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { MachineBasicBlock *FBB, ArrayRef Cond, const DebugLoc &DL, int *BytesAdded = nullptr) const override; - + void insertIndirectBranch(MachineBasicBlock &MBB, + MachineBasicBlock &DestBB, + MachineBasicBlock &RestoreBB, const DebugLoc &DL, + int64_t BrOffset = 0, + RegScavenger *RS = nullptr) const override; unsigned InsertBranchAtInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TBB, ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const; - + unsigned InsertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I, + int64_t offset, + ArrayRef Cond, DebugLoc DL, + int *BytesAdded) const; // Return true if MI is a conditional or unconditional branch. // When returning true, set Cond to the mask of condition-code // values on which the instruction will branch, and set Target diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h index ba5557c446b637..d5403ff35a197a 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h @@ -40,6 +40,10 @@ struct XtensaRegisterInfo : public XtensaGenRegisterInfo { return true; } + bool trackLivenessAfterRegAlloc(const MachineFunction &) const override { + return true; + } + const uint16_t * getCalleeSavedRegs(const MachineFunction *MF = 0) const override; const uint32_t *getCallPreservedMask(const MachineFunction &MF, diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index c9a18c3728e78d..32d1684cc329a6 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -89,6 +89,7 @@ class XtensaPassConfig : public TargetPassConfig { } bool addInstSelector() override; + void addPreEmitPass() override; }; } // end anonymous namespace @@ -97,6 +98,8 @@ bool XtensaPassConfig::addInstSelector() { return false; } +void XtensaPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } + TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) { return new XtensaPassConfig(*this, PM); } From 336ee0811c522199bafe095f4602d018a8c670c8 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:30 +0300 Subject: [PATCH 021/261] [Xtensa] Implement code density feature operations --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 10 +++ .../Disassembler/XtensaDisassembler.cpp | 62 +++++++++++++++++ .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 22 ++++++ .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 2 + .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 48 ++++++++++++- llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 3 +- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 4 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 68 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaOperands.td | 14 ++++ 9 files changed, 230 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 3f808298527f8f..4b7b8ed0eb6847 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -179,6 +179,10 @@ struct XtensaOperand : public MCParsedAsmOperand { bool isImm1_16() const { return isImm(1, 16); } + bool isImm1n_15() const { return (isImm(1, 15) || isImm(-1, -1)); } + + bool isImm32n_95() const { return isImm(-32, 95); } + bool isB4const() const { if (Kind != Immediate) return false; @@ -402,6 +406,12 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidImm1_16: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [1, 16]"); + case Match_InvalidImm1n_15: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-1, 15] except 0"); + case Match_InvalidImm32n_95: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-32, 95] except 0"); case Match_InvalidShimm1_31: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [1, 31]"); diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 2d36b94dd40c77..612f43f7b72033 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -190,6 +190,28 @@ static DecodeStatus decodeImm1_16Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeImm1n_15Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<4>(Imm) && "Invalid immediate"); + if (!Imm) + Inst.addOperand(MCOperand::createImm(-1)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeImm32n_95Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<7>(Imm) && "Invalid immediate"); + if ((Imm & 0x60) == 0x60) + Inst.addOperand(MCOperand::createImm((~0x1f) | Imm)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { @@ -243,6 +265,34 @@ static DecodeStatus decodeMem32Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeMem32nOperand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder); + Inst.addOperand(MCOperand::createImm((Imm >> 2) & 0x3c)); + return MCDisassembler::Success; +} + +/// Read two bytes from the ArrayRef and return 16 bit data sorted +/// according to the given endianness. +static DecodeStatus readInstruction16(ArrayRef Bytes, uint64_t Address, + uint64_t &Size, uint32_t &Insn, + bool IsLittleEndian) { + // We want to read exactly 2 Bytes of data. + if (Bytes.size() < 2) { + Size = 0; + return MCDisassembler::Fail; + } + + if (!IsLittleEndian) { + llvm_unreachable("Big-endian mode currently is not supported!"); + } else { + Insn = (Bytes[1] << 8) | Bytes[0]; + } + + return MCDisassembler::Success; +} + /// Read three bytes from the ArrayRef and return 24 bit data static DecodeStatus readInstruction24(ArrayRef Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, @@ -272,6 +322,18 @@ DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size, uint32_t Insn; DecodeStatus Result; + if (hasDensity()) { + Result = readInstruction16(Bytes, Address, Size, Insn, IsLittleEndian); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + LLVM_DEBUG(dbgs() << "Trying Xtensa 16-bit instruction table :\n"); + Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + } + Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index 10becc9e8c83b3..d6175eb80eadb5 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -251,6 +251,28 @@ void XtensaInstPrinter::printImm1_16_AsmOperand(const MCInst *MI, int OpNum, printOperand(MI, OpNum, O); } +void XtensaInstPrinter::printImm1n_15_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -1 && (Value != 0) && Value <= 15) && + "Invalid argument, value must be in ranges <-1,-1> or <1,15>"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printImm32n_95_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -32 && Value <= 95) && + "Invalid argument, value must be in ranges <-32,95>"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + void XtensaInstPrinter::printOffset8m8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { if (MI->getOperand(OpNum).isImm()) { diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index 34d03569b9bce6..ca87d79bfb67db 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -60,6 +60,8 @@ class XtensaInstPrinter : public MCInstPrinter { void printUimm5_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printShimm1_31_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printImm1_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printImm1n_15_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printImm32n_95_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset8m8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset8m16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset8m32_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 1afdbb38f9571a..179887fa0fb087 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -103,6 +103,14 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + uint32_t getImm1n_15OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint32_t getImm32n_95OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + uint32_t getShimm1_31OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -255,6 +263,8 @@ XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo, break; case Xtensa::S32I: case Xtensa::L32I: + case Xtensa::S32I_N: + case Xtensa::L32I_N: if (Res & 0x3) { report_fatal_error("Unexpected operand value!"); } @@ -262,7 +272,15 @@ XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo, break; } - assert((isUInt<8>(Res)) && "Unexpected operand value!"); + switch (MI.getOpcode()) { + case Xtensa::S32I_N: + case Xtensa::L32I_N: + assert((isUInt<4>(Res)) && "Unexpected operand value!"); + break; + default: + assert((isUInt<8>(Res)) && "Unexpected operand value!"); + break; + } uint32_t OffBits = Res << 4; uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); @@ -354,6 +372,34 @@ XtensaMCCodeEmitter::getImm1_16OpValue(const MCInst &MI, unsigned OpNo, return (Res - 1); } +uint32_t +XtensaMCCodeEmitter::getImm1n_15OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int32_t Res = static_cast(MO.getImm()); + + assert(((Res >= -1) && (Res <= 15) && (Res != 0)) && + "Unexpected operand value!"); + + if (Res < 0) + Res = 0; + + return Res; +} + +uint32_t +XtensaMCCodeEmitter::getImm32n_95OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int32_t Res = static_cast(MO.getImm()); + + assert(((Res >= -32) && (Res <= 95)) && "Unexpected operand value!"); + + return Res; +} + uint32_t XtensaMCCodeEmitter::getB4constOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 5d27c0dadff8e7..31d2a4839d73bf 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -27,11 +27,12 @@ using namespace llvm; namespace { class XtensaDAGToDAGISel : public SelectionDAGISel { + const XtensaSubtarget *Subtarget; public: static char ID; XtensaDAGToDAGISel(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel), Subtarget(TM.getSubtargetImpl()) {} // Override MachineFunctionPass. StringRef getPassName() const override { diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index fab06277d59c49..614d25640df9f9 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -1490,10 +1490,12 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( case Xtensa::S8I: case Xtensa::S16I: case Xtensa::S32I: + case Xtensa::S32I_N: case Xtensa::L8UI: case Xtensa::L16SI: case Xtensa::L16UI: - case Xtensa::L32I: { + case Xtensa::L32I: + case Xtensa::L32I_N: { const MachineMemOperand &MMO = **MI.memoperands_begin(); if (MMO.isVolatile()) { BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW)); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 316c660dfffb2a..573e0477fc8f1a 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -635,3 +635,71 @@ let usesCustomInserter = 1 in { "!select $dst, $lhs, $rhs, $t, $f, $cond", [(set AR:$dst, (Xtensa_select_cc AR:$lhs, AR:$rhs, AR:$t, AR:$f, imm:$cond))]>; } + +//===----------------------------------------------------------------------===// +// Code Density instructions +//===----------------------------------------------------------------------===// + +class ArithLogic_RRRN oper0, string instrAsm, + SDPatternOperator opNode, bit isComm = 0> + : RRRN_Inst, Requires<[HasDensity]> { + let isCommutable = isComm; + let isReMaterializable = 0; +} + +def ADD_N : ArithLogic_RRRN<0x0a, "add.n", add, 1>; + +def ADDI_N : RRRN_Inst<0x0B, (outs AR:$r), (ins AR:$s, imm1n_15:$imm), + "addi.n\t$r, $s, $imm", + [(set AR:$r, (add AR:$s, imm1n_15:$imm))]>, Requires<[HasDensity]> { + bits<4> imm; + + let t = imm; +} + +def MOV_N : RRRN_Inst<0x0D, (outs AR:$t), (ins AR:$s), + "mov.n\t$t, $s", []>, Requires<[HasDensity]> { + let r = 0; +} + +def : InstAlias<"mov\t $t, $s", (OR AR:$t, AR:$s, AR:$s)>; + +def MOVI_N : RI7_Inst<0xc, 0x0, (outs AR:$s), (ins imm32n_95:$imm7), + "movi.n\t$s, $imm7", + [(set AR:$s, imm32n_95:$imm7)]>, Requires<[HasDensity]>; + +// Load instruction +let mayLoad = 1, usesCustomInserter = 1 in { + def L32I_N : RRRN_Inst<0x8, (outs AR:$t), (ins mem32n:$addr), + "l32i.n\t$t, $addr", []>, Requires<[HasDensity]> { + bits<8> addr; + + let r{3-0} = addr{7-4}; + let s{3-0} = addr{3-0}; + } +} + +// Store instruction +let mayStore = 1, usesCustomInserter = 1 in { + def S32I_N : RRRN_Inst<0x9, (outs), (ins AR:$t, mem32n:$addr), + "s32i.n\t$t, $addr", []>, Requires<[HasDensity]> { + bits<8> addr; + + let r{3-0} = addr{7-4}; + let s{3-0} = addr{3-0}; + } +} + +//Return instruction +let isReturn = 1, isTerminator = 1, + isBarrier = 1, Uses = [A0] in { + def RET_N : RRRN_Inst<0x0D, (outs), (ins), + "ret.n", [(Xtensa_retflag)]>, + Requires<[HasDensity]> { + let r = 0x0F; + let s = 0; + let t = 0; + } +} diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 034aef55f76350..a1db366e2425fb 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -72,6 +72,20 @@ def imm1_16 : Immediate= 1 && Imm <= 16; }], "Imm1_16_AsmOp let DecoderMethod = "decodeImm1_16Operand"; } +// imm1n_15 predicate - Immediate in the range [-1,15], except 0 +def Imm1n_15_AsmOperand: ImmAsmOperand<"Imm1n_15">; +def imm1n_15: Immediate= -1 && Imm <= 15 && Imm != 0; }], "Imm1n_15_AsmOperand"> { + let EncoderMethod = "getImm1n_15OpValue"; + let DecoderMethod = "decodeImm1n_15Operand"; +} + +// imm32n_95 predicate - Immediate in the range [-32,95] +def Imm32n_95_AsmOperand: ImmAsmOperand<"Imm32n_95">; +def imm32n_95: Immediate= -32 && Imm <= 95; }], "Imm32n_95_AsmOperand"> { + let EncoderMethod = "getImm32n_95OpValue"; + let DecoderMethod = "decodeImm32n_95Operand"; +} + // shimm1_31 predicate - Immediate in the range [1,31] def Shimm1_31_AsmOperand : ImmAsmOperand<"Shimm1_31">; def shimm1_31 : Immediate= 1 && Imm <= 31; }], "Shimm1_31_AsmOperand"> { From d6df053d5e9b717e66455bf2f5221f584541f8b0 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:31 +0300 Subject: [PATCH 022/261] [Xtensa] Add code size reduction pass. --- llvm/lib/Target/Xtensa/CMakeLists.txt | 1 + llvm/lib/Target/Xtensa/Xtensa.h | 1 + .../Target/Xtensa/XtensaSizeReductionPass.cpp | 253 ++++++++++++++++++ .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 5 +- 4 files changed, 259 insertions(+), 1 deletion(-) create mode 100644 llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index 2208428f4c10c1..1a3ff0c5311fe6 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -24,6 +24,7 @@ add_llvm_target(XtensaCodeGen XtensaMachineFunctionInfo.cpp XtensaMCInstLower.cpp XtensaRegisterInfo.cpp + XtensaSizeReductionPass.cpp XtensaSubtarget.cpp XtensaTargetMachine.cpp diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h index 6f258654bd6cec..20e2ab7bbb5d06 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.h +++ b/llvm/lib/Target/Xtensa/Xtensa.h @@ -26,5 +26,6 @@ class FunctionPass; FunctionPass *createXtensaISelDag(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel); +FunctionPass *createXtensaSizeReductionPass(); } // namespace llvm #endif /* LLVM_LIB_TARGET_XTENSA_XTENSA_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp b/llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp new file mode 100644 index 00000000000000..f69c1e601a788c --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp @@ -0,0 +1,253 @@ +//===- XtensaSizeReductionPass.cpp - Xtensa Size Reduction ----------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "XtensaInstrInfo.h" +#include "XtensaSubtarget.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen//MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +#define DEBUG_TYPE "xtensa-size-reduce-pass" + +STATISTIC(NumReduced, "Number of 24-bit instructions reduced to 16-bit ones"); + +class XtensaSizeReduce : public MachineFunctionPass { +public: + static char ID; + XtensaSizeReduce() : MachineFunctionPass(ID) {} + + const XtensaSubtarget *Subtarget; + static const XtensaInstrInfo *XtensaII; + + bool runOnMachineFunction(MachineFunction &MF) override; + + llvm::StringRef getPassName() const override { + return "Xtensa instruction size reduction pass"; + } + +private: + /// Reduces width of instructions in the specified basic block. + bool ReduceMBB(MachineBasicBlock &MBB); + + /// Attempts to reduce MI, returns true on success. + bool ReduceMI(const MachineBasicBlock::instr_iterator &MII); +}; + +char XtensaSizeReduce::ID = 0; +const XtensaInstrInfo *XtensaSizeReduce::XtensaII; + +bool XtensaSizeReduce::ReduceMI(const MachineBasicBlock::instr_iterator &MII) { + MachineInstr *MI = &*MII; + MachineBasicBlock &MBB = *MI->getParent(); + unsigned Opcode = MI->getOpcode(); + + switch (Opcode) { + case Xtensa::L32I: { + MachineOperand Op0 = MI->getOperand(0); + MachineOperand Op1 = MI->getOperand(1); + MachineOperand Op2 = MI->getOperand(2); + + int64_t Imm = Op2.getImm(); + if (Imm >= 0 && Imm <= 60) { + // Replace L32I to L32I.N + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::L32I_N); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + MIB.add(Op0); + MIB.add(Op1); + MIB.add(Op2); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); + NumReduced++; + MBB.erase_instr(MI); + return true; + } + } break; + + case Xtensa::S32I: { + MachineOperand Op0 = MI->getOperand(0); + MachineOperand Op1 = MI->getOperand(1); + MachineOperand Op2 = MI->getOperand(2); + + int64_t Imm = Op2.getImm(); + if (Imm >= 0 && Imm <= 60) { + // Replace S32I to S32I.N + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::S32I_N); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + MIB.add(Op0); + MIB.add(Op1); + MIB.add(Op2); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); + NumReduced++; + MBB.erase_instr(MI); + return true; + } + + } break; + + case Xtensa::MOVI: { + MachineOperand Op0 = MI->getOperand(0); + MachineOperand Op1 = MI->getOperand(1); + + int64_t Imm = Op1.getImm(); + if (Imm >= -32 && Imm <= 95) { + // Replace MOVI to MOVI.N + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MOVI_N); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + MIB.add(Op0); + MIB.add(Op1); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); + NumReduced++; + MBB.erase_instr(MI); + return true; + } + + } break; + + case Xtensa::ADD: { + MachineOperand Op0 = MI->getOperand(0); + MachineOperand Op1 = MI->getOperand(1); + MachineOperand Op2 = MI->getOperand(2); + + // Replace ADD to ADD.N + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::ADD_N); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + MIB.add(Op0); + MIB.add(Op1); + MIB.add(Op2); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); + NumReduced++; + MBB.erase_instr(MI); + return true; + + } break; + + case Xtensa::ADDI: { + MachineOperand Op0 = MI->getOperand(0); + MachineOperand Op1 = MI->getOperand(1); + MachineOperand Op2 = MI->getOperand(2); + + int64_t Imm = Op2.getImm(); + if ((Imm >= 1 && Imm <= 15) || (Imm == -1)) { + // Replace ADDI to ADDI.N + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::ADDI_N); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + MIB.add(Op0); + MIB.add(Op1); + MIB.add(Op2); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); + NumReduced++; + MBB.erase_instr(MI); + return true; + } + } break; + + case Xtensa::OR: { + MachineOperand Op0 = MI->getOperand(0); + MachineOperand Op1 = MI->getOperand(1); + MachineOperand Op2 = MI->getOperand(2); + + if (Op1.getReg() != Op2.getReg()) + break; + + // Replace OR R1, R2, R2 to MOV.N R1, R2 + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MOV_N); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + MIB.add(Op0); + MIB.add(Op1); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); + NumReduced++; + MBB.erase_instr(MI); + return true; + } break; + + case Xtensa::RET: { + // Replace RET to RET.N + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::RET_N); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); + NumReduced++; + MBB.erase_instr(MI); + return true; + } break; + + default: + break; + } + + return false; +} + +bool XtensaSizeReduce::ReduceMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::instr_iterator MII = MBB.instr_begin(), + E = MBB.instr_end(); + MachineBasicBlock::instr_iterator NextMII; + + // Iterate through the instructions in the basic block + for (; MII != E; MII = NextMII) { + NextMII = std::next(MII); + MachineInstr *MI = &*MII; + + // Don't reduce bundled instructions or pseudo operations + if (MI->isBundle() || MI->isTransient()) + continue; + + // Try to reduce 24-bit instruction into 16-bit instruction + Modified |= ReduceMI(MII); + } + + return Modified; +} + +bool XtensaSizeReduce::runOnMachineFunction(MachineFunction &MF) { + + Subtarget = &static_cast(MF.getSubtarget()); + XtensaII = static_cast(Subtarget->getInstrInfo()); + bool Modified = false; + + if (!Subtarget->hasDensity()) + return Modified; + + MachineFunction::iterator I = MF.begin(), E = MF.end(); + + for (; I != E; ++I) + Modified |= ReduceMBB(*I); + return Modified; +} + +FunctionPass *llvm::createXtensaSizeReductionPass() { + return new XtensaSizeReduce(); +} diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 32d1684cc329a6..2d2bf2112226b5 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -98,7 +98,10 @@ bool XtensaPassConfig::addInstSelector() { return false; } -void XtensaPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } +void XtensaPassConfig::addPreEmitPass() { + addPass(createXtensaSizeReductionPass()); + addPass(&BranchRelaxationPassID); +} TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) { return new XtensaPassConfig(*this, PM); From 1321421fc3b7d94fec0270a8118c32372ca4afa1 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:31 +0300 Subject: [PATCH 023/261] [Xtensa] Implement Windowed feature operations --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 16 +++ .../Disassembler/XtensaDisassembler.cpp | 29 +++- .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 34 +++++ .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 3 + .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 52 +++++++ llvm/lib/Target/Xtensa/Xtensa.td | 5 + llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 3 + llvm/lib/Target/Xtensa/XtensaISelLowering.h | 6 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 135 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaOperands.td | 21 +++ llvm/lib/Target/Xtensa/XtensaOperators.td | 10 +- llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 6 +- .../Target/Xtensa/XtensaSizeReductionPass.cpp | 15 +- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 7 + 15 files changed, 339 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 4b7b8ed0eb6847..9b59c95dd24ccf 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -167,6 +167,8 @@ struct XtensaOperand : public MCParsedAsmOperand { ((cast(getImm())->getValue() & 0x3) == 0); } + bool isentry_imm12() const { return isImm(0, 32760); } + bool isUimm4() const { return isImm(0, 15); } bool isUimm5() const { return isImm(0, 31); } @@ -183,6 +185,11 @@ struct XtensaOperand : public MCParsedAsmOperand { bool isImm32n_95() const { return isImm(-32, 95); } + bool isImm64n_4n() const { + return isImm(-64, -4) && + ((dyn_cast(getImm())->getValue() & 0x3) == 0); + } + bool isB4const() const { if (Kind != Immediate) return false; @@ -412,6 +419,12 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidImm32n_95: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [-32, 95] except 0"); + case Match_InvalidImm64n_4n: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-64, -4]"); + case Match_InvalidImm8n_7: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-8, 7]"); case Match_InvalidShimm1_31: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [1, 31]"); @@ -436,6 +449,9 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [0, 60], first 2 bits " "should be zero"); + case Match_Invalidentry_imm12: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 32760]"); } report_fatal_error("Unknown match type detected!"); diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 612f43f7b72033..bf36925c92c6b6 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -75,7 +75,8 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Success; } -static const unsigned SRDecoderTable[] = {Xtensa::SAR, 3}; +static const unsigned SRDecoderTable[] = { + Xtensa::SAR, 3, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73}; static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, @@ -212,6 +213,32 @@ static DecodeStatus decodeImm32n_95Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeImm8n_7Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + assert(isUInt<4>(Imm) && "Invalid immediate"); + if (Imm > 7) + Inst.addOperand(MCOperand::createImm(Imm - 16)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<4>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm((~0x3f) | (Imm << 2))); + return MCDisassembler::Success; +} + +static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<12>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm << 3)); + return MCDisassembler::Success; +} + static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index d6175eb80eadb5..d1308ed56aa003 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -273,6 +273,28 @@ void XtensaInstPrinter::printImm32n_95_AsmOperand(const MCInst *MI, int OpNum, printOperand(MI, OpNum, O); } +void XtensaInstPrinter::printImm8n_7_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -8 && Value <= 7) && + "Invalid argument, value must be in ranges <-8,7>"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printImm64n_4n_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -64 && Value <= -4) & ((Value & 0x3) == 0) && + "Invalid argument, value must be in ranges <-64,-4>"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + void XtensaInstPrinter::printOffset8m8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { if (MI->getOperand(OpNum).isImm()) { @@ -318,6 +340,18 @@ void XtensaInstPrinter::printOffset4m32_AsmOperand(const MCInst *MI, int OpNum, printOperand(MI, OpNum, O); } +void XtensaInstPrinter::printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 32760) && + "Invalid argument, value must be multiples of eight in range " + "<0,32760>"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + void XtensaInstPrinter::printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { if (MI->getOperand(OpNum).isImm()) { diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index ca87d79bfb67db..f8a9f592e01101 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -62,10 +62,13 @@ class XtensaInstPrinter : public MCInstPrinter { void printImm1_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printImm1n_15_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printImm32n_95_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printImm8n_7_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printImm64n_4n_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset8m8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset8m16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset8m32_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset4m32_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); }; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 179887fa0fb087..110e3962470705 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -111,6 +111,18 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + uint32_t getImm8n_7OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint32_t getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint32_t getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + uint32_t getShimm1_31OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -400,6 +412,46 @@ XtensaMCCodeEmitter::getImm32n_95OpValue(const MCInst &MI, unsigned OpNo, return Res; } +uint32_t +XtensaMCCodeEmitter::getImm8n_7OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int32_t Res = static_cast(MO.getImm()); + + assert(((Res >= -8) && (Res <= 7)) && "Unexpected operand value!"); + + if (Res < 0) + return Res + 16; + + return Res; +} + +uint32_t +XtensaMCCodeEmitter::getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int32_t Res = static_cast(MO.getImm()); + + assert(((Res >= -64) && (Res <= -4) && ((Res & 0x3) == 0)) && + "Unexpected operand value!"); + + return Res & 0x3f; +} + +uint32_t +XtensaMCCodeEmitter::getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint32_t res = static_cast(MO.getImm()); + + assert(((res & 0x7) == 0) && "Unexpected operand value!"); + + return res; +} + uint32_t XtensaMCCodeEmitter::getB4constOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 460a15e808b3a4..8a9f0778337faa 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -21,6 +21,11 @@ def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true", "Enable Density instructions">; def HasDensity : Predicate<"Subtarget->hasDensity()">, AssemblerPredicate<(all_of FeatureDensity)>; + +def FeatureWindowed : SubtargetFeature<"windowed", "HasWindowed", "true", + "Enable Xtensa Windowed Register option">; +def HasWindowed : Predicate<"Subtarget->hasWindowed()">, + AssemblerPredicate<(all_of FeatureWindowed)>; //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 614d25640df9f9..dc9afc42ca66a7 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -1285,11 +1285,14 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { return "XtensaISD::" #NAME switch (Opcode) { OPCODE(RET_FLAG); + OPCODE(RETW_FLAG); OPCODE(CALL); + OPCODE(CALLW); OPCODE(PCREL_WRAPPER); OPCODE(SELECT); OPCODE(SELECT_CC); OPCODE(BR_JT); + OPCODE(MOVSP); OPCODE(SHL); OPCODE(SRA); OPCODE(SRL); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index e9dd80709bb1cb..875cc8a943c34d 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -31,6 +31,10 @@ enum { // is the target address. The arguments start at operand 2. // There is an optional glue operand at the end. CALL, + // WinABI Call version + CALLW, + + MOVSP, // Wraps a TargetGlobalAddress that should be loaded using PC-relative // accesses. Operand 0 is the address. @@ -38,6 +42,8 @@ enum { // Return with a flag operand. Operand 0 is the chain operand. RET_FLAG, + // WinABI Return + RETW_FLAG, // Selects between operand 0 and operand 1. Operand 2 is the // mask of condition-code values for which operand 0 should be diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 573e0477fc8f1a..d547e7bffb28c4 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -703,3 +703,138 @@ let isReturn = 1, isTerminator = 1, let t = 0; } } + +//===----------------------------------------------------------------------===// +// Windowed instructions +//===----------------------------------------------------------------------===// + +def ENTRY : BRI12_Inst<0x06, 0x3, 0x0, (outs), (ins AR:$s, entry_imm12:$imm), + "entry\t$s, $imm", []>, Requires<[HasWindowed]> { + bits<15> imm; + + let imm12{11-0} = imm{14-3}; + let Defs = [SP]; +} + +//Call instructions +let isCall = 1, Defs = [A0] in { + def CALL4 : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset), + "call4\t$offset", []>, Requires<[HasWindowed]> { + let n = 1; + } + + def CALL8 : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset), + "call8\t$offset", []>, Requires<[HasWindowed]> { + let n = 2; + } + + def CALL12 : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset), + "call12\t$offset", []>, Requires<[HasWindowed]> { + let n = 3; + } + + def CALLX4 : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s), + "callx4\t$s", []>, Requires<[HasWindowed]> { + let m = 0x3; + let n = 0x1; + let r = 0; + } + + def CALLX8 : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s), + "callx8\t$s", []>, Requires<[HasWindowed]> { + let m = 0x3; + let n = 0x2; + let r = 0; + } + + def CALLX12 : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s), + "callx12\t$s", []>, Requires<[HasWindowed]> { + let m = 0x3; + let n = 0x3; + let r = 0; + } +} + +//Windowed call patterns +def : Pat<(Xtensa_callw (i32 tglobaladdr:$dst)), + (CALL8 tglobaladdr:$dst)>; +def : Pat<(Xtensa_callw (i32 texternalsym:$dst)), + (CALL8 texternalsym:$dst)>; +def : Pat<(Xtensa_callw AR:$dst), + (CALLX8 AR:$dst)>; + +def MOVSP : RRR_Inst<0x00, 0x00, 0x00, (outs AR:$t), (ins AR:$s), + "movsp\t$t, $s", + [(set AR:$t, (Xtensa_movsp AR:$s))]>, + Requires<[HasWindowed]> { + let r = 0x01; +} + +//Return instructions +let isReturn = 1, isTerminator = 1, + isBarrier = 1, Uses = [A0] in { + def RETW_N : RRRN_Inst<0x0D, (outs), (ins), + "retw.n", [(Xtensa_retWflag)]>, + Requires<[HasWindowed, HasDensity]> { + let r = 0x0F; + let s = 0; + let t = 1; + } + + def RETW : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins), + "retw", [(Xtensa_retWflag)]>, + Requires<[HasWindowed]> { + let m = 0x2; + let n = 0x1; + let s = 0; + let r = 0; + } +} + +//Store 32-bit for Window Exceptions +def S32E : RRI4_Inst<0x00, 0x09, (outs), (ins AR:$t, AR:$s, imm64n_4n:$imm), + "s32e\t$t, $s, $imm", []>, Requires<[HasWindowed]> { + bits<6> imm; + + let r = imm{5-2}; + let imm4 = 0x4; + let mayStore = 1; +} + +def L32E : RRI4_Inst<0x00, 0x09, (outs), (ins AR:$t, AR:$s, imm64n_4n:$imm), + "l32e\t$t, $s, $imm", []>, Requires<[HasWindowed]> { + bits<6> imm; + + let r = imm{5-2}; + let imm4 = 0x0; + let mayLoad = 1; +} + +//Return from window +def RFWU : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), + "rfwu", []>, Requires<[HasWindowed]> { + bits<4> imm; + + let r = 0x3; + let s = 0x5; + let t = 0x0; +} + +def RFWO : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), + "rfwo", []>, Requires<[HasWindowed]> { + bits<4> imm; + + let r = 0x3; + let s = 0x4; + let t = 0x0; +} + +//Rotate window +def ROTW : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins imm8n_7:$imm), + "rotw\t$imm", []>, Requires<[HasWindowed]> { + bits<4> imm; + + let r = 0x8; + let s = 0x0; + let t = imm{3-0}; +} diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index a1db366e2425fb..47946596282ad9 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -37,6 +37,20 @@ def imm8_sh8 : Immediate= -32768 && Imm <= 32512 && ((Imm & let DecoderMethod = "decodeImm8_sh8Operand"; } +// imm8n_7 predicate - Immediate in the range [-8,7] +def Imm8n_7_AsmOperand: ImmAsmOperand<"Imm8n_7">; +def imm8n_7: Immediate= -8 && Imm <= 7; }], "Imm8n_7_AsmOperand"> { + let EncoderMethod = "getImm8n_7OpValue"; + let DecoderMethod = "decodeImm8n_7Operand"; +} + +// imm64n_4n predicate - Immediate in the range [-64,-4] +def Imm64n_4n_AsmOperand: ImmAsmOperand<"Imm64n_4n">; +def imm64n_4n: Immediate= -64 && Imm <= -4; }], "Imm64n_4n_AsmOperand"> { + let EncoderMethod = "getImm64n_4nOpValue"; + let DecoderMethod = "decodeImm64n_4nOperand"; +} + // imm12 predicate - Immediate in the range [-2048,2047] def Imm12_AsmOperand : ImmAsmOperand<"Imm12">; def imm12 : Immediate= -2048 && Imm <= 2047; }], "Imm12_AsmOperand"> { @@ -117,6 +131,13 @@ def offset4m32 : Immediate= 0 && Imm <= 60 && (Imm & 0x3 == 0); }], "Offset4m32_AsmOperand">; +// entry_imm12 predicate - Immediate in the range [0,32760], ENTRY parameter +def Entry_Imm12_AsmOperand: ImmAsmOperand<"entry_imm12">; +def entry_imm12: Immediate= 0 && Imm <= 32760 && (Imm & 0x3 == 0); }], "Entry_Imm12_AsmOperand"> { + let EncoderMethod = "getEntry_Imm12OpValue"; + let DecoderMethod = "decodeEntry_Imm12OpValue"; +} + // b4const predicate - Branch Immediate 4-bit signed operand def B4const_AsmOperand: ImmAsmOperand<"B4const">; def b4const: Immediate, SDTCisSameAs<2, 3>, SDTCisVT<5, i32>]>; + +def SDT_XtensaMOVSP : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>; def SDT_XtensaBrJT : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; @@ -43,7 +45,8 @@ def Xtensa_call: SDNode<"XtensaISD::CALL", SDT_XtensaCall, def Xtensa_retflag: SDNode<"XtensaISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; - +def Xtensa_retWflag: SDNode<"XtensaISD::RETW_FLAG", SDTNone, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def Xtensa_callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_XtensaCallSeqStart, [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; @@ -57,6 +60,9 @@ def Xtensa_select : SDNode<"XtensaISD::SELECT", SDTSelect>; def Xtensa_select_cc: SDNode<"XtensaISD::SELECT_CC", SDT_XtensaSelectCC, [SDNPInGlue]>; +def Xtensa_movsp: SDNode<"XtensaISD::MOVSP", SDT_XtensaMOVSP, + [SDNPInGlue]>; + def Xtensa_shl: SDNode<"XtensaISD::SHL", SDT_XtensaSHL, [SDNPInGlue]>; def Xtensa_sra: SDNode<"XtensaISD::SRA", SDT_XtensaSRA, [SDNPInGlue]>; def Xtensa_srl: SDNode<"XtensaISD::SRL", SDT_XtensaSRL, [SDNPInGlue]>; @@ -65,3 +71,5 @@ def Xtensa_ssl: SDNode<"XtensaISD::SSL", SDT_XtensaSSL, [SDNPOutGlue]>; def Xtensa_ssr: SDNode<"XtensaISD::SSR", SDT_XtensaSSR, [SDNPOutGlue]>; def Xtensa_brjt: SDNode<"XtensaISD::BR_JT", SDT_XtensaBrJT, [SDNPHasChain]>; +def Xtensa_callw: SDNode<"XtensaISD::CALLW", SDT_XtensaCall, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 5c07386b060cd9..9939d19ef1907c 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -75,4 +75,8 @@ class SRReg num, string n, list alt = []> : XtensaReg { // Shift Amount Register def SAR : SRReg<3, "sar", ["SAR","3"]>; -def SR : RegisterClass<"Xtensa", [i32], 32, (add SAR)>; +def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>; +def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>; + +def SR : RegisterClass<"Xtensa", [i32], 32, (add SAR, + WINDOWBASE, WINDOWSTART)>; diff --git a/llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp b/llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp index f69c1e601a788c..1377d7fccf1e05 100644 --- a/llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp @@ -173,7 +173,7 @@ bool XtensaSizeReduce::ReduceMI(const MachineBasicBlock::instr_iterator &MII) { MachineOperand Op1 = MI->getOperand(1); MachineOperand Op2 = MI->getOperand(2); - if (Op1.getReg() != Op2.getReg()) + if (Op1.getReg() != Op2.getReg()) break; // Replace OR R1, R2, R2 to MOV.N R1, R2 @@ -203,6 +203,19 @@ bool XtensaSizeReduce::ReduceMI(const MachineBasicBlock::instr_iterator &MII) { return true; } break; + case Xtensa::RETW: { + // Replace RETW to RETW.N + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::RETW_N); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); + NumReduced++; + MBB.erase_instr(MI); + return true; + } break; + default: break; } diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index f76af66cac1efd..fe47de0f952712 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -33,6 +33,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { } HasDensity = false; + HasWindowed = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index 476f1f943a9ea7..aea0a9ed9b452d 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -41,6 +41,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enabled Xtensa Density extension bool HasDensity; + // Enabled Xtensa Windowed Register option + bool HasWindowed; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -56,8 +59,12 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { const XtensaTargetLowering *getTargetLowering() const override { return &TLInfo; } const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { return &TSInfo; } + bool isWinABI() const { return hasWindowed(); } + bool hasDensity() const { return HasDensity; } + bool hasWindowed() const { return HasWindowed; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; From 59dca5ec31bbe3a41ce55f5dcee84a4303225455 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:32 +0300 Subject: [PATCH 024/261] [Xtensa] Implement Windowed Call ABI --- llvm/lib/Target/Xtensa/XtensaCallingConv.td | 14 ++ .../lib/Target/Xtensa/XtensaFrameLowering.cpp | 167 +++++++++++++----- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 58 +++++- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 10 +- llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 13 +- 5 files changed, 203 insertions(+), 59 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaCallingConv.td b/llvm/lib/Target/Xtensa/XtensaCallingConv.td index c39eb665b4d33c..adfb8656b32d38 100644 --- a/llvm/lib/Target/Xtensa/XtensaCallingConv.td +++ b/llvm/lib/Target/Xtensa/XtensaCallingConv.td @@ -32,3 +32,17 @@ def RetCC_Xtensa : CallingConv<[ //===----------------------------------------------------------------------===// def CSR_Xtensa : CalleeSavedRegs<(add A0, A12, A13, A14, A15)>; +def CSRWE_Xtensa : CalleeSavedRegs<(add)> { + let OtherPreserved = (add A0, SP, A2, A3, A4, A5, A6, A7); +} +//===----------------------------------------------------------------------===// + +def RetCCW_Xtensa : CallingConv<[ + CCIfType<[i1, i8, i16], CCPromoteToType>, + CCIfType<[f32], CCBitConvertToType>, + + //First two return values go in a10, a11, a12, a13 + CCIfType<[i32], CCAssignToReg<[A10, A11, A12, A13]>>, + CCIfType<[f32], CCAssignToReg<[A10, A11, A12, A13]>>, + CCIfType<[i64], CCAssignToRegWithShadow<[A10, A12], [A11, A13]>> +]>; diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index 53d180cc0e58d6..82cc9584a31b04 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -79,6 +79,12 @@ bool XtensaFrameLowering::hasFP(const MachineFunction &MF) const { MFI.hasVarSizedObjects(); } +/* minimum frame = reg save area (4 words) plus static chain (1 word) + and the total number of words must be a multiple of 128 bits. */ +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD 4 +#define MIN_FRAME_SIZE (8 * UNITS_PER_WORD) + void XtensaFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { assert(&MBB == &MF.front() && "Shrink-wrapping not yet implemented"); @@ -88,6 +94,7 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF, const XtensaInstrInfo &TII = *static_cast(MF.getSubtarget().getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); + const XtensaSubtarget &STI = MF.getSubtarget(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); unsigned SP = Xtensa::SP; unsigned FP = RegInfo->getFrameRegister(MF); @@ -101,53 +108,105 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF, // Round up StackSize to 16*N StackSize += (16 - StackSize) & 0xf; - // No need to allocate space on the stack. - if (StackSize == 0 && !MFI.adjustsStack()) - return; + if (STI.isWinABI()) { + StackSize += 32; + + if (StackSize <= 32760) { + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::ENTRY)) + .addReg(SP) + .addImm(StackSize); + } else { + /* Use a8 as a temporary since a0-a7 may be live. */ + unsigned TmpReg = Xtensa::A8; + + const XtensaInstrInfo &TII = *static_cast( + MBB.getParent()->getSubtarget().getInstrInfo()); + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::ENTRY)) + .addReg(SP) + .addImm(MIN_FRAME_SIZE); + TII.loadImmediate(MBB, MBBI, &TmpReg, StackSize - MIN_FRAME_SIZE); + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::SUB), TmpReg) + .addReg(SP) + .addReg(TmpReg); + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::MOVSP), SP).addReg(TmpReg); + } - // Adjust stack. - TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); - - // emit ".cfi_def_cfa_offset StackSize" - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); - BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); - - const std::vector &CSI = MFI.getCalleeSavedInfo(); - - if (CSI.size()) { - // Find the instruction past the last instruction that saves a - // callee-saved register to the stack. - for (unsigned i = 0; i < CSI.size(); ++i) - ++MBBI; - - // Iterate over list of callee-saved registers and emit .cfi_offset - // directives. - for (const auto &I : CSI) { - int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); - unsigned Reg = I.getReg(); - - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, MRI->getDwarfRegNum(Reg, 1), Offset)); + // Store FP register in A8, because FP may be used to pass function + // arguments + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::OR), Xtensa::A8) + .addReg(FP) + .addReg(FP); + + // if framepointer enabled, set it to point to the stack pointer. + if (hasFP(MF)) { + // Insert instruction "move $fp, $sp" at this location. + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::OR), FP) + .addReg(SP) + .addReg(SP) + .setMIFlag(MachineInstr::FrameSetup); + + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( + nullptr, MRI->getDwarfRegNum(FP, true), StackSize); + unsigned CFIIndex = MF.addFrameInst(Inst); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + } else { + // emit ".cfi_def_cfa_offset StackSize" + unsigned CFIIndex = MF.addFrameInst( + MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } - } + } else { + // No need to allocate space on the stack. + if (StackSize == 0 && !MFI.adjustsStack()) + return; - // if framepointer enabled, set it to point to the stack pointer. - if (hasFP(MF)) { - // Insert instruction "move $fp, $sp" at this location. - BuildMI(MBB, MBBI, dl, TII.get(Xtensa::OR), FP) - .addReg(SP) - .addReg(SP) - .setMIFlag(MachineInstr::FrameSetup); - - // emit ".cfi_def_cfa_register $fp" - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( - nullptr, MRI->getDwarfRegNum(FP, true))); + // Adjust stack. + TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); + + // emit ".cfi_def_cfa_offset StackSize" + unsigned CFIIndex = MF.addFrameInst( + MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); + + const std::vector &CSI = MFI.getCalleeSavedInfo(); + + if (CSI.size()) { + // Find the instruction past the last instruction that saves a + // callee-saved register to the stack. + for (unsigned i = 0; i < CSI.size(); ++i) + ++MBBI; + + // Iterate over list of callee-saved registers and emit .cfi_offset + // directives. + for (const auto &I : CSI) { + int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); + unsigned Reg = I.getReg(); + + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( + nullptr, MRI->getDwarfRegNum(Reg, 1), Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + } + } + + // if framepointer enabled, set it to point to the stack pointer. + if (hasFP(MF)) { + // Insert instruction "move $fp, $sp" at this location. + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::OR), FP) + .addReg(SP) + .addReg(SP) + .setMIFlag(MachineInstr::FrameSetup); + + // emit ".cfi_def_cfa_register $fp" + unsigned CFIIndex = + MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( + nullptr, MRI->getDwarfRegNum(FP, true))); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + } } if (StackSize != PrevStackSize) { @@ -172,6 +231,7 @@ void XtensaFrameLowering::emitEpilogue(MachineFunction &MF, MF.getSubtarget().getRegisterInfo()); const XtensaInstrInfo &TII = *static_cast(MF.getSubtarget().getInstrInfo()); + const XtensaSubtarget &STI = MF.getSubtarget(); DebugLoc dl = MBBI->getDebugLoc(); unsigned SP = Xtensa::SP; unsigned FP = RegInfo->getFrameRegister(MF); @@ -183,10 +243,17 @@ void XtensaFrameLowering::emitEpilogue(MachineFunction &MF, for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) --I; - - BuildMI(MBB, I, dl, TII.get(Xtensa::OR), SP).addReg(FP).addReg(FP); + if (STI.isWinABI()) { + // Insert instruction "movsp $sp, $fp" at this location. + BuildMI(MBB, I, dl, TII.get(Xtensa::MOVSP), SP).addReg(FP); + } else { + BuildMI(MBB, I, dl, TII.get(Xtensa::OR), SP).addReg(FP).addReg(FP); + } } + if (STI.isWinABI()) + return; + // Get the number of bytes from FrameInfo uint64_t StackSize = MFI.getStackSize(); @@ -201,6 +268,10 @@ bool XtensaFrameLowering::spillCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef CSI, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); + const XtensaSubtarget &STI = MF->getSubtarget(); + + if (STI.isWinABI()) + return true; MachineBasicBlock &EntryBlock = *(MF->begin()); const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); @@ -229,8 +300,11 @@ bool XtensaFrameLowering::spillCalleeSavedRegisters( bool XtensaFrameLowering::restoreCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - MutableArrayRef CSI, - const TargetRegisterInfo *TRI) const { + MutableArrayRef CSI, const TargetRegisterInfo *TRI) const { + MachineFunction *MF = MBB.getParent(); + const XtensaSubtarget &STI = MF->getSubtarget(); + if (STI.isWinABI()) + return true; return TargetFrameLowering::restoreCalleeSavedRegisters(MBB, MI, CSI, TRI); } @@ -257,11 +331,16 @@ MachineBasicBlock::iterator XtensaFrameLowering::eliminateCallFramePseudoInstr( void XtensaFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { + const XtensaSubtarget &STI = MF.getSubtarget(); MachineFrameInfo &MFI = MF.getFrameInfo(); const XtensaRegisterInfo *RegInfo = static_cast( MF.getSubtarget().getRegisterInfo()); unsigned FP = RegInfo->getFrameRegister(MF); + if (STI.isWinABI()) { + return; + } + TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); // Mark $fp as used if function has dedicated frame pointer. diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index dc9afc42ca66a7..3d5b7f11185689 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -43,6 +43,15 @@ static bool isLongCall(const char *str) { return true; } +// The calling conventions in XtensaCallingConv.td are described in terms of the +// callee's register window. This function translates registers to the +// corresponding caller window %o register. +static unsigned toCallerWindow(unsigned Reg) { + if (Reg >= Xtensa::A2 && Reg <= Xtensa::A7) + return Reg - Xtensa::A2 + Xtensa::A10; + return Reg; +} + XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, const XtensaSubtarget &STI) : TargetLowering(tm), Subtarget(STI) { @@ -428,7 +437,17 @@ SDValue XtensaTargetLowering::LowerFormalArguments( // Transform the arguments stored on // physical registers into virtual ones - unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); + unsigned Reg = 0; + unsigned FrameReg = Subtarget.getRegisterInfo()->getFrameRegister(MF); + + // Argument passed in FrameReg in WinABI we save in A8 (in emitPrologue), + // so load argument from A8 + if (Subtarget.isWinABI() && (VA.getLocReg() == FrameReg)) { + Reg = MF.addLiveIn(Xtensa::A8, RC); + } else { + Reg = MF.addLiveIn(VA.getLocReg(), RC); + } + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); // If this is an 8 or 16-bit value, it has been passed promoted @@ -646,6 +665,8 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, SDValue Glue; for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) { unsigned Reg = RegsToPass[I].first; + if (Subtarget.isWinABI()) + Reg = toCallerWindow(Reg); Chain = DAG.getCopyToReg(Chain, DL, Reg, RegsToPass[I].second, Glue); Glue = Chain.getValue(1); } @@ -702,6 +723,8 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, // known live into the call. for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) { unsigned Reg = RegsToPass[I].first; + if (Subtarget.isWinABI()) + Reg = toCallerWindow(Reg); Ops.push_back(DAG.getRegister(Reg, RegsToPass[I].second.getValueType())); } @@ -710,7 +733,8 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, Ops.push_back(Glue); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); - Chain = DAG.getNode(XtensaISD::CALL, DL, NodeTys, Ops); + Chain = DAG.getNode(Subtarget.isWinABI() ? XtensaISD::CALLW : XtensaISD::CALL, + DL, NodeTys, Ops); Glue = Chain.getValue(1); // Mark the end of the call, which is glued to the call itself. @@ -721,7 +745,8 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, // Assign locations to each value returned by this call. SmallVector RetLocs; CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext()); - RetCCInfo.AnalyzeCallResult(Ins, RetCC_Xtensa); + RetCCInfo.AnalyzeCallResult(Ins, Subtarget.isWinABI() ? RetCCW_Xtensa + : RetCC_Xtensa); // Copy all of the result registers out of their specified physreg. for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) { @@ -764,7 +789,9 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, SDValue Glue; // Quick exit for void returns if (RetLocs.empty()) - return DAG.getNode(XtensaISD::RET_FLAG, DL, MVT::Other, Chain); + return DAG.getNode(Subtarget.isWinABI() ? XtensaISD::RETW_FLAG + : XtensaISD::RET_FLAG, + DL, MVT::Other, Chain); // Copy the result values into the output registers. SmallVector RetOps; @@ -791,7 +818,9 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, if (Glue.getNode()) RetOps.push_back(Glue); - return DAG.getNode(XtensaISD::RET_FLAG, DL, MVT::Other, RetOps); + return DAG.getNode(Subtarget.isWinABI() ? XtensaISD::RETW_FLAG + : XtensaISD::RET_FLAG, + DL, MVT::Other, RetOps); } SDValue XtensaTargetLowering::LowerSELECT_CC(SDValue Op, @@ -906,14 +935,14 @@ SDValue XtensaTargetLowering::LowerGlobalAddress(SDValue Op, const GlobalValue *GV = G->getGlobal(); // Check Op SDNode users - // If there are only CALL nodes, don't expand Global Address + // If there are only CALL/CALLW nodes, don't expand Global Address SDNode &OpNode = *Op.getNode(); bool Val = false; for (SDNode::use_iterator UI = OpNode.use_begin(); UI != OpNode.use_end(); ++UI) { SDNode &User = *UI.getUse().getUser(); unsigned OpCode = User.getOpcode(); - if (OpCode != XtensaISD::CALL) { + if (OpCode != XtensaISD::CALL && OpCode != XtensaISD::CALLW) { Val = true; break; } @@ -1014,7 +1043,13 @@ SDValue XtensaTargetLowering::LowerSTACKSAVE(SDValue Op, SDValue XtensaTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const { unsigned sp = Xtensa::SP; - return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op), sp, Op.getOperand(1)); + if (Subtarget.isWinABI()) { + SDValue NewSP = + DAG.getNode(XtensaISD::MOVSP, SDLoc(Op), MVT::i32, Op.getOperand(1)); + return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op), sp, NewSP); + } else { + return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op), sp, Op.getOperand(1)); + } } SDValue XtensaTargetLowering::LowerFRAMEADDR(SDValue Op, @@ -1050,7 +1085,12 @@ SDValue XtensaTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, unsigned SPReg = Xtensa::SP; SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT); SDValue NewSP = DAG.getNode(ISD::SUB, DL, VT, SP, SizeRoundUp); // Value - Chain = DAG.getCopyToReg(SP.getValue(1), DL, SPReg, NewSP); // Output chain + if (Subtarget.isWinABI()) { + SDValue NewSP1 = DAG.getNode(XtensaISD::MOVSP, DL, MVT::i32, NewSP); + Chain = DAG.getCopyToReg(SP.getValue(1), DL, SPReg, NewSP1); // Output chain + } else { + Chain = DAG.getCopyToReg(SP.getValue(1), DL, SPReg, NewSP); // Output chain + } SDValue NewVal = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32); Chain = NewVal.getValue(1); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 9d37a866cf9a4d..28cccd9d48075b 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -75,9 +75,13 @@ void XtensaInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, .addReg(Reg1, RegState::Kill); } - BuildMI(MBB, I, DL, get(Xtensa::OR), SP) - .addReg(Reg, RegState::Kill) - .addReg(Reg, RegState::Kill); + if (STI.isWinABI()) { + BuildMI(MBB, I, DL, get(Xtensa::MOVSP), SP).addReg(Reg, RegState::Kill); + } else { + BuildMI(MBB, I, DL, get(Xtensa::OR), SP) + .addReg(Reg, RegState::Kill) + .addReg(Reg, RegState::Kill); + } } void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index 011bd55c7de40e..4a736cdb26f1d8 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -34,13 +34,19 @@ XtensaRegisterInfo::XtensaRegisterInfo(const XtensaSubtarget &STI) const uint16_t * XtensaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - return CSR_Xtensa_SaveList; + if (Subtarget.isWinABI()) + return CSRWE_Xtensa_SaveList; + else + return CSR_Xtensa_SaveList; } const uint32_t * XtensaRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const { - return CSR_Xtensa_RegMask; + if (Subtarget.isWinABI()) + return CSRWE_Xtensa_RegMask; + else + return CSR_Xtensa_RegMask; } BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { @@ -174,5 +180,6 @@ bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - return TFI->hasFP(MF) ? (Xtensa::A15) : Xtensa::SP; + return TFI->hasFP(MF) ? (Subtarget.isWinABI() ? Xtensa::A7 : Xtensa::A15) + : Xtensa::SP; } From aba9d2601b8354968bc4b977ba0eccf870f402e3 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:32 +0300 Subject: [PATCH 025/261] [Xtensa] Reserve an emergency spill slot for scavenger. Reserve an emergency spill slot for the register scavenger when Windowed Call ABI is used. --- llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp | 16 ++++++++++++++++ llvm/lib/Target/Xtensa/XtensaFrameLowering.h | 3 +++ 2 files changed, 19 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index 82cc9584a31b04..53b6b7e1b01822 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -360,3 +360,19 @@ void XtensaFrameLowering::determineCalleeSaves(MachineFunction &MF, int FI = MF.getFrameInfo().CreateStackObject(Size, Alignment, false); RS->addScavengingFrameIndex(FI); } + +void XtensaFrameLowering::processFunctionBeforeFrameFinalized( + MachineFunction &MF, RegScavenger *RS) const { + const XtensaSubtarget &STI = MF.getSubtarget(); + + // In WinABI mode add register scavenging slot + // FIXME: It may be posssible to add spill slot by more optimal way + if (STI.isWinABI() && (MF.getFrameInfo().estimateStackSize(MF) > 256)) { + MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterClass &RC = Xtensa::ARRegClass; + const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); + unsigned Size = TRI.getSpillSize(RC); + Align Alignment = TRI.getSpillAlign(RC); + RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); + } +} diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h index b112f069cd618a..8eb44c4932660e 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h @@ -44,6 +44,9 @@ class XtensaFrameLowering : public TargetFrameLowering { void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override; + + void processFunctionBeforeFrameFinalized(MachineFunction &MF, + RegScavenger *RS) const override; }; } // namespace llvm From 110b1812d57fcde23f7aa0ec8453d0f0b2344f17 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:32 +0300 Subject: [PATCH 026/261] [Xtensa] Implement Boolean feature operations --- .../Disassembler/XtensaDisassembler.cpp | 19 +++++- llvm/lib/Target/Xtensa/Xtensa.td | 6 ++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 4 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 28 ++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 65 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 19 +++++- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 ++ 8 files changed, 145 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index bf36925c92c6b6..c0d3634989b943 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -75,8 +75,25 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Success; } +static const unsigned BRDecoderTable[] = { + Xtensa::B0, Xtensa::B1, Xtensa::B2, Xtensa::B3, Xtensa::B4, Xtensa::B5, + Xtensa::B6, Xtensa::B7, Xtensa::B8, Xtensa::B9, Xtensa::B10, Xtensa::B11, + Xtensa::B12, Xtensa::B13, Xtensa::B14, Xtensa::B15}; + +static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= std::size(BRDecoderTable)) + return MCDisassembler::Fail; + + unsigned Reg = BRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static const unsigned SRDecoderTable[] = { - Xtensa::SAR, 3, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73}; + Xtensa::SAR, 3, Xtensa::BREG, 4, + Xtensa ::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73}; static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 8a9f0778337faa..8e3532dac41576 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -26,6 +26,12 @@ def FeatureWindowed : SubtargetFeature<"windowed", "HasWindowed", "true" "Enable Xtensa Windowed Register option">; def HasWindowed : Predicate<"Subtarget->hasWindowed()">, AssemblerPredicate<(all_of FeatureWindowed)>; + +def FeatureBoolean : SubtargetFeature<"bool", "HasBoolean", "true", + "Enable Xtensa Boolean extension">; +def HasBoolean : Predicate<"Subtarget->hasBoolean()">, + AssemblerPredicate<(all_of FeatureBoolean)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 3d5b7f11185689..4046fe07f8c4aa 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -191,6 +191,10 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); + + if (Subtarget.hasBoolean()) { + addRegisterClass(MVT::i1, &Xtensa::BRRegClass); + } } bool XtensaTargetLowering::isOffsetFoldingLegal( diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 28cccd9d48075b..a43dabd4b8009f 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -236,6 +236,12 @@ bool XtensaInstrInfo::reverseBranchCondition( Cond[0].setImm(Xtensa::BLTZ); return false; + case Xtensa::BF: + Cond[0].setImm(Xtensa::BT); + return false; + case Xtensa::BT: + Cond[0].setImm(Xtensa::BF); + return false; default: llvm_unreachable("Invalid branch condition!"); } @@ -272,6 +278,10 @@ XtensaInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { case Xtensa::BGEZ: return MI.getOperand(1).getMBB(); + case Xtensa::BT: + case Xtensa::BF: + return MI.getOperand(1).getMBB(); + default: llvm_unreachable("Unknown branch opcode"); } @@ -307,6 +317,10 @@ bool XtensaInstrInfo::isBranchOffsetInRange(unsigned BranchOp, case Xtensa::BGEZ: BrOffset -= 4; return isIntN(12, BrOffset); + case Xtensa::BT: + case Xtensa::BF: + BrOffset -= 4; + return isIntN(8, BrOffset); default: llvm_unreachable("Unknown branch opcode"); } @@ -531,6 +545,10 @@ unsigned XtensaInstrInfo::InsertConstBranchAtInst( case Xtensa::BGEZ: MI = BuildMI(MBB, I, DL, get(BR_C)).addImm(offset).addReg(Cond[1].getReg()); break; + case Xtensa::BT: + case Xtensa::BF: + MI = BuildMI(MBB, I, DL, get(BR_C)).addImm(offset).addReg(Cond[1].getReg()); + break; default: llvm_unreachable("Invalid branch type!"); } @@ -591,6 +609,10 @@ unsigned XtensaInstrInfo::InsertBranchAtInst(MachineBasicBlock &MBB, case Xtensa::BGEZ: MI = BuildMI(MBB, I, DL, get(BR_C)).addReg(Cond[1].getReg()).addMBB(TBB); break; + case Xtensa::BT: + case Xtensa::BF: + MI = BuildMI(MBB, I, DL, get(BR_C)).addReg(Cond[1].getReg()).addMBB(TBB); + break; default: llvm_unreachable("Invalid branch type!"); } @@ -639,6 +661,12 @@ bool XtensaInstrInfo::isBranch(const MachineBasicBlock::iterator &MI, Target = &MI->getOperand(1); return true; + case Xtensa::BT: + case Xtensa::BF: + Cond[0].setImm(OpCode); + Target = &MI->getOperand(1); + return true; + default: assert(!MI->getDesc().isBranch() && "Unknown branch opcode"); return false; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index d547e7bffb28c4..560f50b59cc9da 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -838,3 +838,68 @@ def ROTW : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins imm8n_7:$imm), let s = 0x0; let t = imm{3-0}; } + +//===----------------------------------------------------------------------===// +// Boolean Instructions +//===----------------------------------------------------------------------===// + +def ALL4 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s), + "all4\t$t, $s", []>, Requires<[HasBoolean]> { + let r = 0x9; +} + +def ALL8 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s), + "all8\t$t, $s", []>, Requires<[HasBoolean]> { + let r = 0xB; +} + +def ANDB : RRR_Inst<0x00, 0x02, 0x00, (outs BR:$r), (ins BR:$s, BR:$t), + "andb\t$r, $s, $t", []>, Requires<[HasBoolean]>; +def ANDBC : RRR_Inst<0x00, 0x02, 0x01, (outs BR:$r), (ins BR:$s, BR:$t), + "andbc\t$r, $s, $t", []>, Requires<[HasBoolean]>; + +def ANY4 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s), + "any4\t$t, $s", []>, Requires<[HasBoolean]> { + let r = 0x8; +} + +def ANY8 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s), + "any8\t$t, $s", []>, Requires<[HasBoolean]> { + let r = 0xA; +} + +let isBranch = 1, isTerminator = 1, Predicates = [HasBoolean] in { + def BT : RRI8_Inst<0x06, (outs), (ins BR:$b, brtarget:$target), + "bt\t$b, $target", []> { + bits<8> target; + bits<4> b; + + let r = 0x1; + let s = b; + let t = 0x7; + let imm8 = target; + } + + def BF : RRI8_Inst<0x06, (outs), (ins BR:$b, brtarget:$target), + "bf\t$b, $target", []> { + bits<8> target; + bits<4> b; + + let r = 0x0; + let s = b; + let t = 0x7; + let imm8 = target; + } +} + +def MOVF : RRR_Inst<0x00, 0x03, 0x0C, (outs AR:$r), (ins AR:$s, BR:$t), + "movf\t$r, $s, $t", []>, Requires<[HasBoolean]>; +def MOVT : RRR_Inst<0x00, 0x03, 0x0D, (outs AR:$r), (ins AR:$s, BR:$t), + "movt\t$r, $s, $t", []>, Requires<[HasBoolean]>; + +def ORB : RRR_Inst<0x00, 0x02, 0x02, (outs BR:$r), (ins BR:$s, BR:$t), + "orb\t$r, $s, $t", []>, Requires<[HasBoolean]>; +def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t), + "orbc\t$r, $s, $t", []>, Requires<[HasBoolean]>; +def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t), + "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>; diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 9939d19ef1907c..5b87a83786ac42 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -75,8 +75,25 @@ class SRReg num, string n, list alt = []> : XtensaReg { // Shift Amount Register def SAR : SRReg<3, "sar", ["SAR","3"]>; +def BREG : SRReg<4, "br", ["BR", "4"]>; + def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>; def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>; def SR : RegisterClass<"Xtensa", [i32], 32, (add SAR, - WINDOWBASE, WINDOWSTART)>; + BREG, WINDOWBASE, WINDOWSTART)>; + +//===----------------------------------------------------------------------===// +// Boolean registers +//===----------------------------------------------------------------------===// +class BReg num, string n> : XtensaReg { + let HWEncoding{3-0} = num; +} + +foreach i = 0-15 in { + def B#i : BReg, DwarfRegNum<[i]>; +} + +// Boolean register class +def BR : RegisterClass<"Xtensa", [i1], 0, (add B0, B1, +B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15)>; diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index fe47de0f952712..df8e248dbfdf7b 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -34,6 +34,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasDensity = false; HasWindowed = false; + HasBoolean = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index aea0a9ed9b452d..cf014f5371d1ae 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -44,6 +44,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enabled Xtensa Windowed Register option bool HasWindowed; + // Enabled Xtensa Boolean extension + bool HasBoolean; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -65,6 +68,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasWindowed() const { return HasWindowed; } + bool hasBoolean() const { return HasBoolean; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; From 99e7f23e4b67ffa724f4817ef0eff4aadd8b8374 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:33 +0300 Subject: [PATCH 027/261] [Xtensa] Implement Floating-Point feature operations. Also implement User Registers class. --- .../Disassembler/XtensaDisassembler.cpp | 38 ++++ .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 2 + llvm/lib/Target/Xtensa/Xtensa.td | 5 + llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 10 + llvm/lib/Target/Xtensa/XtensaISelLowering.h | 15 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 3 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 198 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaOperators.td | 15 ++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 44 ++++ llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 + 11 files changed, 336 insertions(+) diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index c0d3634989b943..50d153204bfba4 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -75,6 +75,22 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Success; } +static const unsigned FPRDecoderTable[] = { + Xtensa::F0, Xtensa::F1, Xtensa::F2, Xtensa::F3, Xtensa::F4, Xtensa::F5, + Xtensa::F6, Xtensa::F7, Xtensa::F8, Xtensa::F9, Xtensa::F10, Xtensa::F11, + Xtensa::F12, Xtensa::F13, Xtensa::F14, Xtensa::F15}; + +static DecodeStatus DecodeFPRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= std::size(FPRDecoderTable)) + return MCDisassembler::Fail; + + unsigned Reg = FPRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static const unsigned BRDecoderTable[] = { Xtensa::B0, Xtensa::B1, Xtensa::B2, Xtensa::B3, Xtensa::B4, Xtensa::B5, Xtensa::B6, Xtensa::B7, Xtensa::B8, Xtensa::B9, Xtensa::B10, Xtensa::B11, @@ -112,6 +128,28 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Fail; } +static const unsigned URDecoderTable[] = {Xtensa::FCR, 232, Xtensa::FSR, 233}; + +static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + const llvm::MCSubtargetInfo STI = + ((const MCDisassembler *)Decoder)->getSubtargetInfo(); + + if (RegNo > 255) + return MCDisassembler::Fail; + + for (unsigned i = 0; i < std::size(URDecoderTable); i += 2) { + if (URDecoderTable[i + 1] == RegNo) { + unsigned Reg = URDecoderTable[i]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; + } + } + + return MCDisassembler::Fail; +} + static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t InstSize, MCInst &MI, diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 110e3962470705..1d96955708f93b 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -277,6 +277,8 @@ XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo, case Xtensa::L32I: case Xtensa::S32I_N: case Xtensa::L32I_N: + case Xtensa::S32F: + case Xtensa::L32F: if (Res & 0x3) { report_fatal_error("Unexpected operand value!"); } diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 8e3532dac41576..a4ed90783fdc1a 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -22,6 +22,11 @@ def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true", def HasDensity : Predicate<"Subtarget->hasDensity()">, AssemblerPredicate<(all_of FeatureDensity)>; +def FeatureSingleFloat : SubtargetFeature<"fp", "HasSingleFloat", "true", + "Enable Xtensa Single FP instructions">; +def HasSingleFloat : Predicate<"Subtarget->hasSingleFloat()">, + AssemblerPredicate<(all_of FeatureSingleFloat)>; + def FeatureWindowed : SubtargetFeature<"windowed", "HasWindowed", "true", "Enable Xtensa Windowed Register option">; def HasWindowed : Predicate<"Subtarget->hasWindowed()">, diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 4046fe07f8c4aa..d2fdd8de33d223 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -1336,6 +1336,16 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(SELECT); OPCODE(SELECT_CC); OPCODE(BR_JT); + OPCODE(CMPUO); + OPCODE(CMPUEQ); + OPCODE(CMPULE); + OPCODE(CMPULT); + OPCODE(CMPOEQ); + OPCODE(CMPOLE); + OPCODE(CMPOLT); + OPCODE(MADD); + OPCODE(MSUB); + OPCODE(MOVS); OPCODE(MOVSP); OPCODE(SHL); OPCODE(SRA); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 875cc8a943c34d..09065e463d9d5c 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -34,6 +34,21 @@ enum { // WinABI Call version CALLW, + // Floating point unordered compare conditions + CMPUEQ, + CMPULE, + CMPULT, + CMPUO, + // Floating point compare conditions + CMPOEQ, + CMPOLE, + CMPOLT, + // FP multipy-add/sub + MADD, + MSUB, + // FP move + MOVS, + MOVSP, // Wraps a TargetGlobalAddress that should be loaded using PC-relative diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index a43dabd4b8009f..e1130dd4a324f4 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -130,6 +130,9 @@ void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, if (RC == &Xtensa::ARRegClass) { LoadOpcode = Xtensa::L32I; StoreOpcode = Xtensa::S32I; + } else if (RC == &Xtensa::FPRRegClass) { + LoadOpcode = Xtensa::L32F; + StoreOpcode = Xtensa::S32F; } else llvm_unreachable("Unsupported regclass to load or store"); } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 560f50b59cc9da..e827167ee098d4 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -903,3 +903,201 @@ def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t), "orbc\t$r, $s, $t", []>, Requires<[HasBoolean]>; def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t), "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>; + +//===----------------------------------------------------------------------===// +// Floating-Point Instructions +//===----------------------------------------------------------------------===// + +class FPArith_RRR oper2, bits<4> oper1, string instrAsm, + SDPatternOperator opNode, bit isComm = 0> + : RRR_Inst<0x00, oper1, oper2, (outs FPR:$r), (ins FPR:$s, FPR:$t), + instrAsm#"\t$r, $s, $t", + [(set FPR:$r, (opNode FPR:$s, FPR:$t))]> { + let isCommutable = isComm; + let isReMaterializable = 0; + let Predicates = [HasSingleFloat]; +} + +def ADD_S : FPArith_RRR<0x00, 0x0A, "add.s", fadd, 1>; +def SUB_S : FPArith_RRR<0x01, 0x0A, "sub.s", fsub>; +def MUL_S : FPArith_RRR<0x02, 0x0A, "mul.s", fmul, 1>; + +def ABS_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "abs.s\t$r, $s", + [(set FPR:$r, (fabs FPR:$s))]> { + let t = 0x01; +} + +def NEG_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "neg.s\t$r, $s", + [(set FPR:$r, (fneg FPR:$s))]> { + let t = 0x06; +} + +def TRUNC_S : RRR_Inst<0x00, 0x0A, 0x09, (outs AR:$r), (ins FPR:$s), + "trunc.s\t$r, $s, 0", + [(set AR:$r, (fp_to_sint FPR:$s))]> { + let t = 0x00; +} + +def UTRUNC_S : RRR_Inst<0x00, 0x0A, 0x0e, (outs AR:$r), (ins FPR:$s), + "utrunc.s\t$r, $s, 0", + [(set AR:$r, (fp_to_uint FPR:$s))]> { + let t = 0x00; +} + +def FLOAT_S : RRR_Inst<0x00, 0x0A, 0x0c, (outs FPR:$r), (ins AR:$s), + "float.s\t$r, $s, 0", + [(set FPR:$r, (sint_to_fp AR:$s))]> { + let t = 0x00; +} + +def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s), + "ufloat.s\t$r, $s, 0", + [(set FPR:$r, (uint_to_fp AR:$s))]> { + let t = 0x00; +} + +def RFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs AR:$r), (ins FPR:$s), + "rfr\t$r, $s", + [(set AR:$r, (bitconvert FPR:$s))]> { + let t = 0x04; +} + +def WFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins AR:$s), + "wfr\t$r, $s", + [(set FPR:$r, (bitconvert AR:$s))]> { + let t = 0x05; +} + +// FP load instructions +let mayLoad = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { + class LoadF_RRI8 oper, string instrAsm, SDPatternOperator opNode, + ComplexPattern addrOp,Operand memOp>: RRI8_Inst<0x03, (outs FPR:$t), (ins memOp:$addr), + instrAsm#"\t$t, $addr", + [(set FPR:$t, (opNode addrOp:$addr))]> { + bits<12> addr; + + let r = oper; + let imm8{7-0} = addr{11-4}; + let s{3-0} = addr{3-0}; + } +} + +def L32F : LoadF_RRI8<0x00, "lsi", load, addr_ish4, mem32>, Requires<[]>; + +// FP store instructions +let mayStore = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { + class StoreF_RRI8 oper, string instrAsm, SDPatternOperator opNode, + ComplexPattern addrOp, Operand memOp>: RRI8_Inst<0x03, (outs), (ins FPR:$t, memOp:$addr), + instrAsm#"\t$t, $addr", + [(opNode FPR:$t, addrOp:$addr)]> { + bits<12> addr; + + let r = oper; + let imm8{7-0} = addr{11-4}; + let s{3-0} = addr{3-0}; + } +} + +def S32F : StoreF_RRI8<0x04, "ssi", store, addr_ish4, mem32>; + +// FP compare instructions +let isCompare = 1, Predicates = [HasSingleFloat] in { + class FCompare oper2, bits<4> oper1, string instrAsm, + SDPatternOperator opNode, bit isComm = 0> + : RRR_Inst<0x00, oper1, oper2, (outs BR:$r), (ins FPR:$s, FPR:$t), + instrAsm#"\t$r, $s, $t", + [(set BR:$r, (opNode FPR:$s, FPR:$t))]> { + let isCommutable = isComm; + let isReMaterializable = 0; + let Predicates = [HasSingleFloat]; + } +} + +def OEQ_S : FCompare<0x02, 0x0b, "oeq.s", Xtensa_cmpoeq, 1>; +def OLT_S : FCompare<0x04, 0x0b, "olt.s", Xtensa_cmpolt, 0>; +def OLE_S : FCompare<0x06, 0x0b, "ole.s", Xtensa_cmpole, 0>; + +def UEQ_S : FCompare<0x03, 0x0b, "ueq.s", Xtensa_cmpueq, 1>; +def ULT_S : FCompare<0x05, 0x0b, "ult.s", Xtensa_cmpult, 0>; +def ULE_S : FCompare<0x07, 0x0b, "ule.s", Xtensa_cmpule, 0>; +def UN_S : FCompare<0x01, 0x0b, "un.s", Xtensa_cmpuo, 1>; + +//FP complex operations +def MADD_S : RRR_Inst<0x00, 0x0A, 0x04, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), + "madd.s\t$r, $s, $t", + [(set FPR:$r, (Xtensa_madd FPR:$a, FPR:$s, FPR:$t))]>, + Requires<[HasSingleFloat]> { + let isCommutable = 0; + let isReMaterializable = 0; + let Constraints = "$r = $a"; +} + +def MSUB_S : RRR_Inst<0x00, 0x0A, 0x05, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), + "msub.s\t$r, $s, $t", + [(set FPR:$r, (Xtensa_msub FPR:$a, FPR:$s, FPR:$t))]>, + Requires<[HasSingleFloat]> { + let isCommutable = 0; + let isReMaterializable = 0; + let Constraints = "$r = $a"; +} + +//FP move operations +def MOV_S : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins FPR:$s), + "mov.s\t$r, $s", + [(set FPR:$r, (Xtensa_movs FPR:$s))]>, Requires<[HasSingleFloat]> +{ + let t = 0x00; +} + +def CONST_S : RRR_Inst<0x00, 0x0a, 0x0f, (outs FPR:$r), (ins uimm4:$imm), + "const.s\t$r, $imm", []>, Requires<[HasSingleFloat]> { + bits<4> imm; + + let t = 0x03; + let s = imm{3-0}; +} + +def DIV0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "div0.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x7; +} + +def MADDN_S : RRR_Inst<0x00, 0x0A, 0x06, (outs FPR:$r), (ins FPR:$s, FPR:$t), + "maddn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]> { + let isCommutable = 0; +} + +def MKDADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "mkdadj.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x0D; +} + +def MKSADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "mksadj.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x0C; +} + +def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "addexp.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x0E; +} + +def ADDEXPM_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "addexpm.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x0F; +} + +def DIVN_S : RRR_Inst<0x00, 0x0A, 0x07, (outs FPR:$r), (ins FPR:$s, FPR:$t), + "divn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; + +def NEXP01_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "nexp01.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x0B; +} + +def SQRT0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "sqrt0.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x09; +} diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index 41b2f9d72a64ae..975d6820802d96 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -25,6 +25,9 @@ def SDT_XtensaSelectCC : SDTypeProfile<1, 5, SDTCisVT<5, i32>]>; def SDT_XtensaMOVSP : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>; +def SDT_XtensaCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>; +def SDT_XtensaMADD : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, f32>]>; +def SDT_XtensaMOVS : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, f32>]>; def SDT_XtensaBrJT : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; @@ -63,6 +66,18 @@ def Xtensa_select_cc: SDNode<"XtensaISD::SELECT_CC", SDT_XtensaSelectCC, def Xtensa_movsp: SDNode<"XtensaISD::MOVSP", SDT_XtensaMOVSP, [SDNPInGlue]>; +def Xtensa_cmpoeq : SDNode<"XtensaISD::CMPOEQ", SDT_XtensaCmp, [SDNPOutGlue]>; +def Xtensa_cmpolt : SDNode<"XtensaISD::CMPOLT", SDT_XtensaCmp, [SDNPOutGlue]>; +def Xtensa_cmpole : SDNode<"XtensaISD::CMPOLE", SDT_XtensaCmp, [SDNPOutGlue]>; +def Xtensa_cmpueq : SDNode<"XtensaISD::CMPUEQ", SDT_XtensaCmp, [SDNPOutGlue]>; +def Xtensa_cmpult : SDNode<"XtensaISD::CMPULT", SDT_XtensaCmp, [SDNPOutGlue]>; +def Xtensa_cmpule : SDNode<"XtensaISD::CMPULE", SDT_XtensaCmp, [SDNPOutGlue]>; +def Xtensa_cmpuo : SDNode<"XtensaISD::CMPUO", SDT_XtensaCmp, [SDNPOutGlue]>; + +def Xtensa_madd: SDNode<"XtensaISD::MADD", SDT_XtensaMADD, [SDNPInGlue]>; +def Xtensa_msub: SDNode<"XtensaISD::MSUB", SDT_XtensaMADD, [SDNPInGlue]>; +def Xtensa_movs: SDNode<"XtensaISD::MOVS", SDT_XtensaMOVS, [SDNPInGlue]>; + def Xtensa_shl: SDNode<"XtensaISD::SHL", SDT_XtensaSHL, [SDNPInGlue]>; def Xtensa_sra: SDNode<"XtensaISD::SRA", SDT_XtensaSRA, [SDNPInGlue]>; def Xtensa_srl: SDNode<"XtensaISD::SRL", SDT_XtensaSRL, [SDNPInGlue]>; diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 5b87a83786ac42..18341287347d29 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -83,6 +83,50 @@ def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>; def SR : RegisterClass<"Xtensa", [i32], 32, (add SAR, BREG, WINDOWBASE, WINDOWSTART)>; +//===----------------------------------------------------------------------===// +// USER registers +//===----------------------------------------------------------------------===// +class URReg num, string n, list alt = []> : XtensaReg { + let HWEncoding{7-0} = num; + let AltNames = alt; +} + +def FCR : URReg<232, "fcr", ["FCR"]>; +def FSR : URReg<233, "fsr", ["FSR"]>; + +def UR : RegisterClass<"Xtensa", [i32], 32, (add FCR, FSR)>; + +//===----------------------------------------------------------------------===// +// Floating-Point registers +//===----------------------------------------------------------------------===// + +// Xtensa Floating-Point regs +class FPReg num, string n> : XtensaReg { + let HWEncoding{3-0} = num; +} + +def F0 : FPReg<0, "f0">, DwarfRegNum<[19]>; +def F1 : FPReg<1, "f1">, DwarfRegNum<[20]>; +def F2 : FPReg<2, "f2">, DwarfRegNum<[21]>; +def F3 : FPReg<3, "f3">, DwarfRegNum<[22]>; +def F4 : FPReg<4, "f4">, DwarfRegNum<[23]>; +def F5 : FPReg<5, "f5">, DwarfRegNum<[24]>; +def F6 : FPReg<6, "f6">, DwarfRegNum<[25]>; +def F7 : FPReg<7, "f7">, DwarfRegNum<[26]>; +def F8 : FPReg<8, "f8">, DwarfRegNum<[27]>; +def F9 : FPReg<9, "f9">, DwarfRegNum<[28]>; +def F10 : FPReg<10, "f10">, DwarfRegNum<[29]>; +def F11 : FPReg<11, "f11">, DwarfRegNum<[30]>; +def F12 : FPReg<12, "f12">, DwarfRegNum<[31]>; +def F13 : FPReg<13, "f13">, DwarfRegNum<[32]>; +def F14 : FPReg<14, "f14">, DwarfRegNum<[33]>; +def F15 : FPReg<15, "f15">, DwarfRegNum<[34]>; + +// Floating-Point register class with allocation order +def FPR : RegisterClass<"Xtensa", [f32], 32, (add + F8, F9, F10, F11, F12, F13, F14, F15, + F7, F6, F5, F4, F3, F2, F1, F0)>; + //===----------------------------------------------------------------------===// // Boolean registers //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index df8e248dbfdf7b..a878477726da75 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -33,6 +33,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { } HasDensity = false; + HasSingleFloat = false; HasWindowed = false; HasBoolean = false; diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index cf014f5371d1ae..3e2cbbee972fb5 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -41,6 +41,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enabled Xtensa Density extension bool HasDensity; + // Enabled Xtensa Single FP instructions + bool HasSingleFloat; + // Enabled Xtensa Windowed Register option bool HasWindowed; @@ -66,6 +69,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasDensity() const { return HasDensity; } + bool hasSingleFloat() const { return HasSingleFloat; } + bool hasWindowed() const { return HasWindowed; } bool hasBoolean() const { return HasBoolean; } From a8aed189359345657daef329bc25b902f9c59153 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:33 +0300 Subject: [PATCH 028/261] [Xtensa] Lowering Floating-Point Operations SELECT_CC/SETCC/BR_CC. Implement DAG Combine for BRCOND operation with f32 operands. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 352 +++++++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 7 + llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 17 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 16 + llvm/lib/Target/Xtensa/XtensaOperators.td | 9 + 5 files changed, 385 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index d2fdd8de33d223..65363a562f055f 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -59,6 +59,10 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, // Set up the register classes. addRegisterClass(MVT::i32, &Xtensa::ARRegClass); + if (Subtarget.hasSingleFloat()) { + addRegisterClass(MVT::f32, &Xtensa::FPRRegClass); + } + // Set up special registers. setStackPointerRegisterToSaveRestore(Xtensa::SP); @@ -94,16 +98,29 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::BR_CC, MVT::i32, Legal); setOperationAction(ISD::BR_CC, MVT::i64, Expand); + if (Subtarget.hasSingleFloat()) + setOperationAction(ISD::BR_CC, MVT::f32, Custom); + else + setOperationAction(ISD::BR_CC, MVT::f32, Expand); setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::i64, Expand); + setOperationAction(ISD::SELECT, MVT::f32, Expand); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); + if (Subtarget.hasSingleFloat()) + setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); + else + setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); setOperationAction(ISD::SETCC, MVT::i32, Custom); // folds into brcond setOperationAction(ISD::SETCC, MVT::i64, Expand); + if (Subtarget.hasSingleFloat()) + setOperationAction(ISD::SETCC, MVT::f32, Custom); + else + setOperationAction(ISD::SETCC, MVT::f32, Expand); // Expand jump table branches as address arithmetic followed by an // indirect jump. @@ -175,6 +192,83 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); + // Handle floating-point types. + for (unsigned I = MVT::FIRST_FP_VALUETYPE; I <= MVT::LAST_FP_VALUETYPE; ++I) { + MVT VT = MVT::SimpleValueType(I); + if (isTypeLegal(VT)) { + // We can use FI for FRINT. + // setOperationAction(ISD::FRINT, VT, Legal); + if (VT.getSizeInBits() == 32 && Subtarget.hasSingleFloat()) { + setOperationAction(ISD::FADD, VT, Legal); + setOperationAction(ISD::FSUB, VT, Legal); + setOperationAction(ISD::FMUL, VT, Legal); + setOperationAction(ISD::FDIV, VT, Expand); + } else { + setOperationAction(ISD::FADD, VT, Expand); + setOperationAction(ISD::FSUB, VT, Expand); + setOperationAction(ISD::FMUL, VT, Expand); + setOperationAction(ISD::FDIV, VT, Expand); + } + + // TODO: once implemented in InstrInfo uncomment + setOperationAction(ISD::FSQRT, VT, Expand); + + // No special instructions for these. + setOperationAction(ISD::FSIN, VT, Expand); + setOperationAction(ISD::FCOS, VT, Expand); + setOperationAction(ISD::FREM, VT, Expand); + setOperationAction(ISD::FABS, VT, Expand); + } + } + + // Handle floating-point types. + if (Subtarget.hasSingleFloat()) { + setOperationAction(ISD::FMA, MVT::f32, Legal); + setOperationAction(ISD::BITCAST, MVT::i32, Legal); + setOperationAction(ISD::BITCAST, MVT::f32, Legal); + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); + setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); + } else { + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::SETCC, MVT::f32, Expand); + setOperationAction(ISD::BITCAST, MVT::i32, Expand); + setOperationAction(ISD::BITCAST, MVT::f32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); + setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand); + } + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::SETCC, MVT::f64, Expand); + setOperationAction(ISD::BITCAST, MVT::i64, Expand); + setOperationAction(ISD::BITCAST, MVT::f64, Expand); + + if (Subtarget.hasSingleFloat()) { + setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); + setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); + setCondCodeAction(ISD::SETONE, MVT::f32, Expand); + setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); + setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); + + setTargetDAGCombine(ISD::BRCOND); + } + + // Needed so that we don't try to implement f128 constant loads using + // a load-and-extend of a f80 constant (in cases where the constant + // would fit in an f80). + for (MVT VT : MVT::fp_valuetypes()) + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); + + // Floating-point truncation and stores need to be done separately. + setTruncStoreAction(MVT::f64, MVT::f32, Expand); + // Implement custom stack allocations setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom); // Implement custom stack save and restore @@ -289,6 +383,50 @@ void XtensaTargetLowering::LowerAsmOperandForConstraint( TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); } +//===----------------------------------------------------------------------===// +// DAG Combine functions +//===----------------------------------------------------------------------===// + +static SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const XtensaSubtarget &Subtarget) { + if (DCI.isBeforeLegalizeOps()) { + SDValue Chain = N->getOperand(0); + + if (N->getOperand(1).getOpcode() != ISD::SETCC) + return SDValue(); + + SDLoc DL(N); + SDValue SetCC = N->getOperand(1); + SDValue Dest = N->getOperand(2); + ISD::CondCode CC = cast(SetCC->getOperand(2))->get(); + SDValue LHS = SetCC->getOperand(0); + SDValue RHS = SetCC->getOperand(1); + + if (LHS.getValueType() != MVT::i32) + return SDValue(); + + return DAG.getNode(ISD::BR_CC, DL, MVT::isVoid, Chain, DAG.getCondCode(CC), + LHS, RHS, Dest); + } + return SDValue(); +} + +SDValue XtensaTargetLowering::PerformDAGCombine(SDNode *N, + DAGCombinerInfo &DCI) const { + SelectionDAG &DAG = DCI.DAG; + unsigned Opc = N->getOpcode(); + + switch (Opc) { + default: + break; + case ISD::BRCOND: + return PerformBRCONDCombine(N, DAG, DCI, Subtarget); + } + + return SDValue(); +} + //===----------------------------------------------------------------------===// // Calling conventions //===----------------------------------------------------------------------===// @@ -827,6 +965,90 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, DL, MVT::Other, RetOps); } +static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, SDLoc dl, + SelectionDAG &DAG, int &br_code) { + // Minor optimization: if LHS is a constant, swap operands, then the + // constant can be folded into comparison. + if (LHS.getOpcode() == ISD::Constant) + std::swap(LHS, RHS); + int cmp_code = 0; + + switch (CC) { + default: + llvm_unreachable("Invalid condition!"); + break; + case ISD::SETUNE: + br_code = XtensaISD::BR_CC_F; + cmp_code = XtensaISD::CMPOEQ; + break; + case ISD::SETUO: + br_code = XtensaISD::BR_CC_T; + cmp_code = XtensaISD::CMPUO; + break; + case ISD::SETO: + br_code = XtensaISD::BR_CC_F; + cmp_code = XtensaISD::CMPUO; + break; + case ISD::SETUEQ: + br_code = XtensaISD::BR_CC_T; + cmp_code = XtensaISD::CMPUEQ; + break; + case ISD::SETULE: + br_code = XtensaISD::BR_CC_T; + cmp_code = XtensaISD::CMPULE; + break; + case ISD::SETULT: + br_code = XtensaISD::BR_CC_T; + cmp_code = XtensaISD::CMPULT; + break; + case ISD::SETEQ: + case ISD::SETOEQ: + br_code = XtensaISD::BR_CC_T; + cmp_code = XtensaISD::CMPOEQ; + break; + case ISD::SETNE: + br_code = XtensaISD::BR_CC_F; + cmp_code = XtensaISD::CMPOEQ; + break; + case ISD::SETLE: + case ISD::SETOLE: + br_code = XtensaISD::BR_CC_T; + cmp_code = XtensaISD::CMPOLE; + break; + case ISD::SETLT: + case ISD::SETOLT: + br_code = XtensaISD::BR_CC_T; + cmp_code = XtensaISD::CMPOLT; + break; + case ISD::SETGE: + br_code = XtensaISD::BR_CC_F; + cmp_code = XtensaISD::CMPOLT; + break; + case ISD::SETGT: + br_code = XtensaISD::BR_CC_F; + cmp_code = XtensaISD::CMPOLE; + break; + } + return DAG.getNode(cmp_code, dl, MVT::i1, LHS, RHS); +} + +SDValue XtensaTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); + ISD::CondCode CC = cast(Op.getOperand(1))->get(); + SDValue LHS = Op.getOperand(2); + SDValue RHS = Op.getOperand(3); + SDValue Dest = Op.getOperand(4); + SDLoc DL(Op); + + if (LHS.getValueType() == MVT::f32) { + int br_code; + SDValue Flag = EmitCMP(LHS, RHS, CC, DL, DAG, br_code); + return DAG.getNode(br_code, DL, Op.getValueType(), Chain, Flag, Dest); + } else { + llvm_unreachable("invalid BR_CC to lower"); + } +} + SDValue XtensaTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); @@ -839,8 +1061,15 @@ SDValue XtensaTargetLowering::LowerSELECT_CC(SDValue Op, SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32); // Wrap select nodes - return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueV, FalseV, - TargetCC); + if (LHS.getValueType() == MVT::f32) + return DAG.getNode(XtensaISD::SELECT_CC_FP, DL, TrueV.getValueType(), LHS, + RHS, TrueV, FalseV, TargetCC); + else if (TrueV.getValueType() == MVT::f32) + return DAG.getNode(XtensaISD::SELECT_CC_FP, DL, TrueV.getValueType(), LHS, + RHS, TrueV, FalseV, TargetCC); + else + return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueV, FalseV, + TargetCC); } SDValue XtensaTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { @@ -873,8 +1102,15 @@ SDValue XtensaTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType()); SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType()); - return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueV, FalseV, - TargetCC); + if (LHS.getValueType() == MVT::f32) + return DAG.getNode(XtensaISD::SELECT_CC_FP, DL, TrueV.getValueType(), LHS, + RHS, TrueV, FalseV, TargetCC); + else if (TrueV.getValueType() == MVT::f32) + return DAG.getNode(XtensaISD::SELECT_CC_FP, DL, TrueV.getValueType(), LHS, + RHS, TrueV, FalseV, TargetCC); + else + return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueV, FalseV, + TargetCC); } SDValue XtensaTargetLowering::LowerRETURNADDR(SDValue Op, @@ -1288,6 +1524,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerImmediateFP(Op, DAG); case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); + case ISD::BR_CC: + return LowerBR_CC(Op, DAG); case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::SELECT_CC: @@ -1335,6 +1573,9 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(PCREL_WRAPPER); OPCODE(SELECT); OPCODE(SELECT_CC); + OPCODE(SELECT_CC_FP); + OPCODE(BR_CC_T); + OPCODE(BR_CC_F); OPCODE(BR_JT); OPCODE(CMPUO); OPCODE(CMPUEQ); @@ -1401,6 +1642,66 @@ static int GetBranchKind(int Cond, bool &BrInv) { } } +static void GetFPBranchKind(int Cond, int &BrKind, int &CmpKind) { + + switch (Cond) { + default: + llvm_unreachable("Invalid condition!"); + break; + case ISD::SETUNE: + BrKind = Xtensa::BF; + CmpKind = Xtensa::OEQ_S; + break; + case ISD::SETUO: + BrKind = Xtensa::BT; + CmpKind = Xtensa::UN_S; + break; + case ISD::SETO: + BrKind = Xtensa::BF; + CmpKind = Xtensa::UN_S; + break; + case ISD::SETUEQ: + BrKind = Xtensa::BT; + CmpKind = Xtensa::UEQ_S; + break; + case ISD::SETULE: + BrKind = Xtensa::BT; + CmpKind = Xtensa::ULE_S; + break; + case ISD::SETULT: + BrKind = Xtensa::BT; + CmpKind = Xtensa::ULT_S; + break; + case ISD::SETEQ: + case ISD::SETOEQ: + BrKind = Xtensa::BT; + CmpKind = Xtensa::OEQ_S; + break; + case ISD::SETNE: + BrKind = Xtensa::BF; + CmpKind = Xtensa::OEQ_S; + break; + case ISD::SETLE: + case ISD::SETOLE: + BrKind = Xtensa::BT; + CmpKind = Xtensa::OLE_S; + break; + case ISD::SETLT: + case ISD::SETOLT: + BrKind = Xtensa::BT; + CmpKind = Xtensa::OLT_S; + break; + case ISD::SETGE: + BrKind = Xtensa::BF; + CmpKind = Xtensa::OLT_S; + break; + case ISD::SETGT: + BrKind = Xtensa::BF; + CmpKind = Xtensa::OLE_S; + break; + } +} + MachineBasicBlock * XtensaTargetLowering::emitSelectCC(MachineInstr &MI, MachineBasicBlock *BB) const { @@ -1443,19 +1744,35 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - bool BrInv = false; - int BrKind = GetBranchKind(Cond.getImm(), BrInv); - if (BrInv) { - BuildMI(BB, DL, TII.get(BrKind)) - .addReg(RHS.getReg()) + if ((MI.getOpcode() == Xtensa::SELECT_CC_FP_FP) || + (MI.getOpcode() == Xtensa::SELECT_CC_FP_INT)) { + int BrKind = 0; + int CmpKind = 0; + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &RegInfo = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i1); + unsigned b = RegInfo.createVirtualRegister(RC); + GetFPBranchKind(Cond.getImm(), BrKind, CmpKind); + BuildMI(BB, DL, TII.get(CmpKind), b) .addReg(LHS.getReg()) - .addMBB(sinkMBB); + .addReg(RHS.getReg()); + BuildMI(BB, DL, TII.get(BrKind)).addReg(b).addMBB(sinkMBB); } else { - BuildMI(BB, DL, TII.get(BrKind)) - .addReg(LHS.getReg()) - .addReg(RHS.getReg()) - .addMBB(sinkMBB); + bool BrInv = false; + int BrKind = GetBranchKind(Cond.getImm(), BrInv); + if (BrInv) { + BuildMI(BB, DL, TII.get(BrKind)) + .addReg(RHS.getReg()) + .addReg(LHS.getReg()) + .addMBB(sinkMBB); + } else { + BuildMI(BB, DL, TII.get(BrKind)) + .addReg(LHS.getReg()) + .addReg(RHS.getReg()) + .addMBB(sinkMBB); + } } + // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB @@ -1487,6 +1804,9 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( DebugLoc DL = MI.getDebugLoc(); switch (MI.getOpcode()) { + case Xtensa::SELECT_CC_FP_FP: + case Xtensa::SELECT_CC_FP_INT: + case Xtensa::SELECT_CC_INT_FP: case Xtensa::SELECT: return emitSelectCC(MI, MBB); @@ -1548,11 +1868,13 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( case Xtensa::S16I: case Xtensa::S32I: case Xtensa::S32I_N: + case Xtensa::S32F: case Xtensa::L8UI: case Xtensa::L16SI: case Xtensa::L16UI: case Xtensa::L32I: - case Xtensa::L32I_N: { + case Xtensa::L32I_N: + case Xtensa::L32F: { const MachineMemOperand &MMO = **MI.memoperands_begin(); if (MMO.isVolatile()) { BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW)); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 09065e463d9d5c..28dfe34d1c8bb6 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -25,6 +25,9 @@ namespace XtensaISD { enum { FIRST_NUMBER = ISD::BUILTIN_OP_END, + BR_CC_T, + BR_CC_F, + BR_JT, // Calls a function. Operand 0 is the chain operand and operand 1 @@ -66,6 +69,7 @@ enum { // Operand 3 is the flag operand. SELECT, SELECT_CC, + SELECT_CC_FP, // Shift SHL, @@ -116,6 +120,8 @@ class XtensaTargetLowering : public TargetLowering { std::vector &Ops, SelectionDAG &DAG) const override; + SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; + SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, @@ -150,6 +156,7 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; + SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index e1130dd4a324f4..e957609c337dc5 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -88,13 +88,28 @@ void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const { + unsigned Opcode; + // when we are copying a phys reg we want the bits for fp - if (Xtensa::ARRegClass.contains(DestReg, SrcReg)) + if (Xtensa::ARRegClass.contains(DestReg, SrcReg)) { BuildMI(MBB, MBBI, DL, get(Xtensa::OR), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)) .addReg(SrcReg, getKillRegState(KillSrc)); + return; + } else if (STI.hasSingleFloat() && Xtensa::FPRRegClass.contains(SrcReg) && + Xtensa::FPRRegClass.contains(DestReg)) + Opcode = Xtensa::MOV_S; + else if (STI.hasSingleFloat() && Xtensa::FPRRegClass.contains(SrcReg) && + Xtensa::ARRegClass.contains(DestReg)) + Opcode = Xtensa::RFR; + else if (STI.hasSingleFloat() && Xtensa::ARRegClass.contains(SrcReg) && + Xtensa::FPRRegClass.contains(DestReg)) + Opcode = Xtensa::WFR; else llvm_unreachable("Impossible reg-to-reg copy"); + + BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); } void XtensaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index e827167ee098d4..add781633b5c06 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -904,6 +904,9 @@ def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t), def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t), "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>; +def : Pat<(Xtensa_brcc_t BR:$b, bb:$target), (BT BR:$b, bb:$target)>; +def : Pat<(Xtensa_brcc_f BR:$b, bb:$target), (BF BR:$b, bb:$target)>; + //===----------------------------------------------------------------------===// // Floating-Point Instructions //===----------------------------------------------------------------------===// @@ -1101,3 +1104,16 @@ def SQRT0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "sqrt0.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x09; } + +// FP select operations +let usesCustomInserter = 1 in { + def SELECT_CC_FP_INT : Pseudo<(outs AR:$dst), (ins FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, i32imm:$cond), + "!select_cc_fp_int $dst, $lhs, $rhs, $t, $f, $cond", + [(set AR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, imm:$cond))]>; + def SELECT_CC_INT_FP : Pseudo<(outs FPR:$dst), (ins AR:$lhs, AR:$rhs, FPR:$t, FPR:$f, i32imm:$cond), + "!select_cc_int_fp $dst, $lhs, $rhs, $t, $f, $cond", + [(set FPR:$dst, (Xtensa_select_cc_fp AR:$lhs, AR:$rhs, FPR:$t, FPR:$f, imm:$cond))]>; + def SELECT_CC_FP_FP : Pseudo<(outs FPR:$dst), (ins FPR:$lhs, FPR:$rhs, FPR:$t, FPR:$f, i32imm:$cond), + "!select_cc_fp_fp $dst, $lhs, $rhs, $t, $f, $cond", + [(set FPR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, FPR:$t, FPR:$f, imm:$cond))]>; +} diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index 975d6820802d96..fcb82e400a39fe 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -25,9 +25,11 @@ def SDT_XtensaSelectCC : SDTypeProfile<1, 5, SDTCisVT<5, i32>]>; def SDT_XtensaMOVSP : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>; +def SDT_XtensaBrCC : SDTypeProfile<0, 2, [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]>; def SDT_XtensaCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>; def SDT_XtensaMADD : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, f32>]>; def SDT_XtensaMOVS : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, f32>]>; +def SDT_XtensaSelectCCFP : SDTypeProfile<1, 5, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>; def SDT_XtensaBrJT : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; @@ -62,10 +64,17 @@ def Xtensa_pcrel_wrapper: SDNode<"XtensaISD::PCREL_WRAPPER", SDT_XtensaWrapPtr, def Xtensa_select : SDNode<"XtensaISD::SELECT", SDTSelect>; def Xtensa_select_cc: SDNode<"XtensaISD::SELECT_CC", SDT_XtensaSelectCC, [SDNPInGlue]>; +def Xtensa_select_cc_fp: SDNode<"XtensaISD::SELECT_CC_FP", SDT_XtensaSelectCCFP, + [SDNPInGlue]>; def Xtensa_movsp: SDNode<"XtensaISD::MOVSP", SDT_XtensaMOVSP, [SDNPInGlue]>; +def Xtensa_brcc_t : SDNode<"XtensaISD::BR_CC_T", SDT_XtensaBrCC, + [SDNPHasChain, SDNPInGlue]>; +def Xtensa_brcc_f : SDNode<"XtensaISD::BR_CC_F", SDT_XtensaBrCC, + [SDNPHasChain, SDNPInGlue]>; + def Xtensa_cmpoeq : SDNode<"XtensaISD::CMPOEQ", SDT_XtensaCmp, [SDNPOutGlue]>; def Xtensa_cmpolt : SDNode<"XtensaISD::CMPOLT", SDT_XtensaCmp, [SDNPOutGlue]>; def Xtensa_cmpole : SDNode<"XtensaISD::CMPOLE", SDT_XtensaCmp, [SDNPOutGlue]>; From fbb9a9509724b26a33665e9dcdf11d966fa2980b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:34 +0300 Subject: [PATCH 029/261] [Xtensa] Implement DAG Combine for FADD and FSUB operations. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 72 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 3 + 2 files changed, 75 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 65363a562f055f..09d275c7e145bb 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -257,6 +257,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); + setTargetDAGCombine(ISD::FADD); + setTargetDAGCombine(ISD::FSUB); setTargetDAGCombine(ISD::BRCOND); } @@ -291,6 +293,21 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, } } +bool XtensaTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, + EVT VT) const { + if (!VT.isSimple()) + return false; + + switch (VT.getSimpleVT().SimpleTy) { + case MVT::f32: + return Subtarget.hasSingleFloat(); + default: + break; + } + + return false; +} + bool XtensaTargetLowering::isOffsetFoldingLegal( const GlobalAddressSDNode *GA) const { // The Xtensa target isn't yet aware of offsets. @@ -387,6 +404,57 @@ void XtensaTargetLowering::LowerAsmOperandForConstraint( // DAG Combine functions //===----------------------------------------------------------------------===// +static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, + const XtensaSubtarget &Subtarget) { + if (ROOTNode->getOperand(0).getValueType() != MVT::f32) + return SDValue(); + + if (ROOTNode->getOperand(0).getOpcode() != ISD::FMUL && + ROOTNode->getOperand(1).getOpcode() != ISD::FMUL) + return SDValue(); + + SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::FMUL + ? ROOTNode->getOperand(0) + : ROOTNode->getOperand(1); + + SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::FMUL + ? ROOTNode->getOperand(1) + : ROOTNode->getOperand(0); + + if (!Mult.hasOneUse()) + return SDValue(); + + SDLoc DL(ROOTNode); + + bool IsAdd = ROOTNode->getOpcode() == ISD::FADD; + unsigned Opcode = IsAdd ? XtensaISD::MADD : XtensaISD::MSUB; + SDValue MAddOps[3] = {AddOperand, Mult->getOperand(0), Mult->getOperand(1)}; + EVT VTs[3] = {MVT::f32, MVT::f32, MVT::f32}; + SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); + + return MAdd; +} + +static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const XtensaSubtarget &Subtarget) { + if (DCI.isBeforeLegalizeOps()) { + if (Subtarget.hasSingleFloat() && N->getValueType(0) == MVT::f32) + return performMADD_MSUBCombine(N, DAG, Subtarget); + } + return SDValue(); +} + +static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const XtensaSubtarget &Subtarget) { + if (DCI.isBeforeLegalizeOps()) { + if (Subtarget.hasSingleFloat() && N->getValueType(0) == MVT::f32) + return performMADD_MSUBCombine(N, DAG, Subtarget); + } + return SDValue(); +} + static SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const XtensaSubtarget &Subtarget) { @@ -420,6 +488,10 @@ SDValue XtensaTargetLowering::PerformDAGCombine(SDNode *N, switch (Opc) { default: break; + case ISD::FADD: + return performADDCombine(N, DAG, DCI, Subtarget); + case ISD::FSUB: + return performSUBCombine(N, DAG, DCI, Subtarget); case ISD::BRCOND: return PerformBRCONDCombine(N, DAG, DCI, Subtarget); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 28dfe34d1c8bb6..557bc3804935b9 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -99,6 +99,9 @@ class XtensaTargetLowering : public TargetLowering { return VT.changeVectorElementTypeToInteger(); } + bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, + EVT VT) const override; + bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; From aa8b304e5d41c00392674f5c313ed1c126a33bb3 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:34 +0300 Subject: [PATCH 030/261] [Xtensa] Implement Loop, SEXT and NSA features. --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 5 ++ .../Disassembler/XtensaDisassembler.cpp | 13 ++++- .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 11 ++++ .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 1 + .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 20 ++++++- llvm/lib/Target/Xtensa/Xtensa.td | 15 +++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 18 ++++-- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 56 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaOperands.td | 8 +++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 8 ++- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 3 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 15 +++++ 12 files changed, 163 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 9b59c95dd24ccf..f2b2bcc877c815 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -250,6 +250,8 @@ struct XtensaOperand : public MCParsedAsmOperand { return false; } + bool isseimm7_22() const { return isImm(7, 22); } + /// getStartLoc - Gets location of the first token of this operand SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Gets location of the last token of this operand @@ -452,6 +454,9 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_Invalidentry_imm12: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [0, 32760]"); + case Match_Invalidseimm7_22: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [7, 22]"); } report_fatal_error("Unknown match type detected!"); diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 50d153204bfba4..0e684250b7b319 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -108,8 +108,9 @@ static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo, } static const unsigned SRDecoderTable[] = { - Xtensa::SAR, 3, Xtensa::BREG, 4, - Xtensa ::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73}; + Xtensa::LBEG, 0, Xtensa::LEND, 1, Xtensa::LCOUNT, 2, + Xtensa::SAR, 3, Xtensa::BREG, 4, Xtensa ::WINDOWBASE, 72, + Xtensa::WINDOWSTART, 73}; static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, @@ -302,6 +303,14 @@ static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeSeimm7_22Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<4>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm + 7)); + return MCDisassembler::Success; +} + static int64_t TableB4const[16] = {-1, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256}; static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm, diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index d1308ed56aa003..89343d203e9eba 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -413,3 +413,14 @@ void XtensaInstPrinter::printB4constu_AsmOperand(const MCInst *MI, int OpNum, } else printOperand(MI, OpNum, O); } + +void XtensaInstPrinter::printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 7 && Value <= 22) && + "Invalid argument, value must be in range <7,22>"); + O << Value; + } else + printOperand(MI, OpNum, O); +} diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index f8a9f592e01101..f6858b383cbf16 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -71,6 +71,7 @@ class XtensaInstPrinter : public MCInstPrinter { void printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 1d96955708f93b..eadcae39255d59 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -134,6 +134,10 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { uint32_t getB4constuOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + + uint32_t getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; }; } // namespace @@ -285,7 +289,7 @@ XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo, Res >>= 2; break; } - + switch (MI.getOpcode()) { case Xtensa::S32I_N: case Xtensa::L32I_N: @@ -551,4 +555,18 @@ XtensaMCCodeEmitter::getB4constuOpValue(const MCInst &MI, unsigned OpNo, return Res; } + +uint32_t +XtensaMCCodeEmitter::getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint32_t res = static_cast(MO.getImm()); + + res -= 7; + assert(((res & 0xf) == res) && "Unexpected operand value!"); + + return res; +} + #include "XtensaGenMCCodeEmitter.inc" diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index a4ed90783fdc1a..4ab0786e16d73f 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -37,6 +37,21 @@ def FeatureBoolean : SubtargetFeature<"bool", "HasBoolean", "true", def HasBoolean : Predicate<"Subtarget->hasBoolean()">, AssemblerPredicate<(all_of FeatureBoolean)>; +def FeatureLoop : SubtargetFeature<"loop", "HasLoop", "true", + "Enable Xtensa Loop extension">; +def HasLoop : Predicate<"Subtarget->hasLoop()">, + AssemblerPredicate<(all_of FeatureLoop)>; + +def FeatureSEXT : SubtargetFeature<"sext", "HasSEXT", "true", + "Enable Xtensa Sign Extend option">; +def HasSEXT : Predicate<"Subtarget->hasSEXT()">, + AssemblerPredicate<(all_of FeatureSEXT)>; + +def FeatureNSA : SubtargetFeature<"nsa", "HasNSA", "true", + "Enable Xtensa NSA option">; +def HasNSA : Predicate<"Subtarget->hasNSA()">, + AssemblerPredicate<(all_of FeatureNSA)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 09d275c7e145bb..ef8a25f096ea9b 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -1928,14 +1928,22 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( BuildMI(*MBB, MI, DL, TII.get(Xtensa::L8UI), R1).add(Op1).add(Op2); - unsigned R2 = MRI.createVirtualRegister(RC); - BuildMI(*MBB, MI, DL, TII.get(Xtensa::SLLI), R2).addReg(R1).addImm(24); - BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRAI), R.getReg()) - .addReg(R2) - .addImm(24); + if (Subtarget.hasSEXT()) { + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SEXT), R.getReg()) + .addReg(R1) + .addImm(7); + } else { + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SLLI), R2).addReg(R1).addImm(24); + BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRAI), R.getReg()) + .addReg(R2) + .addImm(24); + } + MI.eraseFromParent(); return MBB; } + case Xtensa::S8I: case Xtensa::S16I: case Xtensa::S32I: diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index add781633b5c06..840b34c621c0f3 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1117,3 +1117,59 @@ let usesCustomInserter = 1 in { "!select_cc_fp_fp $dst, $lhs, $rhs, $t, $f, $cond", [(set FPR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, FPR:$t, FPR:$f, imm:$cond))]>; } + +//===----------------------------------------------------------------------===// +// Loop Instructions +//===----------------------------------------------------------------------===// + +def LOOP : RRI8_Inst<0x06, (outs), (ins AR:$s, mem8:$uimm8), + "loop\t$$s, $uimm8", []>, Requires<[HasLoop]> { + bits<8> uimm8; + + let r = 0x08; + let t = 0x07; + let imm8 = uimm8; +} + +def LOOPGTZ : RRI8_Inst<0x06, (outs), (ins AR:$s, mem8:$uimm8), + "loopgtz\t$$s, $uimm8", []>, Requires<[HasLoop]> { + bits<8> uimm8; + + let r = 0x0A; + let t = 0x07; + let imm8 = uimm8; +} + +def LOOPNEZ : RRI8_Inst<0x06, (outs), (ins AR:$s, mem8:$uimm8), + "loopnez\t$$s, $uimm8", []>, Requires<[HasLoop]> { + bits<8> uimm8; + + let r = 0x09; + let t = 0x07; + let imm8 = uimm8; +} + +//===----------------------------------------------------------------------===// +// SEXT Instructions +//===----------------------------------------------------------------------===// + +def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, seimm7_22:$imm), + "sext\t$r, $s, $imm", []>, Requires<[HasSEXT]> { + bits<4> imm; + + let t = imm; +} + +//===----------------------------------------------------------------------===// +// NSA Instructions +//===----------------------------------------------------------------------===// + +def NSA : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s), + "nsa\t$t, $s", []>, Requires<[HasNSA]> { + let r = 0xE; +} + +def NSAU : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s), + "nsau\t$t, $s", []>, Requires<[HasNSA]> { + let r = 0xF; +} diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 47946596282ad9..1ea3eeab0e3636 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -167,6 +167,14 @@ def b4constu: Immediate; +def seimm7_22: Immediate= 7 && Imm <= 22; }], "Seimm7_22_AsmOperand"> { + let EncoderMethod = "getSeimm7_22OpValue"; + let DecoderMethod = "decodeSeimm7_22Operand"; +} + //===----------------------------------------------------------------------===// // Memory address operands //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 18341287347d29..d7fbdcff09b988 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -72,6 +72,10 @@ class SRReg num, string n, list alt = []> : XtensaReg { let AltNames = alt; } +def LBEG : SRReg<0, "lbeg", ["LBEG", "0"]>; +def LEND : SRReg<1, "lend", ["LEND", "1"]>; +def LCOUNT : SRReg<2, "lcount", ["LCOUNT", "2"]>; + // Shift Amount Register def SAR : SRReg<3, "sar", ["SAR","3"]>; @@ -80,8 +84,8 @@ def BREG : SRReg<4, "br", ["BR", "4"]>; def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>; def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>; -def SR : RegisterClass<"Xtensa", [i32], 32, (add SAR, - BREG, WINDOWBASE, WINDOWSTART)>; +def SR : RegisterClass<"Xtensa", [i32], 32, (add LBEG, LEND, LCOUNT, + SAR, BREG, WINDOWBASE, WINDOWSTART)>; //===----------------------------------------------------------------------===// // USER registers diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index a878477726da75..d6cc451e0268a5 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -36,6 +36,9 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasSingleFloat = false; HasWindowed = false; HasBoolean = false; + HasLoop = false; + HasSEXT = false; + HasNSA = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index 3e2cbbee972fb5..ba619caffc0f5f 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -50,6 +50,15 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enabled Xtensa Boolean extension bool HasBoolean; + // Enabled Xtensa Loop extension + bool HasLoop; + + // Enable Xtensa Sign Extend option + bool HasSEXT; + + // Enable Xtensa NSA option + bool HasNSA; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -75,6 +84,12 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasBoolean() const { return HasBoolean; } + bool hasLoop() const { return HasLoop; } + + bool hasSEXT() const { return HasSEXT; } + + bool hasNSA() const { return HasNSA; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; From adf9feece50003fed711b72a14541e980539ce5b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:35 +0300 Subject: [PATCH 031/261] [Xtensa] Implement Mul32, Mul32High and Div32 features. --- llvm/lib/Target/Xtensa/Xtensa.td | 15 ++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 30 ++++++++++++++----- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 17 +++++++++++ llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 3 ++ llvm/lib/Target/Xtensa/XtensaSubtarget.h | 15 ++++++++++ 5 files changed, 73 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 4ab0786e16d73f..5555d73ca4be41 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -52,6 +52,21 @@ def FeatureNSA : SubtargetFeature<"nsa", "HasNSA", "true", def HasNSA : Predicate<"Subtarget->hasNSA()">, AssemblerPredicate<(all_of FeatureNSA)>; +def FeatureMul32 : SubtargetFeature<"mul32", "HasMul32", "true", + "Enable Xtensa Mul32 option">; +def HasMul32 : Predicate<"Subtarget->hasMul32()">, + AssemblerPredicate<(all_of FeatureMul32)>; + +def FeatureMul32High : SubtargetFeature<"mul32high", "HasMul32High", "true", + "Enable Xtensa Mul32High option">; +def HasMul32High : Predicate<"Subtarget->hasMul32High()">, + AssemblerPredicate<(all_of FeatureMul32High)>; + +def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true", + "Enable Xtensa Div32 option">; +def HasDiv32 : Predicate<"Subtarget->hasDiv32()">, + AssemblerPredicate<(all_of FeatureDiv32)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index ef8a25f096ea9b..eb9fb025161ada 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -140,17 +140,33 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, } } - setOperationAction(ISD::MUL, MVT::i32, Expand); - setOperationAction(ISD::MULHU, MVT::i32, Expand); - setOperationAction(ISD::MULHS, MVT::i32, Expand); + if (Subtarget.hasMul32()) + setOperationAction(ISD::MUL, MVT::i32, Legal); + else + setOperationAction(ISD::MUL, MVT::i32, Expand); + + if (Subtarget.hasMul32High()) { + setOperationAction(ISD::MULHU, MVT::i32, Legal); + setOperationAction(ISD::MULHS, MVT::i32, Legal); + } else { + setOperationAction(ISD::MULHU, MVT::i32, Expand); + setOperationAction(ISD::MULHS, MVT::i32, Expand); + } setOperationAction(ISD::MUL, MVT::i64, Expand); setOperationAction(ISD::MULHS, MVT::i64, Expand); setOperationAction(ISD::MULHU, MVT::i64, Expand); - setOperationAction(ISD::SDIV, MVT::i32, Expand); - setOperationAction(ISD::UDIV, MVT::i32, Expand); - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::UREM, MVT::i32, Expand); + if (Subtarget.hasDiv32()) { + setOperationAction(ISD::SDIV, MVT::i32, Legal); + setOperationAction(ISD::UDIV, MVT::i32, Legal); + setOperationAction(ISD::SREM, MVT::i32, Legal); + setOperationAction(ISD::UREM, MVT::i32, Legal); + } else { + setOperationAction(ISD::SDIV, MVT::i32, Expand); + setOperationAction(ISD::UDIV, MVT::i32, Expand); + setOperationAction(ISD::SREM, MVT::i32, Expand); + setOperationAction(ISD::UREM, MVT::i32, Expand); + } setOperationAction(ISD::SDIV, MVT::i64, Expand); setOperationAction(ISD::UDIV, MVT::i64, Expand); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 840b34c621c0f3..e12f4a632d10ec 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1173,3 +1173,20 @@ def NSAU : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s), "nsau\t$t, $s", []>, Requires<[HasNSA]> { let r = 0xF; } + +//===----------------------------------------------------------------------===// +// Mul32 Instructions +//===----------------------------------------------------------------------===// + +def MULL : ArithLogic_RRR<0x08, 0x02, "mull", mul, 1>, Requires<[HasMul32]>; +def MULUH : ArithLogic_RRR<0x0A, 0x02, "muluh", mulhu, 1>, Requires<[HasMul32High]>; +def MULSH : ArithLogic_RRR<0x0B, 0x02, "mulsh", mulhs, 1>, Requires<[HasMul32High]>; + +//===----------------------------------------------------------------------===// +// Div32 Instructions +//===----------------------------------------------------------------------===// + +def QUOS : ArithLogic_RRR<0x0D, 0x02, "quos", sdiv>, Requires<[HasDiv32]>; +def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>, Requires<[HasDiv32]>; +def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>, Requires<[HasDiv32]>; +def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>, Requires<[HasDiv32]>; diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index d6cc451e0268a5..03fd8cb99cb9f7 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -39,6 +39,9 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasLoop = false; HasSEXT = false; HasNSA = false; + HasMul32 = false; + HasMul32High = false; + HasDiv32 = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index ba619caffc0f5f..f129ddbdb893bb 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -59,6 +59,15 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa NSA option bool HasNSA; + // Enable Xtensa Mul32 option + bool HasMul32; + + // Enable Xtensa Mul32High option + bool HasMul32High; + + // Enable Xtensa Div32 option + bool HasDiv32; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -90,6 +99,12 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasNSA() const { return HasNSA; } + bool hasMul32() const { return HasMul32; } + + bool hasMul32High() const { return HasMul32High; } + + bool hasDiv32() const { return HasDiv32; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; From 1bf68de86621583599c9cd86f032e65fbdc3f360 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:35 +0300 Subject: [PATCH 032/261] [Xtensa] Implement Mac16 feature and operations. --- .../Disassembler/XtensaDisassembler.cpp | 47 ++- llvm/lib/Target/Xtensa/Xtensa.td | 5 + llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td | 353 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 5 + llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 12 +- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 + llvm/test/MC/Xtensa/xtensa-valid-mac16.s | 234 ++++++++++++ 8 files changed, 658 insertions(+), 4 deletions(-) create mode 100644 llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-mac16.s diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 0e684250b7b319..5abb901f16f63c 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -107,10 +107,51 @@ static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Success; } +static const unsigned MRDecoderTable[] = {Xtensa::M0, Xtensa::M1, Xtensa::M2, + Xtensa::M3}; + +static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= std::size(MRDecoderTable)) + return MCDisassembler::Fail; + + unsigned Reg = MRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static const unsigned MR01DecoderTable[] = {Xtensa::M0, Xtensa::M1}; + +static DecodeStatus DecodeMR01RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 2) + return MCDisassembler::Fail; + + unsigned Reg = MR01DecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static const unsigned MR23DecoderTable[] = {Xtensa::M2, Xtensa::M3}; + +static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if ((RegNo < 2) || (RegNo > 3)) + return MCDisassembler::Fail; + + unsigned Reg = MR23DecoderTable[RegNo - 2]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static const unsigned SRDecoderTable[] = { - Xtensa::LBEG, 0, Xtensa::LEND, 1, Xtensa::LCOUNT, 2, - Xtensa::SAR, 3, Xtensa::BREG, 4, Xtensa ::WINDOWBASE, 72, - Xtensa::WINDOWSTART, 73}; + Xtensa::LEND, 1, Xtensa::LCOUNT, 2, Xtensa::SAR, 3, + Xtensa::BREG, 4, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17, + Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34, + Xtensa::M3, 35, Xtensa ::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73}; static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 5555d73ca4be41..5468b91e24940c 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -67,6 +67,11 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true", def HasDiv32 : Predicate<"Subtarget->hasDiv32()">, AssemblerPredicate<(all_of FeatureDiv32)>; +def FeatureMAC16 : SubtargetFeature<"mac16", "HasMAC16", "true", + "Enable Xtensa MAC16 instructions">; +def HasMAC16 : Predicate<"Subtarget->hasMAC16()">, + AssemblerPredicate<(all_of FeatureMAC16)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td new file mode 100644 index 00000000000000..d80df463206432 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td @@ -0,0 +1,353 @@ +//===- XtensaDSPInstrInfo.td - Xtensa Target Description ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the Xtensa DSP instructions in TableGen format. +// +//===----------------------------------------------------------------------===// + +// Multiply +class UMUL_AA oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t), + instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> { + let r = 0; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def UMUL_AA_LL : UMUL_AA<0x00, "umul.aa.ll">; +def UMUL_AA_HL : UMUL_AA<0x01, "umul.aa.hl">; +def UMUL_AA_LH : UMUL_AA<0x02, "umul.aa.lh">; +def UMUL_AA_HH : UMUL_AA<0x03, "umul.aa.hh">; + +class MUL_AA oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t), + instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> { + let r = 0; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MUL_AA_LL : MUL_AA<0x04, "mul.aa.ll">; +def MUL_AA_HL : MUL_AA<0x05, "mul.aa.hl">; +def MUL_AA_LH : MUL_AA<0x06, "mul.aa.lh">; +def MUL_AA_HH : MUL_AA<0x07, "mul.aa.hh">; + +class MUL_AD oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y), + instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> { + bits<2> y; + + let r = 0; + let t{3} = 0; + let t{2} = y{0}; + let t{1-0} = 0; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MUL_AD_LL : MUL_AD<0x04, "mul.ad.ll">; +def MUL_AD_HL : MUL_AD<0x05, "mul.ad.hl">; +def MUL_AD_LH : MUL_AD<0x06, "mul.ad.lh">; +def MUL_AD_HH : MUL_AD<0x07, "mul.ad.hh">; + +class MUL_DA oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t), + instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> { + bits<2> x; + + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = 0; + let s = 0; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MUL_DA_LL : MUL_DA<0x04, "mul.da.ll">; +def MUL_DA_HL : MUL_DA<0x05, "mul.da.hl">; +def MUL_DA_LH : MUL_DA<0x06, "mul.da.lh">; +def MUL_DA_HH : MUL_DA<0x07, "mul.da.hh">; + +class MUL_DD oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y), + instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> { + bits<2> x; + bits<2> y; + + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = 0; + let s = 0; + let t{3} = 0; + let t{2} = y{0}; + let t{1-0} = 0; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MUL_DD_LL : MUL_DD<0x04, "mul.dd.ll">; +def MUL_DD_HL : MUL_DD<0x05, "mul.dd.hl">; +def MUL_DD_LH : MUL_DD<0x06, "mul.dd.lh">; +def MUL_DD_HH : MUL_DD<0x07, "mul.dd.hh">; + +class MULA_AA oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t), + instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> { + let r = 0; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULA_AA_LL : MULA_AA<0x08, "mula.aa.ll">; +def MULA_AA_HL : MULA_AA<0x09, "mula.aa.hl">; +def MULA_AA_LH : MULA_AA<0x0A, "mula.aa.lh">; +def MULA_AA_HH : MULA_AA<0x0B, "mula.aa.hh">; + +class MULA_AD oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y), + instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> { + bits<2> y; + + let r = 0; + let t{3} = 0; + let t{2} = y{0}; + let t{1-0} = 0; + + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULA_AD_LL : MULA_AD<0x08, "mula.ad.ll">; +def MULA_AD_HL : MULA_AD<0x09, "mula.ad.hl">; +def MULA_AD_LH : MULA_AD<0x0A, "mula.ad.lh">; +def MULA_AD_HH : MULA_AD<0x0B, "mula.ad.hh">; + +class MULA_DA oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t), + instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> { + bits<2> x; + + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = 0; + let s = 0; + + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULA_DA_LL : MULA_DA<0x08, "mula.da.ll">; +def MULA_DA_HL : MULA_DA<0x09, "mula.da.hl">; +def MULA_DA_LH : MULA_DA<0x0A, "mula.da.lh">; +def MULA_DA_HH : MULA_DA<0x0B, "mula.da.hh">; + +class MULA_DD oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y), + instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> { + bits<2> x; + bits<2> y; + + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = 0; + let s = 0; + let t{3} = 0; + let t{2} = y{0}; + let t{1-0} = 0; + + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULA_DD_LL : MULA_DD<0x08, "mula.dd.ll">; +def MULA_DD_HL : MULA_DD<0x09, "mula.dd.hl">; +def MULA_DD_LH : MULA_DD<0x0A, "mula.dd.lh">; +def MULA_DD_HH : MULA_DD<0x0B, "mula.dd.hh">; + +class MULS_AA oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t), + instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> { + let r = 0; + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULS_AA_LL : MULS_AA<0x0C, "muls.aa.ll">; +def MULS_AA_HL : MULS_AA<0x0D, "muls.aa.hl">; +def MULS_AA_LH : MULS_AA<0x0E, "muls.aa.lh">; +def MULS_AA_HH : MULS_AA<0x0F, "muls.aa.hh">; + +class MULS_AD oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y), + instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> { + bits<2> y; + + let r = 0; + let t{3} = 0; + let t{2} = y{0}; + let t{1-0} = 0; + + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULS_AD_LL : MULS_AD<0x0C, "muls.ad.ll">; +def MULS_AD_HL : MULS_AD<0x0D, "muls.ad.hl">; +def MULS_AD_LH : MULS_AD<0x0E, "muls.ad.lh">; +def MULS_AD_HH : MULS_AD<0x0F, "muls.ad.hh">; + +class MULS_DA oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t), + instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> { + bits<2> x; + + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = 0; + let s = 0; + + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULS_DA_LL : MULS_DA<0x0C, "muls.da.ll">; +def MULS_DA_HL : MULS_DA<0x0D, "muls.da.hl">; +def MULS_DA_LH : MULS_DA<0x0E, "muls.da.lh">; +def MULS_DA_HH : MULS_DA<0x0F, "muls.da.hh">; + +class MULS_DD oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y), + instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> { + bits<2> x; + bits<2> y; + + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = 0; + let s = 0; + let t{3} = 0; + let t{2} = y{0}; + let t{1-0} = 0; + + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULS_DD_LL : MULS_DD<0x0C, "muls.dd.ll">; +def MULS_DD_HL : MULS_DD<0x0D, "muls.dd.hl">; +def MULS_DD_LH : MULS_DD<0x0E, "muls.dd.lh">; +def MULS_DD_HH : MULS_DD<0x0F, "muls.dd.hh">; + +//===----------------------------------------------------------------------===// +// Multiply-accumulate with load + +class MULA_DA_LDDEC oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x05, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, AR:$t), + instrAsm#"\t $w, $s, $x, $t", []>, Requires<[HasMAC16]> { + bits<2> x; + bits<2> w; + + let Constraints = "$s = $d"; + let mayLoad = 1; + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = w{1-0}; + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULA_DA_LL_LDDEC : MULA_DA_LDDEC<0x08, "mula.da.ll.lddec">; +def MULA_DA_HL_LDDEC : MULA_DA_LDDEC<0x09, "mula.da.hl.lddec">; +def MULA_DA_LH_LDDEC : MULA_DA_LDDEC<0x0A, "mula.da.lh.lddec">; +def MULA_DA_HH_LDDEC : MULA_DA_LDDEC<0x0B, "mula.da.hh.lddec">; + +class MULA_DA_LDINC oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x04, (outs MR:$w, AR:$d), (ins AR:$s, MR:$x, AR:$t), + instrAsm#"\t $w, $s, $x, $t", []>, Requires<[HasMAC16]> { + bits<1> x; + bits<2> w; + + let Constraints = "$s = $d"; + let mayLoad = 1; + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = w{1-0}; + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULA_DA_LL_LDINC: MULA_DA_LDINC<0x08, "mula.da.ll.ldinc">; +def MULA_DA_HL_LDINC: MULA_DA_LDINC<0x09, "mula.da.hl.ldinc">; +def MULA_DA_LH_LDINC: MULA_DA_LDINC<0x0A, "mula.da.lh.ldinc">; +def MULA_DA_HH_LDINC: MULA_DA_LDINC<0x0B, "mula.da.hh.ldinc">; + +class MULA_DD_LDDEC oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x01, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y), + instrAsm#"\t $w, $s, $x, $y", []>, Requires<[HasMAC16]> { + bits<2> x; + bits<2> y; + bits<2> w; + + let Constraints = "$s = $d"; + let mayLoad = 1; + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = w{1-0}; + let t{3} = 0; + let t{2} = y{0}; + let t{1-0} = 0; + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULA_DD_LL_LDDEC : MULA_DD_LDDEC<0x08, "mula.dd.ll.lddec">; +def MULA_DD_HL_LDDEC : MULA_DD_LDDEC<0x09, "mula.dd.hl.lddec">; +def MULA_DD_LH_LDDEC : MULA_DD_LDDEC<0x0A, "mula.dd.lh.lddec">; +def MULA_DD_HH_LDDEC : MULA_DD_LDDEC<0x0B, "mula.dd.hh.lddec">; + +class MULA_DD_LDINC oper1, string instrAsm> + : RRR_Inst<0x04, oper1, 0x00, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y), + instrAsm#"\t $w, $s, $x, $y", []>, Requires<[HasMAC16]> { + bits<2> x; + bits<2> y; + bits<2> w; + + let Constraints = "$s = $d"; + let mayLoad = 1; + let r{3} = 0; + let r{2} = x{0}; + let r{1-0} = w{1-0}; + let t{3} = 0; + let t{2} = y{0}; + let t{1-0} = 0; + let Uses = [ACCLO, ACCHI]; + let Defs = [M1, M2, ACCLO, ACCHI]; +} + +def MULA_DD_LL_LDINC : MULA_DD_LDINC<0x08, "mula.dd.ll.ldinc">; +def MULA_DD_HL_LDINC : MULA_DD_LDINC<0x09, "mula.dd.hl.ldinc">; +def MULA_DD_LH_LDINC : MULA_DD_LDINC<0x0A, "mula.dd.lh.ldinc">; +def MULA_DD_HH_LDINC : MULA_DD_LDINC<0x0B, "mula.dd.hh.ldinc">; + +def LDDEC : RRR_Inst<0x04, 0x00, 0x09, (outs MR:$w, AR:$d), (ins AR:$s), + "lddec\t $w, $s", []>, Requires<[HasMAC16]> { + bits<2> w; + + let Constraints = "$s = $d"; + let mayLoad = 1; + let r{3-2} = 0; + let r{1-0} = w{1-0}; + let t = 0x00; +} + +def LDINC : RRR_Inst<0x04, 0x00, 0x08, (outs MR:$w, AR:$d), (ins AR:$s), + "ldinc\t $w, $s", []>, Requires<[HasMAC16]> { + bits<2> w; + + let Constraints = "$s = $d"; + let mayLoad = 1; + let r{3-2} = 0; + let r{1-0} = w{1-0}; + let t = 0; +} diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index e12f4a632d10ec..fa15b7833575fb 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1190,3 +1190,8 @@ def QUOS : ArithLogic_RRR<0x0D, 0x02, "quos", sdiv>, Requires<[HasDiv32]>; def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>, Requires<[HasDiv32]>; def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>, Requires<[HasDiv32]>; def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>, Requires<[HasDiv32]>; + +//===----------------------------------------------------------------------===// +// DSP Instructions +//===----------------------------------------------------------------------===// +include "XtensaDSPInstrInfo.td" diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index d7fbdcff09b988..4e953f7bfe159b 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -81,11 +81,21 @@ def SAR : SRReg<3, "sar", ["SAR","3"]>; def BREG : SRReg<4, "br", ["BR", "4"]>; +def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>; +def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>; +def M0 : SRReg<32, "m0", ["M0", "32"]>; +def M1 : SRReg<33, "m1", ["M1", "33"]>; +def M2 : SRReg<34, "m2", ["M2", "34"]>; +def M3 : SRReg<35, "m3", ["M3", "35"]>; def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>; def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>; +def MR01 : RegisterClass<"Xtensa", [i32], 32, (add M0, M1)>; +def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>; +def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>; + def SR : RegisterClass<"Xtensa", [i32], 32, (add LBEG, LEND, LCOUNT, - SAR, BREG, WINDOWBASE, WINDOWSTART)>; + SAR, BREG, MR, WINDOWBASE, WINDOWSTART)>; //===----------------------------------------------------------------------===// // USER registers diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 03fd8cb99cb9f7..b23346ea4335c0 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -42,6 +42,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasMul32 = false; HasMul32High = false; HasDiv32 = false; + HasMAC16 = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index f129ddbdb893bb..a4bfd2ae395676 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -68,6 +68,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa Div32 option bool HasDiv32; + // Enabled Xtensa MAC16 instructions + bool HasMAC16; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -105,6 +108,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasDiv32() const { return HasDiv32; } + bool hasMAC16() const { return HasMAC16; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; diff --git a/llvm/test/MC/Xtensa/xtensa-valid-mac16.s b/llvm/test/MC/Xtensa/xtensa-valid-mac16.s new file mode 100644 index 00000000000000..dee79da7755d96 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-mac16.s @@ -0,0 +1,234 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+mac16 -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +.align 4 +LBL0: + +# CHECK-INST: umul.aa.ll a2, a3 +# CHECK: encoding: [0x34,0x02,0x70] + umul.aa.ll a2, a3 +# CHECK-INST: umul.aa.lh a2, a3 +# CHECK: encoding: [0x34,0x02,0x72] + umul.aa.lh a2, a3 +# CHECK-INST: umul.aa.hl a2, a3 +# CHECK: encoding: [0x34,0x02,0x71] + umul.aa.hl a2, a3 +# CHECK-INST: umul.aa.hh a2, a3 +# CHECK: encoding: [0x34,0x02,0x73] + umul.aa.hh a2, a3 + +# CHECK-INST: mul.aa.ll a2, a3 +# CHECK: encoding: [0x34,0x02,0x74] + mul.aa.ll a2, a3 +# CHECK-INST: mul.aa.lh a2, a3 +# CHECK: encoding: [0x34,0x02,0x76] + mul.aa.lh a2, a3 +# CHECK-INST: mul.aa.hl a2, a3 +# CHECK: encoding: [0x34,0x02,0x75] + mul.aa.hl a2, a3 +# CHECK-INST: mul.aa.hh a2, a3 +# CHECK: encoding: [0x34,0x02,0x77] + mul.aa.hh a2, a3 + +# CHECK-INST: mul.ad.ll a2, m2 +# CHECK: encoding: [0x04,0x02,0x34] + mul.ad.ll a2, m2 +# CHECK-INST: mul.ad.lh a2, m2 +# CHECK: encoding: [0x04,0x02,0x36] + mul.ad.lh a2, m2 +# CHECK-INST: mul.ad.hl a2, m2 +# CHECK: encoding: [0x04,0x02,0x35] + mul.ad.hl a2, m2 +# CHECK-INST: mul.ad.hh a2, m2 +# CHECK: encoding: [0x04,0x02,0x37] + mul.ad.hh a2, m2 + +# CHECK-INST: mul.da.ll m1, a3 +# CHECK: encoding: [0x34,0x40,0x64] + mul.da.ll m1, a3 +# CHECK-INST: mul.da.lh m1, a3 +# CHECK: encoding: [0x34,0x40,0x66] + mul.da.lh m1, a3 +# CHECK-INST: mul.da.hl m1, a3 +# CHECK: encoding: [0x34,0x40,0x65] + mul.da.hl m1, a3 +# CHECK-INST: mul.da.hh m1, a3 +# CHECK: encoding: [0x34,0x40,0x67] + mul.da.hh m1, a3 + +# CHECK-INST: mul.dd.ll m1, m2 +# CHECK: encoding: [0x04,0x40,0x24] + mul.dd.ll m1, m2 +# CHECK-INST: mul.dd.lh m1, m2 +# CHECK: encoding: [0x04,0x40,0x26] + mul.dd.lh m1, m2 +# CHECK-INST: mul.dd.hl m1, m2 +# CHECK: encoding: [0x04,0x40,0x25] + mul.dd.hl m1, m2 +# CHECK-INST: mul.dd.hh m1, m2 +# CHECK: encoding: [0x04,0x40,0x27] + mul.dd.hh m1, m2 + +# CHECK-INST: mula.aa.ll a2, a3 +# CHECK: encoding: [0x34,0x02,0x78] + mula.aa.ll a2, a3 +# CHECK-INST: mula.aa.lh a2, a3 +# CHECK: encoding: [0x34,0x02,0x7a] + mula.aa.lh a2, a3 +# CHECK-INST: mula.aa.hl a2, a3 +# CHECK: encoding: [0x34,0x02,0x79] + mula.aa.hl a2, a3 +# CHECK-INST: mula.aa.hh a2, a3 +# CHECK: encoding: [0x34,0x02,0x7b] + mula.aa.hh a2, a3 + +# CHECK-INST: mula.ad.ll a2, m2 +# CHECK: encoding: [0x04,0x02,0x38] + mula.ad.ll a2, m2 +# CHECK-INST: mula.ad.lh a2, m2 +# CHECK: encoding: [0x04,0x02,0x3a] + mula.ad.lh a2, m2 +# CHECK-INST: mula.ad.hl a2, m2 +# CHECK: encoding: [0x04,0x02,0x39] + mula.ad.hl a2, m2 +# CHECK-INST: mula.ad.hh a2, m2 +# CHECK: encoding: [0x04,0x02,0x3b] + mula.ad.hh a2, m2 + +# CHECK-INST: mula.da.ll m1, a3 +# CHECK: encoding: [0x34,0x40,0x68] + mula.da.ll m1, a3 +# CHECK-INST: mula.da.lh m1, a3 +# CHECK: encoding: [0x34,0x40,0x6a] + mula.da.lh m1, a3 +# CHECK-INST: mula.da.hl m1, a3 +# CHECK: encoding: [0x34,0x40,0x69] + mula.da.hl m1, a3 +# CHECK-INST: mula.da.hh m1, a3 +# CHECK: encoding: [0x34,0x40,0x6b] + mula.da.hh m1, a3 + +# CHECK-INST: mula.dd.ll m1, m2 +# CHECK: encoding: [0x04,0x40,0x28] + mula.dd.ll m1, m2 +# CHECK-INST: mula.dd.lh m1, m2 +# CHECK: encoding: [0x04,0x40,0x2a] + mula.dd.lh m1, m2 +# CHECK-INST: mula.dd.hl m1, m2 +# CHECK: encoding: [0x04,0x40,0x29] + mula.dd.hl m1, m2 +# CHECK-INST: mula.dd.hh m1, m2 +# CHECK: encoding: [0x04,0x40,0x2b] + mula.dd.hh m1, m2 + +# CHECK-INST: muls.aa.ll a2, a3 +# CHECK: encoding: [0x34,0x02,0x7c] + muls.aa.ll a2, a3 +# CHECK-INST: muls.aa.lh a2, a3 +# CHECK: encoding: [0x34,0x02,0x7e] + muls.aa.lh a2, a3 +# CHECK-INST: muls.aa.hl a2, a3 +# CHECK: encoding: [0x34,0x02,0x7d] + muls.aa.hl a2, a3 +# CHECK-INST: muls.aa.hh a2, a3 +# CHECK: encoding: [0x34,0x02,0x7f] + muls.aa.hh a2, a3 + +# CHECK-INST: muls.ad.ll a2, m2 +# CHECK: encoding: [0x04,0x02,0x3c] + muls.ad.ll a2, m2 +# CHECK-INST: muls.ad.lh a2, m2 +# CHECK: encoding: [0x04,0x02,0x3e] + muls.ad.lh a2, m2 +# CHECK-INST: muls.ad.hl a2, m2 +# CHECK: encoding: [0x04,0x02,0x3d] + muls.ad.hl a2, m2 +# CHECK-INST: muls.ad.hh a2, m2 +# CHECK: encoding: [0x04,0x02,0x3f] + muls.ad.hh a2, m2 + +# CHECK-INST: muls.da.ll m1, a3 +# CHECK: encoding: [0x34,0x40,0x6c] + muls.da.ll m1, a3 +# CHECK-INST: muls.da.lh m1, a3 +# CHECK: encoding: [0x34,0x40,0x6e] + muls.da.lh m1, a3 +# CHECK-INST: muls.da.hl m1, a3 +# CHECK: encoding: [0x34,0x40,0x6d] + muls.da.hl m1, a3 +# CHECK-INST: muls.da.hh m1, a3 +# CHECK: encoding: [0x34,0x40,0x6f] + muls.da.hh m1, a3 + +# CHECK-INST: muls.dd.ll m1, m2 +# CHECK: encoding: [0x04,0x40,0x2c] + muls.dd.ll m1, m2 +# CHECK-INST: muls.dd.lh m1, m2 +# CHECK: encoding: [0x04,0x40,0x2e] + muls.dd.lh m1, m2 +# CHECK-INST: muls.dd.hl m1, m2 +# CHECK: encoding: [0x04,0x40,0x2d] + muls.dd.hl m1, m2 +# CHECK-INST: muls.dd.hh m1, m2 +# CHECK: encoding: [0x04,0x40,0x2f] + muls.dd.hh m1, m2 + +# CHECK-INST: mula.da.ll.lddec m1, a8, m0, a3 +# CHECK: encoding: [0x34,0x18,0x58] + mula.da.ll.lddec m1, a8, m0, a3 +# CHECK-INST: mula.da.hl.lddec m1, a8, m0, a3 +# CHECK: encoding: [0x34,0x18,0x59] + mula.da.hl.lddec m1, a8, m0, a3 +# CHECK-INST: mula.da.lh.lddec m1, a8, m0, a3 +# CHECK: encoding: [0x34,0x18,0x5a] + mula.da.lh.lddec m1, a8, m0, a3 +# CHECK-INST: mula.da.hh.lddec m1, a8, m0, a3 +# CHECK: encoding: [0x34,0x18,0x5b] + mula.da.hh.lddec m1, a8, m0, a3 + +# CHECK-INST: mula.dd.ll.lddec m1, a8, m0, m2 +# CHECK: encoding: [0x04,0x18,0x18] + mula.dd.ll.lddec m1, a8, m0, m2 +# CHECK-INST: mula.dd.hl.lddec m1, a8, m0, m2 +# CHECK: encoding: [0x04,0x18,0x19] + mula.dd.hl.lddec m1, a8, m0, m2 +# CHECK-INST: mula.dd.lh.lddec m1, a8, m0, m2 +# CHECK: encoding: [0x04,0x18,0x1a] + mula.dd.lh.lddec m1, a8, m0, m2 +# CHECK-INST: mula.dd.hh.lddec m1, a8, m0, m2 +# CHECK: encoding: [0x04,0x18,0x1b] + mula.dd.hh.lddec m1, a8, m0, m2 + +# CHECK-INST: mula.da.ll.ldinc m1, a8, m0, a3 +# CHECK: encoding: [0x34,0x18,0x48] + mula.da.ll.ldinc m1, a8, m0, a3 +# CHECK-INST: mula.da.hl.ldinc m1, a8, m0, a3 +# CHECK: encoding: [0x34,0x18,0x49] + mula.da.hl.ldinc m1, a8, m0, a3 +# CHECK-INST: mula.da.lh.ldinc m1, a8, m0, a3 +# CHECK: encoding: [0x34,0x18,0x4a] + mula.da.lh.ldinc m1, a8, m0, a3 +# CHECK-INST: mula.da.hh.ldinc m1, a8, m0, a3 +# CHECK: encoding: [0x34,0x18,0x4b] + mula.da.hh.ldinc m1, a8, m0, a3 + +# CHECK-INST: mula.dd.ll.ldinc m1, a8, m0, m2 +# CHECK: encoding: [0x04,0x18,0x08] + mula.dd.ll.ldinc m1, a8, m0, m2 +# CHECK-INST: mula.dd.hl.ldinc m1, a8, m0, m2 +# CHECK: encoding: [0x04,0x18,0x09] + mula.dd.hl.ldinc m1, a8, m0, m2 +# CHECK-INST: mula.dd.lh.ldinc m1, a8, m0, m2 +# CHECK: encoding: [0x04,0x18,0x0a] + mula.dd.lh.ldinc m1, a8, m0, m2 +# CHECK-INST: mula.dd.hh.ldinc m1, a8, m0, m2 +# CHECK: encoding: [0x04,0x18,0x0b] + mula.dd.hh.ldinc m1, a8, m0, m2 + +# CHECK-INST: lddec m0, a8 +# CHECK: encoding: [0x04,0x08,0x90] + lddec m0, a8 +# CHECK-INST: ldinc m0, a8 +# CHECK: encoding: [0x04,0x08,0x80] + ldinc m0, a8 + From d6c26b28b3f61c28a7334bb1e8764addaa2035ac Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:36 +0300 Subject: [PATCH 033/261] [Xtensa] Implement Xtensa features and operations. Implement Debug, DFPAccel, S32C1I, THREADPTR, Extended L32R, ATOMCTL, MEMCTL features. --- .../Disassembler/XtensaDisassembler.cpp | 21 ++++++-- .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 1 + llvm/lib/Target/Xtensa/Xtensa.td | 35 +++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 2 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 39 +++++++++++++++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 49 ++++++++++++++++++- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 7 +++ llvm/lib/Target/Xtensa/XtensaSubtarget.h | 35 +++++++++++++ llvm/test/MC/Xtensa/xtensa-valid-dbg.s | 9 ++++ 9 files changed, 191 insertions(+), 7 deletions(-) create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-dbg.s diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 5abb901f16f63c..b13468e5835716 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -148,10 +148,19 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo, } static const unsigned SRDecoderTable[] = { - Xtensa::LEND, 1, Xtensa::LCOUNT, 2, Xtensa::SAR, 3, - Xtensa::BREG, 4, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17, - Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34, - Xtensa::M3, 35, Xtensa ::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73}; + Xtensa::LBEG, 0, Xtensa::LEND, 1, + Xtensa::LCOUNT, 2, Xtensa::SAR, 3, + Xtensa::BREG, 4, Xtensa::LITBASE, 5, + Xtensa::ACCLO, 16, Xtensa::ACCHI, 17, + Xtensa::M0, 32, Xtensa::M1, 33, + Xtensa::M2, 34, Xtensa::M3, 35, + Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73, + Xtensa::IBREAKENABLE, 96, Xtensa::MEMCTL, 97, + Xtensa::ATOMCTL, 99, Xtensa::IBREAKA0, 128, + Xtensa::IBREAKA1, 129, Xtensa::DBREAKA0, 144, + Xtensa::DBREAKA1, 145, Xtensa::DBREAKC0, 160, + Xtensa::DBREAKC1, 161, Xtensa::DEBUGCAUSE, 233, + Xtensa::ICOUNT, 236, Xtensa::ICOUNTLEVEL, 237}; static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, @@ -170,7 +179,9 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Fail; } -static const unsigned URDecoderTable[] = {Xtensa::FCR, 232, Xtensa::FSR, 233}; +static const unsigned URDecoderTable[] = { + Xtensa::THREADPTR, 231, Xtensa::FCR, 232, Xtensa::FSR, 233, + Xtensa::F64R_LO, 234, Xtensa::F64R_HI, 235, Xtensa::F64S, 236}; static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index eadcae39255d59..01c7bd4bd31857 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -283,6 +283,7 @@ XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo, case Xtensa::L32I_N: case Xtensa::S32F: case Xtensa::L32F: + case Xtensa::S32C1I: if (Res & 0x3) { report_fatal_error("Unexpected operand value!"); } diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 5468b91e24940c..6d4254a4925165 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -72,6 +72,41 @@ def FeatureMAC16 : SubtargetFeature<"mac16", "HasMAC16", "true", def HasMAC16 : Predicate<"Subtarget->hasMAC16()">, AssemblerPredicate<(all_of FeatureMAC16)>; +def FeatureDFPAccel : SubtargetFeature<"dfpaccel", "HasDFPAccel", "true", + "Enable Xtensa Double Precision FP acceleration">; +def HasDFPAccel : Predicate<"Subtarget->hasDFPAccel()">, + AssemblerPredicate<(all_of FeatureDFPAccel)>; + +def FeatureS32C1I : SubtargetFeature<"s32c1i", "HasS32C1I", "true", + "Enable Xtensa S32C1I option">; +def HasS32C1I : Predicate<"Subtarget->hasS32C1I()">, + AssemblerPredicate<(all_of FeatureS32C1I)>; + +def FeatureTHREADPTR : SubtargetFeature<"threadptr", "HasTHREADPTR", "true", + "Enable Xtensa THREADPTR option">; +def HasTHREADPTR : Predicate<"Subtarget->hasTHREADPTR()">, + AssemblerPredicate<(all_of FeatureTHREADPTR)>; + +def FeatureExtendedL32R : SubtargetFeature<"extendedl32r", "HasExtendedL32R", "true", + "Enable Xtensa Extended L32R option">; +def HasExtendedL32R : Predicate<"Subtarget->hasExtendedL32R()">, + AssemblerPredicate<(all_of FeatureExtendedL32R)>; + +def FeatureATOMCTL : SubtargetFeature<"atomctl", "HasATOMCTL", "true", + "Enable Xtensa ATOMCTL option">; +def HasATOMCTL : Predicate<"Subtarget->hasATOMCTL()">, + AssemblerPredicate<(all_of FeatureATOMCTL)>; + +def FeatureMEMCTL : SubtargetFeature<"memctl", "HasMEMCTL", "true", + "Enable Xtensa MEMCTL option">; +def HasMEMCTL : Predicate<"Subtarget->hasMEMCTL()">, + AssemblerPredicate<(all_of FeatureMEMCTL)>; + +def FeatureDebug : SubtargetFeature<"debug", "HasDebug", "true", + "Enable Xtensa Debug option">; +def HasDebug : Predicate<"Subtarget->hasDebug()">, + AssemblerPredicate<(all_of FeatureDebug)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index eb9fb025161ada..2d7df81f3a06ff 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -301,6 +301,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::VACOPY, MVT::Other, Custom); setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::TRAP, MVT::Other, Legal); + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index fa15b7833575fb..9f641f99de2263 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1191,6 +1191,45 @@ def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>, Requires<[HasDiv32]>; def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>, Requires<[HasDiv32]>; def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>, Requires<[HasDiv32]>; +//===----------------------------------------------------------------------===// +// S32C1I +//===----------------------------------------------------------------------===// + +let mayStore = 1, mayLoad = 1, Predicates = [HasS32C1I] in { + def S32C1I : RRI8_Inst<0x02, (outs AR:$a), (ins AR:$t, mem32:$addr), + "s32c1i\t$t, $addr", []> { + bits<12> addr; + + let r = 0x0e; + let Uses = [SCOMPARE1]; + let Constraints = "$a = $t"; + let imm8{7-0} = addr{11-4}; + let s{3-0} = addr{3-0}; + } +} + +//===----------------------------------------------------------------------===// +// Debug instructions +//===----------------------------------------------------------------------===// + +let isBarrier = 1, isTerminator = 1 in { + def BREAK : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$s, uimm4:$t), + "break\t$s, $t", []>, Requires<[HasDebug]> { + let r = 0x04; + } + + def BREAK_N : RRRN_Inst<0x0C, (outs), (ins uimm4:$imm), + "break.n\t$imm", []>, Requires<[HasDensity, HasDebug]> { + bits<4> imm; + + let r = 0xf; + let s = imm; + let t = 0x2; + } +} + +def : Pat<(trap), (BREAK (i32 1), (i32 15))>; + //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 4e953f7bfe159b..b5d371c2e315a6 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -80,6 +80,10 @@ def LCOUNT : SRReg<2, "lcount", ["LCOUNT", "2"]>; def SAR : SRReg<3, "sar", ["SAR","3"]>; def BREG : SRReg<4, "br", ["BR", "4"]>; +def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>; + +// Expected data value for S32C1I operation +def SCOMPARE1 : SRReg<12, "scompare1", ["SCOMPARE1", "12"]>; def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>; def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>; @@ -90,12 +94,46 @@ def M3 : SRReg<35, "m3", ["M3", "35"]>; def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>; def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>; +// Instuction breakpoint enable register +def IBREAKENABLE : SRReg<96, "ibreakenable", ["IBREAKENABLE", "96"]>; + +// Memory Control Register +def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>; + +def ATOMCTL : SRReg<99, "atomctl", ["ATOMCTL", "99"]>; + +// Instuction break address register 0 +def IBREAKA0 : SRReg<128, "ibreaka0", ["IBREAKA0", "128"]>; + +// Instuction break address register 1 +def IBREAKA1 : SRReg<129, "ibreaka1", ["IBREAKA1", "129"]>; + +// Data break address register 0 +def DBREAKA0 : SRReg<144, "dbreaka0", ["DBREAKA0", "144"]>; + +// Data break address register 1 +def DBREAKA1 : SRReg<145, "dbreaka1", ["DBREAKA1", "145"]>; + +// Data breakpoint control register 0 +def DBREAKC0 : SRReg<160, "dbreakc0", ["DBREAKC0", "160"]>; + +// Data breakpoint control register 1 +def DBREAKC1 : SRReg<161, "dbreakc1", ["DBREAKC1", "161"]>; + +// Cause of last debug exception register +def DEBUGCAUSE : SRReg<233, "debugcause", ["DEBUGCAUSE", "233"]>; + +def ICOUNT : SRReg<236, "icount", ["ICOUNT", "236"]>; +def ICOUNTLEVEL : SRReg<237, "icountlevel", ["ICOUNTLEVEL", "237"]>; + def MR01 : RegisterClass<"Xtensa", [i32], 32, (add M0, M1)>; def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>; def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>; def SR : RegisterClass<"Xtensa", [i32], 32, (add LBEG, LEND, LCOUNT, - SAR, BREG, MR, WINDOWBASE, WINDOWSTART)>; + SAR, BREG, LITBASE, SCOMPARE1, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART, + IBREAKENABLE, MEMCTL, ATOMCTL, IBREAKA0, IBREAKA1, DBREAKA0, DBREAKA1, + DBREAKC0, DBREAKC1, DEBUGCAUSE, ICOUNT, ICOUNTLEVEL)>; //===----------------------------------------------------------------------===// // USER registers @@ -105,10 +143,17 @@ class URReg num, string n, list alt = []> : XtensaReg { let AltNames = alt; } +// Thread Pointer register +def THREADPTR : URReg<231, "threadptr", ["THREADPTR"]>; + def FCR : URReg<232, "fcr", ["FCR"]>; def FSR : URReg<233, "fsr", ["FSR"]>; +def F64R_LO : URReg<234, "f64r_lo", ["F64R_LO"]>; +def F64R_HI : URReg<235, "f64r_hi", ["F64R_HI"]>; +def F64S : URReg<236, "f64s", ["F64S"]>; -def UR : RegisterClass<"Xtensa", [i32], 32, (add FCR, FSR)>; +def UR : RegisterClass<"Xtensa", [i32], 32, (add THREADPTR, FCR, + FSR, F64R_LO, F64R_HI, F64S)>; //===----------------------------------------------------------------------===// // Floating-Point registers diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index b23346ea4335c0..800c62d9cefc6b 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -43,6 +43,13 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasMul32High = false; HasDiv32 = false; HasMAC16 = false; + HasDFPAccel = false; + HasS32C1I = false; + HasTHREADPTR = false; + HasExtendedL32R = false; + HasATOMCTL = false; + HasMEMCTL = false; + HasDebug = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index a4bfd2ae395676..eed24f28be1532 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -71,6 +71,27 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enabled Xtensa MAC16 instructions bool HasMAC16; + // Enable Xtensa Xtensa Double Precision FP acceleration + bool HasDFPAccel; + + // Enable Xtensa S32C1I option + bool HasS32C1I; + + // Enable Xtensa THREADPTR option + bool HasTHREADPTR; + + // Enable Xtensa Extended L32R option + bool HasExtendedL32R; + + // Enable Xtensa ATOMCTL option + bool HasATOMCTL; + + // Enable Xtensa ATOMCTL option + bool HasMEMCTL; + + // Enable Xtensa Debug option + bool HasDebug; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -110,6 +131,20 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasMAC16() const { return HasMAC16; } + bool hasDFPAccel() const { return HasDFPAccel; } + + bool hasS32C1I() const { return HasS32C1I; } + + bool hasTHREADPTR() const { return HasTHREADPTR; } + + bool hasExtendedL32R() const { return HasExtendedL32R; } + + bool hasATOMCTL() const { return HasATOMCTL; } + + bool hasMEMCTL() const { return HasMEMCTL; } + + bool hasDebug() const { return HasDebug; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; diff --git a/llvm/test/MC/Xtensa/xtensa-valid-dbg.s b/llvm/test/MC/Xtensa/xtensa-valid-dbg.s new file mode 100644 index 00000000000000..9391c60e43f692 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-dbg.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+debug -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +.align 4 +LBL0: + +# CHECK-INST: break 1, 2 +# CHECK: encoding: [0x20,0x41,0x00] + break 1, 2 From 848b267bbb6f6bd6a6e2a82fcce48379b5bdd5c3 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:36 +0300 Subject: [PATCH 034/261] [Xtensa] Implement Xtensa features and operations. Implement Exception, HighPriInterrupts, Coprocessor, Interrupt, RelocatableVector, TimerInt, PRID, RegionProtection and MiscSR features. Implement instructions for Exception, Interrupt and RegionProtection features with tests. --- .../Disassembler/XtensaDisassembler.cpp | 52 +++++++--- llvm/lib/Target/Xtensa/Xtensa.td | 46 +++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 77 +++++++++++++++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 94 ++++++++++++++++++- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 9 ++ llvm/lib/Target/Xtensa/XtensaSubtarget.h | 45 +++++++++ llvm/test/MC/Xtensa/xtensa-valid-exc.s | 21 +++++ llvm/test/MC/Xtensa/xtensa-valid-int.s | 18 ++++ llvm/test/MC/Xtensa/xtensa-valid-regprotect.s | 14 +++ 9 files changed, 356 insertions(+), 20 deletions(-) create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-exc.s create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-int.s create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-regprotect.s diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index b13468e5835716..d4d84b47f96cab 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -148,19 +148,40 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo, } static const unsigned SRDecoderTable[] = { - Xtensa::LBEG, 0, Xtensa::LEND, 1, - Xtensa::LCOUNT, 2, Xtensa::SAR, 3, - Xtensa::BREG, 4, Xtensa::LITBASE, 5, - Xtensa::ACCLO, 16, Xtensa::ACCHI, 17, - Xtensa::M0, 32, Xtensa::M1, 33, - Xtensa::M2, 34, Xtensa::M3, 35, - Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73, - Xtensa::IBREAKENABLE, 96, Xtensa::MEMCTL, 97, - Xtensa::ATOMCTL, 99, Xtensa::IBREAKA0, 128, - Xtensa::IBREAKA1, 129, Xtensa::DBREAKA0, 144, - Xtensa::DBREAKA1, 145, Xtensa::DBREAKC0, 160, - Xtensa::DBREAKC1, 161, Xtensa::DEBUGCAUSE, 233, - Xtensa::ICOUNT, 236, Xtensa::ICOUNTLEVEL, 237}; + Xtensa::LBEG, 0, Xtensa::LEND, 1, + Xtensa::LCOUNT, 2, Xtensa::SAR, 3, + Xtensa::BREG, 4, Xtensa::LITBASE, 5, + Xtensa::SCOMPARE1, 12, Xtensa::ACCLO, 16, + Xtensa::ACCHI, 17, Xtensa::M0, 32, + Xtensa::M1, 33, Xtensa::M2, 34, + Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, + Xtensa::WINDOWSTART, 73, Xtensa::IBREAKENABLE, 96, + Xtensa::MEMCTL, 97, Xtensa::ATOMCTL, 99, + Xtensa::DDR, 104, Xtensa::IBREAKA0, 128, + Xtensa::IBREAKA1, 129, Xtensa::DBREAKA0, 144, + Xtensa::DBREAKA1, 145, Xtensa::DBREAKC0, 160, + Xtensa::DBREAKC1, 161, Xtensa::CONFIGID0, 176, + Xtensa::EPC1, 177, Xtensa::EPC2, 178, + Xtensa::EPC3, 179, Xtensa::EPC4, 180, + Xtensa::EPC5, 181, Xtensa::EPC6, 182, + Xtensa::EPC7, 183, Xtensa::DEPC, 192, + Xtensa::EPS2, 194, Xtensa::EPS3, 195, + Xtensa::EPS4, 196, Xtensa::EPS5, 197, + Xtensa::EPS6, 198, Xtensa::EPS7, 199, + Xtensa::CONFIGID1, 208, Xtensa::EXCSAVE1, 209, + Xtensa::EXCSAVE2, 210, Xtensa::EXCSAVE3, 211, + Xtensa::EXCSAVE4, 212, Xtensa::EXCSAVE5, 213, + Xtensa::EXCSAVE6, 214, Xtensa::EXCSAVE7, 215, + Xtensa::CPENABLE, 224, Xtensa::INTSET, 226, + Xtensa::INTCLEAR, 227, Xtensa::INTENABLE, 228, + Xtensa::PS, 230, Xtensa::VECBASE, 231, + Xtensa::EXCCAUSE, 232, Xtensa::DEBUGCAUSE, 233, + Xtensa::CCOUNT, 234, Xtensa::PRID, 235, + Xtensa::ICOUNT, 236, Xtensa::ICOUNTLEVEL, 237, + Xtensa::EXCVADDR, 238, Xtensa::CCOMPARE0, 240, + Xtensa::CCOMPARE1, 241, Xtensa::CCOMPARE2, 242, + Xtensa::MISC0, 244, Xtensa::MISC1, 245, + Xtensa::MISC2, 246, Xtensa::MISC3, 247}; static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, @@ -180,8 +201,9 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, } static const unsigned URDecoderTable[] = { - Xtensa::THREADPTR, 231, Xtensa::FCR, 232, Xtensa::FSR, 233, - Xtensa::F64R_LO, 234, Xtensa::F64R_HI, 235, Xtensa::F64S, 236}; + Xtensa::EXPSTATE, 230, Xtensa::THREADPTR, 231, Xtensa::FCR, 232, + Xtensa::FSR, 233, Xtensa::F64R_LO, 234, Xtensa::F64R_HI, 235, + Xtensa::F64S, 236}; static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 6d4254a4925165..f141a6db02b508 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -107,6 +107,52 @@ def FeatureDebug : SubtargetFeature<"debug", "HasDebug", "true", def HasDebug : Predicate<"Subtarget->hasDebug()">, AssemblerPredicate<(all_of FeatureDebug)>; +def FeatureException : SubtargetFeature<"exception", "HasException", "true", + "Enable Xtensa Exception option">; +def HasException : Predicate<"Subtarget->hasException()">, + AssemblerPredicate<(all_of FeatureException)>; + +def FeatureHighPriInterrupts : SubtargetFeature<"highpriinterrupts", + "HasHighPriInterrupts", "true", + "Enable Xtensa HighPriInterrupts option">; +def HasHighPriInterrupts : Predicate<"Subtarget->hasHighPriInterrupts()">, + AssemblerPredicate<(all_of FeatureHighPriInterrupts)>; + +def FeatureCoprocessor : SubtargetFeature<"coprocessor", "HasCoprocessor", "true", + "Enable Xtensa Coprocessor option">; +def HasCoprocessor : Predicate<"Subtarget->hasCoprocessor()">, + AssemblerPredicate<(all_of FeatureCoprocessor)>; + +def FeatureInterrupt : SubtargetFeature<"interrupt", "HasInterrupt", "true", + "Enable Xtensa Interrupt option">; +def HasInterrupt : Predicate<"Subtarget->hasInterrupt()">, + AssemblerPredicate<(all_of FeatureInterrupt)>; + +def FeatureRelocatableVector : SubtargetFeature<"rvector", "HasRelocatableVector", "true", + "Enable Xtensa Relocatable Vector option">; +def HasRelocatableVector : Predicate<"Subtarget->hasRelocatableVector()">, + AssemblerPredicate<(all_of FeatureRelocatableVector)>; + +def FeatureTimerInt : SubtargetFeature<"timerint", "HasTimerInt", "true", + "Enable Xtensa Timer Interrupt option">; +def HasTimerInt : Predicate<"Subtarget->hasTimerInt()">, + AssemblerPredicate<(all_of FeatureTimerInt)>; + +def FeaturePRID : SubtargetFeature<"prid", "HasPRID", "true", + "Enable Xtensa Processor ID option">; +def HasPRID : Predicate<"Subtarget->hasPRID()">, + AssemblerPredicate<(all_of FeaturePRID)>; + +def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true", + "Enable Xtensa Region Protection option">; +def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">, + AssemblerPredicate<(all_of FeatureRegionProtection)>; + +def FeatureMiscSR : SubtargetFeature<"miscsr", "HasMiscSR", "true", + "Enable Xtensa Miscellaneous SR option">; +def HasMiscSR : Predicate<"Subtarget->hasMiscSR()">, + AssemblerPredicate<(all_of FeatureMiscSR)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 9f641f99de2263..378949fa4b02f0 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1230,6 +1230,83 @@ let isBarrier = 1, isTerminator = 1 in { def : Pat<(trap), (BREAK (i32 1), (i32 15))>; +//===----------------------------------------------------------------------===// +// Exception feature instructions +//===----------------------------------------------------------------------===// + +def EXCW : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), + "excw", []>, Requires<[HasException]> { + let r = 0x2; + let s = 0x0; + let t = 0x8; +} + +def RFDE : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), + "rfde", []>, Requires<[HasException]> { + let r = 0x3; + let s = 0x2; + let t = 0x0; +} + + +def RFE : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), + "rfe", []>, Requires<[HasException]> { + let r = 0x3; + let s = 0x0; + let t = 0x0; +} + +def SYSCALL : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), + "syscall", []>, Requires<[HasException]> { + let r = 0x5; + let s = 0x0; + let t = 0x0; +} + +//===----------------------------------------------------------------------===// +// Interrupt feature instructions +//===----------------------------------------------------------------------===// + +def RSIL : RRR_Inst<0x00, 0x00, 0x00, (outs AR:$t), (ins uimm4:$imm), + "rsil\t$t, $imm", []>, Requires<[HasInterrupt]> { + bits<4> imm; + + let r = 0x6; + let s = imm{3-0}; +} + +def WAITI : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$imm), + "waiti\t$imm", []>, Requires<[HasInterrupt]> { + bits<4> imm; + + let r = 0x7; + let s = imm{3-0}; + let t = 0; +} + +def RFI : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$imm), + "rfi\t$imm", []>, Requires<[HasInterrupt]> { + bits<4> imm; + + let r = 0x3; + let s = imm{3-0}; + let t = 0x1; +} + +//===----------------------------------------------------------------------===// +// Region Protection feature instructions +//===----------------------------------------------------------------------===// + +def WDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s), + "wdtlb\t$t, $s", []>, Requires<[HasRegionProtection]> { + let r = 0xE; +} + +def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s), + "witlb\t$t, $s", []>, Requires<[HasRegionProtection]> { + let r = 0x6; +} + //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index b5d371c2e315a6..2fb153d065acaf 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -102,6 +102,8 @@ def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>; def ATOMCTL : SRReg<99, "atomctl", ["ATOMCTL", "99"]>; +def DDR : SRReg<104, "ddr", ["DDR", "104"]>; + // Instuction break address register 0 def IBREAKA0 : SRReg<128, "ibreaka0", ["IBREAKA0", "128"]>; @@ -120,20 +122,100 @@ def DBREAKC0 : SRReg<160, "dbreakc0", ["DBREAKC0", "160"]>; // Data breakpoint control register 1 def DBREAKC1 : SRReg<161, "dbreakc1", ["DBREAKC1", "161"]>; +def CONFIGID0 : SRReg<176, "configid0", ["CONFIGID0", "176"]>; + +// Exception PC1 +def EPC1 : SRReg<177, "epc1", ["EPC1", "177"]>; + +// Exception PC2 +def EPC2 : SRReg<178, "epc2", ["EPC2", "178"]>; + +// Exception PC3 +def EPC3 : SRReg<179, "epc3", ["EPC3", "179"]>; + +// Exception PC4 +def EPC4 : SRReg<180, "epc4", ["EPC4", "180"]>; + +// Exception PC5 +def EPC5 : SRReg<181, "epc5", ["EPC5", "181"]>; + +// Exception PC6 +def EPC6 : SRReg<182, "epc6", ["EPC6", "182"]>; + +// Exception PC7 +def EPC7 : SRReg<183, "epc7", ["EPC7", "183"]>; + +def DEPC : SRReg<192, "depc", ["DEPC", "192"]>; +def EPS2 : SRReg<194, "eps2", ["EPS2", "194"]>; +def EPS3 : SRReg<195, "eps3", ["EPS3", "195"]>; +def EPS4 : SRReg<196, "eps4", ["EPS4", "196"]>; +def EPS5 : SRReg<197, "eps5", ["EPS5", "197"]>; +def EPS6 : SRReg<198, "eps6", ["EPS6", "198"]>; +def EPS7 : SRReg<199, "eps7", ["EPS7", "199"]>; +def CONFIGID1 : SRReg<208, "configid1", ["CONFIGID1", "208"]>; +def EXCSAVE1 : SRReg<209, "excsave1", ["EXCSAVE1", "209"]>; +def EXCSAVE2 : SRReg<210, "excsave2", ["EXCSAVE2", "210"]>; +def EXCSAVE3 : SRReg<211, "excsave3", ["EXCSAVE3", "211"]>; +def EXCSAVE4 : SRReg<212, "excsave4", ["EXCSAVE4", "212"]>; +def EXCSAVE5 : SRReg<213, "excsave5", ["EXCSAVE5", "213"]>; +def EXCSAVE6 : SRReg<214, "excsave6", ["EXCSAVE6", "214"]>; +def EXCSAVE7 : SRReg<215, "excsave7", ["EXCSAVE7", "215"]>; +def CPENABLE : SRReg<224, "cpenable", ["CPENABLE", "224"]>; + +// Interrupt enable mask register +def INTSET : SRReg<226, "interrupt", ["INTERRUPT", "226"]>; + +def INTCLEAR : SRReg<227, "intclear", ["INTCLEAR", "227"]>; + +def INTENABLE : SRReg<228, "intenable", ["INTENABLE", "228"]>; + +// Processor State +def PS : SRReg<230, "ps", ["PS", "230"]>; + +// Vector base register +def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>; + +def EXCCAUSE : SRReg<232, "exccause", ["EXCCAUSE", "232"]>; + // Cause of last debug exception register def DEBUGCAUSE : SRReg<233, "debugcause", ["DEBUGCAUSE", "233"]>; +// Processor Clock Count Register +def CCOUNT : SRReg<234, "ccount", ["CCOUNT", "234"]>; + +// Processor ID Register +def PRID : SRReg<235, "prid", ["PRID", "235"]>; + def ICOUNT : SRReg<236, "icount", ["ICOUNT", "236"]>; def ICOUNTLEVEL : SRReg<237, "icountlevel", ["ICOUNTLEVEL", "237"]>; +def EXCVADDR : SRReg<238, "excvaddr", ["EXCVADDR", "238"]>; + +// Cycle number to interrupt register 0 +def CCOMPARE0 : SRReg<240, "ccompare0", ["CCOMPARE0", "240"]>; + +// Cycle number to interrupt register 1 +def CCOMPARE1 : SRReg<241, "ccompare1", ["CCOMPARE1", "241"]>; + +// Cycle number to interrupt register 2 +def CCOMPARE2 : SRReg<242, "ccompare2", ["CCOMPARE2", "242"]>; + +def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>; +def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>; +def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>; +def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>; def MR01 : RegisterClass<"Xtensa", [i32], 32, (add M0, M1)>; def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>; def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>; -def SR : RegisterClass<"Xtensa", [i32], 32, (add LBEG, LEND, LCOUNT, - SAR, BREG, LITBASE, SCOMPARE1, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART, - IBREAKENABLE, MEMCTL, ATOMCTL, IBREAKA0, IBREAKA1, DBREAKA0, DBREAKA1, - DBREAKC0, DBREAKC1, DEBUGCAUSE, ICOUNT, ICOUNTLEVEL)>; +def SR : RegisterClass<"Xtensa", [i32], 32, (add + LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, SCOMPARE1, ACCLO, ACCHI, MR, + WINDOWBASE, WINDOWSTART, IBREAKENABLE, MEMCTL, ATOMCTL, DDR, IBREAKA0, IBREAKA1, + DBREAKA0, DBREAKA1, DBREAKC0, DBREAKC1, CONFIGID0, EPC1, EPC2, EPC3, EPC4, EPC5, + EPC6, EPC7, DEPC, EPS2, EPS3, EPS4, EPS5, EPS6, EPS7, CONFIGID1, EXCSAVE1, EXCSAVE2, + EXCSAVE3, EXCSAVE4, EXCSAVE5, EXCSAVE6, EXCSAVE7, CPENABLE, INTSET, INTCLEAR, INTENABLE, PS, + VECBASE, EXCCAUSE, DEBUGCAUSE, CCOUNT, PRID, ICOUNT, ICOUNTLEVEL, EXCVADDR, CCOMPARE0, + CCOMPARE1, CCOMPARE2, MISC0, MISC1, MISC2, MISC3)>; //===----------------------------------------------------------------------===// // USER registers @@ -143,6 +225,8 @@ class URReg num, string n, list alt = []> : XtensaReg { let AltNames = alt; } +def EXPSTATE : URReg<230, "expstate", ["EXPSTATE"]>; + // Thread Pointer register def THREADPTR : URReg<231, "threadptr", ["THREADPTR"]>; @@ -152,7 +236,7 @@ def F64R_LO : URReg<234, "f64r_lo", ["F64R_LO"]>; def F64R_HI : URReg<235, "f64r_hi", ["F64R_HI"]>; def F64S : URReg<236, "f64s", ["F64S"]>; -def UR : RegisterClass<"Xtensa", [i32], 32, (add THREADPTR, FCR, +def UR : RegisterClass<"Xtensa", [i32], 32, (add EXPSTATE, THREADPTR, FCR, FSR, F64R_LO, F64R_HI, F64S)>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 800c62d9cefc6b..8c259dd33f2fa3 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -50,6 +50,15 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasATOMCTL = false; HasMEMCTL = false; HasDebug = false; + HasException = false; + HasHighPriInterrupts = false; + HasCoprocessor = false; + HasInterrupt = false; + HasRelocatableVector = false; + HasTimerInt = false; + HasPRID = false; + HasRegionProtection = false; + HasMiscSR = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index eed24f28be1532..8eb3281706cfe0 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -92,6 +92,33 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa Debug option bool HasDebug; + // Enable Xtensa Exceptions option + bool HasException; + + // Enable Xtensa High Priority Interrupt option + bool HasHighPriInterrupts; + + // Enable Xtensa Coprocessor option + bool HasCoprocessor; + + // Enable Xtensa Interrupt option + bool HasInterrupt; + + // Enable Xtensa Relocatable Vector option + bool HasRelocatableVector; + + // Enable Xtensa Timer Interrupt option + bool HasTimerInt; + + // Enable Xtensa Processor ID option + bool HasPRID; + + // Enable Xtensa Region Protection option + bool HasRegionProtection; + + // Enable Xtensa Miscellaneous Special Reigsiters option + bool HasMiscSR; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -145,6 +172,24 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasDebug() const { return HasDebug; } + bool hasException() const { return HasException; } + + bool hasHighPriInterrupts() const { return HasHighPriInterrupts; } + + bool hasCoprocessor() const { return HasCoprocessor; } + + bool hasInterrupt() const { return HasInterrupt; } + + bool hasRelocatableVector() const { return HasRelocatableVector; } + + bool hasTimerInt() const { return HasTimerInt; } + + bool hasPRID() const { return HasPRID; } + + bool hasRegionProtection() const { return HasRegionProtection; } + + bool hasMiscSR() const { return HasMiscSR; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; diff --git a/llvm/test/MC/Xtensa/xtensa-valid-exc.s b/llvm/test/MC/Xtensa/xtensa-valid-exc.s new file mode 100644 index 00000000000000..4d1e9198bd9ad8 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-exc.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+exception -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +.align 4 +LBL0: + +# CHECK-INST: excw +# CHECK: encoding: [0x80,0x20,0x00] + excw + +# CHECK-INST: rfde +# CHECK: encoding: [0x00,0x32,0x00] + rfde + +# CHECK-INST: rfe +# CHECK: encoding: [0x00,0x30,0x00] + rfe + +# CHECK-INST: syscall +# CHECK: encoding: [0x00,0x50,0x00] + syscall diff --git a/llvm/test/MC/Xtensa/xtensa-valid-int.s b/llvm/test/MC/Xtensa/xtensa-valid-int.s new file mode 100644 index 00000000000000..a24191ef4aa5a0 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-int.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+interrupt -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + + +.align 4 +LBL0: + +# CHECK-INST: rfi 1 +# CHECK: encoding: [0x10,0x31,0x00] + rfi 1 + +# CHECK-INST: rsil a3, 1 +# CHECK: encoding: [0x30,0x61,0x00] + rsil a3, 1 + +# CHECK-INST: waiti 1 +# CHECK: encoding: [0x00,0x71,0x00] + waiti 1 \ No newline at end of file diff --git a/llvm/test/MC/Xtensa/xtensa-valid-regprotect.s b/llvm/test/MC/Xtensa/xtensa-valid-regprotect.s new file mode 100644 index 00000000000000..b3504eef1d5576 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-regprotect.s @@ -0,0 +1,14 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+regprotect -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + + +.align 4 +LBL0: + +# CHECK-INST: wdtlb a3, a4 +# CHECK: encoding: [0x30,0xe4,0x50] + wdtlb a3, a4 + +# CHECK-INST: witlb a3, a4 +# CHECK: encoding: [0x30,0x64,0x50] + witlb a3, a4 From 7edb5a7c84da5a2c067693421c6f05aa3ed921de Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:37 +0300 Subject: [PATCH 035/261] [Xtensa] Add the Xtensa target. --- clang/include/clang/Basic/TargetInfo.h | 5 +- clang/lib/AST/ASTContext.cpp | 47 +++++++++ clang/lib/Basic/CMakeLists.txt | 1 + clang/lib/Basic/Targets.cpp | 4 + clang/lib/Basic/Targets/Xtensa.cpp | 29 ++++++ clang/lib/Basic/Targets/Xtensa.h | 108 +++++++++++++++++++++ clang/lib/Driver/ToolChains/CommonArgs.cpp | 5 + clang/lib/Driver/ToolChains/Gnu.cpp | 6 ++ 8 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 clang/lib/Basic/Targets/Xtensa.cpp create mode 100644 clang/lib/Basic/Targets/Xtensa.h diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 3eb23ebdacf0ed..5e4e0610945a08 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -350,7 +350,10 @@ class TargetInfo : public TransferrableTargetInfo, // void *__saved_reg_area_end_pointer; // void *__overflow_area_pointer; //} va_list; - HexagonBuiltinVaList + HexagonBuiltinVaList, + + // Tensilica Xtensa + XtensaABIBuiltinVaList }; protected: diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index cc5de9a6295ebf..947ff52bea9d1e 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -9083,6 +9083,51 @@ static TypedefDecl *CreateHexagonBuiltinVaListDecl(const ASTContext *Context) { return Context->buildImplicitTypedef(VaListTagArrayType, "__builtin_va_list"); } +static TypedefDecl * +CreateXtensaABIBuiltinVaListDecl(const ASTContext *Context) { + // typedef struct __va_list_tag { + RecordDecl *VaListTagDecl; + + VaListTagDecl = Context->buildImplicitRecord("__va_list_tag"); + VaListTagDecl->startDefinition(); + + const size_t NumFields = 3; + QualType FieldTypes[NumFields]; + const char *FieldNames[NumFields]; + + // int* __va_stk; + FieldTypes[0] = Context->getPointerType(Context->IntTy); + FieldNames[0] = "__va_stk"; + + // int* __va_reg; + FieldTypes[1] = Context->getPointerType(Context->IntTy); + FieldNames[1] = "__va_reg"; + + // int __va_ndx; + FieldTypes[2] = Context->IntTy; + FieldNames[2] = "__va_ndx"; + + // Create fields + for (unsigned i = 0; i < NumFields; ++i) { + FieldDecl *Field = FieldDecl::Create( + *Context, VaListTagDecl, SourceLocation(), SourceLocation(), + &Context->Idents.get(FieldNames[i]), FieldTypes[i], /*TInfo=*/nullptr, + /*BitWidth=*/nullptr, + /*Mutable=*/false, ICIS_NoInit); + Field->setAccess(AS_public); + VaListTagDecl->addDecl(Field); + } + VaListTagDecl->completeDefinition(); + Context->VaListTagDecl = VaListTagDecl; + QualType VaListTagType = Context->getRecordType(VaListTagDecl); + + // } __va_list_tag; + TypedefDecl *VaListTagTypedefDecl = + Context->buildImplicitTypedef(VaListTagType, "__builtin_va_list"); + + return VaListTagTypedefDecl; +} + static TypedefDecl *CreateVaListDecl(const ASTContext *Context, TargetInfo::BuiltinVaListKind Kind) { switch (Kind) { @@ -9104,6 +9149,8 @@ static TypedefDecl *CreateVaListDecl(const ASTContext *Context, return CreateSystemZBuiltinVaListDecl(Context); case TargetInfo::HexagonBuiltinVaList: return CreateHexagonBuiltinVaListDecl(Context); + case TargetInfo::XtensaABIBuiltinVaList: + return CreateXtensaABIBuiltinVaListDecl(Context); } llvm_unreachable("Unhandled __builtin_va_list type kind"); diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt index 2e218ba7c84cca..38d1e1b9f3df2b 100644 --- a/clang/lib/Basic/CMakeLists.txt +++ b/clang/lib/Basic/CMakeLists.txt @@ -119,6 +119,7 @@ add_clang_library(clangBasic Targets/WebAssembly.cpp Targets/X86.cpp Targets/XCore.cpp + Targets/Xtensa.cpp TokenKinds.cpp TypeTraits.cpp Version.cpp diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index e3283510c6aac7..0ff8025df08d0d 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -41,6 +41,7 @@ #include "Targets/WebAssembly.h" #include "Targets/X86.h" #include "Targets/XCore.h" +#include "Targets/Xtensa.h" #include "clang/Basic/Diagnostic.h" #include "clang/Basic/DiagnosticFrontend.h" #include "llvm/ADT/StringExtras.h" @@ -749,6 +750,9 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, default: return std::make_unique(Triple, Opts); } + + case llvm::Triple::xtensa : + return std::make_unique(Triple, Opts); } } } // namespace targets diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp new file mode 100644 index 00000000000000..270af0a05cfdcb --- /dev/null +++ b/clang/lib/Basic/Targets/Xtensa.cpp @@ -0,0 +1,29 @@ +//===--- Xtensa.cpp - Implement Xtensa target feature support -------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements Xtensa TargetInfo objects. +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "clang/Basic/Builtins.h" +#include "clang/Basic/MacroBuilder.h" +#include "clang/Basic/TargetBuiltins.h" + +using namespace clang; +using namespace clang::targets; + +void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const { + Builder.defineMacro("__Xtensa__"); + Builder.defineMacro("__xtensa__"); + Builder.defineMacro("__XTENSA__"); + Builder.defineMacro("__XTENSA_EL__"); +} diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h new file mode 100644 index 00000000000000..6a3f5441fc61ad --- /dev/null +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -0,0 +1,108 @@ +//===--- Xtensa.h - Declare Xtensa target feature support -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file declares Xtensa TargetInfo objects. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H +#define LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H + +#include "clang/Basic/TargetInfo.h" +#include "clang/Basic/TargetOptions.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/TargetParser/Triple.h" +#include "llvm/Support/Compiler.h" + +#include "clang/Basic/Builtins.h" +#include "clang/Basic/MacroBuilder.h" +#include "clang/Basic/TargetBuiltins.h" + +namespace clang { +namespace targets { + +class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { + static const Builtin::Info BuiltinInfo[]; + std::string CPU; + +public: + XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &) + : TargetInfo(Triple) { + BigEndian = false; + NoAsmVariants = true; + LongLongAlign = 64; + SuitableAlign = 32; + DoubleAlign = LongDoubleAlign = 64; + SizeType = UnsignedInt; + PtrDiffType = SignedInt; + IntPtrType = SignedInt; + WCharType = UnsignedChar; + WIntType = UnsignedInt; + UseZeroLengthBitfieldAlignment = true; + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; + resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32"); + } + + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override; + + ArrayRef getTargetBuiltins() const override { + return std::nullopt; + } + + BuiltinVaListKind getBuiltinVaListKind() const override { + + return TargetInfo::XtensaABIBuiltinVaList; + } + + std::string_view getClobbers() const override { return ""; } + + ArrayRef getGCCRegNames() const override { + static const char *const GCCRegNames[] = { + // General register name + "a0", "sp", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10", + "a11", "a12", "a13", "a14", "a15", + // Special register name + "sar"}; + return llvm::ArrayRef(GCCRegNames); + } + + ArrayRef getGCCRegAliases() const override { + return std::nullopt; + } + + bool validateAsmConstraint(const char *&Name, + TargetInfo::ConstraintInfo &Info) const override { + switch (*Name) { + default: + return false; + case 'a': + Info.setAllowsRegister(); + return true; + } + return false; + } + + int getEHDataRegisterNumber(unsigned RegNo) const override { + return (RegNo < 2) ? RegNo : -1; + } + + bool isValidCPUName(StringRef Name) const override { + return llvm::StringSwitch(Name).Case("generic", true).Default(false); + } + + bool setCPU(const std::string &Name) override { + CPU = Name; + return isValidCPUName(Name); + } +}; +} // namespace targets +} // namespace clang +#endif // LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 2b916f0003368d..b2cc999810b856 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -618,6 +618,11 @@ std::string tools::getCPUName(const Driver &D, const ArgList &Args, case llvm::Triple::loongarch32: case llvm::Triple::loongarch64: return loongarch::getLoongArchTargetCPU(Args, T); + + case llvm::Triple::xtensa: + if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) + return A->getValue(); + return ""; } } diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index e5e1b1d772697e..b5befefe6d29ef 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -2572,6 +2572,8 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( "s390x-linux-gnu", "s390x-unknown-linux-gnu", "s390x-ibm-linux-gnu", "s390x-suse-linux", "s390x-redhat-linux"}; + static const char *const XtensaLibDirs[] = {"/lib"}; + static const char *const XtensaTriples[] = {"xtensa-unknown-elf"}; using std::begin; using std::end; @@ -2844,6 +2846,10 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( LibDirs.append(begin(SystemZLibDirs), end(SystemZLibDirs)); TripleAliases.append(begin(SystemZTriples), end(SystemZTriples)); break; + case llvm::Triple::xtensa: + LibDirs.append(begin(XtensaLibDirs), end(XtensaLibDirs)); + TripleAliases.append(begin(XtensaTriples), end(XtensaTriples)); + break; default: // By default, just rely on the standard lib directories and the original // triple. From 3a52eb4e62c7b33739a35fe73cd58d3469c2773a Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:37 +0300 Subject: [PATCH 036/261] [Xtensa] Implement Xtensa ABI lowering. --- clang/lib/CodeGen/CMakeLists.txt | 1 + clang/lib/CodeGen/CodeGenModule.cpp | 2 + clang/lib/CodeGen/TargetInfo.h | 3 + clang/lib/CodeGen/Targets/Xtensa.cpp | 241 +++++++++++++++++++++++++++ 4 files changed, 247 insertions(+) create mode 100644 clang/lib/CodeGen/Targets/Xtensa.cpp diff --git a/clang/lib/CodeGen/CMakeLists.txt b/clang/lib/CodeGen/CMakeLists.txt index 52216d93a302bb..0806395479619a 100644 --- a/clang/lib/CodeGen/CMakeLists.txt +++ b/clang/lib/CodeGen/CMakeLists.txt @@ -138,6 +138,7 @@ add_clang_library(clangCodeGen Targets/WebAssembly.cpp Targets/X86.cpp Targets/XCore.cpp + Targets/Xtensa.cpp VarBypassDetector.cpp DEPENDS diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 1280bcd36de943..b740adecf1b6a8 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -316,6 +316,8 @@ createTargetCodeGenInfo(CodeGenModule &CGM) { return createLoongArchTargetCodeGenInfo( CGM, Target.getPointerWidth(LangAS::Default), ABIFRLen); } + case llvm::Triple::xtensa: + return createXtensaTargetCodeGenInfo(CGM); } } diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h index 7682f197041c74..d325a1d6256202 100644 --- a/clang/lib/CodeGen/TargetInfo.h +++ b/clang/lib/CodeGen/TargetInfo.h @@ -554,6 +554,9 @@ createWinX86_64TargetCodeGenInfo(CodeGenModule &CGM, X86AVXABILevel AVXLevel); std::unique_ptr createXCoreTargetCodeGenInfo(CodeGenModule &CGM); +std::unique_ptr +createXtensaTargetCodeGenInfo(CodeGenModule &CGM); + } // namespace CodeGen } // namespace clang diff --git a/clang/lib/CodeGen/Targets/Xtensa.cpp b/clang/lib/CodeGen/Targets/Xtensa.cpp new file mode 100644 index 00000000000000..5bec6c493aeaa5 --- /dev/null +++ b/clang/lib/CodeGen/Targets/Xtensa.cpp @@ -0,0 +1,241 @@ +//===- Xtensa.cpp ---------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ABIInfoImpl.h" +#include "TargetInfo.h" + +using namespace clang; +using namespace clang::CodeGen; +//===----------------------------------------------------------------------===// +// Xtensa ABI Implementation +//===----------------------------------------------------------------------===// + +namespace { +class XtensaABIInfo : public DefaultABIInfo { +private: + static const int MaxNumArgGPRs = 6; + static const int MaxNumRetGPRs = 4; + +public: + XtensaABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} + + // DefaultABIInfo's classifyReturnType and classifyArgumentType are + // non-virtual, but computeInfo is virtual, so we overload it. + void computeInfo(CGFunctionInfo &FI) const override; + + ABIArgInfo classifyArgumentType(QualType Ty, int &ArgGPRsLeft) const; + + ABIArgInfo classifyReturnType(QualType RetTy) const; + + Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, + QualType Ty) const override; + + ABIArgInfo extendType(QualType Ty) const; +}; +} // end anonymous namespace + +void XtensaABIInfo::computeInfo(CGFunctionInfo &FI) const { + QualType RetTy = FI.getReturnType(); + if (!getCXXABI().classifyReturnType(FI)) + FI.getReturnInfo() = classifyReturnType(RetTy); + + int ArgGPRsLeft = MaxNumArgGPRs; + for (auto &ArgInfo : FI.arguments()) { + ArgInfo.info = classifyArgumentType(ArgInfo.type, ArgGPRsLeft); + } +} + +ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty, + int &ArgGPRsLeft) const { + assert(ArgGPRsLeft <= MaxNumArgGPRs && "Arg GPR tracking underflow"); + Ty = useFirstFieldIfTransparentUnion(Ty); + // Structures with either a non-trivial destructor or a non-trivial + // copy constructor are always passed indirectly. + if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) { + if (ArgGPRsLeft) + ArgGPRsLeft -= 1; + return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA == + CGCXXABI::RAA_DirectInMemory); + } + + // Ignore empty structs/unions. + if (isEmptyRecord(getContext(), Ty, true)) + return ABIArgInfo::getIgnore(); + + uint64_t Size = getContext().getTypeSize(Ty); + uint64_t NeededAlign = getContext().getTypeAlign(Ty); + bool MustUseStack = false; + int NeededArgGPRs = (Size + 31) / 32; + + if (NeededAlign == (2 * 32)) + NeededArgGPRs += (ArgGPRsLeft % 2); + + // Put on stack objects which are not fit to 6 registers, + // also on stack object which alignment more then 16 bytes and + // object with 16-byte alignment if it isn't the first argument. + if ((NeededArgGPRs > ArgGPRsLeft) || (NeededAlign > (4 * 32)) || + ((ArgGPRsLeft < 6) && (NeededAlign == (4 * 32)))) { + MustUseStack = true; + NeededArgGPRs = ArgGPRsLeft; + } + ArgGPRsLeft -= NeededArgGPRs; + + if (!isAggregateTypeForABI(Ty) && !Ty->isVectorType() && !MustUseStack) { + // Treat an enum type as its underlying type. + if (const EnumType *EnumTy = Ty->getAs()) + Ty = EnumTy->getDecl()->getIntegerType(); + // All integral types are promoted to XLen width, unless passed on the + // stack. + if (Size < 32 && Ty->isIntegralOrEnumerationType() && !MustUseStack) { + return extendType(Ty); + } + if (Size == 64) + return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64)); + return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 32)); + } + + // Aggregates which are <= 6*32 will be passed in registers if possible, + // so coerce to integers. + if ((Size <= (MaxNumArgGPRs * 32)) && (!MustUseStack)) { + if (Size <= 32) { + return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 32)); + } else if (NeededAlign == (2 * 32)) { + return ABIArgInfo::getDirect(llvm::ArrayType::get( + llvm::IntegerType::get(getVMContext(), 64), NeededArgGPRs / 2)); + } else { + return ABIArgInfo::getDirect(llvm::ArrayType::get( + llvm::IntegerType::get(getVMContext(), 32), NeededArgGPRs)); + } + } +#undef MAX_STRUCT_IN_REGS_SIZE + return getNaturalAlignIndirect(Ty, /*ByVal=*/true); +} + +ABIArgInfo XtensaABIInfo::classifyReturnType(QualType RetTy) const { + if (RetTy->isVoidType()) + return ABIArgInfo::getIgnore(); + int ArgGPRsLeft = MaxNumRetGPRs; + // The rules for return and argument types are the same, so defer to + // classifyArgumentType. + return classifyArgumentType(RetTy, ArgGPRsLeft); +} + +Address XtensaABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, + QualType Ty) const { + // The va_list structure memory layout: + // struct __va_list_tag { + // int32_t *va_stk; + // int32_t *va_reg; + // int32_t va_ndx; + // }; + CGBuilderTy &Builder = CGF.Builder; + + Address OverflowAreaPtr = Builder.CreateStructGEP(VAListAddr, 0, "__va_stk"); + Address OverflowArea = Address(Builder.CreateLoad(OverflowAreaPtr, ""), + CGF.Int32Ty, CharUnits::fromQuantity(4)); + Address RegSaveAreaPtr = Builder.CreateStructGEP(VAListAddr, 1, "__va_reg"); + Address RegSaveArea = Address(Builder.CreateLoad(RegSaveAreaPtr, ""), + CGF.Int32Ty, CharUnits::fromQuantity(4)); + Address ARAreaPtr = Builder.CreateStructGEP(VAListAddr, 2, "__va_ndx"); + llvm::Value *ARIndex = Builder.CreateLoad(ARAreaPtr, ""); + + ARIndex = Builder.CreateLShr(ARIndex, Builder.getInt32(2)); + + unsigned Align = getContext().getTypeAlign(Ty) / 32; + unsigned Size = (getContext().getTypeSize(Ty) + 31) / 32; + + if (Align > 1) { + ARIndex = Builder.CreateAdd(ARIndex, Builder.getInt32(Align - 1)); + ARIndex = + Builder.CreateAnd(ARIndex, Builder.getInt32((uint32_t) ~(Align - 1))); + } + + llvm::Value *ARIndexNext = Builder.CreateAdd(ARIndex, Builder.getInt32(Size)); + Builder.CreateStore(Builder.CreateShl(ARIndexNext, Builder.getInt32(2)), + ARAreaPtr); + + const unsigned OverflowLimit = 6; + llvm::Value *CC = Builder.CreateICmpULE( + ARIndexNext, Builder.getInt32(OverflowLimit), "cond"); + + llvm::BasicBlock *UsingRegSaveArea = + CGF.createBasicBlock("using_regsavearea"); + llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow"); + llvm::BasicBlock *Cont = CGF.createBasicBlock("cont"); + + Builder.CreateCondBr(CC, UsingRegSaveArea, UsingOverflow); + + llvm::Type *DirectTy = CGF.ConvertType(Ty); + + // Case 1: consume registers. + Address RegAddr = Address::invalid(); + { + CGF.EmitBlock(UsingRegSaveArea); + + CharUnits RegSize = CharUnits::fromQuantity(4); + RegSaveArea = + Address(Builder.CreateInBoundsGEP(CGF.Int32Ty, RegSaveArea.getPointer(), + ARIndex), + CGF.Int32Ty, RegSaveArea.getAlignment().alignmentOfArrayElement(RegSize)); + RegAddr = RegSaveArea.withElementType(DirectTy); + CGF.EmitBranch(Cont); + } + + // Case 2: consume space in the overflow area. + Address MemAddr = Address::invalid(); + { + CGF.EmitBlock(UsingOverflow); + llvm::Value *CC1 = Builder.CreateICmpULE( + ARIndex, Builder.getInt32(OverflowLimit), "cond_overflow"); + + llvm::Value *ARIndexOff = Builder.CreateSelect( + CC1, Builder.CreateSub(Builder.getInt32(8), ARIndex), + Builder.getInt32(0)); + + llvm::Value *ARIndexCorr = Builder.CreateAdd(ARIndex, ARIndexOff); + llvm::Value *ARIndexNextCorr = Builder.CreateAdd(ARIndexNext, ARIndexOff); + Builder.CreateStore(Builder.CreateShl(ARIndexNextCorr, Builder.getInt32(2)), + ARAreaPtr); + + CharUnits RegSize = CharUnits::fromQuantity(4); + OverflowArea = + Address(Builder.CreateInBoundsGEP( + CGF.Int32Ty, OverflowArea.getPointer(), ARIndexCorr), + CGF.Int32Ty, OverflowArea.getAlignment().alignmentOfArrayElement(RegSize)); + MemAddr = OverflowArea.withElementType(DirectTy); + CGF.EmitBranch(Cont); + } + + CGF.EmitBlock(Cont); + + // Merge the cases with a phi. + Address Result = + emitMergePHI(CGF, RegAddr, UsingRegSaveArea, MemAddr, UsingOverflow, ""); + + return Result; +} + +ABIArgInfo XtensaABIInfo::extendType(QualType Ty) const { + return ABIArgInfo::getExtend(Ty); +} + +namespace { +class XtensaTargetCodeGenInfo : public TargetCodeGenInfo { +public: + XtensaTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) + : TargetCodeGenInfo(std::make_unique(CGT)) {} +}; +} // namespace + + +std::unique_ptr +CodeGen::createXtensaTargetCodeGenInfo(CodeGenModule &CGM) { + return std::make_unique(CGM.getTypes()); +} + + From 7777687f8516451de988f9598bbdee54bb4cffc2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:37 +0300 Subject: [PATCH 037/261] [Xtensa] Add subtargets ESP32. ESP8266 and ESP32-S2. Make ESP32 default subtarget. --- llvm/lib/Target/Xtensa/Xtensa.td | 12 ++++++++++++ llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index f141a6db02b508..b17442717c21ee 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -161,6 +161,18 @@ class Proc Features> def : Proc<"generic", []>; +def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, + FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, + FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, + FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR]>; + +def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException, FeatureHighPriInterrupts, + FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>; + +def : Proc<"esp32-s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, FeatureDiv32, + FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, + FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR]>; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 8c259dd33f2fa3..106884d8a0311f 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -29,7 +29,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { StringRef CPUName = CPU; if (CPUName.empty()) { // set default cpu name - CPUName = "generic"; + CPUName = "esp32"; } HasDensity = false; From aa4036663acf6d71d3a7ce7766038d235da3f474 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:38 +0300 Subject: [PATCH 038/261] [Xtensa] Add esp32, esp8266 and esp32-s2 to valid cpu names. --- clang/lib/Basic/Targets/Xtensa.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index 6a3f5441fc61ad..76ec5dc6c00337 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -95,7 +95,12 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { } bool isValidCPUName(StringRef Name) const override { - return llvm::StringSwitch(Name).Case("generic", true).Default(false); + return llvm::StringSwitch(Name) + .Case("esp32", true) + .Case("esp8266", true) + .Case("esp32-s2", true) + .Case("generic", true) + .Default(false); } bool setCPU(const std::string &Name) override { From fd5371afa760a70c29990169977a8249d9fc2e5c Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:38 +0300 Subject: [PATCH 039/261] [Xtensa] Improve parsing of the SR and UR registers. Implement subtarget dependent SR and UR register parsing and disassembling, add tests. Implement User Registers read/write instructions and add tests. --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 314 +++++++++++++++++- .../Disassembler/XtensaDisassembler.cpp | 180 +++++++++- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 35 ++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 3 +- llvm/test/MC/Xtensa/Core/processor-control.s | 8 + 5 files changed, 522 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index f2b2bcc877c815..389af6be4b225d 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -50,11 +50,12 @@ class XtensaAsmParser : public MCTargetAsmParser { #include "XtensaGenAsmMatcher.inc" ParseStatus parseImmediate(OperandVector &Operands); - ParseStatus parseRegister(OperandVector &Operands, bool AllowParens = false, - bool SR = false); + ParseStatus parseRegister(OperandVector &Operands, + bool AllowParens = false, bool SR = false, + bool UR = false); ParseStatus parseOperandWithModifier(OperandVector &Operands); bool parseOperand(OperandVector &Operands, StringRef Mnemonic, - bool SR = false); + bool SR = false, bool UR = false); bool ParseInstructionWithSR(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands); ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, @@ -62,6 +63,7 @@ class XtensaAsmParser : public MCTargetAsmParser { return ParseStatus::NoMatch; } ParseStatus parsePCRelTarget(OperandVector &Operands); + bool checkRegister(unsigned RegNo); public: enum XtensaMatchResultTy { @@ -76,6 +78,86 @@ class XtensaAsmParser : public MCTargetAsmParser { : MCTargetAsmParser(Options, STI, MII) { setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } + + bool hasWindowed() const { + return getSTI().getFeatureBits()[Xtensa::FeatureWindowed]; + }; + + bool hasSingleFloat() const { + return getSTI().getFeatureBits()[Xtensa::FeatureSingleFloat]; + }; + + bool hasLoop() const { + return getSTI().getFeatureBits()[Xtensa::FeatureLoop]; + }; + + bool hasMAC16() const { + return getSTI().getFeatureBits()[Xtensa::FeatureMAC16]; + }; + + bool hasBoolean() const { + return getSTI().getFeatureBits()[Xtensa::FeatureBoolean]; + }; + + bool hasDFPAccel() const { + return getSTI().getFeatureBits()[Xtensa::FeatureDFPAccel]; + }; + + bool hasS32C1I() const { + return getSTI().getFeatureBits()[Xtensa::FeatureS32C1I]; + }; + + bool hasTHREADPTR() const { + return getSTI().getFeatureBits()[Xtensa::FeatureTHREADPTR]; + }; + + bool hasExtendedL32R() const { + return getSTI().getFeatureBits()[Xtensa::FeatureExtendedL32R]; + } + + bool hasATOMCTL() const { + return getSTI().getFeatureBits()[Xtensa::FeatureATOMCTL]; + } + + bool hasMEMCTL() const { + return getSTI().getFeatureBits()[Xtensa::FeatureMEMCTL]; + } + + bool hasDebug() const { + return getSTI().getFeatureBits()[Xtensa::FeatureDebug]; + } + + bool hasException() const { + return getSTI().getFeatureBits()[Xtensa::FeatureException]; + } + + bool hasHighPriInterrupts() const { + return getSTI().getFeatureBits()[Xtensa::FeatureHighPriInterrupts]; + } + + bool hasCoprocessor() const { + return getSTI().getFeatureBits()[Xtensa::FeatureCoprocessor]; + } + + bool hasInterrupt() const { + return getSTI().getFeatureBits()[Xtensa::FeatureInterrupt]; + } + + bool hasRelocatableVector() const { + return getSTI().getFeatureBits()[Xtensa::FeatureRelocatableVector]; + } + + bool hasTimerInt() const { + return getSTI().getFeatureBits()[Xtensa::FeatureTimerInt]; + } + + bool hasPRID() const { + return getSTI().getFeatureBits()[Xtensa::FeaturePRID]; + } + + bool hasMiscSR() const { + return getSTI().getFeatureBits()[Xtensa::FeatureMiscSR]; + } }; // Return true if Expr is in the range [MinValue, MaxValue]. @@ -500,17 +582,19 @@ bool XtensaAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, } ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, - bool AllowParens, bool SR) { + bool AllowParens, bool SR, + bool UR) { SMLoc FirstS = getLoc(); bool HadParens = false; AsmToken Buf[2]; - StringRef RegName; + std::string RegName = ""; + int64_t Num; // If this a parenthesised register name is allowed, parse it atomically if (AllowParens && getLexer().is(AsmToken::LParen)) { size_t ReadCount = getLexer().peekTokens(Buf); if (ReadCount == 2 && Buf[1].getKind() == AsmToken::RParen) { - if ((Buf[0].getKind() == AsmToken::Integer) && (!SR)) + if ((Buf[0].getKind() == AsmToken::Integer) && (!SR) && (!UR)) return ParseStatus::NoMatch; HadParens = true; getParser().Lex(); // Eat '(' @@ -523,15 +607,38 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, default: return ParseStatus::NoMatch; case AsmToken::Integer: - if (!SR) + if ((!SR) && (!UR)) return ParseStatus::NoMatch; - RegName = StringRef(std::to_string(getLexer().getTok().getIntVal())); + + Num = getLexer().getTok().getIntVal(); + // Parse case when we expect UR operand as special case, + // because SR and UR registers may have the same number + // and such situation may lead to confilct + if (UR) { + if (Num == 0) + RegName = "GPIO_OUT"; + if (Num == 230) + RegName = "EXPSTATE"; + if (Num == 231) + RegName = "THREADPTR"; + if (Num == 232) + RegName = "FCR"; + if (Num == 233) + RegName = "FSR"; + if (Num == 234) + RegName = "F64R_LO"; + if (Num == 235) + RegName = "F64R_HI"; + if (Num == 236) + RegName = "F64S"; + } else + RegName = std::to_string(Num); RegNo = MatchRegisterName(RegName); if (RegNo == 0) RegNo = MatchRegisterAltName(RegName); break; case AsmToken::Identifier: - RegName = getLexer().getTok().getIdentifier(); + RegName = getLexer().getTok().getIdentifier().str(); RegNo = MatchRegisterName(RegName); if (RegNo == 0) RegNo = MatchRegisterAltName(RegName); @@ -543,6 +650,11 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, getLexer().UnLex(Buf[0]); return ParseStatus::NoMatch; } + + if (!checkRegister(RegNo)) { + return ParseStatus::NoMatch; + } + if (HadParens) Operands.push_back(XtensaOperand::createToken("(", FirstS)); SMLoc S = getLoc(); @@ -601,7 +713,7 @@ ParseStatus XtensaAsmParser::parseOperandWithModifier(OperandVector &Operands) { /// from this information, adding to Operands. /// If operand was parsed, returns false, else true. bool XtensaAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, - bool SR) { + bool SR, bool UR) { // Check if the current operand has a custom associated parser, if so, try to // custom parse the operand, or fallback to the general approach. ParseStatus Res = MatchOperandParserImpl(Operands, Mnemonic); @@ -615,7 +727,7 @@ bool XtensaAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, return true; // Attempt to parse token as register - if (parseRegister(Operands, true, SR).isSuccess()) + if (parseRegister(Operands, true, SR, UR).isSuccess()) return false; // Attempt to parse token as an immediate @@ -629,8 +741,13 @@ bool XtensaAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, bool XtensaAsmParser::ParseInstructionWithSR(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { + bool IsSR = Name.starts_with("wsr") || Name.starts_with("rsr") || + Name.starts_with("xsr"); + bool IsUR = Name.starts_with("wur") || Name.starts_with("rur"); + if ((Name.starts_with("wsr.") || Name.starts_with("rsr.") || - Name.starts_with("xsr.")) && + Name.starts_with("xsr.") || Name.starts_with("rur.") || + Name.starts_with("wur.")) && (Name.size() > 4)) { // Parse case when instruction name is concatenated with SR register // name, like "wsr.sar a1" @@ -647,6 +764,11 @@ bool XtensaAsmParser::ParseInstructionWithSR(ParseInstructionInfo &Info, if (RegNo == 0) return Error(NameLoc, "invalid register name"); + if (!checkRegister(RegNo)) { + Error(NameLoc, "invalid register name"); + return true; + } + // Parse operand if (parseOperand(Operands, Name)) return true; @@ -669,7 +791,7 @@ bool XtensaAsmParser::ParseInstructionWithSR(ParseInstructionInfo &Info, } // Parse second operand - if (parseOperand(Operands, Name, true)) + if (parseOperand(Operands, Name, IsSR, IsUR)) return true; } @@ -687,7 +809,8 @@ bool XtensaAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { if (Name.starts_with("wsr") || Name.starts_with("rsr") || - Name.starts_with("xsr")) { + Name.starts_with("xsr") || Name.starts_with("rur") || + Name.starts_with("wur")) { return ParseInstructionWithSR(Info, Name, NameLoc, Operands); } @@ -716,6 +839,169 @@ bool XtensaAsmParser::ParseInstruction(ParseInstructionInfo &Info, getParser().Lex(); // Consume the EndOfStatement. return false; } + +// Verify SR and UR +bool XtensaAsmParser::checkRegister(unsigned RegNo) { + StringRef CPU = getSTI().getCPU(); + unsigned NumIntLevels = 0; + unsigned NumTimers = 0; + unsigned NumMiscSR = 0; + bool IsESP32 = false; + bool IsESP32_S2 = false; + bool Res = true; + + // Assume that CPU is esp32 by default + if ((CPU == "esp32") || (CPU == "")) { + NumIntLevels = 6; + NumTimers = 3; + NumMiscSR = 4; + IsESP32 = true; + } else if (CPU == "esp32-s2") { + NumIntLevels = 6; + NumTimers = 3; + NumMiscSR = 4; + IsESP32_S2 = true; + } else if (CPU == "esp8266") { + NumIntLevels = 2; + NumTimers = 1; + } + + switch (RegNo) { + case Xtensa::LBEG: + case Xtensa::LEND: + case Xtensa::LCOUNT: + Res = hasLoop(); + break; + case Xtensa::BREG: + Res = hasBoolean(); + break; + case Xtensa::LITBASE: + Res = hasExtendedL32R(); + break; + case Xtensa::SCOMPARE1: + Res = hasS32C1I(); + break; + case Xtensa::ACCLO: + case Xtensa::ACCHI: + case Xtensa::M0: + case Xtensa::M1: + case Xtensa::M2: + case Xtensa::M3: + Res = hasMAC16(); + break; + case Xtensa::WINDOWBASE: + case Xtensa::WINDOWSTART: + Res = hasWindowed(); + break; + case Xtensa::IBREAKENABLE: + case Xtensa::IBREAKA0: + case Xtensa::IBREAKA1: + case Xtensa::DBREAKA0: + case Xtensa::DBREAKA1: + case Xtensa::DBREAKC0: + case Xtensa::DBREAKC1: + case Xtensa::DEBUGCAUSE: + case Xtensa::ICOUNT: + case Xtensa::ICOUNTLEVEL: + Res = hasDebug(); + break; + case Xtensa::ATOMCTL: + Res = hasATOMCTL(); + break; + case Xtensa::MEMCTL: + Res = hasMEMCTL(); + break; + case Xtensa::EPC1: + Res = hasException(); + break; + case Xtensa::EPC2: + case Xtensa::EPC3: + case Xtensa::EPC4: + case Xtensa::EPC5: + case Xtensa::EPC6: + case Xtensa::EPC7: + Res = hasHighPriInterrupts(); + Res = Res & (NumIntLevels >= (RegNo - Xtensa::EPC1)); + break; + case Xtensa::EPS2: + case Xtensa::EPS3: + case Xtensa::EPS4: + case Xtensa::EPS5: + case Xtensa::EPS6: + case Xtensa::EPS7: + Res = hasHighPriInterrupts(); + Res = Res & (NumIntLevels > (RegNo - Xtensa::EPS2)); + break; + case Xtensa::EXCSAVE1: + Res = hasException(); + break; + case Xtensa::EXCSAVE2: + case Xtensa::EXCSAVE3: + case Xtensa::EXCSAVE4: + case Xtensa::EXCSAVE5: + case Xtensa::EXCSAVE6: + case Xtensa::EXCSAVE7: + Res = hasHighPriInterrupts(); + Res = Res & (NumIntLevels >= (RegNo - Xtensa::EXCSAVE1)); + break; + case Xtensa::DEPC: + case Xtensa::EXCCAUSE: + case Xtensa::EXCVADDR: + Res = hasException(); + break; + case Xtensa::CPENABLE: + Res = hasCoprocessor(); + break; + case Xtensa::VECBASE: + Res = hasRelocatableVector(); + break; + case Xtensa::CCOUNT: + Res = hasTimerInt(); + Res &= (NumTimers > 0); + break; + case Xtensa::CCOMPARE0: + case Xtensa::CCOMPARE1: + case Xtensa::CCOMPARE2: + Res = hasTimerInt(); + Res &= (NumTimers > (RegNo - Xtensa::CCOMPARE0)); + break; + case Xtensa::PRID: + Res = hasPRID(); + break; + case Xtensa::INTSET: + case Xtensa::INTCLEAR: + case Xtensa::INTENABLE: + Res = hasInterrupt(); + break; + case Xtensa::MISC0: + case Xtensa::MISC1: + case Xtensa::MISC2: + case Xtensa::MISC3: + Res = hasMiscSR(); + Res &= (NumMiscSR > (RegNo - Xtensa::MISC0)); + break; + case Xtensa::THREADPTR: + Res = hasTHREADPTR(); + break; + case Xtensa::GPIO_OUT: + Res = IsESP32_S2; + break; + case Xtensa::EXPSTATE: + Res = IsESP32; + break; + case Xtensa::FCR: + case Xtensa::FSR: + Res = hasSingleFloat(); + break; + case Xtensa::F64R_LO: + case Xtensa::F64R_HI: + case Xtensa::F64S: + Res = hasDFPAccel(); + break; + } + + return Res; +} // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmParser() { diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index d4d84b47f96cab..c10c31d4f0164c 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -147,6 +147,169 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Success; } +// Verify SR and UR +bool CheckRegister(unsigned RegNo, MCSubtargetInfo STI) { + StringRef CPU = STI.getCPU(); + unsigned NumIntLevels = 0; + unsigned NumTimers = 0; + unsigned NumMiscSR = 0; + bool IsESP32 = false; + bool IsESP32_S2 = false; + bool Res = true; + + // Assume that CPU is esp32 by default + if ((CPU == "esp32") || (CPU == "")) { + NumIntLevels = 6; + NumTimers = 3; + NumMiscSR = 4; + IsESP32 = true; + } else if (CPU == "esp32-s2") { + NumIntLevels = 6; + NumTimers = 3; + NumMiscSR = 4; + IsESP32_S2 = true; + } else if (CPU == "esp8266") { + NumIntLevels = 2; + NumTimers = 1; + } + + switch (RegNo) { + case Xtensa::LBEG: + case Xtensa::LEND: + case Xtensa::LCOUNT: + Res = STI.getFeatureBits()[Xtensa::FeatureLoop]; + break; + case Xtensa::BREG: + Res = STI.getFeatureBits()[Xtensa::FeatureBoolean]; + break; + case Xtensa::LITBASE: + Res = STI.getFeatureBits()[Xtensa::FeatureExtendedL32R]; + break; + case Xtensa::SCOMPARE1: + Res = STI.getFeatureBits()[Xtensa::FeatureS32C1I]; + break; + case Xtensa::ACCLO: + case Xtensa::ACCHI: + case Xtensa::M0: + case Xtensa::M1: + case Xtensa::M2: + case Xtensa::M3: + Res = STI.getFeatureBits()[Xtensa::FeatureMAC16]; + break; + case Xtensa::WINDOWBASE: + case Xtensa::WINDOWSTART: + Res = STI.getFeatureBits()[Xtensa::FeatureWindowed]; + break; + case Xtensa::IBREAKENABLE: + case Xtensa::IBREAKA0: + case Xtensa::IBREAKA1: + case Xtensa::DBREAKA0: + case Xtensa::DBREAKA1: + case Xtensa::DBREAKC0: + case Xtensa::DBREAKC1: + case Xtensa::DEBUGCAUSE: + case Xtensa::ICOUNT: + case Xtensa::ICOUNTLEVEL: + Res = STI.getFeatureBits()[Xtensa::FeatureDebug]; + break; + case Xtensa::ATOMCTL: + Res = STI.getFeatureBits()[Xtensa::FeatureATOMCTL]; + break; + case Xtensa::MEMCTL: + Res = STI.getFeatureBits()[Xtensa::FeatureMEMCTL]; + break; + case Xtensa::EPC1: + Res = STI.getFeatureBits()[Xtensa::FeatureException]; + break; + case Xtensa::EPC2: + case Xtensa::EPC3: + case Xtensa::EPC4: + case Xtensa::EPC5: + case Xtensa::EPC6: + case Xtensa::EPC7: + Res = STI.getFeatureBits()[Xtensa::FeatureHighPriInterrupts]; + Res = Res & (NumIntLevels >= (RegNo - Xtensa::EPC1)); + break; + case Xtensa::EPS2: + case Xtensa::EPS3: + case Xtensa::EPS4: + case Xtensa::EPS5: + case Xtensa::EPS6: + case Xtensa::EPS7: + Res = STI.getFeatureBits()[Xtensa::FeatureHighPriInterrupts]; + Res = Res & (NumIntLevels > (RegNo - Xtensa::EPS2)); + break; + case Xtensa::EXCSAVE1: + Res = STI.getFeatureBits()[Xtensa::FeatureException]; + break; + case Xtensa::EXCSAVE2: + case Xtensa::EXCSAVE3: + case Xtensa::EXCSAVE4: + case Xtensa::EXCSAVE5: + case Xtensa::EXCSAVE6: + case Xtensa::EXCSAVE7: + Res = STI.getFeatureBits()[Xtensa::FeatureHighPriInterrupts]; + Res = Res & (NumIntLevels >= (RegNo - Xtensa::EXCSAVE1)); + break; + case Xtensa::DEPC: + case Xtensa::EXCCAUSE: + case Xtensa::EXCVADDR: + Res = STI.getFeatureBits()[Xtensa::FeatureException]; + break; + case Xtensa::CPENABLE: + Res = STI.getFeatureBits()[Xtensa::FeatureCoprocessor]; + break; + case Xtensa::VECBASE: + Res = STI.getFeatureBits()[Xtensa::FeatureRelocatableVector]; + break; + case Xtensa::CCOUNT: + Res = STI.getFeatureBits()[Xtensa::FeatureTimerInt]; + Res &= (NumTimers > 0); + break; + case Xtensa::CCOMPARE0: + case Xtensa::CCOMPARE1: + case Xtensa::CCOMPARE2: + Res = STI.getFeatureBits()[Xtensa::FeatureTimerInt]; + Res &= (NumTimers > (RegNo - Xtensa::CCOMPARE0)); + break; + case Xtensa::PRID: + Res = STI.getFeatureBits()[Xtensa::FeaturePRID]; + break; + case Xtensa::INTSET: + case Xtensa::INTCLEAR: + case Xtensa::INTENABLE: + Res = STI.getFeatureBits()[Xtensa::FeatureInterrupt]; + break; + case Xtensa::MISC0: + case Xtensa::MISC1: + case Xtensa::MISC2: + case Xtensa::MISC3: + Res = STI.getFeatureBits()[Xtensa::FeatureMiscSR]; + Res &= (NumMiscSR > (RegNo - Xtensa::MISC0)); + break; + case Xtensa::THREADPTR: + Res = STI.getFeatureBits()[Xtensa::FeatureTHREADPTR]; + break; + case Xtensa::GPIO_OUT: + Res = IsESP32_S2; + break; + case Xtensa::EXPSTATE: + Res = IsESP32; + break; + case Xtensa::FCR: + case Xtensa::FSR: + Res = STI.getFeatureBits()[Xtensa::FeatureSingleFloat]; + break; + case Xtensa::F64R_LO: + case Xtensa::F64R_HI: + case Xtensa::F64S: + Res = STI.getFeatureBits()[Xtensa::FeatureDFPAccel]; + break; + } + + return Res; +} + static const unsigned SRDecoderTable[] = { Xtensa::LBEG, 0, Xtensa::LEND, 1, Xtensa::LCOUNT, 2, Xtensa::SAR, 3, @@ -186,12 +349,19 @@ static const unsigned SRDecoderTable[] = { static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + const llvm::MCSubtargetInfo STI = + ((const MCDisassembler *)Decoder)->getSubtargetInfo(); + if (RegNo > 255) return MCDisassembler::Fail; for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) { if (SRDecoderTable[i + 1] == RegNo) { unsigned Reg = SRDecoderTable[i]; + + if (!CheckRegister(Reg, STI)) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -201,9 +371,9 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, } static const unsigned URDecoderTable[] = { - Xtensa::EXPSTATE, 230, Xtensa::THREADPTR, 231, Xtensa::FCR, 232, - Xtensa::FSR, 233, Xtensa::F64R_LO, 234, Xtensa::F64R_HI, 235, - Xtensa::F64S, 236}; + Xtensa::GPIO_OUT, 0, Xtensa::EXPSTATE, 230, Xtensa::THREADPTR, 231, + Xtensa::FCR, 232, Xtensa::FSR, 233, Xtensa::F64R_LO, 234, + Xtensa::F64R_HI, 235, Xtensa::F64S, 236}; static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, @@ -217,6 +387,10 @@ static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo, for (unsigned i = 0; i < std::size(URDecoderTable); i += 2) { if (URDecoderTable[i + 1] == RegNo) { unsigned Reg = URDecoderTable[i]; + + if (!CheckRegister(Reg, STI)) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 378949fa4b02f0..a3de1b7249069f 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -611,6 +611,41 @@ def XSR : RSR_Inst<0x00, 0x01, 0x06, (outs AR:$ard, SR:$srd), (ins AR:$t, SR:$sr let Constraints = "$ard = $t, $srd = $sr"; } +//===----------------------------------------------------------------------===// +// User Registers read/write instructions +//===----------------------------------------------------------------------===// + +def WUR : RRR_Inst<0x00, 0x03, 0x0F, (outs UR:$ur), (ins AR:$t), + "wur\t$t, $ur", []> { + bits<8> ur; + + let r = ur{7-4}; + let s = ur{3-0}; +} + +def RUR : RRR_Inst<0x00, 0x03, 0x0E, (outs AR:$r), (ins UR:$ur), + "rur\t$r, $ur", []> { + bits<8> ur; + + let s = ur{7-4}; + let t = ur{3-0}; +} + +//===----------------------------------------------------------------------===// +// External Registers read/write instructions +//===----------------------------------------------------------------------===// + +def RER : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s), + "rer\t$t, $s", []> { + let r = 0x6; +} + +def WER : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins AR:$t, AR:$s), + "wer\t$t, $s", []> { + let r = 0x7; + let hasSideEffects = 1; +} + //===----------------------------------------------------------------------===// // Stack allocation //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 2fb153d065acaf..93e67af82fc86f 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -225,6 +225,7 @@ class URReg num, string n, list alt = []> : XtensaReg { let AltNames = alt; } +def GPIO_OUT : URReg<0, "gpio_out", ["GPIO_OUT"]>; def EXPSTATE : URReg<230, "expstate", ["EXPSTATE"]>; // Thread Pointer register @@ -236,7 +237,7 @@ def F64R_LO : URReg<234, "f64r_lo", ["F64R_LO"]>; def F64R_HI : URReg<235, "f64r_hi", ["F64R_HI"]>; def F64S : URReg<236, "f64s", ["F64S"]>; -def UR : RegisterClass<"Xtensa", [i32], 32, (add EXPSTATE, THREADPTR, FCR, +def UR : RegisterClass<"Xtensa", [i32], 32, (add GPIO_OUT, EXPSTATE, THREADPTR, FCR, FSR, F64R_LO, F64R_HI, F64S)>; //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/Xtensa/Core/processor-control.s b/llvm/test/MC/Xtensa/Core/processor-control.s index 5b648356fc68b1..1e7bac57892769 100644 --- a/llvm/test/MC/Xtensa/Core/processor-control.s +++ b/llvm/test/MC/Xtensa/Core/processor-control.s @@ -25,6 +25,10 @@ isync # CHECK: encoding: [0xf0,0x20,0x00] nop +# CHECK-INST: rer a3, a4 +# CHECK: encoding: [0x30,0x64,0x40] +rer a3, a4 + # Instruction format RSR # CHECK-INST: rsr a8, sar # CHECK: encoding: [0x80,0x03,0x03] @@ -43,6 +47,10 @@ rsr a8, 3 # CHECK: encoding: [0x10,0x20,0x00] rsync +# CHECK-INST: wer a3, a4 +# CHECK: encoding: [0x30,0x74,0x40] +wer a3, a4 + # Instruction format RSR # CHECK-INST: wsr a8, sar # CHECK: encoding: [0x80,0x03,0x13] From ad4dca6c07d9506ec057ec32987df66a731fb2d4 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:39 +0300 Subject: [PATCH 040/261] [Xtensa] Emit literals Implement Xtensa specific streamer to support emit literals. --- .../Target/Xtensa/MCTargetDesc/CMakeLists.txt | 1 + .../MCTargetDesc/XtensaMCTargetDesc.cpp | 20 ++++ .../MCTargetDesc/XtensaTargetStreamer.cpp | 97 +++++++++++++++++++ .../MCTargetDesc/XtensaTargetStreamer.h | 53 ++++++++++ 4 files changed, 171 insertions(+) create mode 100644 llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp create mode 100644 llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt index 6841b44f9d569c..dc12863394c7ad 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt @@ -6,6 +6,7 @@ add_llvm_component_library(LLVMXtensaDesc XtensaMCCodeEmitter.cpp XtensaMCExpr.cpp XtensaMCTargetDesc.cpp + XtensaTargetStreamer.cpp LINK_COMPONENTS MC diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp index 48674d15bdfbe2..5c00ab25d3a871 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp @@ -10,6 +10,7 @@ #include "XtensaMCTargetDesc.h" #include "XtensaInstPrinter.h" #include "XtensaMCAsmInfo.h" +#include "XtensaTargetStreamer.h" #include "TargetInfo/XtensaTargetInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/MC/MCAsmInfo.h" @@ -62,6 +63,17 @@ static MCSubtargetInfo * createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS); } + +static MCTargetStreamer * +createXtensaAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, + MCInstPrinter *InstPrint, bool isVerboseAsm) { + return new XtensaTargetAsmStreamer(S, OS); +} + +static MCTargetStreamer * +createXtensaObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + return new XtensaTargetELFStreamer(S); +} extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() { // Register the MCAsmInfo. @@ -89,4 +101,12 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() { // Register the MCAsmBackend. TargetRegistry::RegisterMCAsmBackend(getTheXtensaTarget(), createXtensaMCAsmBackend); + + // Register the asm target streamer. + TargetRegistry::RegisterAsmTargetStreamer(getTheXtensaTarget(), + createXtensaAsmTargetStreamer); + + // Register the ELF target streamer. + TargetRegistry::RegisterObjectTargetStreamer( + getTheXtensaTarget(), createXtensaObjectTargetStreamer); } diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp new file mode 100644 index 00000000000000..645491d8f97117 --- /dev/null +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp @@ -0,0 +1,97 @@ +//===-- XtensaTargetStreamer.cpp - Xtensa Target Streamer Methods ---------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file provides Xtensa specific target streamer methods. +// +//===----------------------------------------------------------------------===// + +#include "XtensaTargetStreamer.h" +#include "XtensaInstPrinter.h" +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/MC/MCAssembler.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/Support/FormattedStream.h" + +using namespace llvm; + +XtensaTargetStreamer::XtensaTargetStreamer(MCStreamer &S) + : MCTargetStreamer(S) {} + +XtensaTargetAsmStreamer::XtensaTargetAsmStreamer(MCStreamer &S, + formatted_raw_ostream &OS) + : XtensaTargetStreamer(S), OS(OS) {} + +void XtensaTargetAsmStreamer::emitLiteral(std::string str) { OS << str; } + +XtensaTargetELFStreamer::XtensaTargetELFStreamer(MCStreamer &S) + : XtensaTargetStreamer(S) {} + +void XtensaTargetELFStreamer::emitLiteralLabel(MCSymbol *LblSym, SMLoc L) { + MCContext &Context = getStreamer().getContext(); + MCStreamer &OutStreamer = getStreamer(); + MCSectionELF *CS = (MCSectionELF *)OutStreamer.getCurrentSectionOnly(); + std::string CSectionName = CS->getName().str(); + std::size_t Pos = CSectionName.find(".text"); + std::string SectionName; + if (Pos != std::string::npos) { + SectionName = ".literal"; + SectionName += CSectionName.substr(Pos); + } else { + SectionName = CSectionName; + SectionName += ".literal"; + } + + MCSection *ConstSection = Context.getELFSection( + SectionName, ELF::SHT_PROGBITS, ELF::SHF_EXECINSTR | ELF::SHF_ALLOC); + ConstSection->setAlignment(Align(4)); + + OutStreamer.pushSection(); + OutStreamer.switchSection(ConstSection); + OutStreamer.emitLabel(LblSym, L); + OutStreamer.popSection(); +} + +void XtensaTargetELFStreamer::emitLiteral(MCSymbol *LblSym, const MCExpr *Value, + SMLoc L) { + MCStreamer &OutStreamer = getStreamer(); + + OutStreamer.emitLabel(LblSym, L); + OutStreamer.emitValue(Value, 4, L); +} + +void XtensaTargetELFStreamer::emitLiteral(const MCExpr *Value, SMLoc L) { + MCContext &Context = getStreamer().getContext(); + MCStreamer &OutStreamer = getStreamer(); + MCSectionELF *CS = (MCSectionELF *)OutStreamer.getCurrentSectionOnly(); + std::string CSectionName = CS->getName().str(); + std::size_t Pos = CSectionName.find(".text"); + std::string SectionName; + if (Pos != std::string::npos) { + SectionName = ".literal"; + SectionName += CSectionName.substr(Pos); + } else { + SectionName = CSectionName; + SectionName += ".literal"; + } + + MCSection *ConstSection = Context.getELFSection( + SectionName, ELF::SHT_PROGBITS, ELF::SHF_EXECINSTR | ELF::SHF_ALLOC); + + OutStreamer.pushSection(); + OutStreamer.switchSection(ConstSection); + OutStreamer.emitValue(Value, 4, L); + OutStreamer.popSection(); +} + +MCELFStreamer &XtensaTargetELFStreamer::getStreamer() { + return static_cast(Streamer); +} diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h new file mode 100644 index 00000000000000..962da002a997d9 --- /dev/null +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h @@ -0,0 +1,53 @@ +//===-- XtensaTargetStreamer.h - Xtensa Target Streamer --------*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSATARGETSTREAMER_H +#define LLVM_LIB_TARGET_XTENSA_XTENSATARGETSTREAMER_H + +#include "XtensaConstantPoolValue.h" +#include "llvm/MC/MCELFStreamer.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/Support/SMLoc.h" + +namespace llvm { +class formatted_raw_ostream; + +class XtensaTargetStreamer : public MCTargetStreamer { +public: + XtensaTargetStreamer(MCStreamer &S); + virtual void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, SMLoc L) = 0; + virtual void emitLiteralLabel(MCSymbol *LblSym, SMLoc L) = 0; + virtual void emitLiteral(const MCExpr *Value, SMLoc L) = 0; + virtual void emitLiteral(std::string str) = 0; +}; + +class XtensaTargetAsmStreamer : public XtensaTargetStreamer { + formatted_raw_ostream &OS; + +public: + XtensaTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS); + void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, SMLoc L) override {} + void emitLiteralLabel(MCSymbol *LblSym, SMLoc L) override {} + void emitLiteral(const MCExpr *Value, SMLoc L) override {} + void emitLiteral(std::string str) override; +}; + +class XtensaTargetELFStreamer : public XtensaTargetStreamer { +public: + XtensaTargetELFStreamer(MCStreamer &S); + MCELFStreamer &getStreamer(); + void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, SMLoc L) override; + void emitLiteralLabel(MCSymbol *LblSym, SMLoc L) override; + void emitLiteral(const MCExpr *Value, SMLoc L) override; + void emitLiteral(std::string str) override {} +}; +} // end namespace llvm + +#endif From 360664f4aa7c675f9722fa17783a756514edc3da Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:39 +0300 Subject: [PATCH 041/261] [Xtensa] Improve assembler parsing. Improve CFA support. Implement special processing of MOVI and L32R instructions in assembler parser. The MOVI assembler expression now can have 32-bit immediate values, so also correct xtensa-invalid.s test. Also implement computation of CFA during XtensaMCAsmInfo creation. --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 90 ++++++++++++++++++- .../MCTargetDesc/XtensaMCTargetDesc.cpp | 4 + llvm/test/MC/Xtensa/Core/invalid.s | 4 - 3 files changed, 90 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 389af6be4b225d..5025a58e45aa83 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -8,7 +8,9 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/XtensaMCExpr.h" #include "MCTargetDesc/XtensaMCTargetDesc.h" +#include "MCTargetDesc/XtensaTargetStreamer.h" #include "TargetInfo/XtensaTargetInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -35,6 +37,11 @@ class XtensaAsmParser : public MCTargetAsmParser { SMLoc getLoc() const { return getParser().getTok().getLoc(); } + XtensaTargetStreamer &getTargetStreamer() { + MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); + return static_cast(TS); + } + bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -45,6 +52,9 @@ class XtensaAsmParser : public MCTargetAsmParser { unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; + bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + // Auto-generated instruction matching functions #define GET_ASSEMBLER_HEADER #include "XtensaGenAsmMatcher.inc" @@ -230,7 +240,13 @@ struct XtensaOperand : public MCParsedAsmOperand { bool isImm12() const { return isImm(-2048, 2047); } - bool isImm12m() const { return isImm(-2048, 2047); } + // Convert MOVI to literal load, when immediate is not in range (-2048, 2047) + bool isImm12m() const { + //Process special case when operand is symbol + if ((Kind == Immediate) && (getImm()->getKind() == MCExpr::SymbolRef)) + return true; + return isImm(LONG_MIN, LONG_MAX); + } bool isOffset4m32() const { return isImm(0, 60) && @@ -443,6 +459,74 @@ static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, return Loc; } +bool XtensaAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, + MCStreamer &Out, + const MCSubtargetInfo *STI) { + Inst.setLoc(IDLoc); + const unsigned Opcode = Inst.getOpcode(); + + switch (Opcode) { + case Xtensa::L32R: { + const MCSymbolRefExpr *OpExpr = + (const MCSymbolRefExpr *)Inst.getOperand(1).getExpr(); + XtensaMCExpr::VariantKind Kind = XtensaMCExpr::VK_Xtensa_None; + const MCExpr *NewOpExpr = XtensaMCExpr::create(OpExpr, Kind, getContext()); + Inst.getOperand(1).setExpr(NewOpExpr); + } break; + case Xtensa::MOVI: { + XtensaTargetStreamer &TS = this->getTargetStreamer(); + + //In the case of asm output, simply pass the representation of + //the MOVI instruction as is + if (TS.getStreamer().hasRawTextSupport()) + break; + + //Expand MOVI operand + if (!Inst.getOperand(1).isExpr()) { + uint64_t ImmOp64 = Inst.getOperand(1).getImm(); + int32_t Imm = ImmOp64; + if ((Imm < -2048) || (Imm > 2047)) { + XtensaTargetStreamer &TS = this->getTargetStreamer(); + MCInst TmpInst; + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(Xtensa::L32R); + const MCExpr *Value = MCConstantExpr::create(ImmOp64, getContext()); + MCSymbol *Sym = getContext().createTempSymbol(); + const MCExpr *Expr = MCSymbolRefExpr::create( + Sym, MCSymbolRefExpr::VK_None, getContext()); + const MCExpr *OpExpr = XtensaMCExpr::create( + Expr, XtensaMCExpr::VK_Xtensa_None, getContext()); + TmpInst.addOperand(Inst.getOperand(0)); + MCOperand Op1 = MCOperand::createExpr(OpExpr); + TmpInst.addOperand(Op1); + TS.emitLiteralLabel(Sym, IDLoc); + TS.emitLiteral(Value, IDLoc); + Inst = TmpInst; + } + } else { + MCInst TmpInst; + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(Xtensa::L32R); + const MCExpr *Value = Inst.getOperand(1).getExpr(); + MCSymbol *Sym = getContext().createTempSymbol(); + const MCExpr *Expr = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + const MCExpr *OpExpr = XtensaMCExpr::create( + Expr, XtensaMCExpr::VK_Xtensa_None, getContext()); + TmpInst.addOperand(Inst.getOperand(0)); + MCOperand Op1 = MCOperand::createExpr(OpExpr); + TmpInst.addOperand(Op1); + Inst = TmpInst; + TS.emitLiteralLabel(Sym, IDLoc); + TS.emitLiteral(Value, IDLoc); + } + } break; + default: + break; + } + return true; +} + bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -456,6 +540,7 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, default: break; case Match_Success: + processInstruction(Inst, IDLoc, Out, STI); Inst.setLoc(IDLoc); Out.emitInstruction(Inst, getSTI()); return false; @@ -491,9 +576,6 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidImm12: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [-2048, 2047]"); - case Match_InvalidImm12m: - return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), - "expected immediate in range [-2048, 2047]"); case Match_InvalidImm1_16: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [1, 16]"); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp index 5c00ab25d3a871..8832cdf7dc01f1 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp @@ -14,6 +14,7 @@ #include "TargetInfo/XtensaTargetInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -36,6 +37,9 @@ static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new XtensaMCAsmInfo(TT); + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( + nullptr, MRI.getDwarfRegNum(Xtensa::SP, true), 0); + MAI->addInitialFrameState(Inst); return MAI; } diff --git a/llvm/test/MC/Xtensa/Core/invalid.s b/llvm/test/MC/Xtensa/Core/invalid.s index d3d8fba8169a6d..c7473e90c10ba3 100644 --- a/llvm/test/MC/Xtensa/Core/invalid.s +++ b/llvm/test/MC/Xtensa/Core/invalid.s @@ -4,10 +4,6 @@ LBL0: # Out of range immediates -# imm12m -movi a1, 3000 -# CHECK: :[[#@LINE-1]]:10: error: expected immediate in range [-2048, 2047] - # imm8 addi a1, a2, 300 # CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-128, 127] From fb45e70b168e0f31b179a4f00f1d183f32d3e0dd Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:40 +0300 Subject: [PATCH 042/261] [Xtensa] Lowering Exception Selector and Pointer Registers. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 14 ++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 9 +++++++++ 2 files changed, 23 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 2d7df81f3a06ff..dbcef9b1e1f8b0 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -326,6 +326,20 @@ bool XtensaTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, return false; } +/// If a physical register, this returns the register that receives the +/// exception address on entry to an EH pad. +Register XtensaTargetLowering::getExceptionPointerRegister( + const Constant *PersonalityFn) const { + return Xtensa::A2; +} + +/// If a physical register, this returns the register that receives the +/// exception typeid on entry to a landing pad. +Register XtensaTargetLowering::getExceptionSelectorRegister( + const Constant *PersonalityFn) const { + return Xtensa::A3; +} + bool XtensaTargetLowering::isOffsetFoldingLegal( const GlobalAddressSDNode *GA) const { // The Xtensa target isn't yet aware of offsets. diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 557bc3804935b9..2cb15dcd2ef170 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -102,6 +102,15 @@ class XtensaTargetLowering : public TargetLowering { bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override; + /// If a physical register, this returns the register that receives the + /// exception address on entry to an EH pad. + Register + getExceptionPointerRegister(const Constant *PersonalityFn) const override; + /// If a physical register, this returns the register that receives the + /// exception typeid on entry to a landing pad. + Register + getExceptionSelectorRegister(const Constant *PersonalityFn) const override; + bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; From dbfc1c91179415fc1a705a0fa00b331844893d4e Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:40 +0300 Subject: [PATCH 043/261] [Xtensa] Lowering GLobalTLSAddress operation. --- .../MCTargetDesc/XtensaELFObjectWriter.cpp | 6 ++- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 44 ++++++++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 4 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 2 +- llvm/lib/Target/Xtensa/XtensaOperators.td | 4 ++ 5 files changed, 57 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp index 7472371932f119..1422802fb9bcac 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp @@ -46,10 +46,14 @@ XtensaObjectWriter::~XtensaObjectWriter() {} unsigned XtensaObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const { + MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant(); switch ((unsigned)Fixup.getKind()) { case FK_Data_4: - return ELF::R_XTENSA_32; + if (Modifier == MCSymbolRefExpr::VariantKind::VK_TPOFF) + return ELF::R_XTENSA_TLS_TPOFF; + else + return ELF::R_XTENSA_32; default: return ELF::R_XTENSA_SLOT0_OP; } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index dbcef9b1e1f8b0..366468c6d7b35d 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -67,7 +67,7 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setStackPointerRegisterToSaveRestore(Xtensa::SP); setSchedulingPreference(Sched::RegPressure); - + setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrOneBooleanContent); @@ -88,6 +88,7 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, // Handle the various types of symbolic address. setOperationAction(ISD::ConstantPool, PtrVT, Custom); setOperationAction(ISD::GlobalAddress, PtrVT, Custom); + setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom); setOperationAction(ISD::BlockAddress, PtrVT, Custom); setOperationAction(ISD::JumpTable, PtrVT, Custom); @@ -1305,6 +1306,44 @@ SDValue XtensaTargetLowering::LowerGlobalAddress(SDValue Op, llvm_unreachable("invalid global addresses to lower"); } +SDValue XtensaTargetLowering::LowerGlobalTLSAddress(GlobalAddressSDNode *GA, + SelectionDAG &DAG) const { + SDLoc DL(GA); + const GlobalValue *GV = GA->getGlobal(); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + + if (DAG.getTarget().useEmulatedTLS()) + return LowerToTLSEmulatedModel(GA, DAG); + + TLSModel::Model model = getTargetMachine().getTLSModel(GV); + + if (!Subtarget.hasTHREADPTR()) { + llvm_unreachable("only emulated TLS supported"); + } + + if ((model == TLSModel::LocalExec) || (model == TLSModel::InitialExec)) { + auto PtrVt = getPointerTy(DAG.getDataLayout()); + + bool Priv = GV->isPrivateLinkage(GV->getLinkage()); + // Create a constant pool entry for the callee address + XtensaConstantPoolValue *CPV = XtensaConstantPoolSymbol::Create( + *DAG.getContext(), GV->getName().str().c_str() /* Sym */, + 0 /* XtensaCLabelIndex */, Priv, XtensaCP::TPOFF); + + // Get the address of the callee into a register + SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4)); + SDValue CPWrap = getAddrPCRel(CPAddr, DAG); + + SDValue TPRegister = DAG.getRegister(Xtensa::THREADPTR, MVT::i32); + SDValue ThreadPointer = + DAG.getNode(XtensaISD::RUR, DL, MVT::i32, TPRegister); + return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, CPWrap); + } else + llvm_unreachable("only local-exec and initial-exec TLS mode supported"); + + return SDValue(); +} + SDValue XtensaTargetLowering::LowerBlockAddress(BlockAddressSDNode *Node, SelectionDAG &DAG) const { const BlockAddress *BA = Node->getBlockAddress(); @@ -1636,6 +1675,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerSELECT_CC(Op, DAG); case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); + case ISD::GlobalTLSAddress: + return LowerGlobalTLSAddress(cast(Op), DAG); case ISD::BlockAddress: return LowerBlockAddress(cast(Op), DAG); case ISD::JumpTable: @@ -1692,6 +1733,7 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(MSUB); OPCODE(MOVS); OPCODE(MOVSP); + OPCODE(RUR); OPCODE(SHL); OPCODE(SRA); OPCODE(SRL); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 2cb15dcd2ef170..64da3fe119f57a 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -63,6 +63,8 @@ enum { // WinABI Return RETW_FLAG, + RUR, + // Selects between operand 0 and operand 1. Operand 2 is the // mask of condition-code values for which operand 0 should be // chosen over operand 1; it has the same form as BR_CCMASK. @@ -164,6 +166,8 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const; SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerGlobalTLSAddress(GlobalAddressSDNode *Node, + SelectionDAG &DAG) const; SDValue LowerBlockAddress(BlockAddressSDNode *Node, SelectionDAG &DAG) const; SDValue LowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index a3de1b7249069f..bfca64dd6f1ede 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -624,7 +624,7 @@ def WUR : RRR_Inst<0x00, 0x03, 0x0F, (outs UR:$ur), (ins AR:$t), } def RUR : RRR_Inst<0x00, 0x03, 0x0E, (outs AR:$r), (ins UR:$ur), - "rur\t$r, $ur", []> { + "rur\t$r, $ur", [(set AR:$r, (Xtensa_rur UR:$ur))]> { bits<8> ur; let s = ur{7-4}; diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index fcb82e400a39fe..3107137c9ad151 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -40,6 +40,7 @@ def SDT_XtensaSRC : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCi SDTCisVT<2, i32>]>; def SDT_XtensaSSL : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def SDT_XtensaSSR : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; +def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; //===----------------------------------------------------------------------===// // Node definitions @@ -97,3 +98,6 @@ def Xtensa_ssr: SDNode<"XtensaISD::SSR", SDT_XtensaSSR, [SDNPOutGlue]>; def Xtensa_brjt: SDNode<"XtensaISD::BR_JT", SDT_XtensaBrJT, [SDNPHasChain]>; def Xtensa_callw: SDNode<"XtensaISD::CALLW", SDT_XtensaCall, [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; + +def Xtensa_rur: SDNode<"XtensaISD::RUR", SDT_XtensaRUR, + [SDNPInGlue]>; From efb4a02d1a5d661fcdc9db7aed594f40d60c908b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:41 +0300 Subject: [PATCH 044/261] [Xtensa] Lower ATOMIC_FENCE. Add Atomic Expand pass. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 14 ++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 8 ++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 14 ++++++++++++++ llvm/lib/Target/Xtensa/XtensaOperators.td | 5 ++++- llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp | 3 +++ 5 files changed, 43 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 366468c6d7b35d..c625d83d907b4a 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -304,6 +304,10 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::TRAP, MVT::Other, Legal); + // to have the best chance and doing something good with fences custom lower + // them + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); @@ -1656,6 +1660,13 @@ SDValue XtensaTargetLowering::LowerShiftRightParts(SDValue Op, return DAG.getMergeValues(Ops, DL); } +SDValue XtensaTargetLowering::LowerATOMIC_FENCE(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Chain = Op.getOperand(0); + return DAG.getNode(XtensaISD::MEMW, DL, MVT::Other, Chain); +} + SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -1695,6 +1706,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerVASTART(Op, DAG); case ISD::VACOPY: return LowerVACOPY(Op, DAG); + case ISD::ATOMIC_FENCE: + return LowerATOMIC_FENCE(Op, DAG); case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); case ISD::SRA_PARTS: @@ -1732,6 +1745,7 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(MADD); OPCODE(MSUB); OPCODE(MOVS); + OPCODE(MEMW); OPCODE(MOVSP); OPCODE(RUR); OPCODE(SHL); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 64da3fe119f57a..c5740a9e1d3eba 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -52,6 +52,8 @@ enum { // FP move MOVS, + MEMW, + MOVSP, // Wraps a TargetGlobalAddress that should be loaded using PC-relative @@ -155,6 +157,10 @@ class XtensaTargetLowering : public TargetLowering { const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override; + bool shouldInsertFencesForAtomic(const Instruction *I) const override { + return true; + } + MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override; @@ -188,6 +194,8 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; + SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; + SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index bfca64dd6f1ede..4e0b28b6b2afd4 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -557,6 +557,8 @@ def EXTW : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), let hasSideEffects = 1; } +def : Pat<(Xtensa_mem_barrier), (MEMW)>; + //===----------------------------------------------------------------------===// // Processor control instructions //===----------------------------------------------------------------------===// @@ -1342,6 +1344,18 @@ def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s), let r = 0x6; } +//===----------------------------------------------------------------------===// +// Atomic patterns +//===----------------------------------------------------------------------===// + +def : Pat<(i32 (atomic_load_8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>; +def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>; +def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>; + +def : Pat<(atomic_store_8 addr_ish1:$addr, AR:$t), (S8I AR:$t, addr_ish1:$addr)>; +def : Pat<(atomic_store_16 addr_ish2:$addr, AR:$t), (S16I AR:$t, addr_ish2:$addr)>; +def : Pat<(atomic_store_32 addr_ish4:$addr, AR:$t), (S32I AR:$t, addr_ish4:$addr)>; + //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index 3107137c9ad151..e5f96e44652083 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -40,6 +40,7 @@ def SDT_XtensaSRC : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCi SDTCisVT<2, i32>]>; def SDT_XtensaSSL : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def SDT_XtensaSSR : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; +def SDT_XtensaMEMBARRIER : SDTypeProfile<0, 0, []>; def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; //===----------------------------------------------------------------------===// @@ -98,6 +99,8 @@ def Xtensa_ssr: SDNode<"XtensaISD::SSR", SDT_XtensaSSR, [SDNPOutGlue]>; def Xtensa_brjt: SDNode<"XtensaISD::BR_JT", SDT_XtensaBrJT, [SDNPHasChain]>; def Xtensa_callw: SDNode<"XtensaISD::CALLW", SDT_XtensaCall, [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; +def Xtensa_mem_barrier: SDNode<"XtensaISD::MEMW", SDT_XtensaMEMBARRIER, + [SDNPHasChain, SDNPSideEffect]>; def Xtensa_rur: SDNode<"XtensaISD::RUR", SDT_XtensaRUR, - [SDNPInGlue]>; + [SDNPInGlue]>; diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 2d2bf2112226b5..7cdf772611b3eb 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -88,6 +88,7 @@ class XtensaPassConfig : public TargetPassConfig { return getTM(); } + void addIRPasses() override; bool addInstSelector() override; void addPreEmitPass() override; }; @@ -98,6 +99,8 @@ bool XtensaPassConfig::addInstSelector() { return false; } +void XtensaPassConfig::addIRPasses() { addPass(createAtomicExpandPass()); } + void XtensaPassConfig::addPreEmitPass() { addPass(createXtensaSizeReductionPass()); addPass(&BranchRelaxationPassID); From 1c95f6bee2d2b50c061a81e3a9ae7c4d20cbcf1d Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:41 +0300 Subject: [PATCH 045/261] [Xtensa] Lower atomic_cmp_swap_(8/16/32) operations. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 173 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 2 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 12 ++ 3 files changed, 187 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index c625d83d907b4a..a18658cddca00b 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -308,6 +308,16 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, // them setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); + if (!Subtarget.hasS32C1I()) { + for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE; + I <= MVT::LAST_INTEGER_VALUETYPE; ++I) { + MVT VT = MVT::SimpleValueType(I); + if (isTypeLegal(VT)) { + setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); + } + } + } + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); @@ -1956,6 +1966,143 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, return BB; } +// Emit instructions for atomic_cmp_swap node for 8/16 bit operands +MachineBasicBlock * +XtensaTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB, + int isByteOperand) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineBasicBlock *thisBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BBExit. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomValAddr = MI.getOperand(1); + MachineOperand &CmpVal = MI.getOperand(2); + MachineOperand &SwpVal = MI.getOperand(3); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); + + unsigned ByteOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) + .addReg(R1) + .addReg(AtomValAddr.getReg()); + + unsigned AddrAlign = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) + .addReg(AtomValAddr.getReg()) + .addReg(ByteOffs); + + unsigned BitOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) + .addReg(ByteOffs) + .addImm(3); + + unsigned Mask1 = MRI.createVirtualRegister(RC); + if (isByteOperand) { + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); + } else { + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); + BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); + } + + BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); + + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); + + unsigned Mask2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); + + unsigned Mask3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); + + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); + + unsigned R4 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), R4).addReg(R3).addReg(Mask3); + + unsigned Cmp1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Cmp1).addReg(CmpVal.getReg()); + + unsigned Swp1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Swp1).addReg(SwpVal.getReg()); + + BB = BBLoop; + + unsigned MaskPhi = MRI.createVirtualRegister(RC); + unsigned MaskLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), MaskPhi) + .addReg(MaskLoop) + .addMBB(BBLoop) + .addReg(R4) + .addMBB(thisBB); + + unsigned Cmp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Cmp2).addReg(Cmp1).addReg(MaskPhi); + + unsigned Swp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(Swp1).addReg(MaskPhi); + + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(Cmp2); + + unsigned Swp3 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp3) + .addReg(Swp2) + .addReg(AddrAlign) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::AND), MaskLoop).addReg(Swp3).addReg(Mask3); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(MaskLoop) + .addReg(MaskPhi) + .addMBB(BBLoop); + + BB->addSuccessor(BBLoop); + BB->addSuccessor(BBExit); + + BB = BBExit; + auto St = BBExit->begin(); + + unsigned R5 = MRI.createVirtualRegister(RC); + BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); + + BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R5).addReg(Swp3); + + BuildMI(*BB, St, DL, TII.get(Xtensa::AND), Res.getReg()) + .addReg(R5) + .addReg(Mask1); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *MBB) const { const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); @@ -2032,6 +2179,32 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( return MBB; } + case Xtensa::ATOMIC_CMP_SWAP_8_P: { + return emitAtomicCmpSwap(MI, MBB, 1); + } + + case Xtensa::ATOMIC_CMP_SWAP_16_P: { + return emitAtomicCmpSwap(MI, MBB, 0); + } + + case Xtensa::ATOMIC_CMP_SWAP_32_P: { + MachineOperand &R = MI.getOperand(0); + MachineOperand &Addr = MI.getOperand(1); + MachineOperand &Cmp = MI.getOperand(2); + MachineOperand &Swap = MI.getOperand(3); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1) + .addReg(Cmp.getReg()); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::S32C1I), R.getReg()) + .addReg(Swap.getReg()) + .addReg(Addr.getReg()) + .addImm(0); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::S8I: case Xtensa::S16I: case Xtensa::S32I: diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index c5740a9e1d3eba..503bfffe271390 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -203,6 +203,8 @@ class XtensaTargetLowering : public TargetLowering { // Implement EmitInstrWithCustomInserter for individual operation types. MachineBasicBlock *emitSelectCC(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB, + int isByteOperand) const; InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override { diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 4e0b28b6b2afd4..b4d696c237cc39 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1356,6 +1356,18 @@ def : Pat<(atomic_store_8 addr_ish1:$addr, AR:$t), (S8I AR:$t, addr_ish1:$addr) def : Pat<(atomic_store_16 addr_ish2:$addr, AR:$t), (S16I AR:$t, addr_ish2:$addr)>; def : Pat<(atomic_store_32 addr_ish4:$addr, AR:$t), (S32I AR:$t, addr_ish4:$addr)>; +let usesCustomInserter = 1, Predicates = [HasS32C1I] in { + def ATOMIC_CMP_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), + "!atomic_cmp_swap_8_p, $dst, $ptr, $cmp, $swap", + [(set AR:$dst, (atomic_cmp_swap_8 AR:$ptr, AR:$cmp, AR:$swap))]>; + def ATOMIC_CMP_SWAP_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), + "!atomic_cmp_swap_16_p, $dst, $ptr, $cmp, $swap", + [(set AR:$dst, (atomic_cmp_swap_16 AR:$ptr, AR:$cmp, AR:$swap))]>; + def ATOMIC_CMP_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), + "!atomic_cmp_swap_32_p, $dst, $ptr, $cmp, $swap", + [(set AR:$dst, (atomic_cmp_swap_32 AR:$ptr, AR:$cmp, AR:$swap))]>; +} + //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// From 766472cdcea84a96595d8a1bbb7cab92642ed9eb Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:42 +0300 Subject: [PATCH 046/261] [Xtensa] Lower atomic_swap_(8/16/32) operations. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 275 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 4 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 10 + 3 files changed, 289 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index a18658cddca00b..0eaa75533d5dcd 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -314,6 +314,7 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, MVT VT = MVT::SimpleValueType(I); if (isTypeLegal(VT)) { setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); + setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); } } } @@ -2103,6 +2104,268 @@ XtensaTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB, return BB; } +// Emit instructions for atomic_swap node for 8/16 bit operands +MachineBasicBlock * +XtensaTargetLowering::emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB, + int isByteOperand) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBLoop3 = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBLoop4 = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop1); + F->insert(It, BBLoop2); + F->insert(It, BBLoop3); + F->insert(It, BBLoop4); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BBExit. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop1); + BBLoop1->addSuccessor(BBLoop2); + BBLoop2->addSuccessor(BBLoop3); + BBLoop2->addSuccessor(BBLoop4); + BBLoop3->addSuccessor(BBLoop2); + BBLoop3->addSuccessor(BBLoop4); + BBLoop4->addSuccessor(BBLoop1); + BBLoop4->addSuccessor(BBExit); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomValAddr = MI.getOperand(1); + MachineOperand &SwpVal = MI.getOperand(2); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); + + unsigned ByteOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) + .addReg(R1) + .addReg(AtomValAddr.getReg()); + + unsigned AddrAlign = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) + .addReg(AtomValAddr.getReg()) + .addReg(ByteOffs); + + unsigned BitOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) + .addReg(ByteOffs) + .addImm(3); + + unsigned Mask1 = MRI.createVirtualRegister(RC); + if (isByteOperand) { + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); + } else { + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); + BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); + } + + BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); + + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); + + unsigned Mask2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); + + unsigned Mask3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); + + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); + + unsigned R4 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), R4).addReg(R3).addReg(Mask3); + + unsigned SwpValShifted = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), SwpValShifted) + .addReg(SwpVal.getReg()); + + unsigned R5 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R5).addReg(AddrAlign).addImm(0); + + unsigned AtomVal = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), AtomVal).addReg(R5).addReg(Mask2); + + unsigned AtomValPhi = MRI.createVirtualRegister(RC); + unsigned AtomValLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BBLoop1, BBLoop1->begin(), DL, TII.get(Xtensa::PHI), AtomValPhi) + .addReg(AtomValLoop) + .addMBB(BBLoop4) + .addReg(AtomVal) + .addMBB(BB); + + BB = BBLoop1; + + BuildMI(BB, DL, TII.get(Xtensa::MEMW)); + + unsigned R6 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::L32I), R6).addReg(AddrAlign).addImm(0); + + unsigned R7 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R7).addReg(R6).addReg(Mask3); + + unsigned MaskPhi = MRI.createVirtualRegister(RC); + unsigned MaskLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BBLoop2, BBLoop2->begin(), DL, TII.get(Xtensa::PHI), MaskPhi) + .addReg(MaskLoop) + .addMBB(BBLoop3) + .addReg(R7) + .addMBB(BBLoop1); + + BB = BBLoop2; + + unsigned Swp1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Swp1) + .addReg(SwpValShifted) + .addReg(MaskPhi); + + unsigned AtomVal1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), AtomVal1) + .addReg(AtomValPhi) + .addReg(MaskPhi); + + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomVal1); + + unsigned Swp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp2) + .addReg(Swp1) + .addReg(AddrAlign) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::BEQ)) + .addReg(AtomVal1) + .addReg(Swp2) + .addMBB(BBLoop4); + + BB = BBLoop3; + + BuildMI(BB, DL, TII.get(Xtensa::AND), MaskLoop).addReg(Swp2).addReg(Mask3); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(MaskLoop) + .addReg(MaskPhi) + .addMBB(BBLoop2); + + BB = BBLoop4; + + BuildMI(BB, DL, TII.get(Xtensa::AND), AtomValLoop).addReg(Swp2).addReg(Mask2); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(AtomValLoop) + .addReg(AtomValPhi) + .addMBB(BBLoop1); + + BB = BBExit; + + auto St = BB->begin(); + + unsigned R8 = MRI.createVirtualRegister(RC); + + BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); + BuildMI(*BB, St, DL, TII.get(Xtensa::SLL), R8).addReg(AtomValLoop); + + if (isByteOperand) { + BuildMI(*BB, St, DL, TII.get(Xtensa::SEXT), Res.getReg()) + .addReg(R8) + .addImm(7); + } else { + BuildMI(*BB, St, DL, TII.get(Xtensa::SEXT), Res.getReg()) + .addReg(R8) + .addImm(15); + } + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +// Emit instructions for atomic_swap node for 32 bit operands +MachineBasicBlock * +XtensaTargetLowering::emitAtomicSwap(MachineInstr &MI, + MachineBasicBlock *BB) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BBExit. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop); + BBLoop->addSuccessor(BBLoop); + BBLoop->addSuccessor(BBExit); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomValAddr = MI.getOperand(1); + MachineOperand &SwpVal = MI.getOperand(2); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + BuildMI(*BB, MI, DL, TII.get(Xtensa::MEMW)); + + unsigned AtomVal = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), AtomVal) + .addReg(AtomValAddr.getReg()) + .addImm(0); + + unsigned AtomValLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BBLoop, BBLoop->begin(), DL, TII.get(Xtensa::PHI), Res.getReg()) + .addReg(AtomValLoop) + .addMBB(BBLoop) + .addReg(AtomVal) + .addMBB(BB); + + BB = BBLoop; + + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(Res.getReg()); + + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), AtomValLoop) + .addReg(SwpVal.getReg()) + .addReg(AtomValAddr.getReg()) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(AtomValLoop) + .addReg(Res.getReg()) + .addMBB(BBLoop); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *MBB) const { const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); @@ -2205,6 +2468,18 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( return MBB; } + case Xtensa::ATOMIC_SWAP_8_P: { + return emitAtomicSwap(MI, MBB, 1); + } + + case Xtensa::ATOMIC_SWAP_16_P: { + return emitAtomicSwap(MI, MBB, 0); + } + + case Xtensa::ATOMIC_SWAP_32_P: { + return emitAtomicSwap(MI, MBB); + } + case Xtensa::S8I: case Xtensa::S16I: case Xtensa::S32I: diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 503bfffe271390..4b15995f64a4ef 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -203,8 +203,12 @@ class XtensaTargetLowering : public TargetLowering { // Implement EmitInstrWithCustomInserter for individual operation types. MachineBasicBlock *emitSelectCC(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB, + int isByteOperand) const; MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, MachineBasicBlock *BB, int isByteOperand) const; + MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, + MachineBasicBlock *BB) const; InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override { diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index b4d696c237cc39..534501bb81dae4 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1366,6 +1366,16 @@ let usesCustomInserter = 1, Predicates = [HasS32C1I] in { def ATOMIC_CMP_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), "!atomic_cmp_swap_32_p, $dst, $ptr, $cmp, $swap", [(set AR:$dst, (atomic_cmp_swap_32 AR:$ptr, AR:$cmp, AR:$swap))]>; + + def ATOMIC_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), + "!atomic_swap_8_p, $dst, $ptr, $swap", + [(set AR:$dst, (atomic_swap_8 AR:$ptr, AR:$swap))]>; + def ATOMIC_SWAP_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), + "!atomic_swap_16_p, $dst, $ptr, $swap", + [(set AR:$dst, (atomic_swap_16 AR:$ptr, AR:$swap))]>; + def ATOMIC_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), + "!atomic_swap_32_p, $dst, $ptr, $swap", + [(set AR:$dst, (atomic_swap_32 AR:$ptr, AR:$swap))]>; } //===----------------------------------------------------------------------===// From c1dc5c469541801a813151b300cb79609dbeb81f Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:42 +0300 Subject: [PATCH 047/261] [Xtensa] Lower atomic operations. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 419 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 6 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 100 +++++ 3 files changed, 525 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 0eaa75533d5dcd..28ee796295032e 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -315,10 +315,27 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, if (isTypeLegal(VT)) { setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); + setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); } } } + if (Subtarget.hasS32C1I()) { + setMaxAtomicSizeInBitsSupported(32); + setMinCmpXchgSizeInBits(32); + } else { + setMaxAtomicSizeInBitsSupported(0); + } + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); @@ -2366,6 +2383,345 @@ XtensaTargetLowering::emitAtomicSwap(MachineInstr &MI, return BB; } +MachineBasicBlock *XtensaTargetLowering::emitAtomicRMW(MachineInstr &MI, + MachineBasicBlock *BB, + unsigned Opcode, + bool inv, + bool minmax) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineBasicBlock *ThisBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BB2. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomicValAddr = MI.getOperand(1); + MachineOperand &Val = MI.getOperand(2); + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R1).add(AtomicValAddr).addImm(0); + + BB = BBLoop; + + unsigned AtomicValPhi = MRI.createVirtualRegister(RC); + unsigned AtomicValLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), AtomicValPhi) + .addReg(AtomicValLoop) + .addMBB(BBLoop) + .addReg(R1) + .addMBB(ThisBB); + + unsigned R2 = MRI.createVirtualRegister(RC); + + if (minmax) { + MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(It, BBLoop1); + BB->addSuccessor(BBLoop1); + MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(It, BBLoop2); + BB->addSuccessor(BBLoop2); + + BuildMI(BB, DL, TII.get(Opcode)) + .addReg(AtomicValPhi) + .addReg(Val.getReg()) + .addMBB(BBLoop1); + + unsigned R7 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), R7).addReg(Val.getReg()); + + BB = BBLoop1; + unsigned R8 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), R8).addReg(AtomicValPhi); + BB->addSuccessor(BBLoop2); + + BB = BBLoop2; + unsigned R9 = MRI.createVirtualRegister(RC); + + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), R9) + .addReg(R7) + .addMBB(BBLoop) + .addReg(R8) + .addMBB(BBLoop1); + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), R2).addReg(R9); + } else { + BuildMI(BB, DL, TII.get(Opcode), R2) + .addReg(AtomicValPhi) + .addReg(Val.getReg()); + if (inv) { + unsigned Rtmp1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Rtmp1).addImm(-1); + unsigned Rtmp2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Rtmp2) + .addReg(R2) + .addReg(Rtmp1); + R2 = Rtmp2; + } + } + + unsigned R4 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomicValPhi); + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), R4) + .addReg(R2) + .addReg(AtomicValAddr.getReg()) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), AtomicValLoop).addReg(R4); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(AtomicValPhi) + .addReg(R4) + .addMBB(BBLoop); + + BB->addSuccessor(BBLoop); + BB->addSuccessor(BBExit); + + BB = BBExit; + auto st = BBExit->begin(); + + BuildMI(*BB, st, DL, TII.get(Xtensa::MOV_N), Res.getReg()).addReg(R4); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + + return BB; +} + +MachineBasicBlock * +XtensaTargetLowering::emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, + bool isByteOperand, unsigned Opcode, + bool inv, bool minmax) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + + MachineBasicBlock *ThisBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *BBLoop = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *BBExit = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(It, BBLoop); + F->insert(It, BBExit); + + // Transfer the remainder of BB and its successor edges to BB2. + BBExit->splice(BBExit->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + BBExit->transferSuccessorsAndUpdatePHIs(BB); + + BB->addSuccessor(BBLoop); + + MachineOperand &Res = MI.getOperand(0); + MachineOperand &AtomValAddr = MI.getOperand(1); + MachineOperand &Val = MI.getOperand(2); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R1).addImm(3); + + unsigned ByteOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::AND), ByteOffs) + .addReg(R1) + .addReg(AtomValAddr.getReg()); + + unsigned AddrAlign = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SUB), AddrAlign) + .addReg(AtomValAddr.getReg()) + .addReg(ByteOffs); + + unsigned BitOffs = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), BitOffs) + .addReg(ByteOffs) + .addImm(3); + + unsigned Mask1 = MRI.createVirtualRegister(RC); + if (isByteOperand) { + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), Mask1).addImm(0xff); + } else { + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(1); + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLLI), R3).addReg(R2).addImm(16); + BuildMI(*BB, MI, DL, TII.get(Xtensa::ADDI), Mask1).addReg(R3).addImm(-1); + } + + BuildMI(*BB, MI, DL, TII.get(Xtensa::SSL)).addReg(BitOffs); + + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::MOVI), R2).addImm(-1); + + unsigned Mask2 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Mask2).addReg(Mask1); + + unsigned Mask3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::XOR), Mask3).addReg(Mask2).addReg(R2); + + unsigned R3 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R3).addReg(AddrAlign).addImm(0); + + unsigned Val1 = MRI.createVirtualRegister(RC); + BuildMI(*BB, MI, DL, TII.get(Xtensa::SLL), Val1).addReg(Val.getReg()); + + BB = BBLoop; + + unsigned AtomicValPhi = MRI.createVirtualRegister(RC); + unsigned AtomicValLoop = MRI.createVirtualRegister(RC); + + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), AtomicValPhi) + .addReg(AtomicValLoop) + .addMBB(BBLoop) + .addReg(R3) + .addMBB(ThisBB); + + unsigned Swp2; + + if (minmax) { + MachineBasicBlock *BBLoop1 = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(It, BBLoop1); + BB->addSuccessor(BBLoop1); + MachineBasicBlock *BBLoop2 = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(It, BBLoop2); + BB->addSuccessor(BBLoop2); + + unsigned R1 = MRI.createVirtualRegister(RC); + unsigned R2 = MRI.createVirtualRegister(RC); + unsigned R3 = MRI.createVirtualRegister(RC); + unsigned R4 = MRI.createVirtualRegister(RC); + + unsigned R5 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R5) + .addReg(AtomicValPhi) + .addReg(Mask2); + + BuildMI(BB, DL, TII.get(Xtensa::SRL), R1).addReg(R5); + BuildMI(BB, DL, TII.get(Xtensa::SRL), R2).addReg(Val1); + + if ((Opcode == Xtensa::BLT) || (Opcode == Xtensa::BGE)) { + if (isByteOperand) { + BuildMI(BB, DL, TII.get(Xtensa::SEXT), R3).addReg(R1).addImm(7); + BuildMI(BB, DL, TII.get(Xtensa::SEXT), R4).addReg(R2).addImm(7); + } else { + BuildMI(BB, DL, TII.get(Xtensa::SEXT), R3).addReg(R1).addImm(15); + BuildMI(BB, DL, TII.get(Xtensa::SEXT), R4).addReg(R2).addImm(15); + } + } else { + R3 = R1; + R4 = R2; + } + + BuildMI(BB, DL, TII.get(Opcode)).addReg(R3).addReg(R4).addMBB(BBLoop1); + + unsigned R7 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), R7).addReg(Val1); + + BB = BBLoop1; + unsigned R8 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), R8).addReg(AtomicValPhi); + BB->addSuccessor(BBLoop2); + + BB = BBLoop2; + unsigned R9 = MRI.createVirtualRegister(RC); + + BuildMI(*BB, BB->begin(), DL, TII.get(Xtensa::PHI), R9) + .addReg(R7) + .addMBB(BBLoop) + .addReg(R8) + .addMBB(BBLoop1); + + unsigned R10 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R10) + .addReg(AtomicValPhi) + .addReg(Mask3); + + unsigned R11 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R11).addReg(R9).addReg(Mask2); + + Swp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(R10).addReg(R11); + } else { + unsigned R4 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R4) + .addReg(AtomicValPhi) + .addReg(Mask2); + + unsigned Res1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Opcode), Res1).addReg(R4).addReg(Val1); + + unsigned Swp1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), Swp1).addReg(Res1).addReg(Mask2); + + unsigned R5 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::AND), R5) + .addReg(AtomicValPhi) + .addReg(Mask3); + + if (inv) { + unsigned Rtmp1 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::XOR), Rtmp1) + .addReg(AtomicValPhi) + .addReg(Mask2); + R5 = Rtmp1; + } + + Swp2 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::OR), Swp2).addReg(Swp1).addReg(R5); + } + + unsigned Swp3 = MRI.createVirtualRegister(RC); + BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomicValPhi); + BuildMI(BB, DL, TII.get(Xtensa::S32C1I), Swp3) + .addReg(Swp2) + .addReg(AddrAlign) + .addImm(0); + + BuildMI(BB, DL, TII.get(Xtensa::MOV_N), AtomicValLoop).addReg(Swp3); + + BuildMI(BB, DL, TII.get(Xtensa::BNE)) + .addReg(Swp3) + .addReg(AtomicValPhi) + .addMBB(BBLoop); + + BB->addSuccessor(BBLoop); + BB->addSuccessor(BBExit); + BB = BBExit; + auto St = BBExit->begin(); + + unsigned R6 = MRI.createVirtualRegister(RC); + + BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); + + BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R6).addReg(AtomicValLoop); + + BuildMI(*BB, St, DL, TII.get(Xtensa::AND), Res.getReg()) + .addReg(R6) + .addReg(Mask1); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + + return BB; +} + MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *MBB) const { const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); @@ -2480,6 +2836,69 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( return emitAtomicSwap(MI, MBB); } + case Xtensa::ATOMIC_LOAD_ADD_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::ADD, false, false); + case Xtensa::ATOMIC_LOAD_SUB_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::SUB, false, false); + case Xtensa::ATOMIC_LOAD_OR_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::OR, false, false); + case Xtensa::ATOMIC_LOAD_XOR_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::XOR, false, false); + case Xtensa::ATOMIC_LOAD_AND_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::AND, false, false); + case Xtensa::ATOMIC_LOAD_NAND_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::AND, true, false); + case Xtensa::ATOMIC_LOAD_MIN_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::BGE, false, true); + case Xtensa::ATOMIC_LOAD_MAX_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::BLT, false, true); + case Xtensa::ATOMIC_LOAD_UMIN_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::BGEU, false, true); + case Xtensa::ATOMIC_LOAD_UMAX_8_P: + return emitAtomicRMW(MI, MBB, true, Xtensa::BLTU, false, true); + + case Xtensa::ATOMIC_LOAD_ADD_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::ADD, false, false); + case Xtensa::ATOMIC_LOAD_SUB_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::SUB, false, false); + case Xtensa::ATOMIC_LOAD_OR_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::OR, false, false); + case Xtensa::ATOMIC_LOAD_XOR_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::XOR, false, false); + case Xtensa::ATOMIC_LOAD_AND_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::AND, false, false); + case Xtensa::ATOMIC_LOAD_NAND_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::AND, true, false); + case Xtensa::ATOMIC_LOAD_MIN_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::BGE, false, true); + case Xtensa::ATOMIC_LOAD_MAX_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::BLT, false, true); + case Xtensa::ATOMIC_LOAD_UMIN_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::BGEU, false, true); + case Xtensa::ATOMIC_LOAD_UMAX_16_P: + return emitAtomicRMW(MI, MBB, false, Xtensa::BLTU, false, true); + + case Xtensa::ATOMIC_LOAD_ADD_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::ADD, false, false); + case Xtensa::ATOMIC_LOAD_SUB_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::SUB, false, false); + case Xtensa::ATOMIC_LOAD_OR_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::OR, false, false); + case Xtensa::ATOMIC_LOAD_XOR_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::XOR, false, false); + case Xtensa::ATOMIC_LOAD_AND_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::AND, false, false); + case Xtensa::ATOMIC_LOAD_NAND_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::AND, true, false); + case Xtensa::ATOMIC_LOAD_MIN_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::BGE, false, true); + case Xtensa::ATOMIC_LOAD_MAX_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::BLT, false, true); + case Xtensa::ATOMIC_LOAD_UMIN_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::BGEU, false, true); + case Xtensa::ATOMIC_LOAD_UMAX_32_P: + return emitAtomicRMW(MI, MBB, Xtensa::BLTU, false, true); + case Xtensa::S8I: case Xtensa::S16I: case Xtensa::S32I: diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 4b15995f64a4ef..9a116a92cbc59b 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -209,6 +209,12 @@ class XtensaTargetLowering : public TargetLowering { int isByteOperand) const; MachineBasicBlock *emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, + bool isByteOperand, unsigned Opcode, + bool inv, bool minmax) const; + MachineBasicBlock *emitAtomicRMW(MachineInstr &MI, MachineBasicBlock *BB, + unsigned Opcode, bool inv, + bool minmax) const; InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override { diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 534501bb81dae4..38e8fac327cb81 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1376,6 +1376,106 @@ let usesCustomInserter = 1, Predicates = [HasS32C1I] in { def ATOMIC_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$swap), "!atomic_swap_32_p, $dst, $ptr, $swap", [(set AR:$dst, (atomic_swap_32 AR:$ptr, AR:$swap))]>; + + def ATOMIC_LOAD_ADD_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_add_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_add_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_ADD_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_add_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_add_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_ADD_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_add_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_add_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_SUB_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_sub_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_sub_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_SUB_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_sub_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_sub_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_SUB_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_sub_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_sub_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_AND_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_and_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_and_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_AND_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_and_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_and_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_AND_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_and_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_and_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_OR_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_or_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_or_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_OR_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_or_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_or_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_OR_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_or_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_or_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_XOR_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_xor_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_xor_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_XOR_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_xor_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_xor_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_XOR_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_xor_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_xor_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_NAND_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_nand_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_nand_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_NAND_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_nand_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_nand_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_NAND_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_nand_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_nand_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_MIN_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_min_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_min_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_MIN_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_min_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_min_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_MIN_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_min_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_min_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_MAX_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_max_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_max_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_MAX_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_max_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_max_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_MAX_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_max_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_max_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_UMIN_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umin_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umin_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_UMIN_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umin_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umin_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_UMIN_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umin_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umin_32 AR:$ptr, AR:$arg))]>; + + def ATOMIC_LOAD_UMAX_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umax_8_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umax_8 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_UMAX_16_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umax_16_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umax_16 AR:$ptr, AR:$arg))]>; + def ATOMIC_LOAD_UMAX_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$arg), + "!atomic_load_umax_32_p, $dst, $ptr, $arg", + [(set AR:$dst, (atomic_load_umax_32 AR:$ptr, AR:$arg))]>; } //===----------------------------------------------------------------------===// From 74cca1a0560c044e30117ad2e111976d4f0cce15 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:42 +0300 Subject: [PATCH 048/261] Implement Xtensa toolchain. --- clang/lib/Driver/CMakeLists.txt | 1 + clang/lib/Driver/Driver.cpp | 4 + clang/lib/Driver/ToolChains/Xtensa.cpp | 266 +++++++++++++++++++++++++ clang/lib/Driver/ToolChains/Xtensa.h | 94 +++++++++ 4 files changed, 365 insertions(+) create mode 100644 clang/lib/Driver/ToolChains/Xtensa.cpp create mode 100644 clang/lib/Driver/ToolChains/Xtensa.h diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt index 58427e3f83c420..68e81b42acf3a1 100644 --- a/clang/lib/Driver/CMakeLists.txt +++ b/clang/lib/Driver/CMakeLists.txt @@ -81,6 +81,7 @@ add_clang_library(clangDriver ToolChains/VEToolchain.cpp ToolChains/WebAssembly.cpp ToolChains/XCore.cpp + ToolChains/Xtensa.cpp ToolChains/PPCLinux.cpp ToolChains/PPCFreeBSD.cpp ToolChains/InterfaceStubs.cpp diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 93cddf742d521d..19f9392157f07c 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -48,6 +48,7 @@ #include "ToolChains/VEToolchain.h" #include "ToolChains/WebAssembly.h" #include "ToolChains/XCore.h" +#include "ToolChains/Xtensa.h" #include "ToolChains/ZOS.h" #include "clang/Basic/TargetID.h" #include "clang/Basic/Version.h" @@ -6381,6 +6382,9 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, case llvm::Triple::csky: TC = std::make_unique(*this, Target, Args); break; + case llvm::Triple::xtensa: + TC = std::make_unique(*this, Target, Args); + break; default: if (toolchains::BareMetal::handlesTarget(Target)) TC = std::make_unique(*this, Target, Args); diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp new file mode 100644 index 00000000000000..dc32a1a05c2fa9 --- /dev/null +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -0,0 +1,266 @@ +//===--- Xtensa.cpp - Xtensa ToolChain Implementations ----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "CommonArgs.h" +#include "clang/Driver/InputInfo.h" +#include "clang/Basic/Cuda.h" +#include "clang/Config/config.h" +#include "clang/Driver/Compilation.h" +#include "clang/Driver/Distro.h" +#include "clang/Driver/Driver.h" +#include "clang/Driver/DriverDiagnostic.h" +#include "clang/Driver/Options.h" +#include "llvm/Option/ArgList.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/VirtualFileSystem.h" +#include + +using namespace clang::driver; +using namespace clang::driver::tools; +using namespace clang::driver::toolchains; +using namespace clang; +using namespace llvm::opt; + +XtensaGCCToolchainDetector::XtensaGCCToolchainDetector( + const Driver &D, const llvm::Triple &HostTriple, + const llvm::opt::ArgList &Args) { + std::string InstalledDir; + InstalledDir = D.getInstalledDir(); + StringRef CPUName = XtensaToolChain::GetTargetCPUVersion(Args); + std::string Dir; + std::string ToolchainName; + std::string ToolchainDir; + + if (CPUName.equals("esp32")) + ToolchainName = "xtensa-esp32-elf"; + else if (CPUName.equals("esp32-s2")) + ToolchainName = "xtensa-esp32s2-elf"; + else if (CPUName.equals("esp8266")) + ToolchainName = "xtensa-lx106-elf"; + + Slash = llvm::sys::path::get_separator().str(); + + ToolchainDir = InstalledDir + Slash + ".."; + Dir = ToolchainDir + Slash + "lib" + Slash + "gcc" + Slash + ToolchainName + + Slash; + GCCLibAndIncVersion = ""; + + if (D.getVFS().exists(Dir)) { + std::error_code EC; + for (llvm::vfs::directory_iterator LI = D.getVFS().dir_begin(Dir, EC), LE; + !EC && LI != LE; LI = LI.increment(EC)) { + StringRef VersionText = llvm::sys::path::filename(LI->path()); + auto GCCVersion = Generic_GCC::GCCVersion::Parse(VersionText); + if (GCCVersion.Major == -1) + continue; + GCCLibAndIncVersion = GCCVersion.Text; + } + if (GCCLibAndIncVersion == "") + llvm_unreachable("Unexpected Xtensa GCC toolchain version"); + + } else { + // Unable to find Xtensa GCC toolchain; + GCCToolchainName = ""; + return; + } + GCCToolchainDir = ToolchainDir; + GCCToolchainName = ToolchainName; +} + +/// Xtensa Toolchain +XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, + const ArgList &Args) + : Generic_ELF(D, Triple, Args), XtensaGCCToolchain(D, getTriple(), Args) { + for (auto *A : Args) { + std::string Str = A->getAsString(Args); + if (!Str.compare("-mlongcalls")) + A->claim(); + if (!Str.compare("-fno-tree-switch-conversion")) + A->claim(); + + // Currently don't use integrated assembler for assembler input files + if ((IsIntegratedAsm) && (Str.length() > 2)) { + std::string ExtSubStr = Str.substr(Str.length() - 2); + if (!ExtSubStr.compare(".s")) + IsIntegratedAsm = false; + if (!ExtSubStr.compare(".S")) + IsIntegratedAsm = false; + } + } + + // Currently don't use integrated assembler for assembler input files + if (IsIntegratedAsm) { + if (Args.getLastArgValue(options::OPT_x).equals("assembler")) + IsIntegratedAsm = false; + + if (Args.getLastArgValue(options::OPT_x).equals("assembler-with-cpp")) + IsIntegratedAsm = false; + } + + const std::string Slash = XtensaGCCToolchain.Slash; + std::string Libs = + XtensaGCCToolchain.GCCToolchainDir + Slash + "lib" + Slash + "gcc" + + Slash + XtensaGCCToolchain.GCCToolchainName + Slash + + XtensaGCCToolchain.GCCLibAndIncVersion; + getFilePaths().push_back(Libs); + + Libs = XtensaGCCToolchain.GCCToolchainDir + Slash + + XtensaGCCToolchain.GCCToolchainName + Slash + "lib"; + getFilePaths().push_back(Libs); +} + +Tool *XtensaToolChain::buildLinker() const { + return new tools::Xtensa::Linker(*this); +} + +Tool *XtensaToolChain::buildAssembler() const { + return new tools::Xtensa::Assembler(*this); +} + +void XtensaToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, + ArgStringList &CC1Args) const { + if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc) || + DriverArgs.hasArg(options::OPT_nostdlibinc)) + return; + + if (!XtensaGCCToolchain.IsValid()) + return; + + std::string Slash = XtensaGCCToolchain.Slash; + + std::string Path1 = getDriver().ResourceDir.c_str() + Slash + "include"; + std::string Path2 = XtensaGCCToolchain.GCCToolchainDir + Slash + + XtensaGCCToolchain.GCCToolchainName + Slash + + "sys-include"; + std::string Path3 = XtensaGCCToolchain.GCCToolchainDir + Slash + + XtensaGCCToolchain.GCCToolchainName + Slash + "include"; + + const StringRef Paths[] = {Path1, Path2, Path3}; + addSystemIncludes(DriverArgs, CC1Args, Paths); +} + +void XtensaToolChain::addLibStdCxxIncludePaths( + const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args) const { + if (!XtensaGCCToolchain.IsValid()) + return; + + std::string Slash = XtensaGCCToolchain.Slash; + + std::string BaseDir = XtensaGCCToolchain.GCCToolchainDir + Slash + + XtensaGCCToolchain.GCCToolchainName + Slash + + "include" + Slash + "c++" + Slash + + XtensaGCCToolchain.GCCLibAndIncVersion; + std::string TargetDir = BaseDir + Slash + XtensaGCCToolchain.GCCToolchainName; + addLibStdCXXIncludePaths(BaseDir, "", "", DriverArgs, CC1Args); + addLibStdCXXIncludePaths(TargetDir, "", "", DriverArgs, CC1Args); + TargetDir = BaseDir + Slash + "backward"; + addLibStdCXXIncludePaths(TargetDir, "", "", DriverArgs, CC1Args); +} + +ToolChain::CXXStdlibType +XtensaToolChain::GetCXXStdlibType(const ArgList &Args) const { + Arg *A = Args.getLastArg(options::OPT_stdlib_EQ); + if (!A) + return ToolChain::CST_Libstdcxx; + + StringRef Value = A->getValue(); + if (Value != "libstdc++") + getDriver().Diag(diag::err_drv_invalid_stdlib_name) << A->getAsString(Args); + + return ToolChain::CST_Libstdcxx; +} + +const StringRef XtensaToolChain::GetTargetCPUVersion(const ArgList &Args) { + if (Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ)) { + StringRef CPUName = A->getValue(); + return CPUName; + } + return "esp32"; +} + +void tools::Xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, + const InputInfoList &Inputs, + const ArgList &Args, + const char *LinkingOutput) const { + const auto &TC = + static_cast(getToolChain()); + + if (!TC.XtensaGCCToolchain.IsValid()) + llvm_unreachable("Unable to find Xtensa GCC assembler"); + + claimNoWarnArgs(Args); + ArgStringList CmdArgs; + + CmdArgs.push_back("-o"); + CmdArgs.push_back(Output.getFilename()); + + CmdArgs.push_back("-c"); + + if (Args.hasArg(options::OPT_v)) + CmdArgs.push_back("-v"); + + if (Arg *A = Args.getLastArg(options::OPT_g_Group)) + if (!A->getOption().matches(options::OPT_g0)) + CmdArgs.push_back("-g"); + + if (Args.hasFlag(options::OPT_fverbose_asm, options::OPT_fno_verbose_asm, + false)) + CmdArgs.push_back("-fverbose-asm"); + + Args.AddAllArgValues(CmdArgs, options::OPT_Wa_COMMA, options::OPT_Xassembler); + + for (const auto &II : Inputs) + CmdArgs.push_back(II.getFilename()); + + std::string Slash = TC.XtensaGCCToolchain.Slash; + + const char *Asm = + Args.MakeArgString(getToolChain().getDriver().Dir + Slash + + TC.XtensaGCCToolchain.GCCToolchainName + "-as"); + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), Asm, CmdArgs, Inputs)); +} + +void Xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, + const InputInfoList &Inputs, + const ArgList &Args, + const char *LinkingOutput) const { + const auto &TC = + static_cast(getToolChain()); + std::string Slash = TC.XtensaGCCToolchain.Slash; + + if (!TC.XtensaGCCToolchain.IsValid()) + llvm_unreachable("Unable to find Xtensa GCC linker"); + + std::string Linker = getToolChain().getDriver().Dir + Slash + + TC.XtensaGCCToolchain.GCCToolchainName + "-ld"; + ArgStringList CmdArgs; + + Args.AddAllArgs(CmdArgs, options::OPT_L); + TC.AddFilePathLibArgs(Args, CmdArgs); + + Args.addAllArgs(CmdArgs, + {options::OPT_T_Group, options::OPT_e, options::OPT_s, + options::OPT_t, options::OPT_u_Group}); + + AddLinkerInputs(getToolChain(), Inputs, Args, CmdArgs, JA); + + CmdArgs.push_back("-lgcc"); + + CmdArgs.push_back("-o"); + CmdArgs.push_back(Output.getFilename()); + C.addCommand( + std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), + Args.MakeArgString(Linker), CmdArgs, Inputs)); +} diff --git a/clang/lib/Driver/ToolChains/Xtensa.h b/clang/lib/Driver/ToolChains/Xtensa.h new file mode 100644 index 00000000000000..663dc63f6d2795 --- /dev/null +++ b/clang/lib/Driver/ToolChains/Xtensa.h @@ -0,0 +1,94 @@ +//===--- Xtensa.h - Xtensa Tool and ToolChain Implementations ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_Xtensa_H +#define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_Xtensa_H + +#include "Gnu.h" +#include "clang/Driver/InputInfo.h" +#include "clang/Driver/Tool.h" +#include "clang/Driver/ToolChain.h" + +namespace clang { +namespace driver { +namespace toolchains { + +class XtensaGCCToolchainDetector { +public: + std::string GCCLibAndIncVersion; + std::string GCCToolchainName; + std::string GCCToolchainDir; + std::string Slash; + + XtensaGCCToolchainDetector(const Driver &D, const llvm::Triple &HostTriple, + const llvm::opt::ArgList &Args); + + bool IsValid() const { return GCCToolchainName != ""; } +}; + +class LLVM_LIBRARY_VISIBILITY XtensaToolChain : public Generic_ELF { +protected: + Tool *buildLinker() const override; + Tool *buildAssembler() const override; + +public: + XtensaToolChain(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args); + void + AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args) const override; + void + addLibStdCxxIncludePaths(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args) const override; + CXXStdlibType GetCXXStdlibType(const llvm::opt::ArgList &Args) const override; + bool IsIntegratedAssemblerDefault() const override { + return (IsIntegratedAsm || (XtensaGCCToolchain.GCCToolchainName == "")); + } + + static const StringRef GetTargetCPUVersion(const llvm::opt::ArgList &Args); + + XtensaGCCToolchainDetector XtensaGCCToolchain; + bool IsIntegratedAsm = true; +}; + +} // end namespace toolchains + +namespace tools { +namespace Xtensa { +class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +public: + Linker(const ToolChain &TC) + : Tool("Xtensa::Linker", "xtensa-esp32-elf-ld", TC) {} + bool hasIntegratedCPP() const override { return false; } + bool isLinkJob() const override { return true; } + void ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, const InputInfoList &Inputs, + const llvm::opt::ArgList &TCArgs, + const char *LinkingOutput) const override; +}; + +class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +public: + Assembler(const ToolChain &TC) + : Tool("Xtensa::Assembler", "xtensa-esp32-elf-as", TC) {} + + bool hasIntegratedCPP() const override { return false; } + void ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, const InputInfoList &Inputs, + const llvm::opt::ArgList &TCArgs, + const char *LinkingOutput) const override; +}; + +} // end namespace Xtensa +} // end namespace tools +} // end namespace driver +} // end namespace clang + +#endif // LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_Xtensa_H From 6ef9b5e0781a6cd3af42b1daf3cf4498223d3b26 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:43 +0300 Subject: [PATCH 049/261] [Xtensa] Implement multilib support Use Multilib class functionality to choose between library variants, based on the command line args. --- clang/lib/Driver/ToolChains/Xtensa.cpp | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index dc32a1a05c2fa9..9cd05867f3a017 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -17,6 +17,7 @@ #include "clang/Driver/Distro.h" #include "clang/Driver/Driver.h" #include "clang/Driver/DriverDiagnostic.h" +#include "clang/Driver/MultilibBuilder.h" #include "clang/Driver/Options.h" #include "llvm/Option/ArgList.h" #include "llvm/Support/Path.h" @@ -29,6 +30,8 @@ using namespace clang::driver::toolchains; using namespace clang; using namespace llvm::opt; +using tools::addMultilibFlag; + XtensaGCCToolchainDetector::XtensaGCCToolchainDetector( const Driver &D, const llvm::Triple &HostTriple, const llvm::opt::ArgList &Args) { @@ -105,15 +108,30 @@ XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, IsIntegratedAsm = false; } + Multilibs.push_back(Multilib()); + + Multilibs.push_back(MultilibBuilder("no-rtti", {}, {}) + .flag("-frtti", /*Disallow=*/true) + .flag("-fno-rtti") + .makeMultilib()); + + Multilib::flags_list Flags; + addMultilibFlag( + Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, false), "frtti", + Flags); + + Multilibs.select(Flags, SelectedMultilibs); + const std::string Slash = XtensaGCCToolchain.Slash; std::string Libs = XtensaGCCToolchain.GCCToolchainDir + Slash + "lib" + Slash + "gcc" + Slash + XtensaGCCToolchain.GCCToolchainName + Slash + - XtensaGCCToolchain.GCCLibAndIncVersion; + XtensaGCCToolchain.GCCLibAndIncVersion + SelectedMultilibs.back().gccSuffix(); getFilePaths().push_back(Libs); Libs = XtensaGCCToolchain.GCCToolchainDir + Slash + - XtensaGCCToolchain.GCCToolchainName + Slash + "lib"; + XtensaGCCToolchain.GCCToolchainName + Slash + "lib" + + SelectedMultilibs.back().gccSuffix(); getFilePaths().push_back(Libs); } From 6155a31553c4f69567ff67c74bb2891b980c1197 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Feb 2024 09:21:23 +0300 Subject: [PATCH 050/261] [Xtensa] Implemented builtins for Xtensa MAC16 instructions. --- clang/include/clang/Sema/Sema.h | 2 + clang/lib/Sema/SemaChecking.cpp | 79 ++++++++++++++++++++++++++++++ llvm/include/llvm/IR/Intrinsics.td | 1 + 3 files changed, 82 insertions(+) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 6adb8fb7966b3f..8ea0b9caa669af 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -13932,6 +13932,8 @@ class Sema final { bool CheckNVPTXBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, CallExpr *TheCall); + bool CheckXtensaBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall); + bool SemaBuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall); bool SemaBuiltinVAStartARMMicrosoft(CallExpr *Call); bool SemaBuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID); diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 09b7e1c62fbd7b..3eaec26c6bd166 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -2113,6 +2113,8 @@ bool Sema::CheckTSBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, case llvm::Triple::nvptx: case llvm::Triple::nvptx64: return CheckNVPTXBuiltinFunctionCall(TI, BuiltinID, TheCall); + case llvm::Triple::xtensa: + return CheckXtensaBuiltinFunctionCall(BuiltinID, TheCall); } } @@ -6210,6 +6212,83 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI, return false; } +bool Sema::CheckXtensaBuiltinFunctionCall(unsigned BuiltinID, + CallExpr *TheCall) { + unsigned i = 0, l = 0, u = 0; + switch (BuiltinID) { + default: + return false; + case Xtensa::BI__builtin_xtensa_mul_ad_ll: + case Xtensa::BI__builtin_xtensa_mul_ad_lh: + case Xtensa::BI__builtin_xtensa_mul_ad_hl: + case Xtensa::BI__builtin_xtensa_mul_ad_hh: + case Xtensa::BI__builtin_xtensa_mula_ad_ll: + case Xtensa::BI__builtin_xtensa_mula_ad_lh: + case Xtensa::BI__builtin_xtensa_mula_ad_hl: + case Xtensa::BI__builtin_xtensa_mula_ad_hh: + case Xtensa::BI__builtin_xtensa_muls_ad_ll: + case Xtensa::BI__builtin_xtensa_muls_ad_lh: + case Xtensa::BI__builtin_xtensa_muls_ad_hl: + case Xtensa::BI__builtin_xtensa_muls_ad_hh: + i = 1; + l = 2; + u = 3; + break; + case Xtensa::BI__builtin_xtensa_mul_da_ll: + case Xtensa::BI__builtin_xtensa_mul_da_lh: + case Xtensa::BI__builtin_xtensa_mul_da_hl: + case Xtensa::BI__builtin_xtensa_mul_da_hh: + case Xtensa::BI__builtin_xtensa_mula_da_ll: + case Xtensa::BI__builtin_xtensa_mula_da_lh: + case Xtensa::BI__builtin_xtensa_mula_da_hl: + case Xtensa::BI__builtin_xtensa_mula_da_hh: + case Xtensa::BI__builtin_xtensa_muls_da_ll: + case Xtensa::BI__builtin_xtensa_muls_da_lh: + case Xtensa::BI__builtin_xtensa_muls_da_hl: + case Xtensa::BI__builtin_xtensa_muls_da_hh: + i = 0; + l = 0; + u = 1; + break; + case Xtensa::BI__builtin_xtensa_mul_dd_ll: + case Xtensa::BI__builtin_xtensa_mul_dd_lh: + case Xtensa::BI__builtin_xtensa_mul_dd_hl: + case Xtensa::BI__builtin_xtensa_mul_dd_hh: + case Xtensa::BI__builtin_xtensa_mula_dd_ll: + case Xtensa::BI__builtin_xtensa_mula_dd_lh: + case Xtensa::BI__builtin_xtensa_mula_dd_hl: + case Xtensa::BI__builtin_xtensa_mula_dd_hh: + case Xtensa::BI__builtin_xtensa_muls_dd_ll: + case Xtensa::BI__builtin_xtensa_muls_dd_lh: + case Xtensa::BI__builtin_xtensa_muls_dd_hl: + case Xtensa::BI__builtin_xtensa_muls_dd_hh: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1) || + SemaBuiltinConstantArgRange(TheCall, 1, 2, 3); + case Xtensa::BI__builtin_xtensa_mula_da_ll_lddec: + case Xtensa::BI__builtin_xtensa_mula_da_lh_lddec: + case Xtensa::BI__builtin_xtensa_mula_da_hl_lddec: + case Xtensa::BI__builtin_xtensa_mula_da_hh_lddec: + case Xtensa::BI__builtin_xtensa_mula_da_ll_ldinc: + case Xtensa::BI__builtin_xtensa_mula_da_lh_ldinc: + case Xtensa::BI__builtin_xtensa_mula_da_hl_ldinc: + case Xtensa::BI__builtin_xtensa_mula_da_hh_ldinc: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || + SemaBuiltinConstantArgRange(TheCall, 2, 0, 1); + case Xtensa::BI__builtin_xtensa_mula_dd_ll_lddec: + case Xtensa::BI__builtin_xtensa_mula_dd_lh_lddec: + case Xtensa::BI__builtin_xtensa_mula_dd_hl_lddec: + case Xtensa::BI__builtin_xtensa_mula_dd_hh_lddec: + case Xtensa::BI__builtin_xtensa_mula_dd_ll_ldinc: + case Xtensa::BI__builtin_xtensa_mula_dd_lh_ldinc: + case Xtensa::BI__builtin_xtensa_mula_dd_hl_ldinc: + case Xtensa::BI__builtin_xtensa_mula_dd_hh_ldinc: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || + SemaBuiltinConstantArgRange(TheCall, 2, 0, 1) || + SemaBuiltinConstantArgRange(TheCall, 3, 2, 3); + } + return SemaBuiltinConstantArgRange(TheCall, i, l, u); +} + void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) { const TargetInfo &TI = Context.getTargetInfo(); diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index 3c19c7b063652c..c889a6c4121999 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -2602,5 +2602,6 @@ include "llvm/IR/IntrinsicsSPIRV.td" include "llvm/IR/IntrinsicsVE.td" include "llvm/IR/IntrinsicsDirectX.td" include "llvm/IR/IntrinsicsLoongArch.td" +include "llvm/IR/IntrinsicsXtensa.td" #endif // TEST_INTRINSICS_SUPPRESS_DEFS From 6539c0d65febc8307d0ae72efd217452c3980120 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:44 +0300 Subject: [PATCH 051/261] Implemented builtins for Xtensa MAC16 instructions. --- clang/include/clang/Basic/BuiltinsXtensa.def | 127 +++++++ clang/include/clang/Basic/TargetBuiltins.h | 10 + clang/lib/Basic/Targets/Xtensa.cpp | 11 + clang/lib/Basic/Targets/Xtensa.h | 5 +- llvm/include/llvm/IR/CMakeLists.txt | 1 + llvm/include/llvm/IR/IntrinsicsXtensa.td | 251 ++++++++++++++ llvm/lib/IR/Function.cpp | 1 + llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td | 175 ++++++++-- llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 257 +++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 262 ++++++++++++++ llvm/test/CodeGen/Xtensa/lit.local.cfg | 2 + llvm/test/CodeGen/Xtensa/mac16_intrinsics.ll | 319 ++++++++++++++++++ .../secondary/llvm/include/llvm/IR/BUILD.gn | 5 + 13 files changed, 1388 insertions(+), 38 deletions(-) create mode 100644 clang/include/clang/Basic/BuiltinsXtensa.def create mode 100644 llvm/include/llvm/IR/IntrinsicsXtensa.td create mode 100644 llvm/test/CodeGen/Xtensa/lit.local.cfg create mode 100644 llvm/test/CodeGen/Xtensa/mac16_intrinsics.ll diff --git a/clang/include/clang/Basic/BuiltinsXtensa.def b/clang/include/clang/Basic/BuiltinsXtensa.def new file mode 100644 index 00000000000000..47f75f1665b163 --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsXtensa.def @@ -0,0 +1,127 @@ +//===-- BuiltinsXtensa.def - Xtensa Builtin function database ----*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the Xtensa-specific builtin function database. Users of +// this file must define the BUILTIN macro to make use of this information. +// +//===----------------------------------------------------------------------===// + +// The format of this database matches clang/Basic/Builtins.def. + +BUILTIN(__builtin_xtensa_umul_aa_ll, "vUiUi", "n") +BUILTIN(__builtin_xtensa_umul_aa_lh, "vUiUi", "n") +BUILTIN(__builtin_xtensa_umul_aa_hl, "vUiUi", "n") +BUILTIN(__builtin_xtensa_umul_aa_hh, "vUiUi", "n") + +BUILTIN(__builtin_xtensa_mul_aa_ll, "vUiUi", "n") +BUILTIN(__builtin_xtensa_mul_aa_lh, "vUiUi", "n") +BUILTIN(__builtin_xtensa_mul_aa_hl, "vUiUi", "n") +BUILTIN(__builtin_xtensa_mul_aa_hh, "vUiUi", "n") + +BUILTIN(__builtin_xtensa_mul_ad_ll, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_mul_ad_lh, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_mul_ad_hl, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_mul_ad_hh, "vUiIUi", "n") + +BUILTIN(__builtin_xtensa_mul_da_ll, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_mul_da_lh, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_mul_da_hl, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_mul_da_hh, "vIUiUi", "n") + +BUILTIN(__builtin_xtensa_mul_dd_ll, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_mul_dd_lh, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_mul_dd_hl, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_mul_dd_hh, "vIUiIUi", "n") + +BUILTIN(__builtin_xtensa_mula_aa_ll, "vUiUi", "n") +BUILTIN(__builtin_xtensa_mula_aa_lh, "vUiUi", "n") +BUILTIN(__builtin_xtensa_mula_aa_hl, "vUiUi", "n") +BUILTIN(__builtin_xtensa_mula_aa_hh, "vUiUi", "n") + +BUILTIN(__builtin_xtensa_mula_ad_ll, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_ad_lh, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_ad_hl, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_ad_hh, "vUiIUi", "n") + +BUILTIN(__builtin_xtensa_mula_da_ll, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_mula_da_lh, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_mula_da_hl, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_mula_da_hh, "vIUiUi", "n") + +BUILTIN(__builtin_xtensa_mula_dd_ll, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_lh, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_hl, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_hh, "vIUiIUi", "n") + +BUILTIN(__builtin_xtensa_muls_aa_ll, "vUiUi", "n") +BUILTIN(__builtin_xtensa_muls_aa_lh, "vUiUi", "n") +BUILTIN(__builtin_xtensa_muls_aa_hl, "vUiUi", "n") +BUILTIN(__builtin_xtensa_muls_aa_hh, "vUiUi", "n") + +BUILTIN(__builtin_xtensa_muls_ad_ll, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_muls_ad_lh, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_muls_ad_hl, "vUiIUi", "n") +BUILTIN(__builtin_xtensa_muls_ad_hh, "vUiIUi", "n") + +BUILTIN(__builtin_xtensa_muls_da_ll, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_muls_da_lh, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_muls_da_hl, "vIUiUi", "n") +BUILTIN(__builtin_xtensa_muls_da_hh, "vIUiUi", "n") + +BUILTIN(__builtin_xtensa_muls_dd_ll, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_muls_dd_lh, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_muls_dd_hl, "vIUiIUi", "n") +BUILTIN(__builtin_xtensa_muls_dd_hh, "vIUiIUi", "n") + +BUILTIN(__builtin_xtensa_mula_da_ll_lddec, "vIUii**IUii", "n") +BUILTIN(__builtin_xtensa_mula_da_lh_lddec, "vIUii**IUii", "n") +BUILTIN(__builtin_xtensa_mula_da_hl_lddec, "vIUii**IUii", "n") +BUILTIN(__builtin_xtensa_mula_da_hh_lddec, "vIUii**IUii", "n") + +BUILTIN(__builtin_xtensa_mula_da_ll_ldinc, "vIUii**IUii", "n") +BUILTIN(__builtin_xtensa_mula_da_lh_ldinc, "vIUii**IUii", "n") +BUILTIN(__builtin_xtensa_mula_da_hl_ldinc, "vIUii**IUii", "n") +BUILTIN(__builtin_xtensa_mula_da_hh_ldinc, "vIUii**IUii", "n") + +BUILTIN(__builtin_xtensa_mula_dd_ll_lddec, "vIUii**IUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_lh_lddec, "vIUii**IUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_hl_lddec, "vIUii**IUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_hh_lddec, "vIUii**IUiIUi", "n") + +BUILTIN(__builtin_xtensa_mula_dd_ll_ldinc, "vIUii**IUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_lh_ldinc, "vIUii**IUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_hl_ldinc, "vIUii**IUiIUi", "n") +BUILTIN(__builtin_xtensa_mula_dd_hh_ldinc, "vIUii**IUiIUi", "n") + +// Load operations + +BUILTIN(__builtin_xtensa_ldinc, "vIUii**", "n") +BUILTIN(__builtin_xtensa_lddec, "vIUii**", "n") + +// WSR/RSR/XSR + +BUILTIN(__builtin_xtensa_wsr_acclo, "vUi", "n") +BUILTIN(__builtin_xtensa_rsr_acclo, "Ui", "n") +BUILTIN(__builtin_xtensa_xsr_acclo, "vUi*", "n") +BUILTIN(__builtin_xtensa_wsr_acchi, "vUi", "n") +BUILTIN(__builtin_xtensa_rsr_acchi, "Ui", "n") +BUILTIN(__builtin_xtensa_xsr_acchi, "vUi*", "n") +BUILTIN(__builtin_xtensa_wsr_m0, "vUi", "n") +BUILTIN(__builtin_xtensa_rsr_m0, "Ui", "n") +BUILTIN(__builtin_xtensa_xsr_m0, "vUi*", "n") +BUILTIN(__builtin_xtensa_wsr_m1, "vUi", "n") +BUILTIN(__builtin_xtensa_rsr_m1, "Ui", "n") +BUILTIN(__builtin_xtensa_xsr_m1, "vUi*", "n") +BUILTIN(__builtin_xtensa_wsr_m2, "vUi", "n") +BUILTIN(__builtin_xtensa_rsr_m2, "Ui", "n") +BUILTIN(__builtin_xtensa_xsr_m2, "vUi*", "n") +BUILTIN(__builtin_xtensa_wsr_m3, "vUi", "n") +BUILTIN(__builtin_xtensa_rsr_m3, "Ui", "n") +BUILTIN(__builtin_xtensa_xsr_m3, "vUi*", "n") + +#undef BUILTIN \ No newline at end of file diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index c31834fb52a904..50c4052a995571 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -366,6 +366,16 @@ namespace clang { }; } + /// Xtensa builtins + namespace Xtensa { + enum { + LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1, +#define BUILTIN(ID, TYPE, ATTRS) BI##ID, +#include "clang/Basic/BuiltinsXtensa.def" + LastTSBuiltin + }; + } // namespace Xtensa + static constexpr uint64_t LargestBuiltinID = std::max( {ARM::LastTSBuiltin, AArch64::LastTSBuiltin, BPF::LastTSBuiltin, PPC::LastTSBuiltin, NVPTX::LastTSBuiltin, AMDGPU::LastTSBuiltin, diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp index 270af0a05cfdcb..6ca5cba2f6aeca 100644 --- a/clang/lib/Basic/Targets/Xtensa.cpp +++ b/clang/lib/Basic/Targets/Xtensa.cpp @@ -20,6 +20,17 @@ using namespace clang; using namespace clang::targets; +static constexpr Builtin::Info BuiltinInfo[] = { +#define BUILTIN(ID, TYPE, ATTRS) \ + {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, +#include "clang/Basic/BuiltinsXtensa.def" +}; + +ArrayRef XtensaTargetInfo::getTargetBuiltins() const { + return llvm::ArrayRef(BuiltinInfo, + clang::Xtensa::LastTSBuiltin - Builtin::FirstTSBuiltin); +} + void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__Xtensa__"); diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index 76ec5dc6c00337..a9bf0f8cc8f58d 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -29,7 +29,6 @@ namespace clang { namespace targets { class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { - static const Builtin::Info BuiltinInfo[]; std::string CPU; public: @@ -53,9 +52,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override; - ArrayRef getTargetBuiltins() const override { - return std::nullopt; - } + ArrayRef getTargetBuiltins() const override; BuiltinVaListKind getBuiltinVaListKind() const override { diff --git a/llvm/include/llvm/IR/CMakeLists.txt b/llvm/include/llvm/IR/CMakeLists.txt index 468d663796ed43..83e98c8fd7c923 100644 --- a/llvm/include/llvm/IR/CMakeLists.txt +++ b/llvm/include/llvm/IR/CMakeLists.txt @@ -21,5 +21,6 @@ tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390) tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm) tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86) tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore) +tablegen(LLVM IntrinsicsXtensa.h -gen-intrinsic-enums -intrinsic-prefix=xtensa) tablegen(LLVM IntrinsicsVE.h -gen-intrinsic-enums -intrinsic-prefix=ve) add_public_tablegen_target(intrinsics_gen) diff --git a/llvm/include/llvm/IR/IntrinsicsXtensa.td b/llvm/include/llvm/IR/IntrinsicsXtensa.td new file mode 100644 index 00000000000000..d7d25609b5d56f --- /dev/null +++ b/llvm/include/llvm/IR/IntrinsicsXtensa.td @@ -0,0 +1,251 @@ +//===- IntrinsicsXtensa.td - Defines Xtensa intrinsics -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the Xtensa-specific intrinsics. +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "xtensa" in { // All intrinsics start with "llvm.xtensa.". + +def int_xtensa_umul_aa_ll: ClangBuiltin<"__builtin_xtensa_umul_aa_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_umul_aa_hl: ClangBuiltin<"__builtin_xtensa_umul_aa_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_umul_aa_lh: ClangBuiltin<"__builtin_xtensa_umul_aa_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_umul_aa_hh: ClangBuiltin<"__builtin_xtensa_umul_aa_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_mul_aa_ll: ClangBuiltin<"__builtin_xtensa_mul_aa_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_mul_aa_hl: ClangBuiltin<"__builtin_xtensa_mul_aa_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_mul_aa_lh: ClangBuiltin<"__builtin_xtensa_mul_aa_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_mul_aa_hh: ClangBuiltin<"__builtin_xtensa_mul_aa_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_mul_ad_ll: ClangBuiltin<"__builtin_xtensa_mul_ad_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mul_ad_hl: ClangBuiltin<"__builtin_xtensa_mul_ad_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mul_ad_lh: ClangBuiltin<"__builtin_xtensa_mul_ad_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mul_ad_hh: ClangBuiltin<"__builtin_xtensa_mul_ad_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_mul_da_ll: ClangBuiltin<"__builtin_xtensa_mul_da_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mul_da_hl: ClangBuiltin<"__builtin_xtensa_mul_da_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mul_da_lh: ClangBuiltin<"__builtin_xtensa_mul_da_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mul_da_hh: ClangBuiltin<"__builtin_xtensa_mul_da_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_mul_dd_ll: ClangBuiltin<"__builtin_xtensa_mul_dd_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_mul_dd_hl: ClangBuiltin<"__builtin_xtensa_mul_dd_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_mul_dd_lh: ClangBuiltin<"__builtin_xtensa_mul_dd_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_mul_dd_hh: ClangBuiltin<"__builtin_xtensa_mul_dd_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_mula_aa_ll: ClangBuiltin<"__builtin_xtensa_mula_aa_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_mula_aa_hl: ClangBuiltin<"__builtin_xtensa_mula_aa_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_mula_aa_lh: ClangBuiltin<"__builtin_xtensa_mula_aa_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_mula_aa_hh: ClangBuiltin<"__builtin_xtensa_mula_aa_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_mula_ad_ll: ClangBuiltin<"__builtin_xtensa_mula_ad_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mula_ad_hl: ClangBuiltin<"__builtin_xtensa_mula_ad_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mula_ad_lh: ClangBuiltin<"__builtin_xtensa_mula_ad_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mula_ad_hh: ClangBuiltin<"__builtin_xtensa_mula_ad_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_mula_da_ll: ClangBuiltin<"__builtin_xtensa_mula_da_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mula_da_hl: ClangBuiltin<"__builtin_xtensa_mula_da_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mula_da_lh: ClangBuiltin<"__builtin_xtensa_mula_da_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_mula_da_hh: ClangBuiltin<"__builtin_xtensa_mula_da_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_mula_dd_ll: ClangBuiltin<"__builtin_xtensa_mula_dd_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_hl: ClangBuiltin<"__builtin_xtensa_mula_dd_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_lh: ClangBuiltin<"__builtin_xtensa_mula_dd_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_hh: ClangBuiltin<"__builtin_xtensa_mula_dd_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_muls_aa_ll: ClangBuiltin<"__builtin_xtensa_muls_aa_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_muls_aa_hl: ClangBuiltin<"__builtin_xtensa_muls_aa_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_muls_aa_lh: ClangBuiltin<"__builtin_xtensa_muls_aa_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_xtensa_muls_aa_hh: ClangBuiltin<"__builtin_xtensa_muls_aa_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_muls_ad_ll: ClangBuiltin<"__builtin_xtensa_muls_ad_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_muls_ad_hl: ClangBuiltin<"__builtin_xtensa_muls_ad_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_muls_ad_lh: ClangBuiltin<"__builtin_xtensa_muls_ad_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_muls_ad_hh: ClangBuiltin<"__builtin_xtensa_muls_ad_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_muls_da_ll: ClangBuiltin<"__builtin_xtensa_muls_da_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_muls_da_hl: ClangBuiltin<"__builtin_xtensa_muls_da_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_muls_da_lh: ClangBuiltin<"__builtin_xtensa_muls_da_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; +def int_xtensa_muls_da_hh: ClangBuiltin<"__builtin_xtensa_muls_da_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_muls_dd_ll: ClangBuiltin<"__builtin_xtensa_muls_dd_ll">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_muls_dd_hl: ClangBuiltin<"__builtin_xtensa_muls_dd_hl">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_muls_dd_lh: ClangBuiltin<"__builtin_xtensa_muls_dd_lh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; +def int_xtensa_muls_dd_hh: ClangBuiltin<"__builtin_xtensa_muls_dd_hh">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + + +def int_xtensa_mula_da_ll_lddec: ClangBuiltin<"__builtin_xtensa_mula_da_ll_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>]>; +def int_xtensa_mula_da_lh_lddec: ClangBuiltin<"__builtin_xtensa_mula_da_lh_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>]>; +def int_xtensa_mula_da_hl_lddec: ClangBuiltin<"__builtin_xtensa_mula_da_hl_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>]>; +def int_xtensa_mula_da_hh_lddec: ClangBuiltin<"__builtin_xtensa_mula_da_hh_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>]>; + +def int_xtensa_mula_da_ll_ldinc: ClangBuiltin<"__builtin_xtensa_mula_da_ll_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>]>; +def int_xtensa_mula_da_lh_ldinc: ClangBuiltin<"__builtin_xtensa_mula_da_lh_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>]>; +def int_xtensa_mula_da_hl_ldinc: ClangBuiltin<"__builtin_xtensa_mula_da_hl_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>]>; +def int_xtensa_mula_da_hh_ldinc: ClangBuiltin<"__builtin_xtensa_mula_da_hh_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>]>; + +def int_xtensa_mula_dd_ll_lddec: ClangBuiltin<"__builtin_xtensa_mula_dd_ll_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_lh_lddec: ClangBuiltin<"__builtin_xtensa_mula_dd_lh_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_hl_lddec: ClangBuiltin<"__builtin_xtensa_mula_dd_hl_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_hh_lddec: ClangBuiltin<"__builtin_xtensa_mula_dd_hh_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_mula_dd_ll_ldinc: ClangBuiltin<"__builtin_xtensa_mula_dd_ll_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_lh_ldinc: ClangBuiltin<"__builtin_xtensa_mula_dd_lh_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_hl_ldinc: ClangBuiltin<"__builtin_xtensa_mula_dd_hl_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, ImmArg>]>; +def int_xtensa_mula_dd_hh_ldinc: ClangBuiltin<"__builtin_xtensa_mula_dd_hh_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, ImmArg>]>; + +//===----------------------------------------------------------------------===// +// Load operations + +def int_xtensa_lddec: ClangBuiltin<"__builtin_xtensa_lddec">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [ImmArg>]>; + +def int_xtensa_ldinc: ClangBuiltin<"__builtin_xtensa_ldinc">, + Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [ImmArg>]>; + +//===----------------------------------------------------------------------===// +// WSR/XSR/RSR + +def int_xtensa_wsr_acclo: ClangBuiltin<"__builtin_xtensa_wsr_acclo">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_rsr_acclo: ClangBuiltin<"__builtin_xtensa_rsr_acclo">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_xsr_acclo: ClangBuiltin<"__builtin_xtensa_xsr_acclo">, + Intrinsic<[], [llvm_ptr_ty], []>; + +def int_xtensa_wsr_acchi: ClangBuiltin<"__builtin_xtensa_wsr_acchi">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_rsr_acchi: ClangBuiltin<"__builtin_xtensa_rsr_acchi">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_xsr_acchi: ClangBuiltin<"__builtin_xtensa_xsr_acchi">, + Intrinsic<[], [llvm_ptr_ty], []>; + +def int_xtensa_wsr_m0: ClangBuiltin<"__builtin_xtensa_wsr_m0">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_rsr_m0: ClangBuiltin<"__builtin_xtensa_rsr_m0">, + Intrinsic<[llvm_i32_ty]>; + +def int_xtensa_xsr_m0: ClangBuiltin<"__builtin_xtensa_xsr_m0">, + Intrinsic<[], [llvm_ptr_ty], []>; + +def int_xtensa_wsr_m1: ClangBuiltin<"__builtin_xtensa_wsr_m1">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_rsr_m1: ClangBuiltin<"__builtin_xtensa_rsr_m1">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_xsr_m1: ClangBuiltin<"__builtin_xtensa_xsr_m1">, + Intrinsic<[], [llvm_ptr_ty], []>; + +def int_xtensa_wsr_m2: ClangBuiltin<"__builtin_xtensa_wsr_m2">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_rsr_m2: ClangBuiltin<"__builtin_xtensa_rsr_m2">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_xsr_m2: ClangBuiltin<"__builtin_xtensa_xsr_m2">, + Intrinsic<[], [llvm_ptr_ty], []>; + +def int_xtensa_wsr_m3: ClangBuiltin<"__builtin_xtensa_wsr_m3">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_rsr_m3: ClangBuiltin<"__builtin_xtensa_rsr_m3">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_xsr_m3: ClangBuiltin<"__builtin_xtensa_xsr_m3">, + Intrinsic<[], [llvm_ptr_ty], []>; + +} diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp index 22e2455462bf44..b1138d602c6975 100644 --- a/llvm/lib/IR/Function.cpp +++ b/llvm/lib/IR/Function.cpp @@ -48,6 +48,7 @@ #include "llvm/IR/IntrinsicsWebAssembly.h" #include "llvm/IR/IntrinsicsX86.h" #include "llvm/IR/IntrinsicsXCore.h" +#include "llvm/IR/IntrinsicsXtensa.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/MDBuilder.h" #include "llvm/IR/Metadata.h" diff --git a/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td index d80df463206432..aec66efd8d2f28 100644 --- a/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td @@ -13,29 +13,31 @@ //===----------------------------------------------------------------------===// // Multiply -class UMUL_AA oper1, string instrAsm> +class UMUL_AA oper1, string instrAsm, SDPatternOperator opNode> : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t), - instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> { + instrAsm#"\t$s, $t", + [(opNode AR:$s, AR:$t)]>, Requires<[HasMAC16]> { let r = 0; let Defs = [M1, M2, ACCLO, ACCHI]; } -def UMUL_AA_LL : UMUL_AA<0x00, "umul.aa.ll">; -def UMUL_AA_HL : UMUL_AA<0x01, "umul.aa.hl">; -def UMUL_AA_LH : UMUL_AA<0x02, "umul.aa.lh">; -def UMUL_AA_HH : UMUL_AA<0x03, "umul.aa.hh">; +def UMUL_AA_LL : UMUL_AA<0x00, "umul.aa.ll", int_xtensa_umul_aa_ll>; +def UMUL_AA_HL : UMUL_AA<0x01, "umul.aa.hl", int_xtensa_umul_aa_hl>; +def UMUL_AA_LH : UMUL_AA<0x02, "umul.aa.lh", int_xtensa_umul_aa_lh>; +def UMUL_AA_HH : UMUL_AA<0x03, "umul.aa.hh", int_xtensa_umul_aa_hh>; -class MUL_AA oper1, string instrAsm> +class MUL_AA oper1, string instrAsm, SDPatternOperator opNode> : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t), - instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> { + instrAsm#"\t$s, $t", + [(opNode AR:$s, AR:$t)]>, Requires<[HasMAC16]> { let r = 0; let Defs = [M1, M2, ACCLO, ACCHI]; } -def MUL_AA_LL : MUL_AA<0x04, "mul.aa.ll">; -def MUL_AA_HL : MUL_AA<0x05, "mul.aa.hl">; -def MUL_AA_LH : MUL_AA<0x06, "mul.aa.lh">; -def MUL_AA_HH : MUL_AA<0x07, "mul.aa.hh">; +def MUL_AA_LL : MUL_AA<0x04, "mul.aa.ll", int_xtensa_mul_aa_ll>; +def MUL_AA_HL : MUL_AA<0x05, "mul.aa.hl", int_xtensa_mul_aa_hl>; +def MUL_AA_LH : MUL_AA<0x06, "mul.aa.lh", int_xtensa_mul_aa_lh>; +def MUL_AA_HH : MUL_AA<0x07, "mul.aa.hh", int_xtensa_mul_aa_hh>; class MUL_AD oper1, string instrAsm> : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y), @@ -92,17 +94,18 @@ def MUL_DD_HL : MUL_DD<0x05, "mul.dd.hl">; def MUL_DD_LH : MUL_DD<0x06, "mul.dd.lh">; def MUL_DD_HH : MUL_DD<0x07, "mul.dd.hh">; -class MULA_AA oper1, string instrAsm> +class MULA_AA oper1, string instrAsm, SDPatternOperator opNode> : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t), - instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> { + instrAsm#"\t$s, $t", + [(opNode AR:$s, AR:$t)]>, Requires<[HasMAC16]> { let r = 0; let Defs = [M1, M2, ACCLO, ACCHI]; } -def MULA_AA_LL : MULA_AA<0x08, "mula.aa.ll">; -def MULA_AA_HL : MULA_AA<0x09, "mula.aa.hl">; -def MULA_AA_LH : MULA_AA<0x0A, "mula.aa.lh">; -def MULA_AA_HH : MULA_AA<0x0B, "mula.aa.hh">; +def MULA_AA_LL : MULA_AA<0x08, "mula.aa.ll", int_xtensa_mula_aa_ll>; +def MULA_AA_HL : MULA_AA<0x09, "mula.aa.hl", int_xtensa_mula_aa_hl>; +def MULA_AA_LH : MULA_AA<0x0A, "mula.aa.lh", int_xtensa_mula_aa_lh>; +def MULA_AA_HH : MULA_AA<0x0B, "mula.aa.hh", int_xtensa_mula_aa_hh>; class MULA_AD oper1, string instrAsm> : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y), @@ -165,18 +168,19 @@ def MULA_DD_HL : MULA_DD<0x09, "mula.dd.hl">; def MULA_DD_LH : MULA_DD<0x0A, "mula.dd.lh">; def MULA_DD_HH : MULA_DD<0x0B, "mula.dd.hh">; -class MULS_AA oper1, string instrAsm> +class MULS_AA oper1, string instrAsm, SDPatternOperator opNode> : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t), - instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> { + instrAsm#"\t$s, $t", + [(opNode AR:$s, AR:$t)]>, Requires<[HasMAC16]> { let r = 0; let Uses = [ACCLO, ACCHI]; let Defs = [M1, M2, ACCLO, ACCHI]; } -def MULS_AA_LL : MULS_AA<0x0C, "muls.aa.ll">; -def MULS_AA_HL : MULS_AA<0x0D, "muls.aa.hl">; -def MULS_AA_LH : MULS_AA<0x0E, "muls.aa.lh">; -def MULS_AA_HH : MULS_AA<0x0F, "muls.aa.hh">; +def MULS_AA_LL : MULS_AA<0x0C, "muls.aa.ll", int_xtensa_muls_aa_ll>; +def MULS_AA_HL : MULS_AA<0x0D, "muls.aa.hl", int_xtensa_muls_aa_hl>; +def MULS_AA_LH : MULS_AA<0x0E, "muls.aa.lh", int_xtensa_muls_aa_lh>; +def MULS_AA_HH : MULS_AA<0x0F, "muls.aa.hh", int_xtensa_muls_aa_hh>; class MULS_AD oper1, string instrAsm> : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y), @@ -262,6 +266,21 @@ def MULA_DA_HL_LDDEC : MULA_DA_LDDEC<0x09, "mula.da.hl.lddec">; def MULA_DA_LH_LDDEC : MULA_DA_LDDEC<0x0A, "mula.da.lh.lddec">; def MULA_DA_HH_LDDEC : MULA_DA_LDDEC<0x0B, "mula.da.hh.lddec">; +let usesCustomInserter = 1, Predicates = [HasMAC16] in { + def MULA_DA_LL_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t), + "!xtensa_mula_da_ll_lddec_p, $mw, $s, $mx, $t", + [(int_xtensa_mula_da_ll_lddec timm:$mw, AR:$s, timm:$mx, AR:$t)]>; + def MULA_DA_HL_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t), + "!xtensa_mula_da_hl_lddec_p, $mw, $s, $mx, $t", + [(int_xtensa_mula_da_hl_lddec timm:$mw, AR:$s, timm:$mx, AR:$t)]>; + def MULA_DA_LH_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t), + "!xtensa_mula_da_lh_lddec_p, $mw, $s, $mx, $t", + [(int_xtensa_mula_da_lh_lddec timm:$mw, AR:$s, timm:$mx, AR:$t)]>; + def MULA_DA_HH_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t), + "!xtensa_mula_da_hh_lddec_p, $mw, $s, $mx, $t", + [(int_xtensa_mula_da_hh_lddec timm:$mw, AR:$s, timm:$mx, AR:$t)]>; +} + class MULA_DA_LDINC oper1, string instrAsm> : RRR_Inst<0x04, oper1, 0x04, (outs MR:$w, AR:$d), (ins AR:$s, MR:$x, AR:$t), instrAsm#"\t $w, $s, $x, $t", []>, Requires<[HasMAC16]> { @@ -277,10 +296,25 @@ class MULA_DA_LDINC oper1, string instrAsm> let Defs = [M1, M2, ACCLO, ACCHI]; } -def MULA_DA_LL_LDINC: MULA_DA_LDINC<0x08, "mula.da.ll.ldinc">; -def MULA_DA_HL_LDINC: MULA_DA_LDINC<0x09, "mula.da.hl.ldinc">; -def MULA_DA_LH_LDINC: MULA_DA_LDINC<0x0A, "mula.da.lh.ldinc">; -def MULA_DA_HH_LDINC: MULA_DA_LDINC<0x0B, "mula.da.hh.ldinc">; +def MULA_DA_LL_LDINC : MULA_DA_LDINC<0x08, "mula.da.ll.ldinc">; +def MULA_DA_HL_LDINC : MULA_DA_LDINC<0x09, "mula.da.hl.ldinc">; +def MULA_DA_LH_LDINC : MULA_DA_LDINC<0x0A, "mula.da.lh.ldinc">; +def MULA_DA_HH_LDINC : MULA_DA_LDINC<0x0B, "mula.da.hh.ldinc">; + +let usesCustomInserter = 1, Predicates = [HasMAC16] in { + def MULA_DA_LL_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t), + "!xtensa_mula_da_ll_ldinc_p, $mw, $s, $mx, $t", + [(int_xtensa_mula_da_ll_ldinc timm:$mw, AR:$s, timm:$mx, AR:$t)]>; + def MULA_DA_HL_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t), + "!xtensa_mula_da_hl_ldinc_p, $mw, $s, $mx, $t", + [(int_xtensa_mula_da_hl_ldinc timm:$mw, AR:$s, timm:$mx, AR:$t)]>; + def MULA_DA_LH_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t), + "!xtensa_mula_da_lh_ldinc_p, $mw, $s, $mx, $t", + [(int_xtensa_mula_da_lh_ldinc timm:$mw, AR:$s, timm:$mx, AR:$t)]>; + def MULA_DA_HH_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t), + "!xtensa_mula_da_hh_ldinc_p, $mw, $s, $mx, $t", + [(int_xtensa_mula_da_hh_ldinc timm:$mw, AR:$s, timm:$mx, AR:$t)]>; +} class MULA_DD_LDDEC oper1, string instrAsm> : RRR_Inst<0x04, oper1, 0x01, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y), @@ -306,6 +340,21 @@ def MULA_DD_HL_LDDEC : MULA_DD_LDDEC<0x09, "mula.dd.hl.lddec">; def MULA_DD_LH_LDDEC : MULA_DD_LDDEC<0x0A, "mula.dd.lh.lddec">; def MULA_DD_HH_LDDEC : MULA_DD_LDDEC<0x0B, "mula.dd.hh.lddec">; +let usesCustomInserter = 1, Predicates = [HasMAC16] in { + def MULA_DD_LL_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my), + "!xtensa_mula_dd_ll_lddec_p, $mw, $s, $mx, $my", + [(int_xtensa_mula_dd_ll_lddec timm:$mw, AR:$s, timm:$mx, timm:$my)]>; + def MULA_DD_HL_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my), + "!xtensa_mula_dd_hl_lddec_p, $mw, $s, $mx, $my", + [(int_xtensa_mula_dd_hl_lddec timm:$mw, AR:$s, timm:$mx, timm:$my)]>; + def MULA_DD_LH_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my), + "!xtensa_mula_dd_lh_lddec_p, $mw, $s, $mx, $my", + [(int_xtensa_mula_dd_lh_lddec timm:$mw, AR:$s, timm:$mx, timm:$my)]>; + def MULA_DD_HH_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my), + "!xtensa_mula_dd_hh_lddec_p, $mw, $s, $mx, $my", + [(int_xtensa_mula_dd_hh_lddec timm:$mw, AR:$s, timm:$mx, timm:$my)]>; +} + class MULA_DD_LDINC oper1, string instrAsm> : RRR_Inst<0x04, oper1, 0x00, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y), instrAsm#"\t $w, $s, $x, $y", []>, Requires<[HasMAC16]> { @@ -330,6 +379,21 @@ def MULA_DD_HL_LDINC : MULA_DD_LDINC<0x09, "mula.dd.hl.ldinc">; def MULA_DD_LH_LDINC : MULA_DD_LDINC<0x0A, "mula.dd.lh.ldinc">; def MULA_DD_HH_LDINC : MULA_DD_LDINC<0x0B, "mula.dd.hh.ldinc">; +let usesCustomInserter = 1, Predicates = [HasMAC16] in { + def MULA_DD_LL_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my), + "!xtensa_mula_dd_ll_ldinc_p, $mw, $s, $mx, $my", + [(int_xtensa_mula_dd_ll_ldinc timm:$mw, AR:$s, timm:$mx, timm:$my)]>; + def MULA_DD_HL_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my), + "!xtensa_mula_dd_hl_ldinc_p, $mw, $s, $mx, $my", + [(int_xtensa_mula_dd_hl_ldinc timm:$mw, AR:$s, timm:$mx, timm:$my)]>; + def MULA_DD_LH_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my), + "!xtensa_mula_dd_lh_ldinc_p, $mw, $s, $mx, $my", + [(int_xtensa_mula_dd_lh_ldinc timm:$mw, AR:$s, timm:$mx, timm:$my)]>; + def MULA_DD_HH_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my), + "!xtensa_mula_dd_hh_ldinc_p, $mw, $s, $mx, $my", + [(int_xtensa_mula_dd_hh_ldinc timm:$mw, AR:$s, timm:$mx, timm:$my)]>; +} + def LDDEC : RRR_Inst<0x04, 0x00, 0x09, (outs MR:$w, AR:$d), (ins AR:$s), "lddec\t $w, $s", []>, Requires<[HasMAC16]> { bits<2> w; @@ -351,3 +415,58 @@ def LDINC : RRR_Inst<0x04, 0x00, 0x08, (outs MR:$w, AR:$d), (ins AR:$s), let r{1-0} = w{1-0}; let t = 0; } + +let usesCustomInserter = 1, Predicates = [HasMAC16] in { + def LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s), + "!xtensa_lddec_p, $mw, $s", + [(int_xtensa_lddec timm:$mw, AR:$s)]>; + def LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s), + "!xtensa_ldinc_p, $mw, $s", + [(int_xtensa_ldinc timm:$mw, AR:$s)]>; +} + +def : Pat<(i32 (int_xtensa_rsr_acclo)), (RSR ACCLO)>; +def : Pat<(i32 (int_xtensa_rsr_acchi)), (RSR ACCHI)>; +def : Pat<(i32 (int_xtensa_rsr_m0)), (RSR M0)>; +def : Pat<(i32 (int_xtensa_rsr_m1)), (RSR M1)>; +def : Pat<(i32 (int_xtensa_rsr_m2)), (RSR M2)>; +def : Pat<(i32 (int_xtensa_rsr_m3)), (RSR M3)>; + +let usesCustomInserter = 1, Predicates = [HasMAC16] in { + def XSR_ACCLO_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_xsr_acclo_p, $s", + [(int_xtensa_xsr_acclo AR:$s)]>; + def XSR_ACCHI_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_xsr_acchi_p, $s", + [(int_xtensa_xsr_acchi AR:$s)]>; + def XSR_M0_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_xsr_m0_p, $s", + [(int_xtensa_xsr_m0 AR:$s)]>; + def XSR_M1_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_xsr_m1_p, $s", + [(int_xtensa_xsr_m1 AR:$s)]>; + def XSR_M2_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_xsr_m2_p, $s", + [(int_xtensa_xsr_m2 AR:$s)]>; + def XSR_M3_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_xsr_m3_p, $s", + [(int_xtensa_xsr_m3 AR:$s)]>; + def WSR_ACCLO_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_wsr_acclo_p, $s", + [(int_xtensa_wsr_acclo AR:$s)]>; + def WSR_ACCHI_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_wsr_acchi_p, $s", + [(int_xtensa_wsr_acchi AR:$s)]>; + def WSR_M0_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_wsr_m0_p, $s", + [(int_xtensa_wsr_m0 AR:$s)]>; + def WSR_M1_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_wsr_m1_p, $s", + [(int_xtensa_wsr_m1 AR:$s)]>; + def WSR_M2_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_wsr_m2_p, $s", + [(int_xtensa_wsr_m2 AR:$s)]>; + def WSR_M3_P : Pseudo<(outs), (ins AR:$s), + "!xtensa_wsr_m3_p, $s", + [(int_xtensa_wsr_m3 AR:$s)]>; +} diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 31d2a4839d73bf..f702142e2d15ec 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -14,6 +14,7 @@ #include "Xtensa.h" #include "XtensaTargetMachine.h" +#include "llvm/IR/IntrinsicsXtensa.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" @@ -132,14 +133,258 @@ FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM, } void XtensaDAGToDAGISel::Select(SDNode *Node) { + unsigned Opcode = Node->getOpcode(); SDLoc DL(Node); - // Dump information about the Node being selected - LLVM_DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); + const unsigned MRTable[] = {Xtensa::M0, Xtensa::M1, Xtensa::M2, Xtensa::M3}; - // If we have a custom node, we already have selected! - if (Node->isMachineOpcode()) { - LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); - return; + switch (Opcode) { + case ISD::INTRINSIC_VOID: { + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + switch (IntNo) { + default: + break; + case Intrinsic::xtensa_mul_da_ll: + case Intrinsic::xtensa_mul_da_lh: + case Intrinsic::xtensa_mul_da_hl: + case Intrinsic::xtensa_mul_da_hh: + case Intrinsic::xtensa_mula_da_ll: + case Intrinsic::xtensa_mula_da_lh: + case Intrinsic::xtensa_mula_da_hl: + case Intrinsic::xtensa_mula_da_hh: + case Intrinsic::xtensa_muls_da_ll: + case Intrinsic::xtensa_muls_da_lh: + case Intrinsic::xtensa_muls_da_hl: + case Intrinsic::xtensa_muls_da_hh: { + SDValue ChainIn = Node->getOperand(0); + SDValue ValueMX = Node->getOperand(2); + SDValue ValueT = Node->getOperand(3); + unsigned OpCode; + + switch (IntNo) { + case Intrinsic::xtensa_mul_da_ll: + OpCode = Xtensa::MUL_DA_LL; + break; + case Intrinsic::xtensa_mul_da_lh: + OpCode = Xtensa::MUL_DA_LH; + break; + case Intrinsic::xtensa_mul_da_hl: + OpCode = Xtensa::MUL_DA_HL; + break; + case Intrinsic::xtensa_mul_da_hh: + OpCode = Xtensa::MUL_DA_HH; + break; + case Intrinsic::xtensa_mula_da_ll: + OpCode = Xtensa::MULA_DA_LL; + break; + case Intrinsic::xtensa_mula_da_lh: + OpCode = Xtensa::MULA_DA_LH; + break; + case Intrinsic::xtensa_mula_da_hl: + OpCode = Xtensa::MULA_DA_HL; + break; + case Intrinsic::xtensa_mula_da_hh: + OpCode = Xtensa::MULA_DA_HH; + break; + case Intrinsic::xtensa_muls_da_ll: + OpCode = Xtensa::MULS_DA_LL; + break; + case Intrinsic::xtensa_muls_da_lh: + OpCode = Xtensa::MULS_DA_LH; + break; + case Intrinsic::xtensa_muls_da_hl: + OpCode = Xtensa::MULS_DA_HL; + break; + case Intrinsic::xtensa_muls_da_hh: + OpCode = Xtensa::MULS_DA_HH; + break; + } + + uint64_t MXVal = 4; + if (ValueMX.getOpcode() == ISD::TargetConstant) { + MXVal = cast(ValueMX)->getZExtValue(); + } + + assert( + (MXVal < 2) && + "Unexpected value of mul*_da* first argument, it must be m0 or m1"); + unsigned MXReg = MRTable[MXVal]; + + const EVT MULAResTys[] = {MVT::Other}; + SmallVector MULAOps; + MULAOps.push_back(CurDAG->getRegister(MXReg, MVT::i32)); + MULAOps.push_back(ValueT); + MULAOps.push_back(ChainIn); + + SDNode *MULA = CurDAG->getMachineNode(OpCode, DL, MULAResTys, MULAOps); + ReplaceNode(Node, MULA); + return; + } + case Intrinsic::xtensa_mul_ad_ll: + case Intrinsic::xtensa_mul_ad_lh: + case Intrinsic::xtensa_mul_ad_hl: + case Intrinsic::xtensa_mul_ad_hh: + case Intrinsic::xtensa_mula_ad_ll: + case Intrinsic::xtensa_mula_ad_lh: + case Intrinsic::xtensa_mula_ad_hl: + case Intrinsic::xtensa_mula_ad_hh: + case Intrinsic::xtensa_muls_ad_ll: + case Intrinsic::xtensa_muls_ad_lh: + case Intrinsic::xtensa_muls_ad_hl: + case Intrinsic::xtensa_muls_ad_hh: { + SDValue ChainIn = Node->getOperand(0); + SDValue ValueS = Node->getOperand(2); + SDValue ValueMY = Node->getOperand(3); + unsigned OpCode; + + switch (IntNo) { + case Intrinsic::xtensa_mul_ad_ll: + OpCode = Xtensa::MUL_AD_LL; + break; + case Intrinsic::xtensa_mul_ad_lh: + OpCode = Xtensa::MUL_AD_LH; + break; + case Intrinsic::xtensa_mul_ad_hl: + OpCode = Xtensa::MUL_AD_HL; + break; + case Intrinsic::xtensa_mul_ad_hh: + OpCode = Xtensa::MUL_AD_HH; + break; + case Intrinsic::xtensa_mula_ad_ll: + OpCode = Xtensa::MULA_AD_LL; + break; + case Intrinsic::xtensa_mula_ad_lh: + OpCode = Xtensa::MULA_AD_LH; + break; + case Intrinsic::xtensa_mula_ad_hl: + OpCode = Xtensa::MULA_AD_HL; + break; + case Intrinsic::xtensa_mula_ad_hh: + OpCode = Xtensa::MULA_AD_HH; + break; + case Intrinsic::xtensa_muls_ad_ll: + OpCode = Xtensa::MULS_AD_LL; + break; + case Intrinsic::xtensa_muls_ad_lh: + OpCode = Xtensa::MULS_AD_LH; + break; + case Intrinsic::xtensa_muls_ad_hl: + OpCode = Xtensa::MULS_AD_HL; + break; + case Intrinsic::xtensa_muls_ad_hh: + OpCode = Xtensa::MULS_AD_HH; + break; + } + + uint64_t MYVal = 4; + if (ValueMY.getOpcode() == ISD::TargetConstant) { + MYVal = cast(ValueMY)->getZExtValue(); + } + + assert( + ((MYVal > 1) && (MYVal < 4)) && + "Unexpected value of mul*_ad* second argument, it must be m2 or m3"); + unsigned MYReg = MRTable[MYVal]; + + const EVT MULAResTys[] = {MVT::Other}; + SmallVector MULAOps; + MULAOps.push_back(ValueS); + MULAOps.push_back(CurDAG->getRegister(MYReg, MVT::i32)); + MULAOps.push_back(ChainIn); + + SDNode *MULA = CurDAG->getMachineNode(OpCode, DL, MULAResTys, MULAOps); + ReplaceNode(Node, MULA); + return; + } + case Intrinsic::xtensa_mul_dd_ll: + case Intrinsic::xtensa_mul_dd_lh: + case Intrinsic::xtensa_mul_dd_hl: + case Intrinsic::xtensa_mul_dd_hh: + case Intrinsic::xtensa_mula_dd_ll: + case Intrinsic::xtensa_mula_dd_lh: + case Intrinsic::xtensa_mula_dd_hl: + case Intrinsic::xtensa_mula_dd_hh: + case Intrinsic::xtensa_muls_dd_ll: + case Intrinsic::xtensa_muls_dd_lh: + case Intrinsic::xtensa_muls_dd_hl: + case Intrinsic::xtensa_muls_dd_hh: { + SDValue ChainIn = Node->getOperand(0); + SDValue ValueMX = Node->getOperand(2); + SDValue ValueMY = Node->getOperand(3); + unsigned OpCode; + + switch (IntNo) { + case Intrinsic::xtensa_mul_dd_ll: + OpCode = Xtensa::MUL_DD_LL; + break; + case Intrinsic::xtensa_mul_dd_lh: + OpCode = Xtensa::MUL_DD_LH; + break; + case Intrinsic::xtensa_mul_dd_hl: + OpCode = Xtensa::MUL_DD_HL; + break; + case Intrinsic::xtensa_mul_dd_hh: + OpCode = Xtensa::MUL_DD_HH; + break; + case Intrinsic::xtensa_mula_dd_ll: + OpCode = Xtensa::MULA_DD_LL; + break; + case Intrinsic::xtensa_mula_dd_lh: + OpCode = Xtensa::MULA_DD_LH; + break; + case Intrinsic::xtensa_mula_dd_hl: + OpCode = Xtensa::MULA_DD_HL; + break; + case Intrinsic::xtensa_mula_dd_hh: + OpCode = Xtensa::MULA_DD_HH; + break; + case Intrinsic::xtensa_muls_dd_ll: + OpCode = Xtensa::MULS_DD_LL; + break; + case Intrinsic::xtensa_muls_dd_lh: + OpCode = Xtensa::MULS_DD_LH; + break; + case Intrinsic::xtensa_muls_dd_hl: + OpCode = Xtensa::MULS_DD_HL; + break; + case Intrinsic::xtensa_muls_dd_hh: + OpCode = Xtensa::MULS_DD_HH; + break; + } + uint64_t MXVal = 4; + if (ValueMX.getOpcode() == ISD::TargetConstant) { + MXVal = cast(ValueMX)->getZExtValue(); + } + + assert( + (MXVal < 2) && + "Unexpected value of mul*_dd* first argument, it must be m0 or m1"); + unsigned MXReg = MRTable[MXVal]; + + uint64_t MYVal = 4; + if (ValueMY.getOpcode() == ISD::TargetConstant) { + MYVal = cast(ValueMY)->getZExtValue(); + } + + assert( + ((MYVal > 1) && (MYVal < 4)) && + "Unexpected value of mul*_dd* second argument, it must be m2 or m3"); + unsigned MYReg = MRTable[MYVal]; + + const EVT MULAResTys[] = {MVT::Other}; + SmallVector MULAOps; + MULAOps.push_back(CurDAG->getRegister(MXReg, MVT::i32)); + MULAOps.push_back(CurDAG->getRegister(MYReg, MVT::i32)); + MULAOps.push_back(ChainIn); + + SDNode *MULA = CurDAG->getMachineNode(OpCode, DL, MULAResTys, MULAOps); + ReplaceNode(Node, MULA); + return; + } + } + break; + } + default: + break; } SelectCode(Node); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 28ee796295032e..2043a4d0c3f99f 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -2730,6 +2730,268 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( DebugLoc DL = MI.getDebugLoc(); switch (MI.getOpcode()) { + case Xtensa::MULA_DA_LL_LDDEC_P: + case Xtensa::MULA_DA_LH_LDDEC_P: + case Xtensa::MULA_DA_HL_LDDEC_P: + case Xtensa::MULA_DA_HH_LDDEC_P: + case Xtensa::MULA_DA_LL_LDINC_P: + case Xtensa::MULA_DA_LH_LDINC_P: + case Xtensa::MULA_DA_HL_LDINC_P: + case Xtensa::MULA_DA_HH_LDINC_P: { + MachineOperand &MW = MI.getOperand(0); + MachineOperand &S = MI.getOperand(1); + MachineOperand &MX = MI.getOperand(2); + MachineOperand &T = MI.getOperand(3); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned Reg1 = MRI.createVirtualRegister(RC); + unsigned Reg2 = MRI.createVirtualRegister(RC); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::L32I), Reg1) + .addReg(S.getReg()) + .addImm(0); + + unsigned Opc; + switch (MI.getOpcode()) { + case Xtensa::MULA_DA_LL_LDDEC_P: + Opc = Xtensa::MULA_DA_LL_LDDEC; + break; + case Xtensa::MULA_DA_LH_LDDEC_P: + Opc = Xtensa::MULA_DA_LH_LDDEC; + break; + case Xtensa::MULA_DA_HL_LDDEC_P: + Opc = Xtensa::MULA_DA_HL_LDDEC; + break; + case Xtensa::MULA_DA_HH_LDDEC_P: + Opc = Xtensa::MULA_DA_HH_LDDEC; + break; + case Xtensa::MULA_DA_LL_LDINC_P: + Opc = Xtensa::MULA_DA_LL_LDINC; + break; + case Xtensa::MULA_DA_LH_LDINC_P: + Opc = Xtensa::MULA_DA_LH_LDINC; + break; + case Xtensa::MULA_DA_HL_LDINC_P: + Opc = Xtensa::MULA_DA_HL_LDINC; + break; + case Xtensa::MULA_DA_HH_LDINC_P: + Opc = Xtensa::MULA_DA_HH_LDINC; + break; + } + + unsigned MWVal = MW.getImm(); + assert((MWVal < 4) && "Unexpected value of mula_da*ld* first argument, it " + "must be from m0..m3"); + unsigned MXVal = MX.getImm(); + assert((MXVal < 2) && "Unexpected value of mula_da*ld* third " + "argument, it must be m0 or m1"); + + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::M0 + MWVal, RegState::Define) + .addReg(Reg2, RegState::Define) + .addReg(Reg1) + .addReg(Xtensa::M0 + MXVal) + .addReg(T.getReg()); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::S32I)) + .addReg(Reg2) + .addReg(S.getReg()) + .addImm(0); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::MULA_DD_LL_LDDEC_P: + case Xtensa::MULA_DD_LH_LDDEC_P: + case Xtensa::MULA_DD_HL_LDDEC_P: + case Xtensa::MULA_DD_HH_LDDEC_P: + case Xtensa::MULA_DD_LL_LDINC_P: + case Xtensa::MULA_DD_LH_LDINC_P: + case Xtensa::MULA_DD_HL_LDINC_P: + case Xtensa::MULA_DD_HH_LDINC_P: { + MachineOperand &MW = MI.getOperand(0); + MachineOperand &S = MI.getOperand(1); + MachineOperand &MX = MI.getOperand(2); + MachineOperand &MY = MI.getOperand(3); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned Reg1 = MRI.createVirtualRegister(RC); + unsigned Reg2 = MRI.createVirtualRegister(RC); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::L32I), Reg1) + .addReg(S.getReg()) + .addImm(0); + + unsigned Opc; + switch (MI.getOpcode()) { + case Xtensa::MULA_DD_LL_LDDEC_P: + Opc = Xtensa::MULA_DD_LL_LDDEC; + break; + case Xtensa::MULA_DD_LH_LDDEC_P: + Opc = Xtensa::MULA_DD_LH_LDDEC; + break; + case Xtensa::MULA_DD_HL_LDDEC_P: + Opc = Xtensa::MULA_DD_HL_LDDEC; + break; + case Xtensa::MULA_DD_HH_LDDEC_P: + Opc = Xtensa::MULA_DD_HH_LDDEC; + break; + case Xtensa::MULA_DD_LL_LDINC_P: + Opc = Xtensa::MULA_DD_LL_LDINC; + break; + case Xtensa::MULA_DD_LH_LDINC_P: + Opc = Xtensa::MULA_DD_LH_LDINC; + break; + case Xtensa::MULA_DD_HL_LDINC_P: + Opc = Xtensa::MULA_DD_HL_LDINC; + break; + case Xtensa::MULA_DD_HH_LDINC_P: + Opc = Xtensa::MULA_DD_HH_LDINC; + break; + } + + unsigned MWVal = MW.getImm(); + assert((MWVal < 4) && "Unexpected value of mula_dd*ld* first argument, " + "it must be from m0..m3"); + unsigned MXVal = MX.getImm(); + assert((MXVal < 2) && "Unexpected value of mula_dd*ld* third " + "argument, it must be m0 or m1"); + unsigned MYVal = MY.getImm(); + assert(((MYVal > 1) && (MYVal < 4)) && + "Unexpected value of mula_dd*ld* fourth " + "argument, it must be m2 or m3"); + + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::M0 + MWVal, RegState::Define) + .addReg(Reg2, RegState::Define) + .addReg(Reg1) + .addReg(Xtensa::M0 + MXVal) + .addReg(Xtensa::M0 + MYVal); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::S32I)) + .addReg(Reg2) + .addReg(S.getReg()) + .addImm(0); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::XSR_ACCLO_P: + case Xtensa::XSR_ACCHI_P: + case Xtensa::XSR_M0_P: + case Xtensa::XSR_M1_P: + case Xtensa::XSR_M2_P: + case Xtensa::XSR_M3_P: { + MachineOperand &T = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned Reg1 = MRI.createVirtualRegister(RC); + unsigned Reg2 = MRI.createVirtualRegister(RC); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::L32I), Reg1) + .addReg(T.getReg()) + .addImm(0); + + unsigned SReg; + switch (MI.getOpcode()) { + case Xtensa::XSR_ACCLO_P: + SReg = Xtensa::ACCLO; + break; + case Xtensa::XSR_ACCHI_P: + SReg = Xtensa::ACCHI; + break; + case Xtensa::XSR_M0_P: + SReg = Xtensa::M0; + break; + case Xtensa::XSR_M1_P: + SReg = Xtensa::M1; + break; + case Xtensa::XSR_M2_P: + SReg = Xtensa::M2; + break; + case Xtensa::XSR_M3_P: + SReg = Xtensa::M3; + break; + } + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::XSR)) + .addReg(Reg2, RegState::Define) + .addReg(SReg, RegState::Define) + .addReg(Reg1) + .addReg(SReg); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::S32I)) + .addReg(Reg2) + .addReg(T.getReg()) + .addImm(0); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::WSR_ACCLO_P: + case Xtensa::WSR_ACCHI_P: + case Xtensa::WSR_M0_P: + case Xtensa::WSR_M1_P: + case Xtensa::WSR_M2_P: + case Xtensa::WSR_M3_P: { + MachineOperand &T = MI.getOperand(0); + + unsigned SReg; + switch (MI.getOpcode()) { + case Xtensa::WSR_ACCLO_P: + SReg = Xtensa::ACCLO; + break; + case Xtensa::WSR_ACCHI_P: + SReg = Xtensa::ACCHI; + break; + case Xtensa::WSR_M0_P: + SReg = Xtensa::M0; + break; + case Xtensa::WSR_M1_P: + SReg = Xtensa::M1; + break; + case Xtensa::WSR_M2_P: + SReg = Xtensa::M2; + break; + case Xtensa::WSR_M3_P: + SReg = Xtensa::M3; + break; + } + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::WSR)) + .addReg(SReg, RegState::Define) + .addReg(T.getReg()); + MI.eraseFromParent(); + return MBB; + } + case Xtensa::LDDEC_P: + case Xtensa::LDINC_P: { + MachineOperand &MW = MI.getOperand(0); + MachineOperand &S = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned Reg1 = MRI.createVirtualRegister(RC); + unsigned Reg2 = MRI.createVirtualRegister(RC); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::L32I), Reg1) + .addReg(S.getReg()) + .addImm(0); + + unsigned Opc = Xtensa::LDDEC; + + if (MI.getOpcode() == Xtensa::LDINC_P) + Opc = Xtensa::LDINC; + + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::M0 + MW.getImm(), RegState::Define) + .addReg(Reg2, RegState::Define) + .addReg(Reg1); + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::S32I)) + .addReg(Reg2) + .addReg(S.getReg()) + .addImm(0); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::SELECT_CC_FP_FP: case Xtensa::SELECT_CC_FP_INT: case Xtensa::SELECT_CC_INT_FP: diff --git a/llvm/test/CodeGen/Xtensa/lit.local.cfg b/llvm/test/CodeGen/Xtensa/lit.local.cfg new file mode 100644 index 00000000000000..9e0be9979305d3 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'Xtensa' in config.root.targets: + config.unsupported = True diff --git a/llvm/test/CodeGen/Xtensa/mac16_intrinsics.ll b/llvm/test/CodeGen/Xtensa/mac16_intrinsics.ll new file mode 100644 index 00000000000000..fd58c76872aff8 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/mac16_intrinsics.ll @@ -0,0 +1,319 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +define void @test_xtensa_umul(i32 %a, i32 %b) nounwind { +; CHECK-LABEL: test_xtensa_umul +; CHECK: umul.aa.ll a2, a3 + call void @llvm.xtensa.umul.aa.ll(i32 %a, i32 %b) +; CHECK: umul.aa.lh a2, a3 + call void @llvm.xtensa.umul.aa.lh(i32 %a, i32 %b) +; CHECK: umul.aa.hl a2, a3 + call void @llvm.xtensa.umul.aa.hl(i32 %a, i32 %b) +; CHECK: umul.aa.hh a2, a3 + call void @llvm.xtensa.umul.aa.hh(i32 %a, i32 %b) + ret void +} + +define void @test_xtensa_mul(i32 %a, i32 %b) nounwind { +; CHECK-LABEL: test_xtensa_mul +; CHECK: mul.aa.ll a2, a3 + call void @llvm.xtensa.mul.aa.ll(i32 %a, i32 %b) +; CHECK: mul.aa.lh a2, a3 + call void @llvm.xtensa.mul.aa.lh(i32 %a, i32 %b) +; CHECK: mul.aa.hl a2, a3 + call void @llvm.xtensa.mul.aa.hl(i32 %a, i32 %b) +; CHECK: mul.aa.hh a2, a3 + call void @llvm.xtensa.mul.aa.hh(i32 %a, i32 %b) +; CHECK: mul.ad.ll a2, m2 + call void @llvm.xtensa.mul.ad.ll(i32 %a, i32 2) +; CHECK: mul.ad.lh a2, m2 + call void @llvm.xtensa.mul.ad.lh(i32 %a, i32 2) +; CHECK: mul.ad.hl a2, m2 + call void @llvm.xtensa.mul.ad.hl(i32 %a, i32 2) +; CHECK: mul.ad.hh a2, m2 + call void @llvm.xtensa.mul.ad.hh(i32 %a, i32 2) +; CHECK: mul.da.ll m1, a3 + call void @llvm.xtensa.mul.da.ll(i32 1, i32 %b) +; CHECK: mul.da.lh m1, a3 + call void @llvm.xtensa.mul.da.lh(i32 1, i32 %b) +; CHECK: mul.da.hl m1, a3 + call void @llvm.xtensa.mul.da.hl(i32 1, i32 %b) +; CHECK: mul.da.hh m1, a3 + call void @llvm.xtensa.mul.da.hh(i32 1, i32 %b) +; CHECK: mul.dd.ll m1, m2 + call void @llvm.xtensa.mul.dd.ll(i32 1, i32 2) +; CHECK: mul.dd.lh m1, m2 + call void @llvm.xtensa.mul.dd.lh(i32 1, i32 2) +; CHECK: mul.dd.hl m1, m2 + call void @llvm.xtensa.mul.dd.hl(i32 1, i32 2) +; CHECK: mul.dd.hh m1, m2 + call void @llvm.xtensa.mul.dd.hh(i32 1, i32 2) + ret void +} + +define void @test_xtensa_mula(i32 %a, i32 %b) nounwind { +; CHECK-LABEL: test_xtensa_mula +; CHECK: mula.aa.ll a2, a3 + call void @llvm.xtensa.mula.aa.ll(i32 %a, i32 %b) +; CHECK: mula.aa.lh a2, a3 + call void @llvm.xtensa.mula.aa.lh(i32 %a, i32 %b) +; CHECK: mula.aa.hl a2, a3 + call void @llvm.xtensa.mula.aa.hl(i32 %a, i32 %b) +; CHECK: mula.aa.hh a2, a3 + call void @llvm.xtensa.mula.aa.hh(i32 %a, i32 %b) +; CHECK: mula.ad.ll a2, m2 + call void @llvm.xtensa.mula.ad.ll(i32 %a, i32 2) +; CHECK: mula.ad.lh a2, m2 + call void @llvm.xtensa.mula.ad.lh(i32 %a, i32 2) +; CHECK: mula.ad.hl a2, m2 + call void @llvm.xtensa.mula.ad.hl(i32 %a, i32 2) +; CHECK: mula.ad.hh a2, m2 + call void @llvm.xtensa.mula.ad.hh(i32 %a, i32 2) +; CHECK: mula.da.ll m1, a3 + call void @llvm.xtensa.mula.da.ll(i32 1, i32 %b) +; CHECK: mula.da.lh m1, a3 + call void @llvm.xtensa.mula.da.lh(i32 1, i32 %b) +; CHECK: mula.da.hl m1, a3 + call void @llvm.xtensa.mula.da.hl(i32 1, i32 %b) +; CHECK: mula.da.hh m1, a3 + call void @llvm.xtensa.mula.da.hh(i32 1, i32 %b) +; CHECK: mula.dd.ll m1, m2 + call void @llvm.xtensa.mula.dd.ll(i32 1, i32 2) +; CHECK: mula.dd.lh m1, m2 + call void @llvm.xtensa.mula.dd.lh(i32 1, i32 2) +; CHECK: mula.dd.hl m1, m2 + call void @llvm.xtensa.mula.dd.hl(i32 1, i32 2) +; CHECK: mula.dd.hh m1, m2 + call void @llvm.xtensa.mula.dd.hh(i32 1, i32 2) + ret void +} + +define void @test_xtensa_muls(i32 %a, i32 %b) nounwind { +; CHECK-LABEL: test_xtensa_muls +; CHECK: muls.aa.ll a2, a3 + call void @llvm.xtensa.muls.aa.ll(i32 %a, i32 %b) +; CHECK: muls.aa.lh a2, a3 + call void @llvm.xtensa.muls.aa.lh(i32 %a, i32 %b) +; CHECK: muls.aa.hl a2, a3 + call void @llvm.xtensa.muls.aa.hl(i32 %a, i32 %b) +; CHECK: muls.aa.hh a2, a3 + call void @llvm.xtensa.muls.aa.hh(i32 %a, i32 %b) +; CHECK: muls.ad.ll a2, m2 + call void @llvm.xtensa.muls.ad.ll(i32 %a, i32 2) +; CHECK: muls.ad.lh a2, m2 + call void @llvm.xtensa.muls.ad.lh(i32 %a, i32 2) +; CHECK: muls.ad.hl a2, m2 + call void @llvm.xtensa.muls.ad.hl(i32 %a, i32 2) +; CHECK: muls.ad.hh a2, m2 + call void @llvm.xtensa.muls.ad.hh(i32 %a, i32 2) +; CHECK: muls.da.ll m1, a3 + call void @llvm.xtensa.muls.da.ll(i32 1, i32 %b) +; CHECK: muls.da.lh m1, a3 + call void @llvm.xtensa.muls.da.lh(i32 1, i32 %b) +; CHECK: muls.da.hl m1, a3 + call void @llvm.xtensa.muls.da.hl(i32 1, i32 %b) +; CHECK: muls.da.hh m1, a3 + call void @llvm.xtensa.muls.da.hh(i32 1, i32 %b) +; CHECK: muls.dd.ll m1, m2 + call void @llvm.xtensa.muls.dd.ll(i32 1, i32 2) +; CHECK: muls.dd.lh m1, m2 + call void @llvm.xtensa.muls.dd.lh(i32 1, i32 2) +; CHECK: muls.dd.hl m1, m2 + call void @llvm.xtensa.muls.dd.hl(i32 1, i32 2) +; CHECK: muls.dd.hh m1, m2 + call void @llvm.xtensa.muls.dd.hh(i32 1, i32 2) + ret void +} + +define void @test_xtensa_mula_ld(i32 %pa.coerce, i32 %b) nounwind { +; CHECK-LABEL: test_xtensa_mula_ld +entry: + %0 = inttoptr i32 %pa.coerce to i8* +; CHECK: mula.da.ll.lddec m1, a{{[0-9]+}}, m0, a3 + call void @llvm.xtensa.mula.da.ll.lddec(i32 1, i8* %0, i32 0, i32 %b) +; CHECK: mula.da.lh.lddec m1, a{{[0-9]+}}, m0, a3 + call void @llvm.xtensa.mula.da.lh.lddec(i32 1, i8* %0, i32 0, i32 %b) +; CHECK: mula.da.hl.lddec m1, a{{[0-9]+}}, m0, a3 + call void @llvm.xtensa.mula.da.hl.lddec(i32 1, i8* %0, i32 0, i32 %b) +; CHECK: mula.da.hh.lddec m1, a{{[0-9]+}}, m0, a3 + call void @llvm.xtensa.mula.da.hh.lddec(i32 1, i8* %0, i32 0, i32 %b) +; CHECK: mula.dd.ll.lddec m1, a{{[0-9]+}}, m0, m2 + call void @llvm.xtensa.mula.dd.ll.lddec(i32 1, i8* %0, i32 0, i32 2) +; CHECK: mula.dd.lh.lddec m1, a{{[0-9]+}}, m0, m2 + call void @llvm.xtensa.mula.dd.lh.lddec(i32 1, i8* %0, i32 0, i32 2) +; CHECK: mula.dd.hl.lddec m1, a{{[0-9]+}}, m0, m2 + call void @llvm.xtensa.mula.dd.hl.lddec(i32 1, i8* %0, i32 0, i32 2) +; CHECK: mula.dd.hh.lddec m1, a{{[0-9]+}}, m0, m2 + call void @llvm.xtensa.mula.dd.hh.lddec(i32 1, i8* %0, i32 0, i32 2) +; CHECK: mula.da.ll.ldinc m1, a{{[0-9]+}}, m0, a3 + call void @llvm.xtensa.mula.da.ll.ldinc(i32 1, i8* %0, i32 0, i32 %b) +; CHECK: mula.da.lh.ldinc m1, a{{[0-9]+}}, m0, a3 + call void @llvm.xtensa.mula.da.lh.ldinc(i32 1, i8* %0, i32 0, i32 %b) +; CHECK: mula.da.hl.ldinc m1, a{{[0-9]+}}, m0, a3 + call void @llvm.xtensa.mula.da.hl.ldinc(i32 1, i8* %0, i32 0, i32 %b) +; CHECK: mula.da.hh.ldinc m1, a{{[0-9]+}}, m0, a3 + call void @llvm.xtensa.mula.da.hh.ldinc(i32 1, i8* %0, i32 0, i32 %b) +; CHECK: mula.dd.ll.ldinc m1, a{{[0-9]+}}, m0, m2 + call void @llvm.xtensa.mula.dd.ll.ldinc(i32 1, i8* %0, i32 0, i32 2) +; CHECK: mula.dd.lh.ldinc m1, a{{[0-9]+}}, m0, m2 + call void @llvm.xtensa.mula.dd.lh.ldinc(i32 1, i8* %0, i32 0, i32 2) +; CHECK: mula.dd.hl.ldinc m1, a{{[0-9]+}}, m0, m2 + call void @llvm.xtensa.mula.dd.hl.ldinc(i32 1, i8* %0, i32 0, i32 2) +; CHECK: mula.dd.hh.ldinc m1, a{{[0-9]+}}, m0, m2 + call void @llvm.xtensa.mula.dd.hh.ldinc(i32 1, i8* %0, i32 0, i32 2) + ret void +} + +define void @test_xtensa_ld(i32 %pa.coerce) nounwind { +; CHECK-LABEL: test_xtensa_ld +entry: + %0 = inttoptr i32 %pa.coerce to i8* +; CHECK: lddec m0, a{{[0-9]+}} + call void @llvm.xtensa.lddec(i32 0, i8* %0) +; CHECK: ldinc m0, a{{[0-9]+}} + call void @llvm.xtensa.ldinc(i32 0, i8* %0) + ret void +} + +define void @test_xtensa_wsr(i32 %a) { +; CHECK-LABEL: test_xtensa_wsr +; CHECK: wsr a2, acclo + call void @llvm.xtensa.wsr.acclo(i32 %a) +; CHECK: wsr a2, acchi + call void @llvm.xtensa.wsr.acchi(i32 %a) +; CHECK: wsr a2, m0 + call void @llvm.xtensa.wsr.m0(i32 %a) +; CHECK: wsr a2, m1 + call void @llvm.xtensa.wsr.m1(i32 %a) +; CHECK: wsr a2, m2 + call void @llvm.xtensa.wsr.m2(i32 %a) +; CHECK: wsr a2, m3 + call void @llvm.xtensa.wsr.m3(i32 %a) + ret void +} + +define void @test_xtensa_xsr(i32 %a.coerce) { +; CHECK-LABEL: test_xtensa_xsr +entry: + %0 = inttoptr i32 %a.coerce to i8* +; CHECK: xsr a{{[0-9]+}}, acclo + call void @llvm.xtensa.xsr.acclo(i8* %0) +; CHECK: xsr a{{[0-9]+}}, acchi + call void @llvm.xtensa.xsr.acchi(i8* %0) +; CHECK: xsr a{{[0-9]+}}, m0 + call void @llvm.xtensa.xsr.m0(i8* %0) +; CHECK: xsr a{{[0-9]+}}, m1 + call void @llvm.xtensa.xsr.m1(i8* %0) +; CHECK: xsr a{{[0-9]+}}, m2 + call void @llvm.xtensa.xsr.m2(i8* %0) +; CHECK: xsr a{{[0-9]+}}, m3 + call void @llvm.xtensa.xsr.m3(i8* %0) + ret void +} + +define void @test_xtensa_rsr() { +; CHECK-LABEL: test_xtensa_rsr +entry: +; CHECK: rsr a{{[0-9]+}}, acclo + %0 = call i32 @llvm.xtensa.rsr.acclo() +; CHECK: rsr a{{[0-9]+}}, acchi + %1 = call i32 @llvm.xtensa.rsr.acchi() +; CHECK: rsr a{{[0-9]+}}, m0 + %2 = call i32 @llvm.xtensa.rsr.m0() +; CHECK: rsr a{{[0-9]+}}, m1 + %3 = call i32 @llvm.xtensa.rsr.m1() +; CHECK: rsr a{{[0-9]+}}, m2 + %4 = call i32 @llvm.xtensa.rsr.m2() +; CHECK: rsr a{{[0-9]+}}, m3 + %5 = call i32 @llvm.xtensa.rsr.m3() + ret void +} + +declare void @llvm.xtensa.umul.aa.ll(i32, i32) nounwind +declare void @llvm.xtensa.umul.aa.lh(i32, i32) nounwind +declare void @llvm.xtensa.umul.aa.hl(i32, i32) nounwind +declare void @llvm.xtensa.umul.aa.hh(i32, i32) nounwind +declare void @llvm.xtensa.mul.aa.ll(i32, i32) nounwind +declare void @llvm.xtensa.mul.aa.lh(i32, i32) nounwind +declare void @llvm.xtensa.mul.aa.hl(i32, i32) nounwind +declare void @llvm.xtensa.mul.aa.hh(i32, i32) nounwind +declare void @llvm.xtensa.mul.ad.ll(i32, i32 immarg) nounwind +declare void @llvm.xtensa.mul.ad.lh(i32, i32 immarg) nounwind +declare void @llvm.xtensa.mul.ad.hl(i32, i32 immarg) nounwind +declare void @llvm.xtensa.mul.ad.hh(i32, i32 immarg) nounwind +declare void @llvm.xtensa.mul.da.ll(i32 immarg, i32) nounwind +declare void @llvm.xtensa.mul.da.lh(i32 immarg, i32) nounwind +declare void @llvm.xtensa.mul.da.hl(i32 immarg, i32) nounwind +declare void @llvm.xtensa.mul.da.hh(i32 immarg, i32) nounwind +declare void @llvm.xtensa.mul.dd.ll(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mul.dd.lh(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mul.dd.hl(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mul.dd.hh(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.aa.ll(i32, i32) nounwind +declare void @llvm.xtensa.mula.aa.lh(i32, i32) nounwind +declare void @llvm.xtensa.mula.aa.hl(i32, i32) nounwind +declare void @llvm.xtensa.mula.aa.hh(i32, i32) nounwind +declare void @llvm.xtensa.mula.ad.ll(i32, i32 immarg) nounwind +declare void @llvm.xtensa.mula.ad.lh(i32, i32 immarg) nounwind +declare void @llvm.xtensa.mula.ad.hl(i32, i32 immarg) nounwind +declare void @llvm.xtensa.mula.ad.hh(i32, i32 immarg) nounwind +declare void @llvm.xtensa.mula.da.ll(i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.lh(i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.hl(i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.hh(i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.dd.ll(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.lh(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.hl(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.hh(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.muls.aa.ll(i32, i32) nounwind +declare void @llvm.xtensa.muls.aa.lh(i32, i32) nounwind +declare void @llvm.xtensa.muls.aa.hl(i32, i32) nounwind +declare void @llvm.xtensa.muls.aa.hh(i32, i32) nounwind +declare void @llvm.xtensa.muls.ad.ll(i32, i32 immarg) nounwind +declare void @llvm.xtensa.muls.ad.lh(i32, i32 immarg) nounwind +declare void @llvm.xtensa.muls.ad.hl(i32, i32 immarg) nounwind +declare void @llvm.xtensa.muls.ad.hh(i32, i32 immarg) nounwind +declare void @llvm.xtensa.muls.da.ll(i32 immarg, i32) nounwind +declare void @llvm.xtensa.muls.da.lh(i32 immarg, i32) nounwind +declare void @llvm.xtensa.muls.da.hl(i32 immarg, i32) nounwind +declare void @llvm.xtensa.muls.da.hh(i32 immarg, i32) nounwind +declare void @llvm.xtensa.muls.dd.ll(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.muls.dd.lh(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.muls.dd.hl(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.muls.dd.hh(i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.da.ll.lddec(i32 immarg, i8*, i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.lh.lddec(i32 immarg, i8*, i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.hl.lddec(i32 immarg, i8*, i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.hh.lddec(i32 immarg, i8*, i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.dd.ll.lddec(i32 immarg, i8*, i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.lh.lddec(i32 immarg, i8*, i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.hl.lddec(i32 immarg, i8*, i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.hh.lddec(i32 immarg, i8*, i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.da.ll.ldinc(i32 immarg, i8*, i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.lh.ldinc(i32 immarg, i8*, i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.hl.ldinc(i32 immarg, i8*, i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.da.hh.ldinc(i32 immarg, i8*, i32 immarg, i32) nounwind +declare void @llvm.xtensa.mula.dd.ll.ldinc(i32 immarg, i8*, i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.lh.ldinc(i32 immarg, i8*, i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.hl.ldinc(i32 immarg, i8*, i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.mula.dd.hh.ldinc(i32 immarg, i8*, i32 immarg, i32 immarg) nounwind +declare void @llvm.xtensa.lddec(i32 immarg, i8*) nounwind +declare void @llvm.xtensa.ldinc(i32 immarg, i8*) nounwind +declare i32 @llvm.xtensa.rsr.acclo() nounwind +declare i32 @llvm.xtensa.rsr.acchi() nounwind +declare i32 @llvm.xtensa.rsr.m0() nounwind +declare i32 @llvm.xtensa.rsr.m1() nounwind +declare i32 @llvm.xtensa.rsr.m2() nounwind +declare i32 @llvm.xtensa.rsr.m3() nounwind +declare void @llvm.xtensa.xsr.acclo(i8*) nounwind +declare void @llvm.xtensa.xsr.acchi(i8*) nounwind +declare void @llvm.xtensa.xsr.m0(i8*) nounwind +declare void @llvm.xtensa.xsr.m1(i8*) nounwind +declare void @llvm.xtensa.xsr.m2(i8*) nounwind +declare void @llvm.xtensa.xsr.m3(i8*) nounwind +declare void @llvm.xtensa.wsr.acclo(i32) nounwind +declare void @llvm.xtensa.wsr.acchi(i32) nounwind +declare void @llvm.xtensa.wsr.m0(i32) nounwind +declare void @llvm.xtensa.wsr.m1(i32) nounwind +declare void @llvm.xtensa.wsr.m2(i32) nounwind +declare void @llvm.xtensa.wsr.m3(i32) nounwind + diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn index a594d2afbf7d64..2f95a445bb97b8 100644 --- a/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn @@ -101,6 +101,10 @@ gen_arch_intrinsics("IntrinsicsXCore") { intrinsic_prefix = "xcore" } +gen_arch_intrinsics("IntrinsicsXtensa") { + intrinsic_prefix = "xtensa" +} + # Groups all tablegen() calls that create .inc files that are included in # IR's public headers. //llvm/lib/IR has this as a public_dep, so targets # depending on //llvm/lib/IR don't need to depend on this. This exists @@ -132,5 +136,6 @@ group("public_tablegen") { ":IntrinsicsWebAssembly", ":IntrinsicsX86", ":IntrinsicsXCore", + ":IntrinsicsXtensa", ] } From 675210a506771726d4f76d00c965e3b414f18b06 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:44 +0300 Subject: [PATCH 052/261] Implement lowering llvm intrinsics fshr/fshl. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 27 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 1 + llvm/test/CodeGen/Xtensa/funnel-shift.ll | 24 +++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 llvm/test/CodeGen/Xtensa/funnel-shift.ll diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 2043a4d0c3f99f..ac37b4b3ad6e30 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -188,6 +188,10 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); + // Funnel shifts + setOperationAction(ISD::FSHR, MVT::i32, Custom); + setOperationAction(ISD::FSHL, MVT::i32, Custom); + // Bit Manipulation setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i64, Expand); @@ -1688,6 +1692,26 @@ SDValue XtensaTargetLowering::LowerShiftRightParts(SDValue Op, return DAG.getMergeValues(Ops, DL); } +SDValue XtensaTargetLowering::LowerFunnelShift(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Op0 = Op.getOperand(0); + SDValue Op1 = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + MVT VT = Op.getSimpleValueType(); + + bool IsFSHR = Op.getOpcode() == ISD::FSHR; + assert((VT == MVT::i32) && "Unexpected funnel shift type!"); + + if (!IsFSHR) { + Shamt = DAG.getNode(ISD::SUB, DL, MVT::i32, + DAG.getConstant(32, DL, MVT::i32), Shamt); + } + SDValue SetSAR = DAG.getNode(XtensaISD::SSR, DL, + MVT::Glue, Shamt); + return DAG.getNode(XtensaISD::SRC, DL, VT, Op0, Op1, SetSAR); +} + SDValue XtensaTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); @@ -1742,6 +1766,9 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, return LowerShiftRightParts(Op, DAG, true); case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); + case ISD::FSHL: + case ISD::FSHR: + return LowerFunnelShift(Op, DAG); default: llvm_unreachable("Unexpected node to lower"); } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 9a116a92cbc59b..a15906654a54aa 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -193,6 +193,7 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; + SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const; SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/test/CodeGen/Xtensa/funnel-shift.ll b/llvm/test/CodeGen/Xtensa/funnel-shift.ll new file mode 100644 index 00000000000000..09bf081be37379 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/funnel-shift.ll @@ -0,0 +1,24 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +define dso_local i32 @test_fshr(i32 %value1, i32 %value2, i32 %shift) nounwind { +; CHECK-LABEL: @test_fshr +; CHECK: ssr a4 +; CHECK: src a2, a2, a3 +entry: + %0 = tail call i32 @llvm.fshr.i32(i32 %value1, i32 %value2, i32 %shift) + ret i32 %0 +} + +define dso_local i32 @test_fshl(i32 %value1, i32 %value2, i32 %shift) nounwind { +; CHECK-LABEL: @test_fshl +; CHECK: movi.n a8, 32 +; CHECK: sub a8, a8, a4 +; CHECK: ssr a8 +; CHECK: src a2, a2, a3 +entry: + %0 = tail call i32 @llvm.fshl.i32(i32 %value1, i32 %value2, i32 %shift) + ret i32 %0 +} + +declare i32 @llvm.fshr.i32(i32, i32, i32) nounwind +declare i32 @llvm.fshl.i32(i32, i32, i32) nounwind From 530950f8ee340603f6ee585024431f50ecc316d9 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 21 Sep 2023 00:17:02 +0300 Subject: [PATCH 053/261] Add functions needed to use as rust submodule. --- llvm/include/llvm/MC/MCSubtargetInfo.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/llvm/include/llvm/MC/MCSubtargetInfo.h b/llvm/include/llvm/MC/MCSubtargetInfo.h index f172a799aa3331..eda27051d0debe 100644 --- a/llvm/include/llvm/MC/MCSubtargetInfo.h +++ b/llvm/include/llvm/MC/MCSubtargetInfo.h @@ -240,6 +240,14 @@ class MCSubtargetInfo { return ProcFeatures; } + ArrayRef getCPUTable() const { + return ProcDesc; + } + + ArrayRef getFeatureTable() const { + return ProcFeatures; + } + virtual unsigned getHwMode() const { return 0; } /// Return the cache size in bytes for the given level of cache. From 8f8431c3612711eca6a4b701d666e7b415192c1c Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:45 +0300 Subject: [PATCH 054/261] [Xtensa] Correct Call ABI for function return arguments. --- clang/lib/CodeGen/Targets/Xtensa.cpp | 12 +++++++++--- clang/test/CodeGen/xtensa-abi.c | 14 ++++++++++++++ 2 files changed, 23 insertions(+), 3 deletions(-) create mode 100644 clang/test/CodeGen/xtensa-abi.c diff --git a/clang/lib/CodeGen/Targets/Xtensa.cpp b/clang/lib/CodeGen/Targets/Xtensa.cpp index 5bec6c493aeaa5..506e92ea76ffce 100644 --- a/clang/lib/CodeGen/Targets/Xtensa.cpp +++ b/clang/lib/CodeGen/Targets/Xtensa.cpp @@ -119,10 +119,16 @@ ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty, ABIArgInfo XtensaABIInfo::classifyReturnType(QualType RetTy) const { if (RetTy->isVoidType()) return ABIArgInfo::getIgnore(); + int ArgGPRsLeft = MaxNumRetGPRs; - // The rules for return and argument types are the same, so defer to - // classifyArgumentType. - return classifyArgumentType(RetTy, ArgGPRsLeft); + auto RetSize = llvm::alignTo(getContext().getTypeSize(RetTy), 32) / 32; + + // The rules for return and argument with type size more then 4 bytes + // are the same, so defer to classifyArgumentType. + if (RetSize > 1) + return classifyArgumentType(RetTy, ArgGPRsLeft); + + return DefaultABIInfo::classifyReturnType(RetTy); } Address XtensaABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, diff --git a/clang/test/CodeGen/xtensa-abi.c b/clang/test/CodeGen/xtensa-abi.c new file mode 100644 index 00000000000000..df7a99d77bc0f4 --- /dev/null +++ b/clang/test/CodeGen/xtensa-abi.c @@ -0,0 +1,14 @@ +// RUN: %clang_cc1 -triple xtensa -O0 -emit-llvm %s -o - | FileCheck %s + +#define __malloc_like __attribute__((__malloc__)) +char *bufalloc () __malloc_like ;//__result_use_check; +extern void* malloc (unsigned size); + +char *bufalloc () +{ + char* buf = malloc(1024); + + return buf; +} + +// CHECK: define dso_local noalias ptr @bufalloc() #0 { From 3ebc3df807ee65663c4fc5904522801beb2fe468 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:46 +0300 Subject: [PATCH 055/261] [Xtensa] Implement rest part of FP instructions. Add FP instructions test, format FP instruction descriptions. --- .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 6 +- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 10 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 4 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 263 ++++++++++++------ llvm/test/MC/Xtensa/xtensa-valid-float.s | 178 ++++++++++++ 5 files changed, 366 insertions(+), 95 deletions(-) create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-float.s diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 01c7bd4bd31857..88daa562baedc2 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -281,8 +281,10 @@ XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo, case Xtensa::L32I: case Xtensa::S32I_N: case Xtensa::L32I_N: - case Xtensa::S32F: - case Xtensa::L32F: + case Xtensa::SSI: + case Xtensa::SSIP: + case Xtensa::LSI: + case Xtensa::LSIP: case Xtensa::S32C1I: if (Res & 0x3) { report_fatal_error("Unexpected operand value!"); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index ac37b4b3ad6e30..0996d3cb405e8c 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -3192,13 +3192,19 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( case Xtensa::S16I: case Xtensa::S32I: case Xtensa::S32I_N: - case Xtensa::S32F: + case Xtensa::SSI: + case Xtensa::SSIP: + case Xtensa::SSX: + case Xtensa::SSXP: case Xtensa::L8UI: case Xtensa::L16SI: case Xtensa::L16UI: case Xtensa::L32I: case Xtensa::L32I_N: - case Xtensa::L32F: { + case Xtensa::LSI: + case Xtensa::LSIP: + case Xtensa::LSX: + case Xtensa::LSXP: { const MachineMemOperand &MMO = **MI.memoperands_begin(); if (MMO.isVolatile()) { BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW)); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index e957609c337dc5..6aea911634204a 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -146,8 +146,8 @@ void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, LoadOpcode = Xtensa::L32I; StoreOpcode = Xtensa::S32I; } else if (RC == &Xtensa::FPRRegClass) { - LoadOpcode = Xtensa::L32F; - StoreOpcode = Xtensa::S32F; + LoadOpcode = Xtensa::LSI; + StoreOpcode = Xtensa::SSI; } else llvm_unreachable("Unsupported regclass to load or store"); } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 38e8fac327cb81..743d1c4a757346 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -962,85 +962,63 @@ def ADD_S : FPArith_RRR<0x00, 0x0A, "add.s", fadd, 1>; def SUB_S : FPArith_RRR<0x01, 0x0A, "sub.s", fsub>; def MUL_S : FPArith_RRR<0x02, 0x0A, "mul.s", fmul, 1>; -def ABS_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), - "abs.s\t$r, $s", - [(set FPR:$r, (fabs FPR:$s))]> { - let t = 0x01; -} - -def NEG_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), - "neg.s\t$r, $s", - [(set FPR:$r, (fneg FPR:$s))]> { - let t = 0x06; -} +// FP load instructions +let mayLoad = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { + def LSI : RRI8_Inst<0x03, (outs FPR:$t), (ins mem32:$addr), + "lsi\t$t, $addr", []> { + bits<12> addr; -def TRUNC_S : RRR_Inst<0x00, 0x0A, 0x09, (outs AR:$r), (ins FPR:$s), - "trunc.s\t$r, $s, 0", - [(set AR:$r, (fp_to_sint FPR:$s))]> { - let t = 0x00; -} + let r = 0x00; + let imm8{7-0} = addr{11-4}; + let s{3-0} = addr{3-0}; + } -def UTRUNC_S : RRR_Inst<0x00, 0x0A, 0x0e, (outs AR:$r), (ins FPR:$s), - "utrunc.s\t$r, $s, 0", - [(set AR:$r, (fp_to_uint FPR:$s))]> { - let t = 0x00; -} + def LSIP : RRI8_Inst<0x03, (outs FPR:$t), (ins mem32:$addr), + "lsip\t$t, $addr", []> { + bits<12> addr; -def FLOAT_S : RRR_Inst<0x00, 0x0A, 0x0c, (outs FPR:$r), (ins AR:$s), - "float.s\t$r, $s, 0", - [(set FPR:$r, (sint_to_fp AR:$s))]> { - let t = 0x00; -} + let r = 0x08; + let imm8{7-0} = addr{11-4}; + let s{3-0} = addr{3-0}; + } -def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s), - "ufloat.s\t$r, $s, 0", - [(set FPR:$r, (uint_to_fp AR:$s))]> { - let t = 0x00; -} + def LSX : RRR_Inst<0x00, 0x08, 0x00, (outs), (ins FPR:$r, AR:$s, AR:$t), + "lsx\t$r, $s, $t", []>; -def RFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs AR:$r), (ins FPR:$s), - "rfr\t$r, $s", - [(set AR:$r, (bitconvert FPR:$s))]> { - let t = 0x04; + def LSXP : RRR_Inst<0x00, 0x08, 0x01, (outs), (ins FPR:$r, AR:$s, AR:$t), + "lsxp\t$r, $s, $t", []>; } -def WFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins AR:$s), - "wfr\t$r, $s", - [(set FPR:$r, (bitconvert AR:$s))]> { - let t = 0x05; -} +def : Pat<(f32 (load addr_ish4:$addr)), (f32 (LSI mem32:$addr))>; -// FP load instructions -let mayLoad = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { - class LoadF_RRI8 oper, string instrAsm, SDPatternOperator opNode, - ComplexPattern addrOp,Operand memOp>: RRI8_Inst<0x03, (outs FPR:$t), (ins memOp:$addr), - instrAsm#"\t$t, $addr", - [(set FPR:$t, (opNode addrOp:$addr))]> { +// FP store instructions +let mayStore = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { + def SSI : RRI8_Inst<0x03, (outs), (ins FPR:$t, mem32:$addr), + "ssi\t$t, $addr", []> { bits<12> addr; - let r = oper; + let r = 0x04; let imm8{7-0} = addr{11-4}; let s{3-0} = addr{3-0}; } -} - -def L32F : LoadF_RRI8<0x00, "lsi", load, addr_ish4, mem32>, Requires<[]>; -// FP store instructions -let mayStore = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { - class StoreF_RRI8 oper, string instrAsm, SDPatternOperator opNode, - ComplexPattern addrOp, Operand memOp>: RRI8_Inst<0x03, (outs), (ins FPR:$t, memOp:$addr), - instrAsm#"\t$t, $addr", - [(opNode FPR:$t, addrOp:$addr)]> { + def SSIP : RRI8_Inst<0x03, (outs), (ins FPR:$t, mem32:$addr), + "ssip\t$t, $addr", []> { bits<12> addr; - let r = oper; + let r = 0x0C; let imm8{7-0} = addr{11-4}; let s{3-0} = addr{3-0}; } + + def SSX: RRR_Inst<0x00, 0x08, 0x04, (outs), (ins FPR:$r, AR:$s, AR:$t), + "ssx\t$r, $s, $t", []>; + + def SSXP: RRR_Inst<0x00, 0x08, 0x05, (outs), (ins FPR:$r, AR:$s, AR:$t), + "ssxp\t$r, $s, $t", []>; } -def S32F : StoreF_RRI8<0x04, "ssi", store, addr_ish4, mem32>; +def : Pat<(store FPR:$t, addr_ish4:$addr), (SSI FPR:$t, mem32:$addr)>; // FP compare instructions let isCompare = 1, Predicates = [HasSingleFloat] in { @@ -1064,31 +1042,27 @@ def ULT_S : FCompare<0x05, 0x0b, "ult.s", Xtensa_cmpult, 0>; def ULE_S : FCompare<0x07, 0x0b, "ule.s", Xtensa_cmpule, 0>; def UN_S : FCompare<0x01, 0x0b, "un.s", Xtensa_cmpuo, 1>; -//FP complex operations -def MADD_S : RRR_Inst<0x00, 0x0A, 0x04, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), - "madd.s\t$r, $s, $t", - [(set FPR:$r, (Xtensa_madd FPR:$a, FPR:$s, FPR:$t))]>, - Requires<[HasSingleFloat]> { - let isCommutable = 0; - let isReMaterializable = 0; - let Constraints = "$r = $a"; +def ABS_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "abs.s\t$r, $s", + [(set FPR:$r, (fabs FPR:$s))]> { + let t = 0x01; } -def MSUB_S : RRR_Inst<0x00, 0x0A, 0x05, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), - "msub.s\t$r, $s, $t", - [(set FPR:$r, (Xtensa_msub FPR:$a, FPR:$s, FPR:$t))]>, - Requires<[HasSingleFloat]> { - let isCommutable = 0; - let isReMaterializable = 0; - let Constraints = "$r = $a"; +def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "addexp.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x0E; } -//FP move operations -def MOV_S : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins FPR:$s), - "mov.s\t$r, $s", - [(set FPR:$r, (Xtensa_movs FPR:$s))]>, Requires<[HasSingleFloat]> -{ - let t = 0x00; +def ADDEXPM_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "addexpm.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x0F; +} + +def CEIL_S : RRR_Inst<0x00, 0x0A, 0x0B, (outs AR:$r), (ins FPR:$s, uimm4:$imm), + "ceil.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { + bits<4> imm; + + let t = imm; } def CONST_S : RRR_Inst<0x00, 0x0a, 0x0f, (outs FPR:$r), (ins uimm4:$imm), @@ -1104,11 +1078,40 @@ def DIV0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), let t = 0x7; } +def DIVN_S : RRR_Inst<0x00, 0x0A, 0x07, (outs FPR:$r), (ins FPR:$s, FPR:$t), + "divn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; + +def FLOAT_S : RRR_Inst<0x00, 0x0A, 0x0c, (outs FPR:$r), (ins AR:$s, uimm4:$imm), + "float.s\t$r, $s, $imm", []> { + bits<4> imm; + + let t = imm; +} + +def : Pat<(f32 (sint_to_fp AR:$s)), (FLOAT_S AR:$s, 0)>; + +def FLOOR_S : RRR_Inst<0x00, 0x0A, 0x0A, (outs AR:$r), (ins FPR:$s, uimm4:$imm), + "floor.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { + bits<4> imm; + + let t = imm; +} + def MADDN_S : RRR_Inst<0x00, 0x0A, 0x06, (outs FPR:$r), (ins FPR:$s, FPR:$t), "maddn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]> { let isCommutable = 0; } +// FP multipy-add +def MADD_S : RRR_Inst<0x00, 0x0A, 0x04, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), + "madd.s\t$r, $s, $t", + [(set FPR:$r, (Xtensa_madd FPR:$a, FPR:$s, FPR:$t))]>, + Requires<[HasSingleFloat]> { + let isCommutable = 0; + let isReMaterializable = 0; + let Constraints = "$r = $a"; +} + def MKDADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "mkdadj.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0D; @@ -1119,29 +1122,112 @@ def MKSADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), let t = 0x0C; } -def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), - "addexp.s\t$r, $s", []>, Requires<[HasSingleFloat]> { - let t = 0x0E; +// FP move instructions +def MOV_S : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins FPR:$s), + "mov.s\t$r, $s", + [(set FPR:$r, (Xtensa_movs FPR:$s))]>, Requires<[HasSingleFloat]> { + let t = 0x00; } -def ADDEXPM_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), - "addexpm.s\t$r, $s", []>, Requires<[HasSingleFloat]> { - let t = 0x0F; -} +def MOVEQZ_S : RRR_Inst<0x00, 0x0B, 0x08, (outs FPR:$r), (ins FPR:$s, AR:$t), + "moveqz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; -def DIVN_S : RRR_Inst<0x00, 0x0A, 0x07, (outs FPR:$r), (ins FPR:$s, FPR:$t), - "divn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; +def MOVF_S : RRR_Inst<0x00, 0x0B, 0x0C, (outs FPR:$r), (ins FPR:$s, BR:$t), + "movf.s\t$r, $s, $t", []>, Requires<[HasBoolean, HasSingleFloat]>; + +def MOVGEZ_S : RRR_Inst<0x00, 0x0B, 0x0B, (outs FPR:$r), (ins FPR:$s, AR:$t), + "movgez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; + +def MOVLTZ_S : RRR_Inst<0x00, 0x0B, 0x0A, (outs FPR:$r), (ins FPR:$s, AR:$t), + "movltz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; + +def MOVNEZ_S : RRR_Inst<0x00, 0x0B, 0x09, (outs FPR:$r), (ins FPR:$s, AR:$t), + "movnez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; + +def MOVT_S : RRR_Inst<0x00, 0x0B, 0x0D, (outs FPR:$r), (ins FPR:$s, BR:$t), + "movt.s\t$r, $s, $t", []>, Requires<[HasBoolean, HasSingleFloat]>; + +// FP multipy-sub +def MSUB_S : RRR_Inst<0x00, 0x0A, 0x05, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), + "msub.s\t$r, $s, $t", + [(set FPR:$r, (Xtensa_msub FPR:$a, FPR:$s, FPR:$t))]>, Requires<[HasSingleFloat]> { + let isCommutable = 0; + let isReMaterializable = 0; + let Constraints = "$r = $a"; +} def NEXP01_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "nexp01.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0B; } +def NEG_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "neg.s\t$r, $s", + [(set FPR:$r, (fneg FPR:$s))]> { + let t = 0x06; +} + +def RECIP0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "recip0.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x08; +} + +def RFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs AR:$r), (ins FPR:$s), + "rfr\t$r, $s", + [(set AR:$r, (bitconvert FPR:$s))]> { + let t = 0x04; +} + +def ROUND_S : RRR_Inst<0x00, 0x0A, 0x08, (outs AR:$r), (ins FPR:$s, uimm4:$imm), + "round.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { + bits<4> imm; + + let t = imm; +} + +def RSQRT0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), + "rsqrt0.s\t$r, $s", []>, Requires<[HasSingleFloat]> { + let t = 0x0A; +} + def SQRT0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "sqrt0.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x09; } +def TRUNC_S : RRR_Inst<0x00, 0x0A, 0x09, (outs AR:$r), (ins FPR:$s, uimm4:$imm), + "trunc.s\t$r, $s, $imm", []> { + bits<4> imm; + + let t = imm; +} + +def : Pat<(i32 (fp_to_sint FPR:$s)), (TRUNC_S FPR:$s, 0)>; + +def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s, uimm4:$imm), + "ufloat.s\t$r, $s, $imm", []> { + bits<4> imm; + + let t = imm; +} + +def : Pat<(f32 (uint_to_fp AR:$s)), (UFLOAT_S AR:$s, 0)>; + +def UTRUNC_S : RRR_Inst<0x00, 0x0A, 0x0e, (outs AR:$r), (ins FPR:$s, uimm4:$imm), + "utrunc.s\t$r, $s, $imm", []> { + bits<4> imm; + + let t = imm; +} + +def : Pat<(i32 (fp_to_uint FPR:$s)), (UTRUNC_S FPR:$s, 0)>; + +def WFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins AR:$s), + "wfr\t$r, $s", + [(set FPR:$r, (bitconvert AR:$s))]> { + let t = 0x05; +} + // FP select operations let usesCustomInserter = 1 in { def SELECT_CC_FP_INT : Pseudo<(outs AR:$dst), (ins FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, i32imm:$cond), @@ -1154,7 +1240,6 @@ let usesCustomInserter = 1 in { "!select_cc_fp_fp $dst, $lhs, $rhs, $t, $f, $cond", [(set FPR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, FPR:$t, FPR:$f, imm:$cond))]>; } - //===----------------------------------------------------------------------===// // Loop Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/Xtensa/xtensa-valid-float.s b/llvm/test/MC/Xtensa/xtensa-valid-float.s new file mode 100644 index 00000000000000..40405e93c58431 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-float.s @@ -0,0 +1,178 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+fp -mattr=+bool -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +.align 4 +LBL0: + +# CHECK-INST: abs.s f2, f3 +# CHECK: encoding: [0x10,0x23,0xfa] + abs.s f2, f3 +# CHECK-INST: add.s f2, f3, f4 +# CHECK: encoding: [0x40,0x23,0x0a] + add.s f2, f3, f4 +# CHECK-INST: addexp.s f2, f3 +# CHECK: encoding: [0xe0,0x23,0xfa] + addexp.s f2, f3 +# CHECK-INST: addexpm.s f2, f3 +# CHECK: encoding: [0xf0,0x23,0xfa] + addexpm.s f2, f3 + +# CHECK-INST: ceil.s a2, f3, 5 +# CHECK: encoding: [0x50,0x23,0xba] + ceil.s a2, f3, 5 +# CHECK-INST: const.s f3, 5 +# CHECK: encoding: [0x30,0x35,0xfa] + const.s f3, 5 + +# CHECK-INST: div0.s f2, f3 +# CHECK: encoding: [0x70,0x23,0xfa] + div0.s f2, f3 +# CHECK-INST: divn.s f2, f3, f4 +# CHECK: encoding: [0x40,0x23,0x7a] + divn.s f2, f3, f4 + +# CHECK-INST: float.s f2, a3, 5 +# CHECK: encoding: [0x50,0x23,0xca] + float.s f2, a3, 5 +# CHECK-INST: floor.s a2, f3, 5 +# CHECK: encoding: [0x50,0x23,0xaa] + floor.s a2, f3, 5 + +# CHECK-INST: lsi f2, a3, 8 +# CHECK: encoding: [0x23,0x03,0x02] + lsi f2, a3, 8 +# CHECK-INST: lsip f2, a3, 8 +# CHECK: encoding: [0x23,0x83,0x02] + lsip f2, a3, 8 +# CHECK-INST: lsx f2, a3, a4 +# CHECK: encoding: [0x40,0x23,0x08] + lsx f2, a3, a4 +# CHECK-INST: lsxp f2, a3, a4 +# CHECK: encoding: [0x40,0x23,0x18] + lsxp f2, a3, a4 + +# CHECK-INST: madd.s f2, f3, f4 +# CHECK: encoding: [0x40,0x23,0x4a] + madd.s f2, f3, f4 +# CHECK-INST: maddn.s f2, f3, f4 +# CHECK: encoding: [0x40,0x23,0x6a] + maddn.s f2, f3, f4 +# CHECK-INST: mkdadj.s f2, f3 +# CHECK: encoding: [0xd0,0x23,0xfa] + mkdadj.s f2, f3 +# CHECK-INST: mksadj.s f2, f3 +# CHECK: encoding: [0xc0,0x23,0xfa] + mksadj.s f2, f3 + +# CHECK-INST: mov.s f2, f3 +# CHECK: encoding: [0x00,0x23,0xfa] + mov.s f2, f3 + +# CHECK-INST: moveqz.s f2, f3, a4 +# CHECK: encoding: [0x40,0x23,0x8b] + moveqz.s f2, f3, a4 +# CHECK-INST: movf.s f2, f3, b0 +# CHECK: encoding: [0x00,0x23,0xcb] + movf.s f2, f3, b0 +# CHECK-INST: movgez.s f2, f3, a4 +# CHECK: encoding: [0x40,0x23,0xbb] + movgez.s f2, f3, a4 +# CHECK-INST: movltz.s f2, f3, a4 +# CHECK: encoding: [0x40,0x23,0xab] + movltz.s f2, f3, a4 +# CHECK-INST: movnez.s f2, f3, a4 +# CHECK: encoding: [0x40,0x23,0x9b] + movnez.s f2, f3, a4 +# CHECK-INST: movt.s f2, f3, b0 +# CHECK: encoding: [0x00,0x23,0xdb] + movt.s f2, f3, b0 + +# CHECK-INST: msub.s f2, f3, f4 +# CHECK: encoding: [0x40,0x23,0x5a] + msub.s f2, f3, f4 +# CHECK-INST: mul.s f2, f3, f4 +# CHECK: encoding: [0x40,0x23,0x2a] + mul.s f2, f3, f4 +# CHECK-INST: neg.s f2, f3 +# CHECK: encoding: [0x60,0x23,0xfa] + neg.s f2, f3 + +# CHECK-INST: nexp01.s f2, f3 +# CHECK: encoding: [0xb0,0x23,0xfa] + nexp01.s f2, f3 + +# CHECK-INST: oeq.s b0, f2, f3 +# CHECK: encoding: [0x30,0x02,0x2b] + oeq.s b0, f2, f3 +# CHECK-INST: ole.s b0, f2, f3 +# CHECK: encoding: [0x30,0x02,0x6b] + ole.s b0, f2, f3 +# CHECK-INST: olt.s b0, f2, f3 +# CHECK: encoding: [0x30,0x02,0x4b] + olt.s b0, f2, f3 + +# CHECK-INST: recip0.s f2, f3 +# CHECK: encoding: [0x80,0x23,0xfa] + recip0.s f2, f3 + +# CHECK-INST: rfr a2, f3 +# CHECK: encoding: [0x40,0x23,0xfa] + rfr a2, f3 + +# CHECK-INST: round.s a2, f3, 5 +# CHECK: encoding: [0x50,0x23,0x8a] + round.s a2, f3, 5 +# CHECK-INST: rsqrt0.s f2, f3 +# CHECK: encoding: [0xa0,0x23,0xfa] + rsqrt0.s f2, f3 +# CHECK-INST: sqrt0.s f2, f3 +# CHECK: encoding: [0x90,0x23,0xfa] + sqrt0.s f2, f3 + +# CHECK-INST: ssi f2, a3, 8 +# CHECK: encoding: [0x23,0x43,0x02] + ssi f2, a3, 8 +# CHECK-INST: ssip f2, a3, 8 +# CHECK: encoding: [0x23,0xc3,0x02] + ssip f2, a3, 8 +# CHECK-INST: ssx f2, a3, a4 +# CHECK: encoding: [0x40,0x23,0x48] + ssx f2, a3, a4 +# CHECK-INST: ssxp f2, a3, a4 +# CHECK: encoding: [0x40,0x23,0x58] + ssxp f2, a3, a4 + +# CHECK-INST: sub.s f2, f3, f4 +# CHECK: encoding: [0x40,0x23,0x1a] + sub.s f2, f3, f4 + +# CHECK-INST: trunc.s a2, f3, 5 +# CHECK: encoding: [0x50,0x23,0x9a] + trunc.s a2, f3, 5 + +# CHECK-INST: ueq.s b0, f2, f3 +# CHECK: encoding: [0x30,0x02,0x3b] + ueq.s b0, f2, f3 + +# CHECK-INST: ufloat.s f2, a3, 5 +# CHECK: encoding: [0x50,0x23,0xda] + ufloat.s f2, a3, 5 + +# CHECK-INST: ule.s b0, f2, f3 +# CHECK: encoding: [0x30,0x02,0x7b] + ule.s b0, f2, f3 +# CHECK-INST: ult.s b0, f2, f3 +# CHECK: encoding: [0x30,0x02,0x5b] + ult.s b0, f2, f3 +# CHECK-INST: un.s b0, f2, f3 +# CHECK: encoding: [0x30,0x02,0x1b] + un.s b0, f2, f3 + +# CHECK-INST: utrunc.s a2, f3, 5 +# CHECK: encoding: [0x50,0x23,0xea] + utrunc.s a2, f3, 5 + +# CHECK-INST: wfr f2, a3 +# CHECK: encoding: [0x50,0x23,0xfa] + wfr f2, a3 + From a17f7bd00c3033f678a3a82f77152fa220954c4c Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:46 +0300 Subject: [PATCH 056/261] [Xtensa] Correct lowering BR_CC with FP operands. Remove register class for boolean operands, because it is only suitable for FP compare operations and may lead to problems in other cases. Disable load width reduction, because for IRAM memory it may cause exceptions. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 106 +++++------------- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 12 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 12 +- llvm/lib/Target/Xtensa/XtensaOperators.td | 9 +- llvm/test/CodeGen/Xtensa/xtensa-fcmp.ll | 18 +++ llvm/test/CodeGen/Xtensa/xtensa-icmp.ll | 17 +++ 6 files changed, 90 insertions(+), 84 deletions(-) create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-fcmp.ll create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-icmp.ll diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 0996d3cb405e8c..4f6bc1e9c7514f 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -342,10 +342,6 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); - - if (Subtarget.hasBoolean()) { - addRegisterClass(MVT::i1, &Xtensa::BRRegClass); - } } bool XtensaTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, @@ -1106,73 +1102,6 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, DL, MVT::Other, RetOps); } -static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, SDLoc dl, - SelectionDAG &DAG, int &br_code) { - // Minor optimization: if LHS is a constant, swap operands, then the - // constant can be folded into comparison. - if (LHS.getOpcode() == ISD::Constant) - std::swap(LHS, RHS); - int cmp_code = 0; - - switch (CC) { - default: - llvm_unreachable("Invalid condition!"); - break; - case ISD::SETUNE: - br_code = XtensaISD::BR_CC_F; - cmp_code = XtensaISD::CMPOEQ; - break; - case ISD::SETUO: - br_code = XtensaISD::BR_CC_T; - cmp_code = XtensaISD::CMPUO; - break; - case ISD::SETO: - br_code = XtensaISD::BR_CC_F; - cmp_code = XtensaISD::CMPUO; - break; - case ISD::SETUEQ: - br_code = XtensaISD::BR_CC_T; - cmp_code = XtensaISD::CMPUEQ; - break; - case ISD::SETULE: - br_code = XtensaISD::BR_CC_T; - cmp_code = XtensaISD::CMPULE; - break; - case ISD::SETULT: - br_code = XtensaISD::BR_CC_T; - cmp_code = XtensaISD::CMPULT; - break; - case ISD::SETEQ: - case ISD::SETOEQ: - br_code = XtensaISD::BR_CC_T; - cmp_code = XtensaISD::CMPOEQ; - break; - case ISD::SETNE: - br_code = XtensaISD::BR_CC_F; - cmp_code = XtensaISD::CMPOEQ; - break; - case ISD::SETLE: - case ISD::SETOLE: - br_code = XtensaISD::BR_CC_T; - cmp_code = XtensaISD::CMPOLE; - break; - case ISD::SETLT: - case ISD::SETOLT: - br_code = XtensaISD::BR_CC_T; - cmp_code = XtensaISD::CMPOLT; - break; - case ISD::SETGE: - br_code = XtensaISD::BR_CC_F; - cmp_code = XtensaISD::CMPOLT; - break; - case ISD::SETGT: - br_code = XtensaISD::BR_CC_F; - cmp_code = XtensaISD::CMPOLE; - break; - } - return DAG.getNode(cmp_code, dl, MVT::i1, LHS, RHS); -} - SDValue XtensaTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast(Op.getOperand(1))->get(); @@ -1182,9 +1111,9 @@ SDValue XtensaTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); if (LHS.getValueType() == MVT::f32) { - int br_code; - SDValue Flag = EmitCMP(LHS, RHS, CC, DL, DAG, br_code); - return DAG.getNode(br_code, DL, Op.getValueType(), Chain, Flag, Dest); + SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32); + return DAG.getNode(XtensaISD::BR_CC_FP, DL, Op.getValueType(), Chain, + TargetCC, LHS, RHS, Dest); } else { llvm_unreachable("invalid BR_CC to lower"); } @@ -1787,8 +1716,9 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(SELECT); OPCODE(SELECT_CC); OPCODE(SELECT_CC_FP); - OPCODE(BR_CC_T); - OPCODE(BR_CC_F); + OPCODE(BR_T); + OPCODE(BR_F); + OPCODE(BR_CC_FP); OPCODE(BR_JT); OPCODE(CMPUO); OPCODE(CMPUEQ); @@ -1965,7 +1895,7 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, int CmpKind = 0; MachineFunction *MF = BB->getParent(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); - const TargetRegisterClass *RC = getRegClassFor(MVT::i1); + const TargetRegisterClass *RC = &Xtensa::BRRegClass; unsigned b = RegInfo.createVirtualRegister(RC); GetFPBranchKind(Cond.getImm(), BrKind, CmpKind); BuildMI(BB, DL, TII.get(CmpKind), b) @@ -3019,6 +2949,28 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( return MBB; } + case Xtensa::BRCC_FP: { + MachineOperand &Cond = MI.getOperand(0); + MachineOperand &LHS = MI.getOperand(1); + MachineOperand &RHS = MI.getOperand(2); + MachineBasicBlock *TargetBB = MI.getOperand(3).getMBB(); + int BrKind = 0; + int CmpKind = 0; + MachineFunction *MF = MBB->getParent(); + MachineRegisterInfo &RegInfo = MF->getRegInfo(); + const TargetRegisterClass *RC = &Xtensa::BRRegClass; + + unsigned RegB = RegInfo.createVirtualRegister(RC); + GetFPBranchKind(Cond.getImm(), BrKind, CmpKind); + BuildMI(*MBB, MI, DL, TII.get(CmpKind), RegB) + .addReg(LHS.getReg()) + .addReg(RHS.getReg()); + BuildMI(*MBB, MI, DL, TII.get(BrKind)).addReg(RegB).addMBB(TargetBB); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::SELECT_CC_FP_FP: case Xtensa::SELECT_CC_FP_INT: case Xtensa::SELECT_CC_INT_FP: diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index a15906654a54aa..f3942e35f305e6 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -25,8 +25,11 @@ namespace XtensaISD { enum { FIRST_NUMBER = ISD::BUILTIN_OP_END, - BR_CC_T, - BR_CC_F, + BR_T, + BR_F, + + //Conditional branch with FP operands + BR_CC_FP, BR_JT, @@ -161,6 +164,11 @@ class XtensaTargetLowering : public TargetLowering { return true; } + bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, + EVT NewVT) const override { + return false; + } + MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 743d1c4a757346..1f937857ba0118 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -941,8 +941,8 @@ def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t), def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t), "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>; -def : Pat<(Xtensa_brcc_t BR:$b, bb:$target), (BT BR:$b, bb:$target)>; -def : Pat<(Xtensa_brcc_f BR:$b, bb:$target), (BF BR:$b, bb:$target)>; +def : Pat<(Xtensa_br_t BR:$b, bb:$target), (BT BR:$b, bb:$target)>; +def : Pat<(Xtensa_br_f BR:$b, bb:$target), (BF BR:$b, bb:$target)>; //===----------------------------------------------------------------------===// // Floating-Point Instructions @@ -1240,6 +1240,14 @@ let usesCustomInserter = 1 in { "!select_cc_fp_fp $dst, $lhs, $rhs, $t, $f, $cond", [(set FPR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, FPR:$t, FPR:$f, imm:$cond))]>; } + +// FP brcc pesudo operation +let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, isBarrier = 1 in { + def BRCC_FP : Pseudo<(outs), (ins i32imm:$cond, FPR:$lhs, FPR:$rhs, brtarget:$target), + "!brcc_fp $cond, $lhs, $rhs, $target", + [(Xtensa_brcc_fp imm:$cond, FPR:$lhs, FPR:$rhs, bb:$target)]>; +} + //===----------------------------------------------------------------------===// // Loop Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index e5f96e44652083..e53691159d425d 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -25,7 +25,8 @@ def SDT_XtensaSelectCC : SDTypeProfile<1, 5, SDTCisVT<5, i32>]>; def SDT_XtensaMOVSP : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>; -def SDT_XtensaBrCC : SDTypeProfile<0, 2, [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]>; +def SDT_XtensaBrBool : SDTypeProfile<0, 2, [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]>; +def SDT_XtensaBrCCFP : SDTypeProfile<0, 4, [SDTCisVT<0, i32>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, SDTCisVT<3, OtherVT>]>; def SDT_XtensaCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>; def SDT_XtensaMADD : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, f32>]>; def SDT_XtensaMOVS : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, f32>]>; @@ -72,9 +73,11 @@ def Xtensa_select_cc_fp: SDNode<"XtensaISD::SELECT_CC_FP", SDT_XtensaSelectCCFP, def Xtensa_movsp: SDNode<"XtensaISD::MOVSP", SDT_XtensaMOVSP, [SDNPInGlue]>; -def Xtensa_brcc_t : SDNode<"XtensaISD::BR_CC_T", SDT_XtensaBrCC, +def Xtensa_br_t : SDNode<"XtensaISD::BR_T", SDT_XtensaBrBool, [SDNPHasChain, SDNPInGlue]>; -def Xtensa_brcc_f : SDNode<"XtensaISD::BR_CC_F", SDT_XtensaBrCC, +def Xtensa_br_f : SDNode<"XtensaISD::BR_F", SDT_XtensaBrBool, + [SDNPHasChain, SDNPInGlue]>; +def Xtensa_brcc_fp : SDNode<"XtensaISD::BR_CC_FP", SDT_XtensaBrCCFP, [SDNPHasChain, SDNPInGlue]>; def Xtensa_cmpoeq : SDNode<"XtensaISD::CMPOEQ", SDT_XtensaCmp, [SDNPOutGlue]>; diff --git a/llvm/test/CodeGen/Xtensa/xtensa-fcmp.ll b/llvm/test/CodeGen/Xtensa/xtensa-fcmp.ll new file mode 100644 index 00000000000000..ffd4977a03c615 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-fcmp.ll @@ -0,0 +1,18 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +define void @test_fcmp(i32 %x.coerce) { +; CHECK-LABEL: @test_fcmp +entry: + %0 = bitcast i32 %x.coerce to float + %cmp = fcmp oeq float %0, 0x7FF0000000000000 + br i1 %cmp, label %if.then, label %if.else +; CHECK: oeq.s b0, f9, f8 +; CHECK: bf b0, .LBB0_2 + +if.then: ; preds = %entry + unreachable + +if.else: ; preds = %entry + unreachable +} + diff --git a/llvm/test/CodeGen/Xtensa/xtensa-icmp.ll b/llvm/test/CodeGen/Xtensa/xtensa-icmp.ll new file mode 100644 index 00000000000000..684ff3b2b60b83 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-icmp.ll @@ -0,0 +1,17 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +define i8 @test_bit(i8 %a) { +; CHECK-LABEL: @test_bit + %b = and i8 %a, 16 + %bool = icmp eq i8 %b, 0 + br i1 %bool, label %true, label %false +; CHECK: movi.n a8, 16 +; CHECK: and a8, a2, a8 +; CHECK: bnez a8, .LBB0_2 + +true: + ret i8 1 + +false: + ret i8 0 +} From 4726f7467caa3ad8fc80983d6dde23860a9b0ebf Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:47 +0300 Subject: [PATCH 057/261] [Xtensa] Use ctors for Xtensa target by default --- llvm/lib/Target/Xtensa/CMakeLists.txt | 1 + .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 7 +++++- .../Target/Xtensa/XtensaTargetObjectFile.cpp | 23 +++++++++++++++++ .../Target/Xtensa/XtensaTargetObjectFile.h | 25 +++++++++++++++++++ 4 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 llvm/lib/Target/Xtensa/XtensaTargetObjectFile.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaTargetObjectFile.h diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index 1a3ff0c5311fe6..2d27fa78a9b817 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -27,6 +27,7 @@ add_llvm_target(XtensaCodeGen XtensaSizeReductionPass.cpp XtensaSubtarget.cpp XtensaTargetMachine.cpp + XtensaTargetObjectFile.cpp LINK_COMPONENTS AsmPrinter diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 7cdf772611b3eb..6f91c09fb49bc3 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -14,6 +14,7 @@ #include "XtensaMachineFunctionInfo.h" #include "XtensaTargetMachine.h" +#include "XtensaTargetObjectFile.h" #include "TargetInfo/XtensaTargetInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -43,6 +44,10 @@ static Reloc::Model getEffectiveRelocModel(bool JIT, return *RM; } +static std::unique_ptr createTLOF() { + return std::make_unique(); +} + XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -53,7 +58,7 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT, : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT, CPU, FS, Options, getEffectiveRelocModel(JIT, RM), getEffectiveCodeModel(CM, CodeModel::Small), OL), - TLOF(std::make_unique()), + TLOF(createTLOF()), Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); } diff --git a/llvm/lib/Target/Xtensa/XtensaTargetObjectFile.cpp b/llvm/lib/Target/Xtensa/XtensaTargetObjectFile.cpp new file mode 100644 index 00000000000000..27da879ea860dc --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaTargetObjectFile.cpp @@ -0,0 +1,23 @@ +//===-- llvm/Target/XtensaTargetObjectFile.cpp - Xtensa Object Info Impl --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "XtensaTargetObjectFile.h" +#include "llvm/MC/MCContext.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +//===----------------------------------------------------------------------===// +// ELF Target +//===----------------------------------------------------------------------===// + +void XtensaElfTargetObjectFile::Initialize(MCContext &Ctx, + const TargetMachine &TM) { + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + InitializeELF(false); +} diff --git a/llvm/lib/Target/Xtensa/XtensaTargetObjectFile.h b/llvm/lib/Target/Xtensa/XtensaTargetObjectFile.h new file mode 100644 index 00000000000000..dae8f890459aa0 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaTargetObjectFile.h @@ -0,0 +1,25 @@ +//===- llvm/Target/XtensaTargetObjectFile.h - Xtensa Object Info -*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSATARGETOBJECTFILE_H +#define LLVM_LIB_TARGET_XTENSA_XTENSATARGETOBJECTFILE_H + +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" + +namespace llvm { + +class XtensaElfTargetObjectFile : public TargetLoweringObjectFileELF { +public: + XtensaElfTargetObjectFile() : TargetLoweringObjectFileELF() {} + + void Initialize(MCContext &Ctx, const TargetMachine &TM) override; +}; + +} // end namespace llvm + +#endif // LLVM_LIB_TARGET_XTENSA_XTENSATARGETOBJECTFILE_H From d2db1ed386761f0a6b8dda5d4bd1dc348d67e37b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:47 +0300 Subject: [PATCH 058/261] Implement Hardware Loop optimization pass --- llvm/lib/Target/Xtensa/CMakeLists.txt | 3 + .../Disassembler/XtensaDisassembler.cpp | 10 + .../Xtensa/MCTargetDesc/XtensaAsmBackend.cpp | 8 +- .../Xtensa/MCTargetDesc/XtensaFixupKinds.h | 1 + .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 15 + .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 1 + .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 21 + llvm/lib/Target/Xtensa/Xtensa.h | 2 + llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 2 + llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp | 388 ++++++++++++++++++ .../lib/Target/Xtensa/XtensaHardwareLoops.cpp | 335 +++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 112 ++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 3 + llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 56 +++ llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 4 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 41 +- llvm/lib/Target/Xtensa/XtensaOperands.td | 9 +- llvm/lib/Target/Xtensa/XtensaOperators.td | 6 + .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 21 + llvm/lib/Target/Xtensa/XtensaTargetMachine.h | 2 + .../Xtensa/XtensaTargetTransformInfo.cpp | 35 ++ .../Target/Xtensa/XtensaTargetTransformInfo.h | 51 +++ llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll | 31 ++ .../CodeGen/Xtensa/hwloop_unsuitable_loop.ll | 38 ++ 24 files changed, 1164 insertions(+), 31 deletions(-) create mode 100644 llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp create mode 100644 llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.h create mode 100644 llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll create mode 100644 llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index 2d27fa78a9b817..6b035e8cb41dfe 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -17,7 +17,9 @@ add_public_tablegen_target(XtensaCommonTableGen) add_llvm_target(XtensaCodeGen XtensaAsmPrinter.cpp XtensaConstantPoolValue.cpp + XtensaFixupHWLoops.cpp XtensaFrameLowering.cpp + XtensaHardwareLoops.cpp XtensaInstrInfo.cpp XtensaISelDAGToDAG.cpp XtensaISelLowering.cpp @@ -28,6 +30,7 @@ add_llvm_target(XtensaCodeGen XtensaSubtarget.cpp XtensaTargetMachine.cpp XtensaTargetObjectFile.cpp + XtensaTargetTransformInfo.cpp LINK_COMPONENTS AsmPrinter diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index c10c31d4f0164c..2835e682ed199a 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -443,6 +443,16 @@ static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeLoopOperand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + + assert(isUInt<8>(Imm) && "Invalid immediate"); + if (!tryAddingSymbolicOperand(Imm + 4 + Address, true, Address, 0, 3, Inst, + Decoder)) + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + static DecodeStatus decodeL32ROperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp index db4484bb57c1ad..d3f799caab100d 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp @@ -70,7 +70,8 @@ XtensaMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_xtensa_l32r_16", 8, 16, MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}}; + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + {"fixup_xtensa_loop_8", 16, 8, MCFixupKindInfo::FKF_IsPCRel}}; if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); @@ -120,6 +121,11 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, if (Value & 0x3) Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned"); return (Value & 0xffffc) >> 2; + case Xtensa::fixup_xtensa_loop_8: + Value -= 4; + if (!isUInt<8>(Value)) + Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + return (Value & 0xff); case Xtensa::fixup_xtensa_l32r_16: unsigned Offset = Fixup.getOffset(); if (Offset & 0x3) diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h index 57b114e709a8a6..f6b1e58adf073b 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h @@ -22,6 +22,7 @@ enum FixupKind { fixup_xtensa_jump_18, fixup_xtensa_call_18, fixup_xtensa_l32r_16, + fixup_xtensa_loop_8, fixup_xtensa_invalid, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index 89343d203e9eba..8d5e56b35b51c7 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -114,6 +114,21 @@ void XtensaInstPrinter::printBranchTarget(const MCInst *MI, int OpNum, llvm_unreachable("Invalid operand"); } +void XtensaInstPrinter::printLoopTarget(const MCInst *MI, int OpNum, + raw_ostream &OS) { + const MCOperand &MC = MI->getOperand(OpNum); + if (MI->getOperand(OpNum).isImm()) { + int64_t Val = MC.getImm() + 4; + OS << ". "; + if (Val > 0) + OS << '+'; + OS << Val; + } else if (MC.isExpr()) + MC.getExpr()->print(OS, &MAI, true); + else + llvm_unreachable("Invalid operand"); +} + void XtensaInstPrinter::printJumpTarget(const MCInst *MI, int OpNum, raw_ostream &OS) { const MCOperand &MC = MI->getOperand(OpNum); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index f6858b383cbf16..62b080c635706f 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -48,6 +48,7 @@ class XtensaInstPrinter : public MCInstPrinter { void printOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printMemOperand(const MCInst *MI, int OpNUm, raw_ostream &O); void printBranchTarget(const MCInst *MI, int OpNum, raw_ostream &O); + void printLoopTarget(const MCInst *MI, int OpNum, raw_ostream &O); void printJumpTarget(const MCInst *MI, int OpNum, raw_ostream &O); void printCallOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printL32RTarget(const MCInst *MI, int OpNum, raw_ostream &O); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 88daa562baedc2..14f9026a1ea4bc 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -67,6 +67,10 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + uint32_t getLoopTargetEncoding(const MCInst &MI, unsigned int OpNum, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + uint32_t getCallEncoding(const MCInst &MI, unsigned int OpNum, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -219,6 +223,23 @@ uint32_t XtensaMCCodeEmitter::getBranchTargetEncoding( } } +uint32_t +XtensaMCCodeEmitter::getLoopTargetEncoding(const MCInst &MI, unsigned int OpNum, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNum); + if (MO.isImm()) + return static_cast(MO.getImm()); + + assert((MO.isExpr()) && "Unexpected operand value!"); + + const MCExpr *Expr = MO.getExpr(); + + Fixups.push_back(MCFixup::create( + 0, Expr, MCFixupKind(Xtensa::fixup_xtensa_loop_8), MI.getLoc())); + return 0; +} + uint32_t XtensaMCCodeEmitter::getCallEncoding(const MCInst &MI, unsigned int OpNum, SmallVectorImpl &Fixups, diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h index 20e2ab7bbb5d06..f4ae6d0b99cb46 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.h +++ b/llvm/lib/Target/Xtensa/Xtensa.h @@ -27,5 +27,7 @@ class FunctionPass; FunctionPass *createXtensaISelDag(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel); FunctionPass *createXtensaSizeReductionPass(); +FunctionPass *createXtensaHardwareLoops(); +FunctionPass *createXtensaFixupHwLoops(); } // namespace llvm #endif /* LLVM_LIB_TARGET_XTENSA_XTENSA_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index be2b943d4ff98a..459ad80257dc32 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -55,6 +55,8 @@ void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) { MCInstBuilder(Xtensa::JX).addReg(MI->getOperand(0).getReg())); return; } + case Xtensa::LOOPEND: + return; } Lower.lower(MI, LoweredMI); EmitToStreamer(*OutStreamer, LoweredMI); diff --git a/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp b/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp new file mode 100644 index 00000000000000..dc712a91380585 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp @@ -0,0 +1,388 @@ +//===---- XtensaFixupHWLoops.cpp - Fixup HW loops -------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "XtensaTargetMachine.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/Pass.h" +#include "llvm/Support/MathExtras.h" + +using namespace llvm; + +namespace llvm { +FunctionPass *createXtensaFixupHwLoops(); +void initializeXtensaFixupHwLoopsPass(PassRegistry &); +} // namespace llvm + +namespace { +class XtensaFixupHwLoops : public MachineFunctionPass { + // BasicBlockInfo - Information about the offset and size of a single + // basic block. + struct BasicBlockInfo { + // Offset - Distance from the beginning of the function to the beginning + // of this basic block. + // + // The offset is always aligned as required by the basic block. + unsigned Offset = 0; + + // Size - Size of the basic block in bytes. If the block contains + // inline assembly, this is a worst case estimate. + // + // The size does not include any alignment padding whether from the + // beginning of the block, or from an aligned jump table at the end. + unsigned Size = 0; + + BasicBlockInfo() = default; + + // Compute the offset immediately following this block. \p MBB is the next + // block. + unsigned postOffset(const MachineBasicBlock &MBB) const { + const unsigned PO = Offset + Size; + const Align Alignment = MBB.getAlignment(); + if (Alignment == 1) + return PO; + + const Align ParentAlign = MBB.getParent()->getAlignment(); + if (Alignment <= ParentAlign) + return PO + offsetToAlignment(PO, Alignment); + + // The alignment of this MBB is larger than the function's alignment, so + // we can't tell whether or not it will insert nops. Assume that it will. + return PO + Alignment.value() + offsetToAlignment(PO, Alignment); + } + }; + + SmallVector BlockInfo; + SmallPtrSet AnalyzedMBBs; + + MachineFunction *MF; + MachineLoopInfo *MLI; + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; + + bool processLoop(MachineLoop *L); + + bool fixupLoopInstrs(MachineLoop *L); + + void scanFunction(); + + uint64_t computeBlockSize(const MachineBasicBlock &MBB) const; + + void adjustBlockOffsets(MachineBasicBlock &Start); + +public: + static char ID; + + XtensaFixupHwLoops() : MachineFunctionPass(ID) { + initializeXtensaFixupHwLoopsPass(*PassRegistry::getPassRegistry()); + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set( + MachineFunctionProperties::Property::NoVRegs); + } + + StringRef getPassName() const override { + return "Xtensa Hardware Loop Fixup"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); + } +}; + +char XtensaFixupHwLoops::ID = 0; +} // namespace + +INITIALIZE_PASS(XtensaFixupHwLoops, "hwloopsfixup", + "Xtensa Hardware Loops Fixup", false, false) + +FunctionPass *llvm::createXtensaFixupHwLoops() { + return new XtensaFixupHwLoops(); +} + +// Returns true if the instruction is a hardware loop instruction. +static bool isHardwareLoop(const MachineInstr &MI) { + return (MI.getOpcode() == Xtensa::LOOPSTART); +} + +bool XtensaFixupHwLoops::runOnMachineFunction(MachineFunction &mf) { + if (skipFunction(mf.getFunction())) + return false; + + MF = &mf; + MLI = &getAnalysis(); + const TargetSubtargetInfo &ST = mf.getSubtarget(); + TII = ST.getInstrInfo(); + TRI = ST.getRegisterInfo(); + + // Renumber all of the machine basic blocks in the function, guaranteeing that + // the numbers agree with the position of the block in the function. + mf.RenumberBlocks(); + + // Do the initial scan of the function, building up information about the + // sizes of each block. + scanFunction(); + + AnalyzedMBBs.clear(); + + bool Changed = false; + + for (auto &L : *MLI) + if (!L->getParentLoop()) { + Changed |= processLoop(L); + } + + return Changed; +} + +// Scan loop and find hardware loop pseudo instructions LOOPSTART and LOOPEND. +// Transform LOOPSTART to Xtensa instructions and remove LOOPEND. +bool XtensaFixupHwLoops::fixupLoopInstrs(MachineLoop *L) { + // const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + MachineBasicBlock &MBB = *(L->getHeader()); + bool Changed = false; + unsigned Num = MBB.getNumber(); + unsigned Offset = BlockInfo[Num].Offset; + MachineBasicBlock *LastBlock = nullptr; + unsigned LHOffset = Offset; + unsigned LastBlockOffset = 0; + + // Loop over all the instructions. + MachineBasicBlock::iterator MII = MBB.begin(); + MachineBasicBlock::iterator MIE = MBB.end(); + MachineInstr *PredI1 = nullptr; + MachineInstr *FirstMI = nullptr; + + for (auto MBI = L->block_begin(), MBIE = L->block_end(); MBI != MBIE; ++MBI) { + if (LastBlockOffset < BlockInfo[(*MBI)->getNumber()].Offset) { + LastBlockOffset = BlockInfo[(*MBI)->getNumber()].Offset; + LastBlock = (*MBI); + } + } + + while (MII != MIE) { + if (MII->isMetaInstruction()) { + ++MII; + continue; + } + + MachineInstr &MI = *MII; + + if (FirstMI == nullptr) + FirstMI = &MI; + + if (isHardwareLoop(*MII)) { + MachineBasicBlock *LoopEnd = nullptr; + + MII->getNextNode(); + + MachineBasicBlock::iterator NextMII = std::next(MII); + + // Check whether loop is empty and remove if true + if (NextMII != MIE) { + if ((*NextMII).getOpcode() == Xtensa::LOOPEND) { + MBB.erase(*NextMII); + MBB.erase(*MII); + MBB.removeSuccessor(&MBB, true); + return true; + } + } + + for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin(), + PE = MBB.pred_end(); + PI != PE; ++PI) { + MachineBasicBlock *PMBB = *PI; + MachineBasicBlock::iterator PIB = PMBB->begin(); + MachineBasicBlock::iterator PII = PMBB->end(); + + do { + --PII; + if (PII->isMetaInstruction()) { + continue; + } + + if ((*PII).getOpcode() == Xtensa::LOOPEND) { + DebugLoc DL = PII->getDebugLoc(); + unsigned OffsetLE = BlockInfo[PMBB->getNumber()].Offset; + + // Check if loop end is placed before loop header + // In such case add special MBB after loop header and create jump + // from loop end to it + if (OffsetLE < LHOffset) { + LoopEnd = MF->CreateMachineBasicBlock(); + MF->insert(++LastBlock->getIterator(), LoopEnd); + LoopEnd->transferSuccessors(PMBB); + LoopEnd->splice(LoopEnd->end(), PMBB, PII, PMBB->end()); + + MachineBasicBlock::iterator LEI = LoopEnd->end(); + --LEI; + + // Expect jump instruction + assert((LEI->getOpcode() == Xtensa::J) && "Broken hardware loop"); + + // Create block and insert it before loop end address as + // target for jump instruction to avoid premature exit from loop + MachineBasicBlock *BlockForJump = MF->CreateMachineBasicBlock(); + MF->insert(LoopEnd->getIterator(), BlockForJump); + BlockForJump->addSuccessor(LoopEnd); + BuildMI(*BlockForJump, BlockForJump->end(), DL, + TII->get(Xtensa::NOP)); + BuildMI(*PMBB, PMBB->end(), DL, TII->get(Xtensa::J)) + .addMBB(BlockForJump); + PMBB->addSuccessor(BlockForJump); + + BuildMI(*LoopEnd, LoopEnd->begin(), DL, TII->get(Xtensa::LOOPEND)) + .addMBB(LoopEnd); + LoopEnd->addSuccessor(LoopEnd); + Changed = true; + break; + } + + if (PII != PIB) { + LoopEnd = MF->CreateMachineBasicBlock(); + MF->insert(++(PMBB->getIterator()), LoopEnd); + LoopEnd->transferSuccessors(PMBB); + LoopEnd->splice(LoopEnd->end(), PMBB, PII, PMBB->end()); + PMBB->addSuccessor(LoopEnd); + + BuildMI(*LoopEnd, LoopEnd->begin(), DL, TII->get(Xtensa::LOOPEND)) + .addMBB(LoopEnd); + LoopEnd->addSuccessor(LoopEnd); + } else { + BuildMI(*PMBB, PII, DL, TII->get(Xtensa::LOOPEND)).addMBB(PMBB); + PMBB->addSuccessor(PMBB); + BuildMI(*PMBB, PII, DL, TII->get(Xtensa::NOP)); + LoopEnd = PMBB; + } + + Changed = true; + break; + } + } while (PII != PIB); + if (Changed) + break; + } + + assert((Changed) && "Broken hardware loop"); + + if (MII != FirstMI) { + MBB.splice(FirstMI->getIterator(), &MBB, MII); + Offset = BlockInfo[Num].Offset; + switch (PredI1->getOpcode()) { + case Xtensa::L32I_N: + if (PredI1->getOperand(0).getReg() == MII->getOperand(0).getReg()) { + MBB.splice(MII, &MBB, PredI1); + Offset += 2; + } + break; + case Xtensa::L32I: + if (PredI1->getOperand(0).getReg() == MII->getOperand(0).getReg()) { + MBB.splice(MII, &MBB, PredI1); + Offset += 3; + } + break; + } + } + + DebugLoc DL = MII->getDebugLoc(); + + // Fixup Loop alignment + switch (Offset & 0x3) { + case 0x0: + BuildMI(MBB, MII, DL, TII->get(Xtensa::NOP)); + BuildMI(MBB, MII, DL, TII->get(Xtensa::NOP)); + break; + case 0x3: + BuildMI(MBB, MII, DL, TII->get(Xtensa::NOP)); + break; + } + + BuildMI(MBB, MII, DL, TII->get(Xtensa::LOOP)) + .addReg(MII->getOperand(0).getReg()) + .addMBB(LoopEnd); + MBB.erase(MII); + + MF->RenumberBlocks(); + scanFunction(); + AnalyzedMBBs.insert(&MBB); + return true; + } else { + Offset += TII->getInstSizeInBytes(MI); + PredI1 = &MI; + ++MII; + } + } + + return Changed; +} + +bool XtensaFixupHwLoops::processLoop(MachineLoop *L) { + bool Changed = false; + + // Process nested loops first. + for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) { + Changed |= processLoop(*I); + } + + if (Changed) + return true; + + return fixupLoopInstrs(L); +} + +// scanFunction - Do the initial scan of the function, building up +// information about each block. +void XtensaFixupHwLoops::scanFunction() { + BlockInfo.clear(); + BlockInfo.resize(MF->getNumBlockIDs()); + + // First thing, compute the size of all basic blocks, and see if the function + // has any inline assembly in it. If so, we have to be conservative about + // alignment assumptions, as we don't know for sure the size of any + // instructions in the inline assembly. + for (MachineBasicBlock &MBB : *MF) + BlockInfo[MBB.getNumber()].Size = computeBlockSize(MBB); + + // Compute block offsets and known bits. + adjustBlockOffsets(*MF->begin()); +} + +// computeBlockSize - Compute the size for MBB. +uint64_t +XtensaFixupHwLoops::computeBlockSize(const MachineBasicBlock &MBB) const { + uint64_t Size = 0; + for (const MachineInstr &MI : MBB) + if (MI.getOpcode() != Xtensa::LOOPEND) + Size += TII->getInstSizeInBytes(MI); + return Size; +} + +void XtensaFixupHwLoops::adjustBlockOffsets(MachineBasicBlock &Start) { + unsigned PrevNum = Start.getNumber(); + for (auto &MBB : make_range(MachineFunction::iterator(Start), MF->end())) { + unsigned Num = MBB.getNumber(); + if (!Num) // block zero is never changed from offset zero. + continue; + // Get the offset and known bits at the end of the layout predecessor. + // Include the alignment of the current block. + BlockInfo[Num].Offset = BlockInfo[PrevNum].postOffset(MBB); + + PrevNum = Num; + } +} + diff --git a/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp b/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp new file mode 100644 index 00000000000000..f31d724ebb8f1b --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp @@ -0,0 +1,335 @@ +//===- XtensaHardwareLoops.cpp - Idenify and generate hardware Loops ------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains implementation of the pass which optimizes loops . +// +//===----------------------------------------------------------------------===// + +#include "XtensaInstrInfo.h" +#include "XtensaSubtarget.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DebugLoc.h" +#include "llvm/InitializePasses.h" +#include "llvm/Pass.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace llvm; + +#define DEBUG_TYPE "xtensa-hwloops" +#define MAX_LOOP_SIZE 256 + +namespace llvm { + +FunctionPass *createXtensaHardwareLoops(); +void initializeXtensaHardwareLoopsPass(PassRegistry &); + +} // end namespace llvm + +namespace { + +struct XtensaHardwareLoops : public MachineFunctionPass { + MachineLoopInfo *MLI; + MachineRegisterInfo *MRI; + MachineDominatorTree *MDT; + const XtensaInstrInfo *TII; + const XtensaSubtarget *STI; + SmallPtrSet VisitedMBBs; + +public: + static char ID; + + XtensaHardwareLoops() : MachineFunctionPass(ID) {} + + bool runOnMachineFunction(MachineFunction &MF) override; + + StringRef getPassName() const override { return "Xtensa Hardware Loops"; } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); + } + +private: + // Return true if the instruction is not valid within a hardware + // loop. + bool isInvalidLoopOperation(const MachineInstr *MI) const; + + // Return true if the loop contains an instruction that inhibits + // using the hardware loop. + bool containsInvalidInstruction(MachineLoop *L) const; + + // Given a loop, check if we can convert it to a hardware loop. + // If so, then perform the conversion and return true. + bool processLoop(MachineLoop *L); + + bool checkLoopSize(MachineLoop *L); + + bool checkLoopEndDisplacement(MachineFunction &MF, MachineBasicBlock *LH, MachineBasicBlock* LE); +}; + +char XtensaHardwareLoops::ID = 0; + +} // end anonymous namespace + +INITIALIZE_PASS(XtensaHardwareLoops, "hwloops", "Xtensa Hardware Loops", false, + false) + +FunctionPass *llvm::createXtensaHardwareLoops() { + return new XtensaHardwareLoops(); +} + +bool XtensaHardwareLoops::runOnMachineFunction(MachineFunction &MF) { + LLVM_DEBUG(dbgs() << "********* Xtensa Hardware Loops *********\n"); + if (skipFunction(MF.getFunction())) + return false; + + bool Changed = false; + + MLI = &getAnalysis(); + MRI = &MF.getRegInfo(); + STI = &MF.getSubtarget(); + TII = STI->getInstrInfo(); + + if (!STI->hasLoop()) + return false; + + VisitedMBBs.clear(); + + for (auto &L : *MLI) + if (!L->getParentLoop()) { + Changed |= processLoop(L); + } + + return Changed; +} + +// Return true if the operation is invalid within hardware loop. +bool XtensaHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI) const { + + // Call is not allowed because the callee may use a hardware loop + if (MI->getDesc().isCall()) + return true; + + if ((MI->getOpcode() == Xtensa::LOOP) || + (MI->getOpcode() == Xtensa::LOOPGTZ) || + (MI->getOpcode() == Xtensa::LOOPNEZ)) + return true; + + if (MI->isInlineAsm()) + return true; + + return false; +} + +// Return true if the loop contains an instruction that inhibits +// the use of the hardware loop instruction. +bool XtensaHardwareLoops::containsInvalidInstruction(MachineLoop *L) const { + LLVM_DEBUG(dbgs() << "\nhw_loop head, " + << printMBBReference(**L->block_begin())); + for (MachineBasicBlock *MBB : L->getBlocks()) { + for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); + MII != E; ++MII) { + const MachineInstr *MI = &*MII; + if (isInvalidLoopOperation(MI)) { + LLVM_DEBUG(dbgs() << "\nCannot convert to hw_loop due to:"; + MI->dump();); + return true; + } + } + } + return false; +} + +// Check if this loop is suitable for converting to a hardware loop +bool XtensaHardwareLoops::processLoop(MachineLoop *L) { + // This is just for sanity. + assert(L->getHeader() && "Loop without a header?"); + + bool Changed = false; + + // Process nested loops first. + for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) { + Changed |= processLoop(*I); + } + + if (Changed) + return true; + + using instr_iterator = MachineBasicBlock::instr_iterator; + MachineInstr *LII = nullptr; // LOOPINIT instruction + MachineInstr *LEI = nullptr; // LOOPEND instruction + MachineBasicBlock *LEMBB = nullptr; + MachineBasicBlock *PH = L->getLoopPreheader(); + MachineBasicBlock *LastMBB = L->getLoopLatch(); + + // Try to find LOOPEND instruction in the loop latch + for (auto MBI = L->block_begin(), MBIE = L->block_end(); MBI != MBIE; ++MBI) { + if (VisitedMBBs.count(*MBI)) + continue; + for (auto MII = (*MBI)->begin(), MIE = (*MBI)->end(); MII != MIE; ++MII) { + MachineInstr *LMI = &*MII; + if (LMI->getOpcode() == Xtensa::LOOPEND) { + LEI = LMI; + LEMBB = *MBI; + } + } + VisitedMBBs.insert(*MBI); + } + + if (LEI != nullptr) { + MachineBasicBlock *LH = L->getHeader(); + MachineBasicBlock::iterator LHI = LH->getFirstNonPHI(); + + if (!PH) { + llvm_unreachable("Hardware loop predecessor not found"); + return false; + } + + MachineBasicBlock *LIMBB = PH; + + // Try to find LOOPINIT instruction in predecessors chain + while ((LII == nullptr) && (LIMBB != nullptr) && + ((L->getParentLoop() == nullptr) || + (L->getParentLoop()->contains(LIMBB)))) { + for (instr_iterator I = LIMBB->instr_begin(), E = LIMBB->instr_end(); + I != E; ++I) { + MachineInstr *MI = &*I; + if (MI->getOpcode() == Xtensa::LOOPINIT) { + LII = MI; + break; + } + } + if (LII == nullptr) + LIMBB = *LIMBB->pred_begin(); + } + + if (LII == nullptr) { + llvm_unreachable("Hardware loop init instruction not found"); + return false; + } + + DebugLoc DL = LII->getDebugLoc(); + + // If loop is too large or have wrong configuration + // then restore branch instruction + // sub a, a, 1 + // bnez a, LH + if (!checkLoopSize(L) || containsInvalidInstruction(L) || + (LEMBB != LastMBB) || (!checkLoopEndDisplacement(*LH->getParent(), LH, LEMBB))) { + const MCInstrDesc &PD = TII->get(TargetOpcode::PHI); + MachineInstr *NewPN = LH->getParent()->CreateMachineInstr(PD, DL); + LH->insert(LH->begin(), NewPN); + Register PR = MRI->createVirtualRegister(&Xtensa::ARRegClass); + NewPN->addOperand(MachineOperand::CreateReg(PR, true)); + + MachineOperand MO = + MachineOperand::CreateReg(LII->getOperand(0).getReg(), false); + NewPN->addOperand(MO); + NewPN->addOperand(MachineOperand::CreateMBB(PH)); + + Register IndR = MRI->createVirtualRegister(&Xtensa::ARRegClass); + MO = MachineOperand::CreateReg(IndR, false); + NewPN->addOperand(MO); + NewPN->addOperand(MachineOperand::CreateMBB(LastMBB)); + + MachineInstrBuilder MIB = + BuildMI(*LEMBB, LEI, LEI->getDebugLoc(), TII->get(Xtensa::ADDI), IndR) + .addReg(PR) + .addImm(-1); + + MIB = BuildMI(*LEMBB, LEI, LEI->getDebugLoc(), TII->get(Xtensa::BNEZ)) + .addReg(IndR) + .addMBB(LEI->getOperand(0).getMBB()); + LEMBB->erase(LEI); + PH->erase(LII); + return false; + } + + //Place LOOPSTART instruction in loop header + BuildMI(*LH, LHI, DL, TII->get(Xtensa::LOOPSTART)) + .addReg(LII->getOperand(0).getReg()) + .addMBB(LastMBB); + PH->erase(LII); + return true; + } + + return false; +} + +bool XtensaHardwareLoops::checkLoopSize(MachineLoop *L) { + uint64_t LoopSize = 0; + + for (auto *MBB : L->getBlocks()) { + uint64_t BlockSize = 0; + for (const MachineInstr &MI : *MBB) { + uint64_t InstSize = TII->getInstSizeInBytes(MI); + if (MI.isPHI()) + InstSize = 3; + BlockSize += InstSize; + } + LoopSize += BlockSize; + } + + if (LoopSize > MAX_LOOP_SIZE) + return false; + + return true; +} + +bool XtensaHardwareLoops::checkLoopEndDisplacement(MachineFunction &MF, + MachineBasicBlock *LH, + MachineBasicBlock *LE) { + bool isLHVisited = false; + + if (LH == LE) + return true; + + for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { + MachineBasicBlock *MBB = &*I; + if (MBB == LH) + isLHVisited = true; + else if (MBB == LE) { + if (isLHVisited) + return true; + else + return false; + } + } + llvm_unreachable("Wrong hardware loop"); +} + diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 4f6bc1e9c7514f..ba18d9469312b0 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -520,29 +520,106 @@ static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); } +static SDValue SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm, + bool &Negate) { + switch (N->getOpcode()) { + default: + break; + case ISD::XOR: { + if (!isa(N.getOperand(1))) + return SDValue(); + if (!cast(N.getOperand(1))->isOne()) + return SDValue(); + Negate = !Negate; + return SearchLoopIntrinsic(N.getOperand(0), CC, Imm, Negate); + } + case ISD::SETCC: { + auto *Const = dyn_cast(N.getOperand(1)); + if (!Const) + return SDValue(); + if (Const->isZero()) + Imm = 0; + else if (Const->isOne()) + Imm = 1; + else + return SDValue(); + CC = cast(N.getOperand(2))->get(); + return SearchLoopIntrinsic(N->getOperand(0), CC, Imm, Negate); + } + case ISD::INTRINSIC_W_CHAIN: { + unsigned IntOp = cast(N.getOperand(1))->getZExtValue(); + if (IntOp != Intrinsic::loop_decrement) + return SDValue(); + return N; + } + } + return SDValue(); +} + static SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const XtensaSubtarget &Subtarget) { - if (DCI.isBeforeLegalizeOps()) { - SDValue Chain = N->getOperand(0); + SDValue Chain = N->getOperand(0); + SDLoc DL(N); + SDValue Cond = N->getOperand(1); + SDValue Dest = N->getOperand(2); + ISD::CondCode CC = ISD::SETEQ; + int Imm = 1; + bool Negate = false; + + SDValue Int = SearchLoopIntrinsic(Cond, CC, Imm, Negate); + if (Int) { + assert((N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BR) && + "expected single br user"); + SDNode *Br = *N->use_begin(); + SDValue OtherTarget = Br->getOperand(1); + + if (Negate) + CC = ISD::getSetCCInverse(CC, /* Integer inverse */ MVT::i32); + + auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) { + return (CC == ISD::SETEQ && Imm == 0) || (CC == ISD::SETNE && Imm == 1) || + (CC == ISD::SETLT && Imm == 1) || (CC == ISD::SETULT && Imm == 1); + }; + + auto IsFalseIfZero = [](ISD::CondCode CC, int Imm) { + return (CC == ISD::SETEQ && Imm == 1) || (CC == ISD::SETNE && Imm == 0) || + (CC == ISD::SETGT && Imm == 0) || + (CC == ISD::SETUGT && Imm == 0) || + (CC == ISD::SETGE && Imm == 1) || (CC == ISD::SETUGE && Imm == 1); + }; + + if (IsTrueIfZero(CC, Imm)) { + SDValue NewBrOps[] = {Br->getOperand(0), Dest}; + SDValue NewBr = DAG.getNode(ISD::BR, SDLoc(Br), MVT::Other, NewBrOps); + DAG.ReplaceAllUsesOfValueWith(SDValue(Br, 0), NewBr); + Dest = OtherTarget; + } else if (!IsFalseIfZero(CC, Imm)) { + llvm_unreachable("unsupported condition"); + } - if (N->getOperand(1).getOpcode() != ISD::SETCC) - return SDValue(); + // We now need to make the intrinsic dead (it cannot be instruction + // selected). + DAG.ReplaceAllUsesOfValueWith(Int.getValue(1), Int.getOperand(0)); + assert(Int.getNode()->hasOneUse() && + "Counter decrement has more than one use"); - SDLoc DL(N); - SDValue SetCC = N->getOperand(1); - SDValue Dest = N->getOperand(2); - ISD::CondCode CC = cast(SetCC->getOperand(2))->get(); - SDValue LHS = SetCC->getOperand(0); - SDValue RHS = SetCC->getOperand(1); + return DAG.getNode(XtensaISD::LOOPEND, DL, MVT::Other, N->getOperand(0), + Dest); + } - if (LHS.getValueType() != MVT::i32) - return SDValue(); + if (Cond.getOpcode() != ISD::SETCC) + return SDValue(); - return DAG.getNode(ISD::BR_CC, DL, MVT::isVoid, Chain, DAG.getCondCode(CC), - LHS, RHS, Dest); - } - return SDValue(); + CC = cast(Cond->getOperand(2))->get(); + SDValue LHS = Cond->getOperand(0); + SDValue RHS = Cond->getOperand(1); + + if (LHS.getValueType() != MVT::i32) + return SDValue(); + + return DAG.getNode(ISD::BR_CC, DL, MVT::isVoid, Chain, DAG.getCondCode(CC), + LHS, RHS, Dest); } SDValue XtensaTargetLowering::PerformDAGCombine(SDNode *N, @@ -1639,7 +1716,7 @@ SDValue XtensaTargetLowering::LowerFunnelShift(SDValue Op, SDValue SetSAR = DAG.getNode(XtensaISD::SSR, DL, MVT::Glue, Shamt); return DAG.getNode(XtensaISD::SRC, DL, VT, Op0, Op1, SetSAR); -} +} SDValue XtensaTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { @@ -1727,6 +1804,7 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(CMPOEQ); OPCODE(CMPOLE); OPCODE(CMPOLT); + OPCODE(LOOPEND); OPCODE(MADD); OPCODE(MSUB); OPCODE(MOVS); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index f3942e35f305e6..53b1d18288d1de 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -49,6 +49,9 @@ enum { CMPOEQ, CMPOLE, CMPOLT, + + LOOPEND, + // FP multipy-add/sub MADD, MSUB, diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 6aea911634204a..ed0cab1581b6c6 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -260,6 +260,10 @@ bool XtensaInstrInfo::reverseBranchCondition( case Xtensa::BT: Cond[0].setImm(Xtensa::BF); return false; + + case Xtensa::LOOPEND: + return true; + default: llvm_unreachable("Invalid branch condition!"); } @@ -273,6 +277,7 @@ XtensaInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { case Xtensa::JX: return nullptr; case Xtensa::J: + case Xtensa::LOOPEND: return MI.getOperand(0).getMBB(); case Xtensa::BEQ: case Xtensa::BNE: @@ -313,6 +318,11 @@ bool XtensaInstrInfo::isBranchOffsetInRange(unsigned BranchOp, return isIntN(18, BrOffset); case Xtensa::JX: return true; + case Xtensa::LOOPEND: + BrOffset += 4; + BrOffset += 3 * 3; // 2*NOP + LOOP instrucions + assert((BrOffset <= 0) && "Wrong hardware loop"); + return true; case Xtensa::BR_JT: return true; case Xtensa::BEQ: @@ -631,6 +641,9 @@ unsigned XtensaInstrInfo::InsertBranchAtInst(MachineBasicBlock &MBB, case Xtensa::BF: MI = BuildMI(MBB, I, DL, get(BR_C)).addReg(Cond[1].getReg()).addMBB(TBB); break; + case Xtensa::LOOPEND: + MI = BuildMI(MBB, I, DL, get(BR_C)).addMBB(TBB); + break; default: llvm_unreachable("Invalid branch type!"); } @@ -640,6 +653,48 @@ unsigned XtensaInstrInfo::InsertBranchAtInst(MachineBasicBlock &MBB, return Count; } +bool XtensaInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, + Register &SrcReg2, int64_t &Mask, + int64_t &Value) const { + unsigned Opc = MI.getOpcode(); + + switch (Opc) { + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + SrcReg = MI.getOperand(0).getReg(); + SrcReg2 = MI.getOperand(1).getReg(); + Value = 0; + Mask = 0; + return true; + + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + SrcReg = MI.getOperand(0).getReg(); + Value = MI.getOperand(1).getImm(); + Mask = ~0; + return true; + + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + SrcReg = MI.getOperand(0).getReg(); + Value = 0; + Mask = ~0; + return true; + } + + return false; +} + bool XtensaInstrInfo::isBranch(const MachineBasicBlock::iterator &MI, SmallVectorImpl &Cond, const MachineOperand *&Target) const { @@ -648,6 +703,7 @@ bool XtensaInstrInfo::isBranch(const MachineBasicBlock::iterator &MI, case Xtensa::J: case Xtensa::JX: case Xtensa::BR_JT: + case Xtensa::LOOPEND: Cond[0].setImm(OpCode); Target = &MI->getOperand(0); return true; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h index d9092c63c37133..f2d50c3abafe40 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h @@ -95,6 +95,10 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { int64_t offset, ArrayRef Cond, DebugLoc DL, int *BytesAdded) const; + bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, + Register &SrcReg2, int64_t &CmpMask, + int64_t &CmpValue) const override; + // Return true if MI is a conditional or unconditional branch. // When returning true, set Cond to the mask of condition-code // values on which the instruction will branch, and set Target diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 1f937857ba0118..9dd5dd63d5dca8 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1252,31 +1252,48 @@ let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, isBarrier = 1 in { // Loop Instructions //===----------------------------------------------------------------------===// -def LOOP : RRI8_Inst<0x06, (outs), (ins AR:$s, mem8:$uimm8), - "loop\t$$s, $uimm8", []>, Requires<[HasLoop]> { - bits<8> uimm8; +def LOOP : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), + "loop\t$s, $target", []>, Requires<[HasLoop]> { + bits<8> target; let r = 0x08; let t = 0x07; - let imm8 = uimm8; + let imm8 = target; } -def LOOPGTZ : RRI8_Inst<0x06, (outs), (ins AR:$s, mem8:$uimm8), - "loopgtz\t$$s, $uimm8", []>, Requires<[HasLoop]> { - bits<8> uimm8; +def LOOPGTZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), + "loopgtz\t$s, $target", []>, Requires<[HasLoop]> { + bits<8> target; let r = 0x0A; let t = 0x07; - let imm8 = uimm8; + let imm8 = target; } -def LOOPNEZ : RRI8_Inst<0x06, (outs), (ins AR:$s, mem8:$uimm8), - "loopnez\t$$s, $uimm8", []>, Requires<[HasLoop]> { - bits<8> uimm8; +def LOOPNEZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), + "loopnez\t$s, $target", []>, Requires<[HasLoop]> { + bits<8> target; let r = 0x09; let t = 0x07; - let imm8 = uimm8; + let imm8 = target; +} + +let isTerminator = 1, isBarrier = 1, hasSideEffects = 1, Size = 3 in { + def LOOPINIT : Pseudo<(outs), (ins AR:$elts), + "!loopinit $elts", [(int_set_loop_iterations AR:$elts)]>; +} + +// LOOPSTART pseudo instruction reserves 9 bytes for LOOP operation and NOP operations for possible alignment. +let isTerminator = 1, isBarrier = 1, hasSideEffects = 1, Size = 9 in { + def LOOPSTART : Pseudo<(outs), (ins AR:$s, brtarget:$target), + "!loopstart $s, $target", []>; +} + +// LOOPEND pseudo instruction reserves 6 bytes for Jump and NOP operations. +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 0, Size = 6 in { + def LOOPEND : Pseudo<(outs), (ins brtarget:$target), + "!loopend $target", [(Xtensa_loopend bb:$target)]>; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 1ea3eeab0e3636..9957bf7bd1f474 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -49,7 +49,7 @@ def Imm64n_4n_AsmOperand: ImmAsmOperand<"Imm64n_4n">; def imm64n_4n: Immediate= -64 && Imm <= -4; }], "Imm64n_4n_AsmOperand"> { let EncoderMethod = "getImm64n_4nOpValue"; let DecoderMethod = "decodeImm64n_4nOperand"; -} +} // imm12 predicate - Immediate in the range [-2048,2047] def Imm12_AsmOperand : ImmAsmOperand<"Imm12">; @@ -238,6 +238,13 @@ def jumptarget : Operand { let ParserMatchClass = XtensaPCRelTargetAsmOperand; } +def ltarget : Operand { + let PrintMethod = "printLoopTarget"; + let EncoderMethod = "getLoopTargetEncoding"; + let DecoderMethod = "decodeLoopOperand"; + let ParserMatchClass = XtensaPCRelTargetAsmOperand; +} + def L32Rtarget: Operand { let PrintMethod = "printL32RTarget"; let EncoderMethod = "getL32RTargetEncoding"; diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index e53691159d425d..a37dcd7c8a9869 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -44,6 +44,8 @@ def SDT_XtensaSSR : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def SDT_XtensaMEMBARRIER : SDTypeProfile<0, 0, []>; def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_XtensaLoopEnd : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; + //===----------------------------------------------------------------------===// // Node definitions //===----------------------------------------------------------------------===// @@ -107,3 +109,7 @@ def Xtensa_mem_barrier: SDNode<"XtensaISD::MEMW", SDT_XtensaMEMBARRIER, def Xtensa_rur: SDNode<"XtensaISD::RUR", SDT_XtensaRUR, [SDNPInGlue]>; + +def Xtensa_loopend: SDNode<"XtensaISD::LOOPEND", SDT_XtensaLoopEnd, + [SDNPHasChain, SDNPInGlue]>; + diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 6f91c09fb49bc3..c3fe74f9ad5fd7 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -15,6 +15,7 @@ #include "XtensaMachineFunctionInfo.h" #include "XtensaTargetMachine.h" #include "XtensaTargetObjectFile.h" +#include "XtensaTargetTransformInfo.h" #include "TargetInfo/XtensaTargetInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -76,6 +77,11 @@ XtensaTargetMachine::getSubtargetImpl(const Function &F) const { return &Subtarget; } +TargetTransformInfo +XtensaTargetMachine::getTargetTransformInfo(const Function &F) const { + return TargetTransformInfo(XtensaTTIImpl(this, F)); +} + MachineFunctionInfo *XtensaTargetMachine::createMachineFunctionInfo( BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const { @@ -94,11 +100,21 @@ class XtensaPassConfig : public TargetPassConfig { } void addIRPasses() override; + bool addPreISel() override; bool addInstSelector() override; + void addPreRegAlloc() override; void addPreEmitPass() override; }; } // end anonymous namespace +bool XtensaPassConfig::addPreISel() { + if (TM->getOptLevel() != CodeGenOptLevel::None) { + addPass(createHardwareLoopsLegacyPass()); + } + + return false; +} + bool XtensaPassConfig::addInstSelector() { addPass(createXtensaISelDag(getXtensaTargetMachine(), getOptLevel())); return false; @@ -106,8 +122,13 @@ bool XtensaPassConfig::addInstSelector() { void XtensaPassConfig::addIRPasses() { addPass(createAtomicExpandPass()); } +void XtensaPassConfig::addPreRegAlloc() { + addPass(createXtensaHardwareLoops()); +} + void XtensaPassConfig::addPreEmitPass() { addPass(createXtensaSizeReductionPass()); + addPass(createXtensaFixupHwLoops()); addPass(&BranchRelaxationPassID); } diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h index eea7c7b5be7c66..8400ff98003356 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h @@ -37,6 +37,8 @@ class XtensaTargetMachine : public LLVMTargetMachine { std::optional CM, CodeGenOptLevel OL, bool JIT); + TargetTransformInfo getTargetTransformInfo(const Function &F) const override; + const XtensaSubtarget *getSubtargetImpl() const { return &Subtarget; } const XtensaSubtarget *getSubtargetImpl(const Function &F) const override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override; diff --git a/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp new file mode 100644 index 00000000000000..7bdec70504772f --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp @@ -0,0 +1,35 @@ +//===- XtensaTargetTransformInfo.cpp - Xtensa specific TTI ----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "XtensaTargetTransformInfo.h" + +using namespace llvm; + +#define DEBUG_TYPE "xtensatti" + +static cl::opt DisableLowOverheadLoops( + "disable-xtensa-hwloops", cl::Hidden, cl::init(false), + cl::desc("Disable the generation of hardware loops")); + +bool XtensaTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, + AssumptionCache &AC, + TargetLibraryInfo *LibInfo, + HardwareLoopInfo &HWLoopInfo) { + if (DisableLowOverheadLoops) + return false; + + if (!ST->hasLoop()) + return false; + + LLVMContext &C = L->getHeader()->getContext(); + HWLoopInfo.CounterInReg = false; + HWLoopInfo.IsNestingLegal = false; + HWLoopInfo.CountType = Type::getInt32Ty(C); + HWLoopInfo.LoopDecrement = ConstantInt::get(HWLoopInfo.CountType, 1); + return true; +} diff --git a/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.h b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.h new file mode 100644 index 00000000000000..81bfbacc0381e7 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.h @@ -0,0 +1,51 @@ +//===- XtensaTargetTransformInfo.h - Xtensa specific TTI --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file defines a TargetTransformInfo::Concept conforming object specific +/// to the Xtensa target machine. It uses the target's detailed information to +/// provide more precise answers to certain TTI queries, while letting the +/// target independent and default TTI implementations handle the rest. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSATARGETTRANSFORMINFO_H +#define LLVM_LIB_TARGET_XTENSA_XTENSATARGETTRANSFORMINFO_H + +#include "XtensaSubtarget.h" +#include "XtensaTargetMachine.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/BasicTTIImpl.h" +#include "llvm/IR/Function.h" + +namespace llvm { + +class XtensaTTIImpl : public BasicTTIImplBase { + using BaseT = BasicTTIImplBase; + using TTI = TargetTransformInfo; + + friend BaseT; + + const XtensaSubtarget *ST; + const XtensaTargetLowering *TLI; + + const XtensaSubtarget *getST() const { return ST; } + const XtensaTargetLowering *getTLI() const { return TLI; } + +public: + explicit XtensaTTIImpl(const XtensaTargetMachine *TM, const Function &F) + : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), + TLI(ST->getTargetLowering()) {} + + bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, + AssumptionCache &AC, TargetLibraryInfo *LibInfo, + HardwareLoopInfo &HWLoopInfo); +}; + +} // end namespace llvm + +#endif // LLVM_LIB_TARGET_XTENSA_XTENSATARGETTRANSFORMINFO_H diff --git a/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll b/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll new file mode 100644 index 00000000000000..1942d51136a21b --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll @@ -0,0 +1,31 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + + +; Function Attrs: norecurse nounwind optsize readnone +define i32 @test_hwloop(i32 %a, i32 %b, i32 %n) local_unnamed_addr #0 { +; CHECK-LABEL: @test_hwloop +entry: + %cmp7 = icmp sgt i32 %n, 0 + br i1 %cmp7, label %for.body, label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.body, %entry + %a.addr.0.lcssa = phi i32 [ %a, %entry ], [ %a.addr.1, %for.body ] + ret i32 %a.addr.0.lcssa + +for.body: ; preds = %entry, %for.body + %i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %a.addr.08 = phi i32 [ %a.addr.1, %for.body ], [ %a, %entry ] + %cmp1 = icmp sgt i32 %a.addr.08, 0 + %mul = mul nsw i32 %a.addr.08, %b + %add = select i1 %cmp1, i32 %mul, i32 0 + %a.addr.1 = add nsw i32 %add, %a.addr.08 + %inc = add nuw nsw i32 %i.09, 1 + %cmp = icmp slt i32 %inc, %n + br i1 %cmp, label %for.body, label %for.cond.cleanup +; CHECK: loop a4, .LBB0_5 +; CHECK: bge a8, a2, .LBB0_2 +; CHECK: mull a9, a2, a3 +; CHECK: add.n a2, a9, a2 +; CHECK: .LBB0_5 +} + diff --git a/llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll b/llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll new file mode 100644 index 00000000000000..bed2d7937468da --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll @@ -0,0 +1,38 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +; Function Attrs: nounwind optsize +define i32 @test_hwloop(i32 %a, i32 %b, i32 %n) local_unnamed_addr #1 { +; CHECK-LABEL: @test_hwloop +entry: + %cmp7 = icmp sgt i32 %n, 0 + br i1 %cmp7, label %for.body, label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.body, %entry + %a.addr.0.lcssa = phi i32 [ %a, %entry ], [ %a.addr.1, %for.body ] + ret i32 %a.addr.0.lcssa + +for.body: ; preds = %entry, %for.body + %i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %a.addr.08 = phi i32 [ %a.addr.1, %for.body ], [ %a, %entry ] + tail call void asm sideeffect "", ""() #2, !srcloc !2 + %cmp1 = icmp sgt i32 %a.addr.08, 0 + %mul = mul nsw i32 %a.addr.08, %b + %add = select i1 %cmp1, i32 %mul, i32 0 + %a.addr.1 = add nsw i32 %add, %a.addr.08 + %inc = add nuw nsw i32 %i.09, 1 + %cmp = icmp slt i32 %inc, %n + br i1 %cmp, label %for.body, label %for.cond.cleanup +; CHECK:.LBB0_2: +; CHECK: mov.n a9, a8 +; CHECK:.LBB0_3: +; CHECK: add.n a2, a9, a2 +; CHECK: #APP +; CHECK: #NO_APP +; CHECK: addi.n a4, a4, -1 +; CHECK: beqz a4, .LBB0_6 +; CHECK:.LBB0_4: +; CHECK: bge a8, a2, .LBB0_2 + +} + +!2 = !{i32 216} From 8d155973933c725837cedbb8691abfc026ee8067 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Mon, 5 Feb 2024 19:33:07 +0300 Subject: [PATCH 059/261] [Xtensa] Change using of Frame Pointer. Do not use Frame Pointer by default. Also improve storing function argument from a7 register to a8 register. Corrected funnel shift test. --- clang/lib/Driver/ToolChains/CommonArgs.cpp | 1 + llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp | 9 ++++++--- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 2 ++ llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h | 4 ++++ 4 files changed, 13 insertions(+), 3 deletions(-) diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index b2cc999810b856..9cb70ed885a3ac 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -114,6 +114,7 @@ static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args, case llvm::Triple::csky: case llvm::Triple::loongarch32: case llvm::Triple::loongarch64: + case llvm::Triple::xtensa: return !clang::driver::tools::areOptimizationsEnabled(Args); default: break; diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index 53b6b7e1b01822..31ae435659747e 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -100,6 +100,7 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF, unsigned FP = RegInfo->getFrameRegister(MF); MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + XtensaFunctionInfo *XtensaFI = MF.getInfo(); // First, compute final stack size. uint64_t StackSize = MFI.getStackSize(); @@ -133,9 +134,11 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF, // Store FP register in A8, because FP may be used to pass function // arguments - BuildMI(MBB, MBBI, dl, TII.get(Xtensa::OR), Xtensa::A8) - .addReg(FP) - .addReg(FP); + if (XtensaFI->isSaveFrameRegister()) { + BuildMI(MBB, MBBI, dl, TII.get(Xtensa::OR), Xtensa::A8) + .addReg(FP) + .addReg(FP); + } // if framepointer enabled, set it to point to the stack pointer. if (hasFP(MF)) { diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index ba18d9469312b0..533427b17dce6e 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -800,6 +800,7 @@ SDValue XtensaTargetLowering::LowerFormalArguments( // so load argument from A8 if (Subtarget.isWinABI() && (VA.getLocReg() == FrameReg)) { Reg = MF.addLiveIn(Xtensa::A8, RC); + XtensaFI->setSaveFrameRegister(); } else { Reg = MF.addLiveIn(VA.getLocReg(), RC); } @@ -894,6 +895,7 @@ SDValue XtensaTargetLowering::LowerFormalArguments( // so load argument from A8 if (ArgRegs[I] == FrameReg) { RegInfo.addLiveIn(Xtensa::A8, Reg); + XtensaFI->setSaveFrameRegister(); } else { RegInfo.addLiveIn(ArgRegs[I], Reg); } diff --git a/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h b/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h index ebc99f912ba0e7..10d11fcb21bf1b 100644 --- a/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h @@ -25,6 +25,7 @@ class XtensaFunctionInfo : public MachineFunctionInfo { unsigned VarArgsFirstGPR; int VarArgsStackOffset; unsigned VarArgsFrameIndex; + bool SaveFrameRegister = false; public: explicit XtensaFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) @@ -39,6 +40,9 @@ class XtensaFunctionInfo : public MachineFunctionInfo { // Get and set the frame index of the first stack vararg. unsigned getVarArgsFrameIndex() const { return VarArgsFrameIndex; } void setVarArgsFrameIndex(unsigned FI) { VarArgsFrameIndex = FI; } + + bool isSaveFrameRegister() const { return SaveFrameRegister; } + void setSaveFrameRegister() { SaveFrameRegister = true; } }; } // namespace llvm From fa0fdab5e9e81407dd85285af45d1274535f88ed Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:48 +0300 Subject: [PATCH 060/261] esp/maint: Adds Github workfows --- .github/workflows/issue_comment.yml | 19 +++++++++++++++++++ .github/workflows/new_issues.yml | 19 +++++++++++++++++++ .github/workflows/new_prs.yml | 24 ++++++++++++++++++++++++ 3 files changed, 62 insertions(+) create mode 100644 .github/workflows/issue_comment.yml create mode 100644 .github/workflows/new_issues.yml create mode 100644 .github/workflows/new_prs.yml diff --git a/.github/workflows/issue_comment.yml b/.github/workflows/issue_comment.yml new file mode 100644 index 00000000000000..b5c80040fc9ff8 --- /dev/null +++ b/.github/workflows/issue_comment.yml @@ -0,0 +1,19 @@ +name: Sync issue comments to JIRA + +# This workflow will be triggered when new issue comment is created (including PR comments) +on: issue_comment + +jobs: + sync_issue_comments_to_jira: + name: Sync Issue Comments to Jira + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@master + - name: Sync issue comments to JIRA + uses: espressif/github-actions/sync_issues_to_jira@master + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + JIRA_PASS: ${{ secrets.JIRA_PASS }} + JIRA_PROJECT: LLVM + JIRA_URL: ${{ secrets.JIRA_URL }} + JIRA_USER: ${{ secrets.JIRA_USER }} diff --git a/.github/workflows/new_issues.yml b/.github/workflows/new_issues.yml new file mode 100644 index 00000000000000..a6602d1c7aa1cb --- /dev/null +++ b/.github/workflows/new_issues.yml @@ -0,0 +1,19 @@ +name: Sync issues to Jira + +# This workflow will be triggered when a new issue is opened +on: issues + +jobs: + sync_issues_to_jira: + name: Sync issues to Jira + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@master + - name: Sync GitHub issues to Jira project + uses: espressif/github-actions/sync_issues_to_jira@master + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + JIRA_PASS: ${{ secrets.JIRA_PASS }} + JIRA_PROJECT: LLVM + JIRA_URL: ${{ secrets.JIRA_URL }} + JIRA_USER: ${{ secrets.JIRA_USER }} diff --git a/.github/workflows/new_prs.yml b/.github/workflows/new_prs.yml new file mode 100644 index 00000000000000..199d58ef87b3f3 --- /dev/null +++ b/.github/workflows/new_prs.yml @@ -0,0 +1,24 @@ +name: Sync remain PRs to Jira + +# This workflow will be triggered every hour, to sync remaining PRs (i.e. PRs with zero comment) to Jira project +# Note that, PRs can also get synced when new PR comment is created +on: + schedule: + - cron: "0 * * * *" + +jobs: + sync_prs_to_jira: + name: Sync PRs to Jira + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@master + - name: Sync PRs to Jira project + uses: espressif/github-actions/sync_issues_to_jira@master + with: + cron_job: true + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + JIRA_PASS: ${{ secrets.JIRA_PASS }} + JIRA_PROJECT: LLVM + JIRA_URL: ${{ secrets.JIRA_URL }} + JIRA_USER: ${{ secrets.JIRA_USER }} From 614d272f78bb8cb9e13be5c685ffc25d0b2dc43d Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Mon, 5 Feb 2024 20:12:07 +0300 Subject: [PATCH 061/261] [Xtensa] Implement esp32 psram cache fixes. --- clang/include/clang/Driver/Options.td | 9 + clang/lib/Driver/ToolChains/Clang.cpp | 32 ++ clang/lib/Driver/ToolChains/Clang.h | 2 + clang/lib/Driver/ToolChains/Xtensa.cpp | 19 + llvm/lib/Target/Xtensa/CMakeLists.txt | 1 + llvm/lib/Target/Xtensa/Xtensa.h | 1 + .../lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp | 353 ++++++++++++++++++ .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 1 + llvm/test/CodeGen/Xtensa/psram_memw.ll | 50 +++ llvm/test/CodeGen/Xtensa/psram_nops.ll | 60 +++ 10 files changed, 528 insertions(+) create mode 100644 llvm/lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp create mode 100644 llvm/test/CodeGen/Xtensa/psram_memw.ll create mode 100644 llvm/test/CodeGen/Xtensa/psram_nops.ll diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 175bedbfb4d01c..40d518eef9474e 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -210,6 +210,8 @@ def m_ve_Features_Group : OptionGroup<"">, Group, DocName<"VE">; def m_loongarch_Features_Group : OptionGroup<"">, Group, DocName<"LoongArch">; +def m_xtensa_Features_Group : OptionGroup<"">, + Group, DocName<"Xtensa">; def m_libc_Group : OptionGroup<"">, Group, Flags<[HelpHidden]>; @@ -6100,6 +6102,13 @@ def mvevpu : Flag<["-"], "mvevpu">, Group, def mno_vevpu : Flag<["-"], "mno-vevpu">, Group; } // let Flags = [TargetSpecific] +// Xtensa feature flags +def malways_memw : Flag<["-"], "malways-memw">, Group; +def mfix_esp32_psram_cache_issue : Flag<["-"], "mfix-esp32-psram-cache-issue">, Group; +def mfix_esp32_psram_cache_strategy_EQ : Joined<["-"], "mfix-esp32-psram-cache-strategy=">, Group, + HelpText<" Psram cache fix strategies : memw, nops">, + Values<"memw, nops">; + // These are legacy user-facing driver-level option spellings. They are always // aliases for options that are spelled using the more common Unix / GNU flag // style of double-dash and equals-joined flags. diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index aa344b3465ab27..e908416fc3bf0f 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -1691,6 +1691,10 @@ void Clang::RenderTargetOptions(const llvm::Triple &EffectiveTriple, case llvm::Triple::ve: AddVETargetArgs(Args, CmdArgs); break; + + case llvm::Triple::xtensa: + AddXtensaTargetArgs(Args, CmdArgs); + break; } } @@ -2334,6 +2338,34 @@ void Clang::AddVETargetArgs(const ArgList &Args, ArgStringList &CmdArgs) const { CmdArgs.push_back("hard"); } +void Clang::AddXtensaTargetArgs(const ArgList &Args, + ArgStringList &CmdArgs) const { + const Driver &D = getToolChain().getDriver(); + + if (Args.getLastArg(options::OPT_malways_memw) != nullptr) { + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back("-malways-memw"); + } + + if (Args.getLastArg(options::OPT_mfix_esp32_psram_cache_issue) != nullptr) { + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back("-mfix-esp32-psram-cache-issue"); + + if (Arg *A = + Args.getLastArg(options::OPT_mfix_esp32_psram_cache_strategy_EQ)) { + StringRef Value = A->getValue(); + if (Value == "memw" || Value == "nops") { + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back( + Args.MakeArgString("-mfix-esp32-psram-cache-strategy=" + Value)); + } else { + D.Diag(diag::err_drv_unsupported_option_argument) + << A->getOption().getName() << Value; + } + } + } +} + void Clang::DumpCompilationDatabase(Compilation &C, StringRef Filename, StringRef Target, const InputInfo &Output, const InputInfo &Input, const ArgList &Args) const { diff --git a/clang/lib/Driver/ToolChains/Clang.h b/clang/lib/Driver/ToolChains/Clang.h index 0f503c4bd1c4fe..9f524c55ba5ae3 100644 --- a/clang/lib/Driver/ToolChains/Clang.h +++ b/clang/lib/Driver/ToolChains/Clang.h @@ -81,6 +81,8 @@ class LLVM_LIBRARY_VISIBILITY Clang : public Tool { llvm::opt::ArgStringList &CmdArgs) const; void AddVETargetArgs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const; + void AddXtensaTargetArgs(const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const; enum RewriteKind { RK_None, RK_Fragile, RK_NonFragile }; diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index 9cd05867f3a017..33b3dfaedf7f07 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -108,18 +108,37 @@ XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, IsIntegratedAsm = false; } + bool IsESP32 = XtensaToolChain::GetTargetCPUVersion(Args).equals("esp32"); Multilibs.push_back(Multilib()); + if (IsESP32) + Multilibs.push_back(MultilibBuilder("esp32-psram", {}, {}) + .flag("-mfix-esp32-psram-cache-issue") + .makeMultilib()); + Multilibs.push_back(MultilibBuilder("no-rtti", {}, {}) .flag("-frtti", /*Disallow=*/true) .flag("-fno-rtti") .makeMultilib()); + if (IsESP32) + Multilibs.push_back(MultilibBuilder("esp32-psram/no-rtti", {}, {}) + .flag("-fno-rtti") + .flag("-frtti", /*Disallow=*/true) + .flag("-mfix-esp32-psram-cache-issue") + .makeMultilib()); + Multilib::flags_list Flags; addMultilibFlag( Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, false), "frtti", Flags); + if (IsESP32) + addMultilibFlag(Args.hasFlag(options::OPT_mfix_esp32_psram_cache_issue, + options::OPT_mfix_esp32_psram_cache_issue, + false), + "mfix-esp32-psram-cache-issue", Flags); + Multilibs.select(Flags, SelectedMultilibs); const std::string Slash = XtensaGCCToolchain.Slash; diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index 6b035e8cb41dfe..fccdde013bbc97 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -17,6 +17,7 @@ add_public_tablegen_target(XtensaCommonTableGen) add_llvm_target(XtensaCodeGen XtensaAsmPrinter.cpp XtensaConstantPoolValue.cpp + XtensaESP32PSRAMFix.cpp XtensaFixupHWLoops.cpp XtensaFrameLowering.cpp XtensaHardwareLoops.cpp diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h index f4ae6d0b99cb46..07b9cb23a5e48d 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.h +++ b/llvm/lib/Target/Xtensa/Xtensa.h @@ -29,5 +29,6 @@ FunctionPass *createXtensaISelDag(XtensaTargetMachine &TM, FunctionPass *createXtensaSizeReductionPass(); FunctionPass *createXtensaHardwareLoops(); FunctionPass *createXtensaFixupHwLoops(); +FunctionPass *createXtensaPSRAMCacheFixPass(); } // namespace llvm #endif /* LLVM_LIB_TARGET_XTENSA_XTENSA_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp b/llvm/lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp new file mode 100644 index 00000000000000..5f22c2ea0e20c5 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp @@ -0,0 +1,353 @@ +//===- XtensaPSRAMFIx.cpp - Fixup PSRAM Cache issues --------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "XtensaInstrInfo.h" +#include "XtensaSubtarget.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen//MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +#define DEBUG_TYPE "xtensa-fix-esp32-psram-cache-pass" + +enum PSRAMFixChoice { + ESP32_PSRAM_FIX_MEMW, + ESP32_PSRAM_FIX_NOPS +}; + +static cl::opt AlwaysMembarrier("malways-memw", cl::init(false), + cl::Hidden); + +static cl::opt FixESP32PSRAMCacheIssue("mfix-esp32-psram-cache-issue", + cl::init(false), cl::Hidden); + +static cl::opt ESP32PSRAMFixStrat( + "mfix-esp32-psram-cache-strategy", cl::init(ESP32_PSRAM_FIX_MEMW), + cl::desc(""), + cl::values(clEnumValN(ESP32_PSRAM_FIX_MEMW, "memw", ""), + clEnumValN(ESP32_PSRAM_FIX_NOPS, "nops", ""))); + +STATISTIC(NumAdded, "Number of instructions added"); + +class createXtensaPSRAMCacheFix : public MachineFunctionPass { +public: + static char ID; + createXtensaPSRAMCacheFix() : MachineFunctionPass(ID) {} + + const XtensaSubtarget *Subtarget; + static const XtensaInstrInfo *XtensaII; + + bool runOnMachineFunction(MachineFunction &MF) override; + + llvm::StringRef getPassName() const override { + return "Xtensa fix PSRAM cache issue in the ESP32 chips"; + } + +private: + bool xtensaPSRAMCacheFixNopReorg(MachineFunction &MF); + /* + Alternative fix to xtensaPSRAMCacheFixNopReorg. Tries to solve the 32-bit + load/store inversion by explicitly inserting a memory barrier instead of nops. + Slower than nops, but faster than just adding memws everywhere. + */ + bool xtensaPSRAMCacheFixMemwReorg(MachineFunction &MF); + // Emits a memw before every load/store instruction. Hard-handed approach to + // get rid of any pipeline/memory issues... + bool xtensaInsertMemwReorg(MachineFunction &MF); +}; + +char createXtensaPSRAMCacheFix::ID = 0; +const XtensaInstrInfo *createXtensaPSRAMCacheFix::XtensaII; + +// Affected piece of pipeline is 5 entries long; the load/store itself fills +// one. +#define LOAD_STORE_OFF 4 + +bool createXtensaPSRAMCacheFix::xtensaPSRAMCacheFixNopReorg( + MachineFunction &MF) { + MachineFunction::iterator I = MF.begin(), E = MF.end(); + MachineInstr *LastHIQIStore = nullptr; + MachineInstr *StoreInsn = nullptr; + int InsnsSinceStore = 0; + bool Modified = false; + + for (; I != E; ++I) { + MachineBasicBlock &MBB = *I; + MachineBasicBlock::instr_iterator MII = MBB.instr_begin(), + MIE = MBB.instr_end(); + MachineBasicBlock::instr_iterator NextMII; + + // Iterate through the instructions in the basic block + for (; MII != MIE; MII = NextMII) { + MachineInstr *MI = &*MII; + unsigned Opcode = MI->getOpcode(); + NextMII = std::next(MII); + + if (MI->isCall() || MI->isBranch() || MI->isReturn()) { + if (LastHIQIStore) { + DebugLoc dl = LastHIQIStore->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(*LastHIQIStore->getParent(), LastHIQIStore, dl, NewMCID); + LastHIQIStore = nullptr; + Modified = true; + NumAdded++; + } + if (!(MI->isBranch() && (MI->getOpcode() != Xtensa::J) && + (MI->getOpcode() != Xtensa::JX))) { + StoreInsn = nullptr; + } + continue; + } + + switch (Opcode) { + case Xtensa::LSI: + case Xtensa::L32I_N: + case Xtensa::L32I: + case Xtensa::L16SI: + case Xtensa::L16UI: + case Xtensa::L8UI: + if (StoreInsn) { + while (InsnsSinceStore++ < LOAD_STORE_OFF) { + DebugLoc dl = MII->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::NOP); + BuildMI(MBB, MII, dl, NewMCID); + Modified = true; + NumAdded++; + } + } + if (LastHIQIStore) { + DebugLoc dl = LastHIQIStore->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(*LastHIQIStore->getParent(), + std::next(LastHIQIStore->getIterator()), dl, NewMCID); + LastHIQIStore = nullptr; + Modified = true; + NumAdded++; + } + break; + case Xtensa::SSI: + case Xtensa::S32I_N: + case Xtensa::S32I: { + LastHIQIStore = nullptr; + InsnsSinceStore = 0; + StoreInsn = MI; + } break; + case Xtensa::S16I: + case Xtensa::S8I: { + LastHIQIStore = MI; + InsnsSinceStore = 0; + StoreInsn = MI; + } break; + default: + InsnsSinceStore++; + break; + } + } + } + return Modified; +} + +bool createXtensaPSRAMCacheFix::xtensaPSRAMCacheFixMemwReorg( + MachineFunction &MF) { + MachineFunction::iterator I = MF.begin(), E = MF.end(); + MachineInstr *LastHIQIStore = nullptr; + MachineInstr *StoreInsn = nullptr; + bool Modified = false; + + for (; I != E; ++I) { + MachineBasicBlock &MBB = *I; + + MachineBasicBlock::instr_iterator MII = MBB.instr_begin(), + MIE = MBB.instr_end(); + MachineBasicBlock::instr_iterator NextMII; + + // Iterate through the instructions in the basic block + for (; MII != MIE; MII = NextMII) { + NextMII = std::next(MII); + MachineInstr *MI = &*MII; + unsigned Opcode = MI->getOpcode(); + + // Don't process bundled instructions or pseudo operations + if (MI->isBundle() || MI->isTransient()) + continue; + + if (MI->isCall() || MI->isBranch() || MI->isReturn()) { + if (StoreInsn) { + if (!(MI->isBranch() && (MI->getOpcode() != Xtensa::J) && + (MI->getOpcode() != Xtensa::JX))) { + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + MachineBasicBlock::instr_iterator BranchI = MI->getIterator(); + while (((*BranchI).isBranch() || (*BranchI).isCall() || + (*BranchI).isReturn()) && + (BranchI != MBB.instr_begin())) + BranchI = std::prev(BranchI); + + if (BranchI != MBB.instr_begin()) + BranchI = std::next(BranchI); + + BuildMI(MBB, BranchI, dl, NewMCID); + Modified = true; + StoreInsn = nullptr; + NumAdded++; + } + } + if (LastHIQIStore) { + DebugLoc dl = LastHIQIStore->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(*LastHIQIStore->getParent(), + std::next(LastHIQIStore->getIterator()), dl, NewMCID); + LastHIQIStore = nullptr; + Modified = true; + NumAdded++; + } + continue; + } + + switch (Opcode) { + case Xtensa::LSI: + case Xtensa::L32I_N: + case Xtensa::L32I: + case Xtensa::L16SI: + case Xtensa::L16UI: + case Xtensa::L8UI: + if (StoreInsn) { + MachineMemOperand *MMO = *MII->memoperands_begin(); + if (!MMO->isVolatile()) { + DebugLoc dl = MII->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(MBB, MII, dl, NewMCID); + Modified = true; + StoreInsn = nullptr; + NumAdded++; + } + } + if (LastHIQIStore) { + DebugLoc dl = LastHIQIStore->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(*LastHIQIStore->getParent(), + std::next(LastHIQIStore->getIterator()), dl, NewMCID); + LastHIQIStore = nullptr; + Modified = true; + NumAdded++; + } + break; + case Xtensa::SSI: + case Xtensa::S32I_N: + case Xtensa::S32I: { + LastHIQIStore = nullptr; + StoreInsn = MI; + } break; + case Xtensa::S16I: + case Xtensa::S8I: { + MachineMemOperand *MMO = *MII->memoperands_begin(); + if (!MMO->isVolatile()) { + LastHIQIStore = MI; + } + StoreInsn = MI; + } break; + } + } + } + return Modified; +} + +bool createXtensaPSRAMCacheFix::xtensaInsertMemwReorg(MachineFunction &MF) { + MachineFunction::iterator I = MF.begin(), E = MF.end(); + bool Modified = false; + bool HadMemw = false; + + for (; I != E; ++I) { + MachineBasicBlock &MBB = *I; + + MachineBasicBlock::instr_iterator MII = MBB.instr_begin(), + MIE = MBB.instr_end(); + MachineBasicBlock::instr_iterator NextMII; + + // Iterate through the instructions in the basic block + for (; MII != MIE; MII = NextMII) { + NextMII = std::next(MII); + MachineInstr *MI = &*MII; + unsigned Opcode = MI->getOpcode(); + + // Don't process bundled instructions or pseudo operations + if (MI->isBundle() || MI->isTransient()) + continue; + + switch (Opcode) { + case Xtensa::LSI: + case Xtensa::L32I_N: + case Xtensa::L32I: + case Xtensa::L16SI: + case Xtensa::L16UI: + case Xtensa::L8UI: { + MachineMemOperand *MMO = *MII->memoperands_begin(); + if (!MMO->isVolatile() && (!HadMemw)) { + DebugLoc dl = MII->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(MBB, MII, dl, NewMCID); + Modified = true; + NumAdded++; + } + HadMemw = false; + } break; + case Xtensa::SSI: + case Xtensa::S32I_N: + case Xtensa::S32I: + case Xtensa::S16I: + case Xtensa::S8I: { + MachineMemOperand *MMO = *MII->memoperands_begin(); + if (!MMO->isVolatile()) { + DebugLoc dl = MII->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(MBB, NextMII, dl, NewMCID); + Modified = true; + NumAdded++; + } + HadMemw = true; + } break; + default: + HadMemw = false; + break; + } + } + } + return Modified; +} + +bool createXtensaPSRAMCacheFix::runOnMachineFunction(MachineFunction &MF) { + + Subtarget = &static_cast(MF.getSubtarget()); + XtensaII = static_cast(Subtarget->getInstrInfo()); + bool Modified = false; + + if (AlwaysMembarrier) + return xtensaInsertMemwReorg(MF); + + if (!FixESP32PSRAMCacheIssue) + return false; + + if (ESP32PSRAMFixStrat == ESP32_PSRAM_FIX_MEMW) { + Modified = xtensaPSRAMCacheFixMemwReorg(MF); + } else if (ESP32PSRAMFixStrat == ESP32_PSRAM_FIX_NOPS) { + Modified = xtensaPSRAMCacheFixNopReorg(MF); + } + + return Modified; +} + +FunctionPass *llvm::createXtensaPSRAMCacheFixPass() { + return new createXtensaPSRAMCacheFix(); +} + diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index c3fe74f9ad5fd7..cf4acabd088530 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -127,6 +127,7 @@ void XtensaPassConfig::addPreRegAlloc() { } void XtensaPassConfig::addPreEmitPass() { + addPass(createXtensaPSRAMCacheFixPass()); addPass(createXtensaSizeReductionPass()); addPass(createXtensaFixupHwLoops()); addPass(&BranchRelaxationPassID); diff --git a/llvm/test/CodeGen/Xtensa/psram_memw.ll b/llvm/test/CodeGen/Xtensa/psram_memw.ll new file mode 100644 index 00000000000000..f10417ec779e6b --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/psram_memw.ll @@ -0,0 +1,50 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw %s -o - | FileCheck %s + +@a = dso_local local_unnamed_addr global i32 0, align 4 +@b = dso_local local_unnamed_addr global i32 0, align 4 + +; Function Attrs: nofree norecurse nounwind +define dso_local void @f(i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce, i32 %a4.coerce, i32 %cond) local_unnamed_addr #0 { +entry: + %coerce.val.ip = inttoptr i32 %a1.coerce to i8* + %coerce.val.ip1 = inttoptr i32 %a2.coerce to i16* + %coerce.val.ip2 = inttoptr i32 %a3.coerce to i32* + %coerce.val.ip3 = inttoptr i32 %a4.coerce to i32* + %0 = load i32, i32* %coerce.val.ip2, align 4 + %conv = trunc i32 %0 to i8 + store i8 %conv, i8* %coerce.val.ip, align 1 + %tobool.not = icmp eq i32 %cond, 0 + br i1 %tobool.not, label %if.end, label %if.then +; CHECK: s8i a8, a2, 0 +; CHECK: memw + +if.then: ; preds = %entry + %1 = load i32, i32* %coerce.val.ip2, align 4 + %conv8 = trunc i32 %1 to i16 + store i16 %conv8, i16* %coerce.val.ip1, align 2 + %2 = load i32, i32* %coerce.val.ip3, align 4 + store i32 %2, i32* %coerce.val.ip2, align 4 + %conv10 = trunc i32 %2 to i8 + store i8 %conv10, i8* %coerce.val.ip, align 1 + br label %return +; CHECK: l32i.n a8, a4, 0 +; CHECK: s16i a8, a3, 0 +; CHECK: memw +; CHECK: memw +; CHECK: l32i.n a8, a5, 0 +; CHECK: s32i.n a8, a4, 0 +; CHECK: s8i a8, a2, 0 +; CHECK: memw + +if.end: ; preds = %entry + %3 = load i32, i32* %coerce.val.ip3, align 4 + %conv9 = trunc i32 %3 to i16 + store i16 %conv9, i16* %coerce.val.ip1, align 2 + br label %return +; CHECK: l32i.n a8, a5, 0 +; CHECK: s16i a8, a3, 0 +; CHECK: memw + +return: ; preds = %if.then, %if.end + ret void +} diff --git a/llvm/test/CodeGen/Xtensa/psram_nops.ll b/llvm/test/CodeGen/Xtensa/psram_nops.ll new file mode 100644 index 00000000000000..ece7d6f6432c4b --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/psram_nops.ll @@ -0,0 +1,60 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=nops %s -o - | FileCheck %s + +@a = dso_local local_unnamed_addr global i32 0, align 4 +@b = dso_local local_unnamed_addr global i32 0, align 4 + +; Function Attrs: nofree norecurse nounwind +define dso_local void @f(i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce, i32 %a4.coerce, i32 %cond) local_unnamed_addr #0 { +entry: + %coerce.val.ip = inttoptr i32 %a1.coerce to i8* + %coerce.val.ip1 = inttoptr i32 %a2.coerce to i16* + %coerce.val.ip2 = inttoptr i32 %a3.coerce to i32* + %coerce.val.ip3 = inttoptr i32 %a4.coerce to i32* + %0 = load i32, i32* %coerce.val.ip2, align 4 + %conv = trunc i32 %0 to i8 + store i8 %conv, i8* %coerce.val.ip, align 1 + %tobool.not = icmp eq i32 %cond, 0 + br i1 %tobool.not, label %if.end, label %if.then +; CHECK: l32i.n a8, a4, 0 +; CHECK: memw +; CHECK: s8i a8, a2, 0 + + +if.then: ; preds = %entry + %1 = load i32, i32* %coerce.val.ip2, align 4 + %conv8 = trunc i32 %1 to i16 + store i16 %conv8, i16* %coerce.val.ip1, align 2 + %2 = load i32, i32* %coerce.val.ip3, align 4 + store i32 %2, i32* %coerce.val.ip2, align 4 + %conv10 = trunc i32 %2 to i8 + store i8 %conv10, i8* %coerce.val.ip, align 1 + br label %return +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: l32i.n a8, a4, 0 +; CHECK: s16i a8, a3, 0 +; CHECK: memw +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: l32i.n a8, a5, 0 +; CHECK: s32i.n a8, a4, 0 +; CHECK: memw +; CHECK: s8i a8, a2, 0 + +if.end: ; preds = %entry + %3 = load i32, i32* %coerce.val.ip3, align 4 + %conv9 = trunc i32 %3 to i16 + store i16 %conv9, i16* %coerce.val.ip1, align 2 + br label %return +; CHECK: l32i.n a8, a5, 0 +; CHECK: memw +; CHECK: s16i a8, a3, 0 + + +return: ; preds = %if.then, %if.end + ret void +} From 058d859fb64c1e013654a8cff20d687e2eb6b24e Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:49 +0300 Subject: [PATCH 062/261] Fix Hardware Loop optimization --- .../lib/Target/Xtensa/XtensaHardwareLoops.cpp | 133 ++++++++++++------ llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 1 - 2 files changed, 93 insertions(+), 41 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp b/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp index f31d724ebb8f1b..a1a2432ded4c1d 100644 --- a/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp +++ b/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp @@ -194,8 +194,10 @@ bool XtensaHardwareLoops::processLoop(MachineLoop *L) { MachineInstr *LII = nullptr; // LOOPINIT instruction MachineInstr *LEI = nullptr; // LOOPEND instruction MachineBasicBlock *LEMBB = nullptr; - MachineBasicBlock *PH = L->getLoopPreheader(); + MachineBasicBlock *LH = L->getHeader(); MachineBasicBlock *LastMBB = L->getLoopLatch(); + std::vector LoopInitInsts; + std::map LoopInitMap; // Try to find LOOPEND instruction in the loop latch for (auto MBI = L->block_begin(), MBIE = L->block_end(); MBI != MBIE; ++MBI) { @@ -207,40 +209,56 @@ bool XtensaHardwareLoops::processLoop(MachineLoop *L) { LEI = LMI; LEMBB = *MBI; } + // Collect LOOPINIT instructions inside the loop + if (LMI->getOpcode() == Xtensa::LOOPINIT) { + LoopInitInsts.push_back(LMI); + MachineBasicBlock *SB = LMI->getParent(); + while (!SB->isSuccessor(LH)) { + for (auto SBI : SB->successors()) { + if (!L->contains(SBI)) + continue; + SB = SBI; + break; + } + if (!L->contains(SB)) + llvm_unreachable("Wrong hardware loop"); + } + LoopInitMap[SB] = LMI; + } } VisitedMBBs.insert(*MBI); } if (LEI != nullptr) { - MachineBasicBlock *LH = L->getHeader(); MachineBasicBlock::iterator LHI = LH->getFirstNonPHI(); - - if (!PH) { - llvm_unreachable("Hardware loop predecessor not found"); - return false; - } - - MachineBasicBlock *LIMBB = PH; - - // Try to find LOOPINIT instruction in predecessors chain - while ((LII == nullptr) && (LIMBB != nullptr) && - ((L->getParentLoop() == nullptr) || - (L->getParentLoop()->contains(LIMBB)))) { - for (instr_iterator I = LIMBB->instr_begin(), E = LIMBB->instr_end(); - I != E; ++I) { - MachineInstr *MI = &*I; - if (MI->getOpcode() == Xtensa::LOOPINIT) { - LII = MI; - break; + MachineBasicBlock *LIMBB = nullptr; + + // Collect LOOPINIT instructions in predecessors from outter loop + for (auto PBI : LH->predecessors()) { + if (L->contains(PBI)) + continue; + LIMBB = PBI; + LII = nullptr; + // Try to find LOOPINIT instructions in predecessor + while ((LII == nullptr) && (LIMBB != nullptr) && + ((L->getParentLoop() == nullptr) || + (L->getParentLoop()->contains(LIMBB)))) { + for (instr_iterator I = LIMBB->instr_begin(), E = LIMBB->instr_end(); + I != E; ++I) { + MachineInstr *MI = &*I; + if (MI->getOpcode() == Xtensa::LOOPINIT) { + LII = MI; + break; + } } + if (LII == nullptr) + LIMBB = *LIMBB->pred_begin(); } - if (LII == nullptr) - LIMBB = *LIMBB->pred_begin(); - } - - if (LII == nullptr) { - llvm_unreachable("Hardware loop init instruction not found"); - return false; + if (LII == nullptr) { + llvm_unreachable("Hardware loop init instruction not found"); + return false; + } + LoopInitMap[PBI] = LII; } DebugLoc DL = LII->getDebugLoc(); @@ -250,22 +268,30 @@ bool XtensaHardwareLoops::processLoop(MachineLoop *L) { // sub a, a, 1 // bnez a, LH if (!checkLoopSize(L) || containsInvalidInstruction(L) || - (LEMBB != LastMBB) || (!checkLoopEndDisplacement(*LH->getParent(), LH, LEMBB))) { + (LEMBB != LastMBB) || + (!checkLoopEndDisplacement(*LH->getParent(), LH, LEMBB))) { const MCInstrDesc &PD = TII->get(TargetOpcode::PHI); MachineInstr *NewPN = LH->getParent()->CreateMachineInstr(PD, DL); LH->insert(LH->begin(), NewPN); Register PR = MRI->createVirtualRegister(&Xtensa::ARRegClass); NewPN->addOperand(MachineOperand::CreateReg(PR, true)); - MachineOperand MO = - MachineOperand::CreateReg(LII->getOperand(0).getReg(), false); - NewPN->addOperand(MO); - NewPN->addOperand(MachineOperand::CreateMBB(PH)); - Register IndR = MRI->createVirtualRegister(&Xtensa::ARRegClass); - MO = MachineOperand::CreateReg(IndR, false); - NewPN->addOperand(MO); - NewPN->addOperand(MachineOperand::CreateMBB(LastMBB)); + + for (auto PB : LH->predecessors()) { + + if (LoopInitMap.find(PB) != LoopInitMap.end()) { + MachineOperand MO = MachineOperand::CreateReg( + LoopInitMap[PB]->getOperand(0).getReg(), false); + NewPN->addOperand(MO); + NewPN->addOperand(MachineOperand::CreateMBB(PB)); + LoopInitMap[PB]->getParent()->erase(LoopInitMap[PB]); + } else { + MachineOperand MO = MachineOperand::CreateReg(IndR, false); + NewPN->addOperand(MO); + NewPN->addOperand(MachineOperand::CreateMBB(PB)); + } + } MachineInstrBuilder MIB = BuildMI(*LEMBB, LEI, LEI->getDebugLoc(), TII->get(Xtensa::ADDI), IndR) @@ -276,15 +302,42 @@ bool XtensaHardwareLoops::processLoop(MachineLoop *L) { .addReg(IndR) .addMBB(LEI->getOperand(0).getMBB()); LEMBB->erase(LEI); - PH->erase(LII); return false; } - //Place LOOPSTART instruction in loop header + // If several LOOPINIT instructions are dicovered then create PHI + // function + if (LoopInitMap.size() > 1) { + const MCInstrDesc &PD = TII->get(TargetOpcode::PHI); + MachineInstr *NewPN = LH->getParent()->CreateMachineInstr(PD, DL); + LH->insert(LH->begin(), NewPN); + Register PR = MRI->createVirtualRegister(&Xtensa::ARRegClass); + NewPN->addOperand(MachineOperand::CreateReg(PR, true)); + + for (auto PB : LH->predecessors()) { + + if (LoopInitMap.find(PB) != LoopInitMap.end()) { + MachineOperand MO = MachineOperand::CreateReg( + LoopInitMap[PB]->getOperand(0).getReg(), false); + NewPN->addOperand(MO); + NewPN->addOperand(MachineOperand::CreateMBB(PB)); + LoopInitMap[PB]->getParent()->erase(LoopInitMap[PB]); + } else { + MachineOperand MO = MachineOperand::CreateReg(PR, false); + NewPN->addOperand(MO); + NewPN->addOperand(MachineOperand::CreateMBB(PB)); + } + } + LII = NewPN; + } + BuildMI(*LH, LHI, DL, TII->get(Xtensa::LOOPSTART)) .addReg(LII->getOperand(0).getReg()) - .addMBB(LastMBB); - PH->erase(LII); + .addMBB(LEMBB); + + if (LII->getOpcode() == Xtensa::LOOPINIT) + LII->getParent()->erase(LII); + return true; } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index ed0cab1581b6c6..81979f522c827d 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -320,7 +320,6 @@ bool XtensaInstrInfo::isBranchOffsetInRange(unsigned BranchOp, return true; case Xtensa::LOOPEND: BrOffset += 4; - BrOffset += 3 * 3; // 2*NOP + LOOP instrucions assert((BrOffset <= 0) && "Wrong hardware loop"); return true; case Xtensa::BR_JT: From 0ec32f0bd21e981ca215dc6e0c304d5c5882e3d2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:49 +0300 Subject: [PATCH 063/261] Remove unnecessary MOVSP in epilogue. --- llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index 31ae435659747e..aabdc73b2f6ec1 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -247,8 +247,13 @@ void XtensaFrameLowering::emitEpilogue(MachineFunction &MF, for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) --I; if (STI.isWinABI()) { - // Insert instruction "movsp $sp, $fp" at this location. - BuildMI(MBB, I, dl, TII.get(Xtensa::MOVSP), SP).addReg(FP); + // In most architectures, we need to explicitly restore the stack pointer + // before returning. + // + // For Xtensa Windowed Register option, it is not needed to explicitly + // restore the stack pointer. Reason being is that on function return, + // the window of the caller (including the old stack pointer) gets + // restored anyways. } else { BuildMI(MBB, I, dl, TII.get(Xtensa::OR), SP).addReg(FP).addReg(FP); } From e0ce3d51f81ef5c2ad520e265d05017224b56a58 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:50 +0300 Subject: [PATCH 064/261] [Xtensa] Support 'f' Inline Assembly Constraint This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. This patch adds support in both the clang frontend, and LLVM itself. --- clang/lib/Basic/Targets/Xtensa.h | 1 + clang/test/CodeGen/xtensa-inline-asm.c | 13 +++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 13 ++++++++++- .../CodeGen/Xtensa/inline-asm-constraints.ll | 23 +++++++++++++++++++ .../test/CodeGen/Xtensa/inline-asm-invalid.ll | 8 +++++++ 5 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 clang/test/CodeGen/xtensa-inline-asm.c create mode 100644 llvm/test/CodeGen/Xtensa/inline-asm-constraints.ll create mode 100644 llvm/test/CodeGen/Xtensa/inline-asm-invalid.ll diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index a9bf0f8cc8f58d..dfe3080482ce20 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -81,6 +81,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { default: return false; case 'a': + case 'f': Info.setAllowsRegister(); return true; } diff --git a/clang/test/CodeGen/xtensa-inline-asm.c b/clang/test/CodeGen/xtensa-inline-asm.c new file mode 100644 index 00000000000000..2ebf175a5a050f --- /dev/null +++ b/clang/test/CodeGen/xtensa-inline-asm.c @@ -0,0 +1,13 @@ +// RUN: %clang_cc1 -triple xtensa -O1 -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +// Test Xtensa specific inline assembly constraints. + +float f; +void test_f() { +// CHECK-LABEL: define dso_local void @test_f() local_unnamed_addr #0 { +// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, ptr @f +// CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]]) + asm volatile ("" :: "f"(f)); +} + diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 533427b17dce6e..dc85a727804cd8 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -398,6 +398,7 @@ XtensaTargetLowering::getConstraintType(StringRef Constraint) const { switch (Constraint[0]) { case 'a': case 'd': + case 'f': case 'r': return C_RegisterClass; @@ -418,6 +419,8 @@ XtensaTargetLowering::getSingleConstraintMatchWeight( if (CallOperandVal == NULL) return CW_Default; + Type *type = CallOperandVal->getType(); + // Look at the constraint type. switch (*constraint) { default: @@ -427,9 +430,14 @@ XtensaTargetLowering::getSingleConstraintMatchWeight( case 'a': case 'd': case 'r': - if (CallOperandVal->getType()->isIntegerTy()) + if (type->isIntegerTy()) + weight = CW_Register; + break; + case 'f': + if (type->isFloatingPointTy()) weight = CW_Register; break; + } return weight; } @@ -446,6 +454,9 @@ XtensaTargetLowering::getRegForInlineAsmConstraint( case 'd': // Data register (equivalent to 'r') case 'r': // General-purpose register return std::make_pair(0U, &Xtensa::ARRegClass); + case 'f': // Floating-point register + if (Subtarget.hasSingleFloat()) + return std::make_pair(0U, &Xtensa::FPRRegClass); } } return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); diff --git a/llvm/test/CodeGen/Xtensa/inline-asm-constraints.ll b/llvm/test/CodeGen/Xtensa/inline-asm-constraints.ll new file mode 100644 index 00000000000000..7dbb0f07debda7 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/inline-asm-constraints.ll @@ -0,0 +1,23 @@ +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=Xtensa %s + + +@gf = external global float + +define float @constraint_f_float(float %a) nounwind { +; Xtensa-LABEL: constraint_f_float: +; Xtensa: # %bb.0: +; Xtensa-NEXT: entry a1, 32 +; Xtensa-NEXT: wfr f8, a2 +; Xtensa-NEXT: l32r a8, .LCPI0_0 +; Xtensa-NEXT: lsi f9, a8, 0 +; Xtensa-NEXT: #APP +; Xtensa-NEXT: add.s f8, f8, f9 +; Xtensa-NEXT: #NO_APP +; Xtensa-NEXT: rfr a2, f8 +; Xtensa-NEXT: retw + %1 = load float, float* @gf + %2 = tail call float asm "add.s $0, $1, $2", "=f,f,f"(float %a, float %1) + ret float %2 +} + diff --git a/llvm/test/CodeGen/Xtensa/inline-asm-invalid.ll b/llvm/test/CodeGen/Xtensa/inline-asm-invalid.ll new file mode 100644 index 00000000000000..260429d9334468 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/inline-asm-invalid.ll @@ -0,0 +1,8 @@ +; RUN: not llc -mtriple=xtensa -mcpu=generic < %s 2>&1 | FileCheck %s + +define void @constraint_f() nounwind { +; CHECK: error: couldn't allocate input reg for constraint 'f' + tail call void asm "add.s f0, f1, $0", "f"(float 0.0) + ret void +} + From f6f7c4cc6bbcfd46051664a425e08a98c62aa539 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:50 +0300 Subject: [PATCH 065/261] [Xtensa] Correction of the PSRAM fix pass --- .../lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp | 58 +++++++++++-------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp b/llvm/lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp index 5f22c2ea0e20c5..0c4433ed00122a 100644 --- a/llvm/lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp +++ b/llvm/lib/Target/Xtensa/XtensaESP32PSRAMFix.cpp @@ -223,14 +223,16 @@ bool createXtensaPSRAMCacheFix::xtensaPSRAMCacheFixMemwReorg( case Xtensa::L16UI: case Xtensa::L8UI: if (StoreInsn) { - MachineMemOperand *MMO = *MII->memoperands_begin(); - if (!MMO->isVolatile()) { - DebugLoc dl = MII->getDebugLoc(); - const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); - BuildMI(MBB, MII, dl, NewMCID); - Modified = true; - StoreInsn = nullptr; - NumAdded++; + if (!MII->memoperands_empty()) { + MachineMemOperand *MMO = *MII->memoperands_begin(); + if (!MMO->isVolatile()) { + DebugLoc dl = MII->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(MBB, MII, dl, NewMCID); + Modified = true; + StoreInsn = nullptr; + NumAdded++; + } } } if (LastHIQIStore) { @@ -251,9 +253,11 @@ bool createXtensaPSRAMCacheFix::xtensaPSRAMCacheFixMemwReorg( } break; case Xtensa::S16I: case Xtensa::S8I: { - MachineMemOperand *MMO = *MII->memoperands_begin(); - if (!MMO->isVolatile()) { - LastHIQIStore = MI; + if (!MII->memoperands_empty()) { + MachineMemOperand *MMO = *MII->memoperands_begin(); + if (!MMO->isVolatile()) { + LastHIQIStore = MI; + } } StoreInsn = MI; } break; @@ -292,13 +296,15 @@ bool createXtensaPSRAMCacheFix::xtensaInsertMemwReorg(MachineFunction &MF) { case Xtensa::L16SI: case Xtensa::L16UI: case Xtensa::L8UI: { - MachineMemOperand *MMO = *MII->memoperands_begin(); - if (!MMO->isVolatile() && (!HadMemw)) { - DebugLoc dl = MII->getDebugLoc(); - const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); - BuildMI(MBB, MII, dl, NewMCID); - Modified = true; - NumAdded++; + if (!MII->memoperands_empty()) { + MachineMemOperand *MMO = *MII->memoperands_begin(); + if (!MMO->isVolatile() && (!HadMemw)) { + DebugLoc dl = MII->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(MBB, MII, dl, NewMCID); + Modified = true; + NumAdded++; + } } HadMemw = false; } break; @@ -307,13 +313,15 @@ bool createXtensaPSRAMCacheFix::xtensaInsertMemwReorg(MachineFunction &MF) { case Xtensa::S32I: case Xtensa::S16I: case Xtensa::S8I: { - MachineMemOperand *MMO = *MII->memoperands_begin(); - if (!MMO->isVolatile()) { - DebugLoc dl = MII->getDebugLoc(); - const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); - BuildMI(MBB, NextMII, dl, NewMCID); - Modified = true; - NumAdded++; + if (!MII->memoperands_empty()) { + MachineMemOperand *MMO = *MII->memoperands_begin(); + if (!MMO->isVolatile()) { + DebugLoc dl = MII->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::MEMW); + BuildMI(MBB, NextMII, dl, NewMCID); + Modified = true; + NumAdded++; + } } HadMemw = true; } break; From 11029d5eca5b8211c462d1255b91336afec9b814 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:51 +0300 Subject: [PATCH 066/261] [Xtensa] Correction of the hardware loop instrinsics detection. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index dc85a727804cd8..91d85201c3670b 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -280,6 +280,9 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setTargetDAGCombine(ISD::FADD); setTargetDAGCombine(ISD::FSUB); + } + + if (Subtarget.hasSingleFloat() || Subtarget.hasLoop()) { setTargetDAGCombine(ISD::BRCOND); } From 1a6e1b64c35acab9e19ee971750bc2d94e0f8773 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:51 +0300 Subject: [PATCH 067/261] [Xtensa] Correction of the ESP32-S2 target. The ESP32-S2 chip includes Xtensa ISA extension which helps to work with GPIO, so we add instructions description and test. Add MEMCTL feature to ESP32-S2 target. Implement Xtensa illegal instructions with tests. --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 5 ++ .../Disassembler/XtensaDisassembler.cpp | 8 +++ .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 11 ++++ .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 1 + .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 17 ++++++ llvm/lib/Target/Xtensa/Xtensa.td | 9 ++- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 55 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaOperands.td | 7 +++ llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 ++ llvm/test/MC/Xtensa/Core/processor-control.s | 4 ++ llvm/test/MC/Xtensa/xtensa-esp32s2-valid.s | 21 +++++++ llvm/test/MC/Xtensa/xtensa-valid-density.s | 9 +++ 13 files changed, 151 insertions(+), 2 deletions(-) create mode 100644 llvm/test/MC/Xtensa/xtensa-esp32s2-valid.s create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-density.s diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 5025a58e45aa83..97c1df987e1025 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -350,6 +350,8 @@ struct XtensaOperand : public MCParsedAsmOperand { bool isseimm7_22() const { return isImm(7, 22); } + bool isSelect_256() const { return isImm(0, 255); } + /// getStartLoc - Gets location of the first token of this operand SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Gets location of the last token of this operand @@ -621,6 +623,9 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_Invalidseimm7_22: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [7, 22]"); + case Match_InvalidSelect_256: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 255]"); } report_fatal_error("Unknown match type detected!"); diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 2835e682ed199a..11e71fe8b0922b 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -569,6 +569,14 @@ static DecodeStatus decodeSeimm7_22Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeSelect_256Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + static int64_t TableB4const[16] = {-1, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256}; static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm, diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index 8d5e56b35b51c7..0960c73dba9375 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -439,3 +439,14 @@ void XtensaInstPrinter::printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, } else printOperand(MI, OpNum, O); } + +void XtensaInstPrinter::printSelect_256_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 255) && + "Invalid argument, value must be in range [0,255]"); + O << Value; + } else + printOperand(MI, OpNum, O); +} diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index 62b080c635706f..b103fb5dc9e014 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -73,6 +73,7 @@ class XtensaInstPrinter : public MCInstPrinter { void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printSelect_256_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 14f9026a1ea4bc..73039c2a44480c 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -142,6 +142,11 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { uint32_t getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + + uint32_t getSelect_256OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + }; } // namespace @@ -593,4 +598,16 @@ XtensaMCCodeEmitter::getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo, return res; } +uint32_t +XtensaMCCodeEmitter::getSelect_256OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint32_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 255)) && "Unexpected operand value!"); + + return Res; +} + #include "XtensaGenMCCodeEmitter.inc" diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index b17442717c21ee..e5d5e4eb1e0b5c 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -153,6 +153,11 @@ def FeatureMiscSR : SubtargetFeature<"miscsr", "HasMiscSR", "true", def HasMiscSR : Predicate<"Subtarget->hasMiscSR()">, AssemblerPredicate<(all_of FeatureMiscSR)>; +def FeatureESP32S2Ops : SubtargetFeature<"esp32s2", "HasESP32S2Ops", "true", + "Support Xtensa esp32-s2 ISA extension">; +def HasESP32S2Ops : Predicate<"Subtarget->hasESP32S2Ops()">, + AssemblerPredicate<(all_of FeatureESP32S2Ops)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// @@ -170,8 +175,8 @@ def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul32, FeatureExtended FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>; def : Proc<"esp32-s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, FeatureDiv32, - FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, - FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR]>; + FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, + FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureESP32S2Ops]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 9dd5dd63d5dca8..f901b2d5cf5d53 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1454,6 +1454,27 @@ def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s), let r = 0x6; } +//===----------------------------------------------------------------------===// +// Illegal instructions +//===----------------------------------------------------------------------===// + +let isBarrier = 1, isTerminator = 1 in { + def ILL : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins), + "ill", []> { + let m = 0x0; + let n = 0x0; + let r = 0; + let s = 0; + } + + def ILL_N : RRRN_Inst<0x0C, (outs), (ins), + "ill.n", []>, Requires<[HasDensity]> { + let r = 0xf; + let s = 0x0; + let t = 0x6; + } +} + //===----------------------------------------------------------------------===// // Atomic patterns //===----------------------------------------------------------------------===// @@ -1588,6 +1609,40 @@ let usesCustomInserter = 1, Predicates = [HasS32C1I] in { [(set AR:$dst, (atomic_load_umax_32 AR:$ptr, AR:$arg))]>; } +//===----------------------------------------------------------------------===// +// Xtensa ESP32S2 Instructions +//===----------------------------------------------------------------------===// +let Predicates = [HasESP32S2Ops] in { + def WR_MASK_GPIO_OUT : RRR_Inst<0x0, 0x06, 0x0, (outs), (ins AR:$s, AR:$t), + "wr_mask_gpio_out\t$s, $t", []> { + let r = 0x2; + } + + def SET_BIT_GPIO_OUT : RRR_Inst<0x0, 0x06, 0x0, (outs), (ins select_256:$imm), + "set_bit_gpio_out\t$imm", []> { + bits<8> imm; + + let r = 0x1; + let s = imm{7-4}; + let t = imm{3-0}; + } + + def CLR_BIT_GPIO_OUT : RRR_Inst<0x0, 0x06, 0x0, (outs), (ins select_256:$imm), + "clr_bit_gpio_out\t$imm", []> { + bits<8> imm; + + let r = 0x0; + let s = imm{7-4}; + let t = imm{3-0}; + } + + def GET_GPIO_IN : RRR_Inst<0x0, 0x06, 0x0, (outs AR:$t), (ins), + "get_gpio_in\t$t", []> { + let r = 0x3; + let s = 0x0; + } +} + //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 9957bf7bd1f474..620aeee0005183 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -175,6 +175,13 @@ def seimm7_22: Immediate= 7 && Imm <= 22; }], "Seimm7_22_As let DecoderMethod = "decodeSeimm7_22Operand"; } +// select_256 predicate - Immediate in the range [0,255] +def Select_256_AsmOperand: ImmAsmOperand<"Select_256">; +def select_256: Immediate= 0 && Imm <= 255; }], "Select_256_AsmOperand"> { + let EncoderMethod = "getSelect_256OpValue"; + let DecoderMethod = "decodeSelect_256Operand"; +} + //===----------------------------------------------------------------------===// // Memory address operands //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 106884d8a0311f..2b90365eb870c6 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -59,6 +59,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasPRID = false; HasRegionProtection = false; HasMiscSR = false; + HasESP32S2Ops = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index 8eb3281706cfe0..24be0de4bf2ac2 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -119,6 +119,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa Miscellaneous Special Reigsiters option bool HasMiscSR; + // Enable Xtensa esp32-s2 ISA extension + bool HasESP32S2Ops; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -190,6 +193,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasMiscSR() const { return HasMiscSR; } + bool hasESP32S2Ops() const { return HasESP32S2Ops; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; diff --git a/llvm/test/MC/Xtensa/Core/processor-control.s b/llvm/test/MC/Xtensa/Core/processor-control.s index 1e7bac57892769..ebbc577db77226 100644 --- a/llvm/test/MC/Xtensa/Core/processor-control.s +++ b/llvm/test/MC/Xtensa/Core/processor-control.s @@ -15,6 +15,10 @@ dsync # CHECK: encoding: [0x20,0x20,0x00] esync +# CHECK-INST: ill +# CHECK: encoding: [0x00,0x00,0x00] +ill + # Instruction format RRR # CHECK-INST: isync # CHECK: encoding: [0x00,0x20,0x00] diff --git a/llvm/test/MC/Xtensa/xtensa-esp32s2-valid.s b/llvm/test/MC/Xtensa/xtensa-esp32s2-valid.s new file mode 100644 index 00000000000000..9c998e919c81e5 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-esp32s2-valid.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+esp32s2 -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +.align 4 +LBL0: + +# CHECK-INST: clr_bit_gpio_out 52 +# CHECK: encoding: [0x40,0x03,0x06] +clr_bit_gpio_out 52 + +# CHECK-INST: get_gpio_in a2 +# CHECK: encoding: [0x20,0x30,0x06] +get_gpio_in a2 + +# CHECK-INST: set_bit_gpio_out 18 +# CHECK: encoding: [0x20,0x11,0x06] +set_bit_gpio_out 18 + +# CHECK-INST: wr_mask_gpio_out a3, a2 +# CHECK: encoding: [0x20,0x23,0x06] +wr_mask_gpio_out a3, a2 diff --git a/llvm/test/MC/Xtensa/xtensa-valid-density.s b/llvm/test/MC/Xtensa/xtensa-valid-density.s new file mode 100644 index 00000000000000..fc5457ce82ddc6 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-density.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+density -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +.align 4 +LBL0: + +# CHECK-INST: ill.n +# CHECK: encoding: [0x6c,0xf0] +ill.n From c7f67c09fa02a6b5ff7c80ad8f1eee332141cbad Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:52 +0300 Subject: [PATCH 068/261] [Xtensa] Implement ESP32-S3 target. Implement support of the ESP32-S3 chip in clang and llvm. The ESP32-S3 chip includes Xtensa ISA extension which helps to work with GPIO, so we add instructions description and test. --- clang/lib/Basic/Targets/Xtensa.h | 1 + clang/lib/Driver/ToolChains/Xtensa.cpp | 2 ++ .../Xtensa/AsmParser/XtensaAsmParser.cpp | 8 ++++- llvm/lib/Target/Xtensa/Xtensa.td | 11 ++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 34 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 +++ llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s | 21 ++++++++++++ 8 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index dfe3080482ce20..2bf3f742d17656 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -97,6 +97,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { .Case("esp32", true) .Case("esp8266", true) .Case("esp32-s2", true) + .Case("esp32-s3", true) .Case("generic", true) .Default(false); } diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index 33b3dfaedf7f07..50c3f1563d1e7c 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -46,6 +46,8 @@ XtensaGCCToolchainDetector::XtensaGCCToolchainDetector( ToolchainName = "xtensa-esp32-elf"; else if (CPUName.equals("esp32-s2")) ToolchainName = "xtensa-esp32s2-elf"; + else if (CPUName.equals("esp32-s3")) + ToolchainName = "xtensa-esp32s3-elf"; else if (CPUName.equals("esp8266")) ToolchainName = "xtensa-lx106-elf"; diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 97c1df987e1025..4267393005ce00 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -935,6 +935,7 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { unsigned NumMiscSR = 0; bool IsESP32 = false; bool IsESP32_S2 = false; + bool IsESP32_S3 = false; bool Res = true; // Assume that CPU is esp32 by default @@ -948,6 +949,11 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { NumTimers = 3; NumMiscSR = 4; IsESP32_S2 = true; + } else if (CPU == "esp32-s3") { + NumIntLevels = 6; + NumTimers = 3; + NumMiscSR = 4; + IsESP32_S3 = true; } else if (CPU == "esp8266") { NumIntLevels = 2; NumTimers = 1; @@ -1071,7 +1077,7 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { Res = hasTHREADPTR(); break; case Xtensa::GPIO_OUT: - Res = IsESP32_S2; + Res = IsESP32_S2 || IsESP32_S3; break; case Xtensa::EXPSTATE: Res = IsESP32; diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index e5d5e4eb1e0b5c..dfcf95b9a61587 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -158,6 +158,11 @@ def FeatureESP32S2Ops : SubtargetFeature<"esp32s2", "HasESP32S2Ops", "tru def HasESP32S2Ops : Predicate<"Subtarget->hasESP32S2Ops()">, AssemblerPredicate<(all_of FeatureESP32S2Ops)>; +def FeatureESP32S3Ops : SubtargetFeature<"esp32s3", "HasESP32S3Ops", "true", + "Support Xtensa esp32-s3 ISA extension">; +def HasESP32S3Ops : Predicate<"Subtarget->hasESP32S3Ops()">, + AssemblerPredicate<(all_of FeatureESP32S3Ops)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// @@ -178,6 +183,12 @@ def : Proc<"esp32-s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureESP32S2Ops]>; +def : Proc<"esp32-s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, + FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, + FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, + FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, + FeatureESP32S3Ops]>; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index f901b2d5cf5d53..331868f7abbe99 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1643,6 +1643,40 @@ let Predicates = [HasESP32S2Ops] in { } } +//===----------------------------------------------------------------------===// +// Xtensa ESP32S3 Instructions +//===----------------------------------------------------------------------===// +let Predicates = [HasESP32S3Ops] in { + def EE_WR_MASK_GPIO_OUT : RRR_Inst<0x04, 0x02, 0x07, (outs), (ins AR:$t, AR:$s), + "ee.wr_mask_gpio_out\t$t, $s", []> { + let r = 0x4; + } + + def EE_SET_BIT_GPIO_OUT : RRR_Inst<0x04, 0x05, 0x07, (outs), (ins select_256:$imm), + "ee.set_bit_gpio_out\t$imm", []> { + bits<8> imm; + + let r = 0x4; + let s = imm{7-4}; + let t = imm{3-0}; + } + + def EE_CLR_BIT_GPIO_OUT : RRR_Inst<0x04, 0x06, 0x07, (outs), (ins select_256:$imm), + "ee.clr_bit_gpio_out\t$imm", []> { + bits<8> imm; + + let r = 0x4; + let s = imm{7-4}; + let t = imm{3-0}; + } + + def EE_GET_GPIO_IN : RRR_Inst<0x04, 0x05, 0x06, (outs AR:$t), (ins), + "ee.get_gpio_in\t$t", []> { + let r = 0x0; + let s = 0x8; + } +} + //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 2b90365eb870c6..c9b8e0bd0e8c28 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -60,6 +60,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasRegionProtection = false; HasMiscSR = false; HasESP32S2Ops = false; + HasESP32S3Ops = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index 24be0de4bf2ac2..ee173686c2a206 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -122,6 +122,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa esp32-s2 ISA extension bool HasESP32S2Ops; + // Enable Xtensa esp32-s3 ISA extension + bool HasESP32S3Ops; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -195,6 +198,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasESP32S2Ops() const { return HasESP32S2Ops; } + bool hasESP32S3Ops() const { return HasESP32S3Ops; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; diff --git a/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s b/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s new file mode 100644 index 00000000000000..50037ea38df156 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+esp32s3 -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +.align 4 +LBL0: + +# CHECK-INST: ee.clr_bit_gpio_out 52 +# CHECK: encoding: [0x44,0x43,0x76] +ee.clr_bit_gpio_out 52 + +# CHECK-INST: ee.get_gpio_in a2 +# CHECK: encoding: [0x24,0x08,0x65] +ee.get_gpio_in a2 + +# CHECK-INST: ee.set_bit_gpio_out 18 +# CHECK: encoding: [0x24,0x41,0x75] +ee.set_bit_gpio_out 18 + +# CHECK-INST: ee.wr_mask_gpio_out a3, a2 +# CHECK: encoding: [0x34,0x42,0x72] +ee.wr_mask_gpio_out a3, a2 From d96035c9e3d6d162bac6c02fbb971c00391e3e51 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:52 +0300 Subject: [PATCH 069/261] [Xtensa] Define register type for CC Implement getRegisterTypeForCallingConv() method in XtensaTargetLowering --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 10 ++++++++++ llvm/lib/Target/Xtensa/XtensaISelLowering.h | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 91d85201c3670b..46a00b5428ccfd 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -347,6 +347,16 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, computeRegisterProperties(STI.getRegisterInfo()); } +/// Return the register type for a given MVT +MVT XtensaTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, + CallingConv::ID CC, + EVT VT) const { + if (VT.isFloatingPoint()) + return MVT::i32; + + return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); +} + bool XtensaTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const { if (!VT.isSimple()) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 53b1d18288d1de..57d99cbe9703ba 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -102,6 +102,10 @@ class XtensaTargetLowering : public TargetLowering { return LHSTy.getSizeInBits() <= 32 ? MVT::i32 : MVT::i64; } + /// Return the register type for a given MVT + MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, + EVT VT) const override; + EVT getSetCCResultType(const DataLayout &, LLVMContext &, EVT VT) const override { if (!VT.isVector()) From e465cdbb910c9381fbf6f5dfab603e871a98be63 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:52 +0300 Subject: [PATCH 070/261] [Xtensa] Correcting FP instructions and intrinsics. Correcting FP instruction descriptions. Implement lowering of the fma, powf and other FP intrinsics. Add test for base FP intrinsics. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 62 ++- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 30 +- llvm/test/CodeGen/Xtensa/float-intrinsics.ll | 363 ++++++++++++++++++ 3 files changed, 422 insertions(+), 33 deletions(-) create mode 100644 llvm/test/CodeGen/Xtensa/float-intrinsics.ll diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 46a00b5428ccfd..1ce10184ed3dcd 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -217,56 +217,76 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, for (unsigned I = MVT::FIRST_FP_VALUETYPE; I <= MVT::LAST_FP_VALUETYPE; ++I) { MVT VT = MVT::SimpleValueType(I); if (isTypeLegal(VT)) { - // We can use FI for FRINT. - // setOperationAction(ISD::FRINT, VT, Legal); if (VT.getSizeInBits() == 32 && Subtarget.hasSingleFloat()) { + setOperationAction(ISD::FABS, VT, Legal); setOperationAction(ISD::FADD, VT, Legal); - setOperationAction(ISD::FSUB, VT, Legal); + setOperationAction(ISD::FMA, VT, Legal); setOperationAction(ISD::FMUL, VT, Legal); - setOperationAction(ISD::FDIV, VT, Expand); + setOperationAction(ISD::FNEG, VT, Legal); + setOperationAction(ISD::FSUB, VT, Legal); } else { + setOperationAction(ISD::FABS, VT, Expand); setOperationAction(ISD::FADD, VT, Expand); - setOperationAction(ISD::FSUB, VT, Expand); + setOperationAction(ISD::FMA, VT, Expand); setOperationAction(ISD::FMUL, VT, Expand); - setOperationAction(ISD::FDIV, VT, Expand); + setOperationAction(ISD::FNEG, VT, Expand); + setOperationAction(ISD::FSUB, VT, Expand); } - // TODO: once implemented in InstrInfo uncomment - setOperationAction(ISD::FSQRT, VT, Expand); - // No special instructions for these. - setOperationAction(ISD::FSIN, VT, Expand); + setOperationAction(ISD::FCBRT, VT, Expand); + setOperationAction(ISD::FCEIL, VT, Expand); + setOperationAction(ISD::FCOPYSIGN, VT, Expand); setOperationAction(ISD::FCOS, VT, Expand); + setOperationAction(ISD::FDIV, VT, Expand); + setOperationAction(ISD::FEXP, VT, Expand); + setOperationAction(ISD::FEXP2, VT, Expand); + setOperationAction(ISD::FFLOOR, VT, Expand); + setOperationAction(ISD::FLOG, VT, Expand); + setOperationAction(ISD::FLOG2, VT, Expand); + setOperationAction(ISD::FLOG10, VT, Expand); + setOperationAction(ISD::FMAXIMUM, VT, Expand); + setOperationAction(ISD::FMINIMUM, VT, Expand); + setOperationAction(ISD::FMAXNUM, VT, Expand); + setOperationAction(ISD::FMINNUM, VT, Expand); + setOperationAction(ISD::FNEARBYINT, VT, Expand); + setOperationAction(ISD::FPOW, VT, Expand); + setOperationAction(ISD::FPOWI, VT, Expand); setOperationAction(ISD::FREM, VT, Expand); - setOperationAction(ISD::FABS, VT, Expand); + setOperationAction(ISD::FRINT, VT, Expand); + setOperationAction(ISD::FROUND, VT, Expand); + setOperationAction(ISD::FSIN, VT, Expand); + setOperationAction(ISD::FSINCOS, VT, Expand); + setOperationAction(ISD::FSQRT, VT, Expand); + setOperationAction(ISD::FTRUNC, VT, Expand); + setOperationAction(ISD::LLRINT, VT, Expand); + setOperationAction(ISD::LLROUND, VT, Expand); + setOperationAction(ISD::LRINT, VT, Expand); + setOperationAction(ISD::LROUND, VT, Expand); } } - // Handle floating-point types. if (Subtarget.hasSingleFloat()) { - setOperationAction(ISD::FMA, MVT::f32, Legal); setOperationAction(ISD::BITCAST, MVT::i32, Legal); setOperationAction(ISD::BITCAST, MVT::f32, Legal); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); } else { - setOperationAction(ISD::FMA, MVT::f32, Expand); - setOperationAction(ISD::SETCC, MVT::f32, Expand); setOperationAction(ISD::BITCAST, MVT::i32, Expand); setOperationAction(ISD::BITCAST, MVT::f32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); - setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand); - setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); - setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand); } - setOperationAction(ISD::FMA, MVT::f64, Expand); + + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); + setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand); + setOperationAction(ISD::SETCC, MVT::f64, Expand); setOperationAction(ISD::BITCAST, MVT::i64, Expand); setOperationAction(ISD::BITCAST, MVT::f64, Expand); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 331868f7abbe99..2adff84ac4551d 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1044,10 +1044,12 @@ def UN_S : FCompare<0x01, 0x0b, "un.s", Xtensa_cmpuo, 1>; def ABS_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "abs.s\t$r, $s", - [(set FPR:$r, (fabs FPR:$s))]> { + [(set FPR:$r, (fabs FPR:$s))]>, Requires<[HasSingleFloat]> { let t = 0x01; } +def : Pat<(fabs FPR:$s), (ABS_S $s)>; + def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "addexp.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0E; @@ -1082,7 +1084,7 @@ def DIVN_S : RRR_Inst<0x00, 0x0A, 0x07, (outs FPR:$r), (ins FPR:$s, FPR:$t), "divn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; def FLOAT_S : RRR_Inst<0x00, 0x0A, 0x0c, (outs FPR:$r), (ins AR:$s, uimm4:$imm), - "float.s\t$r, $s, $imm", []> { + "float.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { bits<4> imm; let t = imm; @@ -1112,6 +1114,10 @@ def MADD_S : RRR_Inst<0x00, 0x0A, 0x04, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR: let Constraints = "$r = $a"; } +// fmadd: r1 * r2 + r3 +def : Pat<(fma FPR:$r1, FPR:$r2, FPR:$r3), + (MADD_S $r3, $r1, $r2)>; + def MKDADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "mkdadj.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0D; @@ -1163,7 +1169,7 @@ def NEXP01_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), def NEG_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "neg.s\t$r, $s", - [(set FPR:$r, (fneg FPR:$s))]> { + [(set FPR:$r, (fneg FPR:$s))]>, Requires<[HasSingleFloat]> { let t = 0x06; } @@ -1174,7 +1180,7 @@ def RECIP0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), def RFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs AR:$r), (ins FPR:$s), "rfr\t$r, $s", - [(set AR:$r, (bitconvert FPR:$s))]> { + [(set AR:$r, (bitconvert FPR:$s))]>, Requires<[HasSingleFloat]> { let t = 0x04; } @@ -1196,16 +1202,16 @@ def SQRT0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), } def TRUNC_S : RRR_Inst<0x00, 0x0A, 0x09, (outs AR:$r), (ins FPR:$s, uimm4:$imm), - "trunc.s\t$r, $s, $imm", []> { + "trunc.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { bits<4> imm; let t = imm; } -def : Pat<(i32 (fp_to_sint FPR:$s)), (TRUNC_S FPR:$s, 0)>; +def : Pat<(i32 (any_fp_to_sint FPR:$s)), (TRUNC_S FPR:$s, 0)>; def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s, uimm4:$imm), - "ufloat.s\t$r, $s, $imm", []> { + "ufloat.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { bits<4> imm; let t = imm; @@ -1214,22 +1220,22 @@ def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s, uimm4:$imm) def : Pat<(f32 (uint_to_fp AR:$s)), (UFLOAT_S AR:$s, 0)>; def UTRUNC_S : RRR_Inst<0x00, 0x0A, 0x0e, (outs AR:$r), (ins FPR:$s, uimm4:$imm), - "utrunc.s\t$r, $s, $imm", []> { + "utrunc.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { bits<4> imm; let t = imm; } -def : Pat<(i32 (fp_to_uint FPR:$s)), (UTRUNC_S FPR:$s, 0)>; +def : Pat<(i32 (any_fp_to_uint FPR:$s)), (UTRUNC_S FPR:$s, 0)>; def WFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins AR:$s), "wfr\t$r, $s", - [(set FPR:$r, (bitconvert AR:$s))]> { + [(set FPR:$r, (bitconvert AR:$s))]>, Requires<[HasSingleFloat]> { let t = 0x05; } // FP select operations -let usesCustomInserter = 1 in { +let usesCustomInserter = 1, Predicates = [HasSingleFloat] in { def SELECT_CC_FP_INT : Pseudo<(outs AR:$dst), (ins FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, i32imm:$cond), "!select_cc_fp_int $dst, $lhs, $rhs, $t, $f, $cond", [(set AR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, imm:$cond))]>; @@ -1242,7 +1248,7 @@ let usesCustomInserter = 1 in { } // FP brcc pesudo operation -let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, isBarrier = 1 in { +let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, isBarrier = 1, Predicates = [HasSingleFloat] in { def BRCC_FP : Pseudo<(outs), (ins i32imm:$cond, FPR:$lhs, FPR:$rhs, brtarget:$target), "!brcc_fp $cond, $lhs, $rhs, $target", [(Xtensa_brcc_fp imm:$cond, FPR:$lhs, FPR:$rhs, bb:$target)]>; diff --git a/llvm/test/CodeGen/Xtensa/float-intrinsics.ll b/llvm/test/CodeGen/Xtensa/float-intrinsics.ll new file mode 100644 index 00000000000000..256a1dee2abf8d --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/float-intrinsics.ll @@ -0,0 +1,363 @@ +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=XTENSA %s + +declare float @llvm.sqrt.f32(float) + +define float @sqrt_f32(float %a) nounwind { +; XTENSA: .literal .LCPI0_0, sqrtf +; XTENSA-LABEL: sqrt_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI0_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n +; + %1 = call float @llvm.sqrt.f32(float %a) + ret float %1 +} + +declare float @llvm.powi.f32(float, i32) + +define float @powi_f32(float %a, i32 %b) nounwind { +; XTENSA: .literal .LCPI1_0, __powisf2 +; XTENSA-LABEL: powi_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI1_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: mov.n a11, a3 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.powi.f32(float %a, i32 %b) + ret float %1 +} + +declare float @llvm.sin.f32(float) + +define float @sin_f32(float %a) nounwind { +; XTENSA: .literal .LCPI2_0, sinf +; XTENSA-LABEL: sin_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI2_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.sin.f32(float %a) + ret float %1 +} + +declare float @llvm.cos.f32(float) + +define float @cos_f32(float %a) nounwind { +; XTENSA: .literal .LCPI3_0, cosf +; XTENSA-LABEL: cos_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI3_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.cos.f32(float %a) + ret float %1 +} + +declare float @llvm.pow.f32(float, float) + +define float @pow_f32(float %a, float %b) nounwind { +; XTENSA: .literal .LCPI4_0, powf +; XTENSA-LABEL: pow_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI4_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: mov.n a11, a3 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + %1 = call float @llvm.pow.f32(float %a, float %b) + ret float %1 +} + +declare float @llvm.exp.f32(float) + +define float @exp_f32(float %a) nounwind { +; XTENSA: .literal .LCPI5_0, expf +; XTENSA-LABEL: exp_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI5_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + %1 = call float @llvm.exp.f32(float %a) + ret float %1 +} + +declare float @llvm.exp2.f32(float) + +define float @exp2_f32(float %a) nounwind { +; XTENSA: .literal .LCPI6_0, exp2 +; XTENSA-LABEL: exp2_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI6_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + %1 = call float @llvm.exp2.f32(float %a) + ret float %1 +} + +declare float @llvm.log.f32(float) + +define float @log_f32(float %a) nounwind { +; XTENSA: .literal .LCPI7_0, log +; XTENSA-LABEL: log_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI7_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + %1 = call float @llvm.log.f32(float %a) + ret float %1 +} + +declare float @llvm.log10.f32(float) + +define float @log10_f32(float %a) nounwind { +; XTENSA: .literal .LCPI8_0, log10 +; XTENSA-LABEL: log10_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI8_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + %1 = call float @llvm.log10.f32(float %a) + ret float %1 +} + +declare float @llvm.log2.f32(float) + +define float @log2_f32(float %a) nounwind { +; XTENSA: .literal .LCPI9_0, log2 +; XTENSA-LABEL: log2_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI9_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + %1 = call float @llvm.log2.f32(float %a) + ret float %1 +} + +declare float @llvm.fma.f32(float, float, float) + +define float @fma_f32(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fma_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: madd.s f10, f9, f8 +; XTENSA-NEXT: rfr a2, f10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.fma.f32(float %a, float %b, float %c) + ret float %1 +} + +declare float @llvm.minnum.f32(float, float) + +define float @minnum_f32(float %a, float %b) nounwind { +; XTENSA: .literal .LCPI11_0, fminf +; XTENSA-LABEL: minnum_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI11_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: mov.n a11, a3 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.minnum.f32(float %a, float %b) + ret float %1 +} + +declare float @llvm.maxnum.f32(float, float) + +define float @maxnum_f32(float %a, float %b) nounwind { +; XTENSA: .literal .LCPI12_0, fmaxf +; XTENSA-LABEL: maxnum_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI12_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: mov.n a11, a3 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.maxnum.f32(float %a, float %b) + ret float %1 +} + +declare float @llvm.fabs.f32(float) + +define float @fabs_f32(float %a) nounwind { +; XTENSA: .literal .LCPI13_0, 2147483647 +; XTENSA-LABEL: fabs_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI13_0 +; XTENSA-NEXT: and a2, a2, a8 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.fabs.f32(float %a) + ret float %1 +} + +declare float @llvm.copysign.f32(float, float) + +define float @copysign_f32(float %a, float %b) nounwind { +; XTENSA: .literal .LCPI14_0, -2147483648 +; XTENSA: .literal .LCPI14_1, 2147483647 +; XTENSA-LABEL: copysign_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI14_0 +; XTENSA-NEXT: and a8, a3, a8 +; XTENSA-NEXT: l32r a9, .LCPI14_1 +; XTENSA-NEXT: and a9, a2, a9 +; XTENSA-NEXT: wfr f8, a9 +; XTENSA-NEXT: movi.n a9, 0 +; XTENSA-NEXT: beq a8, a9, .LBB14_2 +; XTENSA-NEXT: # %bb.1: +; XTENSA-NEXT: neg.s f8, f8 +; XTENSA-NEXT: .LBB14_2: +; XTENSA-NEXT: rfr a2, f8 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.copysign.f32(float %a, float %b) + ret float %1 +} + +declare float @llvm.floor.f32(float) + +define float @floor_f32(float %a) nounwind { +; XTENSA: .literal .LCPI15_0, floor +; XTENSA-LABEL: floor_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI15_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.floor.f32(float %a) + ret float %1 +} + +declare float @llvm.ceil.f32(float) + +define float @ceil_f32(float %a) nounwind { +; XTENSA: .literal .LCPI16_0, ceil +; XTENSA-LABEL: ceil_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI16_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.ceil.f32(float %a) + ret float %1 +} + +declare float @llvm.trunc.f32(float) + +define float @trunc_f32(float %a) nounwind { +; XTENSA: .literal .LCPI17_0, trunc +; XTENSA-LABEL: trunc_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI17_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.trunc.f32(float %a) + ret float %1 +} + +declare float @llvm.rint.f32(float) + +define float @rint_f32(float %a) nounwind { +; XTENSA: .literal .LCPI18_0, rint +; XTENSA-LABEL: rint_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI18_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.rint.f32(float %a) + ret float %1 +} + +declare float @llvm.nearbyint.f32(float) + +define float @nearbyint_f32(float %a) nounwind { +; XTENSA: .literal .LCPI19_0, nearbyint +; XTENSA-LABEL: nearbyint_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI19_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.nearbyint.f32(float %a) + ret float %1 +} + +declare float @llvm.round.f32(float) + +define float @round_f32(float %a) nounwind { +; XTENSA: .literal .LCPI20_0, round +; XTENSA-LABEL: round_f32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: l32r a8, .LCPI20_0 +; XTENSA-NEXT: mov.n a10, a2 +; XTENSA-NEXT: callx8 a8 +; XTENSA-NEXT: mov.n a2, a10 +; XTENSA-NEXT: retw.n + + %1 = call float @llvm.round.f32(float %a) + ret float %1 +} From d1d8e9623025f304410f504b59d053a728bf6cc1 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:53 +0300 Subject: [PATCH 071/261] [Xtensa] Implement MUL16 feature. --- llvm/lib/Target/Xtensa/Xtensa.td | 21 +++++++++++++-------- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 11 +++++++++++ llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 +++++ llvm/test/MC/Xtensa/xtensa-valid-mul16.s | 14 ++++++++++++++ 5 files changed, 44 insertions(+), 8 deletions(-) create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-mul16.s diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index dfcf95b9a61587..dd4b484aa6bad1 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -52,6 +52,11 @@ def FeatureNSA : SubtargetFeature<"nsa", "HasNSA", "true", def HasNSA : Predicate<"Subtarget->hasNSA()">, AssemblerPredicate<(all_of FeatureNSA)>; +def FeatureMul16 : SubtargetFeature<"mul16", "HasMul16", "true", + "Enable Xtensa Mul16 option">; +def HasMul16 : Predicate<"Subtarget->hasMul16()">, + AssemblerPredicate<(all_of FeatureMul16)>; + def FeatureMul32 : SubtargetFeature<"mul32", "HasMul32", "true", "Enable Xtensa Mul32 option">; def HasMul32 : Predicate<"Subtarget->hasMul32()">, @@ -171,20 +176,20 @@ class Proc Features> def : Proc<"generic", []>; -def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, - FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, +def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR]>; -def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException, FeatureHighPriInterrupts, - FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>; +def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException, + FeatureHighPriInterrupts, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>; -def : Proc<"esp32-s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, FeatureDiv32, - FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, +def : Proc<"esp32-s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, + FeatureDiv32, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureESP32S2Ops]>; -def : Proc<"esp32-s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, - FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, +def : Proc<"esp32-s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureESP32S3Ops]>; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 2adff84ac4551d..e12d0e1b0b3098 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1327,6 +1327,17 @@ def NSAU : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s), let r = 0xF; } +//===----------------------------------------------------------------------===// +// Mul16 Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasMul16] in { + def MUL16S : RRR_Inst<0x00, 0x01, 0x0D, (outs AR:$r), (ins AR:$s, AR:$t), + "mul16s\t$r, $s, $t", []>; + def MUL16U : RRR_Inst<0x00, 0x01, 0x0C, (outs AR:$r), (ins AR:$s, AR:$t), + "mul16u\t$r, $s, $t", []>; +} + //===----------------------------------------------------------------------===// // Mul32 Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index c9b8e0bd0e8c28..e164da998b5e79 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -39,6 +39,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasLoop = false; HasSEXT = false; HasNSA = false; + HasMul16 = false; HasMul32 = false; HasMul32High = false; HasDiv32 = false; diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index ee173686c2a206..b4fac0b65eb194 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -59,6 +59,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa NSA option bool HasNSA; + // Enable Xtensa Mul16 option + bool HasMul16; + // Enable Xtensa Mul32 option bool HasMul32; @@ -156,6 +159,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasNSA() const { return HasNSA; } + bool hasMul16() const { return HasMul16; } + bool hasMul32() const { return HasMul32; } bool hasMul32High() const { return HasMul32High; } diff --git a/llvm/test/MC/Xtensa/xtensa-valid-mul16.s b/llvm/test/MC/Xtensa/xtensa-valid-mul16.s new file mode 100644 index 00000000000000..4a6c525191f87e --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-mul16.s @@ -0,0 +1,14 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+mul16 -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + + +.align 4 +LBL0: + +# CHECK-INST: mul16s a2, a3, a4 +# CHECK: encoding: [0x40,0x23,0xd1] + mul16s a2, a3, a4 + +# CHECK-INST: mul16u a2, a3, a4 +# CHECK: encoding: [0x40,0x23,0xc1] + mul16u a2, a3, a4 From ce466909dc0512381703c143c6a681fbfde225a2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:53 +0300 Subject: [PATCH 072/261] [Xtensa] Add a no-op -mlongcalls option for better compatibility Many projects targeting Xtensa architecture use GCC-specific -mlongcalls option. The current behavior of LLVM for Xtensa is equivalent to this option being set, so accept this option without changing the behavior. --- clang/include/clang/Driver/Options.td | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 40d518eef9474e..4cf9ad4fd448df 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6108,6 +6108,7 @@ def mfix_esp32_psram_cache_issue : Flag<["-"], "mfix-esp32-psram-cache-issue">, def mfix_esp32_psram_cache_strategy_EQ : Joined<["-"], "mfix-esp32-psram-cache-strategy=">, Group, HelpText<" Psram cache fix strategies : memw, nops">, Values<"memw, nops">; +def mlongcalls : Flag<["-"], "mlongcalls">, Group; // These are legacy user-facing driver-level option spellings. They are always // aliases for options that are spelled using the more common Unix / GNU flag From 3d367d724df410435ddcb7dd8597742aa017b43f Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:54 +0300 Subject: [PATCH 073/261] [Xtensa] Add atomicrmw_xchg test. --- llvm/test/CodeGen/Xtensa/atomicrmw.ll | 103 ++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 llvm/test/CodeGen/Xtensa/atomicrmw.ll diff --git a/llvm/test/CodeGen/Xtensa/atomicrmw.ll b/llvm/test/CodeGen/Xtensa/atomicrmw.ll new file mode 100644 index 00000000000000..f2b7526e33e84c --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/atomicrmw.ll @@ -0,0 +1,103 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=CHECK-XTENSA %s + +define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { +; CHECK-XTENSA-LABEL: atomicrmw_xchg_i8_seq_cst: +; CHECK-XTENSA: # %bb.0: +; CHECK-XTENSA-NEXT: entry a1, 32 +; CHECK-XTENSA-NEXT: memw +; CHECK-XTENSA-NEXT: movi.n a8, 3 +; CHECK-XTENSA-NEXT: and a8, a8, a2 +; CHECK-XTENSA-NEXT: sub a9, a2, a8 +; CHECK-XTENSA-NEXT: slli a8, a8, 3 +; CHECK-XTENSA-NEXT: movi a10, 255 +; CHECK-XTENSA-NEXT: ssl a8 +; CHECK-XTENSA-NEXT: movi.n a11, -1 +; CHECK-XTENSA-NEXT: sll a10, a10 +; CHECK-XTENSA-NEXT: xor a11, a10, a11 +; CHECK-XTENSA-NEXT: l32i.n a12, a9, 0 +; CHECK-XTENSA-NEXT: sll a12, a3 +; CHECK-XTENSA-NEXT: l32i.n a13, a9, 0 +; CHECK-XTENSA-NEXT: and a14, a13, a10 +; CHECK-XTENSA-NEXT: .LBB0_1: # =>This Loop Header: Depth=1 +; CHECK-XTENSA-NEXT: # Child Loop BB0_2 Depth 2 +; CHECK-XTENSA-NEXT: mov.n a13, a14 +; CHECK-XTENSA-NEXT: memw +; CHECK-XTENSA-NEXT: l32i.n a14, a9, 0 +; CHECK-XTENSA-NEXT: and a7, a14, a11 +; CHECK-XTENSA-NEXT: .LBB0_2: # Parent Loop BB0_1 Depth=1 +; CHECK-XTENSA-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-XTENSA-NEXT: mov.n a15, a7 +; CHECK-XTENSA-NEXT: or a14, a12, a15 +; CHECK-XTENSA-NEXT: or a7, a13, a15 +; CHECK-XTENSA-NEXT: wsr a7, scompare1 +; CHECK-XTENSA-NEXT: s32c1i a14, a9, 0 +; CHECK-XTENSA-NEXT: beq a7, a14, .LBB0_4 +; CHECK-XTENSA-NEXT: # %bb.3: # in Loop: Header=BB0_2 Depth=2 +; CHECK-XTENSA-NEXT: and a7, a14, a11 +; CHECK-XTENSA-NEXT: bne a7, a15, .LBB0_2 +; CHECK-XTENSA-NEXT: .LBB0_4: # in Loop: Header=BB0_1 Depth=1 +; CHECK-XTENSA-NEXT: and a14, a14, a10 +; CHECK-XTENSA-NEXT: bne a14, a13, .LBB0_1 +; CHECK-XTENSA-NEXT: # %bb.5: +; CHECK-XTENSA-NEXT: ssr a8 +; CHECK-XTENSA-NEXT: srl a8, a14 +; CHECK-XTENSA-NEXT: sext a2, a8, 7 +; CHECK-XTENSA-NEXT: memw +; CHECK-XTENSA-NEXT: retw.n + + %1 = atomicrmw xchg i8* %a, i8 %b seq_cst + ret i8 %1 +} + +define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { +; CHECK-XTENSA-LABEL: atomicrmw_xchg_i16_seq_cst: +; CHECK-XTENSA: # %bb.0: +; CHECK-XTENSA-NEXT: entry a1, 32 +; CHECK-XTENSA-NEXT: memw +; CHECK-XTENSA-NEXT: movi.n a8, 3 +; CHECK-XTENSA-NEXT: and a8, a8, a2 +; CHECK-XTENSA-NEXT: sub a9, a2, a8 +; CHECK-XTENSA-NEXT: slli a8, a8, 3 +; CHECK-XTENSA-NEXT: movi.n a10, 1 +; CHECK-XTENSA-NEXT: slli a10, a10, 16 +; CHECK-XTENSA-NEXT: addi.n a10, a10, -1 +; CHECK-XTENSA-NEXT: ssl a8 +; CHECK-XTENSA-NEXT: movi.n a11, -1 +; CHECK-XTENSA-NEXT: sll a10, a10 +; CHECK-XTENSA-NEXT: xor a11, a10, a11 +; CHECK-XTENSA-NEXT: l32i.n a12, a9, 0 +; CHECK-XTENSA-NEXT: sll a12, a3 +; CHECK-XTENSA-NEXT: l32i.n a13, a9, 0 +; CHECK-XTENSA-NEXT: and a14, a13, a10 +; CHECK-XTENSA-NEXT: .LBB1_1: # =>This Loop Header: Depth=1 +; CHECK-XTENSA-NEXT: # Child Loop BB1_2 Depth 2 +; CHECK-XTENSA-NEXT: mov.n a13, a14 +; CHECK-XTENSA-NEXT: memw +; CHECK-XTENSA-NEXT: l32i.n a14, a9, 0 +; CHECK-XTENSA-NEXT: and a7, a14, a11 +; CHECK-XTENSA-NEXT: .LBB1_2: # Parent Loop BB1_1 Depth=1 +; CHECK-XTENSA-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-XTENSA-NEXT: mov.n a15, a7 +; CHECK-XTENSA-NEXT: or a14, a12, a15 +; CHECK-XTENSA-NEXT: or a7, a13, a15 +; CHECK-XTENSA-NEXT: wsr a7, scompare1 +; CHECK-XTENSA-NEXT: s32c1i a14, a9, 0 +; CHECK-XTENSA-NEXT: beq a7, a14, .LBB1_4 +; CHECK-XTENSA-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=2 +; CHECK-XTENSA-NEXT: and a7, a14, a11 +; CHECK-XTENSA-NEXT: bne a7, a15, .LBB1_2 +; CHECK-XTENSA-NEXT: .LBB1_4: # in Loop: Header=BB1_1 Depth=1 +; CHECK-XTENSA-NEXT: and a14, a14, a10 +; CHECK-XTENSA-NEXT: bne a14, a13, .LBB1_1 +; CHECK-XTENSA-NEXT: # %bb.5: +; CHECK-XTENSA-NEXT: ssr a8 +; CHECK-XTENSA-NEXT: srl a8, a14 +; CHECK-XTENSA-NEXT: sext a2, a8, 15 +; CHECK-XTENSA-NEXT: memw +; CHECK-XTENSA-NEXT: retw.n + + %1 = atomicrmw xchg i16* %a, i16 %b seq_cst + ret i16 %1 +} From 6db70e2c1d7c12864e6b09fd8eecc235d6702550 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:54 +0300 Subject: [PATCH 074/261] [Xtensa] Initialize MCSubtargetInfo with esp32. Initialize Xtensa MCSubtargetInfo with esp32 subtarget by default. --- llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp index 8832cdf7dc01f1..ffb26e566709f9 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp @@ -65,6 +65,8 @@ static MCRegisterInfo *createXtensaMCRegisterInfo(const Triple &TT) { static MCSubtargetInfo * createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + if (CPU.empty()) + CPU = "esp32"; return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS); } From 16f68b5e95084c8efbe70f5e8ece87f3db3abd67 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:55 +0300 Subject: [PATCH 075/261] [Xtensa] Correction of the Hardware Loop pass. Update loop counter via a phi instruction. This improvement fix case when loop have multiple enters. --- .../lib/Target/Xtensa/XtensaHardwareLoops.cpp | 182 ++++++++++++------ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 62 +++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 4 + llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 9 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 14 +- llvm/lib/Target/Xtensa/XtensaOperators.td | 7 +- .../Xtensa/XtensaTargetTransformInfo.cpp | 2 +- 7 files changed, 201 insertions(+), 79 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp b/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp index a1a2432ded4c1d..34dc193995594d 100644 --- a/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp +++ b/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp @@ -67,6 +67,7 @@ struct XtensaHardwareLoops : public MachineFunctionPass { MachineRegisterInfo *MRI; MachineDominatorTree *MDT; const XtensaInstrInfo *TII; + const TargetRegisterInfo *TRI; const XtensaSubtarget *STI; SmallPtrSet VisitedMBBs; @@ -99,7 +100,10 @@ struct XtensaHardwareLoops : public MachineFunctionPass { bool checkLoopSize(MachineLoop *L); - bool checkLoopEndDisplacement(MachineFunction &MF, MachineBasicBlock *LH, MachineBasicBlock* LE); + bool checkLoopEndDisplacement(MachineFunction &MF, MachineBasicBlock *LH, + MachineBasicBlock *LE); + + void revertNonLoops(MachineFunction &M); }; char XtensaHardwareLoops::ID = 0; @@ -119,11 +123,11 @@ bool XtensaHardwareLoops::runOnMachineFunction(MachineFunction &MF) { return false; bool Changed = false; - MLI = &getAnalysis(); MRI = &MF.getRegInfo(); STI = &MF.getSubtarget(); TII = STI->getInstrInfo(); + TRI = STI->getRegisterInfo(); if (!STI->hasLoop()) return false; @@ -135,6 +139,8 @@ bool XtensaHardwareLoops::runOnMachineFunction(MachineFunction &MF) { Changed |= processLoop(L); } + revertNonLoops(MF); + return Changed; } @@ -191,27 +197,33 @@ bool XtensaHardwareLoops::processLoop(MachineLoop *L) { return true; using instr_iterator = MachineBasicBlock::instr_iterator; - MachineInstr *LII = nullptr; // LOOPINIT instruction - MachineInstr *LEI = nullptr; // LOOPEND instruction - MachineBasicBlock *LEMBB = nullptr; + MachineInstr *LII = nullptr; // LOOPINIT instruction + MachineInstr *LDECI = nullptr; // LOOPDEC instruction + MachineInstr *LBRI = nullptr; // LOOPBR instruction + MachineBasicBlock *LDECMBB = nullptr; + MachineBasicBlock *LBRMBB = nullptr; MachineBasicBlock *LH = L->getHeader(); MachineBasicBlock *LastMBB = L->getLoopLatch(); - std::vector LoopInitInsts; std::map LoopInitMap; - // Try to find LOOPEND instruction in the loop latch + // Try to find LOOPENDDEC instruction in the loop latch for (auto MBI = L->block_begin(), MBIE = L->block_end(); MBI != MBIE; ++MBI) { if (VisitedMBBs.count(*MBI)) continue; for (auto MII = (*MBI)->begin(), MIE = (*MBI)->end(); MII != MIE; ++MII) { MachineInstr *LMI = &*MII; - if (LMI->getOpcode() == Xtensa::LOOPEND) { - LEI = LMI; - LEMBB = *MBI; + if (LMI->getOpcode() == Xtensa::LOOPDEC) { + LDECI = LMI; + LDECMBB = *MBI; + } + + if (LMI->getOpcode() == Xtensa::LOOPBR) { + LBRI = LMI; + LBRMBB = *MBI; } + // Collect LOOPINIT instructions inside the loop if (LMI->getOpcode() == Xtensa::LOOPINIT) { - LoopInitInsts.push_back(LMI); MachineBasicBlock *SB = LMI->getParent(); while (!SB->isSuccessor(LH)) { for (auto SBI : SB->successors()) { @@ -229,10 +241,17 @@ bool XtensaHardwareLoops::processLoop(MachineLoop *L) { VisitedMBBs.insert(*MBI); } - if (LEI != nullptr) { - MachineBasicBlock::iterator LHI = LH->getFirstNonPHI(); + if ((LBRI != nullptr) && (LDECI != nullptr)) { MachineBasicBlock *LIMBB = nullptr; + for (const auto &Use : MRI->use_operands(LDECI->getOperand(0).getReg())) { + const MachineInstr *UseMI = Use.getParent(); + if ((UseMI != LBRI) && (UseMI->getOpcode() != TargetOpcode::PHI)) { + LLVM_DEBUG(dbgs() << "Xtensa Loops: Unable to remove LoopDec.\n"); + return false; + } + } + // Collect LOOPINIT instructions in predecessors from outter loop for (auto PBI : LH->predecessors()) { if (L->contains(PBI)) @@ -268,76 +287,72 @@ bool XtensaHardwareLoops::processLoop(MachineLoop *L) { // sub a, a, 1 // bnez a, LH if (!checkLoopSize(L) || containsInvalidInstruction(L) || - (LEMBB != LastMBB) || - (!checkLoopEndDisplacement(*LH->getParent(), LH, LEMBB))) { - const MCInstrDesc &PD = TII->get(TargetOpcode::PHI); - MachineInstr *NewPN = LH->getParent()->CreateMachineInstr(PD, DL); - LH->insert(LH->begin(), NewPN); - Register PR = MRI->createVirtualRegister(&Xtensa::ARRegClass); - NewPN->addOperand(MachineOperand::CreateReg(PR, true)); - - Register IndR = MRI->createVirtualRegister(&Xtensa::ARRegClass); + (LBRMBB != LastMBB) || + (!checkLoopEndDisplacement(*LH->getParent(), LH, LBRMBB))) { for (auto PB : LH->predecessors()) { - if (LoopInitMap.find(PB) != LoopInitMap.end()) { - MachineOperand MO = MachineOperand::CreateReg( - LoopInitMap[PB]->getOperand(0).getReg(), false); - NewPN->addOperand(MO); - NewPN->addOperand(MachineOperand::CreateMBB(PB)); + Register Elts = LoopInitMap[PB]->getOperand(1).getReg(); + Register Def = LoopInitMap[PB]->getOperand(0).getReg(); + + for (auto &Use : make_early_inc_range(MRI->use_operands(Def))) { + Use.setReg(Elts); + } LoopInitMap[PB]->getParent()->erase(LoopInitMap[PB]); - } else { - MachineOperand MO = MachineOperand::CreateReg(IndR, false); - NewPN->addOperand(MO); - NewPN->addOperand(MachineOperand::CreateMBB(PB)); } } - MachineInstrBuilder MIB = - BuildMI(*LEMBB, LEI, LEI->getDebugLoc(), TII->get(Xtensa::ADDI), IndR) - .addReg(PR) - .addImm(-1); - - MIB = BuildMI(*LEMBB, LEI, LEI->getDebugLoc(), TII->get(Xtensa::BNEZ)) - .addReg(IndR) - .addMBB(LEI->getOperand(0).getMBB()); - LEMBB->erase(LEI); + Register IndR = LDECI->getOperand(0).getReg(); + Register PR = LDECI->getOperand(1).getReg(); + + BuildMI(*LDECMBB, LDECI, LDECI->getDebugLoc(), TII->get(Xtensa::ADDI), + IndR) + .addReg(PR) + .addImm(-1); + BuildMI(*LBRMBB, LBRI, LBRI->getDebugLoc(), TII->get(Xtensa::BNEZ)) + .addReg(IndR) + .addMBB(LBRI->getOperand(1).getMBB()); + LDECMBB->erase(LDECI); + LBRMBB->erase(LBRI); return false; } - // If several LOOPINIT instructions are dicovered then create PHI - // function - if (LoopInitMap.size() > 1) { - const MCInstrDesc &PD = TII->get(TargetOpcode::PHI); - MachineInstr *NewPN = LH->getParent()->CreateMachineInstr(PD, DL); - LH->insert(LH->begin(), NewPN); - Register PR = MRI->createVirtualRegister(&Xtensa::ARRegClass); - NewPN->addOperand(MachineOperand::CreateReg(PR, true)); - - for (auto PB : LH->predecessors()) { + MachineInstr *PN = nullptr; - if (LoopInitMap.find(PB) != LoopInitMap.end()) { - MachineOperand MO = MachineOperand::CreateReg( - LoopInitMap[PB]->getOperand(0).getReg(), false); - NewPN->addOperand(MO); - NewPN->addOperand(MachineOperand::CreateMBB(PB)); - LoopInitMap[PB]->getParent()->erase(LoopInitMap[PB]); - } else { - MachineOperand MO = MachineOperand::CreateReg(PR, false); - NewPN->addOperand(MO); - NewPN->addOperand(MachineOperand::CreateMBB(PB)); - } + for (auto &Use : MRI->use_operands(LDECI->getOperand(0).getReg())) { + MachineInstr *UseMI = Use.getParent(); + if (UseMI->getOpcode() == TargetOpcode::PHI) { + PN = UseMI; } - LII = NewPN; } + assert(((PN != nullptr) && (PN->getParent() == LH)) && + "Expected PHI node successor of the LOOPEND instruction in loop " + "header"); + LII = PN; + + Register EltsDec = LDECI->getOperand(0).getReg(); + Register Elts = LDECI->getOperand(1).getReg(); + + for (MachineOperand &MO : PN->operands()) { + if (!MO.isReg() || MO.getReg() != EltsDec) + continue; + MO.substVirtReg(Elts, 0, *TRI); + } + LDECMBB->erase(LDECI); + + MachineBasicBlock::iterator LHI = LH->getFirstNonPHI(); + BuildMI(*LH, LHI, DL, TII->get(Xtensa::LOOPSTART)) .addReg(LII->getOperand(0).getReg()) - .addMBB(LEMBB); + .addMBB(LBRMBB); if (LII->getOpcode() == Xtensa::LOOPINIT) LII->getParent()->erase(LII); + BuildMI(*LBRMBB, LBRI, DL, TII->get(Xtensa::LOOPEND)).addMBB(LH); + LBRMBB->erase(LBRI); + return true; } @@ -386,3 +401,44 @@ bool XtensaHardwareLoops::checkLoopEndDisplacement(MachineFunction &MF, llvm_unreachable("Wrong hardware loop"); } +void XtensaHardwareLoops::revertNonLoops(MachineFunction &MF) { + for (MachineFunction::iterator I = MF.begin(); I != MF.end(); ++I) { + MachineBasicBlock &MBB = *I; + + for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); MII != E; + ++MII) { + MachineInstr *MI = &*MII; + if (MI->getOpcode() == Xtensa::LOOPINIT) { + MachineInstr *LI = MI; + MachineBasicBlock *LIMBB = LI->getParent(); + Register Elts = LI->getOperand(1).getReg(); + Register Def = LI->getOperand(0).getReg(); + for (auto &Use : make_early_inc_range(MRI->use_operands(Def))) { + Use.setReg(Elts); + } + --MII; + LIMBB->erase(LI); + } else if (MI->getOpcode() == Xtensa::LOOPDEC) { + MachineInstr *LEI = MI; + MachineBasicBlock *LEMBB = LEI->getParent(); + Register IndR = LEI->getOperand(0).getReg(); + Register PR = LEI->getOperand(1).getReg(); + + BuildMI(*LEMBB, LEI, LEI->getDebugLoc(), TII->get(Xtensa::ADDI), IndR) + .addReg(PR) + .addImm(-1); + --MII; + LEMBB->erase(LEI); + } else if (MI->getOpcode() == Xtensa::LOOPBR) { + MachineInstr *LBRI = MI; + MachineBasicBlock *LBRMBB = LBRI->getParent(); + + BuildMI(*LBRMBB, LBRI, LBRI->getDebugLoc(), TII->get(Xtensa::BNEZ)) + .addReg(LBRI->getOperand(0).getReg()) + .addMBB(LBRI->getOperand(1).getMBB()); + --MII; + LBRMBB->erase(LBRI); + } + } + } +} diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 1ce10184ed3dcd..c08ef83b1cf7de 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -302,10 +302,14 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setTargetDAGCombine(ISD::FSUB); } - if (Subtarget.hasSingleFloat() || Subtarget.hasLoop()) { + if (Subtarget.hasSingleFloat()) { setTargetDAGCombine(ISD::BRCOND); } + if (Subtarget.hasLoop()) { + setTargetDAGCombine(ISD::BR_CC); + } + // Needed so that we don't try to implement f128 constant loads using // a load-and-extend of a f80 constant (in cases where the constant // would fit in an f80). @@ -592,7 +596,7 @@ static SDValue SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm, } case ISD::INTRINSIC_W_CHAIN: { unsigned IntOp = cast(N.getOperand(1))->getZExtValue(); - if (IntOp != Intrinsic::loop_decrement) + if (IntOp != Intrinsic::loop_decrement_reg) return SDValue(); return N; } @@ -600,17 +604,28 @@ static SDValue SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm, return SDValue(); } -static SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG, +static SDValue PerformHWLoopCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const XtensaSubtarget &Subtarget) { SDValue Chain = N->getOperand(0); SDLoc DL(N); - SDValue Cond = N->getOperand(1); - SDValue Dest = N->getOperand(2); + SDValue Cond; + SDValue Dest; ISD::CondCode CC = ISD::SETEQ; int Imm = 1; bool Negate = false; + assert(N->getOpcode() == ISD::BR_CC && "Expected BR_CC!"); + CC = cast(N->getOperand(1))->get(); + Cond = N->getOperand(2); + Dest = N->getOperand(4); + if (auto *Const = dyn_cast(N->getOperand(3))) { + if (!Const->isOne() && !Const->isZero()) + return SDValue(); + Imm = Const->getZExtValue(); + } else + return SDValue(); + SDValue Int = SearchLoopIntrinsic(Cond, CC, Imm, Negate); if (Int) { assert((N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BR) && @@ -641,16 +656,39 @@ static SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG, } else if (!IsFalseIfZero(CC, Imm)) { llvm_unreachable("unsupported condition"); } + SDLoc dl(Int); + SDValue Elements = Int.getOperand(2); + SDValue Size = DAG.getTargetConstant( + cast(Int.getOperand(3))->getZExtValue(), dl, MVT::i32); + SDValue Args[] = { + Int.getOperand(0), + Elements, + Size, + }; + SDValue LoopDec = DAG.getNode(XtensaISD::LOOPDEC, dl, + DAG.getVTList(MVT::i32, MVT::Other), Args); // We now need to make the intrinsic dead (it cannot be instruction // selected). - DAG.ReplaceAllUsesOfValueWith(Int.getValue(1), Int.getOperand(0)); - assert(Int.getNode()->hasOneUse() && - "Counter decrement has more than one use"); + DAG.ReplaceAllUsesWith(Int.getNode(), LoopDec.getNode()); + + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + SDValue(LoopDec.getNode(), 1), Chain); - return DAG.getNode(XtensaISD::LOOPEND, DL, MVT::Other, N->getOperand(0), - Dest); + SDValue EndArgs[] = {Chain, SDValue(LoopDec.getNode(), 0), Dest}; + return DAG.getNode(XtensaISD::LOOPBR, dl, MVT::Other, EndArgs); } + return SDValue(); +} + +static SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const XtensaSubtarget &Subtarget) { + SDValue Chain = N->getOperand(0); + SDLoc DL(N); + SDValue Cond = N->getOperand(1); + SDValue Dest = N->getOperand(2); + ISD::CondCode CC = ISD::SETEQ; if (Cond.getOpcode() != ISD::SETCC) return SDValue(); @@ -678,6 +716,8 @@ SDValue XtensaTargetLowering::PerformDAGCombine(SDNode *N, return performADDCombine(N, DAG, DCI, Subtarget); case ISD::FSUB: return performSUBCombine(N, DAG, DCI, Subtarget); + case ISD::BR_CC: + return PerformHWLoopCombine(N, DAG, DCI, Subtarget); case ISD::BRCOND: return PerformBRCONDCombine(N, DAG, DCI, Subtarget); } @@ -1850,6 +1890,8 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(CMPOEQ); OPCODE(CMPOLE); OPCODE(CMPOLT); + OPCODE(LOOPBR); + OPCODE(LOOPDEC); OPCODE(LOOPEND); OPCODE(MADD); OPCODE(MSUB); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 57d99cbe9703ba..800b8e69cfdbe1 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -50,6 +50,10 @@ enum { CMPOLE, CMPOLT, + // Branch at the end of the loop, uses result of the LOOPDEC + LOOPBR, + // Decrement loop counter + LOOPDEC, LOOPEND, // FP multipy-add/sub diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 81979f522c827d..04d3d2d3c04119 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -262,6 +262,7 @@ bool XtensaInstrInfo::reverseBranchCondition( return false; case Xtensa::LOOPEND: + case Xtensa::LOOPBR: return true; default: @@ -299,6 +300,7 @@ XtensaInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { case Xtensa::BNEZ: case Xtensa::BLTZ: case Xtensa::BGEZ: + case Xtensa::LOOPBR: return MI.getOperand(1).getMBB(); case Xtensa::BT: @@ -319,6 +321,7 @@ bool XtensaInstrInfo::isBranchOffsetInRange(unsigned BranchOp, case Xtensa::JX: return true; case Xtensa::LOOPEND: + case Xtensa::LOOPBR: BrOffset += 4; assert((BrOffset <= 0) && "Wrong hardware loop"); return true; @@ -634,6 +637,7 @@ unsigned XtensaInstrInfo::InsertBranchAtInst(MachineBasicBlock &MBB, case Xtensa::BNEZ: case Xtensa::BLTZ: case Xtensa::BGEZ: + case Xtensa::LOOPBR: MI = BuildMI(MBB, I, DL, get(BR_C)).addReg(Cond[1].getReg()).addMBB(TBB); break; case Xtensa::BT: @@ -641,7 +645,7 @@ unsigned XtensaInstrInfo::InsertBranchAtInst(MachineBasicBlock &MBB, MI = BuildMI(MBB, I, DL, get(BR_C)).addReg(Cond[1].getReg()).addMBB(TBB); break; case Xtensa::LOOPEND: - MI = BuildMI(MBB, I, DL, get(BR_C)).addMBB(TBB); + MI = BuildMI(MBB, I, DL, get(Xtensa::LOOPEND)).addMBB(TBB); break; default: llvm_unreachable("Invalid branch type!"); @@ -730,6 +734,7 @@ bool XtensaInstrInfo::isBranch(const MachineBasicBlock::iterator &MI, case Xtensa::BNEZ: case Xtensa::BLTZ: case Xtensa::BGEZ: + case Xtensa::LOOPBR: Cond[0].setImm(OpCode); Target = &MI->getOperand(1); return true; @@ -744,4 +749,4 @@ bool XtensaInstrInfo::isBranch(const MachineBasicBlock::iterator &MI, assert(!MI->getDesc().isBranch() && "Unknown branch opcode"); return false; } -} +} \ No newline at end of file diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index e12d0e1b0b3098..2a59d179761f06 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1286,8 +1286,8 @@ def LOOPNEZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), } let isTerminator = 1, isBarrier = 1, hasSideEffects = 1, Size = 3 in { - def LOOPINIT : Pseudo<(outs), (ins AR:$elts), - "!loopinit $elts", [(int_set_loop_iterations AR:$elts)]>; + def LOOPINIT : Pseudo<(outs AR:$elts), (ins AR:$eltsin), + "!loopinit $elts, $eltsin", [(set AR:$elts, (int_start_loop_iterations AR:$eltsin))]>; } // LOOPSTART pseudo instruction reserves 9 bytes for LOOP operation and NOP operations for possible alignment. @@ -1302,6 +1302,16 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 0, Size = "!loopend $target", [(Xtensa_loopend bb:$target)]>; } +let isTerminator = 1, isBarrier = 1, hasSideEffects = 1, Size = 3 in { + def LOOPDEC : Pseudo<(outs AR:$eltsout), (ins AR:$eltsin), + "!loopdec $eltsout, $eltsin", [(set AR:$eltsout, (Xtensa_loopdec AR:$eltsin))]>; +} + +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 0, Size = 3 in { + def LOOPBR : Pseudo<(outs), (ins AR:$elts, brtarget:$target), + "!loopbr $elts, $target", [(Xtensa_loopbr AR:$elts, bb:$target)]>; +} + //===----------------------------------------------------------------------===// // SEXT Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index a37dcd7c8a9869..cdc29be5deb3bb 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -45,6 +45,8 @@ def SDT_XtensaMEMBARRIER : SDTypeProfile<0, 0, []>; def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; def SDT_XtensaLoopEnd : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; +def SDT_XtensaLoopDec : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>; +def SDT_XtensaLoopBr : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisVT<1, OtherVT>]>; //===----------------------------------------------------------------------===// // Node definitions @@ -112,4 +114,7 @@ def Xtensa_rur: SDNode<"XtensaISD::RUR", SDT_XtensaRUR, def Xtensa_loopend: SDNode<"XtensaISD::LOOPEND", SDT_XtensaLoopEnd, [SDNPHasChain, SDNPInGlue]>; - +def Xtensa_loopdec: SDNode<"XtensaISD::LOOPDEC", SDT_XtensaLoopDec, + [SDNPHasChain, SDNPInGlue]>; +def Xtensa_loopbr: SDNode<"XtensaISD::LOOPBR", SDT_XtensaLoopBr, + [SDNPHasChain, SDNPInGlue]>; diff --git a/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp index 7bdec70504772f..62ad8b6b00997f 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp @@ -27,7 +27,7 @@ bool XtensaTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, return false; LLVMContext &C = L->getHeader()->getContext(); - HWLoopInfo.CounterInReg = false; + HWLoopInfo.CounterInReg = true; HWLoopInfo.IsNestingLegal = false; HWLoopInfo.CountType = Type::getInt32Ty(C); HWLoopInfo.LoopDecrement = ConstantInt::get(HWLoopInfo.CountType, 1); From b5a004a46f5a6567449589caf36c5a6bf2245e2e Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:55 +0300 Subject: [PATCH 076/261] [Xtensa] Fix atomic swap for 8/16 bit operands. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index c08ef83b1cf7de..7ae0efd5529afa 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -2423,7 +2423,7 @@ XtensaTargetLowering::emitAtomicSwap(MachineInstr &MI, MachineBasicBlock *BB, unsigned R8 = MRI.createVirtualRegister(RC); BuildMI(*BB, St, DL, TII.get(Xtensa::SSR)).addReg(BitOffs); - BuildMI(*BB, St, DL, TII.get(Xtensa::SLL), R8).addReg(AtomValLoop); + BuildMI(*BB, St, DL, TII.get(Xtensa::SRL), R8).addReg(AtomValLoop); if (isByteOperand) { BuildMI(*BB, St, DL, TII.get(Xtensa::SEXT), Res.getReg()) From 9adbe8c2199c22dbf451f629aadc6a1c14a795a0 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:56 +0300 Subject: [PATCH 077/261] [Xtensa] Initial porting compiler-rt library for Xtensa. --- compiler-rt/cmake/Modules/CompilerRTUtils.cmake | 2 ++ compiler-rt/cmake/base-config-ix.cmake | 2 ++ compiler-rt/cmake/builtin-config-ix.cmake | 3 ++- compiler-rt/lib/builtins/CMakeLists.txt | 2 ++ compiler-rt/lib/builtins/crtbegin.c | 14 ++++++++++++++ 5 files changed, 22 insertions(+), 1 deletion(-) diff --git a/compiler-rt/cmake/Modules/CompilerRTUtils.cmake b/compiler-rt/cmake/Modules/CompilerRTUtils.cmake index 25e7823716fc2f..c858a08af0ca10 100644 --- a/compiler-rt/cmake/Modules/CompilerRTUtils.cmake +++ b/compiler-rt/cmake/Modules/CompilerRTUtils.cmake @@ -214,6 +214,8 @@ macro(detect_target_arch) add_default_target_arch(sparc) elseif(__WEBASSEMBLY32) add_default_target_arch(wasm32) + elseif(__XTENSA) + add_default_target_arch(xtensa) elseif(__WEBASSEMBLY64) add_default_target_arch(wasm64) elseif(__VE) diff --git a/compiler-rt/cmake/base-config-ix.cmake b/compiler-rt/cmake/base-config-ix.cmake index 908c8a40278cf0..f52b82aa822382 100644 --- a/compiler-rt/cmake/base-config-ix.cmake +++ b/compiler-rt/cmake/base-config-ix.cmake @@ -274,6 +274,8 @@ macro(test_targets) test_target_arch(riscv64 "" "") elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "wasm32") test_target_arch(wasm32 "" "--target=wasm32-unknown-unknown") + elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "xtensa") + test_target_arch(xtensa "" "--target=xtensa") elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "wasm64") test_target_arch(wasm64 "" "--target=wasm64-unknown-unknown") elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "ve") diff --git a/compiler-rt/cmake/builtin-config-ix.cmake b/compiler-rt/cmake/builtin-config-ix.cmake index b17c43bf6a68b8..af83b0b0873c46 100644 --- a/compiler-rt/cmake/builtin-config-ix.cmake +++ b/compiler-rt/cmake/builtin-config-ix.cmake @@ -67,6 +67,7 @@ set(SPARCV9 sparcv9) set(WASM32 wasm32) set(WASM64 wasm64) set(VE ve) +set(XTENSA xtensa) if(APPLE) set(ARM64 arm64 arm64e) @@ -78,7 +79,7 @@ set(ALL_BUILTIN_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${AVR} ${HEXAGON} ${MIPS32} ${MIPS64} ${PPC32} ${PPC64} ${RISCV32} ${RISCV64} ${SPARC} ${SPARCV9} - ${WASM32} ${WASM64} ${VE} ${LOONGARCH64}) + ${WASM32} ${WASM64} ${VE} ${LOONGARCH64} ${XTENSA}) include(CompilerRTUtils) include(CompilerRTDarwinUtils) diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt index 28ded8766f2533..d73362f0f1d0c4 100644 --- a/compiler-rt/lib/builtins/CMakeLists.txt +++ b/compiler-rt/lib/builtins/CMakeLists.txt @@ -733,6 +733,8 @@ set(riscv64_SOURCES set(sparc_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES}) set(sparcv9_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES}) +set(xtensa_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES}) + set(wasm32_SOURCES ${GENERIC_TF_SOURCES} ${GENERIC_SOURCES} diff --git a/compiler-rt/lib/builtins/crtbegin.c b/compiler-rt/lib/builtins/crtbegin.c index a0860ca12ea032..fb22c0035ddc9b 100644 --- a/compiler-rt/lib/builtins/crtbegin.c +++ b/compiler-rt/lib/builtins/crtbegin.c @@ -73,6 +73,13 @@ __asm__(".pushsection .init,\"ax\",@progbits\n\t" __asm__(".pushsection .init,\"ax\",@progbits\n\t" "call __do_init\n\t" ".popsection"); +#elif defined(__xtensa__) +__asm__(".pushsection .init.literal,\"ax\",@progbits\n\t" + ".popsection\n\t" + ".pushsection .init,\"ax\",@progbits\n\t" + "movi a8, __do_init\n\t" + "callx8 a8\n\t" + ".popsection"); #else #error "crtbegin without .init_fini array unimplemented for this architecture" #endif // CRT_HAS_INITFINI_ARRAY @@ -130,6 +137,13 @@ __asm__(".pushsection .fini,\"ax\",@progbits\n\t" __asm__(".pushsection .fini,\"ax\",@progbits\n\t" "call __do_fini\n\t" ".popsection"); +#elif defined(__xtensa__) +__asm__(".pushsection .fini.literal,\"ax\",@progbits\n\t" + ".popsection\n\t" + ".pushsection .fini,\"ax\",@progbits\n\t" + "movi a8, __do_fini\n\t" + "callx8 a8\n\t" + ".popsection"); #else #error "crtbegin without .init_fini array unimplemented for this architecture" #endif // CRT_HAS_INIT_FINI_ARRAY From 38c63a138901e5bbef84dd14ba6f39ca545bbfbd Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:56 +0300 Subject: [PATCH 078/261] [Xtensa] Add support of "-mcpu" option. Implement support of the "-mcpu" option. Support Xtensa features in clang. Add macros definintion in XtensaTargetInfo based on Xtensa features. --- clang/lib/Basic/Targets/Xtensa.cpp | 54 ++++++++++- clang/lib/Basic/Targets/Xtensa.h | 23 +++-- clang/lib/Driver/ToolChains/CommonArgs.cpp | 4 + clang/lib/Driver/ToolChains/Xtensa.cpp | 42 +++++++-- clang/lib/Driver/ToolChains/Xtensa.h | 7 +- clang/test/Driver/xtensa-cpus.c | 36 +++++++ clang/test/Misc/target-invalid-cpu-note.c | 4 + .../llvm/TargetParser/XtensaTargetParser.def | 83 +++++++++++++++++ .../llvm/TargetParser/XtensaTargetParser.h | 71 ++++++++++++++ llvm/include/module.modulemap | 1 + .../Xtensa/AsmParser/XtensaAsmParser.cpp | 14 +-- .../Disassembler/XtensaDisassembler.cpp | 8 +- .../MCTargetDesc/XtensaMCTargetDesc.cpp | 4 + llvm/lib/Target/Xtensa/Xtensa.td | 18 ++-- .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 12 ++- llvm/lib/TargetParser/CMakeLists.txt | 1 + llvm/lib/TargetParser/XtensaTargetParser.cpp | 93 +++++++++++++++++++ .../secondary/llvm/lib/TargetParser/BUILD.gn | 1 + 18 files changed, 439 insertions(+), 37 deletions(-) create mode 100644 clang/test/Driver/xtensa-cpus.c create mode 100644 llvm/include/llvm/TargetParser/XtensaTargetParser.def create mode 100644 llvm/include/llvm/TargetParser/XtensaTargetParser.h create mode 100644 llvm/lib/TargetParser/XtensaTargetParser.cpp diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp index 6ca5cba2f6aeca..3bc8cc531069d6 100644 --- a/clang/lib/Basic/Targets/Xtensa.cpp +++ b/clang/lib/Basic/Targets/Xtensa.cpp @@ -33,8 +33,60 @@ ArrayRef XtensaTargetInfo::getTargetBuiltins() const { void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { - Builder.defineMacro("__Xtensa__"); + Builder.defineMacro("__ELF__"); Builder.defineMacro("__xtensa__"); Builder.defineMacro("__XTENSA__"); Builder.defineMacro("__XTENSA_EL__"); + if (HasWindowed) + Builder.defineMacro("__XTENSA_WINDOWED_ABI__"); + else + Builder.defineMacro("__XTENSA_CALL0_ABI__"); + if (!HasFP) + Builder.defineMacro("__XTENSA_SOFT_FLOAT__"); +} + +void XtensaTargetInfo::fillValidCPUList( + SmallVectorImpl &Values) const { + llvm::Xtensa::fillValidCPUList(Values); +} + +bool XtensaTargetInfo::initFeatureMap( + llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU, + const std::vector &FeaturesVec) const { + + // Assume that by default cpu is esp32 + if (CPU.empty()) + CPU = "esp32"; + + CPU = llvm::Xtensa::getBaseName(CPU); + + SmallVector CPUFeatures; + llvm::Xtensa::getCPUFeatures(CPU, CPUFeatures); + + for (auto Feature : CPUFeatures) + if (Feature[0] == '+') + Features[Feature.drop_front(1)] = true; + + return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); +} + +/// Return true if has this feature, need to sync with handleTargetFeatures. +bool XtensaTargetInfo::hasFeature(StringRef Feature) const { + return llvm::StringSwitch(Feature) + .Case("fp", HasFP) + .Case("windowed", HasWindowed) + .Default(false); +} + +/// Perform initialization based on the user configured set of features. +bool XtensaTargetInfo::handleTargetFeatures(std::vector &Features, + DiagnosticsEngine &Diags) { + for (const auto &Feature : Features) { + if (Feature == "+fp") + HasFP = true; + else if (Feature == "+windowed") + HasWindowed = true; + } + + return true; } diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index 2bf3f742d17656..26dba0225014f4 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -20,6 +20,7 @@ #include "llvm/ADT/StringSwitch.h" #include "llvm/TargetParser/Triple.h" #include "llvm/Support/Compiler.h" +#include "llvm/TargetParser/XtensaTargetParser.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/MacroBuilder.h" @@ -30,6 +31,8 @@ namespace targets { class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { std::string CPU; + bool HasFP = false; + bool HasWindowed = false; public: XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &) @@ -93,19 +96,25 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { } bool isValidCPUName(StringRef Name) const override { - return llvm::StringSwitch(Name) - .Case("esp32", true) - .Case("esp8266", true) - .Case("esp32-s2", true) - .Case("esp32-s3", true) - .Case("generic", true) - .Default(false); + return llvm::Xtensa::parseCPUKind(Name) != llvm::Xtensa::CK_INVALID; } bool setCPU(const std::string &Name) override { CPU = Name; return isValidCPUName(Name); } + + void fillValidCPUList(SmallVectorImpl &Values) const override; + + bool + initFeatureMap(llvm::StringMap &Features, DiagnosticsEngine &Diags, + StringRef CPU, + const std::vector &FeaturesVec) const override; + + bool hasFeature(StringRef Feature) const override; + + bool handleTargetFeatures(std::vector &Features, + DiagnosticsEngine &Diags) override; }; } // namespace targets } // namespace clang diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 9cb70ed885a3ac..03558f150aa9e3 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -23,6 +23,7 @@ #include "Hexagon.h" #include "MSP430.h" #include "Solaris.h" +#include "Xtensa.h" #include "clang/Basic/CharInfo.h" #include "clang/Basic/CodeGenOptions.h" #include "clang/Basic/LangOptions.h" @@ -712,6 +713,9 @@ void tools::getTargetFeatures(const Driver &D, const llvm::Triple &Triple, case llvm::Triple::loongarch64: loongarch::getLoongArchTargetFeatures(D, Triple, Args, Features); break; + case llvm::Triple::xtensa: + xtensa::getXtensaTargetFeatures(D, Triple, Args, Features); + break; } for (auto Feature : unifyTargetFeatures(Features)) { diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index 50c3f1563d1e7c..6d25895aeba64e 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -22,6 +22,7 @@ #include "llvm/Option/ArgList.h" #include "llvm/Support/Path.h" #include "llvm/Support/VirtualFileSystem.h" +#include "llvm/TargetParser/XtensaTargetParser.h" #include using namespace clang::driver; @@ -44,9 +45,9 @@ XtensaGCCToolchainDetector::XtensaGCCToolchainDetector( if (CPUName.equals("esp32")) ToolchainName = "xtensa-esp32-elf"; - else if (CPUName.equals("esp32-s2")) + else if (CPUName.equals("esp32-s2") || CPUName.equals("esp32s2")) ToolchainName = "xtensa-esp32s2-elf"; - else if (CPUName.equals("esp32-s3")) + else if (CPUName.equals("esp32-s3") || CPUName.equals("esp32s3")) ToolchainName = "xtensa-esp32s3-elf"; else if (CPUName.equals("esp8266")) ToolchainName = "xtensa-lx106-elf"; @@ -157,11 +158,11 @@ XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, } Tool *XtensaToolChain::buildLinker() const { - return new tools::Xtensa::Linker(*this); + return new tools::xtensa::Linker(*this); } Tool *XtensaToolChain::buildAssembler() const { - return new tools::Xtensa::Assembler(*this); + return new tools::xtensa::Assembler(*this); } void XtensaToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, @@ -226,7 +227,7 @@ const StringRef XtensaToolChain::GetTargetCPUVersion(const ArgList &Args) { return "esp32"; } -void tools::Xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, +void tools::xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, const InputInfo &Output, const InputInfoList &Inputs, const ArgList &Args, @@ -270,7 +271,7 @@ void tools::Xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, JA, *this, ResponseFileSupport::AtFileCurCP(), Asm, CmdArgs, Inputs)); } -void Xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, +void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, const InputInfo &Output, const InputInfoList &Inputs, const ArgList &Args, @@ -303,3 +304,32 @@ void Xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), Args.MakeArgString(Linker), CmdArgs, Inputs)); } + +// Get features by CPU name +static void getXtensaFeaturesFromMcpu(const Driver &D, + const llvm::opt::ArgList &Args, + const llvm::opt::Arg *A, StringRef Mcpu, + std::vector &Features) { + if (llvm::Xtensa::parseCPUKind(Mcpu) == llvm::Xtensa::CK_INVALID) { + D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args); + } else { + SmallVector CPUFeatures; + llvm::Xtensa::getCPUFeatures(Mcpu, CPUFeatures); + for (auto &F : CPUFeatures) { + Features.push_back(F); + } + } +} + +// Xtensa target features. +void xtensa::getXtensaTargetFeatures(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + std::vector &Features) { + if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) + getXtensaFeaturesFromMcpu(D, Args, A, A->getValue(), Features); + + // Now add any that the user explicitly requested on the command line, + // which may override the defaults. + handleTargetFeaturesGroup(D, Triple, Args, Features, + options::OPT_m_xtensa_Features_Group); +} diff --git a/clang/lib/Driver/ToolChains/Xtensa.h b/clang/lib/Driver/ToolChains/Xtensa.h index 663dc63f6d2795..f040a7d333c916 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.h +++ b/clang/lib/Driver/ToolChains/Xtensa.h @@ -61,7 +61,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaToolChain : public Generic_ELF { } // end namespace toolchains namespace tools { -namespace Xtensa { +namespace xtensa { class LLVM_LIBRARY_VISIBILITY Linker : public Tool { public: Linker(const ToolChain &TC) @@ -86,7 +86,10 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -} // end namespace Xtensa +void getXtensaTargetFeatures(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + std::vector &Features); +} // end namespace xtensa } // end namespace tools } // end namespace driver } // end namespace clang diff --git a/clang/test/Driver/xtensa-cpus.c b/clang/test/Driver/xtensa-cpus.c new file mode 100644 index 00000000000000..7a93f4cba4b0c8 --- /dev/null +++ b/clang/test/Driver/xtensa-cpus.c @@ -0,0 +1,36 @@ +// Check target CPUs are correctly passed. + +// RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp8266 | FileCheck -check-prefix=MCPU-ESP8266 %s +// MCPU-ESP8266: "-target-cpu" "esp8266" +// MCPU-ESP8266: "-target-feature" "+density" "-target-feature" "+nsa" "-target-feature" "+mul32" "-target-feature" "+extendedl32r" +// MCPU-ESP8266: "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts" +// MCPU-ESP8266: "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint" "-target-feature" "+prid" +// MCPU-ESP8266: "-target-feature" "+regprotect" + +// RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32 | FileCheck -check-prefix=MCPU-ESP32 %s +// MCPU-ESP32: "-target-cpu" "esp32" +// MCPU-ESP32: "-target-feature" "+density" "-target-feature" "+fp" "-target-feature" "+windowed" "-target-feature" "+bool" +// MCPU-ESP32: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+mul32" +// MCPU-ESP32: "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+mac16" "-target-feature" "+dfpaccel" +// MCPU-ESP32: "-target-feature" "+s32c1i" "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl" +// MCPU-ESP32: "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts" +// MCPU-ESP32: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint" +// MCPU-ESP32: "-target-feature" "+prid" "-target-feature" "+regprotect" "-target-feature" "+miscsr" + +// RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32s2 | FileCheck -check-prefix=MCPU-ESP32S2 %s +// MCPU-ESP32S2: "-target-cpu" "esp32s2" +// MCPU-ESP32S2: "-target-feature" "+density" "-target-feature" "+windowed" "-target-feature" "+sext" "-target-feature" "+nsa" +// MCPU-ESP32S2: "-target-feature" "+mul32" "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+threadptr" +// MCPU-ESP32S2: "-target-feature" "+memctl" "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts" +// MCPU-ESP32S2: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint" +// MCPU-ESP32S2: "-target-feature" "+prid" "-target-feature" "+regprotect" "-target-feature" "+miscsr" "-target-feature" "+esp32s2" + +// RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32s3 | FileCheck -check-prefix=MCPU-ESP32S3 %s +// MCPU-ESP32S3: "-target-cpu" "esp32s3" +// MCPU-ESP32S3: "-target-feature" "+density" "-target-feature" "+fp" "-target-feature" "+windowed" "-target-feature" "+bool" +// MCPU-ESP32S3: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+mul32" +// MCPU-ESP32S3: "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+mac16" "-target-feature" "+dfpaccel" +// MCPU-ESP32S3: "-target-feature" "+s32c1i" "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl" +// MCPU-ESP32S3: "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts" +// MCPU-ESP32S3: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint" +// MCPU-ESP32S3: "-target-feature" "+prid" "-target-feature" "+regprotect" "-target-feature" "+miscsr" "-target-feature" "+esp32s3" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 39ed02f50950dd..dc81fd74c7e5ec 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -94,3 +94,7 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' // TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} + +// RUN: not %clang_cc1 -triple xtensa -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-XTENSA +// TUNE-XTENSA: error: unknown target CPU 'not-a-cpu' +// TUNE-XTENSA: note: valid target CPU values are: generic, esp8266, esp32, esp32s2, esp32-s2, esp32s3, esp32-s3 diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.def b/llvm/include/llvm/TargetParser/XtensaTargetParser.def new file mode 100644 index 00000000000000..e46020700f2e2a --- /dev/null +++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.def @@ -0,0 +1,83 @@ +//===- XtensaTargetParser.def - Xtensa target parsing defines ---*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file provides defines to build up the Xtensa target parser's logic. +// +//===----------------------------------------------------------------------===// + +#ifndef XTENSA_FEATURE +#define XTENSA_FEATURE(ID, STR) +#endif + +XTENSA_FEATURE(FK_DENSITY, "density") +XTENSA_FEATURE(FK_FP, "fp") +XTENSA_FEATURE(FK_WINDOWED, "windowed") +XTENSA_FEATURE(FK_BOOLEAN, "bool") +XTENSA_FEATURE(FK_LOOP, "loop") +XTENSA_FEATURE(FK_SEXT, "sext") +XTENSA_FEATURE(FK_NSA, "nsa") +XTENSA_FEATURE(FK_MUL32, "mul32") +XTENSA_FEATURE(FK_MUL32HIGH, "mul32high") +XTENSA_FEATURE(FK_DIV32, "div32") +XTENSA_FEATURE(FK_MAC16, "mac16") +XTENSA_FEATURE(FK_DFPACCEL, "dfpaccel") +XTENSA_FEATURE(FK_S32C1I, "s32c1i") +XTENSA_FEATURE(FK_THREADPTR, "threadptr") +XTENSA_FEATURE(FK_EXTENDEDL32R, "extendedl32r") +XTENSA_FEATURE(FK_ATOMCTL, "atomctl") +XTENSA_FEATURE(FK_MEMCTL, "memctl") +XTENSA_FEATURE(FK_DEBUG, "debug") +XTENSA_FEATURE(FK_EXCEPTION, "exception") +XTENSA_FEATURE(FK_HIGHPRIINTERRUPTS, "highpriinterrupts") +XTENSA_FEATURE(FK_COPROCESSOR, "coprocessor") +XTENSA_FEATURE(FK_INTERRUPT, "interrupt") +XTENSA_FEATURE(FK_RVECTOR, "rvector") +XTENSA_FEATURE(FK_TIMERINT, "timerint") +XTENSA_FEATURE(FK_PRID, "prid") +XTENSA_FEATURE(FK_REGPROTECT, "regprotect") +XTENSA_FEATURE(FK_MISCSR, "miscsr") +XTENSA_FEATURE(FK_ESP32S2OPS, "esp32s2") +XTENSA_FEATURE(FK_ESP32S3OPS, "esp32s3") + +#undef XTENSA_FEATURE + +#ifndef XTENSA_CPU +#define XTENSA_CPU(ENUM, NAME, FEATURES) +#endif + +XTENSA_CPU(INVALID, {"invalid"}, FK_INVALID) +XTENSA_CPU(GENERIC, {"generic"}, FK_NONE) +XTENSA_CPU(ESP8266, {"esp8266"}, + (FK_DENSITY | FK_NSA | FK_MUL32 | FK_EXTENDEDL32R | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | + FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_REGPROTECT | FK_PRID)) +XTENSA_CPU(ESP32, {"esp32"}, + (FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN | + FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | FK_THREADPTR | FK_DIV32 | + FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | + FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR)) +XTENSA_CPU(ESP32S2, {"esp32s2"}, + (FK_DENSITY | FK_WINDOWED | FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_THREADPTR | FK_DIV32 | + FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | FK_INTERRUPT | + FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S2OPS)) +XTENSA_CPU(ESP32S3, {"esp32s3"}, + (FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN | + FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | FK_THREADPTR | FK_DIV32 | + FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | + FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | + FK_ESP32S3OPS)) + +#undef XTENSA_CPU + +#ifndef XTENSA_CPU_ALIAS +#define XTENSA_CPU_ALIAS(NAME, ALTNMAME) +#endif + +XTENSA_CPU_ALIAS("esp32s2", "esp32-s2") +XTENSA_CPU_ALIAS("esp32s3", "esp32-s3") + +#undef XTENSA_CPU_ALIAS diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.h b/llvm/include/llvm/TargetParser/XtensaTargetParser.h new file mode 100644 index 00000000000000..b2d642b2d63ef5 --- /dev/null +++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.h @@ -0,0 +1,71 @@ +//==-- XtensaTargetParser - Parser for Xtensa features --*- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements a target parser to recognise Xtensa hardware features +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TARGETPARSER_XTENSATARGETPARSER_H +#define LLVM_TARGETPARSER_XTENSATARGETPARSER_H + +#include "llvm/TargetParser/Triple.h" +#include + +namespace llvm { +class StringRef; + +namespace Xtensa { + +enum CPUKind : unsigned { +#define XTENSA_CPU(ENUM, NAME, FEATURES) CK_##ENUM, +#include "XtensaTargetParser.def" +}; + +enum FeatureKind : uint64_t { + FK_INVALID = 0, + FK_NONE = 1, + FK_FP = 1 << 1, + FK_WINDOWED = 1 << 2, + FK_BOOLEAN = 1 << 3, + FK_DENSITY = 1 << 4, + FK_LOOP = 1 << 5, + FK_SEXT = 1 << 6, + FK_NSA = 1 << 7, + FK_MUL32 = 1 << 8, + FK_MUL32HIGH = 1 << 9, + FK_DIV32 = 1 << 10, + FK_MAC16 = 1 << 11, + FK_DFPACCEL = 1 << 12, + FK_S32C1I = 1 << 13, + FK_THREADPTR = 1 << 14, + FK_EXTENDEDL32R = 1 << 15, + FK_ATOMCTL = 1 << 16, + FK_MEMCTL = 1 << 17, + FK_DEBUG = 1 << 18, + FK_EXCEPTION = 1 << 19, + FK_HIGHPRIINTERRUPTS = 1 << 20, + FK_COPROCESSOR = 1 << 21, + FK_INTERRUPT = 1 << 22, + FK_RVECTOR = 1 << 23, + FK_TIMERINT = 1 << 24, + FK_PRID = 1 << 25, + FK_REGPROTECT = 1 << 26, + FK_MISCSR = 1 << 27, + FK_ESP32S2OPS = 1 << 28, + FK_ESP32S3OPS = 1 << 29 +}; + +CPUKind parseCPUKind(StringRef CPU); +StringRef getBaseName(StringRef CPU); +void getCPUFeatures(StringRef CPU, SmallVectorImpl &Features); +void fillValidCPUList(SmallVectorImpl &Values); + +} // namespace Xtensa +} // namespace llvm + +#endif // LLVM_SUPPORT_XTENSATARGETPARSER_H diff --git a/llvm/include/module.modulemap b/llvm/include/module.modulemap index 8930fa8c087cf4..29c9195896805f 100644 --- a/llvm/include/module.modulemap +++ b/llvm/include/module.modulemap @@ -401,6 +401,7 @@ module LLVM_Utils { textual header "llvm/TargetParser/CSKYTargetParser.def" textual header "llvm/TargetParser/X86TargetParser.def" textual header "llvm/TargetParser/LoongArchTargetParser.def" + textual header "TargetParser/XtensaTargetParser.def" } // This part of the module is usable from both C and C++ code. diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 4267393005ce00..9d7bb37fa6add0 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -934,8 +934,8 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { unsigned NumTimers = 0; unsigned NumMiscSR = 0; bool IsESP32 = false; - bool IsESP32_S2 = false; - bool IsESP32_S3 = false; + bool IsESP32S2 = false; + bool IsESP32S3 = false; bool Res = true; // Assume that CPU is esp32 by default @@ -944,16 +944,16 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { NumTimers = 3; NumMiscSR = 4; IsESP32 = true; - } else if (CPU == "esp32-s2") { + } else if (CPU == "esp32s2") { NumIntLevels = 6; NumTimers = 3; NumMiscSR = 4; - IsESP32_S2 = true; - } else if (CPU == "esp32-s3") { + IsESP32S2 = true; + } else if (CPU == "esp32s3") { NumIntLevels = 6; NumTimers = 3; NumMiscSR = 4; - IsESP32_S3 = true; + IsESP32S3 = true; } else if (CPU == "esp8266") { NumIntLevels = 2; NumTimers = 1; @@ -1077,7 +1077,7 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { Res = hasTHREADPTR(); break; case Xtensa::GPIO_OUT: - Res = IsESP32_S2 || IsESP32_S3; + Res = IsESP32S2 || IsESP32S3; break; case Xtensa::EXPSTATE: Res = IsESP32; diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 11e71fe8b0922b..a55a13340075bd 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -154,7 +154,7 @@ bool CheckRegister(unsigned RegNo, MCSubtargetInfo STI) { unsigned NumTimers = 0; unsigned NumMiscSR = 0; bool IsESP32 = false; - bool IsESP32_S2 = false; + bool IsESP32S2 = false; bool Res = true; // Assume that CPU is esp32 by default @@ -163,11 +163,11 @@ bool CheckRegister(unsigned RegNo, MCSubtargetInfo STI) { NumTimers = 3; NumMiscSR = 4; IsESP32 = true; - } else if (CPU == "esp32-s2") { + } else if (CPU == "esp32s2") { NumIntLevels = 6; NumTimers = 3; NumMiscSR = 4; - IsESP32_S2 = true; + IsESP32S2 = true; } else if (CPU == "esp8266") { NumIntLevels = 2; NumTimers = 1; @@ -291,7 +291,7 @@ bool CheckRegister(unsigned RegNo, MCSubtargetInfo STI) { Res = STI.getFeatureBits()[Xtensa::FeatureTHREADPTR]; break; case Xtensa::GPIO_OUT: - Res = IsESP32_S2; + Res = IsESP32S2; break; case Xtensa::EXPSTATE: Res = IsESP32; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp index ffb26e566709f9..7876af4fde1125 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp @@ -67,6 +67,10 @@ static MCSubtargetInfo * createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { if (CPU.empty()) CPU = "esp32"; + else if (CPU == "esp32-s2") + CPU = "esp32s2"; + else if (CPU == "esp32-s3") + CPU = "esp32s3"; return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS); } diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index dd4b484aa6bad1..363bb45a72f76b 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -184,15 +184,15 @@ def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>; -def : Proc<"esp32-s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, - FeatureDiv32, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, - FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureESP32S2Ops]>; - -def : Proc<"esp32-s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT, - FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, - FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, - FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, - FeatureESP32S3Ops]>; +def : Proc<"esp32s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, + FeatureDiv32, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, + FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureESP32S2Ops]>; + +def : Proc<"esp32s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, + FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, + FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, + FeatureESP32S3Ops]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index cf4acabd088530..faa0f950ee6082 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -49,6 +49,16 @@ static std::unique_ptr createTLOF() { return std::make_unique(); } +static StringRef getCPUName(StringRef CPU) { + if (CPU.empty()) + CPU = "esp32"; + else if (CPU == "esp32-s2") + CPU = "esp32s2"; + else if (CPU == "esp32-s3") + CPU = "esp32s3"; + return CPU; +} + XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -70,7 +80,7 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : XtensaTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} + : XtensaTargetMachine(T, TT, getCPUName(CPU), FS, Options, RM, CM, OL, JIT, true) {} const XtensaSubtarget * XtensaTargetMachine::getSubtargetImpl(const Function &F) const { diff --git a/llvm/lib/TargetParser/CMakeLists.txt b/llvm/lib/TargetParser/CMakeLists.txt index da1e352b037338..5c988a50d8706f 100644 --- a/llvm/lib/TargetParser/CMakeLists.txt +++ b/llvm/lib/TargetParser/CMakeLists.txt @@ -25,6 +25,7 @@ add_llvm_component_library(LLVMTargetParser TargetParser.cpp Triple.cpp X86TargetParser.cpp + XtensaTargetParser.cpp ADDITIONAL_HEADER_DIRS Unix diff --git a/llvm/lib/TargetParser/XtensaTargetParser.cpp b/llvm/lib/TargetParser/XtensaTargetParser.cpp new file mode 100644 index 00000000000000..c3cc59ed84bc04 --- /dev/null +++ b/llvm/lib/TargetParser/XtensaTargetParser.cpp @@ -0,0 +1,93 @@ +//==-- XtensaTargetParser - Parser for Xtensa features ------------*- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements a target parser to recognise Xtensa hardware features +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/TargetParser/XtensaTargetParser.h" + +namespace llvm { + +namespace Xtensa { +struct CPUInfo { + StringLiteral Name; + CPUKind Kind; + uint64_t Features; +}; + +struct FeatureName { + uint64_t ID; + const char *NameCStr; + size_t NameLength; + + StringRef getName() const { return StringRef(NameCStr, NameLength); } +}; + +const FeatureName XtensaFeatureNames[] = { +#define XTENSA_FEATURE(ID, NAME) {ID, "+" NAME, sizeof(NAME)}, +#include "llvm/TargetParser/XtensaTargetParser.def" +}; + +constexpr CPUInfo XtensaCPUInfo[] = { +#define XTENSA_CPU(ENUM, NAME, FEATURES) {NAME, CK_##ENUM, FEATURES}, +#include "llvm/TargetParser/XtensaTargetParser.def" +}; + +StringRef getBaseName(StringRef CPU){ + return llvm::StringSwitch(CPU) +#define XTENSA_CPU_ALIAS(NAME, ANAME) .Case(ANAME, NAME) +#include "llvm/TargetParser/XtensaTargetParser.def" + .Default(CPU); +} + +StringRef getAliasName(StringRef CPU){ + return llvm::StringSwitch(CPU) +#define XTENSA_CPU_ALIAS(NAME, ANAME) .Case(NAME, ANAME) +#include "llvm/TargetParser/XtensaTargetParser.def" + .Default(CPU); +} + +CPUKind parseCPUKind(StringRef CPU) { + CPU = getBaseName(CPU); + return llvm::StringSwitch(CPU) +#define XTENSA_CPU(ENUM, NAME, FEATURES) .Case(NAME, CK_##ENUM) +#include "llvm/TargetParser/XtensaTargetParser.def" + .Default(CK_INVALID); +} + +//Get all features for the CPU +void getCPUFeatures(StringRef CPU, SmallVectorImpl &Features) { + CPU = getBaseName(CPU); + auto I = llvm::find_if(XtensaCPUInfo, + [&](const CPUInfo &CI) { return CI.Name == CPU; }); + assert(I != std::end(XtensaCPUInfo) && "CPU not found!"); + uint64_t Bits = I->Features; + + for (const auto &F : XtensaFeatureNames) { + if ((Bits & F.ID) == F.ID) + Features.push_back(F.getName()); + } +} + +//Find all valid CPUs +void fillValidCPUList(SmallVectorImpl &Values) { + for (const auto &C : XtensaCPUInfo) { + if (C.Kind != CK_INVALID) { + Values.emplace_back(C.Name); + StringRef Name = getAliasName(C.Name); + if (Name != C.Name) + Values.emplace_back(Name); + } + } +} + +} // namespace Xtensa +} // namespace llvm diff --git a/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn index 1a91bb7e6fa9f5..aaceb3f964e6b4 100644 --- a/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn @@ -18,5 +18,6 @@ static_library("TargetParser") { "TargetParser.cpp", "Triple.cpp", "X86TargetParser.cpp", + "XtensaTargetParser.cpp", ] } From b4bcd1345bb0f701453ed4c2bc87e12f7d3772ec Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:57 +0300 Subject: [PATCH 079/261] [Xtensa] Improve Xtensa multilib support in clang. Use GCCInstallationDetector in Xtensa toolchain instead of XtensaGCCToolchainDetector for initialization of the gcc environment. Add xtensa toolchain test tree with multilib subdirectories. --- clang/lib/Driver/ToolChains/Gnu.cpp | 46 ++++- clang/lib/Driver/ToolChains/Xtensa.cpp | 179 ++++++------------ clang/lib/Driver/ToolChains/Xtensa.h | 23 +-- .../bin/xtensa-esp32-elf-ld | 1 + .../lib/gcc/xtensa-esp32-elf/8.4.0/crtbegin.o | 0 .../lib/gcc/xtensa-esp32-elf/8.4.0/crtend.o | 0 .../8.4.0/esp32-psram/crtbegin.o | 0 .../8.4.0/esp32-psram/crtend.o | 0 .../8.4.0/esp32-psram/no-rtti/crtbegin.o | 0 .../8.4.0/esp32-psram/no-rtti/crtend.o | 0 .../xtensa-esp32-elf/8.4.0/no-rtti/crtbegin.o | 0 .../xtensa-esp32-elf/8.4.0/no-rtti/crtend.o | 0 .../xtensa-esp32-elf/lib/crt0.o | 0 .../xtensa-esp32-elf/lib/esp32-psram/crt0.o | 0 .../lib/esp32-psram/no-rtti/crt0.o | 0 .../xtensa-esp32-elf/lib/no-rtti/crt0.o | 0 clang/test/Driver/xtensa-toolchain.c | 42 ++++ 17 files changed, 150 insertions(+), 141 deletions(-) create mode 100755 clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/no-rtti/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/no-rtti/crt0.o create mode 100644 clang/test/Driver/xtensa-toolchain.c diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index b5befefe6d29ef..b8c07b66926455 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1938,6 +1938,46 @@ static void findRISCVMultilibs(const Driver &D, Result.Multilibs = RISCVMultilibs; } +static void findXtensaMultilibs(const Driver &D, + const llvm::Triple &TargetTriple, StringRef Path, + const ArgList &Args, DetectedMultilibs &Result) { + + MultilibSet XtensaMultilibs = MultilibSet(); + bool IsESP32 = Args.getLastArgValue(options::OPT_mcpu_EQ, "esp32").equals("esp32"); + + XtensaMultilibs.push_back(Multilib()); + if (IsESP32) + XtensaMultilibs.push_back(MultilibBuilder("esp32-psram", {}, {}) + .flag("-mfix-esp32-psram-cache-issue") + .makeMultilib()); + + XtensaMultilibs.push_back(MultilibBuilder("no-rtti", {}, {}) + .flag("-frtti", /*Disallow=*/true) + .flag("-fno-rtti") + .makeMultilib()); + + if (IsESP32) + XtensaMultilibs.push_back(MultilibBuilder("esp32-psram/no-rtti", {}, {}) + .flag("-fno-rtti") + .flag("-frtti", /*Disallow=*/true) + .flag("-mfix-esp32-psram-cache-issue") + .makeMultilib()); + + Multilib::flags_list Flags; + addMultilibFlag( + Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, false), "frtti", + Flags); + + if (IsESP32) + addMultilibFlag(Args.hasFlag(options::OPT_mfix_esp32_psram_cache_issue, + options::OPT_mfix_esp32_psram_cache_issue, + false), + "mfix-esp32-psram-cache-issue", Flags); + + if (XtensaMultilibs.select(Flags, Result.SelectedMultilibs)) + Result.Multilibs = XtensaMultilibs; +} + static bool findBiarchMultilibs(const Driver &D, const llvm::Triple &TargetTriple, StringRef Path, const ArgList &Args, @@ -2573,7 +2613,9 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( "s390x-suse-linux", "s390x-redhat-linux"}; static const char *const XtensaLibDirs[] = {"/lib"}; - static const char *const XtensaTriples[] = {"xtensa-unknown-elf"}; + static const char *const XtensaTriples[] = { + "xtensa-unknown-elf", "xtensa-esp32-elf", "xtensa-esp32s2-elf", + "xtensa-esp32s3-elf"}; using std::begin; using std::end; @@ -2884,6 +2926,8 @@ bool Generic_GCC::GCCInstallationDetector::ScanGCCForMultilibs( findMSP430Multilibs(D, TargetTriple, Path, Args, Detected); } else if (TargetArch == llvm::Triple::avr) { // AVR has no multilibs. + } else if (TargetArch == llvm::Triple::xtensa) { + findXtensaMultilibs(D, TargetTriple, Path, Args, Detected); } else if (!findBiarchMultilibs(D, TargetTriple, Path, Args, NeedsBiarchSuffix, Detected)) { return false; diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index 6d25895aeba64e..f73ab499f0b505 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -10,7 +10,6 @@ #include "Xtensa.h" #include "CommonArgs.h" -#include "clang/Driver/InputInfo.h" #include "clang/Basic/Cuda.h" #include "clang/Config/config.h" #include "clang/Driver/Compilation.h" @@ -33,58 +32,26 @@ using namespace llvm::opt; using tools::addMultilibFlag; -XtensaGCCToolchainDetector::XtensaGCCToolchainDetector( - const Driver &D, const llvm::Triple &HostTriple, - const llvm::opt::ArgList &Args) { - std::string InstalledDir; - InstalledDir = D.getInstalledDir(); - StringRef CPUName = XtensaToolChain::GetTargetCPUVersion(Args); - std::string Dir; - std::string ToolchainName; - std::string ToolchainDir; - - if (CPUName.equals("esp32")) - ToolchainName = "xtensa-esp32-elf"; - else if (CPUName.equals("esp32-s2") || CPUName.equals("esp32s2")) - ToolchainName = "xtensa-esp32s2-elf"; - else if (CPUName.equals("esp32-s3") || CPUName.equals("esp32s3")) - ToolchainName = "xtensa-esp32s3-elf"; - else if (CPUName.equals("esp8266")) - ToolchainName = "xtensa-lx106-elf"; - - Slash = llvm::sys::path::get_separator().str(); - - ToolchainDir = InstalledDir + Slash + ".."; - Dir = ToolchainDir + Slash + "lib" + Slash + "gcc" + Slash + ToolchainName + - Slash; - GCCLibAndIncVersion = ""; - - if (D.getVFS().exists(Dir)) { - std::error_code EC; - for (llvm::vfs::directory_iterator LI = D.getVFS().dir_begin(Dir, EC), LE; - !EC && LI != LE; LI = LI.increment(EC)) { - StringRef VersionText = llvm::sys::path::filename(LI->path()); - auto GCCVersion = Generic_GCC::GCCVersion::Parse(VersionText); - if (GCCVersion.Major == -1) - continue; - GCCLibAndIncVersion = GCCVersion.Text; - } - if (GCCLibAndIncVersion == "") - llvm_unreachable("Unexpected Xtensa GCC toolchain version"); - - } else { - // Unable to find Xtensa GCC toolchain; - GCCToolchainName = ""; - return; - } - GCCToolchainDir = ToolchainDir; - GCCToolchainName = ToolchainName; -} - /// Xtensa Toolchain XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) - : Generic_ELF(D, Triple, Args), XtensaGCCToolchain(D, getTriple(), Args) { + : Generic_ELF(D, Triple, Args) { + + GCCInstallation.init(Triple, Args); + + if (!GCCInstallation.isValid()) { + llvm_unreachable("Unexpected Xtensa GCC toolchain version"); + } + + Multilibs = GCCInstallation.getMultilibs(); + SelectedMultilibs.assign({GCCInstallation.getMultilib()}); + + GCCLibAndIncVersion = GCCInstallation.getVersion().Text; + GCCToolchainName = GCCInstallation.getTriple().str(); + SmallString<128> Path(GCCInstallation.getParentLibPath()); + llvm::sys::path::append(Path, ".."); + GCCToolchainDir = Path.c_str(); + for (auto *A : Args) { std::string Str = A->getAsString(Args); if (!Str.compare("-mlongcalls")) @@ -111,50 +78,18 @@ XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, IsIntegratedAsm = false; } - bool IsESP32 = XtensaToolChain::GetTargetCPUVersion(Args).equals("esp32"); - Multilibs.push_back(Multilib()); - - if (IsESP32) - Multilibs.push_back(MultilibBuilder("esp32-psram", {}, {}) - .flag("-mfix-esp32-psram-cache-issue") - .makeMultilib()); - - Multilibs.push_back(MultilibBuilder("no-rtti", {}, {}) - .flag("-frtti", /*Disallow=*/true) - .flag("-fno-rtti") - .makeMultilib()); - - if (IsESP32) - Multilibs.push_back(MultilibBuilder("esp32-psram/no-rtti", {}, {}) - .flag("-fno-rtti") - .flag("-frtti", /*Disallow=*/true) - .flag("-mfix-esp32-psram-cache-issue") - .makeMultilib()); - - Multilib::flags_list Flags; - addMultilibFlag( - Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, false), "frtti", - Flags); - - if (IsESP32) - addMultilibFlag(Args.hasFlag(options::OPT_mfix_esp32_psram_cache_issue, - options::OPT_mfix_esp32_psram_cache_issue, - false), - "mfix-esp32-psram-cache-issue", Flags); - - Multilibs.select(Flags, SelectedMultilibs); - - const std::string Slash = XtensaGCCToolchain.Slash; - std::string Libs = - XtensaGCCToolchain.GCCToolchainDir + Slash + "lib" + Slash + "gcc" + - Slash + XtensaGCCToolchain.GCCToolchainName + Slash + - XtensaGCCToolchain.GCCLibAndIncVersion + SelectedMultilibs.back().gccSuffix(); - getFilePaths().push_back(Libs); - - Libs = XtensaGCCToolchain.GCCToolchainDir + Slash + - XtensaGCCToolchain.GCCToolchainName + Slash + "lib" + - SelectedMultilibs.back().gccSuffix(); - getFilePaths().push_back(Libs); + SmallString<128> Libs1(GCCToolchainDir); + llvm::sys::path::append(Libs1, "lib", "gcc", GCCToolchainName, + GCCLibAndIncVersion); + if (!SelectedMultilibs.back().gccSuffix().empty()) + llvm::sys::path::append(Libs1, SelectedMultilibs.back().gccSuffix()); + getFilePaths().push_back(Libs1.c_str()); + + SmallString<128> Libs2(GCCToolchainDir); + llvm::sys::path::append(Libs2, GCCToolchainName, "lib"); + if (!SelectedMultilibs.back().gccSuffix().empty()) + llvm::sys::path::append(Libs2, SelectedMultilibs.back().gccSuffix()); + getFilePaths().push_back(Libs2.c_str()); } Tool *XtensaToolChain::buildLinker() const { @@ -171,17 +106,15 @@ void XtensaToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, DriverArgs.hasArg(options::OPT_nostdlibinc)) return; - if (!XtensaGCCToolchain.IsValid()) + if (!GCCInstallation.isValid()) return; - std::string Slash = XtensaGCCToolchain.Slash; - - std::string Path1 = getDriver().ResourceDir.c_str() + Slash + "include"; - std::string Path2 = XtensaGCCToolchain.GCCToolchainDir + Slash + - XtensaGCCToolchain.GCCToolchainName + Slash + - "sys-include"; - std::string Path3 = XtensaGCCToolchain.GCCToolchainDir + Slash + - XtensaGCCToolchain.GCCToolchainName + Slash + "include"; + SmallString<128> Path1(getDriver().ResourceDir); + llvm::sys::path::append(Path1, "include"); + SmallString<128> Path2(GCCToolchainDir); + llvm::sys::path::append(Path2, GCCToolchainName, "sys-include"); + SmallString<128> Path3(GCCToolchainDir); + llvm::sys::path::append(Path3, GCCToolchainName, "include"); const StringRef Paths[] = {Path1, Path2, Path3}; addSystemIncludes(DriverArgs, CC1Args, Paths); @@ -190,20 +123,20 @@ void XtensaToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, void XtensaToolChain::addLibStdCxxIncludePaths( const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const { - if (!XtensaGCCToolchain.IsValid()) + if (!GCCInstallation.isValid()) return; - std::string Slash = XtensaGCCToolchain.Slash; + SmallString<128> BaseDir(GCCToolchainDir); + llvm::sys::path::append(BaseDir, GCCToolchainName, "include", "c++", + GCCLibAndIncVersion); + SmallString<128> TargetDir(BaseDir); + llvm::sys::path::append(TargetDir, GCCToolchainName); + SmallString<128> TargetDirBackward(BaseDir); + llvm::sys::path::append(TargetDirBackward, "backward"); - std::string BaseDir = XtensaGCCToolchain.GCCToolchainDir + Slash + - XtensaGCCToolchain.GCCToolchainName + Slash + - "include" + Slash + "c++" + Slash + - XtensaGCCToolchain.GCCLibAndIncVersion; - std::string TargetDir = BaseDir + Slash + XtensaGCCToolchain.GCCToolchainName; addLibStdCXXIncludePaths(BaseDir, "", "", DriverArgs, CC1Args); addLibStdCXXIncludePaths(TargetDir, "", "", DriverArgs, CC1Args); - TargetDir = BaseDir + Slash + "backward"; - addLibStdCXXIncludePaths(TargetDir, "", "", DriverArgs, CC1Args); + addLibStdCXXIncludePaths(TargetDirBackward, "", "", DriverArgs, CC1Args); } ToolChain::CXXStdlibType @@ -235,7 +168,7 @@ void tools::xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, const auto &TC = static_cast(getToolChain()); - if (!TC.XtensaGCCToolchain.IsValid()) + if (TC.GCCToolchainName == "") llvm_unreachable("Unable to find Xtensa GCC assembler"); claimNoWarnArgs(Args); @@ -262,13 +195,13 @@ void tools::xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, for (const auto &II : Inputs) CmdArgs.push_back(II.getFilename()); - std::string Slash = TC.XtensaGCCToolchain.Slash; + SmallString<128> Asm(TC.GCCToolchainDir); + llvm::sys::path::append(Asm, "bin", + TC.GCCToolchainName + "-" + getShortName()); - const char *Asm = - Args.MakeArgString(getToolChain().getDriver().Dir + Slash + - TC.XtensaGCCToolchain.GCCToolchainName + "-as"); - C.addCommand(std::make_unique( - JA, *this, ResponseFileSupport::AtFileCurCP(), Asm, CmdArgs, Inputs)); + C.addCommand( + std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), + Args.MakeArgString(Asm), CmdArgs, Inputs)); } void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, @@ -278,13 +211,13 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, const char *LinkingOutput) const { const auto &TC = static_cast(getToolChain()); - std::string Slash = TC.XtensaGCCToolchain.Slash; - if (!TC.XtensaGCCToolchain.IsValid()) + if (TC.GCCToolchainName == "") llvm_unreachable("Unable to find Xtensa GCC linker"); - std::string Linker = getToolChain().getDriver().Dir + Slash + - TC.XtensaGCCToolchain.GCCToolchainName + "-ld"; + SmallString<128> Linker(TC.GCCToolchainDir); + llvm::sys::path::append(Linker, "bin", + TC.GCCToolchainName + "-" + getShortName()); ArgStringList CmdArgs; Args.AddAllArgs(CmdArgs, options::OPT_L); diff --git a/clang/lib/Driver/ToolChains/Xtensa.h b/clang/lib/Driver/ToolChains/Xtensa.h index f040a7d333c916..10fc87c90bc6ac 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.h +++ b/clang/lib/Driver/ToolChains/Xtensa.h @@ -20,19 +20,6 @@ namespace clang { namespace driver { namespace toolchains { -class XtensaGCCToolchainDetector { -public: - std::string GCCLibAndIncVersion; - std::string GCCToolchainName; - std::string GCCToolchainDir; - std::string Slash; - - XtensaGCCToolchainDetector(const Driver &D, const llvm::Triple &HostTriple, - const llvm::opt::ArgList &Args); - - bool IsValid() const { return GCCToolchainName != ""; } -}; - class LLVM_LIBRARY_VISIBILITY XtensaToolChain : public Generic_ELF { protected: Tool *buildLinker() const override; @@ -49,13 +36,15 @@ class LLVM_LIBRARY_VISIBILITY XtensaToolChain : public Generic_ELF { llvm::opt::ArgStringList &CC1Args) const override; CXXStdlibType GetCXXStdlibType(const llvm::opt::ArgList &Args) const override; bool IsIntegratedAssemblerDefault() const override { - return (IsIntegratedAsm || (XtensaGCCToolchain.GCCToolchainName == "")); + return (IsIntegratedAsm || (GCCToolchainName == "")); } static const StringRef GetTargetCPUVersion(const llvm::opt::ArgList &Args); - XtensaGCCToolchainDetector XtensaGCCToolchain; bool IsIntegratedAsm = true; + std::string GCCLibAndIncVersion = ""; + std::string GCCToolchainName = ""; + std::string GCCToolchainDir = ""; }; } // end namespace toolchains @@ -65,7 +54,7 @@ namespace xtensa { class LLVM_LIBRARY_VISIBILITY Linker : public Tool { public: Linker(const ToolChain &TC) - : Tool("Xtensa::Linker", "xtensa-esp32-elf-ld", TC) {} + : Tool("Xtensa::Linker", "ld", TC) {} bool hasIntegratedCPP() const override { return false; } bool isLinkJob() const override { return true; } void ConstructJob(Compilation &C, const JobAction &JA, @@ -77,7 +66,7 @@ class LLVM_LIBRARY_VISIBILITY Linker : public Tool { class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { public: Assembler(const ToolChain &TC) - : Tool("Xtensa::Assembler", "xtensa-esp32-elf-as", TC) {} + : Tool("Xtensa::Assembler", "as", TC) {} bool hasIntegratedCPP() const override { return false; } void ConstructJob(Compilation &C, const JobAction &JA, diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld b/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/no-rtti/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/no-rtti/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/xtensa-toolchain.c b/clang/test/Driver/xtensa-toolchain.c new file mode 100644 index 00000000000000..245e09902f0f8c --- /dev/null +++ b/clang/test/Driver/xtensa-toolchain.c @@ -0,0 +1,42 @@ +// A basic clang -cc1 command-line, and simple environment check. + +// RUN: %clang %s -### -no-canonical-prefixes -target xtensa \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=CC1 %s +// CC1: clang{{.*}} "-cc1" "-triple" "xtensa" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL %s + +// C-XTENSA-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" +// C-XTENSA-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -frtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-RTTI %s + +// C-XTENSA-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" +// C-XTENSA-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-PSRAM %s + +// C-XTENSA-BAREMETAL-PSRAM: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram/no-rtti" +// C-XTENSA-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram/no-rtti" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue -frtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-PSRAM-RTTI %s + +// C-XTENSA-BAREMETAL-PSRAM-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-BAREMETAL-PSRAM-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram" +// C-XTENSA-BAREMETAL-PSRAM-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram" From 06a3c81774e8972cb32d6f3d35cae01bba1a442d Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:57 +0300 Subject: [PATCH 080/261] [Xtensa] Add '--rtlib' option support for ESP Xtensa toolchain --- clang/lib/Driver/ToolChains/Xtensa.cpp | 62 ++++++++++++++++++++------ clang/lib/Driver/ToolChains/Xtensa.h | 2 + 2 files changed, 50 insertions(+), 14 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index f73ab499f0b505..f23da72ec434f6 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -152,6 +152,11 @@ XtensaToolChain::GetCXXStdlibType(const ArgList &Args) const { return ToolChain::CST_Libstdcxx; } +ToolChain::UnwindLibType +XtensaToolChain::GetUnwindLibType(const llvm::opt::ArgList &Args) const { + return ToolChain::UNW_None; +} + const StringRef XtensaToolChain::GetTargetCPUVersion(const ArgList &Args) { if (Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ)) { StringRef CPUName = A->getValue(); @@ -209,33 +214,62 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const auto &TC = - static_cast(getToolChain()); + ArgStringList CmdArgs; + bool WantCRTs = + !Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles); + const auto &ToolChain = + static_cast(getToolChain()); - if (TC.GCCToolchainName == "") + if (ToolChain.GCCToolchainName == "") llvm_unreachable("Unable to find Xtensa GCC linker"); - SmallString<128> Linker(TC.GCCToolchainDir); + SmallString<128> Linker(ToolChain.GCCToolchainDir); llvm::sys::path::append(Linker, "bin", - TC.GCCToolchainName + "-" + getShortName()); - ArgStringList CmdArgs; + ToolChain.GCCToolchainName + "-" + getShortName()); - Args.AddAllArgs(CmdArgs, options::OPT_L); - TC.AddFilePathLibArgs(Args, CmdArgs); + const char *crtbegin, *crtend; + auto RuntimeLib = ToolChain.GetRuntimeLibType(Args); + if (RuntimeLib == ToolChain::RLT_Libgcc) { + crtbegin = "crtbegin.o"; + crtend = "crtend.o"; + } else { + assert (RuntimeLib == ToolChain::RLT_CompilerRT); + crtbegin = ToolChain.getCompilerRTArgString(Args, "crtbegin", + ToolChain::FT_Object); + crtend = ToolChain.getCompilerRTArgString(Args, "crtend", + ToolChain::FT_Object); + } + if (WantCRTs) { + // TODO: The crt0.o is not used for esp targets, but maybe used in + // future for other vendors + //CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin))); + } + + AddLinkerInputs(getToolChain(), Inputs, Args, CmdArgs, JA); + + Args.AddAllArgs(CmdArgs, options::OPT_L); + ToolChain.AddFilePathLibArgs(Args, CmdArgs); Args.addAllArgs(CmdArgs, {options::OPT_T_Group, options::OPT_e, options::OPT_s, options::OPT_t, options::OPT_u_Group}); + + if (!Args.hasArg(options::OPT_nostdlib) && + !Args.hasArg(options::OPT_nodefaultlibs)) { + if (ToolChain.ShouldLinkCXXStdlib(Args)) + ToolChain.AddCXXStdlibLibArgs(Args, CmdArgs); + AddRunTimeLibs(ToolChain, ToolChain.getDriver(), CmdArgs, Args); + } - AddLinkerInputs(getToolChain(), Inputs, Args, CmdArgs, JA); - - CmdArgs.push_back("-lgcc"); + if (WantCRTs) + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtend))); CmdArgs.push_back("-o"); CmdArgs.push_back(Output.getFilename()); - C.addCommand( - std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), - Args.MakeArgString(Linker), CmdArgs, Inputs)); + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), Args.MakeArgString(Linker), + CmdArgs, Inputs)); } // Get features by CPU name diff --git a/clang/lib/Driver/ToolChains/Xtensa.h b/clang/lib/Driver/ToolChains/Xtensa.h index 10fc87c90bc6ac..38f8f1b2c8d5f9 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.h +++ b/clang/lib/Driver/ToolChains/Xtensa.h @@ -35,6 +35,8 @@ class LLVM_LIBRARY_VISIBILITY XtensaToolChain : public Generic_ELF { addLibStdCxxIncludePaths(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; CXXStdlibType GetCXXStdlibType(const llvm::opt::ArgList &Args) const override; + UnwindLibType GetUnwindLibType(const llvm::opt::ArgList &Args) const override; + bool IsIntegratedAssemblerDefault() const override { return (IsIntegratedAsm || (GCCToolchainName == "")); } From 718d1a51048e19126e9c37874c74d7b448924684 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:57 +0300 Subject: [PATCH 081/261] [Xtensa]: Add '-fuse-ld' option support to ESP Xtensa toolchain --- clang/lib/Driver/ToolChains/Xtensa.cpp | 11 ++++++++--- clang/test/Driver/xtensa-toolchain.c | 8 ++++---- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index f23da72ec434f6..aaf1ab90f71c10 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -215,6 +215,7 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, const ArgList &Args, const char *LinkingOutput) const { ArgStringList CmdArgs; + SmallString<128> Linker; bool WantCRTs = !Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles); const auto &ToolChain = @@ -223,9 +224,13 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (ToolChain.GCCToolchainName == "") llvm_unreachable("Unable to find Xtensa GCC linker"); - SmallString<128> Linker(ToolChain.GCCToolchainDir); - llvm::sys::path::append(Linker, "bin", - ToolChain.GCCToolchainName + "-" + getShortName()); + if (Args.hasArg(options::OPT_fuse_ld_EQ)) { + Linker.assign(ToolChain.GetLinkerPath()); + } else { + Linker.assign(ToolChain.GCCToolchainDir); + llvm::sys::path::append(Linker, "bin", + ToolChain.GCCToolchainName + "-" + getShortName()); + } const char *crtbegin, *crtend; auto RuntimeLib = ToolChain.GetRuntimeLibType(Args); diff --git a/clang/test/Driver/xtensa-toolchain.c b/clang/test/Driver/xtensa-toolchain.c index 245e09902f0f8c..0570c1d0f0b571 100644 --- a/clang/test/Driver/xtensa-toolchain.c +++ b/clang/test/Driver/xtensa-toolchain.c @@ -5,7 +5,7 @@ // RUN: | FileCheck -check-prefix=CC1 %s // CC1: clang{{.*}} "-cc1" "-triple" "xtensa" -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: %clang %s -### -no-canonical-prefixes \ // RUN: -target xtensa --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL %s @@ -14,7 +14,7 @@ // C-XTENSA-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" // C-XTENSA-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: %clang %s -### -no-canonical-prefixes \ // RUN: -target xtensa --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -frtti 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-RTTI %s @@ -23,7 +23,7 @@ // C-XTENSA-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" // C-XTENSA-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: %clang %s -### -no-canonical-prefixes \ // RUN: -target xtensa --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-PSRAM %s @@ -32,7 +32,7 @@ // C-XTENSA-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram/no-rtti" // C-XTENSA-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram/no-rtti" -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: %clang %s -### -no-canonical-prefixes \ // RUN: -target xtensa --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue -frtti 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-PSRAM-RTTI %s From 8d1bc2c47247b3e2c91e4a3ec5dba1572c4fb3bc Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:58 +0300 Subject: [PATCH 082/261] [Xtensa] Use B0 register for FP cmp operations. The virtual bool registers allocation from BR class may cause situation when we need to spill such 1-bit registers, this would cause performance degradation due to load/store operations of the 32-bit BR register. The performance improvement from using virtual bool registers is not significant. So, just use only B0 register for FP compare operations. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 7ae0efd5529afa..8943a18de867af 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -2059,15 +2059,15 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, (MI.getOpcode() == Xtensa::SELECT_CC_FP_INT)) { int BrKind = 0; int CmpKind = 0; - MachineFunction *MF = BB->getParent(); - MachineRegisterInfo &RegInfo = MF->getRegInfo(); - const TargetRegisterClass *RC = &Xtensa::BRRegClass; - unsigned b = RegInfo.createVirtualRegister(RC); + unsigned b = Xtensa::B0; + GetFPBranchKind(Cond.getImm(), BrKind, CmpKind); BuildMI(BB, DL, TII.get(CmpKind), b) .addReg(LHS.getReg()) .addReg(RHS.getReg()); - BuildMI(BB, DL, TII.get(BrKind)).addReg(b).addMBB(sinkMBB); + BuildMI(BB, DL, TII.get(BrKind)) + .addReg(b, RegState::Kill) + .addMBB(sinkMBB); } else { bool BrInv = false; int BrKind = GetBranchKind(Cond.getImm(), BrInv); @@ -3122,16 +3122,15 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( MachineBasicBlock *TargetBB = MI.getOperand(3).getMBB(); int BrKind = 0; int CmpKind = 0; - MachineFunction *MF = MBB->getParent(); - MachineRegisterInfo &RegInfo = MF->getRegInfo(); - const TargetRegisterClass *RC = &Xtensa::BRRegClass; + unsigned RegB = Xtensa::B0; - unsigned RegB = RegInfo.createVirtualRegister(RC); GetFPBranchKind(Cond.getImm(), BrKind, CmpKind); BuildMI(*MBB, MI, DL, TII.get(CmpKind), RegB) .addReg(LHS.getReg()) .addReg(RHS.getReg()); - BuildMI(*MBB, MI, DL, TII.get(BrKind)).addReg(RegB).addMBB(TargetBB); + BuildMI(*MBB, MI, DL, TII.get(BrKind)) + .addReg(RegB, RegState::Kill) + .addMBB(TargetBB); MI.eraseFromParent(); return MBB; From 6e90d86255d5eac9d3961d4dad2059b0498c48ea Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:58 +0300 Subject: [PATCH 083/261] ci: add .gitlab-ci.yml to support CI/CD --- .gitlab-ci.yml | 195 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 .gitlab-ci.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100644 index 00000000000000..94f59533db5ad4 --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,195 @@ +stages: + - build + - private_deploy + - test + - public_deploy + +image: ${CI_DOCKER_REGISTRY}/llvm-build:3 + +variables: + + CONF_TARGET: "xtensa-esp32-elf" + XTENSA_CLANG_TOOLCHAIN: "${CONF_TARGET}-clang" + PLATFORM_NAME_LINUX: "linux-amd64" + PLATFORM_NAME_WIN: "win64" + PLATFORM_NAME_MACOS: "macos" + + XTENSA_CLANG_TOOLCHAIN_BRANCH: "esp-20220415-r14.0.0" + GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" + + ARCHIVE_TOOL_LINUX: "tar -cJf" + UNARCHIVE_TOOL_LINUX: "tar -xf" + ARCHIVE_EXT_LINUX: "tar.xz" + + ARCHIVE_TOOL_WIN: "zip -9 -r" + UNARCHIVE_TOOL_WIN: "unzip" + ARCHIVE_EXT_WIN: "zip" + + ARCHIVE_TOOL_MACOS: "tar -cJf" + UNARCHIVE_TOOL_MACOS: "tar -xf" + ARCHIVE_EXT_MACOS: "tar.xz" + + DIST_DIR: "dist" + +.use_ci_tools: &use_ci_tools | + curl -sSL ${CIT_LOADER_URL} -o cit_loader.sh && sh cit_loader.sh + source citools/import_functions + +.add_gitlab_key: &add_gitlab_key | + cit_add_ssh_key "${GITLAB_KEY}" + +before_script: + - *use_ci_tools + - *add_gitlab_key + +# Prepare release name/number +.get_release_name: &get_release_name | + # using annotated tags + REL_NUM=$(git describe --abbrev=7) + REL_SFX="llvm14_0_0" + REL_NAME=${CONF_TARGET}-${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} + ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} + echo "CONF_TARGET: $CONF_TARGET" + echo "PLATFORM_NAME: $PLATFORM_NAME" + echo "REL_NUM: $REL_NUM" + echo "REL_NAME: $REL_NAME" + echo "ARCHIVE_NAME: $ARCHIVE_NAME" + +# Get an existing crosstool-ng build for esp32 +.get_gcc_toolchain: &get_gcc_toolchain | + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/${XTENSA_GCC_TOOLCHAIN} + ${UNARCHIVE_TOOL} ${XTENSA_GCC_TOOLCHAIN} + mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} + +.get_clang_toolchain_build_scripts: &get_clang_toolchain_build_scripts | + git clone -b ${XTENSA_CLANG_TOOLCHAIN_BRANCH} ${GITLAB_SSH_SERVER}/${XTENSA_CLANG_TOOLCHAIN_REPO} + cp -r xtensa-clang-toolchain/* . + +# LLVM Build System used the remote address to show detailed version info, we'll change it to the public repository +.fix_origin_remote_for_public: &fix_origin_remote_for_public | + git remote set-url origin "${GH_REPO_HTTPS}" + + # Pack the toolchain +.package_toolchain: &package_toolchain | + ${ARCHIVE_TOOL} ${ARCHIVE_NAME} ${XTENSA_CLANG_TOOLCHAIN}/ + mkdir -p ${DIST_DIR} + mv ${ARCHIVE_NAME} ${DIST_DIR}/ + echo "${ARCHIVE_NAME}" > ${DIST_DIR}/file_${PLATFORM_NAME}_${CONF_TARGET} + +.build_template: + stage: build + tags: [ "amd64", "build" ] + artifacts: + paths: + - ${DIST_DIR}/ + when: always + expire_in: 10 day + script: + - *get_release_name + - *get_gcc_toolchain + - *fix_origin_remote_for_public + - *get_clang_toolchain_build_scripts + - ${BUILD_TOOLCHAIN_CMD} "${XTENSA_CLANG_TOOLCHAIN}" + - *package_toolchain + +linux_amd64_build: + extends: .build_template + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + # a filename was moved here from the global 'variables:' because of GCC_REL_NAME value couldn't be expanded and substituted there + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux.sh" + +win64_build: + extends: .build_template + variables: + PLATFORM_NAME: "${PLATFORM_NAME_WIN}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" + ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-win64.zip" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" + +macos_amd64_build: + extends: .build_template + variables: + PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" + ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-macos.tar.gz" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh" + +linux_amd64_testsuite: + stage: test + tags: [ "amd64", "build" ] + dependencies: + - linux_amd64_build + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + script: + - *get_release_name + - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} + + # getting testsuit + - git clone -b feature/ci_llvm_multitarget --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git + + # preparing testsuit + - export PATH=$PATH:${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/ + - cd llvm-xtensa-testsuite + + # qemu + - ./qemu_esp32_install.sh + + # run testsuite for esp32 + - ./run_esp32_tests.sh + +upload_to_http: + stage: private_deploy + when: manual + allow_failure: true + tags: [ "deploy", "shiny" ] + variables: + # force the fetch strategy to clean old archives up in dist/ dir + GIT_STRATEGY: fetch + before_script: + - *use_ci_tools + script: + - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" + # List of archives + - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) + - cd ${DIST_DIR} + - scp ${FILES} ${HTTP_UPLOAD_DIR}/ct-ng/llvm-builds + # Show info + - echo -e "\nArchives were published there:\n\n$(for n in ${FILES}; do echo "${HTTP_PUBLIC_DIR}/ct-ng/llvm-builds/${n}"; done)\n" + +upload_to_github: + stage: public_deploy + when: manual + allow_failure: true + only: + - tags + tags: [ "amd64", "internet" ] + image: espressif/github-hub:2 + variables: + GIT_STRATEGY: fetch + GITHUB_TOKEN: "${GH_TOKEN}" + GITHUB_REPO: "${GH_REPO_HTTPS}" + TAG: "${CI_COMMIT_TAG}" + before_script: [] + script: + - ls -l dist*/ + - git remote add github ${GH_REPO_HTTPS} + - hub release show ${TAG} || { echo "Please create a release on GitHub with ${TAG} tag at first"; exit 1; } + # List of archives + - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) + - cd ${DIST_DIR} + - ls -l $FILES + # Upload archives + - for n in ${FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done From 576156d2240c3a8919244016352d72bd1bf94ade Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:59 +0300 Subject: [PATCH 084/261] [Xtensa] Fix inline asm Fix inline asm printing of the memory operands. --- .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 9 ------- .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 3 --- llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 27 +++++++++++-------- llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 1 - llvm/test/CodeGen/Xtensa/inline-asm.ll | 20 ++++++++++++++ 5 files changed, 36 insertions(+), 24 deletions(-) create mode 100644 llvm/test/CodeGen/Xtensa/inline-asm.ll diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index 0960c73dba9375..0a0d298ad267a6 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -27,15 +27,6 @@ using namespace llvm; #include "XtensaGenAsmWriter.inc" -void XtensaInstPrinter::printAddress(unsigned Base, int64_t Disp, - raw_ostream &O) { - O << Disp; - if (Base) { - O << '('; - O << getRegisterName(Base) << ')'; - } -} - static void printExpr(const MCExpr *Expr, raw_ostream &OS) { int Offset = 0; const MCSymbolRefExpr *SRE; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index b103fb5dc9e014..3e8c752bc44260 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -35,9 +35,6 @@ class XtensaInstPrinter : public MCInstPrinter { // Print the given operand. static void printOperand(const MCOperand &MO, raw_ostream &O); - // Print an address - static void printAddress(unsigned Base, int64_t Disp, raw_ostream &O); - // Override MCInstPrinter. void printRegName(raw_ostream &O, MCRegister Reg) const override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index 459ad80257dc32..bea24bc568bd7c 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -260,18 +260,23 @@ bool XtensaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) { - XtensaInstPrinter::printAddress(MI->getOperand(OpNo).getReg(), - MI->getOperand(OpNo + 1).getImm(), OS); - return false; -} + if (ExtraCode && ExtraCode[0]) + return true; // Unknown modifier. + + assert(OpNo + 1 < MI->getNumOperands() && "Insufficient operands"); + + const MachineOperand &Base = MI->getOperand(OpNo); + const MachineOperand &Offset = MI->getOperand(OpNo + 1); -void XtensaAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, - raw_ostream &OS) { - OS << '%' - << XtensaInstPrinter::getRegisterName(MI->getOperand(opNum).getReg()); - OS << "("; - OS << MI->getOperand(opNum + 1).getImm(); - OS << ")"; + assert(Base.isReg() && + "Unexpected base pointer for inline asm memory operand."); + assert(Offset.isImm() && "Unexpected offset for inline asm memory operand."); + + OS << XtensaInstPrinter::getRegisterName(Base.getReg()); + OS << ", "; + OS << Offset.getImm(); + + return false; } // Force static initialization. diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h index 50feaa0fcd2c0d..e17059a2d4c3bf 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h @@ -43,7 +43,6 @@ class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter { const char *ExtraCode, raw_ostream &O) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override; - void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); }; } // end namespace llvm diff --git a/llvm/test/CodeGen/Xtensa/inline-asm.ll b/llvm/test/CodeGen/Xtensa/inline-asm.ll new file mode 100644 index 00000000000000..7a267d51459811 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/inline-asm.ll @@ -0,0 +1,20 @@ +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=Xtensa %s + + +define dso_local i32 @test_memptr(i32 noundef %0) local_unnamed_addr #0 { +; Xtensa-LABEL: test_memptr: +; Xtensa: # %bb.0: +; Xtensa-NEXT: entry a1, 32 +; Xtensa-NEXT: #APP +; Xtensa-NEXT: l32i a2, a2, 0 +; Xtensa-NEXT: #NO_APP +; Xtensa-NEXT: retw + %2 = inttoptr i32 %0 to i32* + %3 = call i32 asm sideeffect "l32i $0, $1", "=r,*m"(i32* elementtype(i32) %2) + ret i32 %3 +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind } + From ce0331f6b0d07a3c0e042d41ff4f23b8e0ed5739 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:42:59 +0300 Subject: [PATCH 085/261] [Xtensa]: Fix handling of empty '-fuse-ld' option for ESP toolchain --- clang/lib/Driver/ToolChains/Xtensa.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index aaf1ab90f71c10..c6a6f3e1479c3f 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -224,7 +224,7 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (ToolChain.GCCToolchainName == "") llvm_unreachable("Unable to find Xtensa GCC linker"); - if (Args.hasArg(options::OPT_fuse_ld_EQ)) { + if (!Args.getLastArgValue(options::OPT_fuse_ld_EQ).empty()) { Linker.assign(ToolChain.GetLinkerPath()); } else { Linker.assign(ToolChain.GCCToolchainDir); From b2f5913d2bd44816e2dbb7e7159799faa76500b1 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:00 +0300 Subject: [PATCH 086/261] esp: Adds support for vendor 'Espressif' to target triple --- clang/lib/Driver/ToolChains/Gnu.cpp | 3 +- clang/lib/Driver/ToolChains/Xtensa.cpp | 14 ++- .../bin/xtensa-esp32s2-elf-ld | 1 + .../bin/xtensa-esp32s3-elf-ld | 1 + .../gcc/xtensa-esp32s2-elf/8.4.0/crtbegin.o | 0 .../lib/gcc/xtensa-esp32s2-elf/8.4.0/crtend.o | 0 .../8.4.0/no-rtti/crtbegin.o | 0 .../xtensa-esp32s2-elf/8.4.0/no-rtti/crtend.o | 0 .../gcc/xtensa-esp32s3-elf/8.4.0/crtbegin.o | 0 .../lib/gcc/xtensa-esp32s3-elf/8.4.0/crtend.o | 0 .../8.4.0/no-rtti/crtbegin.o | 0 .../xtensa-esp32s3-elf/8.4.0/no-rtti/crtend.o | 0 .../xtensa-esp32s2-elf/lib/crt0.o | 0 .../xtensa-esp32s2-elf/lib/no-rtti/crt0.o | 0 .../xtensa-esp32s3-elf/lib/crt0.o | 0 .../xtensa-esp32s3-elf/lib/no-rtti/crt0.o | 0 clang/test/Driver/xtensa-toolchain.c | 105 +++++++++++++----- llvm/include/llvm/TargetParser/Triple.h | 1 + llvm/lib/TargetParser/Triple.cpp | 2 + 19 files changed, 97 insertions(+), 30 deletions(-) create mode 100755 clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld create mode 100755 clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/no-rtti/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/no-rtti/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/no-rtti/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/no-rtti/crt0.o diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index b8c07b66926455..dc74b7bfbe1f84 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -2614,8 +2614,7 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( static const char *const XtensaLibDirs[] = {"/lib"}; static const char *const XtensaTriples[] = { - "xtensa-unknown-elf", "xtensa-esp32-elf", "xtensa-esp32s2-elf", - "xtensa-esp32s3-elf"}; + "xtensa-esp-elf", "xtensa-esp-unknown-elf"}; using std::begin; using std::end; diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index c6a6f3e1479c3f..c7fb67a8d20ae9 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -37,8 +37,20 @@ XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) : Generic_ELF(D, Triple, Args) { - GCCInstallation.init(Triple, Args); + std::vector ExtraAliases; + if (Triple.getVendor() == llvm::Triple::Espressif) { + std::string ESPCpuName = "esp32"; + if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) { + ESPCpuName = A->getValue(); + } + ExtraAliases = {std::string("xtensa-") + ESPCpuName + "-elf"}; + if (Args.hasArg(options::OPT_v)) { + llvm::errs() << "Use GCC target extra alias: " << ExtraAliases[0] << "\n"; + } + } + + GCCInstallation.init(Triple, Args, ExtraAliases); if (!GCCInstallation.isValid()) { llvm_unreachable("Unexpected Xtensa GCC toolchain version"); } diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld b/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld b/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/no-rtti/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/no-rtti/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/no-rtti/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/no-rtti/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/xtensa-toolchain.c b/clang/test/Driver/xtensa-toolchain.c index 0570c1d0f0b571..aa753abcf63667 100644 --- a/clang/test/Driver/xtensa-toolchain.c +++ b/clang/test/Driver/xtensa-toolchain.c @@ -1,42 +1,93 @@ // A basic clang -cc1 command-line, and simple environment check. -// RUN: %clang %s -### -no-canonical-prefixes -target xtensa \ +// RUN: %clang %s -### -no-canonical-prefixes -target xtensa-esp-elf \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=CC1 %s -// CC1: clang{{.*}} "-cc1" "-triple" "xtensa" +// RUN: | FileCheck -check-prefix=CC1-ESP-DEFAULT %s +// CC1-ESP-DEFAULT: clang{{.*}} "-cc1" "-triple" "xtensa-esp-unknown-elf" -// RUN: %clang %s -### -no-canonical-prefixes \ -// RUN: -target xtensa --rtlib=platform \ +// RUN: %clang %s -### -no-canonical-prefixes -target xtensa-esp-elf -mcpu=esp32\ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL %s +// RUN: | FileCheck -check-prefix=CC1-ESP32 %s +// CC1-ESP32: clang{{.*}} "-cc1" "-triple" "xtensa-esp-unknown-elf" {{.*}}"-target-cpu" "esp32" -// C-XTENSA-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" -// C-XTENSA-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" +// RUN: %clang %s -### -no-canonical-prefixes -target xtensa-esp-elf -mcpu=esp32s2\ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=CC1-ESP32S2 %s +// CC1-ESP32S2: clang{{.*}} "-cc1" "-triple" "xtensa-esp-unknown-elf" {{.*}}"-target-cpu" "esp32s2" + +// RUN: %clang %s -### -no-canonical-prefixes -target xtensa-esp-elf -mcpu=esp32s3\ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=CC1-ESP32S3 %s +// CC1-ESP32S3: clang{{.*}} "-cc1" "-triple" "xtensa-esp-unknown-elf" {{.*}}"-target-cpu" "esp32s3" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa-esp-elf --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL %s -// RUN: %clang %s -### -no-canonical-prefixes \ -// RUN: -target xtensa --rtlib=platform \ +// C-XTENSA-ESP32-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" +// C-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa-esp-elf --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -frtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-RTTI %s +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-RTTI %s -// C-XTENSA-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" -// C-XTENSA-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" +// C-XTENSA-ESP32-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" +// C-XTENSA-ESP32-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" -// RUN: %clang %s -### -no-canonical-prefixes \ -// RUN: -target xtensa --rtlib=platform \ +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa-esp-elf --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-PSRAM %s +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-PSRAM %s -// C-XTENSA-BAREMETAL-PSRAM: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram/no-rtti" -// C-XTENSA-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram/no-rtti" +// C-XTENSA-ESP32-BAREMETAL-PSRAM: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram/no-rtti" +// C-XTENSA-ESP32-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram/no-rtti" -// RUN: %clang %s -### -no-canonical-prefixes \ -// RUN: -target xtensa --rtlib=platform \ +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa-esp-elf --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue -frtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-BAREMETAL-PSRAM-RTTI %s +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI %s + +// C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram" +// C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa-esp-elf -mcpu=esp32s2 --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-BAREMETAL %s + +// C-XTENSA-ESP32S2-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" +// C-XTENSA-ESP32S2-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s2-elf{{/|\\\\}}8.4.0/no-rtti" +// C-XTENSA-ESP32S2-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s2-elf{{/|\\\\}}lib/no-rtti" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa-esp-elf -mcpu=esp32s2 --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -frtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-BAREMETAL-RTTI %s + +// C-XTENSA-ESP32S2-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" +// C-XTENSA-ESP32S2-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s2-elf{{/|\\\\}}8.4.0" +// C-XTENSA-ESP32S2-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s2-elf{{/|\\\\}}lib" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa-esp-elf -mcpu=esp32s3 --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-BAREMETAL %s + +// C-XTENSA-ESP32S3-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" +// C-XTENSA-ESP32S3-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}8.4.0/no-rtti" +// C-XTENSA-ESP32S3-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}lib/no-rtti" + +// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ +// RUN: -target xtensa-esp-elf -mcpu=esp32s3 --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -frtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-BAREMETAL-RTTI %s -// C-XTENSA-BAREMETAL-PSRAM-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-BAREMETAL-PSRAM-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram" -// C-XTENSA-BAREMETAL-PSRAM-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram" +// C-XTENSA-ESP32S3-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" +// C-XTENSA-ESP32S3-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}8.4.0" +// C-XTENSA-ESP32S3-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}lib" diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 49ec8de9c528de..2b1a15742a0df4 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -182,6 +182,7 @@ class Triple { Mesa, SUSE, OpenEmbedded, + Espressif, LastVendorType = OpenEmbedded }; enum OSType { diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index 0bbe8a3cedfd78..2df8faa8ccb7da 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -228,6 +228,7 @@ StringRef Triple::getVendorTypeName(VendorType Kind) { case PC: return "pc"; case SCEI: return "scei"; case SUSE: return "suse"; + case Espressif: return "esp"; } llvm_unreachable("Invalid VendorType!"); @@ -602,6 +603,7 @@ static Triple::VendorType parseVendor(StringRef VendorName) { .Case("mesa", Triple::Mesa) .Case("suse", Triple::SUSE) .Case("oe", Triple::OpenEmbedded) + .Case("esp", Triple::Espressif) .Default(Triple::UnknownVendor); } From 72d9a18ec3af79716dea2e8ad787a423cc304dcc Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 6 Feb 2024 14:07:40 +0300 Subject: [PATCH 087/261] [Xtensa] Fix multilib support. This is temporary fix, according to new api changes in release 18. --- clang/lib/Driver/ToolChains/Gnu.cpp | 7 +++++-- clang/lib/Driver/ToolChains/Xtensa.cpp | 15 +-------------- 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index dc74b7bfbe1f84..ed52d92546bd48 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -2613,8 +2613,11 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( "s390x-suse-linux", "s390x-redhat-linux"}; static const char *const XtensaLibDirs[] = {"/lib"}; - static const char *const XtensaTriples[] = { - "xtensa-esp-elf", "xtensa-esp-unknown-elf"}; + static const char *const XtensaTriples[] = {"xtensa-esp-elf", + "xtensa-esp-unknown-elf", + "xtensa-esp32-elf", + "xtensa-esp32s2-elf", + "xtensa-esp32s3-elf"}; using std::begin; using std::end; diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index c7fb67a8d20ae9..a3fa8c57823748 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -37,20 +37,7 @@ XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) : Generic_ELF(D, Triple, Args) { - std::vector ExtraAliases; - - if (Triple.getVendor() == llvm::Triple::Espressif) { - std::string ESPCpuName = "esp32"; - if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) { - ESPCpuName = A->getValue(); - } - ExtraAliases = {std::string("xtensa-") + ESPCpuName + "-elf"}; - if (Args.hasArg(options::OPT_v)) { - llvm::errs() << "Use GCC target extra alias: " << ExtraAliases[0] << "\n"; - } - } - - GCCInstallation.init(Triple, Args, ExtraAliases); + GCCInstallation.init(Triple, Args); if (!GCCInstallation.isValid()) { llvm_unreachable("Unexpected Xtensa GCC toolchain version"); } From 830ded8586a44020efc1e35fe081af0cace06ff6 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:00 +0300 Subject: [PATCH 088/261] esp/riscv: Use GCC assembler for ESP RISCV chips --- clang/lib/Driver/ToolChains/RISCVToolchain.cpp | 1 + clang/lib/Driver/ToolChains/RISCVToolchain.h | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp index 5e4fa4d5331ff2..e32ca300551333 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp @@ -8,6 +8,7 @@ #include "RISCVToolchain.h" #include "CommonArgs.h" +#include "Arch/RISCV.h" #include "clang/Driver/Compilation.h" #include "clang/Driver/InputInfo.h" #include "clang/Driver/Options.h" diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.h b/clang/lib/Driver/ToolChains/RISCVToolchain.h index cec817ef7190be..35f6cbeed408b1 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.h +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.h @@ -35,6 +35,12 @@ class LLVM_LIBRARY_VISIBILITY RISCVToolChain : public Generic_ELF { addLibStdCxxIncludePaths(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; + bool IsIntegratedAssemblerDefault() const override { + if (GCCInstallation.getTriple().getVendor() == llvm::Triple::Espressif) + return false; + return Generic_ELF::IsIntegratedAssemblerDefault(); + } + protected: Tool *buildLinker() const override; From a6820fbaa9f0d314de37971c65cb91a9c0d867c6 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:01 +0300 Subject: [PATCH 089/261] esp/riscv: Adds support for 'riscv32-esp-elf' target triple --- clang/lib/Driver/ToolChains/Gnu.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index ed52d92546bd48..b3537692908fb8 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -2594,7 +2594,9 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( static const char *const RISCV32LibDirs[] = {"/lib32", "/lib"}; static const char *const RISCV32Triples[] = {"riscv32-unknown-linux-gnu", "riscv32-linux-gnu", - "riscv32-unknown-elf"}; + "riscv32-unknown-elf", + "riscv32-esp-elf", + "riscv32-esp-unknown-elf"}; static const char *const RISCV64LibDirs[] = {"/lib64", "/lib"}; static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu", "riscv64-linux-gnu", From fd19346742ec708fe34d671c741b15ca7d7f6df0 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Sep 2023 18:42:22 +0300 Subject: [PATCH 090/261] riscv: Add default multilib. Make '-print-multi-lib' output compatible with GCC --- clang/lib/Driver/ToolChains/Gnu.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index b3537692908fb8..ce78e94fb5804a 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1857,6 +1857,10 @@ static void findRISCVBareMetalMultilibs(const Driver &D, {"rv64imafdc", "lp64d"}}; std::vector Ms; + + if (TargetTriple.getVendor() == llvm::Triple::Espressif) + Ms.emplace_back(MultilibBuilder()); + for (auto Element : RISCVMultilibSet) { // multilib path rule is ${march}/${mabi} Ms.emplace_back( From 8b6bbd9f6a67c00bdfb7c892a944ed46cd10548c Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Sep 2023 20:27:08 +0300 Subject: [PATCH 091/261] esp/riscv: Add multilib support for 'riscv32-esp-elf' GCC toolcahin --- clang/lib/Driver/ToolChains/Gnu.cpp | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index ce78e94fb5804a..1cbcc26e6eff05 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1853,6 +1853,7 @@ static void findRISCVBareMetalMultilibs(const Driver &D, // TODO: support MULTILIB_REUSE constexpr RiscvMultilib RISCVMultilibSet[] = { {"rv32i", "ilp32"}, {"rv32im", "ilp32"}, {"rv32iac", "ilp32"}, + {"rv32imc", "ilp32"}, {"rv32imac", "ilp32"}, {"rv32imafc", "ilp32f"}, {"rv64imac", "lp64"}, {"rv64imafdc", "lp64d"}}; @@ -1873,13 +1874,21 @@ static void findRISCVBareMetalMultilibs(const Driver &D, MultilibSetBuilder() .Either(Ms) .makeMultilibSet() - .FilterOut(NonExistent) - .setFilePathsCallback([](const Multilib &M) { - return std::vector( - {M.gccSuffix(), - "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix(), - "/../../../../riscv32-unknown-elf/lib" + M.gccSuffix()}); - }); + .FilterOut(NonExistent); + + if (TargetTriple.getVendor() == llvm::Triple::Espressif) { + RISCVMultilibs.setFilePathsCallback([](const Multilib &M) { + return std::vector( + {M.gccSuffix(), "/../../../../riscv32-esp-elf/lib" + M.gccSuffix()}); + }); + } else { + RISCVMultilibs.setFilePathsCallback([](const Multilib &M) { + return std::vector( + {M.gccSuffix(), + "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix(), + "/../../../../riscv32-unknown-elf/lib" + M.gccSuffix()}); + }); + } Multilib::flags_list Flags; llvm::StringSet<> Added_ABIs; From 828f35c18df5e5ca364bb285bb65931eb4a7379c Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:02 +0300 Subject: [PATCH 092/261] esp/riscv: Add 'libnosys' to linker command line by default Necessary to avoid build failures when build system (e.g. cmake) tries to make simple compiler checks at configuration stage. --- clang/lib/Driver/ToolChains/RISCVToolchain.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp index e32ca300551333..f12af8552d419e 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp @@ -8,7 +8,6 @@ #include "RISCVToolchain.h" #include "CommonArgs.h" -#include "Arch/RISCV.h" #include "clang/Driver/Compilation.h" #include "clang/Driver/InputInfo.h" #include "clang/Driver/Options.h" @@ -209,6 +208,9 @@ void RISCV::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("--start-group"); CmdArgs.push_back("-lc"); CmdArgs.push_back("-lgloss"); + if (ToolChain.getTriple().getVendor() == llvm::Triple::Espressif) { + CmdArgs.push_back("-lnosys"); + } CmdArgs.push_back("--end-group"); AddRunTimeLibs(ToolChain, ToolChain.getDriver(), CmdArgs, Args); } From a43197f3b5084ae4937fb6757c977e510692d068 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:02 +0300 Subject: [PATCH 093/261] esp/riscv: Exclude 'crt0.o' from linking in 'freestanding' mode --- clang/lib/Driver/ToolChains/RISCVToolchain.cpp | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp index f12af8552d419e..8d9a6e20eab3cd 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp @@ -184,7 +184,17 @@ void RISCV::Linker::ConstructJob(Compilation &C, const JobAction &JA, } if (WantCRTs) { - CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); + /* Espressif toolcahin uses newlib. crt0.o from it refers to 'main' symbol. + In 'freestanding' mode 'main' is not marked as special symbol by clang, + so when compiling C++ program with 'clang++' 'main' gets mmangled + (if not decalred as 'extern "C"' ) and linker can not resolve it. + The problem can happen, for example, when cmake checks C++ compiler by buiding simple C++ code, + unfortunately 'main' function in that code is not decalred as 'extern "C"'. */ + bool Freestanding = + Args.hasFlag(options::OPT_ffreestanding, options::OPT_fhosted, false); + if (!Freestanding || ToolChain.getTriple().getVendor() != llvm::Triple::Espressif) { + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); + } CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin))); } From 6bc7aaa931b8478114b35cae77919da34f916e32 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:03 +0300 Subject: [PATCH 094/261] riscv: Add ESP toolchain tests --- .../bin/riscv32-esp-elf-as | 1 + .../bin/riscv32-esp-elf-ld | 1 + .../lib/gcc/riscv32-esp-elf/8.4.0/crtbegin.o | 0 .../lib/gcc/riscv32-esp-elf/8.4.0/crtend.o | 0 .../8.4.0/rv32i/ilp32/crtbegin.o | 0 .../8.4.0/rv32i/ilp32/crtend.o | 0 .../8.4.0/rv32imac/ilp32/crtbegin.o | 0 .../8.4.0/rv32imac/ilp32/crtend.o | 0 .../8.4.0/rv32imafc/ilp32f/crtbegin.o | 0 .../8.4.0/rv32imafc/ilp32f/crtend.o | 0 .../8.4.0/rv32imc/ilp32/crtbegin.o | 0 .../8.4.0/rv32imc/ilp32/crtend.o | 0 .../riscv32-esp-elf/include/c++/8.4.0/.keep | 0 .../riscv32-esp-elf/lib/crt0.o | 0 .../riscv32-esp-elf/lib/rv32i/ilp32/crt0.o | 0 .../riscv32-esp-elf/lib/rv32imac/ilp32/crt0.o | 0 .../lib/rv32imafc/ilp32f/crt0.o | 0 .../riscv32-esp-elf/lib/rv32imc/ilp32/crt0.o | 0 clang/test/Driver/riscv32-esp-toolchain.c | 306 ++++++++++++++++++ 19 files changed, 308 insertions(+) create mode 100755 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-as create mode 100755 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++/8.4.0/.keep create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32i/ilp32/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imac/ilp32/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imafc/ilp32f/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/crt0.o create mode 100644 clang/test/Driver/riscv32-esp-toolchain.c diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-as b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-as new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-as @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++/8.4.0/.keep b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++/8.4.0/.keep new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32i/ilp32/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32i/ilp32/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imac/ilp32/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imac/ilp32/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imafc/ilp32f/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imafc/ilp32f/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/riscv32-esp-toolchain.c b/clang/test/Driver/riscv32-esp-toolchain.c new file mode 100644 index 00000000000000..5c34c0a3bf7a15 --- /dev/null +++ b/clang/test/Driver/riscv32-esp-toolchain.c @@ -0,0 +1,306 @@ +// A basic clang -cc1 command-line, and simple environment check. + +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ +// RUN: | FileCheck -check-prefix=CC1 %s +// CC1: clang{{.*}} "-cc1" "-triple" "riscv32-esp-unknown-elf" + +// Test interaction with -fuse-ld=lld, if lld is available. +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk -fuse-ld=lld 2>&1 \ +// RUN: | FileCheck -check-prefix=LLD %s +// LLD: {{(error: invalid linker name in argument '-fuse-ld=lld')|(ld.lld)}} + +// rv32imac is the default + +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk \ +// RUN: --sysroot=%S/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMAC-BAREMETAL-MULTI-ILP32 %s + +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "-mabi" "ilp32" "-march" "rv32imac" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "--sysroot={{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "-m" "elf32lriscv" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtbegin.o" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" +// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" + +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ +// RUN: --sysroot= \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32 %s + +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-mabi" "ilp32" "-march" "rv32imac" +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-m" "elf32lriscv" +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtbegin.o" +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" +// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" + +// RUN: %clangxx %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: -ffreestanding -stdlib=libstdc++ --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk \ +// RUN: --sysroot=%S/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf 2>&1 \ +// RUN: | FileCheck -check-prefix=CXX-RV32IMAC-BAREMETAL-MULTI-ILP32 %s + +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-internal-isystem" "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++{{/|\\\\}}8.4.0" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-mabi" "ilp32" "-march" "rv32imac" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "--sysroot={{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-m" "elf32lriscv" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtbegin.o" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-lstdc++" "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" +// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" + +// RUN: %clangxx %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: -ffreestanding -stdlib=libstdc++ --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ +// RUN: --sysroot= \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ +// RUN: | FileCheck -check-prefix=CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32 %s + +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-internal-isystem" "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/include/c++{{/|\\\\}}8.4.0" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-mabi" "ilp32" "-march" "rv32imac" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-m" "elf32lriscv" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtbegin.o" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-lstdc++" "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" +// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" + +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: -march=rv32i -mabi=ilp32 \ +// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld --sysroot= \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32I-BAREMETAL-MULTI-ILP32 %s + +// C-RV32I-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" +// C-RV32I-BAREMETAL-MULTI-ILP32: "-mabi" "ilp32" "-march" "rv32i" +// C-RV32I-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32I-BAREMETAL-MULTI-ILP32: "-m" "elf32lriscv" +// C-RV32I-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32{{/|\\\\}}crtbegin.o" +// C-RV32I-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" +// C-RV32I-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" +// C-RV32I-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" +// C-RV32I-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32{{/|\\\\}}crtend.o" + +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: -march=rv32imc -mabi=ilp32 \ +// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld --sysroot= \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMC-BAREMETAL-MULTI-ILP32 %s + +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "-mabi" "ilp32" "-march" "rv32imc" +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "-m" "elf32lriscv" +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32{{/|\\\\}}crtbegin.o" +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" +// C-RV32IMC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32{{/|\\\\}}crtend.o" + +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: -march=rv32imafc -mabi=ilp32f \ +// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld --sysroot= \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMAFC-BAREMETAL-MULTI-ILP32F %s + +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "-mabi" "ilp32f" "-march" "rv32imafc" +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "-m" "elf32lriscv" +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f{{/|\\\\}}crtbegin.o" +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" +// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f{{/|\\\\}}crtend.o" + +// RUN: %clang -target riscv32-esp-elf %s -emit-llvm -S -o - | FileCheck %s + +typedef __builtin_va_list va_list; +typedef __SIZE_TYPE__ size_t; +typedef __PTRDIFF_TYPE__ ptrdiff_t; +typedef __WCHAR_TYPE__ wchar_t; +typedef __WINT_TYPE__ wint_t; + + +// Check Alignments + +// CHECK: @align_c = dso_local global i32 1 +int align_c = __alignof(char); + +// CHECK: @align_s = dso_local global i32 2 +int align_s = __alignof(short); + +// CHECK: @align_i = dso_local global i32 4 +int align_i = __alignof(int); + +// CHECK: @align_wc = dso_local global i32 4 +int align_wc = __alignof(wchar_t); + +// CHECK: @align_wi = dso_local global i32 4 +int align_wi = __alignof(wint_t); + +// CHECK: @align_l = dso_local global i32 4 +int align_l = __alignof(long); + +// CHECK: @align_ll = dso_local global i32 8 +int align_ll = __alignof(long long); + +// CHECK: @align_p = dso_local global i32 4 +int align_p = __alignof(void*); + +// CHECK: @align_f = dso_local global i32 4 +int align_f = __alignof(float); + +// CHECK: @align_d = dso_local global i32 8 +int align_d = __alignof(double); + +// CHECK: @align_ld = dso_local global i32 16 +int align_ld = __alignof(long double); + +// CHECK: @align_vl = dso_local global i32 4 +int align_vl = __alignof(va_list); + +// CHECK: @align_a_c = dso_local global i32 1 +int align_a_c = __alignof(_Atomic(char)); + +// CHECK: @align_a_s = dso_local global i32 2 +int align_a_s = __alignof(_Atomic(short)); + +// CHECK: @align_a_i = dso_local global i32 4 +int align_a_i = __alignof(_Atomic(int)); + +// CHECK: @align_a_wc = dso_local global i32 4 +int align_a_wc = __alignof(_Atomic(wchar_t)); + +// CHECK: @align_a_wi = dso_local global i32 4 +int align_a_wi = __alignof(_Atomic(wint_t)); + +// CHECK: @align_a_l = dso_local global i32 4 +int align_a_l = __alignof(_Atomic(long)); + +// CHECK: @align_a_ll = dso_local global i32 8 +int align_a_ll = __alignof(_Atomic(long long)); + +// CHECK: @align_a_p = dso_local global i32 4 +int align_a_p = __alignof(_Atomic(void*)); + +// CHECK: @align_a_f = dso_local global i32 4 +int align_a_f = __alignof(_Atomic(float)); + +// CHECK: @align_a_d = dso_local global i32 8 +int align_a_d = __alignof(_Atomic(double)); + +// CHECK: @align_a_ld = dso_local global i32 16 +int align_a_ld = __alignof(_Atomic(long double)); + +// CHECK: @align_a_s4 = dso_local global i32 4 +int align_a_s4 = __alignof(_Atomic(struct { char s[4]; })); + +// CHECK: @align_a_s8 = dso_local global i32 8 +int align_a_s8 = __alignof(_Atomic(struct { char s[8]; })); + +// CHECK: @align_a_s16 = dso_local global i32 16 +int align_a_s16 = __alignof(_Atomic(struct { char s[16]; })); + +// CHECK: @align_a_s32 = dso_local global i32 1 +int align_a_s32 = __alignof(_Atomic(struct { char s[32]; })); + + +// Check Sizes + +// CHECK: @size_a_c = dso_local global i32 1 +int size_a_c = sizeof(_Atomic(char)); + +// CHECK: @size_a_s = dso_local global i32 2 +int size_a_s = sizeof(_Atomic(short)); + +// CHECK: @size_a_i = dso_local global i32 4 +int size_a_i = sizeof(_Atomic(int)); + +// CHECK: @size_a_wc = dso_local global i32 4 +int size_a_wc = sizeof(_Atomic(wchar_t)); + +// CHECK: @size_a_wi = dso_local global i32 4 +int size_a_wi = sizeof(_Atomic(wint_t)); + +// CHECK: @size_a_l = dso_local global i32 4 +int size_a_l = sizeof(_Atomic(long)); + +// CHECK: @size_a_ll = dso_local global i32 8 +int size_a_ll = sizeof(_Atomic(long long)); + +// CHECK: @size_a_p = dso_local global i32 4 +int size_a_p = sizeof(_Atomic(void*)); + +// CHECK: @size_a_f = dso_local global i32 4 +int size_a_f = sizeof(_Atomic(float)); + +// CHECK: @size_a_d = dso_local global i32 8 +int size_a_d = sizeof(_Atomic(double)); + +// CHECK: @size_a_ld = dso_local global i32 16 +int size_a_ld = sizeof(_Atomic(long double)); + + +// Check types + +// CHECK: zeroext i8 @check_char() +char check_char() { return 0; } + +// CHECK: define dso_local signext i16 @check_short() +short check_short() { return 0; } + +// CHECK: define dso_local i32 @check_int() +int check_int() { return 0; } + +// CHECK: define dso_local i32 @check_wchar_t() +int check_wchar_t() { return 0; } + +// CHECK: define dso_local i32 @check_long() +long check_long() { return 0; } + +// CHECK: define dso_local i64 @check_longlong() +long long check_longlong() { return 0; } + +// CHECK: define dso_local zeroext i8 @check_uchar() +unsigned char check_uchar() { return 0; } + +// CHECK: define dso_local zeroext i16 @check_ushort() +unsigned short check_ushort() { return 0; } + +// CHECK: define dso_local i32 @check_uint() +unsigned int check_uint() { return 0; } + +// CHECK: define dso_local i32 @check_ulong() +unsigned long check_ulong() { return 0; } + +// CHECK: define dso_local i64 @check_ulonglong() +unsigned long long check_ulonglong() { return 0; } + +// CHECK: define dso_local i32 @check_size_t() +size_t check_size_t() { return 0; } + +// CHECK: define dso_local float @check_float() +float check_float() { return 0; } + +// CHECK: define dso_local double @check_double() +double check_double() { return 0; } + +// CHECK: define dso_local fp128 @check_longdouble() +long double check_longdouble() { return 0; } From c4a8bf4a9e0f845a21a4422446abce0310a9f155 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:03 +0300 Subject: [PATCH 095/261] esp/ci: Adds Linux build --- .gitlab-ci.yml | 145 ++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 114 insertions(+), 31 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 94f59533db5ad4..2a7be284f5b86f 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -4,19 +4,26 @@ stages: - test - public_deploy -image: ${CI_DOCKER_REGISTRY}/llvm-build:3 +image: ${CI_DOCKER_REGISTRY}/llvm-build:4-e2c59838 variables: - CONF_TARGET: "xtensa-esp32-elf" - XTENSA_CLANG_TOOLCHAIN: "${CONF_TARGET}-clang" + # move all these to CI/CD settings + GCC_REL_NAME: "esp-2021r2-patch3" + GCC_REL_VER: "gcc8_4_0" + XTENSA_CLANG_TOOLCHAIN_REF: "build_newlib_and_toolchain" + NEWLIB_REPO: "newlib-cygwin" + NEWLIB_REF: "esp_based_on_3_3_0" + BINUTILS_REPO: "binutils-gdb" + BINUTILS_REF: "esp_based_on_binutils-2_35" + XTENSA_OVERLAYS_REPO: "xtensa-overlays" + XTENSA_OVERLAYS_REF: "master" + LLVM_GCC_TESTSUITE_REF: "feature/toolchain_build_script" + PLATFORM_NAME_LINUX: "linux-amd64" PLATFORM_NAME_WIN: "win64" PLATFORM_NAME_MACOS: "macos" - XTENSA_CLANG_TOOLCHAIN_BRANCH: "esp-20220415-r14.0.0" - GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" - ARCHIVE_TOOL_LINUX: "tar -cJf" UNARCHIVE_TOOL_LINUX: "tar -xf" ARCHIVE_EXT_LINUX: "tar.xz" @@ -30,6 +37,15 @@ variables: ARCHIVE_EXT_MACOS: "tar.xz" DIST_DIR: "dist" + DOWNLOADS_DIR: "_downloads" + +########################################################################### +#################### START OF TEMPORARY LEGACY CODE ####################### +# TODO: the code below is to be removed after migration to new build script + CONF_TARGET: "xtensa-esp32-elf" + XTENSA_CLANG_TOOLCHAIN: "${CONF_TARGET}-clang" +##################### END OF TEMPORARY LEGACY CODE ######################## +########################################################################### .use_ci_tools: &use_ci_tools | curl -sSL ${CIT_LOADER_URL} -o cit_loader.sh && sh cit_loader.sh @@ -47,36 +63,108 @@ before_script: # using annotated tags REL_NUM=$(git describe --abbrev=7) REL_SFX="llvm14_0_0" - REL_NAME=${CONF_TARGET}-${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} + REL_NAME=${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} - echo "CONF_TARGET: $CONF_TARGET" echo "PLATFORM_NAME: $PLATFORM_NAME" echo "REL_NUM: $REL_NUM" echo "REL_NAME: $REL_NAME" echo "ARCHIVE_NAME: $ARCHIVE_NAME" -# Get an existing crosstool-ng build for esp32 +# Get an existing crosstool-ng builds for all chips .get_gcc_toolchain: &get_gcc_toolchain | - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/${XTENSA_GCC_TOOLCHAIN} - ${UNARCHIVE_TOOL} ${XTENSA_GCC_TOOLCHAIN} - mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} + declare -a XTENSA_CPUS=("esp32" + "esp32s2" + "esp32s3") + for ((i = 0; i < ${#XTENSA_CPUS[@]}; i++)); do + XTENSA_CPU=${XTENSA_CPUS[$i]} + GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_REL_NAME}-linux-amd64.tar.gz + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} + ${UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} + done; + GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_REL_NAME}-linux-amd64.tar.gz + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} + ${UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} .get_clang_toolchain_build_scripts: &get_clang_toolchain_build_scripts | - git clone -b ${XTENSA_CLANG_TOOLCHAIN_BRANCH} ${GITLAB_SSH_SERVER}/${XTENSA_CLANG_TOOLCHAIN_REPO} + git clone -b ${XTENSA_CLANG_TOOLCHAIN_REF} ${GITLAB_SSH_SERVER}/${XTENSA_CLANG_TOOLCHAIN_REPO} cp -r xtensa-clang-toolchain/* . # LLVM Build System used the remote address to show detailed version info, we'll change it to the public repository .fix_origin_remote_for_public: &fix_origin_remote_for_public | git remote set-url origin "${GH_REPO_HTTPS}" - # Pack the toolchain +# Pack the toolchain .package_toolchain: &package_toolchain | + ${ARCHIVE_TOOL} ${ARCHIVE_NAME} esp-elf-clang/ + mkdir -p ${DISTRO_DIR} + mv ${ARCHIVE_NAME} ${DISTRO_DIR}/ + echo "${ARCHIVE_NAME}" > ${DISTRO_DIR}/file_${PLATFORM_NAME} + +.build_template: + stage: build + tags: [ "amd64", "build" ] + artifacts: + paths: + - ${DIST_DIR}/ + - _build_Release/tests.log + when: always + expire_in: 1 day + script: + - *get_release_name + - mkdir ${DOWNLOADS_DIR} + - pushd ${DOWNLOADS_DIR} + - export ESP_GCC_TOOLCHAIN_DIST_BASE=$PWD + - *get_gcc_toolchain + - git clone -b ${NEWLIB_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${NEWLIB_REPO}.git + - export NEWLIB_PATH=$PWD/${NEWLIB_REPO} + - git clone -b ${BINUTILS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${BINUTILS_REPO}.git + - export BINUTILS_PATH=$PWD/${BINUTILS_REPO} + - git clone -b ${XTENSA_OVERLAYS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${XTENSA_OVERLAYS_REPO}.git + - export XTENSA_OVERLAYS_PATH=$PWD/${XTENSA_OVERLAYS_REPO} + - popd + - *get_clang_toolchain_build_scripts + - *fix_origin_remote_for_public + - export ESP_GCC_TOOLCHAIN_REL_VER=${GCC_REL_NAME} + - export LLVM_PROJECT_PATH=$PWD + - export ESP_CLANG_BUILD_TYPE=Release + - export BUILD_PATH=$PWD/_build_$ESP_CLANG_BUILD_TYPE + - ./build_toolchain.sh 2>&1 > /dev/null + # Run tests as non-root user + # permission tests fail when run by root + - useradd -m test_runner + - chown -R test_runner $BUILD_PATH + - runuser -l test_runner -c 'cmake --build '$BUILD_PATH'/clang --target check-all 2>&1 > '$BUILD_PATH'/tests.log' + - export DISTRO_DIR=$PWD/$DIST_DIR + - pushd $BUILD_PATH + - *package_toolchain + - popd + +########################################################################### +#################### START OF TEMPORARY LEGACY CODE ####################### +# TODO: the code below is to be removed after migration to new build script +.get_release_name_old: &get_release_name_old | + # using annotated tags + REL_NUM=$(git describe --abbrev=7) + REL_SFX="llvm14_0_0" + REL_NAME=${CONF_TARGET}-${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} + ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} + echo "PLATFORM_NAME: $PLATFORM_NAME" + echo "REL_NUM: $REL_NUM" + echo "REL_NAME: $REL_NAME" + echo "ARCHIVE_NAME: $ARCHIVE_NAME" + +.get_gcc_toolchain_old: &get_gcc_toolchain_old | + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/${XTENSA_GCC_TOOLCHAIN} + ${UNARCHIVE_TOOL} ${XTENSA_GCC_TOOLCHAIN} + mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} + +.package_toolchain_old: &package_toolchain_old | ${ARCHIVE_TOOL} ${ARCHIVE_NAME} ${XTENSA_CLANG_TOOLCHAIN}/ mkdir -p ${DIST_DIR} mv ${ARCHIVE_NAME} ${DIST_DIR}/ echo "${ARCHIVE_NAME}" > ${DIST_DIR}/file_${PLATFORM_NAME}_${CONF_TARGET} -.build_template: +.build_template_old: stage: build tags: [ "amd64", "build" ] artifacts: @@ -85,12 +173,14 @@ before_script: when: always expire_in: 10 day script: - - *get_release_name - - *get_gcc_toolchain + - *get_release_name_old + - *get_gcc_toolchain_old - *fix_origin_remote_for_public - *get_clang_toolchain_build_scripts - ${BUILD_TOOLCHAIN_CMD} "${XTENSA_CLANG_TOOLCHAIN}" - - *package_toolchain + - *package_toolchain_old +##################### END OF TEMPORARY LEGACY CODE ######################## +########################################################################### linux_amd64_build: extends: .build_template @@ -99,12 +189,9 @@ linux_amd64_build: ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - # a filename was moved here from the global 'variables:' because of GCC_REL_NAME value couldn't be expanded and substituted there - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux.sh" win64_build: - extends: .build_template + extends: .build_template_old variables: PLATFORM_NAME: "${PLATFORM_NAME_WIN}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" @@ -114,7 +201,7 @@ win64_build: BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" macos_amd64_build: - extends: .build_template + extends: .build_template_old variables: PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" @@ -136,17 +223,13 @@ linux_amd64_testsuite: script: - *get_release_name - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} - - # getting testsuit - - git clone -b feature/ci_llvm_multitarget --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git - - # preparing testsuit - - export PATH=$PATH:${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/ + # getting testsuite + - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git + # preparing testsuite + - export PATH=${PWD}/esp-elf-clang/bin:$PATH - cd llvm-xtensa-testsuite - # qemu - ./qemu_esp32_install.sh - # run testsuite for esp32 - ./run_esp32_tests.sh From 91d41ff1abea85a2b60e053f49ebbcd2db0b91dd Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:04 +0300 Subject: [PATCH 096/261] esp/ci: Adds Mingw32 build --- .gitlab-ci.yml | 145 +++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 123 insertions(+), 22 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2a7be284f5b86f..f2923ed513b845 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -4,20 +4,21 @@ stages: - test - public_deploy -image: ${CI_DOCKER_REGISTRY}/llvm-build:4-e2c59838 +image: ${CI_DOCKER_REGISTRY}/llvm-build:3 variables: # move all these to CI/CD settings GCC_REL_NAME: "esp-2021r2-patch3" GCC_REL_VER: "gcc8_4_0" - XTENSA_CLANG_TOOLCHAIN_REF: "build_newlib_and_toolchain" NEWLIB_REPO: "newlib-cygwin" NEWLIB_REF: "esp_based_on_3_3_0" BINUTILS_REPO: "binutils-gdb" BINUTILS_REF: "esp_based_on_binutils-2_35" XTENSA_OVERLAYS_REPO: "xtensa-overlays" XTENSA_OVERLAYS_REF: "master" + # TODO: update vars below to tags names after related branches are merged in those repos + XTENSA_CLANG_TOOLCHAIN_REF: "release_universal_clang_14.0.0_gcc_8.4.0" LLVM_GCC_TESTSUITE_REF: "feature/toolchain_build_script" PLATFORM_NAME_LINUX: "linux-amd64" @@ -27,16 +28,20 @@ variables: ARCHIVE_TOOL_LINUX: "tar -cJf" UNARCHIVE_TOOL_LINUX: "tar -xf" ARCHIVE_EXT_LINUX: "tar.xz" + GCC_ARCHIVE_EXT_LINUX: "tar.gz" ARCHIVE_TOOL_WIN: "zip -9 -r" UNARCHIVE_TOOL_WIN: "unzip" ARCHIVE_EXT_WIN: "zip" + GCC_ARCHIVE_EXT_WIN: "zip" ARCHIVE_TOOL_MACOS: "tar -cJf" UNARCHIVE_TOOL_MACOS: "tar -xf" ARCHIVE_EXT_MACOS: "tar.xz" + GCC_ARCHIVE_EXT_MACOS: "tar.gz" DIST_DIR: "dist" + BUILD_DIR: "_build" DOWNLOADS_DIR: "_downloads" ########################################################################### @@ -77,11 +82,11 @@ before_script: "esp32s3") for ((i = 0; i < ${#XTENSA_CPUS[@]}; i++)); do XTENSA_CPU=${XTENSA_CPUS[$i]} - GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_REL_NAME}-linux-amd64.tar.gz + GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${GCC_ARCHIVE_EXT} wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} ${UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} done; - GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_REL_NAME}-linux-amd64.tar.gz + GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${GCC_ARCHIVE_EXT} wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} ${UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} @@ -95,7 +100,7 @@ before_script: # Pack the toolchain .package_toolchain: &package_toolchain | - ${ARCHIVE_TOOL} ${ARCHIVE_NAME} esp-elf-clang/ + ${ARCHIVE_TOOL} ${ARCHIVE_NAME} esp-clang/ mkdir -p ${DISTRO_DIR} mv ${ARCHIVE_NAME} ${DISTRO_DIR}/ echo "${ARCHIVE_NAME}" > ${DISTRO_DIR}/file_${PLATFORM_NAME} @@ -106,9 +111,15 @@ before_script: artifacts: paths: - ${DIST_DIR}/ - - _build_Release/tests.log + - ${BUILD_DIR}/clang_tests.log + - ${BUILD_DIR}/clang_build.log when: always expire_in: 1 day + variables: + BUILD_TOOLCHAIN_CMD_ARGS: "" + # use separate dist dir for universal toolchain + # TODO: remove this var after switching to universal toolchain builds + DIST_DIR: "dist_new" script: - *get_release_name - mkdir ${DOWNLOADS_DIR} @@ -126,19 +137,99 @@ before_script: - *fix_origin_remote_for_public - export ESP_GCC_TOOLCHAIN_REL_VER=${GCC_REL_NAME} - export LLVM_PROJECT_PATH=$PWD - - export ESP_CLANG_BUILD_TYPE=Release - - export BUILD_PATH=$PWD/_build_$ESP_CLANG_BUILD_TYPE - - ./build_toolchain.sh 2>&1 > /dev/null - # Run tests as non-root user - # permission tests fail when run by root - - useradd -m test_runner - - chown -R test_runner $BUILD_PATH - - runuser -l test_runner -c 'cmake --build '$BUILD_PATH'/clang --target check-all 2>&1 > '$BUILD_PATH'/tests.log' + - export BUILD_PATH=$PWD/${BUILD_DIR} + - mkdir -p ${BUILD_PATH} + - export USE_PARALLEL_LINK_JOBS=2 + - ${BUILD_TOOLCHAIN_CMD} --llvm-path=${LLVM_PROJECT_PATH} --newlib-path=${NEWLIB_PATH} + --gcc-toolchains-path=${ESP_GCC_TOOLCHAIN_DIST_BASE} --binutils-path=${BINUTILS_PATH} + --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} ${BUILD_TOOLCHAIN_CMD_ARGS} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/clang_build.log + # Run unit tests for native build only. + # Run as non-root user because permission tests fail when run by root. + - export BUILD_HOST=$(gcc -dumpmachine) + - export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-Release-${CONF_HOST} + - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then + echo "Run unit tests for native build"; + useradd -m test_runner; + chown -R test_runner ${LLVM_BUILD_PATH}; + touch ${BUILD_PATH}/clang_tests.log; + chmod o+w ${BUILD_PATH}/clang_tests.log; + runuser -l test_runner -c 'cmake --build '${LLVM_BUILD_PATH}' --target check-all 2>&1 > '${BUILD_PATH}'/clang_tests.log'; + fi - export DISTRO_DIR=$PWD/$DIST_DIR - - pushd $BUILD_PATH + - pushd ${BUILD_PATH} - *package_toolchain - popd +build_x86_64-linux-gnu: + extends: .build_template + variables: + CONF_HOST: "x86_64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + GCC_ARCHIVE_EXT: "${GCC_ARCHIVE_EXT_LINUX}" + BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" + +build_x86_64-w64-mingw32: + extends: .build_template + needs: + - job: build_x86_64-linux-gnu + before_script: + - *use_ci_tools + - *add_gitlab_key + # get ARCHIVE_NAME for Linux release. Modify vars to make get_release_name working properly + - export PLATFORM_NAME_ORIG=${PLATFORM_NAME} + - export ARCHIVE_EXT_ORIG=${ARCHIVE_EXT} + - export PLATFORM_NAME=${PLATFORM_NAME_LINUX} + - export ARCHIVE_EXT=${ARCHIVE_EXT_LINUX} + - *get_release_name + # restore modified vars + - export PLATFORM_NAME=${PLATFORM_NAME_ORIG} + - export ARCHIVE_EXT=${ARCHIVE_EXT_ORIG} + # unpack Linux release to re-use it as native Clang for Windows build + - mkdir -p esp-clang-${PLATFORM_NAME_LINUX} + - ${UNARCHIVE_TOOL_LINUX} ${DIST_DIR}/${ARCHIVE_NAME} -C esp-clang-${PLATFORM_NAME_LINUX} + # we do not want to keep artifacts from 'x86_64-linux-gnu' job + - rm -rf ${DIST_DIR} + - rm -rf ${BUILD_DIR} + # add build command args speciifc for Windows build + - export BUILD_TOOLCHAIN_CMD_ARGS="--host=${CONF_HOST} --native-esp-clang-path=$PWD/esp-clang-${PLATFORM_NAME_LINUX}" + variables: + CONF_HOST: "x86_64-w64-mingw32" + PLATFORM_NAME: "${PLATFORM_NAME_WIN}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" + ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" + GCC_ARCHIVE_EXT: "${GCC_ARCHIVE_EXT_WIN}" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" + +test_x86_64-linux-gnu: + stage: test + tags: [ "amd64", "build" ] + needs: + - job: build_x86_64-linux-gnu + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + # use separate dist dir for universal toolchain + # TODO: remove this var after switching to universal toolchain builds + DIST_DIR: "dist_new" + script: + - *get_release_name + - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} + # getting testsuite + - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git + # preparing testsuite + - export PATH=${PWD}/esp-clang/bin:$PATH + - cd llvm-xtensa-testsuite + # qemu + - ./qemu_esp32_install.sh + # run testsuite for esp32 + - ./run_esp32_tests.sh + ########################################################################### #################### START OF TEMPORARY LEGACY CODE ####################### # TODO: the code below is to be removed after migration to new build script @@ -172,6 +263,9 @@ before_script: - ${DIST_DIR}/ when: always expire_in: 10 day + variables: + XTENSA_CLANG_TOOLCHAIN_REF: "esp-20220415-r14.0.0" + GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" script: - *get_release_name_old - *get_gcc_toolchain_old @@ -179,16 +273,16 @@ before_script: - *get_clang_toolchain_build_scripts - ${BUILD_TOOLCHAIN_CMD} "${XTENSA_CLANG_TOOLCHAIN}" - *package_toolchain_old -##################### END OF TEMPORARY LEGACY CODE ######################## -########################################################################### linux_amd64_build: - extends: .build_template + extends: .build_template_old variables: PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux.sh" win64_build: extends: .build_template_old @@ -213,26 +307,33 @@ macos_amd64_build: linux_amd64_testsuite: stage: test tags: [ "amd64", "build" ] - dependencies: - - linux_amd64_build + needs: + - job: linux_amd64_build variables: PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" script: - - *get_release_name + - *get_release_name_old - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} + # getting testsuite - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git + # preparing testsuite - - export PATH=${PWD}/esp-elf-clang/bin:$PATH + - export PATH=$PATH:${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/ - cd llvm-xtensa-testsuite + # qemu - ./qemu_esp32_install.sh + # run testsuite for esp32 - ./run_esp32_tests.sh +##################### END OF TEMPORARY LEGACY CODE ######################## +########################################################################### + upload_to_http: stage: private_deploy when: manual From 3cb640e75166a8f0104c3e466dd9b716d591a230 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Sep 2023 21:05:41 +0300 Subject: [PATCH 097/261] [Xtensa] Remove redundant target features --- clang/lib/Driver/ToolChains/Xtensa.cpp | 5 ----- 1 file changed, 5 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index a3fa8c57823748..0544228c2d3481 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -298,9 +298,4 @@ void xtensa::getXtensaTargetFeatures(const Driver &D, const llvm::Triple &Triple std::vector &Features) { if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) getXtensaFeaturesFromMcpu(D, Args, A, A->getValue(), Features); - - // Now add any that the user explicitly requested on the command line, - // which may override the defaults. - handleTargetFeaturesGroup(D, Triple, Args, Features, - options::OPT_m_xtensa_Features_Group); } From 9293ff76130c1ae194967be356cb73e7ab533b44 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:05 +0300 Subject: [PATCH 098/261] esp/ci: Upgrade universal toolchain to 'gcc11_2_0-esp-2022r1-RC1' and newlib 4.1.0 --- .gitlab-ci.yml | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index f2923ed513b845..025a6c55d42d1f 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -9,10 +9,10 @@ image: ${CI_DOCKER_REGISTRY}/llvm-build:3 variables: # move all these to CI/CD settings - GCC_REL_NAME: "esp-2021r2-patch3" - GCC_REL_VER: "gcc8_4_0" + GCC_REL_NAME: "esp-2022r1-RC1" + GCC_REL_VER: "gcc11_2_0" NEWLIB_REPO: "newlib-cygwin" - NEWLIB_REF: "esp_based_on_3_3_0" + NEWLIB_REF: "esp_based_on_4_1_0" BINUTILS_REPO: "binutils-gdb" BINUTILS_REF: "esp_based_on_binutils-2_35" XTENSA_OVERLAYS_REPO: "xtensa-overlays" @@ -28,17 +28,14 @@ variables: ARCHIVE_TOOL_LINUX: "tar -cJf" UNARCHIVE_TOOL_LINUX: "tar -xf" ARCHIVE_EXT_LINUX: "tar.xz" - GCC_ARCHIVE_EXT_LINUX: "tar.gz" ARCHIVE_TOOL_WIN: "zip -9 -r" UNARCHIVE_TOOL_WIN: "unzip" ARCHIVE_EXT_WIN: "zip" - GCC_ARCHIVE_EXT_WIN: "zip" ARCHIVE_TOOL_MACOS: "tar -cJf" UNARCHIVE_TOOL_MACOS: "tar -xf" ARCHIVE_EXT_MACOS: "tar.xz" - GCC_ARCHIVE_EXT_MACOS: "tar.gz" DIST_DIR: "dist" BUILD_DIR: "_build" @@ -82,11 +79,11 @@ before_script: "esp32s3") for ((i = 0; i < ${#XTENSA_CPUS[@]}; i++)); do XTENSA_CPU=${XTENSA_CPUS[$i]} - GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${GCC_ARCHIVE_EXT} + GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${ARCHIVE_EXT} wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} ${UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} done; - GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${GCC_ARCHIVE_EXT} + GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${ARCHIVE_EXT} wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} ${UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} @@ -168,7 +165,6 @@ build_x86_64-linux-gnu: ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - GCC_ARCHIVE_EXT: "${GCC_ARCHIVE_EXT_LINUX}" BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" build_x86_64-w64-mingw32: @@ -201,7 +197,6 @@ build_x86_64-w64-mingw32: ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" - GCC_ARCHIVE_EXT: "${GCC_ARCHIVE_EXT_WIN}" BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" test_x86_64-linux-gnu: From c69a38d409ee5e97766d57103ede3affe9f31078 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:05 +0300 Subject: [PATCH 099/261] esp/ci: Allow failure for universal toolchain builds --- .gitlab-ci.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 025a6c55d42d1f..81bfcf25648bd5 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -105,6 +105,7 @@ before_script: .build_template: stage: build tags: [ "amd64", "build" ] + allow_failure: true artifacts: paths: - ${DIST_DIR}/ @@ -202,6 +203,7 @@ build_x86_64-w64-mingw32: test_x86_64-linux-gnu: stage: test tags: [ "amd64", "build" ] + allow_failure: true needs: - job: build_x86_64-linux-gnu variables: From 73427248b9dd65a1e77b16f10da34828c777a51a Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Sep 2023 21:47:29 +0300 Subject: [PATCH 100/261] Implement support of the sysroot --- clang/lib/Driver/ToolChains/Xtensa.cpp | 211 +++++++++++------- clang/lib/Driver/ToolChains/Xtensa.h | 3 + .../xtensa-esp32-elf/include/c++/8.4.0/.keep | 0 clang/test/Driver/xtensa-toolchain.c | 32 +++ 4 files changed, 162 insertions(+), 84 deletions(-) create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0/.keep diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index 0544228c2d3481..a1c45ecf5947d4 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -38,57 +38,80 @@ XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, : Generic_ELF(D, Triple, Args) { GCCInstallation.init(Triple, Args); - if (!GCCInstallation.isValid()) { - llvm_unreachable("Unexpected Xtensa GCC toolchain version"); - } - - Multilibs = GCCInstallation.getMultilibs(); - SelectedMultilibs.assign({GCCInstallation.getMultilib()}); - - GCCLibAndIncVersion = GCCInstallation.getVersion().Text; - GCCToolchainName = GCCInstallation.getTriple().str(); - SmallString<128> Path(GCCInstallation.getParentLibPath()); - llvm::sys::path::append(Path, ".."); - GCCToolchainDir = Path.c_str(); - - for (auto *A : Args) { - std::string Str = A->getAsString(Args); - if (!Str.compare("-mlongcalls")) - A->claim(); - if (!Str.compare("-fno-tree-switch-conversion")) - A->claim(); + if (GCCInstallation.isValid()) { + for (auto *A : Args) { + std::string Str = A->getAsString(Args); + if (!Str.compare("-mlongcalls")) + A->claim(); + if (!Str.compare("-fno-tree-switch-conversion")) + A->claim(); + + // Currently don't use integrated assembler for assembler input files + if ((IsIntegratedAsm) && (Str.length() > 2)) { + std::string ExtSubStr = Str.substr(Str.length() - 2); + if (!ExtSubStr.compare(".s")) + IsIntegratedAsm = false; + if (!ExtSubStr.compare(".S")) + IsIntegratedAsm = false; + } + } // Currently don't use integrated assembler for assembler input files - if ((IsIntegratedAsm) && (Str.length() > 2)) { - std::string ExtSubStr = Str.substr(Str.length() - 2); - if (!ExtSubStr.compare(".s")) + if (IsIntegratedAsm) { + if (Args.getLastArgValue(options::OPT_x).equals("assembler")) IsIntegratedAsm = false; - if (!ExtSubStr.compare(".S")) + + if (Args.getLastArgValue(options::OPT_x).equals("assembler-with-cpp")) IsIntegratedAsm = false; } - } - // Currently don't use integrated assembler for assembler input files - if (IsIntegratedAsm) { - if (Args.getLastArgValue(options::OPT_x).equals("assembler")) - IsIntegratedAsm = false; - - if (Args.getLastArgValue(options::OPT_x).equals("assembler-with-cpp")) - IsIntegratedAsm = false; + Multilibs = GCCInstallation.getMultilibs(); + SelectedMultilibs.assign({GCCInstallation.getMultilib()}); + + GCCLibAndIncVersion = GCCInstallation.getVersion().Text; + GCCToolchainName = GCCInstallation.getTriple().str(); + SmallString<128> Path(GCCInstallation.getParentLibPath()); + llvm::sys::path::append(Path, ".."); + GCCToolchainDir = Path.c_str(); + + SmallString<128> Libs1(GCCToolchainDir); + llvm::sys::path::append(Libs1, "lib", "gcc", GCCToolchainName, + GCCLibAndIncVersion); + if (!SelectedMultilibs.back().gccSuffix().empty()) + llvm::sys::path::append(Libs1, SelectedMultilibs.back().gccSuffix()); + getFilePaths().push_back(Libs1.c_str()); + + SmallString<128> Libs2(GCCToolchainDir); + llvm::sys::path::append(Libs2, GCCToolchainName, "lib"); + if (!SelectedMultilibs.back().gccSuffix().empty()) + llvm::sys::path::append(Libs2, SelectedMultilibs.back().gccSuffix()); + getFilePaths().push_back(Libs2.c_str()); + + ToolChain::path_list &PPaths = getProgramPaths(); + // Multilib cross-compiler GCC installations put ld in a triple-prefixed + // directory of the GCC installation parent dir. + StringRef ParentDir = llvm::sys::path::parent_path(GCCInstallation.getParentLibPath()); + + SmallString<128> PathTripleBin(ParentDir); + llvm::sys::path::append(PathTripleBin, GCCInstallation.getTriple().str()); + llvm::sys::path::append(PathTripleBin, "bin"); + PPaths.push_back(PathTripleBin.c_str()); + + SmallString<128> PathBin(ParentDir); + llvm::sys::path::append(PathBin, "bin"); + PPaths.push_back(PathBin.c_str()); + + if (!getDriver().SysRoot.empty()) { + SmallString<128> SysRoot(computeSysRoot()); + llvm::sys::path::append(SysRoot, "lib"); + getFilePaths().push_back(SysRoot.c_str()); + } + } else { + getProgramPaths().push_back(D.Dir); + SmallString<128> SysRoot(computeSysRoot()); + llvm::sys::path::append(SysRoot, "lib"); + getFilePaths().push_back(SysRoot.c_str()); } - - SmallString<128> Libs1(GCCToolchainDir); - llvm::sys::path::append(Libs1, "lib", "gcc", GCCToolchainName, - GCCLibAndIncVersion); - if (!SelectedMultilibs.back().gccSuffix().empty()) - llvm::sys::path::append(Libs1, SelectedMultilibs.back().gccSuffix()); - getFilePaths().push_back(Libs1.c_str()); - - SmallString<128> Libs2(GCCToolchainDir); - llvm::sys::path::append(Libs2, GCCToolchainName, "lib"); - if (!SelectedMultilibs.back().gccSuffix().empty()) - llvm::sys::path::append(Libs2, SelectedMultilibs.back().gccSuffix()); - getFilePaths().push_back(Libs2.c_str()); } Tool *XtensaToolChain::buildLinker() const { @@ -105,18 +128,25 @@ void XtensaToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, DriverArgs.hasArg(options::OPT_nostdlibinc)) return; - if (!GCCInstallation.isValid()) - return; - - SmallString<128> Path1(getDriver().ResourceDir); - llvm::sys::path::append(Path1, "include"); - SmallString<128> Path2(GCCToolchainDir); - llvm::sys::path::append(Path2, GCCToolchainName, "sys-include"); - SmallString<128> Path3(GCCToolchainDir); - llvm::sys::path::append(Path3, GCCToolchainName, "include"); - - const StringRef Paths[] = {Path1, Path2, Path3}; - addSystemIncludes(DriverArgs, CC1Args, Paths); + if (!getDriver().SysRoot.empty()) { + SmallString<128> Dir(getDriver().SysRoot); + llvm::sys::path::append(Dir, "include"); + addSystemInclude(DriverArgs, CC1Args, Dir.str()); + } else if (GCCInstallation.isValid()) { + SmallString<128> Path1(getDriver().ResourceDir); + llvm::sys::path::append(Path1, "include"); + SmallString<128> Path2(GCCToolchainDir); + llvm::sys::path::append(Path2, GCCToolchainName, "sys-include"); + SmallString<128> Path3(GCCToolchainDir); + llvm::sys::path::append(Path3, GCCToolchainName, "include"); + + const StringRef Paths[] = {Path1, Path2, Path3}; + addSystemIncludes(DriverArgs, CC1Args, Paths); + } else { + SmallString<128> Dir(computeSysRoot()); + llvm::sys::path::append(Dir, "include"); + addSystemInclude(DriverArgs, CC1Args, Dir.str()); + } } void XtensaToolChain::addLibStdCxxIncludePaths( @@ -125,17 +155,32 @@ void XtensaToolChain::addLibStdCxxIncludePaths( if (!GCCInstallation.isValid()) return; - SmallString<128> BaseDir(GCCToolchainDir); - llvm::sys::path::append(BaseDir, GCCToolchainName, "include", "c++", - GCCLibAndIncVersion); - SmallString<128> TargetDir(BaseDir); - llvm::sys::path::append(TargetDir, GCCToolchainName); - SmallString<128> TargetDirBackward(BaseDir); - llvm::sys::path::append(TargetDirBackward, "backward"); - - addLibStdCXXIncludePaths(BaseDir, "", "", DriverArgs, CC1Args); - addLibStdCXXIncludePaths(TargetDir, "", "", DriverArgs, CC1Args); - addLibStdCXXIncludePaths(TargetDirBackward, "", "", DriverArgs, CC1Args); + const GCCVersion &Version = GCCInstallation.getVersion(); + StringRef TripleStr = GCCInstallation.getTriple().str(); + addLibStdCXXIncludePaths(computeSysRoot() + "/include/c++/" + Version.Text, + TripleStr, "", DriverArgs, CC1Args); +} + +std::string XtensaToolChain::computeSysRoot() const { + if (!getDriver().SysRoot.empty()) + return getDriver().SysRoot; + + SmallString<128> SysRootDir; + if (GCCInstallation.isValid()) { + StringRef LibDir = GCCInstallation.getParentLibPath(); + StringRef TripleStr = GCCInstallation.getTriple().str(); + llvm::sys::path::append(SysRootDir, LibDir, "..", TripleStr); + } else { + // Use the triple as provided to the driver. Unlike the parsed triple + // this has not been normalized to always contain every field. + llvm::sys::path::append(SysRootDir, getDriver().Dir, "..", + getDriver().getTargetTriple()); + } + + if (!llvm::sys::fs::exists(SysRootDir)) + return std::string(); + + return std::string(SysRootDir.str()); } ToolChain::CXXStdlibType @@ -172,9 +217,6 @@ void tools::xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, const auto &TC = static_cast(getToolChain()); - if (TC.GCCToolchainName == "") - llvm_unreachable("Unable to find Xtensa GCC assembler"); - claimNoWarnArgs(Args); ArgStringList CmdArgs; @@ -218,17 +260,18 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, bool WantCRTs = !Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles); const auto &ToolChain = - static_cast(getToolChain()); + static_cast(getToolChain()); + const Driver &D = ToolChain.getDriver(); - if (ToolChain.GCCToolchainName == "") - llvm_unreachable("Unable to find Xtensa GCC linker"); + if (!D.SysRoot.empty()) + CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot)); - if (!Args.getLastArgValue(options::OPT_fuse_ld_EQ).empty()) { - Linker.assign(ToolChain.GetLinkerPath()); - } else { + if (ToolChain.GCCToolchainName != "") { Linker.assign(ToolChain.GCCToolchainDir); llvm::sys::path::append(Linker, "bin", ToolChain.GCCToolchainName + "-" + getShortName()); + } else { + Linker.assign(ToolChain.GetLinkerPath()); } const char *crtbegin, *crtend; @@ -237,17 +280,17 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, crtbegin = "crtbegin.o"; crtend = "crtend.o"; } else { - assert (RuntimeLib == ToolChain::RLT_CompilerRT); + assert(RuntimeLib == ToolChain::RLT_CompilerRT); crtbegin = ToolChain.getCompilerRTArgString(Args, "crtbegin", ToolChain::FT_Object); - crtend = ToolChain.getCompilerRTArgString(Args, "crtend", - ToolChain::FT_Object); + crtend = + ToolChain.getCompilerRTArgString(Args, "crtend", ToolChain::FT_Object); } if (WantCRTs) { // TODO: The crt0.o is not used for esp targets, but maybe used in // future for other vendors - //CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); + // CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin))); } @@ -258,7 +301,7 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, Args.addAllArgs(CmdArgs, {options::OPT_T_Group, options::OPT_e, options::OPT_s, options::OPT_t, options::OPT_u_Group}); - + if (!Args.hasArg(options::OPT_nostdlib) && !Args.hasArg(options::OPT_nodefaultlibs)) { if (ToolChain.ShouldLinkCXXStdlib(Args)) @@ -271,9 +314,9 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-o"); CmdArgs.push_back(Output.getFilename()); - C.addCommand(std::make_unique( - JA, *this, ResponseFileSupport::AtFileCurCP(), Args.MakeArgString(Linker), - CmdArgs, Inputs)); + C.addCommand( + std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), + Args.MakeArgString(Linker), CmdArgs, Inputs)); } // Get features by CPU name diff --git a/clang/lib/Driver/ToolChains/Xtensa.h b/clang/lib/Driver/ToolChains/Xtensa.h index 38f8f1b2c8d5f9..bef3883742db5b 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.h +++ b/clang/lib/Driver/ToolChains/Xtensa.h @@ -47,6 +47,9 @@ class LLVM_LIBRARY_VISIBILITY XtensaToolChain : public Generic_ELF { std::string GCCLibAndIncVersion = ""; std::string GCCToolchainName = ""; std::string GCCToolchainDir = ""; + +private: + std::string computeSysRoot() const override; }; } // end namespace toolchains diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0/.keep b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0/.keep new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/xtensa-toolchain.c b/clang/test/Driver/xtensa-toolchain.c index aa753abcf63667..7cf4f151de2fc2 100644 --- a/clang/test/Driver/xtensa-toolchain.c +++ b/clang/test/Driver/xtensa-toolchain.c @@ -91,3 +91,35 @@ // C-XTENSA-ESP32S3-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" // C-XTENSA-ESP32S3-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}8.4.0" // C-XTENSA-ESP32S3-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}lib" + +// RUN: %clang %s -### -no-canonical-prefixes \ +// RUN: -target xtensa-esp-elf -mcpu=esp32 --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree \ +// RUN: --sysroot=%S/Inputs/multilib_xtensa_tree/xtensa-esp32-elf 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-SYSROOT-BAREMETAL %s + +// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "--sysroot={{.*}}/Inputs/multilib_xtensa_tree/xtensa-esp32-elf" +// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" +// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" + +// RUN: %clang++ %s -### -no-canonical-prefixes \ +// RUN: -target xtensa-esp-elf -mcpu=esp32 -stdlib=libstdc++ --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=CXX-XTENSA-ESP32-BAREMETAL %s + +// CXX-XTENSA-ESP32-BAREMETAL: "-internal-isystem" "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf/include/c++{{/|\\\\}}8.4.0" +// CXX-XTENSA-ESP32-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" +// CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" + +// RUN: %clang++ %s -### -no-canonical-prefixes \ +// RUN: -target xtensa-esp-elf -mcpu=esp32 -stdlib=libstdc++ --rtlib=platform \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree \ +// RUN: --sysroot=%S/Inputs/multilib_xtensa_tree/xtensa-esp32-elf 2>&1 \ +// RUN: | FileCheck -check-prefix=CXX-XTENSA-ESP32-SYSROOT-BAREMETAL %s + +// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-internal-isystem" "{{.*}}Inputs/multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0" +// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" +// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" From 391f994f07b92b85320c07e9cf61687d196bfa30 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:06 +0300 Subject: [PATCH 101/261] [Xtensa] Fix crtbegin/crtend implementation. Add Xtensa to the list of arcthitectures with crt support in compiler_rt. --- compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake index 416777171d2ca7..594b8b4209c695 100644 --- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake +++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake @@ -16,6 +16,7 @@ set(SPARCV9 sparcv9) set(WASM32 wasm32) set(WASM64 wasm64) set(VE ve) +set(XTENSA xtensa) if(APPLE) set(ARM64 arm64) @@ -25,7 +26,7 @@ endif() set(ALL_SANITIZER_COMMON_SUPPORTED_ARCH ${X86} ${X86_64} ${PPC64} ${RISCV64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64} ${S390X} ${SPARC} ${SPARCV9} - ${HEXAGON} ${LOONGARCH64}) + ${HEXAGON} ${XTENSA} ${LOONGARCH64}) set(ALL_ASAN_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${RISCV64} ${MIPS32} ${MIPS64} ${PPC64} ${S390X} ${SPARC} ${SPARCV9} ${HEXAGON} ${LOONGARCH64}) From ded532a122a1924f4bb9d0dbe129fb5eafdd4e24 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:06 +0300 Subject: [PATCH 102/261] [Xtensa] Build compiler-rt libs. Include compiler-rt libs to the esp32 clang toolchains. --- .gitlab-ci.yml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 81bfcf25648bd5..7397e0c2d708cc 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -244,7 +244,14 @@ test_x86_64-linux-gnu: .get_gcc_toolchain_old: &get_gcc_toolchain_old | wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/${XTENSA_GCC_TOOLCHAIN} ${UNARCHIVE_TOOL} ${XTENSA_GCC_TOOLCHAIN} - mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} + if [[ "$XTENSA_GCC_TOOLCHAIN" == *"linux"* ]]; then + cp -r xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} + else + mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz + tar -xf xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz + fi + export GCC_ESP32_LINUX_TOOLCHAIN="xtensa-esp32-elf" .package_toolchain_old: &package_toolchain_old | ${ARCHIVE_TOOL} ${ARCHIVE_NAME} ${XTENSA_CLANG_TOOLCHAIN}/ @@ -261,7 +268,7 @@ test_x86_64-linux-gnu: when: always expire_in: 10 day variables: - XTENSA_CLANG_TOOLCHAIN_REF: "esp-20220415-r14.0.0" + XTENSA_CLANG_TOOLCHAIN_REF: "esp-20220708-r14.0.0" GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" script: - *get_release_name_old @@ -328,6 +335,9 @@ linux_amd64_testsuite: # run testsuite for esp32 - ./run_esp32_tests.sh + # run testsuite for compiler_rt library + - ./run_esp32_crt_tests.sh ../$XTENSA_CLANG_TOOLCHAIN + ##################### END OF TEMPORARY LEGACY CODE ######################## ########################################################################### From 2885ecc6ea04ab9ed5c1087e019020f48b615a4a Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:07 +0300 Subject: [PATCH 103/261] [Xtensa] Fix ill.n instruction econding --- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 2 +- llvm/test/MC/Xtensa/xtensa-valid-density.s | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 2a59d179761f06..9f234c7cb41e9c 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1494,7 +1494,7 @@ let isBarrier = 1, isTerminator = 1 in { let s = 0; } - def ILL_N : RRRN_Inst<0x0C, (outs), (ins), + def ILL_N : RRRN_Inst<0x0D, (outs), (ins), "ill.n", []>, Requires<[HasDensity]> { let r = 0xf; let s = 0x0; diff --git a/llvm/test/MC/Xtensa/xtensa-valid-density.s b/llvm/test/MC/Xtensa/xtensa-valid-density.s index fc5457ce82ddc6..f4315c61e8efd8 100644 --- a/llvm/test/MC/Xtensa/xtensa-valid-density.s +++ b/llvm/test/MC/Xtensa/xtensa-valid-density.s @@ -5,5 +5,5 @@ LBL0: # CHECK-INST: ill.n -# CHECK: encoding: [0x6c,0xf0] +# CHECK: encoding: [0x6d,0xf0] ill.n From c33a57be753b5ec2873c583e76e872926f6257c2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:07 +0300 Subject: [PATCH 104/261] ci: add jobs for arm64 toolchains --- .gitlab-ci.yml | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7397e0c2d708cc..1912cea3e4c7cb 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -21,6 +21,7 @@ variables: XTENSA_CLANG_TOOLCHAIN_REF: "release_universal_clang_14.0.0_gcc_8.4.0" LLVM_GCC_TESTSUITE_REF: "feature/toolchain_build_script" + PLATFORM_NAME_LINUX_ARM64: "linux-arm64" PLATFORM_NAME_LINUX: "linux-amd64" PLATFORM_NAME_WIN: "win64" PLATFORM_NAME_MACOS: "macos" @@ -244,7 +245,7 @@ test_x86_64-linux-gnu: .get_gcc_toolchain_old: &get_gcc_toolchain_old | wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/${XTENSA_GCC_TOOLCHAIN} ${UNARCHIVE_TOOL} ${XTENSA_GCC_TOOLCHAIN} - if [[ "$XTENSA_GCC_TOOLCHAIN" == *"linux"* ]]; then + if [[ "$XTENSA_GCC_TOOLCHAIN" == *"linux-amd64"* ]]; then cp -r xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} else mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} @@ -268,7 +269,7 @@ test_x86_64-linux-gnu: when: always expire_in: 10 day variables: - XTENSA_CLANG_TOOLCHAIN_REF: "esp-20220708-r14.0.0" + XTENSA_CLANG_TOOLCHAIN_REF: "esp-20220721-r14.0.0" GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" script: - *get_release_name_old @@ -288,6 +289,17 @@ linux_amd64_build: XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz" BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux.sh" +linux_arm64_build: + extends: .build_template_old + image: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-arm64.tar.gz" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux-arm64.sh" + win64_build: extends: .build_template_old variables: @@ -326,7 +338,7 @@ linux_amd64_testsuite: - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git # preparing testsuite - - export PATH=$PATH:${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/ + - export PATH=${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/:$PATH - cd llvm-xtensa-testsuite # qemu From ea0bf0c064ff3ce9e3e17276163782537c49dbc4 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:08 +0300 Subject: [PATCH 105/261] ci/cd: fix clang version in gitlab-ci.yml --- .gitlab-ci.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 1912cea3e4c7cb..6da427203109c3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -65,7 +65,7 @@ before_script: .get_release_name: &get_release_name | # using annotated tags REL_NUM=$(git describe --abbrev=7) - REL_SFX="llvm14_0_0" + REL_SFX="llvm15_0_0" REL_NAME=${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} echo "PLATFORM_NAME: $PLATFORM_NAME" @@ -234,7 +234,7 @@ test_x86_64-linux-gnu: .get_release_name_old: &get_release_name_old | # using annotated tags REL_NUM=$(git describe --abbrev=7) - REL_SFX="llvm14_0_0" + REL_SFX="llvm15_0_0" REL_NAME=${CONF_TARGET}-${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} echo "PLATFORM_NAME: $PLATFORM_NAME" @@ -269,7 +269,7 @@ test_x86_64-linux-gnu: when: always expire_in: 10 day variables: - XTENSA_CLANG_TOOLCHAIN_REF: "esp-20220721-r14.0.0" + XTENSA_CLANG_TOOLCHAIN_REF: "release_esp32_clang_15.0.0_gcc_8.4.0" GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" script: - *get_release_name_old From d15105ba10327f453a46bc0d28f779f8e4fe17bf Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Sep 2023 22:12:15 +0300 Subject: [PATCH 106/261] [Xtensa] fix compiler-rt crt build script --- compiler-rt/cmake/crt-config-ix.cmake | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler-rt/cmake/crt-config-ix.cmake b/compiler-rt/cmake/crt-config-ix.cmake index ebc7d671e74ee6..0897caabdef2e0 100644 --- a/compiler-rt/cmake/crt-config-ix.cmake +++ b/compiler-rt/cmake/crt-config-ix.cmake @@ -31,10 +31,11 @@ set(PPC64 powerpc64 powerpc64le) set(RISCV32 riscv32) set(RISCV64 riscv64) set(VE ve) +set(XTENSA xtensa) set(ALL_CRT_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${PPC32} ${PPC64} ${RISCV32} ${RISCV64} ${VE} ${HEXAGON} ${LOONGARCH64} - ${MIPS32} ${MIPS64} ${SPARC} ${SPARCV9}) + ${MIPS32} ${MIPS64} ${SPARC} ${SPARCV9} ${XTENSA}) include(CompilerRTUtils) From 42f1d83c6421ed74effdf72a1fc8356fe79a8730 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:09 +0300 Subject: [PATCH 107/261] [Xtensa] Implement asm macro for bbci/bbsi. Add bbci.l macro for bbci instructon and bbsi.l for bbsi. --- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 4 ++++ llvm/test/MC/Xtensa/Core/branch.s | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 9f234c7cb41e9c..db9f411ae91388 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -433,6 +433,8 @@ def BBCI : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"bbci.l\t$s, $imm, $target", (BBCI AR:$s, uimm5:$imm, brtarget:$target)>; + def BBSI : RRI8_Inst<0x07, (outs), (ins AR:$s, uimm5:$imm, brtarget:$target), "bbsi\t$s, $imm, $target", []> { @@ -445,6 +447,8 @@ def BBSI : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"bbsi.l\t$s, $imm, $target", (BBSI AR:$s, uimm5:$imm, brtarget:$target)>; + def : Pat<(brcc SETGT, AR:$s, AR:$t, bb:$target), (BLT AR:$t, AR:$s, bb:$target)>; def : Pat<(brcc SETUGT, AR:$s, AR:$t, bb:$target), diff --git a/llvm/test/MC/Xtensa/Core/branch.s b/llvm/test/MC/Xtensa/Core/branch.s index 7e9ba5f713345d..66b68a610c1d25 100644 --- a/llvm/test/MC/Xtensa/Core/branch.s +++ b/llvm/test/MC/Xtensa/Core/branch.s @@ -29,6 +29,10 @@ bbci a3, 16, LBL0 # CHECK: encoding: [0x07,0x73,A] bbci a3, (16), LBL0 +# CHECK-INST: bbci a3, 16, LBL0 +# CHECK: encoding: [0x07,0x73,A] +bbci.l a3, 16, LBL0 + # Instruction format RRI8 # CHECK-INST: bbs a12, a5, LBL0 # CHECK: encoding: [0x57,0xdc,A] @@ -39,6 +43,10 @@ bbs a12, a5, LBL0 # CHECK: encoding: [0x07,0xf3,A] bbsi a3, 16, LBL0 +# CHECK-INST: bbsi a3, 16, LBL0 +# CHECK: encoding: [0x07,0xf3,A] +bbsi.l a3, 16, LBL0 + # Instruction format RRI8 # CHECK-INST: bnall a7, a3, LBL0 # CHECK: encoding: [0x37,0xc7,A] From d94a95aefee7394f7ccc20047b31938c17db1e5b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Sep 2023 23:00:40 +0300 Subject: [PATCH 108/261] [Xtensa] Implement support of literal and region asm directives in asm parser. Implement support of the ".literal" and ".literal_postion" directives in asm parser. Implement support of the regions using ".begin" and ".end" directives, currently only "literal_prefix" region is supported. --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 162 +++++++++++++++++- .../MCTargetDesc/XtensaTargetStreamer.cpp | 42 +++-- .../MCTargetDesc/XtensaTargetStreamer.h | 4 + llvm/test/MC/Xtensa/directive-literal.s | 23 +++ llvm/test/MC/Xtensa/directive-region.s | 25 +++ 5 files changed, 240 insertions(+), 16 deletions(-) create mode 100644 llvm/test/MC/Xtensa/directive-literal.s create mode 100644 llvm/test/MC/Xtensa/directive-region.s diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 9d7bb37fa6add0..57509e6ff2aaed 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -24,6 +24,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Casting.h" @@ -34,6 +35,21 @@ using namespace llvm; struct XtensaOperand; class XtensaAsmParser : public MCTargetAsmParser { + // Xtensa GNU assembler supports region definitions using + // .begin and .end directives. Currently only .literal_prefix regions are + // supported. + struct RegionInfo { + public: + SMLoc Loc; + StringRef RegionDirectiveName; + StringRef LiteralPrefixName; + RegionInfo() = default; + RegionInfo( SMLoc L, StringRef DirectiveName, StringRef Name = "") + : Loc(L), RegionDirectiveName(DirectiveName), LiteralPrefixName(Name) {} + }; + + // Stack of active region definitions. + SmallVector RegionInProgress; SMLoc getLoc() const { return getParser().getTok().getLoc(); } @@ -54,6 +70,7 @@ class XtensaAsmParser : public MCTargetAsmParser { bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); + bool ParseDirective(AsmToken DirectiveID) override; // Auto-generated instruction matching functions #define GET_ASSEMBLER_HEADER @@ -74,6 +91,14 @@ class XtensaAsmParser : public MCTargetAsmParser { } ParseStatus parsePCRelTarget(OperandVector &Operands); bool checkRegister(unsigned RegNo); + bool parseLiteralDirective(SMLoc L); + bool parseBeginDirective(SMLoc L); + bool parseEndDirective(SMLoc L); + void onEndOfFile() override { + if (!RegionInProgress.empty()) { + Error(RegionInProgress.back().Loc, ".end of region is not found"); + } + } public: enum XtensaMatchResultTy { @@ -926,7 +951,142 @@ bool XtensaAsmParser::ParseInstruction(ParseInstructionInfo &Info, getParser().Lex(); // Consume the EndOfStatement. return false; } - + +bool XtensaAsmParser::parseLiteralDirective(SMLoc L) { + MCAsmParser &Parser = getParser(); + MCSymbol *Sym; + const MCExpr *Value; + SMLoc LiteralLoc = getLexer().getLoc(); + XtensaTargetStreamer &TS = this->getTargetStreamer(); + + if (Parser.parseExpression(Value)) + return true; + + const MCSymbolRefExpr *SE = dyn_cast(Value); + if (!SE) + return Error(LiteralLoc, "literal label must be a symbol"); + else { + Sym = getContext().getOrCreateSymbol(SE->getSymbol().getName()); + } + + if (Parser.parseToken(AsmToken::Comma, "expected comma")) + return true; + + SMLoc OpcodeLoc = getLexer().getLoc(); + if (parseOptionalToken(AsmToken::EndOfStatement)) + return Error(OpcodeLoc, "expected value"); + + if (Parser.parseExpression(Value)) + return true; + + TS.emitLiteralLabel(Sym, LiteralLoc); + TS.emitLiteral(Value, LiteralLoc); + + return false; +} + +bool XtensaAsmParser::parseBeginDirective(SMLoc L) { + MCAsmParser &Parser = getParser(); + const MCExpr *Value; + SMLoc BeginLoc = getLexer().getLoc(); + XtensaTargetStreamer &TS = this->getTargetStreamer(); + + if (Parser.parseExpression(Value)) + return true; + + const MCSymbolRefExpr *SE = dyn_cast(Value); + if (!SE) + return Error(BeginLoc, "region option must be a symbol"); + + StringRef RegionDirectiveName = SE->getSymbol().getName(); + + if (RegionDirectiveName == "literal_prefix") { + + SMLoc OpcodeLoc = getLexer().getLoc(); + if (parseOptionalToken(AsmToken::EndOfStatement)) + return Error(OpcodeLoc, "expected literal section name"); + + if (Parser.parseExpression(Value)) + return true; + + OpcodeLoc = getLexer().getLoc(); + SE = dyn_cast(Value); + if (!SE) + return Error(OpcodeLoc, "literal_prefix name must be a symbol"); + + StringRef LiteralPrefixName = SE->getSymbol().getName(); + TS.setLiteralSectionPrefix(LiteralPrefixName); + RegionInProgress.emplace_back(BeginLoc, RegionDirectiveName, LiteralPrefixName); + } else { + return Error(BeginLoc, "unsupported region directive"); + } + + return false; +} + +bool XtensaAsmParser::parseEndDirective(SMLoc L) { + MCAsmParser &Parser = getParser(); + const MCExpr *Value; + SMLoc EndLoc = getLexer().getLoc(); + XtensaTargetStreamer &TS = this->getTargetStreamer(); + + if (Parser.parseExpression(Value)) + return true; + + const MCSymbolRefExpr *SE = dyn_cast(Value); + if (!SE) + return Error(EndLoc, "region option must be a symbol"); + + StringRef RegionDirectiveName = SE->getSymbol().getName(); + + if (RegionInProgress.empty()) + return Error(EndLoc, ".end of the region without .begin"); + else { + RegionInfo Region = RegionInProgress.pop_back_val(); + + if (RegionInProgress.empty()) + TS.setLiteralSectionPrefix(""); + else + TS.setLiteralSectionPrefix(Region.LiteralPrefixName); + + if (RegionDirectiveName != Region.RegionDirectiveName) { + return Error(EndLoc, ".end directive differs from .begin directive"); + } + } + + // Error: does not match begin literal_prefix + return false; +} + +bool XtensaAsmParser::ParseDirective(AsmToken DirectiveID) { + StringRef IDVal = DirectiveID.getString(); + SMLoc Loc = getLexer().getLoc(); + + if (IDVal == ".literal_position") { + // We currently push literals in literal section which name depends on name + // of the current section. + // So, assume that we may skip this directive. + return false; + } + + if (IDVal == ".literal") { + parseLiteralDirective(Loc); + return false; + } + + if (IDVal == ".begin") { + parseBeginDirective(Loc); + return false; + } + + if (IDVal == ".end") { + parseEndDirective(Loc); + return false; + } + + return true; +} + // Verify SR and UR bool XtensaAsmParser::checkRegister(unsigned RegNo) { StringRef CPU = getSTI().getCPU(); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp index 645491d8f97117..134193821c85bf 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp @@ -38,16 +38,22 @@ XtensaTargetELFStreamer::XtensaTargetELFStreamer(MCStreamer &S) void XtensaTargetELFStreamer::emitLiteralLabel(MCSymbol *LblSym, SMLoc L) { MCContext &Context = getStreamer().getContext(); MCStreamer &OutStreamer = getStreamer(); - MCSectionELF *CS = (MCSectionELF *)OutStreamer.getCurrentSectionOnly(); - std::string CSectionName = CS->getName().str(); - std::size_t Pos = CSectionName.find(".text"); + StringRef LiteralSectionPrefix = getLiteralSectionPrefix(); std::string SectionName; - if (Pos != std::string::npos) { - SectionName = ".literal"; - SectionName += CSectionName.substr(Pos); + + if (LiteralSectionPrefix != "") { + SectionName = LiteralSectionPrefix.str() + ".literal"; } else { - SectionName = CSectionName; - SectionName += ".literal"; + MCSectionELF *CS = (MCSectionELF *)OutStreamer.getCurrentSectionOnly(); + std::string CSectionName = CS->getName().str(); + std::size_t Pos = CSectionName.find(".text"); + if (Pos != std::string::npos) { + SectionName = ".literal"; + SectionName += CSectionName.substr(Pos); + } else { + SectionName = CSectionName; + SectionName += ".literal"; + } } MCSection *ConstSection = Context.getELFSection( @@ -72,15 +78,21 @@ void XtensaTargetELFStreamer::emitLiteral(const MCExpr *Value, SMLoc L) { MCContext &Context = getStreamer().getContext(); MCStreamer &OutStreamer = getStreamer(); MCSectionELF *CS = (MCSectionELF *)OutStreamer.getCurrentSectionOnly(); - std::string CSectionName = CS->getName().str(); - std::size_t Pos = CSectionName.find(".text"); + StringRef LiteralSectionPrefix = getLiteralSectionPrefix(); std::string SectionName; - if (Pos != std::string::npos) { - SectionName = ".literal"; - SectionName += CSectionName.substr(Pos); + + if (LiteralSectionPrefix != "") { + SectionName = LiteralSectionPrefix.str() + ".literal"; } else { - SectionName = CSectionName; - SectionName += ".literal"; + std::string CSectionName = CS->getName().str(); + std::size_t Pos = CSectionName.find(".text"); + if (Pos != std::string::npos) { + SectionName = ".literal"; + SectionName += CSectionName.substr(Pos); + } else { + SectionName = CSectionName; + SectionName += ".literal"; + } } MCSection *ConstSection = Context.getELFSection( diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h index 962da002a997d9..ef03578862a26e 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h @@ -20,12 +20,16 @@ namespace llvm { class formatted_raw_ostream; class XtensaTargetStreamer : public MCTargetStreamer { + StringRef LiteralSectionPrefix = ""; + public: XtensaTargetStreamer(MCStreamer &S); virtual void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, SMLoc L) = 0; virtual void emitLiteralLabel(MCSymbol *LblSym, SMLoc L) = 0; virtual void emitLiteral(const MCExpr *Value, SMLoc L) = 0; virtual void emitLiteral(std::string str) = 0; + void setLiteralSectionPrefix(StringRef Name) { LiteralSectionPrefix = Name; } + StringRef getLiteralSectionPrefix() { return LiteralSectionPrefix; } }; class XtensaTargetAsmStreamer : public XtensaTargetStreamer { diff --git a/llvm/test/MC/Xtensa/directive-literal.s b/llvm/test/MC/Xtensa/directive-literal.s new file mode 100644 index 00000000000000..cc2fccdb61c895 --- /dev/null +++ b/llvm/test/MC/Xtensa/directive-literal.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple xtensa-esp-elf -filetype obj -o - %s \ +# RUN: | llvm-readobj -S --sd - \ +# RUN: | FileCheck %s + + .text + .literal_position + .literal .LCPI0_0, 305419896 + .global test_literal + .p2align 2 + .type test_literal,@function +test_literal: +# %bb.0: + entry a1, 32 + mov.n a7, a1 + l32r a2, .LCPI0_0 + retw.n + +# CHECK: Section { +# CHECK: Name: .literal.text +# CHECK: SectionData ( +# CHECK: 0000: 78563412 +# CHECK: ) +# CHECK: } \ No newline at end of file diff --git a/llvm/test/MC/Xtensa/directive-region.s b/llvm/test/MC/Xtensa/directive-region.s new file mode 100644 index 00000000000000..ca62571c31221d --- /dev/null +++ b/llvm/test/MC/Xtensa/directive-region.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple xtensa-esp-elf -filetype obj -o - %s \ +# RUN: | llvm-readobj -S --sd - \ +# RUN: | FileCheck %s + + .text + .begin literal_prefix .ExceptionVector + .literal_position + .literal .LCPI0_0, 305419896 + .global test_literal + .p2align 2 + .type test_literal,@function +test_literal: +# %bb.0: + entry a1, 32 + mov.n a7, a1 + l32r a2, .LCPI0_0 + retw.n + .end literal_prefix + +# CHECK: Section { +# CHECK: Name: .ExceptionVector.literal +# CHECK: SectionData ( +# CHECK: 0000: 78563412 +# CHECK: ) +# CHECK: } \ No newline at end of file From 72519bd2128a1824a6631e1f7d23beb4e5f9f539 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:10 +0300 Subject: [PATCH 109/261] [Xtensa] Corrected asm parser. Expand addi operation immediate, to addmi + addi. Improved constants evalutaion. --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 75 +++++++++++++++---- .../Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp | 4 +- llvm/test/MC/Xtensa/Core/arith.s | 10 +++ llvm/test/MC/Xtensa/Core/invalid.s | 10 +-- llvm/test/MC/Xtensa/Core/processor-control.s | 4 + 5 files changed, 84 insertions(+), 19 deletions(-) diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 57509e6ff2aaed..4c899105c21824 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -111,6 +111,10 @@ class XtensaAsmParser : public MCTargetAsmParser { XtensaAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, STI, MII) { + Parser.addAliasForDirective(".half", ".2byte"); + Parser.addAliasForDirective(".hword", ".2byte"); + Parser.addAliasForDirective(".word", ".4byte"); + Parser.addAliasForDirective(".dword", ".8byte"); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } @@ -256,7 +260,10 @@ struct XtensaOperand : public MCParsedAsmOperand { return Kind == Immediate && inRange(getImm(), MinValue, MaxValue); } - bool isImm8() const { return isImm(-128, 127); } + bool isImm8() const { + //The addi instruction maybe expaned to addmi and addi. + return isImm((-32768 - 128), (32512 + 127)); + } bool isImm8_sh8() const { return isImm(-32768, 32512) && @@ -267,10 +274,10 @@ struct XtensaOperand : public MCParsedAsmOperand { // Convert MOVI to literal load, when immediate is not in range (-2048, 2047) bool isImm12m() const { - //Process special case when operand is symbol - if ((Kind == Immediate) && (getImm()->getKind() == MCExpr::SymbolRef)) - return true; - return isImm(LONG_MIN, LONG_MAX); + if (Kind == Immediate) + return true; + + return false; } bool isOffset4m32() const { @@ -493,6 +500,40 @@ bool XtensaAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, const unsigned Opcode = Inst.getOpcode(); switch (Opcode) { + case Xtensa::ADDI: { + int64_t Imm = Inst.getOperand(2).getImm(); + // Expand 16-bit immediate in ADDI instruction: + // ADDI rd, rs, imm - > ADMI rd, rs, (imm & 0xff00); ADDI rd, rd, (imm & 0xff) + if ((Imm < -128) || (Imm > 127)) { + unsigned DReg = Inst.getOperand(0).getReg(); + unsigned SReg = Inst.getOperand(1).getReg(); + MCInst ADDMIInst; + MCInst ADDIInst; + int64_t ImmHi = Imm & (~((uint64_t)0xff)); + int64_t ImmLo = Imm & 0xff; + + if (ImmLo > 127) { + ImmHi += 0x100; + ImmLo = ImmLo - 0x100; + } + + ADDMIInst.setOpcode(Xtensa::ADDMI); + ADDMIInst.addOperand(MCOperand::createReg(DReg)); + ADDMIInst.addOperand(MCOperand::createReg(SReg)); + ADDMIInst.addOperand(MCOperand::createImm(ImmHi)); + ADDMIInst.setLoc(IDLoc); + + Out.emitInstruction(ADDMIInst, *STI); + + ADDIInst.setOpcode(Xtensa::ADDI); + ADDIInst.addOperand(MCOperand::createReg(DReg)); + ADDIInst.addOperand(MCOperand::createReg(DReg)); + ADDIInst.addOperand(MCOperand::createImm(ImmLo)); + ADDIInst.setLoc(IDLoc); + + Inst = ADDIInst; + } + } break; case Xtensa::L32R: { const MCSymbolRefExpr *OpExpr = (const MCSymbolRefExpr *)Inst.getOperand(1).getExpr(); @@ -589,7 +630,7 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } case Match_InvalidImm8: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), - "expected immediate in range [-128, 127]"); + "expected immediate in range [-32896, 32639]"); case Match_InvalidImm8_sh8: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [-32768, 32512], first 8 bits " @@ -701,6 +742,7 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, AsmToken Buf[2]; std::string RegName = ""; int64_t Num; + bool IsIdentifier = false; // If this a parenthesised register name is allowed, parse it atomically if (AllowParens && getLexer().is(AsmToken::LParen)) { @@ -719,10 +761,17 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, default: return ParseStatus::NoMatch; case AsmToken::Integer: + case AsmToken::LParen: if ((!SR) && (!UR)) return ParseStatus::NoMatch; + const MCExpr *Res; + + if (getParser().parseExpression(Res)) + return ParseStatus::Failure; + + if (!Res->evaluateAsAbsolute(Num)) + return ParseStatus::NoMatch; - Num = getLexer().getTok().getIntVal(); // Parse case when we expect UR operand as special case, // because SR and UR registers may have the same number // and such situation may lead to confilct @@ -750,6 +799,7 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, RegNo = MatchRegisterAltName(RegName); break; case AsmToken::Identifier: + IsIdentifier = true; RegName = getLexer().getTok().getIdentifier().str(); RegNo = MatchRegisterName(RegName); if (RegNo == 0) @@ -771,7 +821,10 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, Operands.push_back(XtensaOperand::createToken("(", FirstS)); SMLoc S = getLoc(); SMLoc E = getParser().getTok().getEndLoc(); - getLexer().Lex(); + + if (IsIdentifier) + getLexer().Lex(); + Operands.push_back(XtensaOperand::createReg(RegNo, S, E)); if (HadParens) { @@ -800,12 +853,8 @@ ParseStatus XtensaAsmParser::parseImmediate(OperandVector &Operands) { return ParseStatus::Failure; break; case AsmToken::Identifier: { - StringRef Identifier; - if (getParser().parseIdentifier(Identifier)) + if (getParser().parseExpression(Res)) return ParseStatus::Failure; - - MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); - Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); break; } case AsmToken::Percent: diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp index 28764d369247a7..4537369b017d0f 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp @@ -23,10 +23,12 @@ XtensaMCAsmInfo::XtensaMCAsmInfo(const Triple &TT) { PrivateGlobalPrefix = ".L"; CommentString = "#"; ZeroDirective = "\t.space\t"; + Data16bitsDirective = "\t.half\t"; + Data32bitsDirective = "\t.word\t"; Data64bitsDirective = "\t.quad\t"; GlobalDirective = "\t.global\t"; UsesELFSectionDirectiveForBSS = true; SupportsDebugInformation = true; ExceptionsType = ExceptionHandling::DwarfCFI; - AlignmentIsInBytes = false; + AlignmentIsInBytes = true; } diff --git a/llvm/test/MC/Xtensa/Core/arith.s b/llvm/test/MC/Xtensa/Core/arith.s index 2f3146b9533c94..fb6ac2608b0a93 100644 --- a/llvm/test/MC/Xtensa/Core/arith.s +++ b/llvm/test/MC/Xtensa/Core/arith.s @@ -27,6 +27,16 @@ addi a8, sp, -128 # CHECK-INST: addi a8, a1, -12 # CHECK: encoding: [0x82,0xc1,0xf4] addi a8, a1, -12 +# CHECK-INST: addmi a8, a1, 256 +# CHECK: encoding: [0x82,0xd1,0x01] +# CHECK-INST: addi a8, a8, 0 +# CHECK: encoding: [0x82,0xc8,0x00] +addi a8, a1, 256 +# CHECK-INST: addmi a8, a1, -9984 +# CHECK: encoding: [0x82,0xd1,0xd9] +# CHECK-INST: addi a8, a8, -16 +# CHECK: encoding: [0x82,0xc8,0xf0] +addi a8, a1, -10000 # Instruction format RRI8 # CHECK-INST: addmi a1, a2, 32512 diff --git a/llvm/test/MC/Xtensa/Core/invalid.s b/llvm/test/MC/Xtensa/Core/invalid.s index c7473e90c10ba3..7fc7b47db1337e 100644 --- a/llvm/test/MC/Xtensa/Core/invalid.s +++ b/llvm/test/MC/Xtensa/Core/invalid.s @@ -5,12 +5,12 @@ LBL0: # Out of range immediates # imm8 -addi a1, a2, 300 -# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-128, 127] +addi a1, a2, -33000 +# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-32896, 32639] # imm8 -addi a1, a2, -129 -# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-128, 127] +addi a1, a2, 34000 +# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-32896, 32639] # imm8_sh8 addmi a1, a2, 33 @@ -66,7 +66,7 @@ aaa a10, a12 and sp, a2, 10 # CHECK: :[[#@LINE-1]]:13: error: invalid operand for instruction addi sp, a1, a2 -# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-128, 127] +# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-32896, 32639] # Check invalid register names for different formats # Instruction format RRR diff --git a/llvm/test/MC/Xtensa/Core/processor-control.s b/llvm/test/MC/Xtensa/Core/processor-control.s index ebbc577db77226..6295786dfb61af 100644 --- a/llvm/test/MC/Xtensa/Core/processor-control.s +++ b/llvm/test/MC/Xtensa/Core/processor-control.s @@ -68,6 +68,10 @@ wsr.sar a8 # CHECK: encoding: [0x80,0x03,0x13] wsr a8, 3 +# CHECK-INST: wsr a8, sar +# CHECK: encoding: [0x80,0x03,0x13] +wsr a8, (2 + 1) + # Instruction format RRR # CHECK-INST: xsr a8, sar # CHECK: encoding: [0x80,0x03,0x61] From 538da6cb3b1e3b18896d9108c9c4f39dc28b2b6b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Sep 2023 01:19:34 +0300 Subject: [PATCH 110/261] riscv/gnu: Adds `no-rtti` multilib support --- clang/lib/Driver/ToolChains/Gnu.cpp | 41 ++++++++++++++++--- .../8.4.0/rv32i/ilp32/no-rtti/crtbegin.o | 0 .../8.4.0/rv32i/ilp32/no-rtti/crtend.o | 0 .../8.4.0/rv32imac/ilp32/no-rtti/crtbegin.o | 0 .../8.4.0/rv32imac/ilp32/no-rtti/crtend.o | 0 .../8.4.0/rv32imafc/ilp32f/no-rtti/crtbegin.o | 0 .../8.4.0/rv32imafc/ilp32f/no-rtti/crtend.o | 0 .../8.4.0/rv32imc/ilp32/no-rtti/crtbegin.o | 0 .../8.4.0/rv32imc/ilp32/no-rtti/crtend.o | 0 .../lib/rv32i/ilp32/no-rtti/crt0.o | 0 .../lib/rv32imac/ilp32/no-rtti/crt0.o | 0 .../lib/rv32imafc/ilp32f/no-rtti/crt0.o | 0 .../lib/rv32imc/ilp32/no-rtti/crt0.o | 0 clang/test/Driver/riscv32-esp-toolchain.c | 19 +++++++++ 14 files changed, 54 insertions(+), 6 deletions(-) create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/no-rtti/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/no-rtti/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/no-rtti/crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/no-rtti/crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32i/ilp32/no-rtti/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imac/ilp32/no-rtti/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imafc/ilp32f/no-rtti/crt0.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/no-rtti/crt0.o diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index 1cbcc26e6eff05..1dff0976df3412 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1861,14 +1861,37 @@ static void findRISCVBareMetalMultilibs(const Driver &D, if (TargetTriple.getVendor() == llvm::Triple::Espressif) Ms.emplace_back(MultilibBuilder()); + if (TargetTriple.getVendor() == llvm::Triple::Espressif) { + Ms.emplace_back(MultilibBuilder()); + Ms.emplace_back(MultilibBuilder("no-rtti") + .flag("-fno-rtti") + .flag("-frtti", /*Disallow=*/true)); + } for (auto Element : RISCVMultilibSet) { - // multilib path rule is ${march}/${mabi} - Ms.emplace_back( - MultilibBuilder( - (Twine(Element.march) + "/" + Twine(Element.mabi)).str()) - .flag(Twine("-march=", Element.march).str()) - .flag(Twine("-mabi=", Element.mabi).str())); + if (TargetTriple.getVendor() == llvm::Triple::Espressif) { + // multilib path rule is ${march}/${mabi} + Ms.emplace_back( + MultilibBuilder( + (Twine(Element.march) + "/" + Twine(Element.mabi)).str()) + .flag(Twine("-march=", Element.march).str()) + .flag(Twine("-mabi=", Element.mabi).str())); + /* no-rtti version for every ${march}/${mabi} */ + Ms.emplace_back( + MultilibBuilder( + (Twine(Element.march) + "/" + Twine(Element.mabi) + "/no-rtti").str()) + .flag(Twine("-march=", Element.march).str()) + .flag(Twine("-mabi=", Element.mabi).str()) + .flag("-fno-rtti") + .flag("-frtti", /*Disallow=*/true)); + } else { + // multilib path rule is ${march}/${mabi} + Ms.emplace_back( + MultilibBuilder( + (Twine(Element.march) + "/" + Twine(Element.mabi)).str()) + .flag(Twine("-march=", Element.march).str()) + .flag(Twine("-mabi=", Element.mabi).str())); + } } MultilibSet RISCVMultilibs = MultilibSetBuilder() @@ -1904,6 +1927,12 @@ static void findRISCVBareMetalMultilibs(const Driver &D, } } + if (TargetTriple.getVendor() == llvm::Triple::Espressif) { + addMultilibFlag( + Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, true), "frtti", + Flags); + } + if (selectRISCVMultilib(RISCVMultilibs, MArch, Flags, Result.SelectedMultilibs)) Result.Multilibs = RISCVMultilibs; diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/no-rtti/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/no-rtti/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/no-rtti/crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/no-rtti/crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32i/ilp32/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32i/ilp32/no-rtti/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imac/ilp32/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imac/ilp32/no-rtti/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imafc/ilp32f/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imafc/ilp32f/no-rtti/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/no-rtti/crt0.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/riscv32-esp-toolchain.c b/clang/test/Driver/riscv32-esp-toolchain.c index 5c34c0a3bf7a15..34ef6871f30f0b 100644 --- a/clang/test/Driver/riscv32-esp-toolchain.c +++ b/clang/test/Driver/riscv32-esp-toolchain.c @@ -81,6 +81,25 @@ // CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-lstdc++" "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" // CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" +// RUN: %clangxx %s -### -no-canonical-prefixes -target riscv32-esp-elf \ +// RUN: -ffreestanding -stdlib=libstdc++ --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk \ +// RUN: --sysroot=%S/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf \ +// RUN: -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32 %s + +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-internal-isystem" "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++{{/|\\\\}}8.4.0" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-mabi" "ilp32" "-march" "rv32imac" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "--sysroot={{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-m" "elf32lriscv" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti{{/|\\\\}}crtbegin.o" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-lstdc++" "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" +// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti{{/|\\\\}}crtend.o" + // RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ // RUN: -march=rv32i -mabi=ilp32 \ // RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld --sysroot= \ From ba9278bd6fdddd80ff5028943ce7648eeb392751 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:11 +0300 Subject: [PATCH 111/261] esp/ci: Adds MacOS x86_64/ARM64 universal toolchain builds --- .gitlab-ci.yml | 70 +++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 58 insertions(+), 12 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6da427203109c3..5ce8137132c93e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -4,7 +4,7 @@ stages: - test - public_deploy -image: ${CI_DOCKER_REGISTRY}/llvm-build:3 +image: ${CI_DOCKER_REGISTRY}/llvm-build:4 variables: @@ -18,7 +18,7 @@ variables: XTENSA_OVERLAYS_REPO: "xtensa-overlays" XTENSA_OVERLAYS_REF: "master" # TODO: update vars below to tags names after related branches are merged in those repos - XTENSA_CLANG_TOOLCHAIN_REF: "release_universal_clang_14.0.0_gcc_8.4.0" + XTENSA_CLANG_TOOLCHAIN_REF: "build_macos_arm64" LLVM_GCC_TESTSUITE_REF: "feature/toolchain_build_script" PLATFORM_NAME_LINUX_ARM64: "linux-arm64" @@ -110,8 +110,10 @@ before_script: artifacts: paths: - ${DIST_DIR}/ + - newlib/ - ${BUILD_DIR}/clang_tests.log - ${BUILD_DIR}/clang_build.log + - ${BUILD_DIR}/newlib_build.log when: always expire_in: 1 day variables: @@ -125,8 +127,6 @@ before_script: - pushd ${DOWNLOADS_DIR} - export ESP_GCC_TOOLCHAIN_DIST_BASE=$PWD - *get_gcc_toolchain - - git clone -b ${NEWLIB_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${NEWLIB_REPO}.git - - export NEWLIB_PATH=$PWD/${NEWLIB_REPO} - git clone -b ${BINUTILS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${BINUTILS_REPO}.git - export BINUTILS_PATH=$PWD/${BINUTILS_REPO} - git clone -b ${XTENSA_OVERLAYS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${XTENSA_OVERLAYS_REPO}.git @@ -139,15 +139,38 @@ before_script: - export BUILD_PATH=$PWD/${BUILD_DIR} - mkdir -p ${BUILD_PATH} - export USE_PARALLEL_LINK_JOBS=2 - - ${BUILD_TOOLCHAIN_CMD} --llvm-path=${LLVM_PROJECT_PATH} --newlib-path=${NEWLIB_PATH} + # build Clang toolchain w/o newlib + - ${BUILD_TOOLCHAIN_CMD} --llvm-path=${LLVM_PROJECT_PATH} --gcc-toolchains-path=${ESP_GCC_TOOLCHAIN_DIST_BASE} --binutils-path=${BINUTILS_PATH} - --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} ${BUILD_TOOLCHAIN_CMD_ARGS} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/clang_build.log + --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} --host=${CONF_HOST} ${BUILD_TOOLCHAIN_CMD_ARGS} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/clang_build.log + # use just built Clang to build newlib + - export PATH=${BUILD_PATH}/esp-clang/bin:$PATH + - export BUILD_HOST=$(gcc -dumpmachine) + - export NEWLIB_OVERLAY_DISTRO_PATH=$PWD/newlib; + # build newlib overlay using ESP native (Linux) clang toolchain only + # it will be re-used for cross-buit toolchains (win and mac). + # FIXME: it would be good to move newlib overlay build to separate job and have job sequence like + # clang_linux_wo_newlib -> newlib_overlay -> clang_linux_full(copy newlib) -> clang_linux_unittests + # but we need full native (Linux) toolchain to run unittests and unittests need clang build dir. + # clang build dir may occupy about 2GB, so it looks too heavy to pass it as artifact + - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then + export BUILD_NEWLIB_PATH=${BUILD_PATH}/newlib; + mkdir -p ${NEWLIB_OVERLAY_DISTRO_PATH}; + git clone -b ${NEWLIB_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${NEWLIB_REPO}.git; + export NEWLIB_PATH=$PWD/${NEWLIB_REPO}; + ./build-toolchain.sh --newlib-path=${NEWLIB_PATH} --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} ${BUILD_NEWLIB_PATH} 2>&1 > ${BUILD_PATH}/newlib_build.log; + pushd ${BUILD_NEWLIB_PATH}; + ${ARCHIVE_TOOL_LINUX} ${NEWLIB_OVERLAY_DISTRO_PATH}/esp-clang-newlib-overlay.${ARCHIVE_EXT_LINUX} esp-clang/; + popd; + fi + - ${UNARCHIVE_TOOL_LINUX} ${NEWLIB_OVERLAY_DISTRO_PATH}/esp-clang-newlib-overlay.${ARCHIVE_EXT_LINUX} -C ${BUILD_PATH} + # strip binutils afer newlib is built + - STRIP_BINUTILS=YES ./build-toolchain.sh --host=${CONF_HOST} ${BUILD_PATH} # Run unit tests for native build only. # Run as non-root user because permission tests fail when run by root. - - export BUILD_HOST=$(gcc -dumpmachine) - - export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-Release-${CONF_HOST} - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then - echo "Run unit tests for native build"; + export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-Release-${CONF_HOST}; + echo "Run unit tests for native build ib ${LLVM_BUILD_PATH}"; useradd -m test_runner; chown -R test_runner ${LLVM_BUILD_PATH}; touch ${BUILD_PATH}/clang_tests.log; @@ -169,7 +192,7 @@ build_x86_64-linux-gnu: ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" -build_x86_64-w64-mingw32: +.build_x86_64-w64-mingw32: extends: .build_template needs: - job: build_x86_64-linux-gnu @@ -192,7 +215,7 @@ build_x86_64-w64-mingw32: - rm -rf ${DIST_DIR} - rm -rf ${BUILD_DIR} # add build command args speciifc for Windows build - - export BUILD_TOOLCHAIN_CMD_ARGS="--host=${CONF_HOST} --native-esp-clang-path=$PWD/esp-clang-${PLATFORM_NAME_LINUX}" + - export BUILD_TOOLCHAIN_CMD_ARGS="--native-esp-clang-path=$PWD/esp-clang-${PLATFORM_NAME_LINUX}" variables: CONF_HOST: "x86_64-w64-mingw32" PLATFORM_NAME: "${PLATFORM_NAME_WIN}" @@ -201,7 +224,30 @@ build_x86_64-w64-mingw32: ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" -test_x86_64-linux-gnu: +.build_apple-darwin_template: + extends: .build_template + needs: + - job: build_x86_64-linux-gnu + variables: + PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" + ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + GCC_ARCHIVE_EXT: "${GCC_ARCHIVE_EXT_MACOS}" + +build_x86_64-apple-darwin: + extends: .build_apple-darwin_template + variables: + CONF_HOST: "x86_64-apple-darwin21.1" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh --host-arch=x86_64" + +build_aarch64-apple-darwin: + extends: .build_apple-darwin_template + variables: + CONF_HOST: "aarch64-apple-darwin21.1" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh --host-arch=aarch64" + +.test_x86_64-linux-gnu: stage: test tags: [ "amd64", "build" ] allow_failure: true From 48d92f99b10799b62000cfc7cb66c974223a5caf Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:11 +0300 Subject: [PATCH 112/261] esp/ci: Adds minimal distro with libraries/headres only --- .gitlab-ci.yml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 5ce8137132c93e..6f616b88656385 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -9,6 +9,8 @@ image: ${CI_DOCKER_REGISTRY}/llvm-build:4 variables: # move all these to CI/CD settings + REL_SFX: "llvm14_0_0" + CLANG_VER: "14.0.0" GCC_REL_NAME: "esp-2022r1-RC1" GCC_REL_VER: "gcc11_2_0" NEWLIB_REPO: "newlib-cygwin" @@ -65,9 +67,9 @@ before_script: .get_release_name: &get_release_name | # using annotated tags REL_NUM=$(git describe --abbrev=7) - REL_SFX="llvm15_0_0" REL_NAME=${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} + LIBS_ARCHIVE_NAME=libs_${REL_NAME}.${ARCHIVE_EXT} echo "PLATFORM_NAME: $PLATFORM_NAME" echo "REL_NUM: $REL_NUM" echo "REL_NAME: $REL_NAME" @@ -103,6 +105,13 @@ before_script: mv ${ARCHIVE_NAME} ${DISTRO_DIR}/ echo "${ARCHIVE_NAME}" > ${DISTRO_DIR}/file_${PLATFORM_NAME} +# Pack libs to be used for Rust, Go etc. +.package_libs: &package_libs | + ${ARCHIVE_TOOL} ${LIBS_ARCHIVE_NAME} esp-clang/lib/libclang* esp-clang/lib/clang/${CLANG_VER}/include + mkdir -p ${DISTRO_DIR} + mv ${LIBS_ARCHIVE_NAME} ${DISTRO_DIR}/ + echo "${LIBS_ARCHIVE_NAME}" > ${DISTRO_DIR}/file_lib${PLATFORM_NAME} + .build_template: stage: build tags: [ "amd64", "build" ] @@ -115,7 +124,7 @@ before_script: - ${BUILD_DIR}/clang_build.log - ${BUILD_DIR}/newlib_build.log when: always - expire_in: 1 day + expire_in: 3 day variables: BUILD_TOOLCHAIN_CMD_ARGS: "" # use separate dist dir for universal toolchain @@ -180,6 +189,7 @@ before_script: - export DISTRO_DIR=$PWD/$DIST_DIR - pushd ${BUILD_PATH} - *package_toolchain + - *package_libs - popd build_x86_64-linux-gnu: From 1bfa188cce7b7b8e03d44ddd429603b1c3585752 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:12 +0300 Subject: [PATCH 113/261] esp/ci: Upgrade GCC toolchain to `esp-2022r1` --- .gitlab-ci.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6f616b88656385..70f206d102ea96 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -11,12 +11,12 @@ variables: # move all these to CI/CD settings REL_SFX: "llvm14_0_0" CLANG_VER: "14.0.0" - GCC_REL_NAME: "esp-2022r1-RC1" + GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" NEWLIB_REPO: "newlib-cygwin" - NEWLIB_REF: "esp_based_on_4_1_0" + NEWLIB_REF: "esp-2022r1" BINUTILS_REPO: "binutils-gdb" - BINUTILS_REF: "esp_based_on_binutils-2_35" + BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REPO: "xtensa-overlays" XTENSA_OVERLAYS_REF: "master" # TODO: update vars below to tags names after related branches are merged in those repos From 684bab9ac53b090442a91c92bb86b2c03f650967 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:12 +0300 Subject: [PATCH 114/261] esp/ci: Move newlib build to separate job --- .gitlab-ci.yml | 248 +++++++++++++++++++++++++++++++++++-------------- 1 file changed, 180 insertions(+), 68 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 70f206d102ea96..f3fadafed1fcde 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,5 +1,6 @@ stages: - build + - pack - private_deploy - test - public_deploy @@ -19,14 +20,16 @@ variables: BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REPO: "xtensa-overlays" XTENSA_OVERLAYS_REF: "master" - # TODO: update vars below to tags names after related branches are merged in those repos + LLVM_GCC_TESTSUITE_REF: "release_universal_clang_toolchain" + # TODO: update var below to tags names after related branches are merged in those repos + # XTENSA_CLANG_TOOLCHAIN_REF: "release_universal_clang_toolchain" XTENSA_CLANG_TOOLCHAIN_REF: "build_macos_arm64" - LLVM_GCC_TESTSUITE_REF: "feature/toolchain_build_script" PLATFORM_NAME_LINUX_ARM64: "linux-arm64" PLATFORM_NAME_LINUX: "linux-amd64" PLATFORM_NAME_WIN: "win64" PLATFORM_NAME_MACOS: "macos" + PLATFORM_NAME_MACOS_ARM64: "macos-arm64" ARCHIVE_TOOL_LINUX: "tar -cJf" UNARCHIVE_TOOL_LINUX: "tar -xf" @@ -40,6 +43,11 @@ variables: UNARCHIVE_TOOL_MACOS: "tar -xf" ARCHIVE_EXT_MACOS: "tar.xz" + ARCHIVE_TOOL_NEWLIB: ${ARCHIVE_TOOL_LINUX} + UNARCHIVE_TOOL_NEWLIB: ${UNARCHIVE_TOOL_LINUX} + ARCHIVE_EXT_NEWLIB: ${ARCHIVE_EXT_LINUX} + + DIST_NEW_DIR: "_dist_new" DIST_DIR: "dist" BUILD_DIR: "_build" DOWNLOADS_DIR: "_downloads" @@ -110,7 +118,19 @@ before_script: ${ARCHIVE_TOOL} ${LIBS_ARCHIVE_NAME} esp-clang/lib/libclang* esp-clang/lib/clang/${CLANG_VER}/include mkdir -p ${DISTRO_DIR} mv ${LIBS_ARCHIVE_NAME} ${DISTRO_DIR}/ - echo "${LIBS_ARCHIVE_NAME}" > ${DISTRO_DIR}/file_lib${PLATFORM_NAME} + echo "${LIBS_ARCHIVE_NAME}" > ${DISTRO_DIR}/file_libs-${PLATFORM_NAME} + +.get_binutils: &get_binutils | + git clone -b ${BINUTILS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${BINUTILS_REPO}.git + BINUTILS_PATH=$PWD/${BINUTILS_REPO} + +.get_xtensa_overlays: &get_xtensa_overlays | + git clone -b ${XTENSA_OVERLAYS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${XTENSA_OVERLAYS_REPO}.git + XTENSA_OVERLAYS_PATH=$PWD/${XTENSA_OVERLAYS_REPO} + +.get_newlib: &get_newlib | + git clone -b ${NEWLIB_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${NEWLIB_REPO}.git + NEWLIB_PATH=$PWD/${NEWLIB_REPO} .build_template: stage: build @@ -119,77 +139,49 @@ before_script: artifacts: paths: - ${DIST_DIR}/ - - newlib/ - - ${BUILD_DIR}/clang_tests.log - - ${BUILD_DIR}/clang_build.log - - ${BUILD_DIR}/newlib_build.log + - ${BUILD_DIR}/tests.log + - ${BUILD_DIR}/build.log when: always - expire_in: 3 day + expire_in: 1 day variables: - BUILD_TOOLCHAIN_CMD_ARGS: "" + BUILD_TOOLCHAIN_CMD_EXTRA_ARGS: "" # use separate dist dir for universal toolchain # TODO: remove this var after switching to universal toolchain builds - DIST_DIR: "dist_new" + DIST_DIR: ${DIST_NEW_DIR} script: - *get_release_name - mkdir ${DOWNLOADS_DIR} - pushd ${DOWNLOADS_DIR} - - export ESP_GCC_TOOLCHAIN_DIST_BASE=$PWD + - ESP_GCC_TOOLCHAIN_DIST_BASE=$PWD - *get_gcc_toolchain - - git clone -b ${BINUTILS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${BINUTILS_REPO}.git - - export BINUTILS_PATH=$PWD/${BINUTILS_REPO} - - git clone -b ${XTENSA_OVERLAYS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${XTENSA_OVERLAYS_REPO}.git - - export XTENSA_OVERLAYS_PATH=$PWD/${XTENSA_OVERLAYS_REPO} + - *get_binutils + - *get_xtensa_overlays - popd - *get_clang_toolchain_build_scripts - *fix_origin_remote_for_public - - export ESP_GCC_TOOLCHAIN_REL_VER=${GCC_REL_NAME} - - export LLVM_PROJECT_PATH=$PWD - - export BUILD_PATH=$PWD/${BUILD_DIR} + - LLVM_PROJECT_PATH=$PWD + - BUILD_PATH=$PWD/${BUILD_DIR} - mkdir -p ${BUILD_PATH} - export USE_PARALLEL_LINK_JOBS=2 # build Clang toolchain w/o newlib - ${BUILD_TOOLCHAIN_CMD} --llvm-path=${LLVM_PROJECT_PATH} --gcc-toolchains-path=${ESP_GCC_TOOLCHAIN_DIST_BASE} --binutils-path=${BINUTILS_PATH} - --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} --host=${CONF_HOST} ${BUILD_TOOLCHAIN_CMD_ARGS} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/clang_build.log - # use just built Clang to build newlib - - export PATH=${BUILD_PATH}/esp-clang/bin:$PATH - - export BUILD_HOST=$(gcc -dumpmachine) - - export NEWLIB_OVERLAY_DISTRO_PATH=$PWD/newlib; - # build newlib overlay using ESP native (Linux) clang toolchain only - # it will be re-used for cross-buit toolchains (win and mac). - # FIXME: it would be good to move newlib overlay build to separate job and have job sequence like - # clang_linux_wo_newlib -> newlib_overlay -> clang_linux_full(copy newlib) -> clang_linux_unittests - # but we need full native (Linux) toolchain to run unittests and unittests need clang build dir. - # clang build dir may occupy about 2GB, so it looks too heavy to pass it as artifact - - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then - export BUILD_NEWLIB_PATH=${BUILD_PATH}/newlib; - mkdir -p ${NEWLIB_OVERLAY_DISTRO_PATH}; - git clone -b ${NEWLIB_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${NEWLIB_REPO}.git; - export NEWLIB_PATH=$PWD/${NEWLIB_REPO}; - ./build-toolchain.sh --newlib-path=${NEWLIB_PATH} --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} ${BUILD_NEWLIB_PATH} 2>&1 > ${BUILD_PATH}/newlib_build.log; - pushd ${BUILD_NEWLIB_PATH}; - ${ARCHIVE_TOOL_LINUX} ${NEWLIB_OVERLAY_DISTRO_PATH}/esp-clang-newlib-overlay.${ARCHIVE_EXT_LINUX} esp-clang/; - popd; - fi - - ${UNARCHIVE_TOOL_LINUX} ${NEWLIB_OVERLAY_DISTRO_PATH}/esp-clang-newlib-overlay.${ARCHIVE_EXT_LINUX} -C ${BUILD_PATH} - # strip binutils afer newlib is built - - STRIP_BINUTILS=YES ./build-toolchain.sh --host=${CONF_HOST} ${BUILD_PATH} - # Run unit tests for native build only. + --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} --host=${CONF_HOST} ${BUILD_TOOLCHAIN_CMD_EXTRA_ARGS} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log + - BUILD_HOST=$(gcc -dumpmachine) + # Do not run unit tests for cross-builds. # Run as non-root user because permission tests fail when run by root. - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-Release-${CONF_HOST}; - echo "Run unit tests for native build ib ${LLVM_BUILD_PATH}"; + echo "Run unit tests for native build in ${LLVM_BUILD_PATH}"; useradd -m test_runner; chown -R test_runner ${LLVM_BUILD_PATH}; - touch ${BUILD_PATH}/clang_tests.log; - chmod o+w ${BUILD_PATH}/clang_tests.log; - runuser -l test_runner -c 'cmake --build '${LLVM_BUILD_PATH}' --target check-all 2>&1 > '${BUILD_PATH}'/clang_tests.log'; + touch ${BUILD_PATH}/tests.log; + chmod o+w ${BUILD_PATH}/tests.log; + runuser -l test_runner -c 'cmake --build '${LLVM_BUILD_PATH}' --target check-all 2>&1 > '${BUILD_PATH}'/tests.log'; fi - export DISTRO_DIR=$PWD/$DIST_DIR - pushd ${BUILD_PATH} - *package_toolchain - - *package_libs - popd build_x86_64-linux-gnu: @@ -202,67 +194,187 @@ build_x86_64-linux-gnu: ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" -.build_x86_64-w64-mingw32: +build_x86_64-w64-mingw32: extends: .build_template needs: + # needs native toolchain and newlib from this job - job: build_x86_64-linux-gnu before_script: - *use_ci_tools - *add_gitlab_key # get ARCHIVE_NAME for Linux release. Modify vars to make get_release_name working properly - - export PLATFORM_NAME_ORIG=${PLATFORM_NAME} - - export ARCHIVE_EXT_ORIG=${ARCHIVE_EXT} - - export PLATFORM_NAME=${PLATFORM_NAME_LINUX} - - export ARCHIVE_EXT=${ARCHIVE_EXT_LINUX} - - *get_release_name - # restore modified vars - - export PLATFORM_NAME=${PLATFORM_NAME_ORIG} - - export ARCHIVE_EXT=${ARCHIVE_EXT_ORIG} - # unpack Linux release to re-use it as native Clang for Windows build + - CLANG_LINUX_ARCHIVE=$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) + # unpack x86_64-linux-gnu toolchain to re-use it as native Clang for Windows build - mkdir -p esp-clang-${PLATFORM_NAME_LINUX} - - ${UNARCHIVE_TOOL_LINUX} ${DIST_DIR}/${ARCHIVE_NAME} -C esp-clang-${PLATFORM_NAME_LINUX} + - ${UNARCHIVE_TOOL_LINUX} ${DIST_DIR}/${CLANG_LINUX_ARCHIVE} -C esp-clang-${PLATFORM_NAME_LINUX} # we do not want to keep artifacts from 'x86_64-linux-gnu' job - rm -rf ${DIST_DIR} - rm -rf ${BUILD_DIR} # add build command args speciifc for Windows build - - export BUILD_TOOLCHAIN_CMD_ARGS="--native-esp-clang-path=$PWD/esp-clang-${PLATFORM_NAME_LINUX}" + - export BUILD_TOOLCHAIN_CMD_EXTRA_ARGS="--native-esp-clang-path=$PWD/esp-clang-${PLATFORM_NAME_LINUX}" variables: CONF_HOST: "x86_64-w64-mingw32" PLATFORM_NAME: "${PLATFORM_NAME_WIN}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" + # Use Linux compressor to minimize artifact size. + # Toolchain is not fully stripped yet, so may exceed max artifact size. + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" .build_apple-darwin_template: extends: .build_template - needs: - - job: build_x86_64-linux-gnu variables: - PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" - GCC_ARCHIVE_EXT: "${GCC_ARCHIVE_EXT_MACOS}" build_x86_64-apple-darwin: extends: .build_apple-darwin_template variables: CONF_HOST: "x86_64-apple-darwin21.1" + PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh --host-arch=x86_64" build_aarch64-apple-darwin: extends: .build_apple-darwin_template variables: CONF_HOST: "aarch64-apple-darwin21.1" + PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh --host-arch=aarch64" -.test_x86_64-linux-gnu: - stage: test +build_newlib: + stage: build + tags: [ "amd64", "build" ] + needs: + # needs native toolchainfrom this job + - job: build_x86_64-linux-gnu + artifacts: + paths: + - ${DIST_DIR}/ + - ${BUILD_DIR}/build.log + when: always + expire_in: 1 day + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + # use separate dist dir for universal toolchain + # TODO: remove this var after switching to universal toolchain builds + DIST_DIR: ${DIST_NEW_DIR} + script: + # get ARCHIVE_NAME for Linux release. + - CLANG_ARCHIVE=$PWD/${DIST_DIR}/$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) + - mkdir -p ${DOWNLOADS_DIR} + - pushd ${DOWNLOADS_DIR} + - *get_xtensa_overlays + - *get_newlib + # unpack clang + - ${UNARCHIVE_TOOL} ${CLANG_ARCHIVE} + - export PATH=$PWD/esp-clang/bin:$PATH + - popd + - rm -rf $PWD/${DIST_DIR} + - *get_clang_toolchain_build_scripts + # build newlib overlay using ESP native (Linux) clang toolchain only + # it will be re-used for cross-buit toolchains (win and mac). + - NEWLIB_OVERLAY_DISTRO_PATH=$PWD/${DIST_DIR} + - mkdir -p ${NEWLIB_OVERLAY_DISTRO_PATH} + - BUILD_PATH=$PWD/${BUILD_DIR} + - mkdir -p ${BUILD_PATH} + - ./build-toolchain.sh --newlib-path=${NEWLIB_PATH} --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log + - pushd ${BUILD_PATH} + - ${ARCHIVE_TOOL_NEWLIB} ${NEWLIB_OVERLAY_DISTRO_PATH}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} esp-clang/ + - popd + +.pack_template: + stage: pack tags: [ "amd64", "build" ] allow_failure: true + artifacts: + paths: + - ${DIST_DIR}/ + when: always + expire_in: 3 day + variables: + # use separate dist dir for universal toolchain + # TODO: remove this var after switching to universal toolchain builds + DIST_DIR: ${DIST_NEW_DIR} + script: + - *get_release_name + - export BUILD_PATH=$PWD/${BUILD_DIR} + - mkdir -p ${BUILD_PATH} + # unpack clang + - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} -C ${BUILD_PATH} + # unpack newlib + - ${UNARCHIVE_TOOL_NEWLIB} ${DIST_DIR}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} -C ${BUILD_PATH} + - rm -rf ${DIST_DIR} + - *get_clang_toolchain_build_scripts + # strip binutils afer newlib is built + - STRIP_BINUTILS=YES ./build-toolchain.sh --host=${CONF_HOST} ${BUILD_PATH} + - DISTRO_DIR=$PWD/${DIST_DIR} + - pushd ${BUILD_PATH} + - *package_toolchain + - *package_libs + - popd + +pack_x86_64-linux-gnu: + extends: .pack_template needs: - job: build_x86_64-linux-gnu + - job: build_newlib + variables: + CONF_HOST: "x86_64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + +pack_x86_64-w64-mingw32: + extends: .pack_template + needs: + - job: build_x86_64-w64-mingw32 + - job: build_newlib + variables: + CONF_HOST: "x86_64-w64-mingw32" + PLATFORM_NAME: "${PLATFORM_NAME_WIN}" + # use Linux compressor to save space. + # upon release archive will be re-packed into zip format for uploading to GH + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" + +.pack_apple-darwin_template: + extends: .pack_template + variables: + ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" + ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + +pack_x86_64-apple-darwin: + extends: .pack_apple-darwin_template + needs: + - job: build_x86_64-apple-darwin + - job: build_newlib + variables: + CONF_HOST: "x86_64-apple-darwin21.1" + PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" + +pack_aarch64-apple-darwin: + extends: .pack_apple-darwin_template + needs: + - job: build_aarch64-apple-darwin + - job: build_newlib + variables: + CONF_HOST: "aarch64-apple-darwin21.1" + PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" + +test_x86_64-linux-gnu: + stage: test + tags: [ "amd64", "build" ] + allow_failure: true + needs: + - job: pack_x86_64-linux-gnu variables: PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" @@ -270,7 +382,7 @@ build_aarch64-apple-darwin: ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" # use separate dist dir for universal toolchain # TODO: remove this var after switching to universal toolchain builds - DIST_DIR: "dist_new" + DIST_DIR: ${DIST_NEW_DIR} script: - *get_release_name - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} From 8419f9ee11a31ab1eef1bb5a9deceadb046d345e Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:13 +0300 Subject: [PATCH 115/261] esp/ci: Adds Linux ARM/ARM64 universal toolchain builds --- .gitignore | 3 +++ .gitlab-ci.yml | 69 ++++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 59 insertions(+), 13 deletions(-) diff --git a/.gitignore b/.gitignore index 20c4f52cd37860..0e13e978416184 100644 --- a/.gitignore +++ b/.gitignore @@ -28,6 +28,9 @@ # Nested build directory /build* +/*/build-* +/_build +/_dist #==============================================================================# # Explicit files to ignore (only matches one). diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index f3fadafed1fcde..6b57687583bf19 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -23,10 +23,12 @@ variables: LLVM_GCC_TESTSUITE_REF: "release_universal_clang_toolchain" # TODO: update var below to tags names after related branches are merged in those repos # XTENSA_CLANG_TOOLCHAIN_REF: "release_universal_clang_toolchain" - XTENSA_CLANG_TOOLCHAIN_REF: "build_macos_arm64" + XTENSA_CLANG_TOOLCHAIN_REF: "universal_toolchain/build_linux_arm64" - PLATFORM_NAME_LINUX_ARM64: "linux-arm64" + CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 PLATFORM_NAME_LINUX: "linux-amd64" + PLATFORM_NAME_LINUX_ARMHF: "linux-armhf" + PLATFORM_NAME_LINUX_ARM64: "linux-arm64" PLATFORM_NAME_WIN: "win64" PLATFORM_NAME_MACOS: "macos" PLATFORM_NAME_MACOS_ARM64: "macos-arm64" @@ -171,7 +173,7 @@ before_script: # Do not run unit tests for cross-builds. # Run as non-root user because permission tests fail when run by root. - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then - export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-Release-${CONF_HOST}; + export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-${CONF_HOST}-Release; echo "Run unit tests for native build in ${LLVM_BUILD_PATH}"; useradd -m test_runner; chown -R test_runner ${LLVM_BUILD_PATH}; @@ -184,16 +186,34 @@ before_script: - *package_toolchain - popd -build_x86_64-linux-gnu: +.build_linux-gnu_template: extends: .build_template variables: - CONF_HOST: "x86_64-linux-gnu" - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" +build_x86_64-linux-gnu: + extends: .build_linux-gnu_template + variables: + CONF_HOST: "x86_64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + +build_arm-linux-gnueabihf: + extends: .build_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + variables: + CONF_HOST: "arm-linux-gnueabihf" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARMHF}" + +build_aarch64-linux-gnu: + extends: .build_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + variables: + CONF_HOST: "aarch64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" + build_x86_64-w64-mingw32: extends: .build_template needs: @@ -228,20 +248,19 @@ build_x86_64-w64-mingw32: ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" build_x86_64-apple-darwin: extends: .build_apple-darwin_template variables: CONF_HOST: "x86_64-apple-darwin21.1" PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh --host-arch=x86_64" build_aarch64-apple-darwin: extends: .build_apple-darwin_template variables: CONF_HOST: "aarch64-apple-darwin21.1" PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh --host-arch=aarch64" build_newlib: stage: build @@ -318,17 +337,41 @@ build_newlib: - *package_libs - popd -pack_x86_64-linux-gnu: +.pack_linux-gnu_template: extends: .pack_template + variables: + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + +pack_x86_64-linux-gnu: + extends: .pack_linux-gnu_template needs: - job: build_x86_64-linux-gnu - job: build_newlib variables: CONF_HOST: "x86_64-linux-gnu" PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + +pack_arm-linux-gnueabihf: + extends: .pack_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + needs: + - job: build_arm-linux-gnueabihf + - job: build_newlib + variables: + CONF_HOST: "arm-linux-gnueabihf" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARMHF}" + +pack_aarch64-linux-gnu: + extends: .pack_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + needs: + - job: build_aarch64-linux-gnu + - job: build_newlib + variables: + CONF_HOST: "aarch64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" pack_x86_64-w64-mingw32: extends: .pack_template @@ -459,7 +502,7 @@ linux_amd64_build: linux_arm64_build: extends: .build_template_old - image: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 + image: ${CROSS_ARM_IMAGE} variables: PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" From f975fa19e56c03fdd738f59b9c6ec2771f8e02ff Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:13 +0300 Subject: [PATCH 116/261] esp/ci: Upgrade Clang ver to 15 --- .gitlab-ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6b57687583bf19..8a41a9dfc1694a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -10,8 +10,8 @@ image: ${CI_DOCKER_REGISTRY}/llvm-build:4 variables: # move all these to CI/CD settings - REL_SFX: "llvm14_0_0" - CLANG_VER: "14.0.0" + REL_SFX: "llvm15_0_0" + CLANG_VER: "15.0.0" GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" NEWLIB_REPO: "newlib-cygwin" From a5de03970ba92be2ee6186b8e109acb9a8fd8c5d Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:14 +0300 Subject: [PATCH 117/261] esp/ci: Adds support to switch between legacy and universal toolchain release pipelines --- .gitlab-ci.yml | 578 +++---------------------------- .legacy-release.yml | 164 +++++++++ .universal-toolchain-release.yml | 409 ++++++++++++++++++++++ 3 files changed, 613 insertions(+), 538 deletions(-) create mode 100644 .legacy-release.yml create mode 100644 .universal-toolchain-release.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 8a41a9dfc1694a..d4a2c816f97ef4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -10,7 +10,7 @@ image: ${CI_DOCKER_REGISTRY}/llvm-build:4 variables: # move all these to CI/CD settings - REL_SFX: "llvm15_0_0" + REL_SFX: "llvm" CLANG_VER: "15.0.0" GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" @@ -21,9 +21,7 @@ variables: XTENSA_OVERLAYS_REPO: "xtensa-overlays" XTENSA_OVERLAYS_REF: "master" LLVM_GCC_TESTSUITE_REF: "release_universal_clang_toolchain" - # TODO: update var below to tags names after related branches are merged in those repos - # XTENSA_CLANG_TOOLCHAIN_REF: "release_universal_clang_toolchain" - XTENSA_CLANG_TOOLCHAIN_REF: "universal_toolchain/build_linux_arm64" + XTENSA_CLANG_TOOLCHAIN_REF: "release_universal_clang_toolchain" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 PLATFORM_NAME_LINUX: "linux-amd64" @@ -40,6 +38,10 @@ variables: ARCHIVE_TOOL_WIN: "zip -9 -r" UNARCHIVE_TOOL_WIN: "unzip" ARCHIVE_EXT_WIN: "zip" + # Use Linux xz compressor to minimize Windows build artifact size. + # Upon release archive will be re-packed into zip format for uploading to GH. + ARCHIVE_TOOL_WIN_INT: ${ARCHIVE_TOOL_LINUX} + UNARCHIVE_TOOL_WIN_INT: ${UNARCHIVE_TOOL_LINUX} ARCHIVE_TOOL_MACOS: "tar -cJf" UNARCHIVE_TOOL_MACOS: "tar -xf" @@ -49,10 +51,13 @@ variables: UNARCHIVE_TOOL_NEWLIB: ${UNARCHIVE_TOOL_LINUX} ARCHIVE_EXT_NEWLIB: ${ARCHIVE_EXT_LINUX} - DIST_NEW_DIR: "_dist_new" + LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + DIST_DIR: "dist" - BUILD_DIR: "_build" - DOWNLOADS_DIR: "_downloads" + BUILD_DIR: "build" + DOWNLOADS_DIR: "downloads" ########################################################################### #################### START OF TEMPORARY LEGACY CODE ####################### @@ -62,548 +67,45 @@ variables: ##################### END OF TEMPORARY LEGACY CODE ######################## ########################################################################### -.use_ci_tools: &use_ci_tools | +.use_ci_tools_snippet: &use_ci_tools_snippet | curl -sSL ${CIT_LOADER_URL} -o cit_loader.sh && sh cit_loader.sh source citools/import_functions -.add_gitlab_key: &add_gitlab_key | - cit_add_ssh_key "${GITLAB_KEY}" - -before_script: - - *use_ci_tools - - *add_gitlab_key - -# Prepare release name/number -.get_release_name: &get_release_name | - # using annotated tags - REL_NUM=$(git describe --abbrev=7) - REL_NAME=${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} - ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} - LIBS_ARCHIVE_NAME=libs_${REL_NAME}.${ARCHIVE_EXT} - echo "PLATFORM_NAME: $PLATFORM_NAME" - echo "REL_NUM: $REL_NUM" - echo "REL_NAME: $REL_NAME" - echo "ARCHIVE_NAME: $ARCHIVE_NAME" - -# Get an existing crosstool-ng builds for all chips -.get_gcc_toolchain: &get_gcc_toolchain | - declare -a XTENSA_CPUS=("esp32" - "esp32s2" - "esp32s3") - for ((i = 0; i < ${#XTENSA_CPUS[@]}; i++)); do - XTENSA_CPU=${XTENSA_CPUS[$i]} - GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${ARCHIVE_EXT} - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} - ${UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} - done; - GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${ARCHIVE_EXT} - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} - ${UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} - -.get_clang_toolchain_build_scripts: &get_clang_toolchain_build_scripts | - git clone -b ${XTENSA_CLANG_TOOLCHAIN_REF} ${GITLAB_SSH_SERVER}/${XTENSA_CLANG_TOOLCHAIN_REPO} - cp -r xtensa-clang-toolchain/* . - -# LLVM Build System used the remote address to show detailed version info, we'll change it to the public repository -.fix_origin_remote_for_public: &fix_origin_remote_for_public | - git remote set-url origin "${GH_REPO_HTTPS}" - -# Pack the toolchain -.package_toolchain: &package_toolchain | - ${ARCHIVE_TOOL} ${ARCHIVE_NAME} esp-clang/ - mkdir -p ${DISTRO_DIR} - mv ${ARCHIVE_NAME} ${DISTRO_DIR}/ - echo "${ARCHIVE_NAME}" > ${DISTRO_DIR}/file_${PLATFORM_NAME} - -# Pack libs to be used for Rust, Go etc. -.package_libs: &package_libs | - ${ARCHIVE_TOOL} ${LIBS_ARCHIVE_NAME} esp-clang/lib/libclang* esp-clang/lib/clang/${CLANG_VER}/include - mkdir -p ${DISTRO_DIR} - mv ${LIBS_ARCHIVE_NAME} ${DISTRO_DIR}/ - echo "${LIBS_ARCHIVE_NAME}" > ${DISTRO_DIR}/file_libs-${PLATFORM_NAME} - -.get_binutils: &get_binutils | - git clone -b ${BINUTILS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${BINUTILS_REPO}.git - BINUTILS_PATH=$PWD/${BINUTILS_REPO} - -.get_xtensa_overlays: &get_xtensa_overlays | - git clone -b ${XTENSA_OVERLAYS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${XTENSA_OVERLAYS_REPO}.git - XTENSA_OVERLAYS_PATH=$PWD/${XTENSA_OVERLAYS_REPO} - -.get_newlib: &get_newlib | - git clone -b ${NEWLIB_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${NEWLIB_REPO}.git - NEWLIB_PATH=$PWD/${NEWLIB_REPO} - -.build_template: - stage: build - tags: [ "amd64", "build" ] - allow_failure: true - artifacts: - paths: - - ${DIST_DIR}/ - - ${BUILD_DIR}/tests.log - - ${BUILD_DIR}/build.log - when: always - expire_in: 1 day - variables: - BUILD_TOOLCHAIN_CMD_EXTRA_ARGS: "" - # use separate dist dir for universal toolchain - # TODO: remove this var after switching to universal toolchain builds - DIST_DIR: ${DIST_NEW_DIR} - script: - - *get_release_name - - mkdir ${DOWNLOADS_DIR} - - pushd ${DOWNLOADS_DIR} - - ESP_GCC_TOOLCHAIN_DIST_BASE=$PWD - - *get_gcc_toolchain - - *get_binutils - - *get_xtensa_overlays - - popd - - *get_clang_toolchain_build_scripts - - *fix_origin_remote_for_public - - LLVM_PROJECT_PATH=$PWD - - BUILD_PATH=$PWD/${BUILD_DIR} - - mkdir -p ${BUILD_PATH} - - export USE_PARALLEL_LINK_JOBS=2 - # build Clang toolchain w/o newlib - - ${BUILD_TOOLCHAIN_CMD} --llvm-path=${LLVM_PROJECT_PATH} - --gcc-toolchains-path=${ESP_GCC_TOOLCHAIN_DIST_BASE} --binutils-path=${BINUTILS_PATH} - --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} --host=${CONF_HOST} ${BUILD_TOOLCHAIN_CMD_EXTRA_ARGS} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log - - BUILD_HOST=$(gcc -dumpmachine) - # Do not run unit tests for cross-builds. - # Run as non-root user because permission tests fail when run by root. - - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then - export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-${CONF_HOST}-Release; - echo "Run unit tests for native build in ${LLVM_BUILD_PATH}"; - useradd -m test_runner; - chown -R test_runner ${LLVM_BUILD_PATH}; - touch ${BUILD_PATH}/tests.log; - chmod o+w ${BUILD_PATH}/tests.log; - runuser -l test_runner -c 'cmake --build '${LLVM_BUILD_PATH}' --target check-all 2>&1 > '${BUILD_PATH}'/tests.log'; - fi - - export DISTRO_DIR=$PWD/$DIST_DIR - - pushd ${BUILD_PATH} - - *package_toolchain - - popd - -.build_linux-gnu_template: - extends: .build_template - variables: - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" - -build_x86_64-linux-gnu: - extends: .build_linux-gnu_template - variables: - CONF_HOST: "x86_64-linux-gnu" - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - -build_arm-linux-gnueabihf: - extends: .build_linux-gnu_template - image: ${CROSS_ARM_IMAGE} - variables: - CONF_HOST: "arm-linux-gnueabihf" - PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARMHF}" - -build_aarch64-linux-gnu: - extends: .build_linux-gnu_template - image: ${CROSS_ARM_IMAGE} - variables: - CONF_HOST: "aarch64-linux-gnu" - PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" - -build_x86_64-w64-mingw32: - extends: .build_template - needs: - # needs native toolchain and newlib from this job - - job: build_x86_64-linux-gnu - before_script: - - *use_ci_tools - - *add_gitlab_key - # get ARCHIVE_NAME for Linux release. Modify vars to make get_release_name working properly - - CLANG_LINUX_ARCHIVE=$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) - # unpack x86_64-linux-gnu toolchain to re-use it as native Clang for Windows build - - mkdir -p esp-clang-${PLATFORM_NAME_LINUX} - - ${UNARCHIVE_TOOL_LINUX} ${DIST_DIR}/${CLANG_LINUX_ARCHIVE} -C esp-clang-${PLATFORM_NAME_LINUX} - # we do not want to keep artifacts from 'x86_64-linux-gnu' job - - rm -rf ${DIST_DIR} - - rm -rf ${BUILD_DIR} - # add build command args speciifc for Windows build - - export BUILD_TOOLCHAIN_CMD_EXTRA_ARGS="--native-esp-clang-path=$PWD/esp-clang-${PLATFORM_NAME_LINUX}" - variables: - CONF_HOST: "x86_64-w64-mingw32" - PLATFORM_NAME: "${PLATFORM_NAME_WIN}" - # Use Linux compressor to minimize artifact size. - # Toolchain is not fully stripped yet, so may exceed max artifact size. - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" - ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" - -.build_apple-darwin_template: - extends: .build_template - variables: - ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" - ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" - BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" - -build_x86_64-apple-darwin: - extends: .build_apple-darwin_template - variables: - CONF_HOST: "x86_64-apple-darwin21.1" - PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" - -build_aarch64-apple-darwin: - extends: .build_apple-darwin_template - variables: - CONF_HOST: "aarch64-apple-darwin21.1" - PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" - -build_newlib: - stage: build - tags: [ "amd64", "build" ] - needs: - # needs native toolchainfrom this job - - job: build_x86_64-linux-gnu - artifacts: - paths: - - ${DIST_DIR}/ - - ${BUILD_DIR}/build.log - when: always - expire_in: 1 day - variables: - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - # use separate dist dir for universal toolchain - # TODO: remove this var after switching to universal toolchain builds - DIST_DIR: ${DIST_NEW_DIR} - script: - # get ARCHIVE_NAME for Linux release. - - CLANG_ARCHIVE=$PWD/${DIST_DIR}/$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) - - mkdir -p ${DOWNLOADS_DIR} - - pushd ${DOWNLOADS_DIR} - - *get_xtensa_overlays - - *get_newlib - # unpack clang - - ${UNARCHIVE_TOOL} ${CLANG_ARCHIVE} - - export PATH=$PWD/esp-clang/bin:$PATH - - popd - - rm -rf $PWD/${DIST_DIR} - - *get_clang_toolchain_build_scripts - # build newlib overlay using ESP native (Linux) clang toolchain only - # it will be re-used for cross-buit toolchains (win and mac). - - NEWLIB_OVERLAY_DISTRO_PATH=$PWD/${DIST_DIR} - - mkdir -p ${NEWLIB_OVERLAY_DISTRO_PATH} - - BUILD_PATH=$PWD/${BUILD_DIR} - - mkdir -p ${BUILD_PATH} - - ./build-toolchain.sh --newlib-path=${NEWLIB_PATH} --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log - - pushd ${BUILD_PATH} - - ${ARCHIVE_TOOL_NEWLIB} ${NEWLIB_OVERLAY_DISTRO_PATH}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} esp-clang/ - - popd - -.pack_template: - stage: pack - tags: [ "amd64", "build" ] - allow_failure: true - artifacts: - paths: - - ${DIST_DIR}/ - when: always - expire_in: 3 day - variables: - # use separate dist dir for universal toolchain - # TODO: remove this var after switching to universal toolchain builds - DIST_DIR: ${DIST_NEW_DIR} - script: - - *get_release_name - - export BUILD_PATH=$PWD/${BUILD_DIR} - - mkdir -p ${BUILD_PATH} - # unpack clang - - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} -C ${BUILD_PATH} - # unpack newlib - - ${UNARCHIVE_TOOL_NEWLIB} ${DIST_DIR}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} -C ${BUILD_PATH} - - rm -rf ${DIST_DIR} - - *get_clang_toolchain_build_scripts - # strip binutils afer newlib is built - - STRIP_BINUTILS=YES ./build-toolchain.sh --host=${CONF_HOST} ${BUILD_PATH} - - DISTRO_DIR=$PWD/${DIST_DIR} - - pushd ${BUILD_PATH} - - *package_toolchain - - *package_libs - - popd - -.pack_linux-gnu_template: - extends: .pack_template - variables: - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - -pack_x86_64-linux-gnu: - extends: .pack_linux-gnu_template - needs: - - job: build_x86_64-linux-gnu - - job: build_newlib - variables: - CONF_HOST: "x86_64-linux-gnu" - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - -pack_arm-linux-gnueabihf: - extends: .pack_linux-gnu_template - image: ${CROSS_ARM_IMAGE} - needs: - - job: build_arm-linux-gnueabihf - - job: build_newlib - variables: - CONF_HOST: "arm-linux-gnueabihf" - PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARMHF}" - -pack_aarch64-linux-gnu: - extends: .pack_linux-gnu_template - image: ${CROSS_ARM_IMAGE} - needs: - - job: build_aarch64-linux-gnu - - job: build_newlib - variables: - CONF_HOST: "aarch64-linux-gnu" - PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" - -pack_x86_64-w64-mingw32: - extends: .pack_template - needs: - - job: build_x86_64-w64-mingw32 - - job: build_newlib - variables: - CONF_HOST: "x86_64-w64-mingw32" - PLATFORM_NAME: "${PLATFORM_NAME_WIN}" - # use Linux compressor to save space. - # upon release archive will be re-packed into zip format for uploading to GH - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" - -.pack_apple-darwin_template: - extends: .pack_template - variables: - ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" - ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" - -pack_x86_64-apple-darwin: - extends: .pack_apple-darwin_template - needs: - - job: build_x86_64-apple-darwin - - job: build_newlib - variables: - CONF_HOST: "x86_64-apple-darwin21.1" - PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" - -pack_aarch64-apple-darwin: - extends: .pack_apple-darwin_template - needs: - - job: build_aarch64-apple-darwin - - job: build_newlib - variables: - CONF_HOST: "aarch64-apple-darwin21.1" - PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" - -test_x86_64-linux-gnu: - stage: test - tags: [ "amd64", "build" ] - allow_failure: true - needs: - - job: pack_x86_64-linux-gnu - variables: - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - # use separate dist dir for universal toolchain - # TODO: remove this var after switching to universal toolchain builds - DIST_DIR: ${DIST_NEW_DIR} +.use_ci_tools: script: - - *get_release_name - - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} - # getting testsuite - - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git - # preparing testsuite - - export PATH=${PWD}/esp-clang/bin:$PATH - - cd llvm-xtensa-testsuite - # qemu - - ./qemu_esp32_install.sh - # run testsuite for esp32 - - ./run_esp32_tests.sh - -########################################################################### -#################### START OF TEMPORARY LEGACY CODE ####################### -# TODO: the code below is to be removed after migration to new build script -.get_release_name_old: &get_release_name_old | - # using annotated tags - REL_NUM=$(git describe --abbrev=7) - REL_SFX="llvm15_0_0" - REL_NAME=${CONF_TARGET}-${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} - ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} - echo "PLATFORM_NAME: $PLATFORM_NAME" - echo "REL_NUM: $REL_NUM" - echo "REL_NAME: $REL_NAME" - echo "ARCHIVE_NAME: $ARCHIVE_NAME" - -.get_gcc_toolchain_old: &get_gcc_toolchain_old | - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/${XTENSA_GCC_TOOLCHAIN} - ${UNARCHIVE_TOOL} ${XTENSA_GCC_TOOLCHAIN} - if [[ "$XTENSA_GCC_TOOLCHAIN" == *"linux-amd64"* ]]; then - cp -r xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} - else - mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz - tar -xf xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz - fi - export GCC_ESP32_LINUX_TOOLCHAIN="xtensa-esp32-elf" + - *use_ci_tools_snippet -.package_toolchain_old: &package_toolchain_old | - ${ARCHIVE_TOOL} ${ARCHIVE_NAME} ${XTENSA_CLANG_TOOLCHAIN}/ - mkdir -p ${DIST_DIR} - mv ${ARCHIVE_NAME} ${DIST_DIR}/ - echo "${ARCHIVE_NAME}" > ${DIST_DIR}/file_${PLATFORM_NAME}_${CONF_TARGET} +.add_gitlab_key_snippet: &add_gitlab_key_snippet | + cit_add_ssh_key "${GITLAB_KEY}" -.build_template_old: - stage: build - tags: [ "amd64", "build" ] - artifacts: - paths: - - ${DIST_DIR}/ - when: always - expire_in: 10 day - variables: - XTENSA_CLANG_TOOLCHAIN_REF: "release_esp32_clang_15.0.0_gcc_8.4.0" - GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" +.add_gitlab_key: script: - - *get_release_name_old - - *get_gcc_toolchain_old - - *fix_origin_remote_for_public - - *get_clang_toolchain_build_scripts - - ${BUILD_TOOLCHAIN_CMD} "${XTENSA_CLANG_TOOLCHAIN}" - - *package_toolchain_old - -linux_amd64_build: - extends: .build_template_old - variables: - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux.sh" + - *add_gitlab_key_snippet -linux_arm64_build: - extends: .build_template_old - image: ${CROSS_ARM_IMAGE} - variables: - PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-arm64.tar.gz" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux-arm64.sh" - -win64_build: - extends: .build_template_old - variables: - PLATFORM_NAME: "${PLATFORM_NAME_WIN}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" - ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-win64.zip" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" - -macos_amd64_build: - extends: .build_template_old - variables: - PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" - ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-macos.tar.gz" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh" +# LLVM Build System used the remote address to show detailed version info, we'll change it to the public repository +.fix_origin_remote_for_public_snippet: &fix_origin_remote_for_public_snippet | + git remote set-url origin "${GH_REPO_HTTPS}" -linux_amd64_testsuite: - stage: test - tags: [ "amd64", "build" ] - needs: - - job: linux_amd64_build - variables: - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" +.fix_origin_remote_for_public: script: - - *get_release_name_old - - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} - - # getting testsuite - - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git - - # preparing testsuite - - export PATH=${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/:$PATH - - cd llvm-xtensa-testsuite - - # qemu - - ./qemu_esp32_install.sh - - # run testsuite for esp32 - - ./run_esp32_tests.sh + - *fix_origin_remote_for_public_snippet - # run testsuite for compiler_rt library - - ./run_esp32_crt_tests.sh ../$XTENSA_CLANG_TOOLCHAIN - -##################### END OF TEMPORARY LEGACY CODE ######################## -########################################################################### +.get_clang_toolchain_build_scripts_snippet: &get_clang_toolchain_build_scripts_snippet | + git clone -b ${XTENSA_CLANG_TOOLCHAIN_REF} ${GITLAB_SSH_SERVER}/${XTENSA_CLANG_TOOLCHAIN_REPO} + cp -r xtensa-clang-toolchain/* . -upload_to_http: - stage: private_deploy - when: manual - allow_failure: true - tags: [ "deploy", "shiny" ] - variables: - # force the fetch strategy to clean old archives up in dist/ dir - GIT_STRATEGY: fetch - before_script: - - *use_ci_tools +.get_clang_toolchain_build_scripts: script: - - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" - # List of archives - - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) - - cd ${DIST_DIR} - - scp ${FILES} ${HTTP_UPLOAD_DIR}/ct-ng/llvm-builds - # Show info - - echo -e "\nArchives were published there:\n\n$(for n in ${FILES}; do echo "${HTTP_PUBLIC_DIR}/ct-ng/llvm-builds/${n}"; done)\n" + - *get_clang_toolchain_build_scripts_snippet -upload_to_github: - stage: public_deploy - when: manual - allow_failure: true - only: - - tags - tags: [ "amd64", "internet" ] - image: espressif/github-hub:2 - variables: - GIT_STRATEGY: fetch - GITHUB_TOKEN: "${GH_TOKEN}" - GITHUB_REPO: "${GH_REPO_HTTPS}" - TAG: "${CI_COMMIT_TAG}" - before_script: [] - script: - - ls -l dist*/ - - git remote add github ${GH_REPO_HTTPS} - - hub release show ${TAG} || { echo "Please create a release on GitHub with ${TAG} tag at first"; exit 1; } - # List of archives - - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) - - cd ${DIST_DIR} - - ls -l $FILES - # Upload archives - - for n in ${FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done +before_script: + - !reference [.use_ci_tools, script] + - !reference [.add_gitlab_key, script] + +include: + - local: .universal-toolchain-release.yml + rules: + - if: $ESP_CLANG_LEGACY_RELEASE != "true" + - local: .legacy-release.yml + rules: + - if: $ESP_CLANG_LEGACY_RELEASE == "true" diff --git a/.legacy-release.yml b/.legacy-release.yml new file mode 100644 index 00000000000000..c46195f3fe4751 --- /dev/null +++ b/.legacy-release.yml @@ -0,0 +1,164 @@ + +.get_release_name_legacy: &get_release_name_legacy | + # using annotated tags + REL_NUM=$(git describe --abbrev=7) + REL_SFX="llvm15_0_0" + REL_NAME=${CONF_TARGET}-${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} + ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} + echo "PLATFORM_NAME: $PLATFORM_NAME" + echo "REL_NUM: $REL_NUM" + echo "REL_NAME: $REL_NAME" + echo "ARCHIVE_NAME: $ARCHIVE_NAME" + +.get_gcc_toolchain_legacy: &get_gcc_toolchain_legacy | + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/${XTENSA_GCC_TOOLCHAIN} + ${UNARCHIVE_TOOL} ${XTENSA_GCC_TOOLCHAIN} + if [[ "$XTENSA_GCC_TOOLCHAIN" == *"linux-amd64"* ]]; then + cp -r xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} + else + mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz + tar -xf xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz + fi + export GCC_ESP32_LINUX_TOOLCHAIN="xtensa-esp32-elf" + +.package_toolchain_legacy: &package_toolchain_legacy | + ${ARCHIVE_TOOL} ${ARCHIVE_NAME} ${XTENSA_CLANG_TOOLCHAIN}/ + mkdir -p ${DIST_DIR} + mv ${ARCHIVE_NAME} ${DIST_DIR}/ + echo "${ARCHIVE_NAME}" > ${DIST_DIR}/file_${PLATFORM_NAME}_${CONF_TARGET} + +.build_template_legacy: + stage: build + tags: [ "amd64", "build" ] + artifacts: + paths: + - ${DIST_DIR}/ + when: always + expire_in: 10 day + variables: + XTENSA_CLANG_TOOLCHAIN_REF: "release_esp32_clang_15.0.0_gcc_8.4.0" + GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" + script: + - *get_release_name_legacy + - *get_gcc_toolchain_legacy + - !reference [.fix_origin_remote_for_public, script] + - !reference [.get_clang_toolchain_build_scripts, script] + - ${BUILD_TOOLCHAIN_CMD} "${XTENSA_CLANG_TOOLCHAIN}" + - *package_toolchain_legacy + +linux_amd64_build: + extends: .build_template_legacy + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux.sh" + +linux_arm64_build: + extends: .build_template_legacy + image: ${CROSS_ARM_IMAGE} + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-arm64.tar.gz" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux-arm64.sh" + +win64_build: + extends: .build_template_legacy + variables: + PLATFORM_NAME: "${PLATFORM_NAME_WIN}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" + ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-win64.zip" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" + +macos_amd64_build: + extends: .build_template_legacy + variables: + PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" + ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-macos.tar.gz" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh" + +linux_amd64_testsuite: + stage: test + tags: [ "amd64", "build" ] + needs: + - job: linux_amd64_build + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + LLVM_GCC_TESTSUITE_REF: "feature/ci_llvm_multitarget_crt_tests" + script: + - *get_release_name_legacy + - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} + + # getting testsuite + - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git + + # preparing testsuite + - export PATH=${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/:$PATH + - cd llvm-xtensa-testsuite + + # qemu + - ./qemu_esp32_install.sh + + # run testsuite for esp32 + - ./run_esp32_tests.sh + + # run testsuite for compiler_rt library + - ./run_esp32_crt_tests.sh ../$XTENSA_CLANG_TOOLCHAIN + +upload_to_http_legacy: + stage: private_deploy + when: manual + allow_failure: true + tags: [ "deploy", "shiny" ] + variables: + # force the fetch strategy to clean old archives up in dist/ dir + GIT_STRATEGY: fetch + before_script: + - !reference [.use_ci_tools, script] + script: + - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" + # List of archives + - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) + - cd ${DIST_DIR} + - scp ${FILES} ${HTTP_UPLOAD_DIR}/ct-ng/llvm-builds + # Show info + - echo -e "\nArchives were published there:\n\n$(for n in ${FILES}; do echo "${HTTP_PUBLIC_DIR}/ct-ng/llvm-builds/${n}"; done)\n" + +upload_to_github_legacy: + stage: public_deploy + when: manual + allow_failure: true + only: + - tags + tags: [ "amd64", "internet" ] + image: espressif/github-hub:2 + variables: + GIT_STRATEGY: fetch + GITHUB_TOKEN: "${GH_TOKEN}" + GITHUB_REPO: "${GH_REPO_HTTPS}" + TAG: "${CI_COMMIT_TAG}" + before_script: [] + script: + - ls -l dist*/ + - git remote add github ${GH_REPO_HTTPS} + - hub release show ${TAG} || { echo "Please create a release on GitHub with ${TAG} tag at first"; exit 1; } + # List of archives + - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) + - cd ${DIST_DIR} + - ls -l $FILES + # Upload archives + - for n in ${FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml new file mode 100644 index 00000000000000..baf00964c24399 --- /dev/null +++ b/.universal-toolchain-release.yml @@ -0,0 +1,409 @@ + +# Prepare release name/number +.get_release_name: &get_release_name | + # using annotated tags + REL_NUM=$(git describe --abbrev=7) + REL_NAME=${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} + ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} + LIBS_ARCHIVE_NAME=libs_${REL_NAME}.${LIBS_ARCHIVE_EXT} + echo "PLATFORM_NAME: $PLATFORM_NAME" + echo "REL_NUM: $REL_NUM" + echo "REL_NAME: $REL_NAME" + echo "ARCHIVE_NAME: $ARCHIVE_NAME" + +# Get an existing crosstool-ng builds for all chips +.get_gcc_toolchain: &get_gcc_toolchain | + declare -a XTENSA_CPUS=("esp32" + "esp32s2" + "esp32s3") + for ((i = 0; i < ${#XTENSA_CPUS[@]}; i++)); do + XTENSA_CPU=${XTENSA_CPUS[$i]} + GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${GCC_ARCHIVE_EXT} + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} + ${GCC_UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} + done; + GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${GCC_ARCHIVE_EXT} + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} + ${GCC_UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} + +# Pack the toolchain +.package_toolchain: &package_toolchain | + ${ARCHIVE_TOOL} ${ARCHIVE_NAME} esp-clang/ + mkdir -p ${DISTRO_DIR} + mv ${ARCHIVE_NAME} ${DISTRO_DIR}/ + echo "${ARCHIVE_NAME}" > ${DISTRO_DIR}/file_${PLATFORM_NAME} + +# Pack libs to be used for Rust, Go etc. +.package_libs: &package_libs | + ${LIBS_ARCHIVE_TOOL} ${LIBS_ARCHIVE_NAME} esp-clang/lib/libclang* esp-clang/lib/clang/${CLANG_VER}/include + mkdir -p ${DISTRO_DIR} + mv ${LIBS_ARCHIVE_NAME} ${DISTRO_DIR}/ + echo "${LIBS_ARCHIVE_NAME}" > ${DISTRO_DIR}/file_libs-${PLATFORM_NAME} + +.get_binutils: &get_binutils | + git clone -b ${BINUTILS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${BINUTILS_REPO}.git + BINUTILS_PATH=$PWD/${BINUTILS_REPO} + +.get_xtensa_overlays: &get_xtensa_overlays | + git clone -b ${XTENSA_OVERLAYS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${XTENSA_OVERLAYS_REPO}.git + XTENSA_OVERLAYS_PATH=$PWD/${XTENSA_OVERLAYS_REPO} + +.get_newlib: &get_newlib | + git clone -b ${NEWLIB_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${NEWLIB_REPO}.git + NEWLIB_PATH=$PWD/${NEWLIB_REPO} + +.build_template: + stage: build + tags: [ "amd64", "build" ] + artifacts: + paths: + - ${DIST_DIR}/ + - ${BUILD_DIR}/tests.log + - ${BUILD_DIR}/build.log + when: always + expire_in: 1 day + variables: + BUILD_TOOLCHAIN_CMD_EXTRA_ARGS: "" + script: + - *get_release_name + - mkdir ${DOWNLOADS_DIR} + - pushd ${DOWNLOADS_DIR} + - ESP_GCC_TOOLCHAIN_DIST_BASE=$PWD + - *get_gcc_toolchain + - *get_binutils + - *get_xtensa_overlays + - popd + - !reference [.get_clang_toolchain_build_scripts, script] + - !reference [.fix_origin_remote_for_public, script] + - LLVM_PROJECT_PATH=$PWD + - BUILD_PATH=$PWD/${BUILD_DIR} + - mkdir -p ${BUILD_PATH} + - export USE_PARALLEL_LINK_JOBS=2 + # build Clang toolchain w/o newlib + - ${BUILD_TOOLCHAIN_CMD} --llvm-path=${LLVM_PROJECT_PATH} + --gcc-toolchains-path=${ESP_GCC_TOOLCHAIN_DIST_BASE} --binutils-path=${BINUTILS_PATH} + --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} --host=${CONF_HOST} ${BUILD_TOOLCHAIN_CMD_EXTRA_ARGS} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log + - BUILD_HOST=$(gcc -dumpmachine) + # Do not run unit tests for cross-builds. + # Run as non-root user because permission tests fail when run by root. + - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then + export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-${CONF_HOST}-Release; + echo "Run unit tests for native build in ${LLVM_BUILD_PATH}"; + useradd -m test_runner; + chown -R test_runner ${LLVM_BUILD_PATH}; + touch ${BUILD_PATH}/tests.log; + chmod o+w ${BUILD_PATH}/tests.log; + runuser -l test_runner -c 'cmake --build '${LLVM_BUILD_PATH}' --target check-all 2>&1 > '${BUILD_PATH}'/tests.log'; + fi + - export DISTRO_DIR=$PWD/$DIST_DIR + - pushd ${BUILD_PATH} + - *package_toolchain + - popd + +.build_linux-gnu_template: + extends: .build_template + variables: + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + GCC_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + GCC_ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" + +build_x86_64-linux-gnu: + extends: .build_linux-gnu_template + variables: + CONF_HOST: "x86_64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + +build_arm-linux-gnueabihf: + extends: .build_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + variables: + CONF_HOST: "arm-linux-gnueabihf" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARMHF}" + +build_aarch64-linux-gnu: + extends: .build_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + variables: + CONF_HOST: "aarch64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" + +build_x86_64-w64-mingw32: + extends: .build_template + needs: + # needs native toolchain and newlib from this job + - job: build_x86_64-linux-gnu + before_script: + - !reference [.use_ci_tools, script] + - !reference [.add_gitlab_key, script] + # get ARCHIVE_NAME for Linux release. Modify vars to make get_release_name working properly + - CLANG_LINUX_ARCHIVE=$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) + # unpack x86_64-linux-gnu toolchain to re-use it as native Clang for Windows build + - mkdir -p esp-clang-${PLATFORM_NAME_LINUX} + - ${UNARCHIVE_TOOL_LINUX} ${DIST_DIR}/${CLANG_LINUX_ARCHIVE} -C esp-clang-${PLATFORM_NAME_LINUX} + # we do not want to keep artifacts from 'x86_64-linux-gnu' job + - rm -rf ${DIST_DIR} + - rm -rf ${BUILD_DIR} + # add build command args speciifc for Windows build + - export BUILD_TOOLCHAIN_CMD_EXTRA_ARGS="--native-esp-clang-path=$PWD/esp-clang-${PLATFORM_NAME_LINUX}" + variables: + CONF_HOST: "x86_64-w64-mingw32" + PLATFORM_NAME: "${PLATFORM_NAME_WIN}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + GCC_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" + GCC_ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" + BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" + +.build_apple-darwin_template: + extends: .build_template + variables: + ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" + ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + GCC_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" + GCC_ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" + +build_x86_64-apple-darwin: + extends: .build_apple-darwin_template + variables: + CONF_HOST: "x86_64-apple-darwin21.1" + PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" + +build_aarch64-apple-darwin: + extends: .build_apple-darwin_template + variables: + CONF_HOST: "aarch64-apple-darwin21.1" + PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" + +build_newlib: + stage: build + tags: [ "amd64", "build" ] + needs: + # needs native toolchainfrom this job + - job: build_x86_64-linux-gnu + artifacts: + paths: + - ${DIST_DIR}/ + - ${BUILD_DIR}/build.log + when: always + expire_in: 1 day + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + script: + # get ARCHIVE_NAME for Linux release. + - CLANG_ARCHIVE=$PWD/${DIST_DIR}/$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) + - mkdir -p ${DOWNLOADS_DIR} + - pushd ${DOWNLOADS_DIR} + - *get_xtensa_overlays + - *get_newlib + # unpack clang + - ${UNARCHIVE_TOOL} ${CLANG_ARCHIVE} + - export PATH=$PWD/esp-clang/bin:$PATH + - popd + - rm -rf $PWD/${DIST_DIR} + - !reference [.get_clang_toolchain_build_scripts, script] + # build newlib overlay using ESP native (Linux) clang toolchain only + # it will be re-used for cross-buit toolchains (win and mac). + - NEWLIB_OVERLAY_DISTRO_PATH=$PWD/${DIST_DIR} + - mkdir -p ${NEWLIB_OVERLAY_DISTRO_PATH} + - BUILD_PATH=$PWD/${BUILD_DIR} + - mkdir -p ${BUILD_PATH} + - ./build-toolchain.sh --newlib-path=${NEWLIB_PATH} --xtensa-overlays-path=${XTENSA_OVERLAYS_PATH} ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log + - pushd ${BUILD_PATH} + - ${ARCHIVE_TOOL_NEWLIB} ${NEWLIB_OVERLAY_DISTRO_PATH}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} esp-clang/ + - popd + +.pack_template: + stage: pack + tags: [ "amd64", "build" ] + artifacts: + paths: + - ${DIST_DIR}/ + when: always + expire_in: 3 day + script: + - *get_release_name + - export BUILD_PATH=$PWD/${BUILD_DIR} + - mkdir -p ${BUILD_PATH} + # unpack clang + - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} -C ${BUILD_PATH} + # unpack newlib + - ${UNARCHIVE_TOOL_NEWLIB} ${DIST_DIR}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} -C ${BUILD_PATH} + - rm -rf ${DIST_DIR} + - !reference [.get_clang_toolchain_build_scripts, script] + # strip binutils afer newlib is built + - STRIP_BINUTILS=YES ./build-toolchain.sh --host=${CONF_HOST} ${BUILD_PATH} + - DISTRO_DIR=$PWD/${DIST_DIR} + - pushd ${BUILD_PATH} + - *package_toolchain + - *package_libs + - popd + +.pack_linux-gnu_template: + extends: .pack_template + variables: + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + +pack_x86_64-linux-gnu: + extends: .pack_linux-gnu_template + needs: + - job: build_x86_64-linux-gnu + - job: build_newlib + variables: + CONF_HOST: "x86_64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + +pack_arm-linux-gnueabihf: + extends: .pack_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + needs: + - job: build_arm-linux-gnueabihf + - job: build_newlib + variables: + CONF_HOST: "arm-linux-gnueabihf" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARMHF}" + +pack_aarch64-linux-gnu: + extends: .pack_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + needs: + - job: build_aarch64-linux-gnu + - job: build_newlib + variables: + CONF_HOST: "aarch64-linux-gnu" + PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" + +pack_x86_64-w64-mingw32: + extends: .pack_template + needs: + - job: build_x86_64-w64-mingw32 + - job: build_newlib + variables: + CONF_HOST: "x86_64-w64-mingw32" + PLATFORM_NAME: "${PLATFORM_NAME_WIN}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" + LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" + LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" + +.pack_apple-darwin_template: + extends: .pack_template + variables: + ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" + ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" + LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" + LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + +pack_x86_64-apple-darwin: + extends: .pack_apple-darwin_template + needs: + - job: build_x86_64-apple-darwin + - job: build_newlib + variables: + CONF_HOST: "x86_64-apple-darwin21.1" + PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" + +pack_aarch64-apple-darwin: + extends: .pack_apple-darwin_template + needs: + - job: build_aarch64-apple-darwin + - job: build_newlib + variables: + CONF_HOST: "aarch64-apple-darwin21.1" + PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" + +test_x86_64-linux-gnu: + stage: test + tags: [ "amd64", "build" ] + needs: + - job: pack_x86_64-linux-gnu + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + script: + - *get_release_name + - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} + # getting testsuite + - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git + # preparing testsuite + - export PATH=${PWD}/esp-clang/bin:$PATH + - cd llvm-xtensa-testsuite + # qemu + - ./qemu_esp32_install.sh + # run testsuite for esp32 + - ./run_esp32_tests.sh + +upload_to_http: + stage: private_deploy + when: manual + allow_failure: true + tags: [ "deploy", "shiny" ] + variables: + # force the fetch strategy to clean old archives up in dist/ dir + GIT_STRATEGY: fetch + needs: + - job: pack_x86_64-linux-gnu + - job: pack_arm-linux-gnueabihf + - job: pack_aarch64-linux-gnu + - job: pack_x86_64-w64-mingw32 + - job: pack_x86_64-apple-darwin + - job: pack_aarch64-apple-darwin + before_script: + - !reference [.use_ci_tools, script] + script: + - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" + # List of archives + - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) + - cd ${DIST_DIR} + - ls -l $FILES + - scp ${FILES} ${HTTP_UPLOAD_DIR}/ct-ng/llvm-builds + # Show info + - echo -e "\nArchives were published there:\n\n$(for n in ${FILES}; do echo "${HTTP_PUBLIC_DIR}/ct-ng/llvm-builds/${n}"; done)\n" + +upload_to_github: + stage: public_deploy + when: manual + allow_failure: true + only: + - tags + tags: [ "amd64", "internet" ] + image: espressif/github-hub:2 + variables: + GIT_STRATEGY: fetch + GITHUB_TOKEN: "${GH_TOKEN}" + GITHUB_REPO: "${GH_REPO_HTTPS}" + TAG: "${CI_COMMIT_TAG}" + needs: + - job: pack_x86_64-linux-gnu + - job: pack_arm-linux-gnueabihf + - job: pack_aarch64-linux-gnu + - job: pack_x86_64-w64-mingw32 + - job: pack_x86_64-apple-darwin + - job: pack_aarch64-apple-darwin + before_script: [] + script: + - ls -l dist*/ + - git remote add github ${GH_REPO_HTTPS} + - hub release show ${TAG} || { echo "Please create a release on GitHub with ${TAG} tag at first"; exit 1; } + # List of archives + - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) + - cd ${DIST_DIR} + - ls -l $FILES + # Upload archives + - for n in ${FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done From 4eb677a63b4f1fc78a12e24d265620e5ccba42a1 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:14 +0300 Subject: [PATCH 118/261] esp/ci: Adds MacOS binaries signing stage --- .gitlab-ci.yml | 1 + .universal-toolchain-release.yml | 59 +++++++++++++++++++++++++++++--- 2 files changed, 56 insertions(+), 4 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d4a2c816f97ef4..e152a1c90a6e9e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,6 +1,7 @@ stages: - build - pack + - sign - private_deploy - test - public_deploy diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index baf00964c24399..3f15eb9637a31a 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -349,6 +349,57 @@ test_x86_64-linux-gnu: # run testsuite for esp32 - ./run_esp32_tests.sh +.macos_codesign: &macos_codesign + stage: sign + tags: [ "darwin", "amd64" ] + resource_group: macos_codesign + artifacts: + paths: + - ${DIST_DIR}/ + when: always + expire_in: 3 day + variables: + KEYCHAIN_NAME: "llvm.keychain" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" + ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + script: + - *get_release_name + - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} + - rm -rf ${DIST_DIR} + - TOOLCHAIN_PATH=$PWD/esp-clang + - echo $MACOS_CERTIFICATE | base64 --decode > $PWD/certificate.p12 + - security create-keychain -p $KEYCHAIN_PWD $KEYCHAIN_NAME || true + - security import $PWD/certificate.p12 -k $KEYCHAIN_NAME -P $MACOS_CERTIFICATE_PWD -T /usr/bin/codesign + - security set-key-partition-list -S apple-tool:,apple:,codesign -s -k $KEYCHAIN_PWD $KEYCHAIN_NAME + - security list-keychains -d user -s ~/Library/Keychains/$KEYCHAIN_NAME + - security find-identity -v -p codesigning + - security unlock-keychain -p $KEYCHAIN_PWD $KEYCHAIN_NAME + - /usr/bin/codesign -v --force --options runtime -s $IDENTITY_ID $TOOLCHAIN_PATH/bin/* $TOOLCHAIN_PATH/lib/*.dylib + - security delete-keychain $KEYCHAIN_NAME + - codesign -dvv $TOOLCHAIN_PATH/bin/* + - DISTRO_DIR=$PWD/${DIST_DIR} + - *package_toolchain + - *package_libs + after_script: + - security find-identity -v + - security delete-keychain $KEYCHAIN_NAME + - security find-identity -v + +sign_x86_64-apple-darwin: + extends: .macos_codesign + needs: + - pack_x86_64-apple-darwin + variables: + PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" + +sign_aarch64-apple-darwin: + extends: .macos_codesign + needs: + - pack_aarch64-apple-darwin + variables: + PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" + upload_to_http: stage: private_deploy when: manual @@ -362,8 +413,8 @@ upload_to_http: - job: pack_arm-linux-gnueabihf - job: pack_aarch64-linux-gnu - job: pack_x86_64-w64-mingw32 - - job: pack_x86_64-apple-darwin - - job: pack_aarch64-apple-darwin + - job: sign_x86_64-apple-darwin + - job: sign_aarch64-apple-darwin before_script: - !reference [.use_ci_tools, script] script: @@ -394,8 +445,8 @@ upload_to_github: - job: pack_arm-linux-gnueabihf - job: pack_aarch64-linux-gnu - job: pack_x86_64-w64-mingw32 - - job: pack_x86_64-apple-darwin - - job: pack_aarch64-apple-darwin + - job: sign_x86_64-apple-darwin + - job: sign_aarch64-apple-darwin before_script: [] script: - ls -l dist*/ From fae16f8b9bc2e9ddafe86cda849717c793042b4e Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:14 +0300 Subject: [PATCH 119/261] [Xtensa] Xtensa ABI 128bit arg alignment - Forces 128bit arguments to have 128bit alignment as per the Xtensa ABI in LLVM & Clang. - Adds a check in the Xtensa calling convention to ensure 128bit aligned arguments are always passed as the first argument _or_ passed via the stack. --- clang/lib/Basic/Targets/Xtensa.h | 2 +- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 9 +++++++-- llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp | 2 +- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index 26dba0225014f4..a23b28684e709a 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -49,7 +49,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { WIntType = UnsignedInt; UseZeroLengthBitfieldAlignment = true; MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; - resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32"); + resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32"); } void getTargetDefines(const LangOptions &Opts, diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 8943a18de867af..f25b6a7f235fc1 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -762,14 +762,19 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, unsigned Reg; Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); - bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8)); + bool needs64BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(8)); + bool needs128BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(16)); if (ValVT == MVT::i32 || ValVT == MVT::f32) { Reg = State.AllocateReg(IntRegs); // If this is the first part of an i64 arg, // the allocated register must be either A2, A4 or A6. - if (isI64 && (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7)) + if (needs64BitAlign && (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7)) Reg = State.AllocateReg(IntRegs); + // arguments with 16byte alignment must be passed in the first register or passed via stack + if (needs128BitAlign && Reg != Xtensa::A2) + while ( (Reg = State.AllocateReg(IntRegs)) ) { + } LocVT = MVT::i32; } else if (ValVT == MVT::f64) { // Allocate int register and shadow next int register. diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index faa0f950ee6082..b9e90d356c3aae 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -34,7 +34,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTarget() { static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool IsLittle) { - std::string Ret = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32"; + std::string Ret = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32"; return Ret; } From abbffc00643bf25bb430959825a99a5fb56a80f5 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Sep 2023 01:35:28 +0300 Subject: [PATCH 120/261] [Xtensa] Fix Call ABI for 16 byte alignment. --- clang/lib/CodeGen/Targets/Xtensa.cpp | 7 ++++--- clang/test/CodeGen/xtensa-abi.c | 14 ++++++++++++++ 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/clang/lib/CodeGen/Targets/Xtensa.cpp b/clang/lib/CodeGen/Targets/Xtensa.cpp index 506e92ea76ffce..f3e0170dda6d26 100644 --- a/clang/lib/CodeGen/Targets/Xtensa.cpp +++ b/clang/lib/CodeGen/Targets/Xtensa.cpp @@ -94,9 +94,8 @@ ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty, if (Size < 32 && Ty->isIntegralOrEnumerationType() && !MustUseStack) { return extendType(Ty); } - if (Size == 64) - return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64)); - return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 32)); + // Assume that type has 32, 64 or 128 bits + return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size)); } // Aggregates which are <= 6*32 will be passed in registers if possible, @@ -107,6 +106,8 @@ ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty, } else if (NeededAlign == (2 * 32)) { return ABIArgInfo::getDirect(llvm::ArrayType::get( llvm::IntegerType::get(getVMContext(), 64), NeededArgGPRs / 2)); + } else if (NeededAlign == (4 * 32)) { + return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 128)); } else { return ABIArgInfo::getDirect(llvm::ArrayType::get( llvm::IntegerType::get(getVMContext(), 32), NeededArgGPRs)); diff --git a/clang/test/CodeGen/xtensa-abi.c b/clang/test/CodeGen/xtensa-abi.c index df7a99d77bc0f4..25b1fbd2d1b97c 100644 --- a/clang/test/CodeGen/xtensa-abi.c +++ b/clang/test/CodeGen/xtensa-abi.c @@ -12,3 +12,17 @@ char *bufalloc () } // CHECK: define dso_local noalias ptr @bufalloc() #0 { + +struct S16 { int a[4]; } __attribute__ ((aligned (16))); + +void callee_struct_a16b_1(struct S16 a) {} + +// CHECK: define dso_local void @callee_struct_a16b_1(i128 %a.coerce) + +void callee_struct_a16b_2(struct S16 a, int b) {} + +// CHECK: define dso_local void @callee_struct_a16b_2(i128 %a.coerce, i32 noundef %b) + +void callee_struct_a16b_3(int a, struct S16 b) {} + +// CHECK: define dso_local void @callee_struct_a16b_3(i32 noundef %a, %struct.S16* noundef byval(%struct.S16) align 16 %b) From 6e4476c87fe3a80726e9055381f9825182a26736 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:15 +0300 Subject: [PATCH 121/261] [Xtensa] Add IR test for 16byte alignment. --- .../test/CodeGen/Xtensa/calling-conv-call8.ll | 170 ++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 llvm/test/CodeGen/Xtensa/calling-conv-call8.ll diff --git a/llvm/test/CodeGen/Xtensa/calling-conv-call8.ll b/llvm/test/CodeGen/Xtensa/calling-conv-call8.ll new file mode 100644 index 00000000000000..16056b99101fb8 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/calling-conv-call8.ll @@ -0,0 +1,170 @@ +; RUN: llc -mtriple=xtensa -mcpu=esp32 -O1 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=XTENSA-STRUCT16 %s +; RUN: llc -mtriple=xtensa -mcpu=esp32 -O1 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=XTENSA-I128 %s + +%struct.S = type { [4 x i32] } + +@v = dso_local global i32 0, align 4 + +define dso_local void @caller_struct_a128b_1([4 x i32] %0) { + +; XTENSA-STRUCT16-LABEL: caller_struct_a128b_1: +; XTENSA-STRUCT16-NEXT: .cfi_startproc +; XTENSA-STRUCT16: # %bb.0: +; XTENSA-STRUCT16-NEXT: entry a1, 32 +; XTENSA-STRUCT16-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-STRUCT16-NEXT: l32r a8, .LCPI0_0 +; XTENSA-STRUCT16-NEXT: mov.n a10, a2 +; XTENSA-STRUCT16-NEXT: mov.n a11, a3 +; XTENSA-STRUCT16-NEXT: mov.n a12, a4 +; XTENSA-STRUCT16-NEXT: mov.n a13, a5 +; XTENSA-STRUCT16-NEXT: callx8 a8 +; XTENSA-STRUCT16-NEXT: retw.n + + call void @callee_struct_a128b_1([4 x i32] %0) + ret void +} + +declare dso_local void @callee_struct_a128b_1([4 x i32]) + +define dso_local void @caller_struct_a128b_2([4 x i32] %0) { +; XTENSA-STRUCT16-LABEL: caller_struct_a128b_2: +; XTENSA-STRUCT16: .cfi_startproc +; XTENSA-STRUCT16-NEXT: # %bb.0: +; XTENSA-STRUCT16-NEXT: entry a1, 32 +; XTENSA-STRUCT16-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-STRUCT16-NEXT: l32r a8, .LCPI1_0 +; XTENSA-STRUCT16-NEXT: l32i.n a14, a8, 0 +; XTENSA-STRUCT16-NEXT: l32r a8, .LCPI1_1 +; XTENSA-STRUCT16-NEXT: mov.n a10, a2 +; XTENSA-STRUCT16-NEXT: mov.n a11, a3 +; XTENSA-STRUCT16-NEXT: mov.n a12, a4 +; XTENSA-STRUCT16-NEXT: mov.n a13, a5 +; XTENSA-STRUCT16-NEXT: callx8 a8 +; XTENSA-STRUCT16-NEXT: retw.n + + %2 = load i32, i32* @v, align 4 + call void @callee_struct_a128b_2([4 x i32] %0, i32 noundef %2) + ret void +} + +declare dso_local void @callee_struct_a128b_2([4 x i32], i32 noundef) + +define dso_local void @caller_struct_a128b_3([4 x i32] %0) { +; XTENSA-STRUCT16-LABEL: caller_struct_a128b_3: +; XTENSA-STRUCT16: .cfi_startproc +; XTENSA-STRUCT16-NEXT: # %bb.0: +; XTENSA-STRUCT16-NEXT: entry a1, 64 +; XTENSA-STRUCT16-NEXT: .cfi_def_cfa_offset 64 +; XTENSA-STRUCT16-NEXT: s32i.n a5, a1, 28 +; XTENSA-STRUCT16-NEXT: s32i.n a4, a1, 24 +; XTENSA-STRUCT16-NEXT: s32i.n a3, a1, 20 +; XTENSA-STRUCT16-NEXT: s32i.n a2, a1, 16 +; XTENSA-STRUCT16-NEXT: l32r a8, .LCPI2_0 +; XTENSA-STRUCT16-NEXT: l32i.n a10, a8, 0 +; XTENSA-STRUCT16-NEXT: l32i.n a8, a1, 28 +; XTENSA-STRUCT16-NEXT: s32i.n a8, a1, 12 +; XTENSA-STRUCT16-NEXT: l32i.n a8, a1, 24 +; XTENSA-STRUCT16-NEXT: s32i.n a8, a1, 8 +; XTENSA-STRUCT16-NEXT: l32i.n a8, a1, 20 +; XTENSA-STRUCT16-NEXT: s32i.n a8, a1, 4 +; XTENSA-STRUCT16-NEXT: l32i.n a8, a1, 16 +; XTENSA-STRUCT16-NEXT: s32i.n a8, a1, 0 +; XTENSA-STRUCT16-NEXT: l32r a8, .LCPI2_1 +; XTENSA-STRUCT16-NEXT: callx8 a8 +; XTENSA-STRUCT16-NEXT: retw.n + + %2 = alloca %struct.S, align 16 + %3 = extractvalue [4 x i32] %0, 0 + %4 = getelementptr inbounds %struct.S, %struct.S* %2, i32 0, i32 0, i32 0 + store i32 %3, i32* %4, align 16 + %5 = extractvalue [4 x i32] %0, 1 + %6 = getelementptr inbounds %struct.S, %struct.S* %2, i32 0, i32 0, i32 1 + store i32 %5, i32* %6, align 4 + %7 = extractvalue [4 x i32] %0, 2 + %8 = getelementptr inbounds %struct.S, %struct.S* %2, i32 0, i32 0, i32 2 + store i32 %7, i32* %8, align 8 + %9 = extractvalue [4 x i32] %0, 3 + %10 = getelementptr inbounds %struct.S, %struct.S* %2, i32 0, i32 0, i32 3 + store i32 %9, i32* %10, align 4 + %11 = load i32, i32* @v, align 4 + call void @callee_struct_a128b_3(i32 noundef %11, %struct.S* noundef nonnull byval(%struct.S) align 16 %2) + ret void +} + +declare dso_local void @callee_struct_a128b_3(i32 noundef, %struct.S* noundef byval(%struct.S) align 16) + +define dso_local void @caller_i128b_1(i128 noundef %0) { +; XTENSA-I128-LABEL: caller_i128b_1: +; XTENSA-I128: .cfi_startproc +; XTENSA-I128-NEXT: # %bb.0: +; XTENSA-I128-NEXT: entry a1, 32 +; XTENSA-I128-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-I128-NEXT: l32r a8, .LCPI3_0 +; XTENSA-I128-NEXT: mov.n a10, a2 +; XTENSA-I128-NEXT: mov.n a11, a3 +; XTENSA-I128-NEXT: mov.n a12, a4 +; XTENSA-I128-NEXT: mov.n a13, a5 +; XTENSA-I128-NEXT: callx8 a8 +; XTENSA-I128-NEXT: retw.n + + call void @callee_i128b_1(i128 noundef %0) + ret void +} + +declare dso_local void @callee_i128b_1(i128 noundef) + +define dso_local void @caller_i128b_2(i128 noundef %0) { +; XTENSA-I128-LABEL: caller_i128b_2: +; XTENSA-I128: .cfi_startproc +; XTENSA-I128-NEXT: # %bb.0: +; XTENSA-I128-NEXT: entry a1, 32 +; XTENSA-I128-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-I128-NEXT: l32r a8, .LCPI4_0 +; XTENSA-I128-NEXT: l32i.n a14, a8, 0 +; XTENSA-I128-NEXT: l32r a8, .LCPI4_1 +; XTENSA-I128-NEXT: mov.n a10, a2 +; XTENSA-I128-NEXT: mov.n a11, a3 +; XTENSA-I128-NEXT: mov.n a12, a4 +; XTENSA-I128-NEXT: mov.n a13, a5 +; XTENSA-I128-NEXT: callx8 a8 +; XTENSA-I128-NEXT: retw.n + + %2 = load i32, i32* @v, align 4 + call void @callee_i128b_2(i128 noundef %0, i32 noundef %2) + ret void +} + +declare dso_local void @callee_i128b_2(i128 noundef, i32 noundef) + +define dso_local void @caller_i128b_3(i128 noundef %0) { +; XTENSA-I128-LABEL: caller_i128b_3: +; XTENSA-I128: .cfi_startproc +; XTENSA-I128-NEXT: # %bb.0: +; XTENSA-I128-NEXT: entry a1, 64 +; XTENSA-I128-NEXT: .cfi_def_cfa_offset 64 +; XTENSA-I128-NEXT: s32i.n a5, a1, 28 +; XTENSA-I128-NEXT: s32i.n a4, a1, 24 +; XTENSA-I128-NEXT: s32i.n a3, a1, 20 +; XTENSA-I128-NEXT: s32i.n a2, a1, 16 +; XTENSA-I128-NEXT: l32r a8, .LCPI5_0 +; XTENSA-I128-NEXT: l32i.n a10, a8, 0 +; XTENSA-I128-NEXT: l32i.n a8, a1, 28 +; XTENSA-I128-NEXT: s32i.n a8, a1, 12 +; XTENSA-I128-NEXT: l32i.n a8, a1, 24 +; XTENSA-I128-NEXT: s32i.n a8, a1, 8 +; XTENSA-I128-NEXT: l32i.n a8, a1, 20 +; XTENSA-I128-NEXT: s32i.n a8, a1, 4 +; XTENSA-I128: l32r a8, .LCPI5_1 +; XTENSA-I128-NEXT: callx8 a8 +; XTENSA-I128-NEXT: retw.n + + %2 = alloca i128, align 16 + %3 = load i32, i32* @v, align 4 + store i128 %0, i128* %2, align 16 + call void @callee_i128b_3(i32 noundef %3, i128* noundef nonnull byval(i128) align 16 %2) + ret void +} + +declare dso_local void @callee_i128b_3(i32 noundef, i128* noundef byval(i128) align 16) From 0f183aa0661d618d95c4df97b629a2fdaec30395 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:16 +0300 Subject: [PATCH 122/261] esp/ci: Run LLD tests. Output test logs in lld-tests.log --- .universal-toolchain-release.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 3f15eb9637a31a..5292918a32a97f 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -58,6 +58,7 @@ artifacts: paths: - ${DIST_DIR}/ + - ${BUILD_DIR}/lld-tests.log - ${BUILD_DIR}/tests.log - ${BUILD_DIR}/build.log when: always @@ -94,6 +95,9 @@ touch ${BUILD_PATH}/tests.log; chmod o+w ${BUILD_PATH}/tests.log; runuser -l test_runner -c 'cmake --build '${LLVM_BUILD_PATH}' --target check-all 2>&1 > '${BUILD_PATH}'/tests.log'; + touch ${BUILD_PATH}/lld-tests.log; + chmod o+w ${BUILD_PATH}/lld-tests.log; + runuser -l test_runner -c 'cmake --build '${LLVM_BUILD_PATH}' --target lld-test 2>&1 > '${BUILD_PATH}'/lld-tests.log'; fi - export DISTRO_DIR=$PWD/$DIST_DIR - pushd ${BUILD_PATH} From 39ae80ee168ae125c9f3f3f146afd3bc61d41af2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:16 +0300 Subject: [PATCH 123/261] [Xtensa] Fix atomic rmw operation. Fix register liveness in emitAtomicRMW function. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index f25b6a7f235fc1..3ab6687b824c40 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -2545,7 +2545,9 @@ MachineBasicBlock *XtensaTargetLowering::emitAtomicRMW(MachineInstr &MI, const TargetRegisterClass *RC = getRegClassFor(MVT::i32); unsigned R1 = MRI.createVirtualRegister(RC); - BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R1).add(AtomicValAddr).addImm(0); + BuildMI(*BB, MI, DL, TII.get(Xtensa::L32I), R1) + .addReg(AtomicValAddr.getReg()) + .addImm(0); BB = BBLoop; @@ -2609,7 +2611,7 @@ MachineBasicBlock *XtensaTargetLowering::emitAtomicRMW(MachineInstr &MI, BuildMI(BB, DL, TII.get(Xtensa::WSR), Xtensa::SCOMPARE1).addReg(AtomicValPhi); BuildMI(BB, DL, TII.get(Xtensa::S32C1I), R4) .addReg(R2) - .addReg(AtomicValAddr.getReg()) + .addReg(AtomicValAddr.getReg(), getKillRegState(AtomicValAddr.isDead())) .addImm(0); BuildMI(BB, DL, TII.get(Xtensa::MOV_N), AtomicValLoop).addReg(R4); From 0217deb2626d6694f74b1aef4bd4f8306ece67f3 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:17 +0300 Subject: [PATCH 124/261] [Xtensa] Fix Hardware Loop pass. If block with LOOPEND instruction has smaller offset then loop heeader block then try to find appropriate place for LOOPEND instruction after loop header --- llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp | 54 ++++++++++++++++--- 1 file changed, 46 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp b/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp index dc712a91380585..3089d7ee59fbff 100644 --- a/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp @@ -153,8 +153,8 @@ bool XtensaFixupHwLoops::runOnMachineFunction(MachineFunction &mf) { // Scan loop and find hardware loop pseudo instructions LOOPSTART and LOOPEND. // Transform LOOPSTART to Xtensa instructions and remove LOOPEND. bool XtensaFixupHwLoops::fixupLoopInstrs(MachineLoop *L) { - // const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); MachineBasicBlock &MBB = *(L->getHeader()); + const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo(); bool Changed = false; unsigned Num = MBB.getNumber(); unsigned Offset = BlockInfo[Num].Offset; @@ -168,10 +168,17 @@ bool XtensaFixupHwLoops::fixupLoopInstrs(MachineLoop *L) { MachineInstr *PredI1 = nullptr; MachineInstr *FirstMI = nullptr; + // Find appropriate place for the LOOPEND block for (auto MBI = L->block_begin(), MBIE = L->block_end(); MBI != MBIE; ++MBI) { - if (LastBlockOffset < BlockInfo[(*MBI)->getNumber()].Offset) { - LastBlockOffset = BlockInfo[(*MBI)->getNumber()].Offset; - LastBlock = (*MBI); + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; + SmallVector Cond; + if (!TII->analyzeBranch(*(*MBI), TBB, FBB, Cond)) { + if (FBB && TBB) { + if (LastBlockOffset < BlockInfo[(*MBI)->getNumber()].Offset) { + LastBlockOffset = BlockInfo[(*MBI)->getNumber()].Offset; + LastBlock = (*MBI); + } + } } } @@ -220,12 +227,43 @@ bool XtensaFixupHwLoops::fixupLoopInstrs(MachineLoop *L) { DebugLoc DL = PII->getDebugLoc(); unsigned OffsetLE = BlockInfo[PMBB->getNumber()].Offset; - // Check if loop end is placed before loop header - // In such case add special MBB after loop header and create jump - // from loop end to it + // In most cases we expect that blocks in loop are ordered by such manner that block + // with LOOPSTART instruction preceeds block with LOOPEND instruction. + // But in some cases after transformations loop block which contains LOOPEND instruction + // maybe placed before LOOPSTART block during code generaion. We must handle such situation + // because "loop" instruction placed instead of LOOPSTART must have positive offset in the target + // field to the LOOPEND block. + // So, in such situation we add new LOOPEND block after the LOOPSTART block and create jump from old + // LOOPEND block to the new LOOPEND block adn set new LOOPEND block then as target for "loop" instruction if (OffsetLE < LHOffset) { LoopEnd = MF->CreateMachineBasicBlock(); - MF->insert(++LastBlock->getIterator(), LoopEnd); + + // If last block in the loop is whithin 256 byte offset from loop instruction + // then just place LOOPEND block after the last block. + if ((LastBlockOffset - LHOffset) < 256) { + //Insert after appropriate block + MF->insert(++LastBlock->getIterator(), LoopEnd); + } else { + // If loop is to large for hardware loop instructuin offset then + // place LoopEnd block just after loop header + MF->insert(++MBB.getIterator(), LoopEnd); + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; + SmallVector Cond; + if (!TII->analyzeBranch(MBB, TBB, FBB, Cond)) { + if (!FBB) { + // LH block just falls through to its succ + for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; + ++I) { + MachineBasicBlock *Succ = *I; + if (Succ != TBB) { + BuildMI(MBB, MBB.end(), DL, TII->get(Xtensa::J)) + .addMBB(Succ); + } + } + } + } + } + LoopEnd->transferSuccessors(PMBB); LoopEnd->splice(LoopEnd->end(), PMBB, PII, PMBB->end()); From f64bce8d11f04846e34623bd3b662651d977eecc Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Mon, 1 Apr 2024 15:24:02 +0300 Subject: [PATCH 125/261] [Xtensa] Add LLD linker support --- lld/ELF/Arch/Xtensa.cpp | 173 ++++++++++++++++++ lld/ELF/CMakeLists.txt | 1 + lld/ELF/InputFiles.cpp | 2 + lld/ELF/Target.cpp | 2 + lld/ELF/Target.h | 1 + lld/test/ELF/xtensa-reloc.s | 17 ++ lld/test/lit.cfg.py | 1 + .../llvm/BinaryFormat/ELFRelocs/Xtensa.def | 6 + 8 files changed, 203 insertions(+) create mode 100644 lld/ELF/Arch/Xtensa.cpp create mode 100644 lld/test/ELF/xtensa-reloc.s diff --git a/lld/ELF/Arch/Xtensa.cpp b/lld/ELF/Arch/Xtensa.cpp new file mode 100644 index 00000000000000..31603068b8df7a --- /dev/null +++ b/lld/ELF/Arch/Xtensa.cpp @@ -0,0 +1,173 @@ +//===- Xtensa.cpp ---------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "InputFiles.h" +#include "Symbols.h" +#include "Target.h" +#include +#include +#include + +using namespace llvm; +using namespace llvm::object; +using namespace llvm::support::endian; +using namespace llvm::ELF; +using namespace lld; +using namespace lld::elf; + +namespace { + +class Xtensa final : public TargetInfo { +public: + Xtensa(); + RelExpr getRelExpr(RelType type, const Symbol &s, + const uint8_t *loc) const override; + void relocate(uint8_t *loc, const Relocation &rel, + uint64_t val) const override; +}; + +} // namespace + +Xtensa::Xtensa() {} + +RelExpr Xtensa::getRelExpr(RelType type, const Symbol &s, + const uint8_t *loc) const { + switch (type) { + case R_XTENSA_32: + return R_ABS; + case R_XTENSA_SLOT0_OP: + // This relocation is used for various instructions, with varying ways to + // calculate the relocation value. This is unlike most ELF architectures, + // and is arguably bad design (see the comment on R_386_GOT32 in X86.cpp). + // But that's what compilers emit, so it needs to be supported. + // + // We work around this by returning R_PC here and calculating the PC address + // in Xtensa::relocate based on the relative value. That's ugly. A better + // solution would be to look at the instruction here and emit various + // Xtensa-specific RelTypes, but that has another problem: the RelExpr enum + // is at its maximum size of 64. This will need to be fixed eventually, but + // for now hack around it and return R_PC. + return R_PC; + case R_XTENSA_ASM_EXPAND: + // This relocation appears to be emitted by the GNU Xtensa compiler as a + // linker relaxation hint. For example, for the following code: + // + // .section .foo + // .align 4 + // foo: + // nop + // nop + // call0 bar + // .align 4 + // bar: + // + // The call0 instruction is compiled to a l32r and callx0 instruction. + // The LLVM Xtensa backend does not emit this relocation. + // Because it's a relaxation hint, this relocation can be ignored for now + // until linker relaxations are implemented. + return R_NONE; + case R_XTENSA_PDIFF8: + case R_XTENSA_PDIFF16: + case R_XTENSA_PDIFF32: + case R_XTENSA_NDIFF8: + case R_XTENSA_NDIFF16: + case R_XTENSA_NDIFF32: + // > Xtensa relocations to mark the difference of two local symbols. + // > These are only needed to support linker relaxation and can be ignored + // > when not relaxing. + // Source: + // https://github.com/espressif/binutils-gdb/commit/30ce8e47fad9b057b6d7af9e1d43061126d34d20: + // Because we don't do linker relaxation, we can ignore these relocations. + return R_NONE; + default: + error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + + ") against symbol " + toString(s)); + return R_NONE; + } +} + +static inline bool isRRI8Branch(uint8_t *loc) { + if ((loc[0] & 0x0f) == 0b0111) { + // instructions: ball, bany, bbc, bbci, bbs, bbsi, beq, bge, bgeu, blt, + // bltu, bnall, bne, bnone + return true; + } + if ((loc[0] & 0b11'1111) == 0b10'0110) { + // instructions: beqi, bgei, bnei, blti + return true; + } + if ((loc[0] & 0b1011'1111) == 0b1011'0110) { + // instructions: bgeui, bltui + return true; + } + // some other instruction + return false; +} + +void Xtensa::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { + switch (rel.type) { + case R_XTENSA_32: + write32le(loc, val); + break; + case R_XTENSA_SLOT0_OP: { + // HACK: calculate the instruction location based on the PC-relative + // relocation value. + uint64_t dest = rel.sym->getVA(rel.addend); + uint64_t p = dest - val; + + // This relocation is used for various instructions. + // Look at the instruction to determine how to do the relocation. + uint8_t opcode = loc[0] & 0x0f; + if (opcode == 0b0001) { // RI16 format: l32r + uint64_t val = dest - ((p + 3) & (uint64_t)0xfffffffc); + checkInt(loc, static_cast(val) >> 2, 16, rel); + checkAlignment(loc, val, 4, rel); + write16le(loc + 1, static_cast(val) >> 2); + } else if (opcode == 0b0101) { // call0, call4, call8, call12 (CALL format) + uint64_t val = dest - ((p + 4) & (uint64_t)0xfffffffc); + checkInt(loc, static_cast(val) >> 2, 18, rel); + checkAlignment(loc, val, 4, rel); + const int64_t target = static_cast(val) >> 2; + loc[0] = (loc[0] & 0b0011'1111) | ((target & 0b0000'0011) << 6); + loc[1] = target >> 2; + loc[2] = target >> 10; + } else if ((loc[0] & 0x3f) == 0b00'0110) { // j (CALL format) + uint64_t val = dest - p + 4; + checkInt(loc, static_cast(val), 18, rel); + loc[0] = (loc[0] & 0b0011'1111) | ((val & 0b0000'0011) << 6); + loc[1] = val >> 2; + loc[2] = val >> 10; + } else if (isRRI8Branch(loc)) { // RRI8 format (various branch instructions) + uint64_t v = val - 4; + checkInt(loc, static_cast(v), 8, rel); + loc[2] = v & 0xff; + } else if ((loc[0] & 0b1000'1111) == 0b1000'1100) { // RI16 format: beqz.n, bnez.n + uint64_t v = val - 4; + checkUInt(loc, v, 6, rel); + loc[0] = (loc[0] & 0xcf) | (v & 0x30); + loc[1] = (loc[1] & 0x0f) | ((v & 0x0f) << 4); + } else if ((loc[0] & 0b0011'1111) == 0b0001'0110) { // BRI12 format: beqz, bgez, bltz, bnez + uint64_t v = val - 4; + checkInt(loc, static_cast(v), 12, rel); + loc[1] = ((loc[1] & 0x0f)) | ((v & 0x0f) << 4); + loc[2] = (v >> 4) & 0xff; + } else { + error(getErrorLocation(loc) + + "unknown opcode for relocation: " + std::to_string(loc[0])); + } + break; + } + default: + llvm_unreachable("unknown relocation"); + } +} + +TargetInfo *elf::getXtensaTargetInfo() { + static Xtensa target; + return ⌖ +} diff --git a/lld/ELF/CMakeLists.txt b/lld/ELF/CMakeLists.txt index 83d816ddb0601e..5ec4f7e870e352 100644 --- a/lld/ELF/CMakeLists.txt +++ b/lld/ELF/CMakeLists.txt @@ -36,6 +36,7 @@ add_lld_library(lldELF Arch/SystemZ.cpp Arch/X86.cpp Arch/X86_64.cpp + Arch/Xtensa.cpp ARMErrataFix.cpp CallGraphSort.cpp DWARF.cpp diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp index 6c7ef27cbd4942..0efefbd9555583 100644 --- a/lld/ELF/InputFiles.cpp +++ b/lld/ELF/InputFiles.cpp @@ -1620,6 +1620,8 @@ static uint16_t getBitcodeMachineKind(StringRef path, const Triple &t) { return t.isOSIAMCU() ? EM_IAMCU : EM_386; case Triple::x86_64: return EM_X86_64; + case Triple::xtensa: + return EM_XTENSA; default: error(path + ": could not infer e_machine from bitcode target triple " + t.str()); diff --git a/lld/ELF/Target.cpp b/lld/ELF/Target.cpp index b7922425a34e43..333b5b83bb103e 100644 --- a/lld/ELF/Target.cpp +++ b/lld/ELF/Target.cpp @@ -91,6 +91,8 @@ TargetInfo *elf::getTarget() { return getSystemZTargetInfo(); case EM_X86_64: return getX86_64TargetInfo(); + case EM_XTENSA: + return getXtensaTargetInfo(); } llvm_unreachable("unknown target machine"); } diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h index 0cefa318135662..a692db6b9e6266 100644 --- a/lld/ELF/Target.h +++ b/lld/ELF/Target.h @@ -191,6 +191,7 @@ TargetInfo *getSPARCV9TargetInfo(); TargetInfo *getSystemZTargetInfo(); TargetInfo *getX86TargetInfo(); TargetInfo *getX86_64TargetInfo(); +TargetInfo *getXtensaTargetInfo(); template TargetInfo *getMipsTargetInfo(); struct ErrorPlace { diff --git a/lld/test/ELF/xtensa-reloc.s b/lld/test/ELF/xtensa-reloc.s new file mode 100644 index 00000000000000..7007756aa2a891 --- /dev/null +++ b/lld/test/ELF/xtensa-reloc.s @@ -0,0 +1,17 @@ +# REQUIRES: xtensa +# RUN: llvm-mc -filetype=obj -triple=xtensa -mcpu=esp32 %s -o %t.o +# RUN: ld.lld %t.o --defsym=a=0x2000 --section-start=.CALL=0x1000 --defsym=b=40 -o %t +# RUN: llvm-objdump -d --print-imm-hex %t | FileCheck %s + +.section .CALL,"ax",@progbits +# CHECK-LABEL: section .CALL: +# CHECK: call0 . +4096 +# CHECK-NEXT: call0 . +4096 +# CHECK-NEXT: call0 . +4092 +# CHECK-NEXT: call0 . +4088 +# CHECK-NEXT: call0 . -4068 + call0 a + call0 a + call0 a + call0 a + call0 b diff --git a/lld/test/lit.cfg.py b/lld/test/lit.cfg.py index d309c2ad4ee284..6a40667defcac2 100644 --- a/lld/test/lit.cfg.py +++ b/lld/test/lit.cfg.py @@ -86,6 +86,7 @@ "SystemZ": "systemz", "WebAssembly": "wasm", "X86": "x86", + 'Xtensa': 'xtensa', }, ), ("--assertion-mode", {"ON": "asserts"}), diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def index 6791a842181ff4..c2e11259164bb4 100644 --- a/llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def +++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def @@ -58,3 +58,9 @@ ELF_RELOC(R_XTENSA_TLS_TPOFF, 53) ELF_RELOC(R_XTENSA_TLS_FUNC, 54) ELF_RELOC(R_XTENSA_TLS_ARG, 55) ELF_RELOC(R_XTENSA_TLS_CALL, 56) +ELF_RELOC(R_XTENSA_PDIFF8, 57) +ELF_RELOC(R_XTENSA_PDIFF16, 58) +ELF_RELOC(R_XTENSA_PDIFF32, 59) +ELF_RELOC(R_XTENSA_NDIFF8, 60) +ELF_RELOC(R_XTENSA_NDIFF16, 61) +ELF_RELOC(R_XTENSA_NDIFF32, 62) From abe998cf769c264227b85f6a6aeddb60ba7e17a7 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Mon, 1 Apr 2024 15:34:35 +0300 Subject: [PATCH 126/261] [Xtensa][LLD] add more tests --- lld/test/ELF/xtensa-reloc.s | 44 +++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/lld/test/ELF/xtensa-reloc.s b/lld/test/ELF/xtensa-reloc.s index 7007756aa2a891..611e671e7646f3 100644 --- a/lld/test/ELF/xtensa-reloc.s +++ b/lld/test/ELF/xtensa-reloc.s @@ -1,17 +1,57 @@ # REQUIRES: xtensa # RUN: llvm-mc -filetype=obj -triple=xtensa -mcpu=esp32 %s -o %t.o -# RUN: ld.lld %t.o --defsym=a=0x2000 --section-start=.CALL=0x1000 --defsym=b=40 -o %t +# RUN: ld.lld %t.o --defsym=a=0x2000 --section-start=.CALL=0x1000 --defsym=b=0x40 --defsym=c=0x140 --section-start=.BRANCH=0x5000 --defsym=d=0x5010 --section-start=.BR12=0x100 -o %t # RUN: llvm-objdump -d --print-imm-hex %t | FileCheck %s +.section .BR12,"ax",@progbits +# CHECK-LABEL:section .BR12 +# CHECK: beqz a2, . +64 +# CHECK-NEXT: bnez a3, . +61 +# CHECK-NEXT: bgez a4, . +58 +# CHECK-NEXT: bltz a5, . +55 + beqz a2, c + bnez a3, c + bgez a4, c + bltz a5, c + .section .CALL,"ax",@progbits # CHECK-LABEL: section .CALL: # CHECK: call0 . +4096 # CHECK-NEXT: call0 . +4096 # CHECK-NEXT: call0 . +4092 # CHECK-NEXT: call0 . +4088 -# CHECK-NEXT: call0 . -4068 +# CHECK-NEXT: j . +4092 +# CHECK-NEXT: j . +4089 +# CHECK-NEXT: j . +4086 +# CHECK-NEXT: j . -4045 +# CHECK-NEXT: j . -3792 +# CHECK-NEXT: call0 . -4056 +# CHECK-NEXT: call0 . -3804 +# CHECK-NEXT: l32r a3, . -4065 +# CHECK-NEXT: callx0 a3 +# CHECK-NEXT: l32r a4, . -3815 +# CHECK-NEXT: callx0 a4 call0 a call0 a call0 a call0 a + j a + j a + j a + j b + j c call0 b + call0 c + l32r a3, b + callx0 a3 + l32r a4, c + callx0 a4 + +.section .BRANCH,"ax",@progbits +# CHECK-LABEL: section .BRANCH: +# CHECK: beq a3, a4, . +16 +# CHECK-NEXT: ball a3, a4, . +13 +# CHECK-NEXT: blt a3, a4, . +10 + beq a3, a4, d + ball a3, a4, d + blt a3, a4, d From 936880662317d677db3182974f22101dea49433f Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Mon, 1 Apr 2024 16:12:11 +0300 Subject: [PATCH 127/261] [Xtensa][LLD] Fix J formula --- lld/ELF/Arch/Xtensa.cpp | 10 +++++----- lld/test/ELF/xtensa-reloc.s | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/lld/ELF/Arch/Xtensa.cpp b/lld/ELF/Arch/Xtensa.cpp index 31603068b8df7a..f6d75fde7ac29f 100644 --- a/lld/ELF/Arch/Xtensa.cpp +++ b/lld/ELF/Arch/Xtensa.cpp @@ -137,11 +137,11 @@ void Xtensa::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { loc[1] = target >> 2; loc[2] = target >> 10; } else if ((loc[0] & 0x3f) == 0b00'0110) { // j (CALL format) - uint64_t val = dest - p + 4; - checkInt(loc, static_cast(val), 18, rel); - loc[0] = (loc[0] & 0b0011'1111) | ((val & 0b0000'0011) << 6); - loc[1] = val >> 2; - loc[2] = val >> 10; + uint64_t valJ = val - 4; + checkInt(loc, static_cast(valJ), 18, rel); + loc[0] = (loc[0] & 0b0011'1111) | ((valJ & 0b0000'0011) << 6); + loc[1] = valJ >> 2; + loc[2] = valJ >> 10; } else if (isRRI8Branch(loc)) { // RRI8 format (various branch instructions) uint64_t v = val - 4; checkInt(loc, static_cast(v), 8, rel); diff --git a/lld/test/ELF/xtensa-reloc.s b/lld/test/ELF/xtensa-reloc.s index 611e671e7646f3..e14151ae4a8141 100644 --- a/lld/test/ELF/xtensa-reloc.s +++ b/lld/test/ELF/xtensa-reloc.s @@ -20,11 +20,11 @@ # CHECK-NEXT: call0 . +4096 # CHECK-NEXT: call0 . +4092 # CHECK-NEXT: call0 . +4088 -# CHECK-NEXT: j . +4092 -# CHECK-NEXT: j . +4089 -# CHECK-NEXT: j . +4086 -# CHECK-NEXT: j . -4045 -# CHECK-NEXT: j . -3792 +# CHECK-NEXT: j . +4084 +# CHECK-NEXT: j . +4081 +# CHECK-NEXT: j . +4078 +# CHECK-NEXT: j . -4053 +# CHECK-NEXT: j . -3800 # CHECK-NEXT: call0 . -4056 # CHECK-NEXT: call0 . -3804 # CHECK-NEXT: l32r a3, . -4065 From 0b3b4c635458d2a32ff6ec61bd8801523ca6c3ce Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:18 +0300 Subject: [PATCH 128/261] [Xtensa] Add emit constant pool option. --- clang/include/clang/Driver/Options.td | 1 + clang/lib/Driver/ToolChains/Clang.cpp | 5 ++++ llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 32 ++++++++++++++------- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 8 ++++++ llvm/lib/Target/Xtensa/XtensaSubtarget.h | 2 ++ 5 files changed, 38 insertions(+), 10 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 4cf9ad4fd448df..aa8969799a7dc9 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6109,6 +6109,7 @@ def mfix_esp32_psram_cache_strategy_EQ : Joined<["-"], "mfix-esp32-psram-cache-s HelpText<" Psram cache fix strategies : memw, nops">, Values<"memw, nops">; def mlongcalls : Flag<["-"], "mlongcalls">, Group; +def mtext_section_literals : Flag<["-"], "mtext-section-literals">, Group; // These are legacy user-facing driver-level option spellings. They are always // aliases for options that are spelled using the more common Unix / GNU flag diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index e908416fc3bf0f..beead97a8c35da 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2364,6 +2364,11 @@ void Clang::AddXtensaTargetArgs(const ArgList &Args, } } } + + if (Args.getLastArg(options::OPT_mtext_section_literals) != nullptr) { + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back("-mtext-section-literals"); + } } void Clang::DumpCompilationDatabase(Compilation &C, StringRef Filename, diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index bea24bc568bd7c..04c504575250c4 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -14,6 +14,7 @@ //===----------------------------------------------------------------------===// #include "XtensaAsmPrinter.h" +#include "XtensaSubtarget.h" #include "MCTargetDesc/XtensaInstPrinter.h" #include "XtensaConstantPoolValue.h" #include "XtensaMCInstLower.h" @@ -70,6 +71,8 @@ void XtensaAsmPrinter::emitConstantPool() { const Function &F = MF->getFunction(); const MachineConstantPool *MCP = MF->getConstantPool(); const std::vector &CP = MCP->getConstants(); + const XtensaSubtarget *Subtarget = &MF->getSubtarget(); + if (CP.empty()) return; @@ -85,18 +88,23 @@ void XtensaAsmPrinter::emitConstantPool() { MCSectionELF *CS = (MCSectionELF *)getObjFileLowering().SectionForGlobal(&F, TM); std::string CSectionName = CS->getName().str(); - std::size_t Pos = CSectionName.find(".text"); std::string SectionName; - if (Pos != std::string::npos) { - if (Pos > 0) - SectionName = CSectionName.substr(0, Pos + 5); - else - SectionName = ""; - SectionName += ".literal"; - SectionName += CSectionName.substr(Pos + 5); + + if (Subtarget->useTextSectionLiterals()) { + SectionName = CSectionName; } else { - SectionName = CSectionName; - SectionName += ".literal"; + std::size_t Pos = CSectionName.find(".text"); + if (Pos != std::string::npos) { + if (Pos > 0) + SectionName = CSectionName.substr(0, Pos + 5); + else + SectionName = ""; + SectionName += ".literal"; + SectionName += CSectionName.substr(Pos + 5); + } else { + SectionName = CSectionName; + SectionName += ".literal"; + } } MCSectionELF *S = @@ -152,6 +160,8 @@ void XtensaAsmPrinter::emitConstantPool() { OutStreamer->emitRawText(StringRef(str)); } else { + OutStreamer->emitCodeAlignment( + Align(4), OutStreamer->getContext().getSubtargetInfo()); OutStreamer->emitLabel(LblSym); emitGlobalConstant(getDataLayout(), CPE.Val.ConstVal); } @@ -215,6 +225,8 @@ void XtensaAsmPrinter::emitMachineConstantPoolValue( const MCExpr *Expr = MCSymbolRefExpr::create(MCSym, VK, OutContext); uint64_t Size = getDataLayout().getTypeAllocSize(ACPV->getType()); + OutStreamer->emitCodeAlignment( + Align(4), OutStreamer->getContext().getSubtargetInfo()); OutStreamer->emitLabel(LblSym); OutStreamer->emitValue(Expr, Size); } diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index e164da998b5e79..0fd2a258261176 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -24,6 +24,14 @@ using namespace llvm; +static cl::opt TextSectionLiterals("mtext-section-literals", + cl::init(false), cl::Hidden); + +bool XtensaSubtarget::useTextSectionLiterals() const +{ + return TextSectionLiterals; +} + XtensaSubtarget & XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { StringRef CPUName = CPU; diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index b4fac0b65eb194..a6647b52096136 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -205,6 +205,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasESP32S3Ops() const { return HasESP32S3Ops; } + bool useTextSectionLiterals() const; + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; From 40de36c4bdee5c5c4eb8a7b7a500661864868b9a Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:19 +0300 Subject: [PATCH 129/261] [Xtensa] Add support of the mcmodel option. For large mcmodel always emit contsant pool just before code. --- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 0fd2a258261176..311b757d55be12 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -29,6 +29,11 @@ static cl::opt TextSectionLiterals("mtext-section-literals", bool XtensaSubtarget::useTextSectionLiterals() const { + // If code model is large then always place literals in + // test section. + if (TLInfo.getTargetMachine().getCodeModel() == CodeModel::Large) + return true; + return TextSectionLiterals; } From 24d141cd65e0f18e89bebd4f65066823756cf746 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:19 +0300 Subject: [PATCH 130/261] [Xtensa] Fix lowering funnel shift left. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 12 ++++++++---- llvm/test/CodeGen/Xtensa/funnel-shift.ll | 4 +--- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 3ab6687b824c40..3e098458f4ad03 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -1800,12 +1800,16 @@ SDValue XtensaTargetLowering::LowerFunnelShift(SDValue Op, bool IsFSHR = Op.getOpcode() == ISD::FSHR; assert((VT == MVT::i32) && "Unexpected funnel shift type!"); + SDValue SetSAR; + if (!IsFSHR) { - Shamt = DAG.getNode(ISD::SUB, DL, MVT::i32, - DAG.getConstant(32, DL, MVT::i32), Shamt); + SetSAR = DAG.getNode(XtensaISD::SSL, DL, + MVT::Glue, Shamt); + } else { + SetSAR = DAG.getNode(XtensaISD::SSR, DL, + MVT::Glue, Shamt); } - SDValue SetSAR = DAG.getNode(XtensaISD::SSR, DL, - MVT::Glue, Shamt); + return DAG.getNode(XtensaISD::SRC, DL, VT, Op0, Op1, SetSAR); } diff --git a/llvm/test/CodeGen/Xtensa/funnel-shift.ll b/llvm/test/CodeGen/Xtensa/funnel-shift.ll index 09bf081be37379..61eed40e72b9f9 100644 --- a/llvm/test/CodeGen/Xtensa/funnel-shift.ll +++ b/llvm/test/CodeGen/Xtensa/funnel-shift.ll @@ -11,9 +11,7 @@ entry: define dso_local i32 @test_fshl(i32 %value1, i32 %value2, i32 %shift) nounwind { ; CHECK-LABEL: @test_fshl -; CHECK: movi.n a8, 32 -; CHECK: sub a8, a8, a4 -; CHECK: ssr a8 +; CHECK: ssl a4 ; CHECK: src a2, a2, a3 entry: %0 = tail call i32 @llvm.fshl.i32(i32 %value1, i32 %value2, i32 %shift) From f018c40df45595361d49de1ea3f0a10ebb0a5d7e Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:20 +0300 Subject: [PATCH 131/261] [Xtensa] Make it possible to use -fuse-ld when GCC toolchain is detected --- clang/lib/Driver/ToolChains/Xtensa.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index a1c45ecf5947d4..36c10ea08a0261 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -266,12 +266,18 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (!D.SysRoot.empty()) CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot)); + bool LinkerIsLLD; + std::string LinkerPath = ToolChain.GetLinkerPath(&LinkerIsLLD); if (ToolChain.GCCToolchainName != "") { - Linker.assign(ToolChain.GCCToolchainDir); - llvm::sys::path::append(Linker, "bin", - ToolChain.GCCToolchainName + "-" + getShortName()); + if (!LinkerIsLLD) { + Linker.assign(ToolChain.GCCToolchainDir); + llvm::sys::path::append( + Linker, "bin", ToolChain.GCCToolchainName + "-" + getShortName()); + } else { + Linker.assign(LinkerPath); + } } else { - Linker.assign(ToolChain.GetLinkerPath()); + Linker.assign(LinkerPath); } const char *crtbegin, *crtend; From a24105c79c60f4aaee921bdd588c46221597de41 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:20 +0300 Subject: [PATCH 132/261] esp/ci: Fixes Windows release archives --- .gitlab-ci.yml | 19 ++++++------------- .legacy-release.yml | 4 ++-- .universal-toolchain-release.yml | 24 ++++++++---------------- 3 files changed, 16 insertions(+), 31 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e152a1c90a6e9e..dbe33f2bd2c313 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -15,14 +15,11 @@ variables: CLANG_VER: "15.0.0" GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" - NEWLIB_REPO: "newlib-cygwin" NEWLIB_REF: "esp-2022r1" - BINUTILS_REPO: "binutils-gdb" BINUTILS_REF: "esp-2022r1-binutils" - XTENSA_OVERLAYS_REPO: "xtensa-overlays" XTENSA_OVERLAYS_REF: "master" - LLVM_GCC_TESTSUITE_REF: "release_universal_clang_toolchain" - XTENSA_CLANG_TOOLCHAIN_REF: "release_universal_clang_toolchain" + LLVM_GCC_TESTSUITE_REF: "esp-15.0.0-20221201" + XTENSA_CLANG_TOOLCHAIN_REF: "esp-15.0.0-20221201" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 PLATFORM_NAME_LINUX: "linux-amd64" @@ -39,10 +36,10 @@ variables: ARCHIVE_TOOL_WIN: "zip -9 -r" UNARCHIVE_TOOL_WIN: "unzip" ARCHIVE_EXT_WIN: "zip" - # Use Linux xz compressor to minimize Windows build artifact size. - # Upon release archive will be re-packed into zip format for uploading to GH. - ARCHIVE_TOOL_WIN_INT: ${ARCHIVE_TOOL_LINUX} - UNARCHIVE_TOOL_WIN_INT: ${UNARCHIVE_TOOL_LINUX} + + PACK_ARCHIVE_TOOL_WIN: "tar -h -cJf" + PACK_UNARCHIVE_TOOL_WIN: "${UNARCHIVE_TOOL_LINUX}" + PACK_ARCHIVE_EXT_WIN: "${ARCHIVE_EXT_LINUX}" ARCHIVE_TOOL_MACOS: "tar -cJf" UNARCHIVE_TOOL_MACOS: "tar -xf" @@ -52,10 +49,6 @@ variables: UNARCHIVE_TOOL_NEWLIB: ${UNARCHIVE_TOOL_LINUX} ARCHIVE_EXT_NEWLIB: ${ARCHIVE_EXT_LINUX} - LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - DIST_DIR: "dist" BUILD_DIR: "build" DOWNLOADS_DIR: "downloads" diff --git a/.legacy-release.yml b/.legacy-release.yml index c46195f3fe4751..2042369e9049d7 100644 --- a/.legacy-release.yml +++ b/.legacy-release.yml @@ -104,11 +104,11 @@ linux_amd64_testsuite: - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} # getting testsuite - - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git + - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/${LLVM_TESTSUITE_REPO}.git # preparing testsuite - export PATH=${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/:$PATH - - cd llvm-xtensa-testsuite + - cd ${LLVM_TESTSUITE_REPO} # qemu - ./qemu_esp32_install.sh diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 5292918a32a97f..27eebaf98e6c7c 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -5,7 +5,7 @@ REL_NUM=$(git describe --abbrev=7) REL_NAME=${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} - LIBS_ARCHIVE_NAME=libs_${REL_NAME}.${LIBS_ARCHIVE_EXT} + LIBS_ARCHIVE_NAME=libs_${REL_NAME}.${ARCHIVE_EXT} echo "PLATFORM_NAME: $PLATFORM_NAME" echo "REL_NUM: $REL_NUM" echo "REL_NAME: $REL_NAME" @@ -35,7 +35,7 @@ # Pack libs to be used for Rust, Go etc. .package_libs: &package_libs | - ${LIBS_ARCHIVE_TOOL} ${LIBS_ARCHIVE_NAME} esp-clang/lib/libclang* esp-clang/lib/clang/${CLANG_VER}/include + eval ${ARCHIVE_TOOL} ${LIBS_ARCHIVE_NAME} esp-clang/lib/clang/${CLANG_VER}/include esp-clang/lib/lib{clang,LLVM}* ${LIBS_PACK_EXTRA_PATHS:-} mkdir -p ${DISTRO_DIR} mv ${LIBS_ARCHIVE_NAME} ${DISTRO_DIR}/ echo "${LIBS_ARCHIVE_NAME}" > ${DISTRO_DIR}/file_libs-${PLATFORM_NAME} @@ -254,9 +254,6 @@ build_newlib: ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" pack_x86_64-linux-gnu: extends: .pack_linux-gnu_template @@ -295,12 +292,10 @@ pack_x86_64-w64-mingw32: variables: CONF_HOST: "x86_64-w64-mingw32" PLATFORM_NAME: "${PLATFORM_NAME_WIN}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" - LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" - LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" + ARCHIVE_TOOL: "${PACK_ARCHIVE_TOOL_WIN}" + UNARCHIVE_TOOL: "${PACK_UNARCHIVE_TOOL_WIN}" + ARCHIVE_EXT: "${PACK_ARCHIVE_EXT_WIN}" + LIBS_PACK_EXTRA_PATHS: esp-clang/bin/lib{c++,clang,LLVM,unwind}* .pack_apple-darwin_template: extends: .pack_template @@ -308,9 +303,6 @@ pack_x86_64-w64-mingw32: ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" - LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" - LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" - LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" pack_x86_64-apple-darwin: extends: .pack_apple-darwin_template @@ -344,10 +336,10 @@ test_x86_64-linux-gnu: - *get_release_name - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} # getting testsuite - - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/llvm-xtensa-testsuite.git + - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/${LLVM_TESTSUITE_REPO}.git # preparing testsuite - export PATH=${PWD}/esp-clang/bin:$PATH - - cd llvm-xtensa-testsuite + - cd ${LLVM_TESTSUITE_REPO} # qemu - ./qemu_esp32_install.sh # run testsuite for esp32 From ed1b6c4551a766f0553af837dbec8b7d9cefe7d6 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:21 +0300 Subject: [PATCH 133/261] esp/ci: Check for OOM failures after build --- .universal-toolchain-release.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 27eebaf98e6c7c..75a41258aead04 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -65,6 +65,14 @@ expire_in: 1 day variables: BUILD_TOOLCHAIN_CMD_EXTRA_ARGS: "" + after_script: + # help to identify that build failed due to OOM + - > + if [ $CI_JOB_STATUS == 'failed' ]; then + [ ! -f "${BUILD_DIR}/build.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/build.log || true + [ ! -f "${BUILD_DIR}/tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/tests.log || true + [ ! -f "${BUILD_DIR}/lld-tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/lld-tests.log || true + fi script: - *get_release_name - mkdir ${DOWNLOADS_DIR} From 3a1fb0daa9baa9d6945f0c54dcffd4777c79563f Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:21 +0300 Subject: [PATCH 134/261] [PATCH 134/230] [LLD][Xtensa] Cover DIFF{8, 16, 32} relocations. --- lld/ELF/Arch/Xtensa.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lld/ELF/Arch/Xtensa.cpp b/lld/ELF/Arch/Xtensa.cpp index f6d75fde7ac29f..10d6c3b52d1dc3 100644 --- a/lld/ELF/Arch/Xtensa.cpp +++ b/lld/ELF/Arch/Xtensa.cpp @@ -71,6 +71,9 @@ RelExpr Xtensa::getRelExpr(RelType type, const Symbol &s, // Because it's a relaxation hint, this relocation can be ignored for now // until linker relaxations are implemented. return R_NONE; + case R_XTENSA_DIFF8: + case R_XTENSA_DIFF16: + case R_XTENSA_DIFF32: case R_XTENSA_PDIFF8: case R_XTENSA_PDIFF16: case R_XTENSA_PDIFF32: From 40e2ac114a402d62910447700d04dbd3961b029f Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Sep 2023 02:07:40 +0300 Subject: [PATCH 135/261] [Xtensa] Implement constant islands pass The constant islands pass is always executed for large code model. Also currently is disabled support of the hardware loops for large code model, need to add support for hwloops in constant islands pass in future. --- llvm/lib/Target/Xtensa/CMakeLists.txt | 1 + llvm/lib/Target/Xtensa/Xtensa.h | 1 + llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 169 +- llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 5 + .../Target/Xtensa/XtensaConstantIsland.cpp | 1468 +++++++++++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 20 + .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 1 + .../Xtensa/XtensaTargetTransformInfo.cpp | 6 + 8 files changed, 1604 insertions(+), 67 deletions(-) create mode 100644 llvm/lib/Target/Xtensa/XtensaConstantIsland.cpp diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index fccdde013bbc97..873de70425a731 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -17,6 +17,7 @@ add_public_tablegen_target(XtensaCommonTableGen) add_llvm_target(XtensaCodeGen XtensaAsmPrinter.cpp XtensaConstantPoolValue.cpp + XtensaConstantIsland.cpp XtensaESP32PSRAMFix.cpp XtensaFixupHWLoops.cpp XtensaFrameLowering.cpp diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h index 07b9cb23a5e48d..5a1560db519d94 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.h +++ b/llvm/lib/Target/Xtensa/Xtensa.h @@ -30,5 +30,6 @@ FunctionPass *createXtensaSizeReductionPass(); FunctionPass *createXtensaHardwareLoops(); FunctionPass *createXtensaFixupHwLoops(); FunctionPass *createXtensaPSRAMCacheFixPass(); +FunctionPass *createXtensaConstantIslandPass(); } // namespace llvm #endif /* LLVM_LIB_TARGET_XTENSA_XTENSA_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index 04c504575250c4..9ade39dee58475 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -14,10 +14,10 @@ //===----------------------------------------------------------------------===// #include "XtensaAsmPrinter.h" -#include "XtensaSubtarget.h" #include "MCTargetDesc/XtensaInstPrinter.h" #include "XtensaConstantPoolValue.h" #include "XtensaMCInstLower.h" +#include "XtensaSubtarget.h" #include "TargetInfo/XtensaTargetInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/BinaryFormat/ELF.h" @@ -48,6 +48,38 @@ void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) { XtensaMCInstLower Lower(MF->getContext(), *this); MCInst LoweredMI; unsigned Opc = MI->getOpcode(); + const MachineConstantPool *MCP = MF->getConstantPool(); + + // If we just ended a constant pool, mark it as such. + if (InConstantPool && Opc != Xtensa::CONSTPOOL_ENTRY) { + OutStreamer->emitDataRegion(MCDR_DataRegionEnd); + InConstantPool = false; + } + + if (Opc == Xtensa::CONSTPOOL_ENTRY) { + // CONSTPOOL_ENTRY - This instruction represents a floating + // constant pool in the function. The first operand is the ID# + // for this instruction, the second is the index into the + // MachineConstantPool that this is, the third is the size in + // bytes of this constant pool entry. + // The required alignment is specified on the basic block holding this MI. + // + unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); + unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); + + // If this is the first entry of the pool, mark it. + if (!InConstantPool) { + if (OutStreamer->hasRawTextSupport()) { + OutStreamer->emitRawText(StringRef("\t.literal_position\n")); + } + OutStreamer->emitDataRegion(MCDR_DataRegion); + InConstantPool = true; + } + const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; + + emitMachineConstantPoolEntry(MCPE, LabelId); + return; + } switch (Opc) { case Xtensa::BR_JT: { @@ -63,6 +95,61 @@ void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) { EmitToStreamer(*OutStreamer, LoweredMI); } +void XtensaAsmPrinter::emitMachineConstantPoolEntry( + const MachineConstantPoolEntry &CPE, int i) { + if (CPE.isMachineConstantPoolEntry()) { + XtensaConstantPoolValue *ACPV = + static_cast(CPE.Val.MachineCPVal); + ACPV->setLabelId(i); + emitMachineConstantPoolValue(CPE.Val.MachineCPVal); + } else { + MCSymbol *LblSym = GetCPISymbol(i); + // TODO find a better way to check whether we emit data to .s file + if (OutStreamer->hasRawTextSupport()) { + std::string str("\t.literal "); + str += LblSym->getName(); + str += ", "; + const Constant *C = CPE.Val.ConstVal; + + Type *Ty = C->getType(); + if (const auto *CFP = dyn_cast(C)) { + str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true); + } else if (const auto *CI = dyn_cast(C)) { + str += toString(CI->getValue(), 10, true); + } else if (isa(Ty)) { + const MCExpr *ME = lowerConstant(C); + const MCSymbolRefExpr &SRE = cast(*ME); + const MCSymbol &Sym = SRE.getSymbol(); + str += Sym.getName(); + } else { + unsigned NumElements; + if (isa(Ty)) + NumElements = (cast(Ty))->getNumElements(); + else + NumElements = Ty->getArrayNumElements(); + + for (unsigned I = 0; I < NumElements; I++) { + const Constant *CAE = C->getAggregateElement(I); + if (I > 0) + str += ", "; + if (const auto *CFP = dyn_cast(CAE)) { + str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true); + } else if (const auto *CI = dyn_cast(CAE)) { + str += toString(CI->getValue(), 10, true); + } + } + } + + OutStreamer->emitRawText(StringRef(str)); + } else { + OutStreamer->emitCodeAlignment( + Align(4), OutStreamer->getContext().getSubtargetInfo()); + OutStreamer->emitLabel(LblSym); + emitGlobalConstant(getDataLayout(), CPE.Val.ConstVal); + } + } +} + /// EmitConstantPool - Print to the current output stream assembly /// representations of the constants in the constant pool MCP. This is /// used to print out constants which have been "spilled to memory" by @@ -73,6 +160,9 @@ void XtensaAsmPrinter::emitConstantPool() { const std::vector &CP = MCP->getConstants(); const XtensaSubtarget *Subtarget = &MF->getSubtarget(); + if (Subtarget->useTextSectionLiterals()) + return; + if (CP.empty()) return; @@ -89,22 +179,17 @@ void XtensaAsmPrinter::emitConstantPool() { (MCSectionELF *)getObjFileLowering().SectionForGlobal(&F, TM); std::string CSectionName = CS->getName().str(); std::string SectionName; - - if (Subtarget->useTextSectionLiterals()) { - SectionName = CSectionName; + std::size_t Pos = CSectionName.find(".text"); + if (Pos != std::string::npos) { + if (Pos > 0) + SectionName = CSectionName.substr(0, Pos + 5); + else + SectionName = ""; + SectionName += ".literal"; + SectionName += CSectionName.substr(Pos + 5); } else { - std::size_t Pos = CSectionName.find(".text"); - if (Pos != std::string::npos) { - if (Pos > 0) - SectionName = CSectionName.substr(0, Pos + 5); - else - SectionName = ""; - SectionName += ".literal"; - SectionName += CSectionName.substr(Pos + 5); - } else { - SectionName = CSectionName; - SectionName += ".literal"; - } + SectionName = CSectionName; + SectionName += ".literal"; } MCSectionELF *S = @@ -115,57 +200,7 @@ void XtensaAsmPrinter::emitConstantPool() { } } - if (CPE.isMachineConstantPoolEntry()) { - XtensaConstantPoolValue *ACPV = - static_cast(CPE.Val.MachineCPVal); - ACPV->setLabelId(i); - emitMachineConstantPoolValue(CPE.Val.MachineCPVal); - } else { - MCSymbol *LblSym = GetCPISymbol(i); - // TODO find a better way to check whether we emit data to .s file - if (OutStreamer->hasRawTextSupport()) { - std::string str("\t.literal "); - str += LblSym->getName(); - str += ", "; - const Constant *C = CPE.Val.ConstVal; - - Type *Ty = C->getType(); - if (const auto *CFP = dyn_cast(C)) { - str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true); - } else if (const auto *CI = dyn_cast(C)) { - str += toString(CI->getValue(), 10, true); - } else if (isa(Ty)) { - const MCExpr *ME = lowerConstant(C); - const MCSymbolRefExpr &SRE = cast(*ME); - const MCSymbol &Sym = SRE.getSymbol(); - str += Sym.getName(); - } else { - unsigned NumElements; - if (isa(Ty)) - NumElements = (cast(Ty))->getNumElements(); - else - NumElements = Ty->getArrayNumElements(); - - for (unsigned I = 0; I < NumElements; I++) { - const Constant *CAE = C->getAggregateElement(I); - if (I > 0) - str += ", "; - if (const auto *CFP = dyn_cast(CAE)) { - str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true); - } else if (const auto *CI = dyn_cast(CAE)) { - str += toString(CI->getValue(), 10, true); - } - } - } - - OutStreamer->emitRawText(StringRef(str)); - } else { - OutStreamer->emitCodeAlignment( - Align(4), OutStreamer->getContext().getSubtargetInfo()); - OutStreamer->emitLabel(LblSym); - emitGlobalConstant(getDataLayout(), CPE.Val.ConstVal); - } - } + emitMachineConstantPoolEntry(CPE, i); } } diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h index e17059a2d4c3bf..dbf092f6712372 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h @@ -17,6 +17,7 @@ #include "XtensaTargetMachine.h" #include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/Support/Compiler.h" namespace llvm { @@ -28,6 +29,9 @@ class raw_ostream; class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter { const MCSubtargetInfo *STI; + /// InConstantPool - Maintain state when emitting a sequence of constant + /// pool entries so we can properly mark them as data regions. + bool InConstantPool = false; public: explicit XtensaAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer) @@ -37,6 +41,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter { StringRef getPassName() const override { return "Xtensa Assembly Printer"; } void emitInstruction(const MachineInstr *MI) override; void emitConstantPool() override; + void emitMachineConstantPoolEntry(const MachineConstantPoolEntry &CPE, int i); void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, diff --git a/llvm/lib/Target/Xtensa/XtensaConstantIsland.cpp b/llvm/lib/Target/Xtensa/XtensaConstantIsland.cpp new file mode 100644 index 00000000000000..f0db5bbe065eae --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaConstantIsland.cpp @@ -0,0 +1,1468 @@ +//===- XtensaConstantIslandPass.cpp - Emit Pc Relative loads +//----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This pass is used to make Pc relative loads of constants. +// +// Loading constants inline is expensive on Xtensa and it's in general better +// to place the constant nearby in code space and then it can be loaded with a +// simple l32r instruction. +// +// The constants can be not just numbers but addresses of functions and labels. +// This can be particularly helpful in static relocation mode for embedded +// non-linux targets. +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "XtensaConstantPoolValue.h" +#include "XtensaMachineFunctionInfo.h" +#include "XtensaSubtarget.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/LivePhysRegs.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/Config/llvm-config.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/DebugLoc.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Type.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include +#include +#include + +using namespace llvm; + +#define DEBUG_TYPE "xtensa-constant-islands" + +STATISTIC(NumCPEs, "Number of constpool entries"); +STATISTIC(NumSplit, "Number of uncond branches inserted"); +STATISTIC(NumCBrFixed, "Number of cond branches fixed"); +STATISTIC(NumUBrFixed, "Number of uncond branches fixed"); + +// FIXME: This option should be removed once it has received sufficient testing. +static cl::opt + AlignConstantIslands("xtensa-align-constant-islands", cl::Hidden, + cl::init(true), + cl::desc("Align constant islands in code")); + +// Rather than do make check tests with huge amounts of code, we force +// the test to use this amount. +static cl::opt ConstantIslandsSmallOffset( + "xtensa-constant-islands-small-offset", cl::init(0), + cl::desc("Make small offsets be this amount for testing purposes"), + cl::Hidden); + +// TODO +// This defines for L32R and J instruction displacemnt for +// testing purposes only +#define MAX_DISP_L32R 262144 +#define BITS_JUMP 18 + +static unsigned int branchTargetOperand(MachineInstr *MI) { + switch (MI->getOpcode()) { + case Xtensa::J: + return 0; + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + return 2; + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + return 1; + case Xtensa::BT: + case Xtensa::BF: + return 1; + } + llvm_unreachable("Unknown branch type"); +} + +namespace { + +using Iter = MachineBasicBlock::iterator; +using ReverseIter = MachineBasicBlock::reverse_iterator; + +/// XtensaConstantIslands - Due to limited PC-relative displacements, Xtensa +/// requires constant pool entries to be scattered among the instructions +/// inside a function. To do this, it completely ignores the normal LLVM +/// constant pool; instead, it places constants wherever it feels like with +/// special instructions. +/// +/// The terminology used in this pass includes: +/// Islands - Clumps of constants placed in the function. +/// Water - Potential places where an island could be formed. +/// CPE - A constant pool entry that has been placed somewhere, which +/// tracks a list of users. + +class XtensaConstantIslands : public MachineFunctionPass { + /// BasicBlockInfo - Information about the offset and size of a single + /// basic block. + struct BasicBlockInfo { + /// Offset - Distance from the beginning of the function to the beginning + /// of this basic block. + /// + /// Offsets are computed assuming worst case padding before an aligned + /// block. This means that subtracting basic block offsets always gives a + /// conservative estimate of the real distance which may be smaller. + /// + /// Because worst case padding is used, the computed offset of an aligned + /// block may not actually be aligned. + unsigned Offset = 0; + + /// Size - Size of the basic block in bytes. If the block contains + /// inline assembly, this is a worst case estimate. + /// + /// The size does not include any alignment padding whether from the + /// beginning of the block, or from an aligned jump table at the end. + unsigned Size = 0; + + BasicBlockInfo() = default; + + unsigned postOffset() const { return Offset + Size; } + }; + + std::vector BBInfo; + + /// WaterList - A sorted list of basic blocks where islands could be placed + /// (i.e. blocks that don't fall through to the following block, due + /// to a return, unreachable, or unconditional branch). + std::vector WaterList; + + /// NewWaterList - The subset of WaterList that was created since the + /// previous iteration by inserting unconditional branches. + SmallSet NewWaterList; + + using water_iterator = std::vector::iterator; + + /// CPUser - One user of a constant pool, keeping the machine instruction + /// pointer, the constant pool being referenced, and the max displacement + /// allowed from the instruction to the CP. The LowWaterMark records the + /// lowest basic block where a new CPEntry can be placed. To ensure this + /// pass terminates, the CP entries are initially placed at the second block + /// of the function and then move monotonically to higher addresses. The + /// exception to this rule is when the current CP entry for a particular + /// CPUser is out of range, but there is another CP entry for the same + /// constant value in range. We want to use the existing in-range CP + /// entry, but if it later moves out of range, the search for new water + /// should resume where it left off. The LowWaterMark is used to record + /// that point. + struct CPUser { + MachineInstr *MI; + MachineInstr *CPEMI; + MachineBasicBlock *LowWaterMark; + + private: + unsigned MaxDisp; + + public: + CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp) + : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp) { + LowWaterMark = CPEMI->getParent(); + } + + /// getMaxDisp - Returns the maximum displacement supported by MI. + unsigned getMaxDisp() const { + unsigned xMaxDisp = + ConstantIslandsSmallOffset ? ConstantIslandsSmallOffset : MaxDisp; + return xMaxDisp; + } + + void setMaxDisp(unsigned val) { MaxDisp = val; } + }; + + /// CPUsers - Keep track of all of the machine instructions that use various + /// constant pools and their max displacement. + std::vector CPUsers; + + /// CPEntry - One per constant pool entry, keeping the machine instruction + /// pointer, the constpool index, and the number of CPUser's which + /// reference this entry. + struct CPEntry { + MachineInstr *CPEMI; + unsigned CPI; + unsigned RefCount; + + CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0) + : CPEMI(cpemi), CPI(cpi), RefCount(rc) {} + }; + + /// CPEntries - Keep track of all of the constant pool entry machine + /// instructions. For each original constpool index (i.e. those that + /// existed upon entry to this pass), it keeps a vector of entries. + /// Original elements are cloned as we go along; the clones are + /// put in the vector of the original element, but have distinct CPIs. + std::vector> CPEntries; + + /// ImmBranch - One per immediate branch, keeping the machine instruction + /// pointer, conditional or unconditional, the max displacement, + /// and (if isCond is true) the corresponding unconditional branch + /// opcode. + struct ImmBranch { + MachineInstr *MI; + unsigned MaxDisp : 31; + bool isCond : 1; + int UncondBr; + + ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, int ubr) + : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {} + }; + + /// ImmBranches - Keep track of all the immediate branch instructions. + /// + std::vector ImmBranches; + + const XtensaSubtarget *STI = nullptr; + const XtensaInstrInfo *TII; + const TargetRegisterInfo *TRI; + XtensaFunctionInfo *MFI; + MachineFunction *MF = nullptr; + MachineConstantPool *MCP = nullptr; + MachineBasicBlock *InitConstantMBB = nullptr; + std::unique_ptr RS; + LivePhysRegs LiveRegs; + + unsigned PICLabelUId; + bool PrescannedForConstants = false; + + void initPICLabelUId(unsigned UId) { PICLabelUId = UId; } + + unsigned createPICLabelUId() { return PICLabelUId++; } + +public: + static char ID; + + XtensaConstantIslands() : MachineFunctionPass(ID) {} + + StringRef getPassName() const override { return "Xtensa Constant Islands"; } + + bool runOnMachineFunction(MachineFunction &F) override; + + MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set( + MachineFunctionProperties::Property::NoVRegs); + } + + void doInitialPlacement(std::vector &CPEMIs); + CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI); + Align getCPEAlign(const MachineInstr &CPEMI); + void initializeFunctionInfo(const std::vector &CPEMIs); + unsigned getOffsetOf(MachineInstr *MI) const; + unsigned getUserOffset(CPUser &) const; + void dumpBBs(); + + bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset, + unsigned Disp); + + void computeBlockSize(MachineBasicBlock *MBB); + MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI); + void updateForInsertedWaterBlock(MachineBasicBlock *NewBB); + void adjustBBOffsetsAfter(MachineBasicBlock *BB); + bool decrementCPEReferenceCount(unsigned CPI, MachineInstr *CPEMI); + int findInRangeCPEntry(CPUser &U, unsigned UserOffset); + bool findAvailableWater(CPUser &U, unsigned UserOffset, + water_iterator &WaterIter); + void createNewWater(unsigned CPUserIndex, unsigned UserOffset, + MachineBasicBlock *&NewMBB); + bool handleConstantPoolUser(unsigned CPUserIndex); + void removeDeadCPEMI(MachineInstr *CPEMI); + bool removeUnusedCPEntries(); + bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, + MachineInstr *CPEMI, unsigned Disp, + bool DoDump = false); + bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water, CPUser &U, + unsigned &Growth); + bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp); + bool fixupImmediateBr(ImmBranch &Br); + bool fixupConditionalBr(ImmBranch &Br); + bool fixupUnconditionalBr(ImmBranch &Br); + void removeEntryJump(); +}; + +} // end anonymous namespace + +char XtensaConstantIslands::ID = 0; + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +/// print block size and offset information - debugging +LLVM_DUMP_METHOD void XtensaConstantIslands::dumpBBs() { + for (unsigned J = 0, E = BBInfo.size(); J != E; ++J) { + const BasicBlockInfo &BBI = BBInfo[J]; + dbgs() << format("%08x %bb.%u\t", BBI.Offset, J) + << format(" size=%#x\n", BBInfo[J].Size); + } +} +#endif + +bool XtensaConstantIslands::runOnMachineFunction(MachineFunction &mf) { + MF = &mf; + MCP = mf.getConstantPool(); + STI = &mf.getSubtarget(); + LLVM_DEBUG(dbgs() << "constant island machine function " + << "\n"); + TII = (const XtensaInstrInfo *)STI->getInstrInfo(); + MFI = MF->getInfo(); + + TRI = STI->getRegisterInfo(); + + if (!STI->useTextSectionLiterals()) + return false; + + if (TRI->trackLivenessAfterRegAlloc(*MF)) + RS.reset(new RegScavenger()); + + LLVM_DEBUG(dbgs() << "constant island processing " + << "\n"); + + // Renumber all of the machine basic blocks in the function, guaranteeing that + // the numbers agree with the position of the block in the function. + MF->RenumberBlocks(); + + bool MadeChange = false; + + // Perform the initial placement of the constant pool entries. To start with, + // we put them all at the end of the function. + std::vector CPEMIs; + doInitialPlacement(CPEMIs); + + // Renumber all of the machine basic blocks in the function, guaranteeing + // that the numbers agree with the position of the block in the function. + MF->RenumberBlocks(); + + /// The next UID to take is the first unused one. + initPICLabelUId(CPEMIs.size()); + + // Do the initial scan of the function, building up information about the + // sizes of each block, the location of all the water, and finding all of the + // constant pool users. + initializeFunctionInfo(CPEMIs); + CPEMIs.clear(); + LLVM_DEBUG(dumpBBs()); + + /// Remove dead constant pool entries. + MadeChange |= removeUnusedCPEntries(); + + // Iteratively place constant pool entries and fix up branches until there + // is no change. + unsigned NoCPIters = 0, NoBRIters = 0; + (void)NoBRIters; + while (true) { + LLVM_DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n'); + bool CPChange = false; + for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { + CPChange |= handleConstantPoolUser(i); + } + if (CPChange && ++NoCPIters > 30) + report_fatal_error("Constant Island pass failed to converge!"); + LLVM_DEBUG(dumpBBs()); + + // Clear NewWaterList now. If we split a block for branches, it should + // appear as "new water" for the next iteration of constant pool placement. + NewWaterList.clear(); + + LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n'); + bool BRChange = false; + for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) + BRChange |= fixupImmediateBr(ImmBranches[i]); + if (BRChange && ++NoBRIters > 30) + report_fatal_error("Branch Fix Up pass failed to converge!"); + LLVM_DEBUG(dumpBBs()); + + if (!CPChange && !BRChange) + break; + + MadeChange = true; + } + removeEntryJump(); + LLVM_DEBUG(dbgs() << '\n'; dumpBBs()); + BBInfo.clear(); + WaterList.clear(); + CPUsers.clear(); + CPEntries.clear(); + ImmBranches.clear(); + return MadeChange; +} + +/// BBHasFallthrough - Return true if the specified basic block can fallthrough +/// into the block immediately after it. +static bool BBHasFallthrough(MachineBasicBlock *MBB) { + // Get the next machine basic block in the function. + MachineFunction::iterator MBBI = MBB->getIterator(); + // Can't fall off end of function. + if (std::next(MBBI) == MBB->getParent()->end()) + return false; + + MachineBasicBlock *NextBB = &*std::next(MBBI); + return llvm::is_contained(MBB->successors(), NextBB); +} + +/// doInitialPlacement - Perform the initial placement of the constant pool +/// entries. To start with, we put them all at the end of the function. +void XtensaConstantIslands::doInitialPlacement( + std::vector &CPEMIs) { + // Create the basic block to hold the CPE's. + MachineBasicBlock *BB = MF->CreateMachineBasicBlock(); + + // TODO + MachineBasicBlock *Entry = &MF->front(); + MachineBasicBlock *NewEntry = MF->CreateMachineBasicBlock(); + + MF->insert(Entry->getIterator(), NewEntry); + BuildMI(NewEntry, DebugLoc(), TII->get(Xtensa::J)).addMBB(Entry); + NewEntry->addSuccessor(Entry); + NewEntry->setAlignment(Entry->getAlignment()); + + // Copy live-in information to new block. + for (const MachineBasicBlock::RegisterMaskPair &RegMaskPair : + Entry->liveins()) + NewEntry->addLiveIn(RegMaskPair); + + // MachineConstantPool measures alignment in bytes. We measure in log2(bytes). + const Align MaxAlign = MCP->getConstantPoolAlign(); + + BB->setAlignment(AlignConstantIslands ? MaxAlign : Align(4)); + + MF->insert(Entry->getIterator(), BB); + + // The function needs to be as aligned as the basic blocks. The linker may + // move functions around based on their alignment. + MF->ensureAlignment(BB->getAlignment()); + + // Order the entries in BB by descending alignment. That ensures correct + // alignment of all entries as long as BB is sufficiently aligned. Keep + // track of the insertion point for each alignment. We are going to bucket + // sort the entries as they are created. + SmallVector InsPoint(Log2(MaxAlign) + 1, + BB->end()); + + // Add all of the constants from the constant pool to the end block, use an + // identity mapping of CPI's to CPE's. + const std::vector &CPs = MCP->getConstants(); + + const DataLayout &TD = MF->getDataLayout(); + for (unsigned i = 0, e = CPs.size(); i != e; ++i) { + unsigned Size = CPs[i].getSizeInBytes(TD); + assert(Size >= 4 && "Too small constant pool entry"); + Align Alignment = CPs[i].getAlign(); + // Verify that all constant pool entries are a multiple of their alignment. + // If not, we would have to pad them out so that instructions stay aligned. + assert(isAligned(Alignment, Size) && "CP Entry not multiple of 4 bytes!"); + + // Insert CONSTPOOL_ENTRY before entries with a smaller alignment. + unsigned LogAlign = Log2(Alignment); + MachineBasicBlock::iterator InsAt = InsPoint[LogAlign]; + + MachineInstr *CPEMI = + BuildMI(*BB, InsAt, DebugLoc(), TII->get(Xtensa::CONSTPOOL_ENTRY)) + .addImm(i) + .addConstantPoolIndex(i) + .addImm(Size); + + CPEMIs.push_back(CPEMI); + + // Ensure that future entries with higher alignment get inserted before + // CPEMI. This is bucket sort with iterators. + for (unsigned a = LogAlign + 1; a <= Log2(MaxAlign); ++a) + if (InsPoint[a] == InsAt) + InsPoint[a] = CPEMI; + // Add a new CPEntry, but no corresponding CPUser yet. + CPEntries.emplace_back(1, CPEntry(CPEMI, i)); + ++NumCPEs; + LLVM_DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = " + << Size << ", align = " << Alignment.value() << '\n'); + } + InitConstantMBB = BB; + LLVM_DEBUG(BB->dump()); +} + +/// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI, +/// look up the corresponding CPEntry. +XtensaConstantIslands::CPEntry * +XtensaConstantIslands::findConstPoolEntry(unsigned CPI, + const MachineInstr *CPEMI) { + std::vector &CPEs = CPEntries[CPI]; + // Number of entries per constpool index should be small, just do a + // linear search. + for (CPEntry &CPE : CPEs) { + if (CPE.CPEMI == CPEMI) + return &CPE; + } + return nullptr; +} + +/// getCPEAlign - Returns the required alignment of the constant pool entry +/// represented by CPEMI. Alignment is measured in log2(bytes) units. +Align XtensaConstantIslands::getCPEAlign(const MachineInstr &CPEMI) { + assert(CPEMI.getOpcode() == Xtensa::CONSTPOOL_ENTRY); + + // Everything is 4-byte aligned unless AlignConstantIslands is set. + if (!AlignConstantIslands) + return Align(4); + + unsigned CPI = CPEMI.getOperand(1).getIndex(); + assert(CPI < MCP->getConstants().size() && "Invalid constant pool index."); + return MCP->getConstants()[CPI].getAlign(); +} + +/// initializeFunctionInfo - Do the initial scan of the function, building up +/// information about the sizes of each block, the location of all the water, +/// and finding all of the constant pool users. +void XtensaConstantIslands::initializeFunctionInfo( + const std::vector &CPEMIs) { + BBInfo.clear(); + BBInfo.resize(MF->getNumBlockIDs()); + + // First thing, compute the size of all basic blocks, and see if the function + // has any inline assembly in it. If so, we have to be conservative about + // alignment assumptions, as we don't know for sure the size of any + // instructions in the inline assembly. + for (MachineBasicBlock &MBB : *MF) + computeBlockSize(&MBB); + + // Compute block offsets. + adjustBBOffsetsAfter(&MF->front()); + + // Now go back through the instructions and build up our data structures. + for (MachineBasicBlock &MBB : *MF) { + // If this block doesn't fall through into the next MBB, then this is + // 'water' that a constant pool island could be placed. + if (!BBHasFallthrough(&MBB)) + WaterList.push_back(&MBB); + for (MachineInstr &MI : MBB) { + if (MI.isDebugInstr()) + continue; + + int Opc = MI.getOpcode(); + if (MI.isBranch()) { + bool isCond = false; + unsigned Bits = 0; + unsigned Scale = 1; + int UOpc = Xtensa::J; + switch (Opc) { + default: + continue; // Ignore other branches for now + case Xtensa::J: + Bits = BITS_JUMP; + Scale = 1; + isCond = false; + break; + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + Bits = 8; + Scale = 1; + isCond = true; + break; + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + Bits = 12; + Scale = 1; + isCond = true; + break; + case Xtensa::BT: + case Xtensa::BF: + Bits = 8; + Scale = 1; + isCond = true; + break; + } + // Record this immediate branch. + unsigned MaxOffs = ((1 << (Bits - 1)) - 1) * Scale - 4; + ImmBranches.push_back(ImmBranch(&MI, MaxOffs, isCond, UOpc)); + } + + if (Opc == Xtensa::CONSTPOOL_ENTRY) + continue; + + // Scan the instructions for constant pool operands. + for (const MachineOperand &MO : MI.operands()) + if (MO.isCPI()) { + // We found one. The addressing mode tells us the max displacement + // from the PC that this instruction permits. + unsigned CPI = MO.getIndex(); + MachineInstr *CPEMI = CPEMIs[CPI]; + + switch (Opc) { + default: + llvm_unreachable("Unknown addressing mode for CP reference!"); + case Xtensa::L32R: + CPUsers.push_back(CPUser(&MI, CPEMI, MAX_DISP_L32R)); + break; + } + + // Increment corresponding CPEntry reference count. + CPEntry *CPE = findConstPoolEntry(CPI, CPEMI); + assert(CPE && "Cannot find a corresponding CPEntry!"); + CPE->RefCount++; + + // Instructions can only use one CP entry, don't bother scanning the + // rest of the operands. + break; + } + } + } +} + +/// computeBlockSize - Compute the size and some alignment information for MBB. +/// This function updates BBInfo directly. +void XtensaConstantIslands::computeBlockSize(MachineBasicBlock *MBB) { + BasicBlockInfo &BBI = BBInfo[MBB->getNumber()]; + BBI.Size = 0; + + for (const MachineInstr &MI : *MBB) { + if (MI.getOpcode() == Xtensa::CONSTPOOL_ENTRY) { + BBI.Size += 4; + } else { + BBI.Size += TII->getInstSizeInBytes(MI); + } + } +} + +/// getOffsetOf - Return the current offset of the specified machine instruction +/// from the start of the function. This offset changes as stuff is moved +/// around inside the function. +unsigned XtensaConstantIslands::getOffsetOf(MachineInstr *MI) const { + MachineBasicBlock *MBB = MI->getParent(); + + // The offset is composed of two things: the sum of the sizes of all MBB's + // before this instruction's block, and the offset from the start of the block + // it is in. + unsigned Offset = BBInfo[MBB->getNumber()].Offset; + + // Sum instructions before MI in MBB. + for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { + assert(I != MBB->end() && "Didn't find MI in its own basic block?"); + Offset += TII->getInstSizeInBytes(*I); + } + return Offset; +} + +/// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB +/// ID. +static bool CompareMBBNumbers(const MachineBasicBlock *LHS, + const MachineBasicBlock *RHS) { + return LHS->getNumber() < RHS->getNumber(); +} + +/// updateForInsertedWaterBlock - When a block is newly inserted into the +/// machine function, it upsets all of the block numbers. Renumber the blocks +/// and update the arrays that parallel this numbering. +void XtensaConstantIslands::updateForInsertedWaterBlock( + MachineBasicBlock *NewBB) { + // Renumber the MBB's to keep them consecutive. + NewBB->getParent()->RenumberBlocks(NewBB); + + // Insert an entry into BBInfo to align it properly with the (newly + // renumbered) block numbers. + BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); + + // Next, update WaterList. Specifically, we need to add NewMBB as having + // available water after it. + water_iterator IP = llvm::lower_bound(WaterList, NewBB, CompareMBBNumbers); + WaterList.insert(IP, NewBB); +} + +unsigned XtensaConstantIslands::getUserOffset(CPUser &U) const { + return getOffsetOf(U.MI); +} + +/// Split the basic block containing MI into two blocks, which are joined by +/// an unconditional branch. Update data structures and renumber blocks to +/// account for this change and returns the newly created block. +MachineBasicBlock * +XtensaConstantIslands::splitBlockBeforeInstr(MachineInstr &MI) { + MachineBasicBlock *OrigBB = MI.getParent(); + + // Collect liveness information at MI. + LivePhysRegs LRs(*MF->getSubtarget().getRegisterInfo()); + LRs.addLiveOuts(*OrigBB); + auto LivenessEnd = ++MachineBasicBlock::iterator(MI).getReverse(); + for (MachineInstr &LiveMI : make_range(OrigBB->rbegin(), LivenessEnd)) + LRs.stepBackward(LiveMI); + + // Create a new MBB for the code after the OrigBB. + MachineBasicBlock *NewBB = + MF->CreateMachineBasicBlock(OrigBB->getBasicBlock()); + MachineFunction::iterator MBBI = ++OrigBB->getIterator(); + MF->insert(MBBI, NewBB); + + // Splice the instructions starting with MI over to NewBB. + NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end()); + + // Add an unconditional branch from OrigBB to NewBB. + // Note the new unconditional branch is not being recorded. + // There doesn't seem to be meaningful DebugInfo available; this doesn't + // correspond to anything in the source. + BuildMI(OrigBB, DebugLoc(), TII->get(Xtensa::J)).addMBB(NewBB); + ++NumSplit; + + // Update the CFG. All succs of OrigBB are now succs of NewBB. + NewBB->transferSuccessors(OrigBB); + + // OrigBB branches to NewBB. + OrigBB->addSuccessor(NewBB); + + // Update live-in information in the new block. + MachineRegisterInfo &MRI = MF->getRegInfo(); + for (MCPhysReg L : LRs) + if (!MRI.isReserved(L)) + NewBB->addLiveIn(L); + + // Update internal data structures to account for the newly inserted MBB. + // This is almost the same as updateForInsertedWaterBlock, except that + // the Water goes after OrigBB, not NewBB. + MF->RenumberBlocks(NewBB); + + // Insert an entry into BBInfo to align it properly with the (newly + // renumbered) block numbers. + BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); + + // Next, update WaterList. Specifically, we need to add OrigMBB as having + // available water after it (but not if it's already there, which happens + // when splitting before a conditional branch that is followed by an + // unconditional branch - in that case we want to insert NewBB). + water_iterator IP = llvm::lower_bound(WaterList, OrigBB, CompareMBBNumbers); + MachineBasicBlock *WaterBB = *IP; + if (WaterBB == OrigBB) + WaterList.insert(std::next(IP), NewBB); + else + WaterList.insert(IP, OrigBB); + NewWaterList.insert(OrigBB); + + // Figure out how large the OrigBB is. As the first half of the original + // block, it cannot contain a tablejump. The size includes + // the new jump we added. (It should be possible to do this without + // recounting everything, but it's very confusing, and this is rarely + // executed.) + computeBlockSize(OrigBB); + + // Figure out how large the NewMBB is. As the second half of the original + // block, it may contain a tablejump. + computeBlockSize(NewBB); + + // All BBOffsets following these blocks must be modified. + adjustBBOffsetsAfter(OrigBB); + +#if 0 + //TODO + // Need to fix live-in lists if we track liveness. + if (TRI->trackLivenessAfterRegAlloc(*MF)) + computeAndAddLiveIns(LiveRegs, *NewBB); +#endif + return NewBB; +} + +/// isOffsetInRange - Checks whether UserOffset (the location of a constant pool +/// reference) is within MaxDisp of TrialOffset (a proposed location of a +/// constant pool entry). +bool XtensaConstantIslands::isOffsetInRange(unsigned UserOffset, + unsigned TrialOffset, + unsigned MaxDisp) { + UserOffset = (UserOffset + 3) & (~0x3); + if ((UserOffset >= TrialOffset) && (UserOffset - TrialOffset <= MaxDisp)) { + return true; + } + return false; +} + +/// isWaterInRange - Returns true if a CPE placed after the specified +/// Water (a basic block) will be in range for the specific MI. +/// +/// Compute how much the function will grow by inserting a CPE after Water. +bool XtensaConstantIslands::isWaterInRange(unsigned UserOffset, + MachineBasicBlock *Water, CPUser &U, + unsigned &Growth) { + unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(); + unsigned NextBlockOffset; + Align NextBlockAlignment; + MachineFunction::const_iterator NextBlock = ++Water->getIterator(); + if (NextBlock == MF->end()) { + NextBlockOffset = BBInfo[Water->getNumber()].postOffset(); + NextBlockAlignment = Align(1); + } else { + NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset; + NextBlockAlignment = NextBlock->getAlignment(); + } + unsigned Size = U.CPEMI->getOperand(2).getImm(); + unsigned CPEEnd = CPEOffset + Size; + + // The CPE may be able to hide in the alignment padding before the next + // block. It may also cause more padding to be required if it is more aligned + // that the next block. + if (CPEEnd > NextBlockOffset) { + Growth = CPEEnd - NextBlockOffset; + // Compute the padding that would go at the end of the CPE to align the next + // block. + Growth += offsetToAlignment(CPEEnd, NextBlockAlignment); + + // If the CPE is to be inserted before the instruction, that will raise + // the offset of the instruction. Also account for unknown alignment padding + // in blocks between CPE and the user. + if (CPEOffset < UserOffset) + UserOffset += Growth; + } else + // CPE fits in existing padding. + Growth = 0; + + return isOffsetInRange(UserOffset, CPEOffset, U.getMaxDisp()); +} + +/// isCPEntryInRange - Returns true if the distance between specific MI and +/// specific ConstPool entry instruction can fit in MI's displacement field. +bool XtensaConstantIslands::isCPEntryInRange(MachineInstr *MI, + unsigned UserOffset, + MachineInstr *CPEMI, + unsigned MaxDisp, bool DoDump) { + unsigned CPEOffset = getOffsetOf(CPEMI); + + if (DoDump) { + LLVM_DEBUG({ + unsigned Block = MI->getParent()->getNumber(); + const BasicBlockInfo &BBI = BBInfo[Block]; + dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm() + << " max delta=" << MaxDisp + << format(" insn address=%#x", UserOffset) << " in " + << printMBBReference(*MI->getParent()) << ": " + << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI + << format("CPE address=%#x offset=%+d: ", CPEOffset, + int(CPEOffset - UserOffset)); + }); + } + + return isOffsetInRange(UserOffset, CPEOffset, MaxDisp); +} + +#ifndef NDEBUG +/// BBIsJumpedOver - Return true of the specified basic block's only predecessor +/// unconditionally branches to its only successor. +static bool BBIsJumpedOver(MachineBasicBlock *MBB) { + if (MBB->pred_size() != 1 || MBB->succ_size() != 1) + return false; + MachineBasicBlock *Succ = *MBB->succ_begin(); + MachineBasicBlock *Pred = *MBB->pred_begin(); + MachineInstr *PredMI = &Pred->back(); + + if (PredMI->getOpcode() == Xtensa::J) + return PredMI->getOperand(0).getMBB() == Succ; + return false; +} +#endif + +void XtensaConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) { + unsigned BBNum = BB->getNumber(); + for (unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) { + // Get the offset and known bits at the end of the layout predecessor. + // Include the alignment of the current block. + unsigned Offset = BBInfo[i - 1].Offset + BBInfo[i - 1].Size; + Align BlockAlignment = MF->getBlockNumbered(i)->getAlignment(); + BBInfo[i].Offset = Offset + offsetToAlignment(Offset, BlockAlignment); + } +} + +/// decrementCPEReferenceCount - find the constant pool entry with index CPI +/// and instruction CPEMI, and decrement its refcount. If the refcount +/// becomes 0 remove the entry and instruction. Returns true if we removed +/// the entry, false if we didn't. +bool XtensaConstantIslands::decrementCPEReferenceCount(unsigned CPI, + MachineInstr *CPEMI) { + // Find the old entry. Eliminate it if it is no longer used. + CPEntry *CPE = findConstPoolEntry(CPI, CPEMI); + assert(CPE && "Unexpected!"); + if (--CPE->RefCount == 0) { + removeDeadCPEMI(CPEMI); + CPE->CPEMI = nullptr; + --NumCPEs; + return true; + } + return false; +} + +/// LookForCPEntryInRange - see if the currently referenced CPE is in range; +/// if not, see if an in-range clone of the CPE is in range, and if so, +/// change the data structures so the user references the clone. Returns: +/// 0 = no existing entry found +/// 1 = entry found, and there were no code insertions or deletions +/// 2 = entry found, and there were code insertions or deletions +int XtensaConstantIslands::findInRangeCPEntry(CPUser &U, unsigned UserOffset) { + MachineInstr *UserMI = U.MI; + MachineInstr *CPEMI = U.CPEMI; + + // Check to see if the CPE is already in-range. + if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp())) { + LLVM_DEBUG(dbgs() << "In range\n"); + return 1; + } + + // No. Look for previously created clones of the CPE that are in range. + unsigned CPI = CPEMI->getOperand(1).getIndex(); + std::vector &CPEs = CPEntries[CPI]; + for (CPEntry &CPE : CPEs) { + // We already tried this one + if (CPE.CPEMI == CPEMI) + continue; + // Removing CPEs can leave empty entries, skip + if (CPE.CPEMI == nullptr) + continue; + if (isCPEntryInRange(UserMI, UserOffset, CPE.CPEMI, U.getMaxDisp())) { + LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" << CPE.CPI + << "\n"); + // Point the CPUser node to the replacement + U.CPEMI = CPE.CPEMI; + // Change the CPI in the instruction operand to refer to the clone. + for (MachineOperand &MO : UserMI->operands()) + if (MO.isCPI()) { + MO.setIndex(CPE.CPI); + break; + } + // Adjust the refcount of the clone... + CPE.RefCount++; + // ...and the original. If we didn't remove the old entry, none of the + // addresses changed, so we don't need another pass. + return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1; + } + } + return 0; +} + +/// getUnconditionalBrDisp - Returns the maximum displacement that can fit in +/// the specific unconditional branch instruction. +static inline unsigned getUnconditionalBrDisp(int Opc) { + // Currently only J instruction is used + return (1 << (BITS_JUMP - 1)); +} + +/// findAvailableWater - Look for an existing entry in the WaterList in which +/// we can place the CPE referenced from U so it's within range of U's MI. +/// Returns true if found, false if not. If it returns true, WaterIter +/// is set to the WaterList entry. +/// To ensure that this pass +/// terminates, the CPE location for a particular CPUser is only allowed to +/// move to a lower address, so search backward from the end of the list and +/// prefer the first water that is in range. +bool XtensaConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset, + water_iterator &WaterIter) { + if (WaterList.empty()) + return false; + + unsigned BestGrowth = ~0u; + for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();; + --IP) { + MachineBasicBlock *WaterBB = *IP; + // Check if water is in range and is either at a higher address than the + // current "low water mark" or a new water block that was created since + // the previous iteration by inserting an unconditional branch. In the + // latter case, we want to allow resetting the low water mark back to + // this new water since we haven't seen it before. Inserting branches + // should be relatively uncommon and when it does happen, we want to be + // sure to take advantage of it for all the CPEs near that block, so that + // we don't insert more branches than necessary. + unsigned Growth; + if (isWaterInRange(UserOffset, WaterBB, U, Growth) && + (WaterBB->getNumber() > U.LowWaterMark->getNumber() || + NewWaterList.count(WaterBB)) && + Growth < BestGrowth) { + // This is the least amount of required padding seen so far. + BestGrowth = Growth; + WaterIter = IP; + LLVM_DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB) + << " Growth=" << Growth << '\n'); + + // Keep looking unless it is perfect. + if (BestGrowth == 0) + return true; + } + if (IP == B) + break; + } + return BestGrowth != ~0u; +} + +/// createNewWater - No existing WaterList entry will work for +/// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the +/// block is used if in range, and the conditional branch munged so control +/// flow is correct. Otherwise the block is split to create a hole with an +/// unconditional branch around it. In either case NewMBB is set to a +/// block following which the new island can be inserted (the WaterList +/// is not adjusted). +void XtensaConstantIslands::createNewWater(unsigned CPUserIndex, + unsigned UserOffset, + MachineBasicBlock *&NewMBB) { + CPUser &U = CPUsers[CPUserIndex]; + MachineInstr *UserMI = U.MI; + MachineBasicBlock *UserMBB = UserMI->getParent(); + NewMBB = splitBlockBeforeInstr(*UserMI); +} + +/// handleConstantPoolUser - Analyze the specified user, checking to see if it +/// is out-of-range. If so, pick up the constant pool value and move it some +/// place in-range. Return true if we changed any addresses (thus must run +/// another pass of branch lengthening), false otherwise. +bool XtensaConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) { + CPUser &U = CPUsers[CPUserIndex]; + MachineInstr *UserMI = U.MI; + MachineInstr *CPEMI = U.CPEMI; + unsigned CPI = CPEMI->getOperand(1).getIndex(); + unsigned Size = CPEMI->getOperand(2).getImm(); + // Compute this only once, it's expensive. + unsigned UserOffset = getUserOffset(U); + + // See if the current entry is within range, or there is a clone of it + // in range. + int result = findInRangeCPEntry(U, UserOffset); + if (result == 1) + return false; + else if (result == 2) + return true; + + // Look for water where we can place this CPE. + MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock(); + MachineBasicBlock *NewMBB; + water_iterator IP; + if (findAvailableWater(U, UserOffset, IP)) { + LLVM_DEBUG(dbgs() << "Found water in range\n"); + MachineBasicBlock *WaterBB = *IP; + + // If the original WaterList entry was "new water" on this iteration, + // propagate that to the new island. This is just keeping NewWaterList + // updated to match the WaterList, which will be updated below. + if (NewWaterList.erase(WaterBB)) + NewWaterList.insert(NewIsland); + + // The new CPE goes before the following block (NewMBB). + NewMBB = &*++WaterBB->getIterator(); + } else { + // No water found. + LLVM_DEBUG(dbgs() << "No water found\n"); + createNewWater(CPUserIndex, UserOffset, NewMBB); + + // splitBlockBeforeInstr adds to WaterList, which is important when it is + // called while handling branches so that the water will be seen on the + // next iteration for constant pools, but in this context, we don't want + // it. Check for this so it will be removed from the WaterList. + // Also remove any entry from NewWaterList. + MachineBasicBlock *WaterBB = &*--NewMBB->getIterator(); + IP = llvm::find(WaterList, WaterBB); + if (IP != WaterList.end()) + NewWaterList.erase(WaterBB); + + // We are adding new water. Update NewWaterList. + NewWaterList.insert(NewIsland); + } + + // Remove the original WaterList entry; we want subsequent insertions in + // this vicinity to go after the one we're about to insert. This + // considerably reduces the number of times we have to move the same CPE + // more than once and is also important to ensure the algorithm terminates. + if (IP != WaterList.end()) + WaterList.erase(IP); + + // Okay, we know we can put an island before NewMBB now, do it! + MF->insert(NewMBB->getIterator(), NewIsland); + + // Update internal data structures to account for the newly inserted MBB. + updateForInsertedWaterBlock(NewIsland); + + // Decrement the old entry, and remove it if refcount becomes 0. + decrementCPEReferenceCount(CPI, CPEMI); + + // No existing clone of this CPE is within range. + // We will be generating a new clone. Get a UID for it. + unsigned ID = createPICLabelUId(); + + // Now that we have an island to add the CPE to, clone the original CPE and + // add it to the island. + U.LowWaterMark = NewIsland; + U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(Xtensa::CONSTPOOL_ENTRY)) + .addImm(ID) + .addConstantPoolIndex(CPI) + .addImm(Size); + CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1)); + ++NumCPEs; + + // Mark the basic block as aligned as required by the const-pool entry. + NewIsland->setAlignment(getCPEAlign(*U.CPEMI)); + + // Increase the size of the island block to account for the new entry. + BBInfo[NewIsland->getNumber()].Size += Size; + adjustBBOffsetsAfter(&*--NewIsland->getIterator()); + + // Finally, change the CPI in the instruction operand to be ID. + for (MachineOperand &MO : UserMI->operands()) + if (MO.isCPI()) { + MO.setIndex(ID); + break; + } + + LLVM_DEBUG( + dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI + << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset)); + + return true; +} + +/// removeDeadCPEMI - Remove a dead constant pool entry instruction. Update +/// sizes and offsets of impacted basic blocks. +void XtensaConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) { + MachineBasicBlock *CPEBB = CPEMI->getParent(); + unsigned Size = CPEMI->getOperand(2).getImm(); + CPEMI->eraseFromParent(); + BBInfo[CPEBB->getNumber()].Size -= Size; + // All succeeding offsets have the current size value added in, fix this. + if (CPEBB->empty()) { + BBInfo[CPEBB->getNumber()].Size = 0; + + // This block no longer needs to be aligned. + CPEBB->setAlignment(Align(1)); + } else { + // Entries are sorted by descending alignment, so realign from the front. + CPEBB->setAlignment(getCPEAlign(*CPEBB->begin())); + } + + adjustBBOffsetsAfter(CPEBB); + // An island has only one predecessor BB and one successor BB. Check if + // this BB's predecessor jumps directly to this BB's successor. This + // shouldn't happen currently. + assert(!BBIsJumpedOver(CPEBB) && "How did this happen?"); + // FIXME: remove the empty blocks after all the work is done? +} + +/// removeUnusedCPEntries - Remove constant pool entries whose refcounts +/// are zero. +bool XtensaConstantIslands::removeUnusedCPEntries() { + unsigned MadeChange = false; + for (std::vector &CPEs : CPEntries) { + for (CPEntry &CPE : CPEs) { + if (CPE.RefCount == 0 && CPE.CPEMI) { + removeDeadCPEMI(CPE.CPEMI); + CPE.CPEMI = nullptr; + MadeChange = true; + } + } + } + return MadeChange; +} + +/// isBBInRange - Returns true if the distance between specific MI and +/// specific BB can fit in MI's displacement field. +bool XtensaConstantIslands::isBBInRange(MachineInstr *MI, + MachineBasicBlock *DestBB, + unsigned MaxDisp) { + unsigned PCAdj = 4; + unsigned BrOffset = getOffsetOf(MI) + PCAdj; + unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; + + LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) + << " from " << printMBBReference(*MI->getParent()) + << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) + << " to " << DestOffset << " offset " + << int(DestOffset - BrOffset) << "\t" << *MI); + if (BrOffset <= DestOffset) { + // Branch before the Dest. + if (DestOffset - BrOffset < MaxDisp) + return true; + } else { + if (BrOffset - DestOffset <= MaxDisp) + return true; + } + return false; +} + +/// fixupImmediateBr - Fix up an immediate branch whose destination is too far +/// away to fit in its displacement field. +bool XtensaConstantIslands::fixupImmediateBr(ImmBranch &Br) { + MachineInstr *MI = Br.MI; + + if (MI->getOpcode() == Xtensa::JX) + return false; + + // TOOO: currently we don't fix J in start block + if (MI->getParent()->getNumber() == 0) + return false; + + unsigned TargetOperand = branchTargetOperand(MI); + MachineBasicBlock *DestBB = MI->getOperand(TargetOperand).getMBB(); + + // Check to see if the DestBB is already in-range. + if (isBBInRange(MI, DestBB, Br.MaxDisp)) + return false; + + if (!Br.isCond) + return fixupUnconditionalBr(Br); + return fixupConditionalBr(Br); +} + +/// fixupUnconditionalBr - Fix up an unconditional branch whose destination is +/// too far away to fit in its displacement field. If the LR register has been +/// spilled in the epilogue, then we can use BL to implement a far jump. +/// Otherwise, add an intermediate branch instruction to a branch. +/// fixupUnconditionalBr - Fix up an unconditional branch whose destination is +/// too far away to fit in its displacement field. If the LR register has been +/// spilled in the epilogue, then we can use BSR to implement a far jump. +/// Otherwise, add an intermediate branch instruction to a branch. +bool XtensaConstantIslands::fixupUnconditionalBr(ImmBranch &Br) { + MachineInstr *MI = Br.MI; + MachineBasicBlock *MBB = MI->getParent(); + MachineBasicBlock *DestBB = TII->getBranchDestBlock(*MI); + MachineFunction *MF = MBB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + MachineConstantPool *ConstantPool = MF->getConstantPool(); + + XtensaConstantPoolValue *C = + XtensaConstantPoolMBB::Create(MF->getFunction().getContext(), DestBB, 0); + unsigned CPSize = ConstantPool->getConstants().size(); + unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4)); + Register DestReg = MRI.createVirtualRegister(&Xtensa::ARRegClass); + + MachineInstr *CPEMI = nullptr; + // Add a new CPEntry, but no corresponding CPUser yet. + unsigned ID = Idx; + if (CPSize == Idx) { + ID = createPICLabelUId(); + CPEMI = + BuildMI(InitConstantMBB, DebugLoc(), TII->get(Xtensa::CONSTPOOL_ENTRY)) + .addImm(ID) + .addConstantPoolIndex(Idx) + .addImm(4); + CPEntries.emplace_back(1, CPEntry(CPEMI, Idx, 1)); + ++NumCPEs; + BBInfo[InitConstantMBB->getNumber()].Size += 4; + adjustBBOffsetsAfter(InitConstantMBB); + } else { + std::vector &CPEs = CPEntries[Idx]; + for (CPEntry &CPE : CPEs) { + if ((CPE.CPEMI != nullptr) && + isCPEntryInRange(MI, MAX_DISP_L32R, CPE.CPEMI, MAX_DISP_L32R, true)) { + CPEMI = CPE.CPEMI; + CPE.RefCount++; + } + } + if (CPEMI == nullptr) { + ID = createPICLabelUId(); + CPEMI = BuildMI(InitConstantMBB, DebugLoc(), + TII->get(Xtensa::CONSTPOOL_ENTRY)) + .addImm(ID) + .addConstantPoolIndex(Idx) + .addImm(4); + CPEntries[Idx].push_back(CPEntry(CPEMI, ID, 1)); + ++NumCPEs; + BBInfo[InitConstantMBB->getNumber()].Size += 4; + adjustBBOffsetsAfter(InitConstantMBB); + } else { + ID = CPEMI->getOperand(0).getImm(); + } + } + MachineInstr *L32R = + BuildMI(*MBB, MI, DebugLoc(), TII->get(Xtensa::L32R), DestReg) + .addConstantPoolIndex(ID); + + MI->setDesc(TII->get(Xtensa::JX)); + MI->removeOperand(0); + MI->addOperand(MachineOperand::CreateReg(DestReg, true)); + + RegScavenger RS; + RS.enterBasicBlockEnd(*MBB); + unsigned Scav = RS.scavengeRegisterBackwards(Xtensa::ARRegClass, + L32R->getIterator(), false, 0); + MRI.replaceRegWith(DestReg, Scav); + MRI.clearVirtRegs(); + RS.setRegUsed(Scav); + CPUsers.push_back(CPUser(L32R, CPEMI, MAX_DISP_L32R)); + BBInfo[MBB->getNumber()].Size += 3; + adjustBBOffsetsAfter(MBB); + ++NumUBrFixed; + + LLVM_DEBUG(dbgs() << " Changed B to long jump " << *MI); + return true; +} + +// TODO +/// fixupConditionalBr - Fix up a conditional branch whose destination is too +/// far away to fit in its displacement field. It is converted to an inverse +/// conditional branch + an unconditional branch to the destination. +bool XtensaConstantIslands::fixupConditionalBr(ImmBranch &Br) { + MachineInstr *MI = Br.MI; + MachineBasicBlock *DestBB = TII->getBranchDestBlock(*MI); + + SmallVector Cond; + Cond.push_back(MachineOperand::CreateImm(MI->getOpcode())); + Cond.push_back(MI->getOperand(0)); + TII->reverseBranchCondition(Cond); + // Add an unconditional branch to the destination and invert the branch + // condition to jump over it: + // bteqz L1 + // => + // bnez L2 + // b L1 + // L2: + + // If the branch is at the end of its MBB and that has a fall-through block, + // direct the updated conditional branch to the fall-through block. Otherwise, + // split the MBB before the next instruction. + MachineBasicBlock *MBB = MI->getParent(); + MachineInstr *BMI = &MBB->back(); + bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB); + + ++NumCBrFixed; + if (BMI != MI) { + if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) && + BMI->isUnconditionalBranch()) { + // Last MI in the BB is an unconditional branch. Can we simply invert the + // condition and swap destinations: + // beqz L1 + // b L2 + // => + // bnez L2 + // b L1 + MachineBasicBlock *NewDest = TII->getBranchDestBlock(*BMI); + if (isBBInRange(MI, NewDest, Br.MaxDisp)) { + LLVM_DEBUG( + dbgs() << " Invert Bcc condition and swap its destination with " + << *BMI); + BMI->getOperand(BMI->getNumExplicitOperands() - 1).setMBB(DestBB); + MI->getOperand(MI->getNumExplicitOperands() - 1).setMBB(NewDest); + + MI->setDesc(TII->get(Cond[0].getImm())); + return true; + } + } + } + + if (NeedSplit) { + splitBlockBeforeInstr(*MI); + // No need for the branch to the next block. We're adding an unconditional + // branch to the destination. + int Delta = TII->getInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size -= Delta; + MBB->back().eraseFromParent(); + + // The conditional successor will be swapped between the BBs after this, so + // update CFG. + MBB->addSuccessor(DestBB); + std::next(MBB->getIterator())->removeSuccessor(DestBB); + } + MachineBasicBlock *NextBB = &*++MBB->getIterator(); + + LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB) + << " also invert condition and change dest. to " + << printMBBReference(*NextBB) << "\n"); + + // Insert a new conditional branch and a new unconditional branch. + // Also update the ImmBranch as well as adding a new entry for the new branch. + switch (MI->getOpcode()) { + case Xtensa::BEQ: + case Xtensa::BNE: + case Xtensa::BLT: + case Xtensa::BLTU: + case Xtensa::BGE: + case Xtensa::BGEU: + BuildMI(MBB, DebugLoc(), TII->get(Cond[0].getImm())) + .addReg(MI->getOperand(0).getReg()) + .addReg(MI->getOperand(1).getReg()) + .addMBB(NextBB); + break; + case Xtensa::BEQI: + case Xtensa::BNEI: + case Xtensa::BLTI: + case Xtensa::BLTUI: + case Xtensa::BGEI: + case Xtensa::BGEUI: + BuildMI(MBB, DebugLoc(), TII->get(Cond[0].getImm())) + .addReg(MI->getOperand(0).getReg()) + .addImm(MI->getOperand(1).getImm()) + .addMBB(NextBB); + break; + case Xtensa::BEQZ: + case Xtensa::BNEZ: + case Xtensa::BLTZ: + case Xtensa::BGEZ: + BuildMI(MBB, DebugLoc(), TII->get(Cond[0].getImm())) + .addReg(MI->getOperand(0).getReg()) + .addMBB(NextBB); + break; + case Xtensa::BT: + case Xtensa::BF: + BuildMI(MBB, DebugLoc(), TII->get(Cond[0].getImm())) + .addReg(MI->getOperand(0).getReg()) + .addMBB(NextBB); + break; + } + + Br.MI = &MBB->back(); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); + BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); + unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); + ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); + + // Remove the old conditional branch. It may or may not still be in MBB. + BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI); + MI->eraseFromParent(); + adjustBBOffsetsAfter(MBB); + return true; +} + +// Check first constant island. If it is empty, then we can remove first block, +// which contains jump instruction to the third block and first constant +// insland. +void XtensaConstantIslands::removeEntryJump() { + MachineFunction *MF = InitConstantMBB->getParent(); + MachineBasicBlock *Entry = &MF->front(); + if (InitConstantMBB->empty()) { + Entry->removeSuccessor(Entry->getSingleSuccessor()); + MF->remove(Entry); + MF->remove(InitConstantMBB); + MF->RenumberBlocks(); + } +} + +/// Returns a pass that converts branches to long branches. +FunctionPass *llvm::createXtensaConstantIslandPass() { + return new XtensaConstantIslands(); +} diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index db9f411ae91388..c96fa2825d33f5 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1640,6 +1640,26 @@ let usesCustomInserter = 1, Predicates = [HasS32C1I] in { [(set AR:$dst, (atomic_load_umax_32 AR:$ptr, AR:$arg))]>; } +//===----------------------------------------------------------------------===// +// Xtensa CONSTPOOL_ENTRY +//===----------------------------------------------------------------------===// + +// An operand for the CONSTPOOL_ENTRY pseudo-instruction. +def cpinst_operand : Operand { + // let PrintMethod = "printCPInstOperand"; +} + +// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in +// the function. The first operand is the ID# for this instruction, the second +// is the index into the MachineConstantPool that this is, the third is the +// size in bytes of this constant pool entry. +// +let hasSideEffects = 0, isNotDuplicable = 1 in +def CONSTPOOL_ENTRY : +Pseudo<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, + i32imm:$size), "foo", []>; + + //===----------------------------------------------------------------------===// // Xtensa ESP32S2 Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index b9e90d356c3aae..199e16d03e4ca2 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -141,6 +141,7 @@ void XtensaPassConfig::addPreEmitPass() { addPass(createXtensaSizeReductionPass()); addPass(createXtensaFixupHwLoops()); addPass(&BranchRelaxationPassID); + addPass(createXtensaConstantIslandPass()); } TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) { diff --git a/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp index 62ad8b6b00997f..2be6c2d394f608 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp @@ -20,6 +20,12 @@ bool XtensaTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) { + // Disable hw loops when literals are placed in text section. + // TODO: Implement support of hw loops in ConstantIslands pass + if (ST->useTextSectionLiterals()) { + return false; + } + if (DisableLowOverheadLoops) return false; From 25481ce8569f61b6888d18506dde8d26a00505a5 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:22 +0300 Subject: [PATCH 136/261] [Xtensa] Disable hardware loops by default. --- llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp index 2be6c2d394f608..4accacb20f2adf 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetTransformInfo.cpp @@ -13,7 +13,7 @@ using namespace llvm; #define DEBUG_TYPE "xtensatti" static cl::opt DisableLowOverheadLoops( - "disable-xtensa-hwloops", cl::Hidden, cl::init(false), + "disable-xtensa-hwloops", cl::Hidden, cl::init(true), cl::desc("Disable the generation of hardware loops")); bool XtensaTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, From bc626556224c8892f8979426dadd14d9062ead7c Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:22 +0300 Subject: [PATCH 137/261] [Xtensa] Improve fixup error messages in asm backend. --- .../Xtensa/MCTargetDesc/XtensaAsmBackend.cpp | 14 +++++++------- .../MC/Xtensa/Relocations/fixups-diagnostics.s | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp index d3f799caab100d..d516b3b9126e06 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp @@ -94,7 +94,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case Xtensa::fixup_xtensa_branch_6: { Value -= 4; if (!isInt<6>(Value)) - Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + Ctx.reportError(Fixup.getLoc(), "branch 6-bit fixup value out is of range"); unsigned Hi2 = (Value >> 4) & 0x3; unsigned Lo4 = Value & 0xf; return (Hi2 << 4) | (Lo4 << 12); @@ -102,36 +102,36 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case Xtensa::fixup_xtensa_branch_8: Value -= 4; if (!isInt<8>(Value)) - Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + Ctx.reportError(Fixup.getLoc(), "branch 8-bit fixup value out of range"); return (Value & 0xff); case Xtensa::fixup_xtensa_branch_12: Value -= 4; if (!isInt<12>(Value)) - Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + Ctx.reportError(Fixup.getLoc(), "branch 12-bit fixup value out of range"); return (Value & 0xfff); case Xtensa::fixup_xtensa_jump_18: Value -= 4; if (!isInt<18>(Value)) - Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + Ctx.reportError(Fixup.getLoc(), "jump fixup value out of range"); return (Value & 0x3ffff); case Xtensa::fixup_xtensa_call_18: Value -= 4; if (!isInt<20>(Value)) - Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + Ctx.reportError(Fixup.getLoc(), "call fixup value out of range"); if (Value & 0x3) Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned"); return (Value & 0xffffc) >> 2; case Xtensa::fixup_xtensa_loop_8: Value -= 4; if (!isUInt<8>(Value)) - Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + Ctx.reportError(Fixup.getLoc(), "loop fixup value out of range"); return (Value & 0xff); case Xtensa::fixup_xtensa_l32r_16: unsigned Offset = Fixup.getOffset(); if (Offset & 0x3) Value -= 4; if (!isInt<18>(Value) && (Value & 0x20000)) - Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + Ctx.reportError(Fixup.getLoc(), "l32r fixup value out of range"); if (Value & 0x3) Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned"); return (Value & 0x3fffc) >> 2; diff --git a/llvm/test/MC/Xtensa/Relocations/fixups-diagnostics.s b/llvm/test/MC/Xtensa/Relocations/fixups-diagnostics.s index e0eac900552ceb..d0d7b4d0f8857c 100644 --- a/llvm/test/MC/Xtensa/Relocations/fixups-diagnostics.s +++ b/llvm/test/MC/Xtensa/Relocations/fixups-diagnostics.s @@ -2,9 +2,9 @@ .align 4 - beq a0, a1, LBL1 # CHECK: :[[@LINE]]:3: error: fixup value out of range + beq a0, a1, LBL1 # CHECK: :[[@LINE]]:3: error: branch 8-bit fixup value out of range LBL0: - beqz a0, LBL2 # CHECK: :[[@LINE]]:3: error: fixup value out of range + beqz a0, LBL2 # CHECK: :[[@LINE]]:3: error: branch 12-bit fixup value out of range call0 LBL0 # CHECK: :[[@LINE]]:3: error: fixup value must be 4-byte aligned From fe14d17e32f47522a63185e25a650a2c81b44141 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:23 +0300 Subject: [PATCH 138/261] [Xtensa] Fix hwloop tests --- llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll | 2 +- llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll b/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll index 1942d51136a21b..ba188d61b5c8ea 100644 --- a/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll +++ b/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 -disable-xtensa-hwloops=false %s -o - | FileCheck %s ; Function Attrs: norecurse nounwind optsize readnone diff --git a/llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll b/llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll index bed2d7937468da..b49102740277e2 100644 --- a/llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll +++ b/llvm/test/CodeGen/Xtensa/hwloop_unsuitable_loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 -disable-xtensa-hwloops=false %s -o - | FileCheck %s ; Function Attrs: nounwind optsize define i32 @test_hwloop(i32 %a, i32 %b, i32 %n) local_unnamed_addr #1 { @@ -29,7 +29,7 @@ for.body: ; preds = %entry, %for.body ; CHECK: #APP ; CHECK: #NO_APP ; CHECK: addi.n a4, a4, -1 -; CHECK: beqz a4, .LBB0_6 +; CHECK: beqz a4, .LBB0_6 ; CHECK:.LBB0_4: ; CHECK: bge a8, a2, .LBB0_2 From 1938b6f2251d85b6b453000e023c715d65e9b50f Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:23 +0300 Subject: [PATCH 139/261] [Xtensa] Place aggregate constants in global variable. Do not use constant pool for aggregate or vector constant types, in such cases create global variable. --- llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 17 +--------- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 31 ++++++++++++++----- .../Target/Xtensa/XtensaMachineFunctionInfo.h | 5 +++ 3 files changed, 30 insertions(+), 23 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index 9ade39dee58475..e1add300ef47b5 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -122,22 +122,7 @@ void XtensaAsmPrinter::emitMachineConstantPoolEntry( const MCSymbol &Sym = SRE.getSymbol(); str += Sym.getName(); } else { - unsigned NumElements; - if (isa(Ty)) - NumElements = (cast(Ty))->getNumElements(); - else - NumElements = Ty->getArrayNumElements(); - - for (unsigned I = 0; I < NumElements; I++) { - const Constant *CAE = C->getAggregateElement(I); - if (I > 0) - str += ", "; - if (const auto *CFP = dyn_cast(CAE)) { - str += toString(CFP->getValueAPF().bitcastToAPInt(), 10, true); - } else if (const auto *CI = dyn_cast(CAE)) { - str += toString(CI->getValue(), 10, true); - } - } + llvm_unreachable("unexpected constant pool entry type"); } OutStreamer->emitRawText(StringRef(str)); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 3e098458f4ad03..223019ebd2e391 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -1538,14 +1538,31 @@ SDValue XtensaTargetLowering::LowerJumpTable(JumpTableSDNode *JT, SDValue XtensaTargetLowering::LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const { EVT PtrVT = getPointerTy(DAG.getDataLayout()); - + auto C = const_cast(CP->getConstVal()); + auto T = const_cast(CP->getType()); SDValue Result; - if (CP->isMachineConstantPoolEntry()) - Result = - DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign()); - else - Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(), - CP->getOffset()); + + // Do not use constant pool for aggregate or vector constant types, + // in such cases create global variable + if (T->isAggregateType() || T->isVectorTy()) { + auto AFI = DAG.getMachineFunction().getInfo(); + auto M = const_cast(DAG.getMachineFunction(). + getFunction().getParent()); + auto GV = new GlobalVariable( + *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C, + Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" + + Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" + + Twine(AFI->createLabelUId()) + ); + Result = DAG.getTargetConstantPool(GV, PtrVT, Align(4)); + } else { + if (CP->isMachineConstantPoolEntry()) + Result = + DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign()); + else + Result = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), + CP->getOffset()); + } return getAddrPCRel(Result, DAG); } diff --git a/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h b/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h index 10d11fcb21bf1b..6b1b26aa6c2409 100644 --- a/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h @@ -26,6 +26,7 @@ class XtensaFunctionInfo : public MachineFunctionInfo { int VarArgsStackOffset; unsigned VarArgsFrameIndex; bool SaveFrameRegister = false; + unsigned LabelUId = 0; public: explicit XtensaFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) @@ -43,6 +44,10 @@ class XtensaFunctionInfo : public MachineFunctionInfo { bool isSaveFrameRegister() const { return SaveFrameRegister; } void setSaveFrameRegister() { SaveFrameRegister = true; } + + unsigned createLabelUId() { + return LabelUId++; + } }; } // namespace llvm From 3f0ad1b4048f2a470ed0eb13a422268a648c48cd Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:24 +0300 Subject: [PATCH 140/261] esp/ci: change clang version to 16. --- .gitlab-ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index dbe33f2bd2c313..81eae5d98a6e05 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -12,13 +12,13 @@ variables: # move all these to CI/CD settings REL_SFX: "llvm" - CLANG_VER: "15.0.0" + CLANG_VER: "16" GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" NEWLIB_REF: "esp-2022r1" BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REF: "master" - LLVM_GCC_TESTSUITE_REF: "esp-15.0.0-20221201" + LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230419" XTENSA_CLANG_TOOLCHAIN_REF: "esp-15.0.0-20221201" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 From 920ac1ccfd654e53bf7b17394b6c95a95ec2d636 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Sep 2023 12:39:43 +0300 Subject: [PATCH 141/261] toolchain: Adds compiler-rt multilibs support for Espressif toolchains --- clang/lib/Driver/ToolChains/CommonArgs.cpp | 13 +++++++++++++ clang/lib/Driver/ToolChains/CommonArgs.h | 6 ++++++ clang/lib/Driver/ToolChains/Gnu.cpp | 11 ++++++++++- clang/lib/Driver/ToolChains/RISCVToolchain.cpp | 12 ++++++++++++ 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 03558f150aa9e3..6b2c8423dc67b0 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -2802,3 +2802,16 @@ void tools::addHIPRuntimeLibArgs(const ToolChain &TC, Compilation &C, } } } + +void tools::addEspMultilibsPaths(const Driver &D, const MultilibSet &Multilibs, + const Multilib &Multilib, + StringRef CPU, + StringRef InstallPath, + ToolChain::path_list &Paths) { + if (const auto &PathsCallback = Multilibs.filePathsCallback()) + for (const auto &Path : PathsCallback(Multilib)) { + SmallString<256> LibPath(D.ResourceDir); + llvm::sys::path::append(LibPath, D.getTargetTriple(), CPU, Path, "lib"); + addPathIfExists(D, LibPath, Paths); + } +} diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h b/clang/lib/Driver/ToolChains/CommonArgs.h index 807867f13a5c30..cf9715f2d67d6d 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.h +++ b/clang/lib/Driver/ToolChains/CommonArgs.h @@ -215,6 +215,12 @@ void addMachineOutlinerArgs(const Driver &D, const llvm::opt::ArgList &Args, void addOpenMPDeviceRTL(const Driver &D, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, StringRef BitcodeSuffix, const llvm::Triple &Triple); + +void addEspMultilibsPaths(const Driver &D, const MultilibSet &Multilibs, + const Multilib &Multilib, + StringRef CPU, + StringRef InstallPath, + ToolChain::path_list &Paths); } // end namespace tools } // end namespace driver } // end namespace clang diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index 1dff0976df3412..0a36cb0b623aa9 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1985,7 +1985,8 @@ static void findXtensaMultilibs(const Driver &D, const ArgList &Args, DetectedMultilibs &Result) { MultilibSet XtensaMultilibs = MultilibSet(); - bool IsESP32 = Args.getLastArgValue(options::OPT_mcpu_EQ, "esp32").equals("esp32"); + StringRef cpu = Args.getLastArgValue(options::OPT_mcpu_EQ, "esp32"); + bool IsESP32 = cpu.equals("esp32"); XtensaMultilibs.push_back(Multilib()); if (IsESP32) @@ -2005,6 +2006,14 @@ static void findXtensaMultilibs(const Driver &D, .flag("-mfix-esp32-psram-cache-issue") .makeMultilib()); + std::string cpu_name = cpu.str(); + XtensaMultilibs + .setFilePathsCallback([cpu_name](const Multilib &M) { + return std::vector( + {M.gccSuffix(), + "/../../../../xtensa-" + cpu_name + "-elf/lib" + M.gccSuffix()}); + }); + Multilib::flags_list Flags; addMultilibFlag( Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, false), "frtti", diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp index 8d9a6e20eab3cd..0a413dcca60033 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp @@ -22,6 +22,7 @@ using namespace clang::driver::tools; using namespace clang; using namespace llvm::opt; + static void addMultilibsFilePaths(const Driver &D, const MultilibSet &Multilibs, const Multilib &Multilib, StringRef InstallPath, @@ -69,6 +70,17 @@ RISCVToolChain::RISCVToolChain(const Driver &D, const llvm::Triple &Triple, } else { getProgramPaths().push_back(D.Dir); } + + if (getTriple().getVendor() == llvm::Triple::Espressif) { + // TODO: need to detect multilibs when GCC installation is not available + addEspMultilibsPaths(D, Multilibs, SelectedMultilibs.back(), + Args.getLastArgValue(options::OPT_mcpu_EQ, "generic-rv32"), + D.getInstalledDir(), getLibraryPaths()); + addEspMultilibsPaths(D, Multilibs, SelectedMultilibs.back(), + Args.getLastArgValue(options::OPT_mcpu_EQ, "generic-rv32"), + D.getInstalledDir(), getFilePaths()); + } + getFilePaths().push_back(computeSysRoot() + "/lib"); } From 899e30f9aecd2018fa0011bccde3e2ddb79d6884 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:25 +0300 Subject: [PATCH 142/261] esp/ci: Build compiler-rt --- .gitlab-ci.yml | 8 +++++ .universal-toolchain-release.yml | 58 ++++++++++++++++++++++++++++++-- 2 files changed, 64 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 81eae5d98a6e05..7323f4fcb7b1c9 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -49,6 +49,14 @@ variables: UNARCHIVE_TOOL_NEWLIB: ${UNARCHIVE_TOOL_LINUX} ARCHIVE_EXT_NEWLIB: ${ARCHIVE_EXT_LINUX} + ARCHIVE_TOOL_COMPILER_RT: ${ARCHIVE_TOOL_LINUX} + UNARCHIVE_TOOL_COMPILER_RT: ${UNARCHIVE_TOOL_LINUX} + ARCHIVE_EXT_COMPILER_RT: ${ARCHIVE_EXT_LINUX} + + LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + DIST_DIR: "dist" BUILD_DIR: "build" DOWNLOADS_DIR: "downloads" diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 75a41258aead04..1f51bcd9d9b399 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -96,7 +96,7 @@ # Do not run unit tests for cross-builds. # Run as non-root user because permission tests fail when run by root. - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then - export LLVM_BUILD_PATH=${LLVM_PROJECT_PATH}/llvm/build-${CONF_HOST}-Release; + export LLVM_BUILD_PATH=${BUILD_PATH}/build/llvm/build-${CONF_HOST}-Release; echo "Run unit tests for native build in ${LLVM_BUILD_PATH}"; useradd -m test_runner; chown -R test_runner ${LLVM_BUILD_PATH}; @@ -193,7 +193,7 @@ build_newlib: stage: build tags: [ "amd64", "build" ] needs: - # needs native toolchainfrom this job + # needs native toolchain - job: build_x86_64-linux-gnu artifacts: paths: @@ -230,6 +230,52 @@ build_newlib: - ${ARCHIVE_TOOL_NEWLIB} ${NEWLIB_OVERLAY_DISTRO_PATH}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} esp-clang/ - popd +build_compiler-rt: + stage: build + tags: [ "amd64", "build" ] + needs: + # needs native toolchain with newlib + # newlib is necessary for building tests + - job: build_x86_64-linux-gnu + - job: build_newlib + artifacts: + paths: + - ${DIST_DIR}/ + - ${BUILD_DIR}/build.log + when: always + expire_in: 1 day + variables: + PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" + UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" + ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" + script: + - LLVM_PROJECT_PATH=$PWD + # get ARCHIVE_NAME for Linux release. + - CLANG_ARCHIVE=$PWD/${DIST_DIR}/$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) + - NEWLIB_ARCHIVE=$PWD/${DIST_DIR}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} + - mkdir -p ${DOWNLOADS_DIR} + - pushd ${DOWNLOADS_DIR} + # unpack clang + - ${UNARCHIVE_TOOL} ${CLANG_ARCHIVE} + # unpack newlib + - ${UNARCHIVE_TOOL_NEWLIB} ${NEWLIB_ARCHIVE} + # now Linux toolchain with newlib is in $PWD/esp-clang + - export PATH=$PWD/esp-clang/bin:$PATH + - popd + - rm -rf $PWD/${DIST_DIR} + - !reference [.get_clang_toolchain_build_scripts, script] + # build compiler-rt overlay using ESP native (Linux) clang toolchain only + # it will be re-used for cross-buit toolchains (win and mac). + - COMPILER_RT_OVERLAY_DISTRO_PATH=$PWD/${DIST_DIR} + - mkdir -p ${COMPILER_RT_OVERLAY_DISTRO_PATH} + - BUILD_PATH=$PWD/${BUILD_DIR} + - mkdir -p ${BUILD_PATH} + - ./build-toolchain.sh --llvm-path=${LLVM_PROJECT_PATH} --build-llvm=no --build-compiler-rt=yes ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log + - pushd ${BUILD_PATH} + - ${ARCHIVE_TOOL_COMPILER_RT} ${COMPILER_RT_OVERLAY_DISTRO_PATH}/esp-clang-compiler-rt-overlay.${ARCHIVE_EXT_COMPILER_RT} esp-clang/ + - popd + .pack_template: stage: pack tags: [ "amd64", "build" ] @@ -246,6 +292,8 @@ build_newlib: - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} -C ${BUILD_PATH} # unpack newlib - ${UNARCHIVE_TOOL_NEWLIB} ${DIST_DIR}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} -C ${BUILD_PATH} + # unpack compiler-rt + - ${UNARCHIVE_TOOL_COMPILER_RT} ${DIST_DIR}/esp-clang-compiler-rt-overlay.${ARCHIVE_EXT_COMPILER_RT} -C ${BUILD_PATH} - rm -rf ${DIST_DIR} - !reference [.get_clang_toolchain_build_scripts, script] # strip binutils afer newlib is built @@ -268,6 +316,7 @@ pack_x86_64-linux-gnu: needs: - job: build_x86_64-linux-gnu - job: build_newlib + - job: build_compiler-rt variables: CONF_HOST: "x86_64-linux-gnu" PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" @@ -278,6 +327,7 @@ pack_arm-linux-gnueabihf: needs: - job: build_arm-linux-gnueabihf - job: build_newlib + - job: build_compiler-rt variables: CONF_HOST: "arm-linux-gnueabihf" PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARMHF}" @@ -288,6 +338,7 @@ pack_aarch64-linux-gnu: needs: - job: build_aarch64-linux-gnu - job: build_newlib + - job: build_compiler-rt variables: CONF_HOST: "aarch64-linux-gnu" PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" @@ -297,6 +348,7 @@ pack_x86_64-w64-mingw32: needs: - job: build_x86_64-w64-mingw32 - job: build_newlib + - job: build_compiler-rt variables: CONF_HOST: "x86_64-w64-mingw32" PLATFORM_NAME: "${PLATFORM_NAME_WIN}" @@ -317,6 +369,7 @@ pack_x86_64-apple-darwin: needs: - job: build_x86_64-apple-darwin - job: build_newlib + - job: build_compiler-rt variables: CONF_HOST: "x86_64-apple-darwin21.1" PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" @@ -326,6 +379,7 @@ pack_aarch64-apple-darwin: needs: - job: build_aarch64-apple-darwin - job: build_newlib + - job: build_compiler-rt variables: CONF_HOST: "aarch64-apple-darwin21.1" PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" From 1636bc317c607fd300b3e89b7cd238e42325c72a Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Sep 2023 12:57:20 +0300 Subject: [PATCH 143/261] toolchain/xtensa: Enable `-frtti` by default for multilib dirs search --- clang/lib/Driver/ToolChains/Gnu.cpp | 18 +++++++++--------- clang/test/Driver/xtensa-toolchain.c | 28 ++++++++++++++-------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index 0a36cb0b623aa9..e8187332c89d15 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1989,22 +1989,22 @@ static void findXtensaMultilibs(const Driver &D, bool IsESP32 = cpu.equals("esp32"); XtensaMultilibs.push_back(Multilib()); - if (IsESP32) - XtensaMultilibs.push_back(MultilibBuilder("esp32-psram", {}, {}) - .flag("-mfix-esp32-psram-cache-issue") - .makeMultilib()); - XtensaMultilibs.push_back(MultilibBuilder("no-rtti", {}, {}) - .flag("-frtti", /*Disallow=*/true) .flag("-fno-rtti") + .flag("-frtti", /*Disallow=*/true) .makeMultilib()); - if (IsESP32) + if (IsESP32) { + XtensaMultilibs.push_back(MultilibBuilder("esp32-psram", {}, {}) + .flag("-mfix-esp32-psram-cache-issue") + .makeMultilib()); + XtensaMultilibs.push_back(MultilibBuilder("esp32-psram/no-rtti", {}, {}) + .flag("-mfix-esp32-psram-cache-issue") .flag("-fno-rtti") .flag("-frtti", /*Disallow=*/true) - .flag("-mfix-esp32-psram-cache-issue") .makeMultilib()); + } std::string cpu_name = cpu.str(); XtensaMultilibs @@ -2016,7 +2016,7 @@ static void findXtensaMultilibs(const Driver &D, Multilib::flags_list Flags; addMultilibFlag( - Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, false), "frtti", + Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, true), "frtti", Flags); if (IsESP32) diff --git a/clang/test/Driver/xtensa-toolchain.c b/clang/test/Driver/xtensa-toolchain.c index 7cf4f151de2fc2..77f23c284cf526 100644 --- a/clang/test/Driver/xtensa-toolchain.c +++ b/clang/test/Driver/xtensa-toolchain.c @@ -22,7 +22,7 @@ // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ // RUN: -target xtensa-esp-elf --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -fno-rtti 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL %s // C-XTENSA-ESP32-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" @@ -31,7 +31,7 @@ // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ // RUN: -target xtensa-esp-elf --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -frtti 2>&1 \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-RTTI %s // C-XTENSA-ESP32-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" @@ -40,7 +40,7 @@ // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ // RUN: -target xtensa-esp-elf --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue 2>&1 \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -fno-rtti -mfix-esp32-psram-cache-issue 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-PSRAM %s // C-XTENSA-ESP32-BAREMETAL-PSRAM: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" @@ -49,7 +49,7 @@ // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ // RUN: -target xtensa-esp-elf --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue -frtti 2>&1 \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI %s // C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" @@ -58,7 +58,7 @@ // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ // RUN: -target xtensa-esp-elf -mcpu=esp32s2 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -fno-rtti 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-BAREMETAL %s // C-XTENSA-ESP32S2-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" @@ -67,7 +67,7 @@ // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ // RUN: -target xtensa-esp-elf -mcpu=esp32s2 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -frtti 2>&1 \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-BAREMETAL-RTTI %s // C-XTENSA-ESP32S2-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" @@ -76,7 +76,7 @@ // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ // RUN: -target xtensa-esp-elf -mcpu=esp32s3 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -fno-rtti 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-BAREMETAL %s // C-XTENSA-ESP32S3-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" @@ -85,7 +85,7 @@ // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ // RUN: -target xtensa-esp-elf -mcpu=esp32s3 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -frtti 2>&1 \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ // RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-BAREMETAL-RTTI %s // C-XTENSA-ESP32S3-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" @@ -100,8 +100,8 @@ // C-XTENSA-ESP32-SYSROOT-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" // C-XTENSA-ESP32-SYSROOT-BAREMETAL: "--sysroot={{.*}}/Inputs/multilib_xtensa_tree/xtensa-esp32-elf" -// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" -// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" +// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" +// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" // RUN: %clang++ %s -### -no-canonical-prefixes \ // RUN: -target xtensa-esp-elf -mcpu=esp32 -stdlib=libstdc++ --rtlib=platform \ @@ -110,8 +110,8 @@ // CXX-XTENSA-ESP32-BAREMETAL: "-internal-isystem" "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf/include/c++{{/|\\\\}}8.4.0" // CXX-XTENSA-ESP32-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" -// CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" +// CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" +// CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" // RUN: %clang++ %s -### -no-canonical-prefixes \ // RUN: -target xtensa-esp-elf -mcpu=esp32 -stdlib=libstdc++ --rtlib=platform \ @@ -121,5 +121,5 @@ // CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-internal-isystem" "{{.*}}Inputs/multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0" // CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" -// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" +// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" +// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" From 444a85afa1c6dde9bd52264679b6991f7d4264ad Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:26 +0300 Subject: [PATCH 144/261] toolchain/esp: Add tests for 'compiler-rt' multilib --- .../generic-rv32/lib/clang_rt.crtbegin.o | 0 .../generic-rv32/lib/clang_rt.crtend.o | 0 .../generic-rv32/lib/libclang_rt.builtins.a | 0 .../rv32i/ilp32/lib/clang_rt.crtbegin.o | 0 .../rv32i/ilp32/lib/clang_rt.crtend.o | 0 .../rv32i/ilp32/lib/libclang_rt.builtins.a | 0 .../ilp32/no-rtti/lib/clang_rt.crtbegin.o | 0 .../rv32i/ilp32/no-rtti/lib/clang_rt.crtend.o | 0 .../ilp32/no-rtti/lib/libclang_rt.builtins.a | 0 .../rv32imac/ilp32/lib/clang_rt.crtbegin.o | 0 .../rv32imac/ilp32/lib/clang_rt.crtend.o | 0 .../rv32imac/ilp32/lib/libclang_rt.builtins.a | 0 .../ilp32/no-rtti/lib/clang_rt.crtbegin.o | 0 .../ilp32/no-rtti/lib/clang_rt.crtend.o | 0 .../ilp32/no-rtti/lib/libclang_rt.builtins.a | 0 .../rv32imafc/ilp32f/lib/clang_rt.crtbegin.o | 0 .../rv32imafc/ilp32f/lib/clang_rt.crtend.o | 0 .../ilp32f/lib/libclang_rt.builtins.a | 0 .../ilp32f/no-rtti/lib/clang_rt.crtbegin.o | 0 .../ilp32f/no-rtti/lib/clang_rt.crtend.o | 0 .../ilp32f/no-rtti/lib/libclang_rt.builtins.a | 0 .../rv32imc/ilp32/lib/clang_rt.crtbegin.o | 0 .../rv32imc/ilp32/lib/clang_rt.crtend.o | 0 .../rv32imc/ilp32/lib/libclang_rt.builtins.a | 0 .../ilp32/no-rtti/lib/clang_rt.crtbegin.o | 0 .../ilp32/no-rtti/lib/clang_rt.crtend.o | 0 .../ilp32/no-rtti/lib/libclang_rt.builtins.a | 0 .../esp32/esp32-psram/lib/clang_rt.crtbegin.o | 0 .../esp32/esp32-psram/lib/clang_rt.crtend.o | 0 .../esp32-psram/lib/libclang_rt.builtins.a | 0 .../no-rtti/lib/clang_rt.crtbegin.o | 0 .../esp32-psram/no-rtti/lib/clang_rt.crtend.o | 0 .../no-rtti/lib/libclang_rt.builtins.a | 0 .../esp32/lib/clang_rt.crtbegin.o | 0 .../esp32/lib/clang_rt.crtend.o | 0 .../esp32/lib/libclang_rt.builtins.a | 0 .../esp32/no-rtti/lib/clang_rt.crtbegin.o | 0 .../esp32/no-rtti/lib/clang_rt.crtend.o | 0 .../esp32/no-rtti/lib/libclang_rt.builtins.a | 0 .../esp32s2/lib/clang_rt.crtbegin.o | 0 .../esp32s2/lib/clang_rt.crtend.o | 0 .../esp32s2/lib/libclang_rt.builtins.a | 0 .../esp32s2/no-rtti/lib/clang_rt.crtbegin.o | 0 .../esp32s2/no-rtti/lib/clang_rt.crtend.o | 0 .../no-rtti/lib/libclang_rt.builtins.a | 0 .../esp32s3/lib/clang_rt.crtbegin.o | 0 .../esp32s3/lib/clang_rt.crtend.o | 0 .../esp32s3/lib/libclang_rt.builtins.a | 0 .../esp32s3/no-rtti/lib/clang_rt.crtbegin.o | 0 .../esp32s3/no-rtti/lib/clang_rt.crtend.o | 0 .../no-rtti/lib/libclang_rt.builtins.a | 0 .../test/Driver/riscv32-esp-toolchain-extra.c | 115 ++++++++++++++++++ .../test/Driver/xtensa-esp-toolchain-extra.c | 111 +++++++++++++++++ 53 files changed, 226 insertions(+) create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtbegin.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtend.o create mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/libclang_rt.builtins.a create mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtbegin.o create mode 100644 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mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/libclang_rt.builtins.a new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/libclang_rt.builtins.a new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/libclang_rt.builtins.a new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/libclang_rt.builtins.a new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/libclang_rt.builtins.a new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/libclang_rt.builtins.a new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/libclang_rt.builtins.a new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtbegin.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtend.o new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/libclang_rt.builtins.a new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/riscv32-esp-toolchain-extra.c b/clang/test/Driver/riscv32-esp-toolchain-extra.c new file mode 100644 index 00000000000000..13e94e981553c2 --- /dev/null +++ b/clang/test/Driver/riscv32-esp-toolchain-extra.c @@ -0,0 +1,115 @@ +// A basic clang -cc1 command-line, and simple environment check. + +// The tests here are similar to those in xtensa-toolchain.c, however +// these tests need to create symlinks to test directory trees in order to +// set up the environment and therefore shell support is required. +// REQUIRES: shell, xtensa-registered-target +// UNSUPPORTED: system-windows + +// Compiler-rt multilibs are located at '$INSTALLDIR/lib/clang/15.0.0//mcpu/'. +// At this moment multilib feature for compiler-rt is supported only when GCC installation with the same multilib structure is found. +// It is safe because ESP toolchain still depends on libstdc++ which is part of GCC installation. +// When libc++ wil be supported by toolchain the dependency on GCC multilibs will be removed. + +// RUN: rm -rf %t +// RUN: mkdir -p %t/multilib_riscv_esp_elf_sdk/bin +// RUN: ln -s %clang %t/multilib_riscv_esp_elf_sdk/bin/clang +// RUN: ln -s %S/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld %t/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld +// RUN: ln -s %S/Inputs/multilib_riscv_esp_elf_sdk/lib %t/multilib_riscv_esp_elf_sdk/lib +// RUN: ln -s %S/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf %t/multilib_riscv_esp_elf_sdk/riscv32-esp-elf + +// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ +// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ +// RUN: --target=riscv32-esp-elf -march=rv32i -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32I-RTLIB-COMPILERRT-NORTTI %s + +// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32i/ilp32/no-rtti{{/|\\\\}}crt0.o" +// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtbegin.o" +// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/libclang_rt.builtins.a" +// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ +// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ +// RUN: --target=riscv32-esp-elf -march=rv32i -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32I-RTLIB-COMPILERRT-RTTI %s + +// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32i/ilp32{{/|\\\\}}crt0.o" +// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtbegin.o" +// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/libclang_rt.builtins.a" +// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ +// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ +// RUN: --target=riscv32-esp-elf -march=rv32imc -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMC-RTLIB-COMPILERRT-NORTTI %s + +// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imc/ilp32/no-rtti{{/|\\\\}}crt0.o" +// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtbegin.o" +// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/libclang_rt.builtins.a" +// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ +// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ +// RUN: --target=riscv32-esp-elf -march=rv32imc -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMC-RTLIB-COMPILERRT-RTTI %s + +// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imc/ilp32{{/|\\\\}}crt0.o" +// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtbegin.o" +// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/libclang_rt.builtins.a" +// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ +// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ +// RUN: --target=riscv32-esp-elf -march=rv32imac -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMAC-RTLIB-COMPILERRT-NORTTI %s + +// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imac/ilp32/no-rtti{{/|\\\\}}crt0.o" +// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtbegin.o" +// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/libclang_rt.builtins.a" +// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ +// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ +// RUN: --target=riscv32-esp-elf -march=rv32imac -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMAC-RTLIB-COMPILERRT-RTTI %s + +// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imac/ilp32{{/|\\\\}}crt0.o" +// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtbegin.o" +// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/libclang_rt.builtins.a" +// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ +// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ +// RUN: --target=riscv32-esp-elf -march=rv32imafc -mabi=ilp32f --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI %s + +// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imafc/ilp32f/no-rtti{{/|\\\\}}crt0.o" +// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtbegin.o" +// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/libclang_rt.builtins.a" +// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ +// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ +// RUN: --target=riscv32-esp-elf -march=rv32imafc -mabi=ilp32f --rtlib=compiler-rt -fuse-ld= 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32IMAFC-RTLIB-COMPILERRT-RTTI %s + +// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" +// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imafc/ilp32f{{/|\\\\}}crt0.o" +// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtbegin.o" +// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/libclang_rt.builtins.a" +// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtend.o" diff --git a/clang/test/Driver/xtensa-esp-toolchain-extra.c b/clang/test/Driver/xtensa-esp-toolchain-extra.c new file mode 100644 index 00000000000000..5e195019820d40 --- /dev/null +++ b/clang/test/Driver/xtensa-esp-toolchain-extra.c @@ -0,0 +1,111 @@ +// A basic clang -cc1 command-line, and simple environment check. + +// The tests here are similar to those in xtensa-toolchain.c, however +// these tests need to create symlinks to test directory trees in order to +// set up the environment and therefore shell support is required. +// REQUIRES: shell, xtensa-registered-target +// UNSUPPORTED: system-windows + +// Compiler-rt multilibs are located at '$INSTALLDIR/lib/clang/15.0.0//mcpu/'. +// At this moment multilib feature for compiler-rt is supported only when GCC installation with the same multilib structure is found. +// It is safe because ESP toolchain still depends on libstdc++ which is part of GCC installation. +// When libc++ wil be supported by toolchain the dependency on GCC multilibs will be removed. + +// RUN: rm -rf %t +// RUN: mkdir -p %t/multilib_xtensa_tree/bin +// RUN: ln -s %clang %t/multilib_xtensa_tree/bin/clang +// RUN: ln -s %S/Inputs/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld %t/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld +// RUN: ln -s %S/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld %t/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld +// RUN: ln -s %S/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld %t/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld +// RUN: ln -s %S/Inputs/multilib_xtensa_tree/lib %t/multilib_xtensa_tree/lib +// RUN: ln -s %S/Inputs/multilib_xtensa_tree/xtensa-esp32-elf %t/multilib_xtensa_tree/xtensa-esp32-elf +// RUN: ln -s %S/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf %t/multilib_xtensa_tree/xtensa-esp32s2-elf +// RUN: ln -s %S/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf %t/multilib_xtensa_tree/xtensa-esp32s3-elf + +// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ +// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ +// RUN: --target=xtensa-esp-elf -mcpu=esp32 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI %s + +// C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtbegin.o" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/libclang_rt.builtins.a" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ +// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ +// RUN: --target=xtensa-esp-elf -mcpu=esp32 --rtlib=compiler-rt -fuse-ld= 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI %s + +// C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtbegin.o" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/libclang_rt.builtins.a" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ +// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ +// RUN: --target=xtensa-esp-elf -mcpu=esp32 --rtlib=compiler-rt -fuse-ld= -mfix-esp32-psram-cache-issue -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI %s + +// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtbegin.o" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/libclang_rt.builtins.a" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ +// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ +// RUN: --target=xtensa-esp-elf -mcpu=esp32 --rtlib=compiler-rt -fuse-ld= -mfix-esp32-psram-cache-issue 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI %s + +// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtbegin.o" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/libclang_rt.builtins.a" +// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ +// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ +// RUN: --target=xtensa-esp-elf -mcpu=esp32s2 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI %s + +// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" +// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtbegin.o" +// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/libclang_rt.builtins.a" +// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ +// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ +// RUN: --target=xtensa-esp-elf -mcpu=esp32s2 --rtlib=compiler-rt -fuse-ld= 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI %s + +// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" +// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtbegin.o" +// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/libclang_rt.builtins.a" +// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ +// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ +// RUN: --target=xtensa-esp-elf -mcpu=esp32s3 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI %s + +// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" +// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtbegin.o" +// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/libclang_rt.builtins.a" +// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtend.o" + +// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ +// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ +// RUN: --target=xtensa-esp-elf -mcpu=esp32s3 --rtlib=compiler-rt -fuse-ld= 2>&1 \ +// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI %s + +// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" +// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtbegin.o" +// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/libclang_rt.builtins.a" +// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtend.o" From 23797f62a955dc31ac783bd77785ba0c31483452 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Mon, 25 Mar 2024 15:02:22 +0300 Subject: [PATCH 145/261] toolchain/xtensa: Use GNU linker when no GCC installation is detected --- clang/lib/Driver/ToolChains/Xtensa.cpp | 35 ++++++++++++++++++++------ clang/lib/Driver/ToolChains/Xtensa.h | 2 +- 2 files changed, 28 insertions(+), 9 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index 36c10ea08a0261..f311eb24ecdd67 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -30,8 +30,6 @@ using namespace clang::driver::toolchains; using namespace clang; using namespace llvm::opt; -using tools::addMultilibFlag; - /// Xtensa Toolchain XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) @@ -112,6 +110,16 @@ XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, llvm::sys::path::append(SysRoot, "lib"); getFilePaths().push_back(SysRoot.c_str()); } + + if (getTriple().getVendor() == llvm::Triple::Espressif) { + StringRef CpuName = GetTargetCPUVersion(Args, Triple); + + // TODO: need to detect multilibs when GCC installation is not available + addEspMultilibsPaths(D, Multilibs, SelectedMultilibs.back(), CpuName, + D.getInstalledDir(), getLibraryPaths()); + addEspMultilibsPaths(D, Multilibs, SelectedMultilibs.back(), CpuName, + D.getInstalledDir(), getFilePaths()); + } } Tool *XtensaToolChain::buildLinker() const { @@ -201,12 +209,17 @@ XtensaToolChain::GetUnwindLibType(const llvm::opt::ArgList &Args) const { return ToolChain::UNW_None; } -const StringRef XtensaToolChain::GetTargetCPUVersion(const ArgList &Args) { +const StringRef XtensaToolChain::GetTargetCPUVersion(const ArgList &Args, const llvm::Triple &Triple) { + StringRef CPUName; if (Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ)) { - StringRef CPUName = A->getValue(); - return CPUName; + CPUName = A->getValue(); + } else if (Triple.getVendor() == llvm::Triple::Espressif) { + // 'esp32' is default for 'xtensa-esp-xxx' targets, + // for generic 'xtensa' target CPU should be always specified explicitly with '-mcpu' + CPUName = "esp32"; + } - return "esp32"; + return CPUName; } void tools::xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, @@ -268,11 +281,17 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, bool LinkerIsLLD; std::string LinkerPath = ToolChain.GetLinkerPath(&LinkerIsLLD); - if (ToolChain.GCCToolchainName != "") { - if (!LinkerIsLLD) { + if (!LinkerIsLLD) { + if (ToolChain.GCCToolchainName != "") { Linker.assign(ToolChain.GCCToolchainDir); llvm::sys::path::append( Linker, "bin", ToolChain.GCCToolchainName + "-" + getShortName()); + } else if (ToolChain.getTriple().getVendor() == llvm::Triple::Espressif) { + // ESP workaround, if there is no GCC installation we need to use xtensa-espXX-elf prefix for ld. + // so guess it basing on selected mcpu + Linker.assign(ToolChain.getDriver().Dir); + llvm::sys::path::append( + Linker, "xtensa-" + ToolChain.GetTargetCPUVersion(Args, ToolChain.getTriple()) + "-elf-" + getShortName()); } else { Linker.assign(LinkerPath); } diff --git a/clang/lib/Driver/ToolChains/Xtensa.h b/clang/lib/Driver/ToolChains/Xtensa.h index bef3883742db5b..d7b68e4c10782d 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.h +++ b/clang/lib/Driver/ToolChains/Xtensa.h @@ -41,7 +41,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaToolChain : public Generic_ELF { return (IsIntegratedAsm || (GCCToolchainName == "")); } - static const StringRef GetTargetCPUVersion(const llvm::opt::ArgList &Args); + static const StringRef GetTargetCPUVersion(const llvm::opt::ArgList &Args, const llvm::Triple &Triple); bool IsIntegratedAsm = true; std::string GCCLibAndIncVersion = ""; From 06d09bdaa219ef71cd352b45007eb1c1da404cf2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:27 +0300 Subject: [PATCH 146/261] tooclahin/xtensa: Add crt0.o to linker command line automatically --- clang/lib/Driver/ToolChains/Xtensa.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index f311eb24ecdd67..3a2231e9dd6ead 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -315,7 +315,8 @@ void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (WantCRTs) { // TODO: The crt0.o is not used for esp targets, but maybe used in // future for other vendors - // CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); + if (ToolChain.getTriple().getVendor() != llvm::Triple::Espressif) + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin))); } From e7da6e1873fbfad516655302a4c682db9cbd861b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:27 +0300 Subject: [PATCH 147/261] [Xtensa] Implement __ieee754_sqrtf builtin --- compiler-rt/lib/builtins/CMakeLists.txt | 6 +- .../lib/builtins/xtensa/ieee754_sqrtf.S | 53 ++++++++++++ .../builtins/Unit/xtensa/ieee754_sqrtf_test.c | 81 +++++++++++++++++++ 3 files changed, 139 insertions(+), 1 deletion(-) create mode 100644 compiler-rt/lib/builtins/xtensa/ieee754_sqrtf.S create mode 100644 compiler-rt/test/builtins/Unit/xtensa/ieee754_sqrtf_test.c diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt index d73362f0f1d0c4..f9c9f0ee9fd17d 100644 --- a/compiler-rt/lib/builtins/CMakeLists.txt +++ b/compiler-rt/lib/builtins/CMakeLists.txt @@ -733,7 +733,11 @@ set(riscv64_SOURCES set(sparc_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES}) set(sparcv9_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES}) -set(xtensa_SOURCES ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES}) +set(xtensa_SOURCES + xtensa/ieee754_sqrtf.S + ${GENERIC_SOURCES} + ${GENERIC_TF_SOURCES} +) set(wasm32_SOURCES ${GENERIC_TF_SOURCES} diff --git a/compiler-rt/lib/builtins/xtensa/ieee754_sqrtf.S b/compiler-rt/lib/builtins/xtensa/ieee754_sqrtf.S new file mode 100644 index 00000000000000..3e5f2a615e67f7 --- /dev/null +++ b/compiler-rt/lib/builtins/xtensa/ieee754_sqrtf.S @@ -0,0 +1,53 @@ +//===-- ieee754_sqrtf.S - single precision square root --------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + + .text + +#ifndef __XTENSA_SOFT_FLOAT__ + .align 4 + .global __ieee754_sqrtf + .type __ieee754_sqrtf, @function +__ieee754_sqrtf: +#ifdef __XTENSA_WINDOWED_ABI__ + entry sp, 16 +#endif + wfr f0, a2 + sqrt0.s f1, f0 + const.s f2, 0 + maddn.s f2, f1, f1 + nexp01.s f3, f0 + const.s f7, 3 + addexp.s f3, f7 + maddn.s f7, f2, f3 + nexp01.s f2, f0 + neg.s f4, f2 + maddn.s f1, f7, f1 + const.s f7, 0 + const.s f5, 0 + const.s f6, 0 + maddn.s f7, f4, f1 + maddn.s f5, f1, f3 + const.s f3, 3 + maddn.s f6, f3, f1 + maddn.s f2, f7, f7 + maddn.s f3, f5, f1 + neg.s f1, f6 + maddn.s f7, f2, f1 + maddn.s f6, f3, f6 + mksadj.s f1, f0 + nexp01.s f0, f0 + maddn.s f0, f7, f7 + neg.s f2, f6 + addexpm.s f7, f1 + addexp.s f2, f1 + divn.s f7, f0, f2 + rfr a2, f7 +#ifdef __XTENSA_WINDOWED_ABI__ + retw +#endif +#endif \ No newline at end of file diff --git a/compiler-rt/test/builtins/Unit/xtensa/ieee754_sqrtf_test.c b/compiler-rt/test/builtins/Unit/xtensa/ieee754_sqrtf_test.c new file mode 100644 index 00000000000000..29a2c168db5ac8 --- /dev/null +++ b/compiler-rt/test/builtins/Unit/xtensa/ieee754_sqrtf_test.c @@ -0,0 +1,81 @@ +// REQUIRES: xtensa-target-arch +// RUN: %clang_builtins %s %librt -o %t && %run %t +#define SINGLE_PRECISION +#include "fp_lib.h" +#include "int_lib.h" +#include +#include + +#if __xtensa__ +extern float __ieee754_sqrtf(float a); + +uint32_t test_data[32] = { + 0x1f411656, + 0x1f088887, + 0x7fc00000, + 0x7fc00000, + 0x4fb5d274, + 0x7fc00000, + 0x4bb53869, + 0x7fc00000, + 0x4ab511d2, + 0x35350b63, + 0x2a800246, + 0x7fc00000, + 0x426f77ec, + 0x7fc00000, + 0x7fc00000, + 0x541460cd, + 0x39ea0f5a, + 0x2cd13a2c, + 0x7fc00000, + 0x43054444, + 0x3160c8cb, + 0x7fc00000, + 0x4423b1e1, + 0x31f40eb0, + 0x28d6dcdd, + 0x2446a9bc, + 0x22066202, + 0x20e172a9, + 0x204c71ae, + 0x20088887, + 0x1fc11656, + 0x1f888887 +}; + +int test__ieee754_sqrtf(){ + if (__ieee754_sqrtf(-0.00000000) != -0.00000000) + return 1; + if (__ieee754_sqrtf(0.00000000) != 0.00000000) + return 1; + if (!isnan(__ieee754_sqrtf(NAN))) + return 1; + if (__ieee754_sqrtf(INFINITY) != INFINITY) + return 1; + if (__ieee754_sqrtf(4.0) != 2.0) + return 1; + + //Check some simple tests usign precalculated data + uint32_t x = 0x123456; + for (int i = 0; i < 32; i++) { + if (toRep(__ieee754_sqrtf(fromRep(x))) != test_data[i]) + return 1; + x = (x >> 1) | ((x & 1) << 31) ; + } + return 0; +} +#endif + + +int main() +{ +#if __xtensa__ + if (test__ieee754_sqrtf()) + return 1; +#else + printf("skipped\n"); +#endif + + return 0; +} From 8630f5f5b983338d3296168d2525469eb654c692 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Sep 2023 13:39:24 +0300 Subject: [PATCH 148/261] compiler-rt/tests: Adds specific build options for Espressif targets --- compiler-rt/test/builtins/Unit/lit.cfg.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler-rt/test/builtins/Unit/lit.cfg.py b/compiler-rt/test/builtins/Unit/lit.cfg.py index f63d15919888ef..0b6b971bca0d6f 100644 --- a/compiler-rt/test/builtins/Unit/lit.cfg.py +++ b/compiler-rt/test/builtins/Unit/lit.cfg.py @@ -104,7 +104,10 @@ def get_libgcc_file_name(): if sys.platform in ["win32"] and execute_external: # Don't pass dosish path separator to msys bash.exe. base_lib = base_lib.replace("\\", "/") - config.substitutions.append(("%librt ", base_lib + " -lc -lm ")) + if config.target_triple in ['xtensa-esp-elf', 'riscv32-esp-elf']: + config.substitutions.append( ("%librt ", "-Wl,--start-group," + base_lib + ',-lm,-lc,--whole-archive,-lgloss,--no-whole-archive,-lc,--whole-archive,-lsys_qemu,--no-whole-archive,--end-group ') ) + else: + config.substitutions.append( ("%librt ", base_lib + ' -lc -lm ') ) builtins_build_crt = get_required_attr(config, "builtins_build_crt") if builtins_build_crt: From 6dbc7a29a8c22ae4587d8edfb870362dead52695 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Mon, 25 Mar 2024 17:31:45 +0300 Subject: [PATCH 149/261] compiler-rt/tests: Disable tests failing for Espressif targets --- .../test/builtins/Unit/compiler_rt_fmaxl_test.c | 2 +- compiler-rt/test/builtins/Unit/compiler_rt_logb_test.c | 6 +++++- .../test/builtins/Unit/compiler_rt_logbl_test.c | 2 +- .../test/builtins/Unit/compiler_rt_scalbnf_test.c | 7 +++++++ .../test/builtins/Unit/compiler_rt_scalbnl_test.c | 2 +- compiler-rt/test/builtins/Unit/ctor_dtor.c | 2 ++ compiler-rt/test/builtins/Unit/divsc3_test.c | 9 ++++++++- compiler-rt/test/builtins/Unit/dso_handle.cpp | 2 +- compiler-rt/test/builtins/Unit/extendhfsf2_test.c | 8 ++++++++ compiler-rt/test/builtins/Unit/mulsc3_test.c | 10 +++++++++- compiler-rt/test/builtins/Unit/udivmoddi4_test.c | 3 +++ 11 files changed, 46 insertions(+), 7 deletions(-) diff --git a/compiler-rt/test/builtins/Unit/compiler_rt_fmaxl_test.c b/compiler-rt/test/builtins/Unit/compiler_rt_fmaxl_test.c index 44f75cf0c3c2a8..7ab76845a52410 100644 --- a/compiler-rt/test/builtins/Unit/compiler_rt_fmaxl_test.c +++ b/compiler-rt/test/builtins/Unit/compiler_rt_fmaxl_test.c @@ -9,7 +9,7 @@ // Since we are comparing the compiler-rt IEEE implementation against libc's // long double implementation, this test can only succeed if long double // is an IEEE 128-bit floating point number. -#if defined(CRT_HAS_TF_MODE) && defined(CRT_LDBL_IEEE_F128) +#if defined(CRT_HAS_TF_MODE) && defined(CRT_LDBL_IEEE_F128) && !defined(__riscv) int test__compiler_rt_fmaxl(fp_t x, fp_t y) { fp_t crt_value = __compiler_rt_fmaxl(x, y); diff --git a/compiler-rt/test/builtins/Unit/compiler_rt_logb_test.c b/compiler-rt/test/builtins/Unit/compiler_rt_logb_test.c index 2c1be875b0b889..c5610b5413a476 100644 --- a/compiler-rt/test/builtins/Unit/compiler_rt_logb_test.c +++ b/compiler-rt/test/builtins/Unit/compiler_rt_logb_test.c @@ -5,6 +5,8 @@ #include #include "fp_lib.h" +#if !defined(__riscv) + int test__compiler_rt_logb(fp_t x) { #if defined(__ve__) if (fpclassify(x) == FP_SUBNORMAL) @@ -29,6 +31,8 @@ double cases[] = { -0.0, 0.0, 1, -2, 2, -0.5, 0.5, }; +#endif + #ifndef __GLIBC_PREREQ #define __GLIBC_PREREQ(x, y) 0 #endif @@ -37,7 +41,7 @@ int main() { // Do not the run the compiler-rt logb test case if using GLIBC version // < 2.23. Older versions might not compute to the same value as the // compiler-rt value. -#if __GLIBC_PREREQ(2, 23) +#if __GLIBC_PREREQ(2, 23) && !defined(__riscv) const unsigned N = sizeof(cases) / sizeof(cases[0]); unsigned i; for (i = 0; i < N; ++i) { diff --git a/compiler-rt/test/builtins/Unit/compiler_rt_logbl_test.c b/compiler-rt/test/builtins/Unit/compiler_rt_logbl_test.c index f49ce710b04432..53c66f0ca6414c 100644 --- a/compiler-rt/test/builtins/Unit/compiler_rt_logbl_test.c +++ b/compiler-rt/test/builtins/Unit/compiler_rt_logbl_test.c @@ -6,7 +6,7 @@ #include #include -#if defined(CRT_HAS_TF_MODE) +#if defined(CRT_HAS_TF_MODE) && !defined(__riscv) int test__compiler_rt_logbl(fp_t x) { # if defined(__ve__) diff --git a/compiler-rt/test/builtins/Unit/compiler_rt_scalbnf_test.c b/compiler-rt/test/builtins/Unit/compiler_rt_scalbnf_test.c index 3ffdde6aed3f20..0a4694864e2df6 100644 --- a/compiler-rt/test/builtins/Unit/compiler_rt_scalbnf_test.c +++ b/compiler-rt/test/builtins/Unit/compiler_rt_scalbnf_test.c @@ -8,6 +8,8 @@ #include #include "fp_lib.h" +#if !defined(__xtensa__) && !defined(__riscv) + int test__compiler_rt_scalbnf(const char *mode, fp_t x, int y) { #if defined(__ve__) if (fpclassify(x) == FP_SUBNORMAL) @@ -52,8 +54,10 @@ int iterate_cases(const char *mode) { } return 0; } +#endif int main() { +#if !defined(__xtensa__) && !defined(__riscv) if (iterate_cases("default")) return 1; // Rounding mode tests on supported architectures. __compiler_rt_scalbnf @@ -80,6 +84,9 @@ int main() { fesetround(FE_TONEAREST); if (iterate_cases("FE_TONEAREST")) return 1; #endif +#else + printf("skipped\n"); +#endif return 0; } diff --git a/compiler-rt/test/builtins/Unit/compiler_rt_scalbnl_test.c b/compiler-rt/test/builtins/Unit/compiler_rt_scalbnl_test.c index 0d9bbdfd68e4a8..ea8cbc5bbe8bd3 100644 --- a/compiler-rt/test/builtins/Unit/compiler_rt_scalbnl_test.c +++ b/compiler-rt/test/builtins/Unit/compiler_rt_scalbnl_test.c @@ -8,7 +8,7 @@ #include #include -#if defined(CRT_HAS_TF_MODE) +#if defined(CRT_HAS_TF_MODE) && !defined(__riscv) int test__compiler_rt_scalbnl(const char *mode, fp_t x, int y) { #if defined(__ve__) diff --git a/compiler-rt/test/builtins/Unit/ctor_dtor.c b/compiler-rt/test/builtins/Unit/ctor_dtor.c index 47560722a9f750..7fa3c8d66d8439 100644 --- a/compiler-rt/test/builtins/Unit/ctor_dtor.c +++ b/compiler-rt/test/builtins/Unit/ctor_dtor.c @@ -4,6 +4,8 @@ // RUN: %clang -o %t -no-pie -nostdlib %crt1 %crti %crtbegin %t.o -lc %libgcc %crtend %crtn // RUN: %run %t 2>&1 | FileCheck %s +// UNSUPPORTED: target={{.*-esp-elf.*}} + #include #include diff --git a/compiler-rt/test/builtins/Unit/divsc3_test.c b/compiler-rt/test/builtins/Unit/divsc3_test.c index 870ab6e8453857..76e24ea8775716 100644 --- a/compiler-rt/test/builtins/Unit/divsc3_test.c +++ b/compiler-rt/test/builtins/Unit/divsc3_test.c @@ -7,6 +7,8 @@ #include #include +// __divsc3 generates LoadStorePIFAddrErrorCause under QEMU +#if !__xtensa__ // Returns: the quotient of (a + ib) / (c + id) @@ -345,9 +347,12 @@ float x[][2] = {INFINITY, INFINITY} }; +#endif int main() { +// __divsc3 generates LoadStorePIFAddrErrorCause under QEMU +#if !__xtensa__ const unsigned N = sizeof(x) / sizeof(x[0]); unsigned i, j; for (i = 0; i < N; ++i) @@ -358,6 +363,8 @@ int main() return 1; } } - +#else + printf("skipped\n"); +#endif return 0; } diff --git a/compiler-rt/test/builtins/Unit/dso_handle.cpp b/compiler-rt/test/builtins/Unit/dso_handle.cpp index 796746992af949..807fd27cfba793 100644 --- a/compiler-rt/test/builtins/Unit/dso_handle.cpp +++ b/compiler-rt/test/builtins/Unit/dso_handle.cpp @@ -6,7 +6,7 @@ // RUN: %clangxx -g -o %t -fno-pic -no-pie -nostdlib %crt1 %crti %crtbegin %t.o %libstdcxx -lc -lm %libgcc %t.so %crtend %crtn // RUN: %run %t 2>&1 | FileCheck %s -// UNSUPPORTED: target={{(arm|aarch64).*}} +// UNSUPPORTED: target={{(arm|aarch64).*}} || target={{.*-esp-elf.*}} #include diff --git a/compiler-rt/test/builtins/Unit/extendhfsf2_test.c b/compiler-rt/test/builtins/Unit/extendhfsf2_test.c index 86150e8fb0d77e..dc3cd980e4899e 100644 --- a/compiler-rt/test/builtins/Unit/extendhfsf2_test.c +++ b/compiler-rt/test/builtins/Unit/extendhfsf2_test.c @@ -5,6 +5,8 @@ #include "fp_test.h" +#if !defined(__riscv_float_abi_single) + float __extendhfsf2(TYPE_FP16 a); int test__extendhfsf2(TYPE_FP16 a, uint32_t expected) @@ -20,9 +22,11 @@ int test__extendhfsf2(TYPE_FP16 a, uint32_t expected) } char assumption_1[sizeof(TYPE_FP16) * CHAR_BIT == 16] = {0}; +#endif int main() { +#if !defined(__riscv_float_abi_single) // qNaN if (test__extendhfsf2(fromRep16(0x7e00), UINT32_C(0x7fc00000))) @@ -83,5 +87,9 @@ int main() if (test__extendhfsf2(fromRep16(0x7bff), UINT32_C(0x477fe000))) return 1; +#else + printf("skipped\n"); +#endif + return 0; } diff --git a/compiler-rt/test/builtins/Unit/mulsc3_test.c b/compiler-rt/test/builtins/Unit/mulsc3_test.c index e7cac4616a68b8..1d405b89226998 100644 --- a/compiler-rt/test/builtins/Unit/mulsc3_test.c +++ b/compiler-rt/test/builtins/Unit/mulsc3_test.c @@ -8,6 +8,9 @@ #include +// __mulsc3 generates LoadStorePIFAddrErrorCause under QEMU +#if !__xtensa__ + // Returns: the product of a + ib and c + id COMPILER_RT_ABI float _Complex @@ -345,9 +348,12 @@ float x[][2] = {INFINITY, INFINITY} }; +#endif int main() { +// __mulsc3 generates LoadStorePIFAddrErrorCause under QEMU +#if !__xtensa__ const unsigned N = sizeof(x) / sizeof(x[0]); unsigned i, j; for (i = 0; i < N; ++i) @@ -358,6 +364,8 @@ int main() return 1; } } - +#else + printf("skipped\n"); +#endif return 0; } diff --git a/compiler-rt/test/builtins/Unit/udivmoddi4_test.c b/compiler-rt/test/builtins/Unit/udivmoddi4_test.c index ed6fea3cd40161..f04a05a3c38c77 100644 --- a/compiler-rt/test/builtins/Unit/udivmoddi4_test.c +++ b/compiler-rt/test/builtins/Unit/udivmoddi4_test.c @@ -213,6 +213,8 @@ du_int tests[][4] = {0x0000000000000001uLL, 0x00000003FFFFFFFDuLL, 0x0000000000000000uLL, 0x0000000000000001uLL}, {0x0000000000000001uLL, 0x00000003FFFFFFFEuLL, 0x0000000000000000uLL, 0x0000000000000001uLL}, {0x0000000000000001uLL, 0x00000003FFFFFFFFuLL, 0x0000000000000000uLL, 0x0000000000000001uLL}, +// huge tests array does not fit into ESP32 memory, so either build fails or qemu crashes +#if !defined(__xtensa__) && !defined(__riscv) {0x0000000000000001uLL, 0x0000001000000000uLL, 0x0000000000000000uLL, 0x0000000000000001uLL}, {0x0000000000000001uLL, 0x0000001000000001uLL, 0x0000000000000000uLL, 0x0000000000000001uLL}, {0x0000000000000001uLL, 0x0000001000000002uLL, 0x0000000000000000uLL, 0x0000000000000001uLL}, @@ -20615,6 +20617,7 @@ du_int tests[][4] = {0xFFFFFFFFFFFFFFFFuLL, 0xFFFFFFFFFFFFFFFDuLL, 0x0000000000000001uLL, 0x0000000000000002uLL}, {0xFFFFFFFFFFFFFFFFuLL, 0xFFFFFFFFFFFFFFFEuLL, 0x0000000000000001uLL, 0x0000000000000001uLL}, {0xFFFFFFFFFFFFFFFFuLL, 0xFFFFFFFFFFFFFFFFuLL, 0x0000000000000001uLL, 0x0000000000000000uLL} +#endif }; int main() From 8ea7854a6426d1a6434663a7f18a3f9999fad87b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:28 +0300 Subject: [PATCH 150/261] esp/ci: Update newlib branch --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7323f4fcb7b1c9..8156bf468ad5b2 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -15,7 +15,7 @@ variables: CLANG_VER: "16" GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" - NEWLIB_REF: "esp-2022r1" + NEWLIB_REF: "esp-4.1.0_20230425" BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REF: "master" LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230419" From 6f1daf4e5021f89cecfdd48054294002e7be6a19 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:29 +0300 Subject: [PATCH 151/261] esp/ci: Saves log for 'test_x86_64-linux-gnu' --- .universal-toolchain-release.yml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 1f51bcd9d9b399..7f5f0cdfe8a00f 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -389,12 +389,19 @@ test_x86_64-linux-gnu: tags: [ "amd64", "build" ] needs: - job: pack_x86_64-linux-gnu + artifacts: + paths: + - ${BUILD_DIR}/tests.log + when: always + expire_in: 1 day variables: PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" script: + - BUILD_PATH=$PWD/$BUILD_DIR + - mkdir -p ${BUILD_PATH} - *get_release_name - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} # getting testsuite @@ -405,7 +412,7 @@ test_x86_64-linux-gnu: # qemu - ./qemu_esp32_install.sh # run testsuite for esp32 - - ./run_esp32_tests.sh + - ./run_esp32_tests.sh 2>&1 > ${BUILD_PATH}/tests.log .macos_codesign: &macos_codesign stage: sign From 34d760103873f15dd86c87886cee3f8f5f0882fc Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:29 +0300 Subject: [PATCH 152/261] esp/ci: Update 'llvm-xtensa-testsuite' ref --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 8156bf468ad5b2..be587f94940d53 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -18,7 +18,7 @@ variables: NEWLIB_REF: "esp-4.1.0_20230425" BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REF: "master" - LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230419" + LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230425" XTENSA_CLANG_TOOLCHAIN_REF: "esp-15.0.0-20221201" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 From b5eea7e21f01b3c2862f8c7ac6f98332de6c6dcd Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:30 +0300 Subject: [PATCH 153/261] esp/ci: Update 'xtensa-clang-toolchain' ref --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index be587f94940d53..c12ca71ffe244c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -19,7 +19,7 @@ variables: BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REF: "master" LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230425" - XTENSA_CLANG_TOOLCHAIN_REF: "esp-15.0.0-20221201" + XTENSA_CLANG_TOOLCHAIN_REF: "esp-16.0.0-20230502" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 PLATFORM_NAME_LINUX: "linux-amd64" From e9f70a33b65d0dc5e224733c285641b2efa5a3a0 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:30 +0300 Subject: [PATCH 154/261] esp/ci: Upload only x86_64-linux-gnu distro to HTTP server --- .universal-toolchain-release.yml | 5 ----- 1 file changed, 5 deletions(-) diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 7f5f0cdfe8a00f..4628e486d6e4c2 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -475,11 +475,6 @@ upload_to_http: GIT_STRATEGY: fetch needs: - job: pack_x86_64-linux-gnu - - job: pack_arm-linux-gnueabihf - - job: pack_aarch64-linux-gnu - - job: pack_x86_64-w64-mingw32 - - job: sign_x86_64-apple-darwin - - job: sign_aarch64-apple-darwin before_script: - !reference [.use_ci_tools, script] script: From 7c310e02be950520b9fa238864dc2355fb9677c5 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:31 +0300 Subject: [PATCH 155/261] esp/ci: stick to binutils 2.35 --- .gitlab-ci.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c12ca71ffe244c..8e7756f7bae908 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -16,6 +16,9 @@ variables: GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" NEWLIB_REF: "esp-4.1.0_20230425" + # TODO: LLVM-248. Upgrade binutils above 2.36 when Clang will be upgraded to >=17.x + # which supports 'zicsr' or 'zifencei' RISCV extensions via '-march=' + # https://www.spinics.net/lists/stable/msg645015.html BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REF: "master" LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230425" From 5ae81a5992988124c1b18d8966b294e4b4ec3323 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:31 +0300 Subject: [PATCH 156/261] [Xtensa] Fix i8/i16 ABI alignment. Set 32-bit alignmnet for i8 and i16 types. --- clang/lib/Basic/Targets/Xtensa.h | 2 +- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 9 ++++++++- llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp | 2 +- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index a23b28684e709a..0e7d054ff47a8f 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -49,7 +49,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { WIntType = UnsignedInt; UseZeroLengthBitfieldAlignment = true; MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; - resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32"); + resetDataLayout("e-m:e-p:32:32-i64:64-i128:128-n32"); } void getTargetDefines(const LangOptions &Opts, diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 223019ebd2e391..fff8c4c2583023 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -739,7 +739,14 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, if (ArgFlags.isByVal()) { Align ByValAlign = ArgFlags.getNonZeroByValAlign(); - unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), ByValAlign); + unsigned ByValSize = ArgFlags.getByValSize(); + if (ByValSize < 4) { + ByValSize = 4; + } + if (ByValAlign < Align(4)) { + ByValAlign = Align(4); + } + unsigned Offset = State.AllocateStack(ByValSize, ByValAlign); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); // Allocate rest of registers, because rest part is not used to pass // arguments diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 199e16d03e4ca2..564c57d06c1a97 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -34,7 +34,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTarget() { static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool IsLittle) { - std::string Ret = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32"; + std::string Ret = "e-m:e-p:32:32-i64:64-i128:128-n32"; return Ret; } From 1f3712531a33b3114c7bffe5709e880b8b3d60fc Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:31 +0300 Subject: [PATCH 157/261] esp/toolchain: Adds '-fdata-sections' to newlib target CFLAGS --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 8e7756f7bae908..c6253679a43bc7 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -22,7 +22,7 @@ variables: BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REF: "master" LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230425" - XTENSA_CLANG_TOOLCHAIN_REF: "esp-16.0.0-20230502" + XTENSA_CLANG_TOOLCHAIN_REF: "esp-16.0.0-20230511" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 PLATFORM_NAME_LINUX: "linux-amd64" From 52980e9ee703d63c24b525f95ad9d669a59422ab Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 1 Jun 2023 00:43:32 +0300 Subject: [PATCH 158/261] toolchain/esp: Bring 'libgcc' back to the toolchain --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c6253679a43bc7..8601675f3b7fd4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -22,7 +22,7 @@ variables: BINUTILS_REF: "esp-2022r1-binutils" XTENSA_OVERLAYS_REF: "master" LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230425" - XTENSA_CLANG_TOOLCHAIN_REF: "esp-16.0.0-20230511" + XTENSA_CLANG_TOOLCHAIN_REF: "esp-16.0.0-20230516" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 PLATFORM_NAME_LINUX: "linux-amd64" From 5785b0214df8d60bfda530a40277c72aef761484 Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Fri, 26 May 2023 12:18:45 +0200 Subject: [PATCH 159/261] [Xtensa] Respect srli assembler semantics --- .../Target/Xtensa/AsmParser/XtensaAsmParser.cpp | 14 ++++++++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 11 ++++++++++- llvm/test/MC/Xtensa/Core/invalid.s | 8 ++++++-- llvm/test/MC/Xtensa/Core/shift.s | 11 ++++++++--- 4 files changed, 38 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 4c899105c21824..d909c3eab82bd1 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -589,6 +589,20 @@ bool XtensaAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, TS.emitLiteral(Value, IDLoc); } } break; + case Xtensa::SRLI: { + uint32_t ImmOp32 = static_cast(Inst.getOperand(2).getImm()); + int64_t Imm = ImmOp32; + if (Imm >= 16 && Imm <= 31) { + MCInst TmpInst; + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(Xtensa::EXTUI); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(MCOperand::createImm(Imm)); + TmpInst.addOperand(MCOperand::createImm(32 - Imm)); + Inst = TmpInst; + } + } break; default: break; } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index c96fa2825d33f5..29bce03c303673 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -162,7 +162,7 @@ def SRAI : RRR_Inst<0x00, 0x01, 0x02, (outs AR:$r), (ins AR:$t, uimm5:$sa), let s = sa{3-0}; } -def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa), +def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm5:$sa), "srli\t$r, $t, $sa", [(set AR:$r, (srl AR:$t, uimm4:$sa))]> { bits<4> sa; @@ -170,6 +170,15 @@ def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa), let s = sa; } +def _SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa), + "_srli\t$r, $t, $sa", + [(set AR:$r, (srl AR:$t, uimm4:$sa))]> { + let DecoderNamespace = "Fallback"; + bits<4> sa; + + let s = sa; +} + def SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm1_31:$sa), "slli\t$r, $s, $sa", [(set AR:$r, (shl AR:$s, shimm1_31:$sa))]> { diff --git a/llvm/test/MC/Xtensa/Core/invalid.s b/llvm/test/MC/Xtensa/Core/invalid.s index 7fc7b47db1337e..b36f3509ea9bc9 100644 --- a/llvm/test/MC/Xtensa/Core/invalid.s +++ b/llvm/test/MC/Xtensa/Core/invalid.s @@ -21,8 +21,12 @@ slli a1, a2, 0 # CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [1, 31] # uimm4 -srli a1, a2, 16 -# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [0, 15] +_srli a1, a2, 16 +# CHECK: :[[#@LINE-1]]:15: error: expected immediate in range [0, 15] + +# uimm5 +srli a1, a2, 32 +# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [0, 31] # uimm5 srai a2, a3, 32 diff --git a/llvm/test/MC/Xtensa/Core/shift.s b/llvm/test/MC/Xtensa/Core/shift.s index 3f9c980ff55541..fbe00dc107d800 100644 --- a/llvm/test/MC/Xtensa/Core/shift.s +++ b/llvm/test/MC/Xtensa/Core/shift.s @@ -41,9 +41,14 @@ src a3, a4, a5 srl a6, a7 # Instruction format RRR -# CHECK-INST: srli a3, a4, 8 -# CHECK: encoding: [0x40,0x38,0x41] -srli a3, a4, 8 +# CHECK-INST: extui a3, a4, 18, 14 +# CHECK: encoding: [0x40,0x32,0xd5] +srli a3, a4, 18 + +# Instruction format RRR +# CHECK-INST: srli a3, a4, 14 +# CHECK: encoding: [0x40,0x3e,0x41] +_srli a3, a4, 14 # Instruction format RRR # CHECK-INST: ssa8l a14 From 3f93de2174bcfaf5e56e47265869b3248e3a2fa2 Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Wed, 28 Jun 2023 10:56:49 +0200 Subject: [PATCH 160/261] [LLD][Xtensa] Recognize bt instruction in lld --- lld/ELF/Arch/Xtensa.cpp | 20 ++++++++++---------- lld/test/ELF/xtensa-reloc.s | 2 ++ 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/lld/ELF/Arch/Xtensa.cpp b/lld/ELF/Arch/Xtensa.cpp index 10d6c3b52d1dc3..fef4d2c06b8995 100644 --- a/lld/ELF/Arch/Xtensa.cpp +++ b/lld/ELF/Arch/Xtensa.cpp @@ -95,19 +95,19 @@ RelExpr Xtensa::getRelExpr(RelType type, const Symbol &s, } static inline bool isRRI8Branch(uint8_t *loc) { - if ((loc[0] & 0x0f) == 0b0111) { - // instructions: ball, bany, bbc, bbci, bbs, bbsi, beq, bge, bgeu, blt, - // bltu, bnall, bne, bnone + // instructions: ball, bany, bbc, bbci, bbs, bbsi, beq, bge, bgeu, blt, + // bltu, bnall, bne, bnone + if ((loc[0] & 0x0f) == 0b0111) return true; - } - if ((loc[0] & 0b11'1111) == 0b10'0110) { - // instructions: beqi, bgei, bnei, blti + // instructions: beqi, bgei, bnei, blti + if ((loc[0] & 0b11'1111) == 0b10'0110) return true; - } - if ((loc[0] & 0b1011'1111) == 0b1011'0110) { - // instructions: bgeui, bltui + // instructions: bgeui, bltui + if ((loc[0] & 0b1011'1111) == 0b1011'0110) + return true; + // instruction: bt + if ((loc[0] & 0b0111'1111) == 0b0111'0110) return true; - } // some other instruction return false; } diff --git a/lld/test/ELF/xtensa-reloc.s b/lld/test/ELF/xtensa-reloc.s index e14151ae4a8141..3e3c4d4508a596 100644 --- a/lld/test/ELF/xtensa-reloc.s +++ b/lld/test/ELF/xtensa-reloc.s @@ -52,6 +52,8 @@ # CHECK: beq a3, a4, . +16 # CHECK-NEXT: ball a3, a4, . +13 # CHECK-NEXT: blt a3, a4, . +10 +# CHECK-NEXT: bt b0, . +7 beq a3, a4, d ball a3, a4, d blt a3, a4, d + bt b0, d From b5901702a2ca4c537734045668a24a78d7610867 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 22 Jun 2023 00:16:29 +0300 Subject: [PATCH 161/261] [Xtensa] Fix i8/i16 alignment. Fix frame indices elimination. The offset value in load/store instructions must be aligned to 32-bit. --- llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index 4a736cdb26f1d8..6ec817e30ddd3a 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -121,13 +121,14 @@ bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II, case Xtensa::L16SI: case Xtensa::L16UI: case Xtensa::S16I: - Valid = (Offset >= 0 && Offset <= 510); + Valid = (Offset >= 0 && Offset <= 510) && ((Offset & 0x1) == 0); break; case Xtensa::LEA_ADD: Valid = (Offset >= -128 && Offset <= 127); break; default: - Valid = (Offset >= 0 && Offset <= 1020); + // assume that MI is 32-bit load/store operation + Valid = (Offset >= 0 && Offset <= 1020) && ((Offset & 0x3) == 0); break; } From f6b185dabbf5c2057998599b93dc02294dbcd737 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Mon, 25 Mar 2024 23:23:59 +0300 Subject: [PATCH 162/261] [Xtensa] Fix asm parsing of special registers. Fix parsing of the interrupt feature registers. The "interrupt" register mnemonic is used only with rsr instruction, "intset" and "intclear" register mnemonics are used only with wsr instruction. Also fixed "debugcause" and "prid" registers parsing. Fix tryParseRegister function. --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 85 +++++++++++++------ .../Disassembler/XtensaDisassembler.cpp | 4 +- .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 18 ++++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 6 +- llvm/test/MC/Xtensa/xtensa-invalid-int.s | 19 +++++ llvm/test/MC/Xtensa/xtensa-valid-int.s | 29 ++++++- 6 files changed, 129 insertions(+), 32 deletions(-) create mode 100644 llvm/test/MC/Xtensa/xtensa-invalid-int.s diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index d909c3eab82bd1..0895c3dd135ace 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -78,6 +78,7 @@ class XtensaAsmParser : public MCTargetAsmParser { ParseStatus parseImmediate(OperandVector &Operands); ParseStatus parseRegister(OperandVector &Operands, + StringRef Mnemonic, bool AllowParens = false, bool SR = false, bool UR = false); ParseStatus parseOperandWithModifier(OperandVector &Operands); @@ -86,11 +87,9 @@ class XtensaAsmParser : public MCTargetAsmParser { bool ParseInstructionWithSR(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands); ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, - SMLoc &EndLoc) override { - return ParseStatus::NoMatch; - } + SMLoc &EndLoc) override; ParseStatus parsePCRelTarget(OperandVector &Operands); - bool checkRegister(unsigned RegNo); + bool checkRegister(StringRef Mnemonic, StringRef RegName, MCRegister RegNo); bool parseLiteralDirective(SMLoc L); bool parseBeginDirective(SMLoc L); bool parseEndDirective(SMLoc L); @@ -732,6 +731,29 @@ ParseStatus XtensaAsmParser::parsePCRelTarget(OperandVector &Operands) { return ParseStatus::Success; } +// Attempts to match Name as a register (either using the default name or +// alternative ABI names), setting RegNo to the matching register. Upon +// failure, returns true and sets RegNo to 0 +static bool matchRegisterNameHelper(MCRegister &RegNo, StringRef Name) { + RegNo = MatchRegisterName(Name); + + if (RegNo == Xtensa::NoRegister) + RegNo = MatchRegisterAltName(Name.lower()); + + if (RegNo == Xtensa::NoRegister) + RegNo = MatchRegisterAltName(Name.upper()); + + return RegNo == Xtensa::NoRegister; +} + +ParseStatus XtensaAsmParser::tryParseRegister(MCRegister &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { + if (parseRegister(RegNo, StartLoc, EndLoc)) + return ParseStatus::NoMatch; + return ParseStatus::Success; +} + bool XtensaAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { const AsmToken &Tok = getParser().getTok(); @@ -749,12 +771,14 @@ bool XtensaAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, } ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, + StringRef Mnemonic, bool AllowParens, bool SR, bool UR) { SMLoc FirstS = getLoc(); bool HadParens = false; AsmToken Buf[2]; std::string RegName = ""; + MCRegister RegNo = 0; int64_t Num; bool IsIdentifier = false; @@ -769,8 +793,6 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, } } - unsigned RegNo = 0; - switch (getLexer().getKind()) { default: return ParseStatus::NoMatch; @@ -808,16 +830,13 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, RegName = "F64S"; } else RegName = std::to_string(Num); - RegNo = MatchRegisterName(RegName); - if (RegNo == 0) - RegNo = MatchRegisterAltName(RegName); + + matchRegisterNameHelper(RegNo, RegName); break; case AsmToken::Identifier: IsIdentifier = true; RegName = getLexer().getTok().getIdentifier().str(); - RegNo = MatchRegisterName(RegName); - if (RegNo == 0) - RegNo = MatchRegisterAltName(RegName); + matchRegisterNameHelper(RegNo, RegName); break; } @@ -827,7 +846,7 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, return ParseStatus::NoMatch; } - if (!checkRegister(RegNo)) { + if (!checkRegister(Mnemonic.lower(), RegName, RegNo)) { return ParseStatus::NoMatch; } @@ -902,7 +921,7 @@ bool XtensaAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, return true; // Attempt to parse token as register - if (parseRegister(Operands, true, SR, UR).isSuccess()) + if (parseRegister(Operands, Mnemonic, true, SR, UR) == MatchOperand_Success) return false; // Attempt to parse token as an immediate @@ -931,15 +950,11 @@ bool XtensaAsmParser::ParseInstructionWithSR(ParseInstructionInfo &Info, Operands.push_back(XtensaOperand::createToken(Name.take_front(3), NameLoc)); StringRef RegName = Name.drop_front(4); - unsigned RegNo = MatchRegisterName(RegName); - - if (RegNo == 0) - RegNo = MatchRegisterAltName(RegName); + MCRegister RegNo = 0; - if (RegNo == 0) - return Error(NameLoc, "invalid register name"); + matchRegisterNameHelper(RegNo, RegName); - if (!checkRegister(RegNo)) { + if (!checkRegister(Name.lower(), RegName, RegNo)) { Error(NameLoc, "invalid register name"); return true; } @@ -1151,7 +1166,8 @@ bool XtensaAsmParser::ParseDirective(AsmToken DirectiveID) { } // Verify SR and UR -bool XtensaAsmParser::checkRegister(unsigned RegNo) { +bool XtensaAsmParser::checkRegister(StringRef Mnemonic, StringRef RegName, + MCRegister RegNo) { StringRef CPU = getSTI().getCPU(); unsigned NumIntLevels = 0; unsigned NumTimers = 0; @@ -1160,6 +1176,8 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { bool IsESP32S2 = false; bool IsESP32S3 = false; bool Res = true; + bool IsWSR = Mnemonic.startswith("wsr"); + bool IsRSR = Mnemonic.startswith("rsr"); // Assume that CPU is esp32 by default if ((CPU == "esp32") || (CPU == "")) { @@ -1216,11 +1234,14 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { case Xtensa::DBREAKA1: case Xtensa::DBREAKC0: case Xtensa::DBREAKC1: - case Xtensa::DEBUGCAUSE: case Xtensa::ICOUNT: case Xtensa::ICOUNTLEVEL: Res = hasDebug(); break; + case Xtensa::DEBUGCAUSE: + Res = hasDebug(); + Res = Res & IsRSR; + break; case Xtensa::ATOMCTL: Res = hasATOMCTL(); break; @@ -1283,9 +1304,23 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { break; case Xtensa::PRID: Res = hasPRID(); + Res = Res & IsRSR; + break; + case Xtensa::INTERRUPT: + // INTSET mnemonic is wrtite-only + // INTERRUPT mnemonic is read-only + if (RegName.startswith("intset")) { + if (!IsWSR) + Res = false; + } else if (!IsRSR) { + Res = false; + } + Res = Res & hasInterrupt(); break; - case Xtensa::INTSET: case Xtensa::INTCLEAR: + Res = hasInterrupt(); + Res = Res & IsWSR; + break; case Xtensa::INTENABLE: Res = hasInterrupt(); break; @@ -1314,6 +1349,8 @@ bool XtensaAsmParser::checkRegister(unsigned RegNo) { case Xtensa::F64S: Res = hasDFPAccel(); break; + case Xtensa::NoRegister: + Res = false; } return Res; diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index a55a13340075bd..e2974da88a4410 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -275,7 +275,7 @@ bool CheckRegister(unsigned RegNo, MCSubtargetInfo STI) { case Xtensa::PRID: Res = STI.getFeatureBits()[Xtensa::FeaturePRID]; break; - case Xtensa::INTSET: + case Xtensa::INTERRUPT: case Xtensa::INTCLEAR: case Xtensa::INTENABLE: Res = STI.getFeatureBits()[Xtensa::FeatureInterrupt]; @@ -335,7 +335,7 @@ static const unsigned SRDecoderTable[] = { Xtensa::EXCSAVE2, 210, Xtensa::EXCSAVE3, 211, Xtensa::EXCSAVE4, 212, Xtensa::EXCSAVE5, 213, Xtensa::EXCSAVE6, 214, Xtensa::EXCSAVE7, 215, - Xtensa::CPENABLE, 224, Xtensa::INTSET, 226, + Xtensa::CPENABLE, 224, Xtensa::INTERRUPT, 226, Xtensa::INTCLEAR, 227, Xtensa::INTENABLE, 228, Xtensa::PS, 230, Xtensa::VECBASE, 231, Xtensa::EXCCAUSE, 232, Xtensa::DEBUGCAUSE, 233, diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index 0a0d298ad267a6..85db697c724d62 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -12,6 +12,7 @@ // //===----------------------------------------------------------------------===// +#include "XtensaInstrInfo.h" #include "XtensaInstPrinter.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/MC/MCExpr.h" @@ -70,6 +71,23 @@ void XtensaInstPrinter::printOperand(const MCOperand &MC, raw_ostream &O) { void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) { + unsigned Opcode = MI->getOpcode(); + + switch (Opcode) { + case Xtensa::WSR: { + // INTERRUPT mnemonic is read-only, so use INTSET mnemonic instead + Register SR = MI->getOperand(0).getReg(); + if (SR == Xtensa::INTERRUPT) { + Register Reg = MI->getOperand(1).getReg(); + O << '\t' << "wsr" << '\t'; + printRegName(O, Reg); + O << ", " + << "intset"; + printAnnotation(O, Annot); + return; + } + } + } printInstruction(MI, Address, O); printAnnotation(O, Annot); } diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 93e67af82fc86f..73b4a3cd00b589 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -163,7 +163,7 @@ def EXCSAVE7 : SRReg<215, "excsave7", ["EXCSAVE7", "215"]>; def CPENABLE : SRReg<224, "cpenable", ["CPENABLE", "224"]>; // Interrupt enable mask register -def INTSET : SRReg<226, "interrupt", ["INTERRUPT", "226"]>; +def INTERRUPT : SRReg<226, "interrupt", ["INTERRUPT", "INTSET", "226"]>; def INTCLEAR : SRReg<227, "intclear", ["INTCLEAR", "227"]>; @@ -213,8 +213,8 @@ def SR : RegisterClass<"Xtensa", [i32], 32, (add WINDOWBASE, WINDOWSTART, IBREAKENABLE, MEMCTL, ATOMCTL, DDR, IBREAKA0, IBREAKA1, DBREAKA0, DBREAKA1, DBREAKC0, DBREAKC1, CONFIGID0, EPC1, EPC2, EPC3, EPC4, EPC5, EPC6, EPC7, DEPC, EPS2, EPS3, EPS4, EPS5, EPS6, EPS7, CONFIGID1, EXCSAVE1, EXCSAVE2, - EXCSAVE3, EXCSAVE4, EXCSAVE5, EXCSAVE6, EXCSAVE7, CPENABLE, INTSET, INTCLEAR, INTENABLE, PS, - VECBASE, EXCCAUSE, DEBUGCAUSE, CCOUNT, PRID, ICOUNT, ICOUNTLEVEL, EXCVADDR, CCOMPARE0, + EXCSAVE3, EXCSAVE4, EXCSAVE5, EXCSAVE6, EXCSAVE7, CPENABLE, INTERRUPT, INTCLEAR, INTENABLE, + PS, VECBASE, EXCCAUSE, DEBUGCAUSE, CCOUNT, PRID, ICOUNT, ICOUNTLEVEL, EXCVADDR, CCOMPARE0, CCOMPARE1, CCOMPARE2, MISC0, MISC1, MISC2, MISC3)>; //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/Xtensa/xtensa-invalid-int.s b/llvm/test/MC/Xtensa/xtensa-invalid-int.s new file mode 100644 index 00000000000000..2a95c9ccd6810e --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-invalid-int.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple xtensa %s 2>&1 | FileCheck %s + +.align 4 +LBL0: + +rsr a0, intclear +# CHECK: :[[#@LINE-1]]:9: error: invalid operand for instruction + +rsr a0, intset +# CHECK: :[[#@LINE-1]]:9: error: invalid operand for instruction + +wsr a1, interrupt +# CHECK: :[[#@LINE-1]]:9: error: invalid operand for instruction + +xsr a1, intset +# CHECK: :[[#@LINE-1]]:9: error: invalid operand for instruction + +xsr a1, interrupt +# CHECK: :[[#@LINE-1]]:9: error: invalid operand for instruction diff --git a/llvm/test/MC/Xtensa/xtensa-valid-int.s b/llvm/test/MC/Xtensa/xtensa-valid-int.s index a24191ef4aa5a0..68d1f24dc4ea83 100644 --- a/llvm/test/MC/Xtensa/xtensa-valid-int.s +++ b/llvm/test/MC/Xtensa/xtensa-valid-int.s @@ -1,7 +1,6 @@ # RUN: llvm-mc %s -triple=xtensa -mattr=+interrupt -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s - .align 4 LBL0: @@ -12,7 +11,31 @@ LBL0: # CHECK-INST: rsil a3, 1 # CHECK: encoding: [0x30,0x61,0x00] rsil a3, 1 - + +# CHECK-INST: rsr a8, interrupt +# CHECK: encoding: [0x80,0xe2,0x03] +rsr a8, interrupt + # CHECK-INST: waiti 1 # CHECK: encoding: [0x00,0x71,0x00] - waiti 1 \ No newline at end of file + waiti 1 + +# CHECK-INST: wsr a0, intclear +# CHECK: encoding: [0x00,0xe3,0x13] + wsr a0, intclear + +# CHECK-INST: wsr a0, intclear +# CHECK: encoding: [0x00,0xe3,0x13] + wsr.intclear a0 + +# CHECK-INST: wsr a0, intset +# CHECK: encoding: [0x00,0xe2,0x13] + wsr a0, intset + +# CHECK-INST: wsr a0, intset +# CHECK: encoding: [0x00,0xe2,0x13] + wsr.intset a0 + +# CHECK-INST: wsr a0, intset +# CHECK: encoding: [0x00,0xe2,0x13] + wsr.INTSET a0 From fbce94a73db6adfc9737589d490003e7f2d188e8 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Mar 2024 01:32:59 +0300 Subject: [PATCH 163/261] [Xtensa] Implement ESP32 S3 DSP instructions. --- clang/include/clang/Basic/BuiltinsXtensa.def | 3 + .../clang/Basic/BuiltinsXtensaESP32S3.def | 269 + clang/lib/Sema/SemaChecking.cpp | 228 + .../CodeGen/Xtensa/xtensa-ee-intrinsics.c | 514 ++ llvm/include/llvm/IR/IntrinsicsXtensa.td | 6 +- .../llvm/IR/IntrinsicsXtensaESP32S3.td | 767 +++ .../Xtensa/AsmParser/XtensaAsmParser.cpp | 83 +- llvm/lib/Target/Xtensa/CMakeLists.txt | 1 + .../Disassembler/XtensaDisassembler.cpp | 121 + .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 129 + .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 11 + .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 187 +- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 34 +- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 6 +- llvm/lib/Target/Xtensa/XtensaInstrFormats.td | 12 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 2 + llvm/lib/Target/Xtensa/XtensaOperands.td | 83 + llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 27 +- .../lib/Target/Xtensa/XtensaS3DSPInstrInfo.td | 5659 +++++++++++++++++ .../Target/Xtensa/XtensaS3ISelLowering.cpp | 5262 +++++++++++++++ .../test/CodeGen/Xtensa/ee-intrinsics-loop.ll | 148 + llvm/test/CodeGen/Xtensa/xtensa-s3-dsp.ll | 764 +++ llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s | 508 +- 23 files changed, 14797 insertions(+), 27 deletions(-) create mode 100644 clang/include/clang/Basic/BuiltinsXtensaESP32S3.def create mode 100644 clang/test/CodeGen/Xtensa/xtensa-ee-intrinsics.c create mode 100644 llvm/include/llvm/IR/IntrinsicsXtensaESP32S3.td create mode 100644 llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td create mode 100644 llvm/lib/Target/Xtensa/XtensaS3ISelLowering.cpp create mode 100644 llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-s3-dsp.ll diff --git a/clang/include/clang/Basic/BuiltinsXtensa.def b/clang/include/clang/Basic/BuiltinsXtensa.def index 47f75f1665b163..bc852bfc984a21 100644 --- a/clang/include/clang/Basic/BuiltinsXtensa.def +++ b/clang/include/clang/Basic/BuiltinsXtensa.def @@ -124,4 +124,7 @@ BUILTIN(__builtin_xtensa_wsr_m3, "vUi", "n") BUILTIN(__builtin_xtensa_rsr_m3, "Ui", "n") BUILTIN(__builtin_xtensa_xsr_m3, "vUi*", "n") +// generated code +#include "clang/Basic/BuiltinsXtensaESP32S3.def" + #undef BUILTIN \ No newline at end of file diff --git a/clang/include/clang/Basic/BuiltinsXtensaESP32S3.def b/clang/include/clang/Basic/BuiltinsXtensaESP32S3.def new file mode 100644 index 00000000000000..6a5a3e2541f0c9 --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsXtensaESP32S3.def @@ -0,0 +1,269 @@ +//=== BuiltinsXtensaESP32S3.def - Xtensa Builtin function database -*- C++ -*-// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the Xtensa-specific builtin function database. Users of +// this file must define the BUILTIN macro to make use of this information. +// +// Automatically generated file, do not edit! +// +//===----------------------------------------------------------------------===// + +// The format of this database matches clang/Basic/Builtins.def. + +BUILTIN(__builtin_xtensa_ee_andq, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_bitrev, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_cmul_s16, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_cmul_s16_ld_incp, "vUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_cmul_s16_st_incp, "vUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_ams_s16_ld_incp, "vUiUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_ams_s16_ld_incp_uaup, "vUiUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_ams_s16_ld_r32_decp, "vUiUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_ams_s16_st_incp, "vUiUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_cmul_s16_ld_xp, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_cmul_s16_st_xp, "vUiUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_r2bf_s16, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_r2bf_s16_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_fft_vst_r32_decp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ldf_128_ip, "vffffUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ldf_128_xp, "vffffUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ldf_64_ip, "vffUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ldf_64_xp, "vffUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ldqa_s16_128_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ldqa_s16_128_xp, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ldqa_s8_128_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ldqa_s8_128_xp, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ldqa_u16_128_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ldqa_u16_128_xp, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ldqa_u8_128_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ldqa_u8_128_xp, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ldxq_32, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ld_128_usar_ip, "vUiUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ld_128_usar_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_ld_accx_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ld_qacc_h_h_32_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ld_qacc_h_l_128_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ld_qacc_l_h_32_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ld_qacc_l_l_128_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_ld_ua_state_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_movi_32_a, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_movi_32_q, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_mov_s16_qacc, "vUi", "n") +BUILTIN(__builtin_xtensa_ee_mov_s8_qacc, "vUi", "n") +BUILTIN(__builtin_xtensa_ee_mov_u16_qacc, "vUi", "n") +BUILTIN(__builtin_xtensa_ee_mov_u8_qacc, "vUi", "n") +BUILTIN(__builtin_xtensa_ee_notq, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_orq, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_slci_2q, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_slcxxp_2q, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_srci_2q, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_srcmb_s16_qacc, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_srcmb_s8_qacc, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_srcq_128_st_incp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_srcxxp_2q, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_src_q, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_src_q_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_src_q_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_src_q_qup, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_srs_accx, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_stf_128_ip, "vffffUiIi", "n") +BUILTIN(__builtin_xtensa_ee_stf_128_xp, "vffffUiUi", "n") +BUILTIN(__builtin_xtensa_ee_stf_64_ip, "vffUiIi", "n") +BUILTIN(__builtin_xtensa_ee_stf_64_xp, "vffUiUi", "n") +BUILTIN(__builtin_xtensa_ee_stxq_32, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_st_accx_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_st_qacc_h_h_32_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_st_qacc_h_l_128_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_st_qacc_l_h_32_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_st_qacc_l_l_128_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_st_ua_state_ip, "vUiIi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s16_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s16_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s32, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s32_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s32_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s8_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vadds_s8_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_eq_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_eq_s32, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_eq_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_gt_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_gt_s32, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_gt_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_lt_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_lt_s32, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vcmp_lt_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_16, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_16_ip, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_16_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_32, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_32_ip, "vUiUiIi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_32_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_8, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_8_ip, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldbc_8_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vldhbc_16_incp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vld_128_ip, "vUiUiIi", "n") +BUILTIN(__builtin_xtensa_ee_vld_128_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vld_h_64_ip, "vUiUiIi", "n") +BUILTIN(__builtin_xtensa_ee_vld_h_64_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vld_l_64_ip, "vUiUiIi", "n") +BUILTIN(__builtin_xtensa_ee_vld_l_64_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s16_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s16_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s32, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s32_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s32_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s8_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmax_s8_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s16_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s16_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s32, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s32_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s32_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s8_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmin_s8_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_accx, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_accx_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_accx_ld_ip_qup, "vUiUiIiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_accx_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_accx_ld_xp_qup, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_qacc, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_qacc_ldbc_incp, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup, "vUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_qacc_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_qacc_ld_ip_qup, "vUiUiIiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_qacc_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s16_qacc_ld_xp_qup, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_accx, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_accx_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_accx_ld_ip_qup, "vUiUiIiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_accx_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_accx_ld_xp_qup, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_qacc, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_qacc_ldbc_incp, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup, "vUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_qacc_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_qacc_ld_ip_qup, "vUiUiIiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_qacc_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_s8_qacc_ld_xp_qup, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_accx, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_accx_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_accx_ld_ip_qup, "vUiUiIiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_accx_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_accx_ld_xp_qup, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_qacc, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_qacc_ldbc_incp, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup, "vUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_qacc_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_qacc_ld_ip_qup, "vUiUiIiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_qacc_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u16_qacc_ld_xp_qup, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_accx, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_accx_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_accx_ld_ip_qup, "vUiUiIiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_accx_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_accx_ld_xp_qup, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_qacc, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_qacc_ldbc_incp, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup, "vUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_qacc_ld_ip, "vUiUiIiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_qacc_ld_ip_qup, "vUiUiIiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_qacc_ld_xp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmulas_u8_qacc_ld_xp_qup, "vUiUiUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_s16_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_s16_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_s8_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_s8_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_u16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_u16_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_u16_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_u8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_u8_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vmul_u8_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vprelu_s16, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vprelu_s8, "vUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vrelu_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vrelu_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsl_32, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsmulas_s16_qacc, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsmulas_s16_qacc_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsmulas_s8_qacc, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsmulas_s8_qacc_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsr_32, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vst_128_ip, "vUiUiIi", "n") +BUILTIN(__builtin_xtensa_ee_vst_128_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vst_h_64_ip, "vUiUiIi", "n") +BUILTIN(__builtin_xtensa_ee_vst_h_64_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vst_l_64_ip, "vUiUiIi", "n") +BUILTIN(__builtin_xtensa_ee_vst_l_64_xp, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s16, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s16_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s16_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s32, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s32_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s32_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s8, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s8_ld_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vsubs_s8_st_incp, "vUiUiUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vunzip_16, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vunzip_32, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vunzip_8, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vzip_16, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vzip_32, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_vzip_8, "vUiUi", "n") +BUILTIN(__builtin_xtensa_ee_xorq, "vUiUiUi", "n") +BUILTIN(__builtin_xtensa_ee_zero_accx, "v", "n") +BUILTIN(__builtin_xtensa_ee_zero_q, "vUi", "n") +BUILTIN(__builtin_xtensa_ee_zero_qacc, "v", "n") +BUILTIN(__builtin_xtensa_rur_accx_0, "i", "n") +BUILTIN(__builtin_xtensa_rur_accx_1, "i", "n") +BUILTIN(__builtin_xtensa_rur_fft_bit_width, "i", "n") +BUILTIN(__builtin_xtensa_rur_gpio_out, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_h_0, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_h_1, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_h_2, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_h_3, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_h_4, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_l_0, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_l_1, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_l_2, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_l_3, "i", "n") +BUILTIN(__builtin_xtensa_rur_qacc_l_4, "i", "n") +BUILTIN(__builtin_xtensa_rur_sar_byte, "i", "n") +BUILTIN(__builtin_xtensa_rur_ua_state_0, "i", "n") +BUILTIN(__builtin_xtensa_rur_ua_state_1, "i", "n") +BUILTIN(__builtin_xtensa_rur_ua_state_2, "i", "n") +BUILTIN(__builtin_xtensa_rur_ua_state_3, "i", "n") +BUILTIN(__builtin_xtensa_wur_accx_0, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_accx_1, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_fft_bit_width, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_gpio_out, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_h_0, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_h_1, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_h_2, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_h_3, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_h_4, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_l_0, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_l_1, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_l_2, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_l_3, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_qacc_l_4, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_sar_byte, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_ua_state_0, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_ua_state_1, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_ua_state_2, "vUi", "n") +BUILTIN(__builtin_xtensa_wur_ua_state_3, "vUi", "n") +BUILTIN(__builtin_xtensa_mv_qr, "vUiUi", "n") \ No newline at end of file diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 3eaec26c6bd166..9d0ebad6a448b3 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -6285,6 +6285,234 @@ bool Sema::CheckXtensaBuiltinFunctionCall(unsigned BuiltinID, return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || SemaBuiltinConstantArgRange(TheCall, 2, 0, 1) || SemaBuiltinConstantArgRange(TheCall, 3, 2, 3); + case Xtensa::BI__builtin_xtensa_ee_andq: + case Xtensa::BI__builtin_xtensa_ee_cmul_s16: + case Xtensa::BI__builtin_xtensa_ee_fft_cmul_s16_st_xp: + case Xtensa::BI__builtin_xtensa_ee_fft_r2bf_s16_st_incp: + case Xtensa::BI__builtin_xtensa_ee_orq: + case Xtensa::BI__builtin_xtensa_ee_src_q: + case Xtensa::BI__builtin_xtensa_ee_src_q_qup: + case Xtensa::BI__builtin_xtensa_ee_vadds_s16: + case Xtensa::BI__builtin_xtensa_ee_vadds_s32: + case Xtensa::BI__builtin_xtensa_ee_vadds_s8: + case Xtensa::BI__builtin_xtensa_ee_vcmp_eq_s16: + case Xtensa::BI__builtin_xtensa_ee_vcmp_eq_s32: + case Xtensa::BI__builtin_xtensa_ee_vcmp_eq_s8: + case Xtensa::BI__builtin_xtensa_ee_vcmp_gt_s16: + case Xtensa::BI__builtin_xtensa_ee_vcmp_gt_s32: + case Xtensa::BI__builtin_xtensa_ee_vcmp_gt_s8: + case Xtensa::BI__builtin_xtensa_ee_vcmp_lt_s16: + case Xtensa::BI__builtin_xtensa_ee_vcmp_lt_s32: + case Xtensa::BI__builtin_xtensa_ee_vcmp_lt_s8: + case Xtensa::BI__builtin_xtensa_ee_vmax_s16: + case Xtensa::BI__builtin_xtensa_ee_vmax_s32: + case Xtensa::BI__builtin_xtensa_ee_vmax_s8: + case Xtensa::BI__builtin_xtensa_ee_vmin_s16: + case Xtensa::BI__builtin_xtensa_ee_vmin_s32: + case Xtensa::BI__builtin_xtensa_ee_vmin_s8: + case Xtensa::BI__builtin_xtensa_ee_vmul_s16: + case Xtensa::BI__builtin_xtensa_ee_vmul_s8: + case Xtensa::BI__builtin_xtensa_ee_vmul_u16: + case Xtensa::BI__builtin_xtensa_ee_vmul_u8: + case Xtensa::BI__builtin_xtensa_ee_vprelu_s16: + case Xtensa::BI__builtin_xtensa_ee_vprelu_s8: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s16: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s32: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s8: + case Xtensa::BI__builtin_xtensa_ee_xorq: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 1, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 2, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_bitrev: + case Xtensa::BI__builtin_xtensa_ee_fft_vst_r32_decp: + case Xtensa::BI__builtin_xtensa_ee_ld_128_usar_ip: + case Xtensa::BI__builtin_xtensa_ee_ld_128_usar_xp: + case Xtensa::BI__builtin_xtensa_ee_movi_32_a: + case Xtensa::BI__builtin_xtensa_ee_movi_32_q: + case Xtensa::BI__builtin_xtensa_ee_mov_s16_qacc: + case Xtensa::BI__builtin_xtensa_ee_mov_s8_qacc: + case Xtensa::BI__builtin_xtensa_ee_mov_u16_qacc: + case Xtensa::BI__builtin_xtensa_ee_mov_u8_qacc: + case Xtensa::BI__builtin_xtensa_ee_srcmb_s16_qacc: + case Xtensa::BI__builtin_xtensa_ee_srcmb_s8_qacc: + case Xtensa::BI__builtin_xtensa_ee_vldbc_16: + case Xtensa::BI__builtin_xtensa_ee_vldbc_16_ip: + case Xtensa::BI__builtin_xtensa_ee_vldbc_16_xp: + case Xtensa::BI__builtin_xtensa_ee_vldbc_32: + case Xtensa::BI__builtin_xtensa_ee_vldbc_32_ip: + case Xtensa::BI__builtin_xtensa_ee_vldbc_32_xp: + case Xtensa::BI__builtin_xtensa_ee_vldbc_8: + case Xtensa::BI__builtin_xtensa_ee_vldbc_8_ip: + case Xtensa::BI__builtin_xtensa_ee_vldbc_8_xp: + case Xtensa::BI__builtin_xtensa_ee_vld_128_ip: + case Xtensa::BI__builtin_xtensa_ee_vld_128_xp: + case Xtensa::BI__builtin_xtensa_ee_vld_h_64_ip: + case Xtensa::BI__builtin_xtensa_ee_vld_h_64_xp: + case Xtensa::BI__builtin_xtensa_ee_vld_l_64_ip: + case Xtensa::BI__builtin_xtensa_ee_vld_l_64_xp: + case Xtensa::BI__builtin_xtensa_ee_vrelu_s16: + case Xtensa::BI__builtin_xtensa_ee_vrelu_s8: + case Xtensa::BI__builtin_xtensa_ee_vst_128_ip: + case Xtensa::BI__builtin_xtensa_ee_vst_128_xp: + case Xtensa::BI__builtin_xtensa_ee_vst_h_64_ip: + case Xtensa::BI__builtin_xtensa_ee_vst_h_64_xp: + case Xtensa::BI__builtin_xtensa_ee_vst_l_64_ip: + case Xtensa::BI__builtin_xtensa_ee_vst_l_64_xp: + case Xtensa::BI__builtin_xtensa_ee_zero_q: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_cmul_s16_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_cmul_s16_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vadds_s16_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vadds_s16_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vadds_s32_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vadds_s32_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vadds_s8_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vadds_s8_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmax_s16_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmax_s16_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmax_s32_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmax_s32_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmax_s8_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmax_s8_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmin_s16_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmin_s16_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmin_s32_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmin_s32_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmin_s8_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmin_s8_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmul_s16_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmul_s16_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmul_s8_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmul_s8_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmul_u16_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmul_u16_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vmul_u8_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vmul_u8_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s16_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s16_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s32_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s32_st_incp: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s8_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vsubs_s8_st_incp: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 2, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 3, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 4, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_fft_ams_s16_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_fft_ams_s16_ld_incp_uaup: + case Xtensa::BI__builtin_xtensa_ee_fft_ams_s16_ld_r32_decp: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 2, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 3, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 4, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 5, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 6, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_fft_ams_s16_st_incp: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 1, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 4, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 5, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 6, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_fft_cmul_s16_ld_xp: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 3, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 4, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 5, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_fft_r2bf_s16: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 1, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 2, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 3, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_ldxq_32: + case Xtensa::BI__builtin_xtensa_ee_notq: + case Xtensa::BI__builtin_xtensa_ee_slci_2q: + case Xtensa::BI__builtin_xtensa_ee_slcxxp_2q: + case Xtensa::BI__builtin_xtensa_ee_srci_2q: + case Xtensa::BI__builtin_xtensa_ee_srcq_128_st_incp: + case Xtensa::BI__builtin_xtensa_ee_srcxxp_2q: + case Xtensa::BI__builtin_xtensa_ee_stxq_32: + case Xtensa::BI__builtin_xtensa_ee_vldhbc_16_incp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_accx: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_qacc: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_accx: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_qacc: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_accx: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_qacc: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_accx: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_qacc: + case Xtensa::BI__builtin_xtensa_ee_vsl_32: + case Xtensa::BI__builtin_xtensa_ee_vsmulas_s16_qacc: + case Xtensa::BI__builtin_xtensa_ee_vsmulas_s8_qacc: + case Xtensa::BI__builtin_xtensa_ee_vsr_32: + case Xtensa::BI__builtin_xtensa_ee_vunzip_16: + case Xtensa::BI__builtin_xtensa_ee_vunzip_32: + case Xtensa::BI__builtin_xtensa_ee_vunzip_8: + case Xtensa::BI__builtin_xtensa_ee_vzip_16: + case Xtensa::BI__builtin_xtensa_ee_vzip_32: + case Xtensa::BI__builtin_xtensa_ee_vzip_8: + case Xtensa::BI__builtin_xtensa_mv_qr: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 1, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_src_q_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_src_q_ld_xp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_accx_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_accx_ld_xp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_qacc_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_qacc_ld_xp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_accx_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_accx_ld_xp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_qacc_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_qacc_ld_xp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_accx_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_accx_ld_xp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_qacc_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_qacc_ld_xp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_accx_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_accx_ld_xp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_qacc_ld_ip: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_qacc_ld_xp: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 3, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 4, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_accx_ld_ip_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_accx_ld_xp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_qacc_ld_ip_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_qacc_ld_xp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_accx_ld_ip_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_accx_ld_xp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_qacc_ld_ip_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_qacc_ld_xp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_accx_ld_ip_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_accx_ld_xp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_qacc_ld_ip_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_qacc_ld_xp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_accx_ld_ip_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_accx_ld_xp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_qacc_ld_ip_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_qacc_ld_xp_qup: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 3, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 4, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 5, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 6, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_qacc_ldbc_incp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_qacc_ldbc_incp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_qacc_ldbc_incp: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_qacc_ldbc_incp: + case Xtensa::BI__builtin_xtensa_ee_vsmulas_s16_qacc_ld_incp: + case Xtensa::BI__builtin_xtensa_ee_vsmulas_s8_qacc_ld_incp: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 2, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 3, 0, 7); + case Xtensa::BI__builtin_xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup: + case Xtensa::BI__builtin_xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup: + return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 2, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 3, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 4, 0, 7) && + SemaBuiltinConstantArgRange(TheCall, 5, 0, 7); } return SemaBuiltinConstantArgRange(TheCall, i, l, u); } diff --git a/clang/test/CodeGen/Xtensa/xtensa-ee-intrinsics.c b/clang/test/CodeGen/Xtensa/xtensa-ee-intrinsics.c new file mode 100644 index 00000000000000..c3ce2e107d8867 --- /dev/null +++ b/clang/test/CodeGen/Xtensa/xtensa-ee-intrinsics.c @@ -0,0 +1,514 @@ +// RUN: %clang_cc1 -no-opaque-pointers -triple xtensa -S -emit-llvm -O0 -o - %s \ +// RUN: | FileCheck %s + +#include + +void test() { + // CHECK: void @test() + uint32_t data = 10; + float a, b, c, d; + __builtin_xtensa_ee_andq(0, 4, 3); + // CHECK: call void @llvm.xtensa.ee.andq + __builtin_xtensa_ee_bitrev(5, data); + // CHECK: call void @llvm.xtensa.ee.bitrev + __builtin_xtensa_ee_cmul_s16(6, 1, 1, 1); + // CHECK: call void @llvm.xtensa.ee.cmul.s16 + __builtin_xtensa_ee_cmul_s16_ld_incp(7, data, 3, 4, 7, 1); + // CHECK: call void @llvm.xtensa.ee.cmul.s16.ld.incp + __builtin_xtensa_ee_cmul_s16_st_incp(0, data, 1, 7, 3, 3); + // CHECK: call void @llvm.xtensa.ee.cmul.s16.st.incp + __builtin_xtensa_ee_fft_ams_s16_ld_incp(0, data, 4, 7, 7, 5, 5, 1); + // CHECK: call void @llvm.xtensa.ee.fft.ams.s16.ld.incp + __builtin_xtensa_ee_fft_ams_s16_ld_incp_uaup(1, data, 5, 2, 7, 3, 4, 0); + // CHECK: call void @llvm.xtensa.ee.fft.ams.s16.ld.incp.uaup + __builtin_xtensa_ee_fft_ams_s16_ld_r32_decp(4, data, 2, 4, 5, 0, 0, 1); + // CHECK: call void @llvm.xtensa.ee.fft.ams.s16.ld.r32.decp + __builtin_xtensa_ee_fft_ams_s16_st_incp(4, 5, data, data, 5, 6, 1, 1); + // CHECK: call void @llvm.xtensa.ee.fft.ams.s16.st.incp + __builtin_xtensa_ee_fft_cmul_s16_ld_xp(0, data, data, 4, 4, 0, 2); + // CHECK: call void @llvm.xtensa.ee.fft.cmul.s16.ld.xp + __builtin_xtensa_ee_fft_cmul_s16_st_xp(1, 1, 5, data, data, 6, 0, 0); + // CHECK: call void @llvm.xtensa.ee.fft.cmul.s16.st.xp + __builtin_xtensa_ee_fft_r2bf_s16(6, 0, 7, 1, 1); + // CHECK: call void @llvm.xtensa.ee.fft.r2bf.s16 + __builtin_xtensa_ee_fft_r2bf_s16_st_incp(4, 6, 3, data, 3); + // CHECK: call void @llvm.xtensa.ee.fft.r2bf.s16.st.incp + __builtin_xtensa_ee_fft_vst_r32_decp(6, data, 0); + // CHECK: call void @llvm.xtensa.ee.fft.vst.r32.decp + __builtin_xtensa_ee_ldf_128_ip(a, b, d, d, data, 46); + // CHECK: call void @llvm.xtensa.ee.ldf.128.ip + __builtin_xtensa_ee_ldf_128_xp(b, b, d, b, data, data); + // CHECK: call void @llvm.xtensa.ee.ldf.128.xp + __builtin_xtensa_ee_ldf_64_ip(b, d, data, -962); + // CHECK: call void @llvm.xtensa.ee.ldf.64.ip + __builtin_xtensa_ee_ldf_64_xp(d, c, data, data); + // CHECK: call void @llvm.xtensa.ee.ldf.64.xp + __builtin_xtensa_ee_ldqa_s16_128_ip(data, 1790); + // CHECK: call void @llvm.xtensa.ee.ldqa.s16.128.ip + __builtin_xtensa_ee_ldqa_s16_128_xp(data, data); + // CHECK: call void @llvm.xtensa.ee.ldqa.s16.128.xp + __builtin_xtensa_ee_ldqa_s8_128_ip(data, -331); + // CHECK: call void @llvm.xtensa.ee.ldqa.s8.128.ip + __builtin_xtensa_ee_ldqa_s8_128_xp(data, data); + // CHECK: call void @llvm.xtensa.ee.ldqa.s8.128.xp + __builtin_xtensa_ee_ldqa_u16_128_ip(data, -1341); + // CHECK: call void @llvm.xtensa.ee.ldqa.u16.128.ip + __builtin_xtensa_ee_ldqa_u16_128_xp(data, data); + // CHECK: call void @llvm.xtensa.ee.ldqa.u16.128.xp + __builtin_xtensa_ee_ldqa_u8_128_ip(data, -1372); + // CHECK: call void @llvm.xtensa.ee.ldqa.u8.128.ip + __builtin_xtensa_ee_ldqa_u8_128_xp(data, data); + // CHECK: call void @llvm.xtensa.ee.ldqa.u8.128.xp + __builtin_xtensa_ee_ldxq_32(3, 3, data, 2, 2); + // CHECK: call void @llvm.xtensa.ee.ldxq.32 + __builtin_xtensa_ee_ld_128_usar_ip(0, data, 344); + // CHECK: call void @llvm.xtensa.ee.ld.128.usar.ip + __builtin_xtensa_ee_ld_128_usar_xp(7, data, data); + // CHECK: call void @llvm.xtensa.ee.ld.128.usar.xp + __builtin_xtensa_ee_ld_accx_ip(data, 144); + // CHECK: call void @llvm.xtensa.ee.ld.accx.ip + __builtin_xtensa_ee_ld_qacc_h_h_32_ip(data, 355); + // CHECK: call void @llvm.xtensa.ee.ld.qacc.h.h.32.ip + __builtin_xtensa_ee_ld_qacc_h_l_128_ip(data, 1267); + // CHECK: call void @llvm.xtensa.ee.ld.qacc.h.l.128.ip + __builtin_xtensa_ee_ld_qacc_l_h_32_ip(data, 220); + // CHECK: call void @llvm.xtensa.ee.ld.qacc.l.h.32.ip + __builtin_xtensa_ee_ld_qacc_l_l_128_ip(data, 1453); + // CHECK: call void @llvm.xtensa.ee.ld.qacc.l.l.128.ip + __builtin_xtensa_ee_ld_ua_state_ip(data, -1314); + // CHECK: call void @llvm.xtensa.ee.ld.ua.state.ip + __builtin_xtensa_ee_movi_32_a(1, data, 0); + // CHECK: call void @llvm.xtensa.ee.movi.32.a + __builtin_xtensa_ee_movi_32_q(4, data, 3); + // CHECK: call void @llvm.xtensa.ee.movi.32.q + __builtin_xtensa_ee_mov_s16_qacc(0); + // CHECK: call void @llvm.xtensa.ee.mov.s16.qacc + __builtin_xtensa_ee_mov_s8_qacc(7); + // CHECK: call void @llvm.xtensa.ee.mov.s8.qacc + __builtin_xtensa_ee_mov_u16_qacc(0); + // CHECK: call void @llvm.xtensa.ee.mov.u16.qacc + __builtin_xtensa_ee_mov_u8_qacc(1); + // CHECK: call void @llvm.xtensa.ee.mov.u8.qacc + __builtin_xtensa_ee_notq(0, 2); + // CHECK: call void @llvm.xtensa.ee.notq + __builtin_xtensa_ee_orq(6, 2, 7); + // CHECK: call void @llvm.xtensa.ee.orq + __builtin_xtensa_ee_slci_2q(4, 3, 8); + // CHECK: call void @llvm.xtensa.ee.slci.2q + __builtin_xtensa_ee_slcxxp_2q(2, 5, data, data); + // CHECK: call void @llvm.xtensa.ee.slcxxp.2q + __builtin_xtensa_ee_srci_2q(0, 6, 13); + // CHECK: call void @llvm.xtensa.ee.srci.2q + __builtin_xtensa_ee_srcmb_s16_qacc(3, data, 1); + // CHECK: call void @llvm.xtensa.ee.srcmb.s16.qacc + __builtin_xtensa_ee_srcmb_s8_qacc(3, data, 1); + // CHECK: call void @llvm.xtensa.ee.srcmb.s8.qacc + __builtin_xtensa_ee_srcq_128_st_incp(0, 7, data); + // CHECK: call void @llvm.xtensa.ee.srcq.128.st.incp + __builtin_xtensa_ee_srcxxp_2q(1, 3, data, data); + // CHECK: call void @llvm.xtensa.ee.srcxxp.2q + __builtin_xtensa_ee_src_q(3, 4, 7); + // CHECK: call void @llvm.xtensa.ee.src.q + __builtin_xtensa_ee_src_q_ld_ip(4, data, -1149, 4, 7); + // CHECK: call void @llvm.xtensa.ee.src.q.ld.ip + __builtin_xtensa_ee_src_q_ld_xp(4, data, data, 7, 2); + // CHECK: call void @llvm.xtensa.ee.src.q.ld.xp + __builtin_xtensa_ee_src_q_qup(4, 5, 7); + // CHECK: call void @llvm.xtensa.ee.src.q.qup + __builtin_xtensa_ee_srs_accx(data, data, 0); + // CHECK: call void @llvm.xtensa.ee.srs.accx + __builtin_xtensa_ee_stf_128_ip(c, a, b, c, data, 14); + // CHECK: call void @llvm.xtensa.ee.stf.128.ip + __builtin_xtensa_ee_stf_128_xp(b, b, d, d, data, data); + // CHECK: call void @llvm.xtensa.ee.stf.128.xp + __builtin_xtensa_ee_stf_64_ip(d, c, data, 984); + // CHECK: call void @llvm.xtensa.ee.stf.64.ip + __builtin_xtensa_ee_stf_64_xp(d, b, data, data); + // CHECK: call void @llvm.xtensa.ee.stf.64.xp + __builtin_xtensa_ee_stxq_32(1, 0, data, 2, 6); + // CHECK: call void @llvm.xtensa.ee.stxq.32 + __builtin_xtensa_ee_st_accx_ip(data, 842); + // CHECK: call void @llvm.xtensa.ee.st.accx.ip + __builtin_xtensa_ee_st_qacc_h_h_32_ip(data, -243); + // CHECK: call void @llvm.xtensa.ee.st.qacc.h.h.32.ip + __builtin_xtensa_ee_st_qacc_h_l_128_ip(data, 663); + // CHECK: call void @llvm.xtensa.ee.st.qacc.h.l.128.ip + __builtin_xtensa_ee_st_qacc_l_h_32_ip(data, 97); + // CHECK: call void @llvm.xtensa.ee.st.qacc.l.h.32.ip + __builtin_xtensa_ee_st_qacc_l_l_128_ip(data, -864); + // CHECK: call void @llvm.xtensa.ee.st.qacc.l.l.128.ip + __builtin_xtensa_ee_st_ua_state_ip(data, -709); + // CHECK: call void @llvm.xtensa.ee.st.ua.state.ip + __builtin_xtensa_ee_vadds_s16(7, 5, 2); + // CHECK: call void @llvm.xtensa.ee.vadds.s16 + __builtin_xtensa_ee_vadds_s16_ld_incp(4, data, 6, 1, 6); + // CHECK: call void @llvm.xtensa.ee.vadds.s16.ld.incp + __builtin_xtensa_ee_vadds_s16_st_incp(4, data, 1, 3, 2); + // CHECK: call void @llvm.xtensa.ee.vadds.s16.st.incp + __builtin_xtensa_ee_vadds_s32(7, 0, 6); + // CHECK: call void @llvm.xtensa.ee.vadds.s32 + __builtin_xtensa_ee_vadds_s32_ld_incp(4, data, 4, 7, 1); + // CHECK: call void @llvm.xtensa.ee.vadds.s32.ld.incp + __builtin_xtensa_ee_vadds_s32_st_incp(1, data, 7, 4, 4); + // CHECK: call void @llvm.xtensa.ee.vadds.s32.st.incp + __builtin_xtensa_ee_vadds_s8(0, 3, 6); + // CHECK: call void @llvm.xtensa.ee.vadds.s8 + __builtin_xtensa_ee_vadds_s8_ld_incp(3, data, 2, 4, 2); + // CHECK: call void @llvm.xtensa.ee.vadds.s8.ld.incp + __builtin_xtensa_ee_vadds_s8_st_incp(2, data, 1, 7, 2); + // CHECK: call void @llvm.xtensa.ee.vadds.s8.st.incp + __builtin_xtensa_ee_vcmp_eq_s16(2, 1, 0); + // CHECK: call void @llvm.xtensa.ee.vcmp.eq.s16 + __builtin_xtensa_ee_vcmp_eq_s32(6, 1, 2); + // CHECK: call void @llvm.xtensa.ee.vcmp.eq.s32 + __builtin_xtensa_ee_vcmp_eq_s8(0, 2, 1); + // CHECK: call void @llvm.xtensa.ee.vcmp.eq.s8 + __builtin_xtensa_ee_vcmp_gt_s16(1, 2, 5); + // CHECK: call void @llvm.xtensa.ee.vcmp.gt.s16 + __builtin_xtensa_ee_vcmp_gt_s32(0, 0, 0); + // CHECK: call void @llvm.xtensa.ee.vcmp.gt.s32 + __builtin_xtensa_ee_vcmp_gt_s8(4, 1, 4); + // CHECK: call void @llvm.xtensa.ee.vcmp.gt.s8 + __builtin_xtensa_ee_vcmp_lt_s16(7, 4, 0); + // CHECK: call void @llvm.xtensa.ee.vcmp.lt.s16 + __builtin_xtensa_ee_vcmp_lt_s32(0, 1, 0); + // CHECK: call void @llvm.xtensa.ee.vcmp.lt.s32 + __builtin_xtensa_ee_vcmp_lt_s8(3, 3, 3); + // CHECK: call void @llvm.xtensa.ee.vcmp.lt.s8 + __builtin_xtensa_ee_vldbc_16(6, data); + // CHECK: call void @llvm.xtensa.ee.vldbc.16 + __builtin_xtensa_ee_vldbc_16_ip(3, data, 115); + // CHECK: call void @llvm.xtensa.ee.vldbc.16.ip + __builtin_xtensa_ee_vldbc_16_xp(0, data, data); + // CHECK: call void @llvm.xtensa.ee.vldbc.16.xp + __builtin_xtensa_ee_vldbc_32(4, data); + // CHECK: call void @llvm.xtensa.ee.vldbc.32 + __builtin_xtensa_ee_vldbc_32_ip(5, data, -213); + // CHECK: call void @llvm.xtensa.ee.vldbc.32.ip + __builtin_xtensa_ee_vldbc_32_xp(1, data, data); + // CHECK: call void @llvm.xtensa.ee.vldbc.32.xp + __builtin_xtensa_ee_vldbc_8(5, data); + // CHECK: call void @llvm.xtensa.ee.vldbc.8 + __builtin_xtensa_ee_vldbc_8_ip(7, data, 32); + // CHECK: call void @llvm.xtensa.ee.vldbc.8.ip + __builtin_xtensa_ee_vldbc_8_xp(6, data, data); + // CHECK: call void @llvm.xtensa.ee.vldbc.8.xp + __builtin_xtensa_ee_vldhbc_16_incp(1, 1, data); + // CHECK: call void @llvm.xtensa.ee.vldhbc.16.incp + __builtin_xtensa_ee_vld_128_ip(6, data, 1284); + // CHECK: call void @llvm.xtensa.ee.vld.128.ip + __builtin_xtensa_ee_vld_128_xp(4, data, data); + // CHECK: call void @llvm.xtensa.ee.vld.128.xp + __builtin_xtensa_ee_vld_h_64_ip(1, data, 400); + // CHECK: call void @llvm.xtensa.ee.vld.h.64.ip + __builtin_xtensa_ee_vld_h_64_xp(1, data, data); + // CHECK: call void @llvm.xtensa.ee.vld.h.64.xp + __builtin_xtensa_ee_vld_l_64_ip(0, data, 907); + // CHECK: call void @llvm.xtensa.ee.vld.l.64.ip + __builtin_xtensa_ee_vld_l_64_xp(0, data, data); + // CHECK: call void @llvm.xtensa.ee.vld.l.64.xp + __builtin_xtensa_ee_vmax_s16(4, 1, 0); + // CHECK: call void @llvm.xtensa.ee.vmax.s16 + __builtin_xtensa_ee_vmax_s16_ld_incp(3, data, 0, 3, 6); + // CHECK: call void @llvm.xtensa.ee.vmax.s16.ld.incp + __builtin_xtensa_ee_vmax_s16_st_incp(7, data, 2, 0, 2); + // CHECK: call void @llvm.xtensa.ee.vmax.s16.st.incp + __builtin_xtensa_ee_vmax_s32(1, 4, 0); + // CHECK: call void @llvm.xtensa.ee.vmax.s32 + __builtin_xtensa_ee_vmax_s32_ld_incp(6, data, 1, 7, 5); + // CHECK: call void @llvm.xtensa.ee.vmax.s32.ld.incp + __builtin_xtensa_ee_vmax_s32_st_incp(5, data, 4, 6, 4); + // CHECK: call void @llvm.xtensa.ee.vmax.s32.st.incp + __builtin_xtensa_ee_vmax_s8(2, 4, 6); + // CHECK: call void @llvm.xtensa.ee.vmax.s8 + __builtin_xtensa_ee_vmax_s8_ld_incp(7, data, 7, 3, 3); + // CHECK: call void @llvm.xtensa.ee.vmax.s8.ld.incp + __builtin_xtensa_ee_vmax_s8_st_incp(0, data, 3, 5, 1); + // CHECK: call void @llvm.xtensa.ee.vmax.s8.st.incp + __builtin_xtensa_ee_vmin_s16(7, 4, 3); + // CHECK: call void @llvm.xtensa.ee.vmin.s16 + __builtin_xtensa_ee_vmin_s16_ld_incp(2, data, 5, 2, 1); + // CHECK: call void @llvm.xtensa.ee.vmin.s16.ld.incp + __builtin_xtensa_ee_vmin_s16_st_incp(4, data, 4, 2, 0); + // CHECK: call void @llvm.xtensa.ee.vmin.s16.st.incp + __builtin_xtensa_ee_vmin_s32(4, 6, 5); + // CHECK: call void @llvm.xtensa.ee.vmin.s32 + __builtin_xtensa_ee_vmin_s32_ld_incp(1, data, 3, 3, 5); + // CHECK: call void @llvm.xtensa.ee.vmin.s32.ld.incp + __builtin_xtensa_ee_vmin_s32_st_incp(3, data, 1, 0, 6); + // CHECK: call void @llvm.xtensa.ee.vmin.s32.st.incp + __builtin_xtensa_ee_vmin_s8(5, 1, 3); + // CHECK: call void @llvm.xtensa.ee.vmin.s8 + __builtin_xtensa_ee_vmin_s8_ld_incp(0, data, 7, 2, 5); + // CHECK: call void @llvm.xtensa.ee.vmin.s8.ld.incp + __builtin_xtensa_ee_vmin_s8_st_incp(0, data, 5, 3, 7); + // CHECK: call void @llvm.xtensa.ee.vmin.s8.st.incp + __builtin_xtensa_ee_vmulas_s16_accx(4, 1); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.accx + __builtin_xtensa_ee_vmulas_s16_accx_ld_ip(7, data, 26, 1, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip + __builtin_xtensa_ee_vmulas_s16_accx_ld_ip_qup(0, data, 7, 2, 3, 3, 7); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip.qup + __builtin_xtensa_ee_vmulas_s16_accx_ld_xp(6, data, data, 0, 3); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.accx.ld.xp + __builtin_xtensa_ee_vmulas_s16_accx_ld_xp_qup(7, data, data, 2, 4, 7, 2); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.accx.ld.xp.qup + __builtin_xtensa_ee_vmulas_s16_qacc(7, 7); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.qacc + __builtin_xtensa_ee_vmulas_s16_qacc_ldbc_incp(6, data, 1, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.qacc.ldbc.incp + __builtin_xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup(5, data, 4, 5, 3, 1); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.qacc.ldbc.incp.qup + __builtin_xtensa_ee_vmulas_s16_qacc_ld_ip(1, data, 35, 2, 2); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.qacc.ld.ip + __builtin_xtensa_ee_vmulas_s16_qacc_ld_ip_qup(1, data, 24, 0, 1, 1, 7); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.qacc.ld.ip.qup + __builtin_xtensa_ee_vmulas_s16_qacc_ld_xp(4, data, data, 5, 3); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.qacc.ld.xp + __builtin_xtensa_ee_vmulas_s16_qacc_ld_xp_qup(2, data, data, 3, 3, 1, 2); + // CHECK: call void @llvm.xtensa.ee.vmulas.s16.qacc.ld.xp.qup + __builtin_xtensa_ee_vmulas_s8_accx(5, 5); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.accx + __builtin_xtensa_ee_vmulas_s8_accx_ld_ip(0, data, -30, 1, 5); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.accx.ld.ip + __builtin_xtensa_ee_vmulas_s8_accx_ld_ip_qup(2, data, -1, 5, 0, 4, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.accx.ld.ip.qup + __builtin_xtensa_ee_vmulas_s8_accx_ld_xp(1, data, data, 4, 5); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.accx.ld.xp + __builtin_xtensa_ee_vmulas_s8_accx_ld_xp_qup(4, data, data, 5, 7, 7, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.accx.ld.xp.qup + __builtin_xtensa_ee_vmulas_s8_qacc(6, 7); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.qacc + __builtin_xtensa_ee_vmulas_s8_qacc_ldbc_incp(3, data, 6, 4); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.qacc.ldbc.incp + __builtin_xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup(7, data, 2, 3, 4, 1); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.qacc.ldbc.incp.qup + __builtin_xtensa_ee_vmulas_s8_qacc_ld_ip(4, data, -99, 2, 4); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.qacc.ld.ip + __builtin_xtensa_ee_vmulas_s8_qacc_ld_ip_qup(4, data, -87, 5, 4, 2, 3); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.qacc.ld.ip.qup + __builtin_xtensa_ee_vmulas_s8_qacc_ld_xp(7, data, data, 1, 1); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.qacc.ld.xp + __builtin_xtensa_ee_vmulas_s8_qacc_ld_xp_qup(2, data, data, 1, 6, 3, 2); + // CHECK: call void @llvm.xtensa.ee.vmulas.s8.qacc.ld.xp.qup + __builtin_xtensa_ee_vmulas_u16_accx(2, 5); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.accx + __builtin_xtensa_ee_vmulas_u16_accx_ld_ip(0, data, -28, 6, 7); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.accx.ld.ip + __builtin_xtensa_ee_vmulas_u16_accx_ld_ip_qup(5, data, -41, 2, 1, 6, 6); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.accx.ld.ip.qup + __builtin_xtensa_ee_vmulas_u16_accx_ld_xp(1, data, data, 6, 7); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.accx.ld.xp + __builtin_xtensa_ee_vmulas_u16_accx_ld_xp_qup(7, data, data, 0, 0, 7, 5); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.accx.ld.xp.qup + __builtin_xtensa_ee_vmulas_u16_qacc(4, 3); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.qacc + __builtin_xtensa_ee_vmulas_u16_qacc_ldbc_incp(3, data, 5, 6); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.qacc.ldbc.incp + __builtin_xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup(3, data, 4, 5, 4, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.qacc.ldbc.incp.qup + __builtin_xtensa_ee_vmulas_u16_qacc_ld_ip(4, data, -94, 5, 3); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.qacc.ld.ip + __builtin_xtensa_ee_vmulas_u16_qacc_ld_ip_qup(7, data, -116, 5, 6, 1, 4); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.qacc.ld.ip.qup + __builtin_xtensa_ee_vmulas_u16_qacc_ld_xp(3, data, data, 0, 6); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.qacc.ld.xp + __builtin_xtensa_ee_vmulas_u16_qacc_ld_xp_qup(0, data, data, 5, 3, 3, 7); + // CHECK: call void @llvm.xtensa.ee.vmulas.u16.qacc.ld.xp.qup + __builtin_xtensa_ee_vmulas_u8_accx(3, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.accx + __builtin_xtensa_ee_vmulas_u8_accx_ld_ip(1, data, -112, 1, 5); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.accx.ld.ip + __builtin_xtensa_ee_vmulas_u8_accx_ld_ip_qup(4, data, -68, 3, 1, 5, 4); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.accx.ld.ip.qup + __builtin_xtensa_ee_vmulas_u8_accx_ld_xp(2, data, data, 0, 5); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.accx.ld.xp + __builtin_xtensa_ee_vmulas_u8_accx_ld_xp_qup(0, data, data, 3, 5, 3, 3); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.accx.ld.xp.qup + __builtin_xtensa_ee_vmulas_u8_qacc(4, 2); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.qacc + __builtin_xtensa_ee_vmulas_u8_qacc_ldbc_incp(6, data, 4, 7); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.qacc.ldbc.incp + __builtin_xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup(3, data, 3, 4, 4, 3); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.qacc.ldbc.incp.qup + __builtin_xtensa_ee_vmulas_u8_qacc_ld_ip(4, data, 46, 2, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.qacc.ld.ip + __builtin_xtensa_ee_vmulas_u8_qacc_ld_ip_qup(4, data, -51, 6, 2, 2, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.qacc.ld.ip.qup + __builtin_xtensa_ee_vmulas_u8_qacc_ld_xp(7, data, data, 1, 2); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.qacc.ld.xp + __builtin_xtensa_ee_vmulas_u8_qacc_ld_xp_qup(5, data, data, 0, 4, 5, 0); + // CHECK: call void @llvm.xtensa.ee.vmulas.u8.qacc.ld.xp.qup + __builtin_xtensa_ee_vmul_s16(4, 2, 5); + // CHECK: call void @llvm.xtensa.ee.vmul.s16 + __builtin_xtensa_ee_vmul_s16_ld_incp(2, data, 7, 0, 3); + // CHECK: call void @llvm.xtensa.ee.vmul.s16.ld.incp + __builtin_xtensa_ee_vmul_s16_st_incp(3, data, 5, 7, 6); + // CHECK: call void @llvm.xtensa.ee.vmul.s16.st.incp + __builtin_xtensa_ee_vmul_s8(1, 3, 6); + // CHECK: call void @llvm.xtensa.ee.vmul.s8 + __builtin_xtensa_ee_vmul_s8_ld_incp(3, data, 2, 2, 6); + // CHECK: call void @llvm.xtensa.ee.vmul.s8.ld.incp + __builtin_xtensa_ee_vmul_s8_st_incp(1, data, 2, 1, 4); + // CHECK: call void @llvm.xtensa.ee.vmul.s8.st.incp + __builtin_xtensa_ee_vmul_u16(6, 6, 2); + // CHECK: call void @llvm.xtensa.ee.vmul.u16 + __builtin_xtensa_ee_vmul_u16_ld_incp(0, data, 7, 0, 5); + // CHECK: call void @llvm.xtensa.ee.vmul.u16.ld.incp + __builtin_xtensa_ee_vmul_u16_st_incp(7, data, 4, 0, 2); + // CHECK: call void @llvm.xtensa.ee.vmul.u16.st.incp + __builtin_xtensa_ee_vmul_u8(1, 5, 7); + // CHECK: call void @llvm.xtensa.ee.vmul.u8 + __builtin_xtensa_ee_vmul_u8_ld_incp(1, data, 7, 4, 0); + // CHECK: call void @llvm.xtensa.ee.vmul.u8.ld.incp + __builtin_xtensa_ee_vmul_u8_st_incp(7, data, 0, 3, 4); + // CHECK: call void @llvm.xtensa.ee.vmul.u8.st.incp + __builtin_xtensa_ee_vprelu_s16(0, 0, 6, data); + // CHECK: call void @llvm.xtensa.ee.vprelu.s16 + __builtin_xtensa_ee_vprelu_s8(4, 7, 1, data); + // CHECK: call void @llvm.xtensa.ee.vprelu.s8 + __builtin_xtensa_ee_vrelu_s16(6, data, data); + // CHECK: call void @llvm.xtensa.ee.vrelu.s16 + __builtin_xtensa_ee_vrelu_s8(1, data, data); + // CHECK: call void @llvm.xtensa.ee.vrelu.s8 + __builtin_xtensa_ee_vsl_32(5, 1); + // CHECK: call void @llvm.xtensa.ee.vsl.32 + __builtin_xtensa_ee_vsmulas_s16_qacc(4, 6, 4); + // CHECK: call void @llvm.xtensa.ee.vsmulas.s16.qacc + __builtin_xtensa_ee_vsmulas_s16_qacc_ld_incp(4, data, 6, 6, 4); + // CHECK: call void @llvm.xtensa.ee.vsmulas.s16.qacc.ld.incp + __builtin_xtensa_ee_vsmulas_s8_qacc(3, 2, 9); + // CHECK: call void @llvm.xtensa.ee.vsmulas.s8.qacc + __builtin_xtensa_ee_vsmulas_s8_qacc_ld_incp(3, data, 2, 2, 5); + // CHECK: call void @llvm.xtensa.ee.vsmulas.s8.qacc.ld.incp + __builtin_xtensa_ee_vsr_32(3, 1); + // CHECK: call void @llvm.xtensa.ee.vsr.32 + __builtin_xtensa_ee_vst_128_ip(6, data, 68); + // CHECK: call void @llvm.xtensa.ee.vst.128.ip + __builtin_xtensa_ee_vst_128_xp(7, data, data); + // CHECK: call void @llvm.xtensa.ee.vst.128.xp + __builtin_xtensa_ee_vst_h_64_ip(2, data, 843); + // CHECK: call void @llvm.xtensa.ee.vst.h.64.ip + __builtin_xtensa_ee_vst_h_64_xp(5, data, data); + // CHECK: call void @llvm.xtensa.ee.vst.h.64.xp + __builtin_xtensa_ee_vst_l_64_ip(7, data, -658); + // CHECK: call void @llvm.xtensa.ee.vst.l.64.ip + __builtin_xtensa_ee_vst_l_64_xp(7, data, data); + // CHECK: call void @llvm.xtensa.ee.vst.l.64.xp + __builtin_xtensa_ee_vsubs_s16(7, 5, 3); + // CHECK: call void @llvm.xtensa.ee.vsubs.s16 + __builtin_xtensa_ee_vsubs_s16_ld_incp(7, data, 5, 1, 2); + // CHECK: call void @llvm.xtensa.ee.vsubs.s16.ld.incp + __builtin_xtensa_ee_vsubs_s16_st_incp(3, data, 5, 2, 3); + // CHECK: call void @llvm.xtensa.ee.vsubs.s16.st.incp + __builtin_xtensa_ee_vsubs_s32(0, 7, 3); + // CHECK: call void @llvm.xtensa.ee.vsubs.s32 + __builtin_xtensa_ee_vsubs_s32_ld_incp(0, data, 4, 1, 0); + // CHECK: call void @llvm.xtensa.ee.vsubs.s32.ld.incp + __builtin_xtensa_ee_vsubs_s32_st_incp(4, data, 6, 7, 6); + // CHECK: call void @llvm.xtensa.ee.vsubs.s32.st.incp + __builtin_xtensa_ee_vsubs_s8(4, 4, 0); + // CHECK: call void @llvm.xtensa.ee.vsubs.s8 + __builtin_xtensa_ee_vsubs_s8_ld_incp(1, data, 1, 4, 4); + // CHECK: call void @llvm.xtensa.ee.vsubs.s8.ld.incp + __builtin_xtensa_ee_vsubs_s8_st_incp(2, data, 4, 4, 1); + // CHECK: call void @llvm.xtensa.ee.vsubs.s8.st.incp + __builtin_xtensa_ee_vunzip_16(7, 6); + // CHECK: call void @llvm.xtensa.ee.vunzip.16 + __builtin_xtensa_ee_vunzip_32(7, 3); + // CHECK: call void @llvm.xtensa.ee.vunzip.32 + __builtin_xtensa_ee_vunzip_8(0, 2); + // CHECK: call void @llvm.xtensa.ee.vunzip.8 + __builtin_xtensa_ee_vzip_16(1, 1); + // CHECK: call void @llvm.xtensa.ee.vzip.16 + __builtin_xtensa_ee_vzip_32(0, 1); + // CHECK: call void @llvm.xtensa.ee.vzip.32 + __builtin_xtensa_ee_vzip_8(0, 5); + // CHECK: call void @llvm.xtensa.ee.vzip.8 + __builtin_xtensa_ee_xorq(4, 3, 3); + // CHECK: call void @llvm.xtensa.ee.xorq + __builtin_xtensa_ee_zero_accx(); + // CHECK: call void @llvm.xtensa.ee.zero.accx + __builtin_xtensa_ee_zero_q(0); + // CHECK: call void @llvm.xtensa.ee.zero.q + __builtin_xtensa_ee_zero_qacc(); + // CHECK: call void @llvm.xtensa.ee.zero.qacc + data = __builtin_xtensa_rur_accx_0(); + // CHECK: call i32 @llvm.xtensa.rur.accx.0 + data = __builtin_xtensa_rur_accx_1(); + // CHECK: call i32 @llvm.xtensa.rur.accx.1 + data = __builtin_xtensa_rur_fft_bit_width(); + // CHECK: call i32 @llvm.xtensa.rur.fft.bit.width + data = __builtin_xtensa_rur_gpio_out(); + // CHECK: call i32 @llvm.xtensa.rur.gpio.out + data = __builtin_xtensa_rur_qacc_h_0(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.h.0 + data = __builtin_xtensa_rur_qacc_h_1(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.h.1 + data = __builtin_xtensa_rur_qacc_h_2(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.h.2 + data = __builtin_xtensa_rur_qacc_h_3(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.h.3 + data = __builtin_xtensa_rur_qacc_h_4(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.h.4 + data = __builtin_xtensa_rur_qacc_l_0(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.l.0 + data = __builtin_xtensa_rur_qacc_l_1(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.l.1 + data = __builtin_xtensa_rur_qacc_l_2(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.l.2 + data = __builtin_xtensa_rur_qacc_l_3(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.l.3 + data = __builtin_xtensa_rur_qacc_l_4(); + // CHECK: call i32 @llvm.xtensa.rur.qacc.l.4 + data = __builtin_xtensa_rur_sar_byte(); + // CHECK: call i32 @llvm.xtensa.rur.sar.byte + data = __builtin_xtensa_rur_ua_state_0(); + // CHECK: call i32 @llvm.xtensa.rur.ua.state.0 + data = __builtin_xtensa_rur_ua_state_1(); + // CHECK: call i32 @llvm.xtensa.rur.ua.state.1 + data = __builtin_xtensa_rur_ua_state_2(); + // CHECK: call i32 @llvm.xtensa.rur.ua.state.2 + data = __builtin_xtensa_rur_ua_state_3(); + // CHECK: call i32 @llvm.xtensa.rur.ua.state.3 + __builtin_xtensa_wur_accx_0(data); + // CHECK: call void @llvm.xtensa.wur.accx.0 + __builtin_xtensa_wur_accx_1(data); + // CHECK: call void @llvm.xtensa.wur.accx.1 + __builtin_xtensa_wur_fft_bit_width(data); + // CHECK: call void @llvm.xtensa.wur.fft.bit.width + __builtin_xtensa_wur_gpio_out(data); + // CHECK: call void @llvm.xtensa.wur.gpio.out + __builtin_xtensa_wur_qacc_h_0(data); + // CHECK: call void @llvm.xtensa.wur.qacc.h.0 + __builtin_xtensa_wur_qacc_h_1(data); + // CHECK: call void @llvm.xtensa.wur.qacc.h.1 + __builtin_xtensa_wur_qacc_h_2(data); + // CHECK: call void @llvm.xtensa.wur.qacc.h.2 + __builtin_xtensa_wur_qacc_h_3(data); + // CHECK: call void @llvm.xtensa.wur.qacc.h.3 + __builtin_xtensa_wur_qacc_h_4(data); + // CHECK: call void @llvm.xtensa.wur.qacc.h.4 + __builtin_xtensa_wur_qacc_l_0(data); + // CHECK: call void @llvm.xtensa.wur.qacc.l.0 + __builtin_xtensa_wur_qacc_l_1(data); + // CHECK: call void @llvm.xtensa.wur.qacc.l.1 + __builtin_xtensa_wur_qacc_l_2(data); + // CHECK: call void @llvm.xtensa.wur.qacc.l.2 + __builtin_xtensa_wur_qacc_l_3(data); + // CHECK: call void @llvm.xtensa.wur.qacc.l.3 + __builtin_xtensa_wur_qacc_l_4(data); + // CHECK: call void @llvm.xtensa.wur.qacc.l.4 + __builtin_xtensa_wur_sar_byte(data); + // CHECK: call void @llvm.xtensa.wur.sar.byte + __builtin_xtensa_wur_ua_state_0(data); + // CHECK: call void @llvm.xtensa.wur.ua.state.0 + __builtin_xtensa_wur_ua_state_1(data); + // CHECK: call void @llvm.xtensa.wur.ua.state.1 + __builtin_xtensa_wur_ua_state_2(data); + // CHECK: call void @llvm.xtensa.wur.ua.state.2 + __builtin_xtensa_wur_ua_state_3(data); + // CHECK: call void @llvm.xtensa.wur.ua.state.3 + __builtin_xtensa_mv_qr(4, 5); + // CHECK: call void @llvm.xtensa.mv.qr +} diff --git a/llvm/include/llvm/IR/IntrinsicsXtensa.td b/llvm/include/llvm/IR/IntrinsicsXtensa.td index d7d25609b5d56f..046df476967f3a 100644 --- a/llvm/include/llvm/IR/IntrinsicsXtensa.td +++ b/llvm/include/llvm/IR/IntrinsicsXtensa.td @@ -248,4 +248,8 @@ def int_xtensa_rsr_m3: ClangBuiltin<"__builtin_xtensa_rsr_m3">, def int_xtensa_xsr_m3: ClangBuiltin<"__builtin_xtensa_xsr_m3">, Intrinsic<[], [llvm_ptr_ty], []>; -} + +// Generated code +// --------------- +include "llvm/IR/IntrinsicsXtensaESP32S3.td" +} \ No newline at end of file diff --git a/llvm/include/llvm/IR/IntrinsicsXtensaESP32S3.td b/llvm/include/llvm/IR/IntrinsicsXtensaESP32S3.td new file mode 100644 index 00000000000000..e42993fa027aa8 --- /dev/null +++ b/llvm/include/llvm/IR/IntrinsicsXtensaESP32S3.td @@ -0,0 +1,767 @@ +//===- IntrinsicsXtensa.td - Defines Xtensa intrinsics -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the Xtensa-specific intrinsics. +// Automatically generated file, do not edit! +//===----------------------------------------------------------------------===// + +def int_xtensa_ee_andq: ClangBuiltin<"__builtin_xtensa_ee_andq">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_bitrev: ClangBuiltin<"__builtin_xtensa_ee_bitrev">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_cmul_s16: ClangBuiltin<"__builtin_xtensa_ee_cmul_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_cmul_s16_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_cmul_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_cmul_s16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_cmul_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_ams_s16_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_fft_ams_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_ams_s16_ld_incp_uaup: ClangBuiltin<"__builtin_xtensa_ee_fft_ams_s16_ld_incp_uaup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_ams_s16_ld_r32_decp: ClangBuiltin<"__builtin_xtensa_ee_fft_ams_s16_ld_r32_decp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_ams_s16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_fft_ams_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_cmul_s16_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_fft_cmul_s16_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_cmul_s16_st_xp: ClangBuiltin<"__builtin_xtensa_ee_fft_cmul_s16_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_r2bf_s16: ClangBuiltin<"__builtin_xtensa_ee_fft_r2bf_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_r2bf_s16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_fft_r2bf_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_fft_vst_r32_decp: ClangBuiltin<"__builtin_xtensa_ee_fft_vst_r32_decp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_ldf_128_ip: ClangBuiltin<"__builtin_xtensa_ee_ldf_128_ip">, + Intrinsic<[], [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ldf_128_xp: ClangBuiltin<"__builtin_xtensa_ee_ldf_128_xp">, + Intrinsic<[], [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_ee_ldf_64_ip: ClangBuiltin<"__builtin_xtensa_ee_ldf_64_ip">, + Intrinsic<[], [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ldf_64_xp: ClangBuiltin<"__builtin_xtensa_ee_ldf_64_xp">, + Intrinsic<[], [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_ee_ldqa_s16_128_ip: ClangBuiltin<"__builtin_xtensa_ee_ldqa_s16_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ldqa_s16_128_xp: ClangBuiltin<"__builtin_xtensa_ee_ldqa_s16_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_ee_ldqa_s8_128_ip: ClangBuiltin<"__builtin_xtensa_ee_ldqa_s8_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ldqa_s8_128_xp: ClangBuiltin<"__builtin_xtensa_ee_ldqa_s8_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_ee_ldqa_u16_128_ip: ClangBuiltin<"__builtin_xtensa_ee_ldqa_u16_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ldqa_u16_128_xp: ClangBuiltin<"__builtin_xtensa_ee_ldqa_u16_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_ee_ldqa_u8_128_ip: ClangBuiltin<"__builtin_xtensa_ee_ldqa_u8_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ldqa_u8_128_xp: ClangBuiltin<"__builtin_xtensa_ee_ldqa_u8_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_ee_ldxq_32: ClangBuiltin<"__builtin_xtensa_ee_ldxq_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_ld_128_usar_ip: ClangBuiltin<"__builtin_xtensa_ee_ld_128_usar_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_ld_128_usar_xp: ClangBuiltin<"__builtin_xtensa_ee_ld_128_usar_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ld_accx_ip: ClangBuiltin<"__builtin_xtensa_ee_ld_accx_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ld_qacc_h_h_32_ip: ClangBuiltin<"__builtin_xtensa_ee_ld_qacc_h_h_32_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ld_qacc_h_l_128_ip: ClangBuiltin<"__builtin_xtensa_ee_ld_qacc_h_l_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ld_qacc_l_h_32_ip: ClangBuiltin<"__builtin_xtensa_ee_ld_qacc_l_h_32_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ld_qacc_l_l_128_ip: ClangBuiltin<"__builtin_xtensa_ee_ld_qacc_l_l_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_ld_ua_state_ip: ClangBuiltin<"__builtin_xtensa_ee_ld_ua_state_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_movi_32_a: ClangBuiltin<"__builtin_xtensa_ee_movi_32_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_movi_32_q: ClangBuiltin<"__builtin_xtensa_ee_movi_32_q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_mov_s16_qacc: ClangBuiltin<"__builtin_xtensa_ee_mov_s16_qacc">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_mov_s8_qacc: ClangBuiltin<"__builtin_xtensa_ee_mov_s8_qacc">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_mov_u16_qacc: ClangBuiltin<"__builtin_xtensa_ee_mov_u16_qacc">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_mov_u8_qacc: ClangBuiltin<"__builtin_xtensa_ee_mov_u8_qacc">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_notq: ClangBuiltin<"__builtin_xtensa_ee_notq">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_orq: ClangBuiltin<"__builtin_xtensa_ee_orq">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_slci_2q: ClangBuiltin<"__builtin_xtensa_ee_slci_2q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_slcxxp_2q: ClangBuiltin<"__builtin_xtensa_ee_slcxxp_2q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_srci_2q: ClangBuiltin<"__builtin_xtensa_ee_srci_2q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_srcmb_s16_qacc: ClangBuiltin<"__builtin_xtensa_ee_srcmb_s16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_srcmb_s8_qacc: ClangBuiltin<"__builtin_xtensa_ee_srcmb_s8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_srcq_128_st_incp: ClangBuiltin<"__builtin_xtensa_ee_srcq_128_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_srcxxp_2q: ClangBuiltin<"__builtin_xtensa_ee_srcxxp_2q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_src_q: ClangBuiltin<"__builtin_xtensa_ee_src_q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_src_q_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_src_q_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_src_q_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_src_q_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_src_q_qup: ClangBuiltin<"__builtin_xtensa_ee_src_q_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_srs_accx: ClangBuiltin<"__builtin_xtensa_ee_srs_accx">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_stf_128_ip: ClangBuiltin<"__builtin_xtensa_ee_stf_128_ip">, + Intrinsic<[], [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_stf_128_xp: ClangBuiltin<"__builtin_xtensa_ee_stf_128_xp">, + Intrinsic<[], [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_ee_stf_64_ip: ClangBuiltin<"__builtin_xtensa_ee_stf_64_ip">, + Intrinsic<[], [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_stf_64_xp: ClangBuiltin<"__builtin_xtensa_ee_stf_64_xp">, + Intrinsic<[], [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_xtensa_ee_stxq_32: ClangBuiltin<"__builtin_xtensa_ee_stxq_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_st_accx_ip: ClangBuiltin<"__builtin_xtensa_ee_st_accx_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_st_qacc_h_h_32_ip: ClangBuiltin<"__builtin_xtensa_ee_st_qacc_h_h_32_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_st_qacc_h_l_128_ip: ClangBuiltin<"__builtin_xtensa_ee_st_qacc_h_l_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_st_qacc_l_h_32_ip: ClangBuiltin<"__builtin_xtensa_ee_st_qacc_l_h_32_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_st_qacc_l_l_128_ip: ClangBuiltin<"__builtin_xtensa_ee_st_qacc_l_l_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_st_ua_state_ip: ClangBuiltin<"__builtin_xtensa_ee_st_ua_state_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vadds_s16: ClangBuiltin<"__builtin_xtensa_ee_vadds_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vadds_s16_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vadds_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vadds_s16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vadds_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vadds_s32: ClangBuiltin<"__builtin_xtensa_ee_vadds_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vadds_s32_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vadds_s32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vadds_s32_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vadds_s32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vadds_s8: ClangBuiltin<"__builtin_xtensa_ee_vadds_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vadds_s8_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vadds_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vadds_s8_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vadds_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_eq_s16: ClangBuiltin<"__builtin_xtensa_ee_vcmp_eq_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_eq_s32: ClangBuiltin<"__builtin_xtensa_ee_vcmp_eq_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_eq_s8: ClangBuiltin<"__builtin_xtensa_ee_vcmp_eq_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_gt_s16: ClangBuiltin<"__builtin_xtensa_ee_vcmp_gt_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_gt_s32: ClangBuiltin<"__builtin_xtensa_ee_vcmp_gt_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_gt_s8: ClangBuiltin<"__builtin_xtensa_ee_vcmp_gt_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_lt_s16: ClangBuiltin<"__builtin_xtensa_ee_vcmp_lt_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_lt_s32: ClangBuiltin<"__builtin_xtensa_ee_vcmp_lt_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vcmp_lt_s8: ClangBuiltin<"__builtin_xtensa_ee_vcmp_lt_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vldbc_16: ClangBuiltin<"__builtin_xtensa_ee_vldbc_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vldbc_16_ip: ClangBuiltin<"__builtin_xtensa_ee_vldbc_16_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vldbc_16_xp: ClangBuiltin<"__builtin_xtensa_ee_vldbc_16_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vldbc_32: ClangBuiltin<"__builtin_xtensa_ee_vldbc_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vldbc_32_ip: ClangBuiltin<"__builtin_xtensa_ee_vldbc_32_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vldbc_32_xp: ClangBuiltin<"__builtin_xtensa_ee_vldbc_32_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vldbc_8: ClangBuiltin<"__builtin_xtensa_ee_vldbc_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vldbc_8_ip: ClangBuiltin<"__builtin_xtensa_ee_vldbc_8_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vldbc_8_xp: ClangBuiltin<"__builtin_xtensa_ee_vldbc_8_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vldhbc_16_incp: ClangBuiltin<"__builtin_xtensa_ee_vldhbc_16_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vld_128_ip: ClangBuiltin<"__builtin_xtensa_ee_vld_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vld_128_xp: ClangBuiltin<"__builtin_xtensa_ee_vld_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vld_h_64_ip: ClangBuiltin<"__builtin_xtensa_ee_vld_h_64_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vld_h_64_xp: ClangBuiltin<"__builtin_xtensa_ee_vld_h_64_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vld_l_64_ip: ClangBuiltin<"__builtin_xtensa_ee_vld_l_64_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vld_l_64_xp: ClangBuiltin<"__builtin_xtensa_ee_vld_l_64_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vmax_s16: ClangBuiltin<"__builtin_xtensa_ee_vmax_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmax_s16_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmax_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmax_s16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmax_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmax_s32: ClangBuiltin<"__builtin_xtensa_ee_vmax_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmax_s32_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmax_s32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmax_s32_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmax_s32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmax_s8: ClangBuiltin<"__builtin_xtensa_ee_vmax_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmax_s8_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmax_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmax_s8_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmax_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s16: ClangBuiltin<"__builtin_xtensa_ee_vmin_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s16_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmin_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmin_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s32: ClangBuiltin<"__builtin_xtensa_ee_vmin_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s32_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmin_s32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s32_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmin_s32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s8: ClangBuiltin<"__builtin_xtensa_ee_vmin_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s8_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmin_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmin_s8_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmin_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_accx: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_accx">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_accx_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_accx_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_accx_ld_ip_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_accx_ld_ip_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_accx_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_accx_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_accx_ld_xp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_accx_ld_xp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_qacc: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_qacc_ldbc_incp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_qacc_ldbc_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_qacc_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_qacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_qacc_ld_ip_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_qacc_ld_ip_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_qacc_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_qacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s16_qacc_ld_xp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s16_qacc_ld_xp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_accx: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_accx">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_accx_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_accx_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_accx_ld_ip_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_accx_ld_ip_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_accx_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_accx_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_accx_ld_xp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_accx_ld_xp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_qacc: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_qacc_ldbc_incp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_qacc_ldbc_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_qacc_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_qacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_qacc_ld_ip_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_qacc_ld_ip_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_qacc_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_qacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_s8_qacc_ld_xp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_s8_qacc_ld_xp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_accx: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_accx">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_accx_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_accx_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_accx_ld_ip_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_accx_ld_ip_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_accx_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_accx_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_accx_ld_xp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_accx_ld_xp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_qacc: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_qacc_ldbc_incp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_qacc_ldbc_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_qacc_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_qacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_qacc_ld_ip_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_qacc_ld_ip_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_qacc_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_qacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u16_qacc_ld_xp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u16_qacc_ld_xp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_accx: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_accx">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_accx_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_accx_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_accx_ld_ip_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_accx_ld_ip_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_accx_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_accx_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_accx_ld_xp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_accx_ld_xp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_qacc: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_qacc_ldbc_incp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_qacc_ldbc_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_qacc_ld_ip: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_qacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_qacc_ld_ip_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_qacc_ld_ip_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_qacc_ld_xp: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_qacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmulas_u8_qacc_ld_xp_qup: ClangBuiltin<"__builtin_xtensa_ee_vmulas_u8_qacc_ld_xp_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_s16: ClangBuiltin<"__builtin_xtensa_ee_vmul_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_s16_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmul_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_s16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmul_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_s8: ClangBuiltin<"__builtin_xtensa_ee_vmul_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_s8_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmul_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_s8_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmul_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_u16: ClangBuiltin<"__builtin_xtensa_ee_vmul_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_u16_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmul_u16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_u16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmul_u16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_u8: ClangBuiltin<"__builtin_xtensa_ee_vmul_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_u8_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vmul_u8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vmul_u8_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vmul_u8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vprelu_s16: ClangBuiltin<"__builtin_xtensa_ee_vprelu_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vprelu_s8: ClangBuiltin<"__builtin_xtensa_ee_vprelu_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vrelu_s16: ClangBuiltin<"__builtin_xtensa_ee_vrelu_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vrelu_s8: ClangBuiltin<"__builtin_xtensa_ee_vrelu_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vsl_32: ClangBuiltin<"__builtin_xtensa_ee_vsl_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsmulas_s16_qacc: ClangBuiltin<"__builtin_xtensa_ee_vsmulas_s16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsmulas_s16_qacc_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vsmulas_s16_qacc_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsmulas_s8_qacc: ClangBuiltin<"__builtin_xtensa_ee_vsmulas_s8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsmulas_s8_qacc_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vsmulas_s8_qacc_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsr_32: ClangBuiltin<"__builtin_xtensa_ee_vsr_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vst_128_ip: ClangBuiltin<"__builtin_xtensa_ee_vst_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vst_128_xp: ClangBuiltin<"__builtin_xtensa_ee_vst_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vst_h_64_ip: ClangBuiltin<"__builtin_xtensa_ee_vst_h_64_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vst_h_64_xp: ClangBuiltin<"__builtin_xtensa_ee_vst_h_64_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vst_l_64_ip: ClangBuiltin<"__builtin_xtensa_ee_vst_l_64_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vst_l_64_xp: ClangBuiltin<"__builtin_xtensa_ee_vst_l_64_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_vsubs_s16: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsubs_s16_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsubs_s16_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsubs_s32: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsubs_s32_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsubs_s32_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsubs_s8: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsubs_s8_ld_incp: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vsubs_s8_st_incp: ClangBuiltin<"__builtin_xtensa_ee_vsubs_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vunzip_16: ClangBuiltin<"__builtin_xtensa_ee_vunzip_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vunzip_32: ClangBuiltin<"__builtin_xtensa_ee_vunzip_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vunzip_8: ClangBuiltin<"__builtin_xtensa_ee_vunzip_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vzip_16: ClangBuiltin<"__builtin_xtensa_ee_vzip_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vzip_32: ClangBuiltin<"__builtin_xtensa_ee_vzip_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_vzip_8: ClangBuiltin<"__builtin_xtensa_ee_vzip_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_xtensa_ee_xorq: ClangBuiltin<"__builtin_xtensa_ee_xorq">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_xtensa_ee_zero_accx: ClangBuiltin<"__builtin_xtensa_ee_zero_accx">, + Intrinsic<[], [], []>; + +def int_xtensa_ee_zero_q: ClangBuiltin<"__builtin_xtensa_ee_zero_q">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ee_zero_qacc: ClangBuiltin<"__builtin_xtensa_ee_zero_qacc">, + Intrinsic<[], [], []>; + +def int_xtensa_rur_accx_0: ClangBuiltin<"__builtin_xtensa_rur_accx_0">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_accx_1: ClangBuiltin<"__builtin_xtensa_rur_accx_1">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_fft_bit_width: ClangBuiltin<"__builtin_xtensa_rur_fft_bit_width">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_gpio_out: ClangBuiltin<"__builtin_xtensa_rur_gpio_out">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_h_0: ClangBuiltin<"__builtin_xtensa_rur_qacc_h_0">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_h_1: ClangBuiltin<"__builtin_xtensa_rur_qacc_h_1">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_h_2: ClangBuiltin<"__builtin_xtensa_rur_qacc_h_2">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_h_3: ClangBuiltin<"__builtin_xtensa_rur_qacc_h_3">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_h_4: ClangBuiltin<"__builtin_xtensa_rur_qacc_h_4">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_l_0: ClangBuiltin<"__builtin_xtensa_rur_qacc_l_0">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_l_1: ClangBuiltin<"__builtin_xtensa_rur_qacc_l_1">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_l_2: ClangBuiltin<"__builtin_xtensa_rur_qacc_l_2">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_l_3: ClangBuiltin<"__builtin_xtensa_rur_qacc_l_3">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_qacc_l_4: ClangBuiltin<"__builtin_xtensa_rur_qacc_l_4">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_sar_byte: ClangBuiltin<"__builtin_xtensa_rur_sar_byte">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_ua_state_0: ClangBuiltin<"__builtin_xtensa_rur_ua_state_0">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_ua_state_1: ClangBuiltin<"__builtin_xtensa_rur_ua_state_1">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_ua_state_2: ClangBuiltin<"__builtin_xtensa_rur_ua_state_2">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_rur_ua_state_3: ClangBuiltin<"__builtin_xtensa_rur_ua_state_3">, + Intrinsic<[llvm_i32_ty], [], []>; + +def int_xtensa_wur_accx_0: ClangBuiltin<"__builtin_xtensa_wur_accx_0">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_accx_1: ClangBuiltin<"__builtin_xtensa_wur_accx_1">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_fft_bit_width: ClangBuiltin<"__builtin_xtensa_wur_fft_bit_width">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_gpio_out: ClangBuiltin<"__builtin_xtensa_wur_gpio_out">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_h_0: ClangBuiltin<"__builtin_xtensa_wur_qacc_h_0">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_h_1: ClangBuiltin<"__builtin_xtensa_wur_qacc_h_1">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_h_2: ClangBuiltin<"__builtin_xtensa_wur_qacc_h_2">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_h_3: ClangBuiltin<"__builtin_xtensa_wur_qacc_h_3">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_h_4: ClangBuiltin<"__builtin_xtensa_wur_qacc_h_4">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_l_0: ClangBuiltin<"__builtin_xtensa_wur_qacc_l_0">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_l_1: ClangBuiltin<"__builtin_xtensa_wur_qacc_l_1">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_l_2: ClangBuiltin<"__builtin_xtensa_wur_qacc_l_2">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_l_3: ClangBuiltin<"__builtin_xtensa_wur_qacc_l_3">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_qacc_l_4: ClangBuiltin<"__builtin_xtensa_wur_qacc_l_4">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_sar_byte: ClangBuiltin<"__builtin_xtensa_wur_sar_byte">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ua_state_0: ClangBuiltin<"__builtin_xtensa_wur_ua_state_0">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ua_state_1: ClangBuiltin<"__builtin_xtensa_wur_ua_state_1">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ua_state_2: ClangBuiltin<"__builtin_xtensa_wur_ua_state_2">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ua_state_3: ClangBuiltin<"__builtin_xtensa_wur_ua_state_3">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_mv_qr: ClangBuiltin<"__builtin_xtensa_mv_qr">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; \ No newline at end of file diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 0895c3dd135ace..c1fdd96f6c0ad3 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -381,8 +381,48 @@ struct XtensaOperand : public MCParsedAsmOperand { bool isseimm7_22() const { return isImm(7, 22); } + bool isSelect_2() const { return isImm(0, 1); } + + bool isSelect_4() const { return isImm(0, 3); } + + bool isSelect_8() const { return isImm(0, 7); } + + bool isSelect_16() const { return isImm(0, 16); } + bool isSelect_256() const { return isImm(0, 255); } + bool isOffset_16_16() const { + return isImm(-128, 112) && + ((cast(getImm())->getValue() & 0xf) == 0); + } + + bool isOffset_256_8() const { + return isImm(-1024, 1016) && + ((cast(getImm())->getValue() & 0x7) == 0); + } + + bool isOffset_256_16() const { + return isImm(-2048, 2032) && + ((cast(getImm())->getValue() & 0xf) == 0); + } + + bool isOffset_256_4() const { + return isImm(-512, 508) && + ((cast(getImm())->getValue() & 0x3) == 0); + } + + bool isOffset_128_2() const { + return isImm(0, 254) && + ((cast(getImm())->getValue() & 0x1) == 0); + } + + bool isOffset_128_1() const { return isImm(0, 127); } + + bool isOffset_64_16() const { + return isImm(-512, 496) && + ((cast(getImm())->getValue() & 0xf) == 0); + } + /// getStartLoc - Gets location of the first token of this operand SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Gets location of the last token of this operand @@ -702,9 +742,48 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_Invalidseimm7_22: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [7, 22]"); + case Match_InvalidSelect_2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 1]"); + case Match_InvalidSelect_4: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 3]"); + case Match_InvalidSelect_8: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 7]"); + case Match_InvalidSelect_16: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 15]"); case Match_InvalidSelect_256: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [0, 255]"); + case Match_InvalidOffset_16_16: + return Error( + RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-128, 112], first 4 bits should be zero"); + case Match_InvalidOffset_256_8: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-1024, 1016], first 3 bits " + "should be zero"); + case Match_InvalidOffset_256_16: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-2048, 2032], first 4 bits " + "should be zero"); + case Match_InvalidOffset_256_4: + return Error( + RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-512, 508], first 2 bits should be zero"); + case Match_InvalidOffset_128_2: + return Error( + RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 254], first bit should be zero"); + case Match_InvalidOffset_128_1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 127]"); + case Match_InvalidOffset_64_16: + return Error( + RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [-512, 496], first 4 bits should be zero"); } report_fatal_error("Unknown match type detected!"); @@ -846,9 +925,9 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands, return ParseStatus::NoMatch; } - if (!checkRegister(Mnemonic.lower(), RegName, RegNo)) { + if (!checkRegister(Mnemonic.lower(), RegName, RegNo)) return ParseStatus::NoMatch; - } + if (HadParens) Operands.push_back(XtensaOperand::createToken("(", FirstS)); diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index 873de70425a731..93a133be9dff85 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -25,6 +25,7 @@ add_llvm_target(XtensaCodeGen XtensaInstrInfo.cpp XtensaISelDAGToDAG.cpp XtensaISelLowering.cpp + XtensaS3ISelLowering.cpp XtensaMachineFunctionInfo.cpp XtensaMCInstLower.cpp XtensaRegisterInfo.cpp diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index e2974da88a4410..0c78d30ea1ab87 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -75,6 +75,21 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Success; } +static const unsigned QRDecoderTable[] = { + Xtensa::Q0, Xtensa::Q1, Xtensa::Q2, Xtensa::Q3, Xtensa::Q4, Xtensa::Q5, + Xtensa::Q6, Xtensa::Q7}; + +static DecodeStatus DecodeQRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= std::size(QRDecoderTable)) + return MCDisassembler::Fail; + + unsigned Reg = QRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static const unsigned FPRDecoderTable[] = { Xtensa::F0, Xtensa::F1, Xtensa::F2, Xtensa::F3, Xtensa::F4, Xtensa::F5, Xtensa::F6, Xtensa::F7, Xtensa::F8, Xtensa::F9, Xtensa::F10, Xtensa::F11, @@ -569,6 +584,38 @@ static DecodeStatus decodeSeimm7_22Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeSelect_2Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeSelect_4Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeSelect_8Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeSelect_16Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + static DecodeStatus decodeSelect_256Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { @@ -577,6 +624,80 @@ static DecodeStatus decodeSelect_256Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeOffset_16_16Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<8>(Imm) && "Invalid immediate"); + if ((Imm & 0xf) != 0) + Inst.addOperand(MCOperand::createImm(Imm << 4)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_256_8Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<16>(Imm) && "Invalid immediate"); + if ((Imm & 0x7) != 0) + Inst.addOperand(MCOperand::createImm(Imm << 3)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<16>(Imm) && "Invalid immediate"); + if ((Imm & 0xf) != 0) + Inst.addOperand(MCOperand::createImm(Imm << 4)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<16>(Imm) && "Invalid immediate"); + if ((Imm & 0x2) != 0) + Inst.addOperand(MCOperand::createImm(Imm << 2)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_128_2Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + if ((Imm & 0x1) != 0) + Inst.addOperand(MCOperand::createImm(Imm << 1)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_128_1Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_64_16Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<16>(Imm) && "Invalid immediate"); + if ((Imm & 0xf) != 0) + Inst.addOperand(MCOperand::createImm(Imm << 4)); + else + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + static int64_t TableB4const[16] = {-1, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256}; static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm, diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index 85db697c724d62..5919ef54014318 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -449,6 +449,50 @@ void XtensaInstPrinter::printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, printOperand(MI, OpNum, O); } +void XtensaInstPrinter::printSelect_2_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 1) && + "Invalid argument, value must be in range [0,1]"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printSelect_4_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 3) && + "Invalid argument, value must be in range [0,3]"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printSelect_8_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 7) && + "Invalid argument, value must be in range [0,7]"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printSelect_16_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 15) && + "Invalid argument, value must be in range [0,15]"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + void XtensaInstPrinter::printSelect_256_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { if (MI->getOperand(OpNum).isImm()) { @@ -459,3 +503,88 @@ void XtensaInstPrinter::printSelect_256_AsmOperand(const MCInst *MI, int OpNum, } else printOperand(MI, OpNum, O); } + +void XtensaInstPrinter::printOffset_16_16_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -128 && Value <= 112 && (Value & 0xf) == 0) && + "Invalid argument, value must be in range [-128,112], first 4 bits " + "should be zero"); + O << Value; + } else{ + printOperand(MI, OpNum, O); + } +} + +void XtensaInstPrinter::printOffset_256_8_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -1024 && Value <= 1016 && (Value & 0x7) == 0) && + "Invalid argument, value must be in range [-1024,1016], first 3 " + "bits should be zero"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printOffset_256_16_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -2048 && Value <= 2032 && (Value & 0xf) == 0) && + "Invalid argument, value must be in range [-2048,2032], first 4 " + "bits should be zero"); + O << Value; + } else{ + printOperand(MI, OpNum, O); + } +} + +void XtensaInstPrinter::printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -512 && Value <= 508 && (Value & 0x3) == 0) && + "Invalid argument, value must be in range [-512,508], first 2 bits " + "should be zero"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printOffset_128_2_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 254 && (Value & 0x1) == 0) && + "Invalid argument, value must be in range [0,254], first bit should " + "be zero"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printOffset_128_1_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 127) && + "Invalid argument, value must be in range [0,127]"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + +void XtensaInstPrinter::printOffset_64_16_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -512 && Value <= 496 && (Value & 0xf) == 0) && + "Invalid argument, value must be in range [-512,496], first 4 bits " + "should be zero"); + O << Value; + } else + printOperand(MI, OpNum, O); +} diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index 3e8c752bc44260..a8416279d6ae0d 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -70,7 +70,18 @@ class XtensaInstPrinter : public MCInstPrinter { void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printSelect_2_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printSelect_4_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printSelect_8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printSelect_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printSelect_256_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printOffset_16_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printOffset_256_8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printOffset_256_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printOffset_128_2_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printOffset_128_1_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printOffset_64_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 73039c2a44480c..1e960cdce26fde 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -143,10 +143,53 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; - uint32_t getSelect_256OpValue(const MCInst &MI, unsigned OpNo, + uint8_t getSelect_2OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + uint8_t getSelect_4OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getSelect_8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getSelect_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getSelect_256OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int8_t getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int16_t getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int16_t getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int16_t getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getOffset_128_2OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getOffset_128_1OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int16_t getOffset_64_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; }; } // namespace @@ -598,16 +641,154 @@ XtensaMCCodeEmitter::getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo, return res; } -uint32_t +uint8_t +XtensaMCCodeEmitter::getSelect_2OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 1)) && "Unexpected operand value!"); + + return Res; +} + +uint8_t +XtensaMCCodeEmitter::getSelect_4OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 3)) && "Unexpected operand value!"); + + return Res; +} + +uint8_t +XtensaMCCodeEmitter::getSelect_8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 7)) && "Unexpected operand value!"); + + return Res; +} + +uint8_t +XtensaMCCodeEmitter::getSelect_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 15)) && "Unexpected operand value!"); + + return Res; +} + +uint8_t XtensaMCCodeEmitter::getSelect_256OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - uint32_t Res = static_cast(MO.getImm()); + uint8_t Res = static_cast(MO.getImm()); assert(((Res >= 0) && (Res <= 255)) && "Unexpected operand value!"); return Res; } +int8_t +XtensaMCCodeEmitter::getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int8_t Res = static_cast(MO.getImm()); + + assert(((Res >= -128) && (Res <= 112) && ((Res & 0xf) == 0)) && + "Unexpected operand value!"); + + return Res; +} + +int16_t +XtensaMCCodeEmitter::getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int16_t Res = static_cast(MO.getImm()); + + assert(((Res >= -1024) && (Res <= 1016) && ((Res & 0x7) == 0)) && + "Unexpected operand value!"); + + return Res; +} + +int16_t +XtensaMCCodeEmitter::getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int16_t Res = static_cast(MO.getImm()); + + assert(((Res >= -2048) && (Res <= 2032) && ((Res & 0xf) == 0)) && + "Unexpected operand value!"); + + return Res; +} + +int16_t +XtensaMCCodeEmitter::getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int16_t Res = static_cast(MO.getImm()); + + assert(((Res >= -512) && (Res <= 508) && ((Res & 0x3) == 0)) && + "Unexpected operand value!"); + + return Res; +} + +uint8_t +XtensaMCCodeEmitter::getOffset_128_2OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 254) && ((Res & 0x1) == 0)) && + "Unexpected operand value!"); + + return Res; +} + +uint8_t +XtensaMCCodeEmitter::getOffset_128_1OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 127)) && "Unexpected operand value!"); + + return Res; +} + +int16_t +XtensaMCCodeEmitter::getOffset_64_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int16_t Res = static_cast(MO.getImm()); + + assert(((Res >= -512) && (Res <= 496) && ((Res & 0xf) == 0)) && + "Unexpected operand value!"); + + return Res; +} + #include "XtensaGenMCCodeEmitter.inc" diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index fff8c4c2583023..54edf6c5fa3b6b 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -373,8 +373,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, /// Return the register type for a given MVT MVT XtensaTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, - CallingConv::ID CC, - EVT VT) const { + CallingConv::ID CC, + EVT VT) const { if (VT.isFloatingPoint()) return MVT::i32; @@ -393,7 +393,7 @@ bool XtensaTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, break; } - return false; + return false; } /// If a physical register, this returns the register that receives the @@ -474,7 +474,6 @@ XtensaTargetLowering::getSingleConstraintMatchWeight( if (type->isFloatingPointTy()) weight = CW_Register; break; - } return weight; } @@ -666,7 +665,7 @@ static SDValue PerformHWLoopCombine(SDNode *N, SelectionDAG &DAG, Size, }; SDValue LoopDec = DAG.getNode(XtensaISD::LOOPDEC, dl, - DAG.getVTList(MVT::i32, MVT::Other), Args); + DAG.getVTList(MVT::i32, MVT::Other), Args); // We now need to make the intrinsic dead (it cannot be instruction // selected). @@ -776,11 +775,13 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, Reg = State.AllocateReg(IntRegs); // If this is the first part of an i64 arg, // the allocated register must be either A2, A4 or A6. - if (needs64BitAlign && (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7)) + if (needs64BitAlign && + (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7)) Reg = State.AllocateReg(IntRegs); - // arguments with 16byte alignment must be passed in the first register or passed via stack + // arguments with 16byte alignment must be passed in the first register or + // passed via stack if (needs128BitAlign && Reg != Xtensa::A2) - while ( (Reg = State.AllocateReg(IntRegs)) ) { + while ((Reg = State.AllocateReg(IntRegs))) { } LocVT = MVT::i32; } else if (ValVT == MVT::f64) { @@ -1731,8 +1732,8 @@ SDValue XtensaTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { // 2*sizeof(int*) + sizeof(int) = 12 Byte unsigned VAListSize = 12; return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2), - DAG.getConstant(VAListSize, SDLoc(Op), MVT::i32), Align(8), - false, true, false, MachinePointerInfo(), + DAG.getConstant(VAListSize, SDLoc(Op), MVT::i32), + Align(8), false, true, false, MachinePointerInfo(), MachinePointerInfo()); } @@ -1827,11 +1828,9 @@ SDValue XtensaTargetLowering::LowerFunnelShift(SDValue Op, SDValue SetSAR; if (!IsFSHR) { - SetSAR = DAG.getNode(XtensaISD::SSL, DL, - MVT::Glue, Shamt); + SetSAR = DAG.getNode(XtensaISD::SSL, DL, MVT::Glue, Shamt); } else { - SetSAR = DAG.getNode(XtensaISD::SSR, DL, - MVT::Glue, Shamt); + SetSAR = DAG.getNode(XtensaISD::SSR, DL, MVT::Glue, Shamt); } return DAG.getNode(XtensaISD::SRC, DL, VT, Op0, Op1, SetSAR); @@ -2098,9 +2097,7 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI, BuildMI(BB, DL, TII.get(CmpKind), b) .addReg(LHS.getReg()) .addReg(RHS.getReg()); - BuildMI(BB, DL, TII.get(BrKind)) - .addReg(b, RegState::Kill) - .addMBB(sinkMBB); + BuildMI(BB, DL, TII.get(BrKind)).addReg(b, RegState::Kill).addMBB(sinkMBB); } else { bool BrInv = false; int BrKind = GetBranchKind(Cond.getImm(), BrInv); @@ -3364,6 +3361,7 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( return MBB; } default: - llvm_unreachable("Unexpected instr type to insert"); + return EmitDSPInstrWithCustomInserter(MI, MBB, TII, MF, MRI, DL); + // llvm_unreachable("Unexpected instr type to insert"); } } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 800b8e69cfdbe1..965e32f2675642 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -28,7 +28,7 @@ enum { BR_T, BR_F, - //Conditional branch with FP operands + // Conditional branch with FP operands BR_CC_FP, BR_JT, @@ -184,6 +184,10 @@ class XtensaTargetLowering : public TargetLowering { EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override; + MachineBasicBlock *EmitDSPInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *MBB, const TargetInstrInfo &TII, + MachineFunction *MF, MachineRegisterInfo &MRI, DebugLoc DL) const; + private: const XtensaSubtarget &Subtarget; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrFormats.td b/llvm/lib/Target/Xtensa/XtensaInstrFormats.td index e7c51da1e14fa0..beb15c3c5647b9 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrFormats.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrFormats.td @@ -210,6 +210,18 @@ class RI6_Inst op0, bits<1> i, bits<1> z, dag outs, dag ins, let Inst{3-0} = op0; } +class EE_Inst24 pattern, + InstrItinClass itin = NoItinerary> + : XtensaInst24 { +} + +class EE_Inst32 pattern, + InstrItinClass itin = NoItinerary> + : XtensaInst<4, outs, ins, asmstr, pattern, itin> { + field bits<32> Inst; + field bits<32> SoftFail = 0; +} + // Pseudo instructions class Pseudo pattern> : XtensaInst<2, outs, ins, asmstr, pattern> { diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 29bce03c303673..5f92e869f68eaf 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1736,8 +1736,10 @@ let Predicates = [HasESP32S3Ops] in { let s = 0x8; } } +include "XtensaS3DSPInstrInfo.td" //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// include "XtensaDSPInstrInfo.td" + diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 620aeee0005183..7810d0a36a354a 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -182,6 +182,89 @@ def select_256: Immediate= 0 && Imm <= 255; }], "Select_256 let DecoderMethod = "decodeSelect_256Operand"; } +// select_2 predicate - Immediate in the range [0,1] +def Select_2_AsmOperand: ImmAsmOperand<"Select_2">; +def select_2: Immediate= 0 && Imm <= 1; }], "Select_2_AsmOperand"> { + let EncoderMethod = "getSelect_2OpValue"; + let DecoderMethod = "decodeSelect_2Operand"; +} + +// select_4 predicate - Immediate in the range [0,3] +def Select_4_AsmOperand: ImmAsmOperand<"Select_4">; +def select_4: Immediate= 0 && Imm <= 3; }], "Select_4_AsmOperand"> { + let EncoderMethod = "getSelect_4OpValue"; + let DecoderMethod = "decodeSelect_4Operand"; +} + +// select_8 predicate - Immediate in the range [0,7] +def Select_8_AsmOperand: ImmAsmOperand<"Select_8">; +def select_8: Immediate= 0 && Imm <= 7; }], "Select_8_AsmOperand"> { + let EncoderMethod = "getSelect_8OpValue"; + let DecoderMethod = "decodeSelect_8Operand"; +} + +// select_16 predicate - Immediate in the range [0,15] +def Select_16_AsmOperand: ImmAsmOperand<"Select_16">; +def select_16: Immediate= 0 && Imm <= 15; }], "Select_16_AsmOperand"> { + let EncoderMethod = "getSelect_16OpValue"; + let DecoderMethod = "decodeSelect_16Operand"; +} +/// --------------------------- /// +// offset_16_16 predicate - 4-bit signed immediate in the range [-128,112] with an interval +// of 16. +def Offset_16_16_AsmOperand: ImmAsmOperand<"Offset_16_16">; +def offset_16_16: Immediate= -128 && Imm <= 112) && (Imm & 0xf == 0); }], "Offset_16_16_AsmOperand"> { + let EncoderMethod = "getOffset_16_16OpValue"; + let DecoderMethod = "decodeOffset_16_16Operand"; +} + +// offset_256_8 predicate - 4-bit signed immediate in the range [-1024,1016] with an interval +// of 8. +def Offset_256_8_AsmOperand: ImmAsmOperand<"Offset_256_8">; +def offset_256_8: Immediate= -1024 && Imm <= 1016) && (Imm & 0x7 == 0); }], "Offset_256_8_AsmOperand"> { + let EncoderMethod = "getOffset_256_8OpValue"; + let DecoderMethod = "decodeOffset_256_8Operand"; +} + +// offset_256_16 predicate - 8-bit signed immediate in the range [-2048,2032] with an interval +// of 16. +def Offset_256_16_AsmOperand: ImmAsmOperand<"Offset_256_16">; +def offset_256_16: Immediate= -2048 && Imm <= 2032) && (Imm & 0xf == 0); }], "Offset_256_16_AsmOperand"> { + let EncoderMethod = "getOffset_256_16OpValue"; + let DecoderMethod = "decodeOffset_256_16Operand"; +} + +// offset_256_4 predicate - 4-bit signed immediate in the range [-512,508] with an interval +// of 4. +def Offset_256_4_AsmOperand: ImmAsmOperand<"Offset_256_4">; +def offset_256_4: Immediate= -512 && Imm <= 508) && (Imm & 0x3 == 0); }], "Offset_256_4_AsmOperand"> { + let EncoderMethod = "getOffset_256_4OpValue"; + let DecoderMethod = "decodeOffset_256_4Operand"; +} + +// offset_128_2 predicate - 4-bit signed immediate in the range [0,254] with an interval +// of 2. +def Offset_128_2_AsmOperand: ImmAsmOperand<"Offset_128_2">; +def offset_128_2: Immediate= 0 && Imm <= 254) && (Imm & 0x1 == 0); }], "Offset_128_2_AsmOperand"> { + let EncoderMethod = "getOffset_128_2OpValue"; + let DecoderMethod = "decodeOffset_128_2Operand"; +} + +// offset_128_1 predicate - 4-bit signed immediate in the range [0,127] +def Offset_128_1_AsmOperand: ImmAsmOperand<"Offset_128_1">; +def offset_128_1: Immediate= 0 && Imm <= 127; }], "Offset_128_1_AsmOperand"> { + let EncoderMethod = "getOffset_128_1OpValue"; + let DecoderMethod = "decodeOffset_128_1Operand"; +} + +// offset_64_16 predicate - 4-bit signed immediate in the range [-512,496] with an interval +// of 16. +def Offset_64_16_AsmOperand: ImmAsmOperand<"Offset_64_16">; +def offset_64_16: Immediate= -512 && Imm <= 496) && (Imm & 0xf == 0); }], "Offset_64_16_AsmOperand"> { + let EncoderMethod = "getOffset_64_16OpValue"; + let DecoderMethod = "decodeOffset_64_16Operand"; +} + //===----------------------------------------------------------------------===// // Memory address operands //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 73b4a3cd00b589..dc2d5abc48758f 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -64,6 +64,25 @@ def A15 : ARReg<15, "a15">, DwarfRegNum<[15]>; def AR : RegisterClass<"Xtensa", [i32], 32, (add A8, A9, A10, A11, A12, A13, A14, A15, A7, A6, A5, A4, A3, A2, A0, SP)>; + + +// 128-bit general-purpose registers +class QRReg num, string n, listalt = []> : XtensaReg{ + let HWEncoding{15-0} = num; + let AltNames = alt; +} + +def Q0 : QRReg<0, "q0">, DwarfRegNum<[0]>; +def Q1 : QRReg<1, "q1">, DwarfRegNum<[1]>; +def Q2 : QRReg<2, "q2">, DwarfRegNum<[2]>; +def Q3 : QRReg<3, "q3">, DwarfRegNum<[3]>; +def Q4 : QRReg<4, "q4">, DwarfRegNum<[4]>; +def Q5 : QRReg<5, "q5">, DwarfRegNum<[5]>; +def Q6 : QRReg<6, "q6">, DwarfRegNum<[6]>; +def Q7 : QRReg<7, "q7">, DwarfRegNum<[7]>; + +def QR : RegisterClass<"Xtensa", [v16i8, v4i32], 128, (sequence "Q%u", 0, 7)>; + //===----------------------------------------------------------------------===// // Special-purpose registers //===----------------------------------------------------------------------===// @@ -237,8 +256,14 @@ def F64R_LO : URReg<234, "f64r_lo", ["F64R_LO"]>; def F64R_HI : URReg<235, "f64r_hi", ["F64R_HI"]>; def F64S : URReg<236, "f64s", ["F64S"]>; +def ACCX : URReg<237, "accx", ["accx_0", "accx_1"]>; +def QACC : URReg<238, "qacc", ["qacc_h_0", "qacc_h_1", "qacc_h_2", "qacc_h_3", "qacc_h_4", "qacc_l_0", "qacc_l_1", "qacc_l_2", "qacc_l_3", "qacc_l_4"]>; +def FFT_BIT_WIDTH : URReg<239, "fft_bit_width", ["fft_bit_width"]>; +def SAR_BYTE : URReg<240, "sar_byte", ["sar_byte"]>; +def UA_STATE : URReg<241, "ua_state", ["ua_state_0", "ua_state_1", "ua_state_2", "ua_state_3"]>; + def UR : RegisterClass<"Xtensa", [i32], 32, (add GPIO_OUT, EXPSTATE, THREADPTR, FCR, - FSR, F64R_LO, F64R_HI, F64S)>; + FSR, F64R_LO, F64R_HI, F64S, ACCX, QACC, FFT_BIT_WIDTH, SAR_BYTE, UA_STATE)>; //===----------------------------------------------------------------------===// // Floating-Point registers diff --git a/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td new file mode 100644 index 00000000000000..557463fd461c42 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td @@ -0,0 +1,5659 @@ +//===- XtensaS3DSPInstrInfo.td - Xtensa Target Description -*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the Xtensa S3 DSP instructions in TableGen format. +// +// These definitions are generated +// This file is generated +// AI_S6_V2.h +// +//===----------------------------------------------------------------------===// + +// This file is generated + + +def EE_ANDQ: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.andq\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qa{0}; + let Inst{14-12} = 0x3; + let Inst{11-10} = qy{2-1}; + let Inst{9-8} = 0x0; + let Inst{7-6} = qx{2-1}; + let Inst{5} = qy{0}; + let Inst{4} = qx{0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_ANDQ_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_andq_p, $qa, $qx, $qy", + [(int_xtensa_ee_andq timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_BITREV: EE_Inst24<(outs QR:$qa, AR:$axr), (ins AR:$ax), + "ee.bitrev\t $qa, $ax", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<4> ax; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qa{0}; + let Inst{14-8} = 0x7b; + let Inst{7-4} = ax{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_BITREV_P : Pseudo<(outs), (ins imm8:$qa, AR:$ax), + "!xtensa_ee_bitrev_p, $qa, $ax", + [(int_xtensa_ee_bitrev timm:$qa, AR:$ax)]>; + +def EE_CMUL_S16: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy, select_4:$sel4), + "ee.cmul.s16\t $qz, $qx, $qy, $sel4", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qz; + bits<3> qx; + bits<3> qy; + bits<2> sel4; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qz{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qz{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-6} = 0x0; + let Inst{5-4} = sel4{1-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_CMUL_S16_P : Pseudo<(outs), (ins imm8:$qz, imm8:$qx, imm8:$qy, select_4:$sel4), + "!xtensa_ee_cmul_s16_p, $qz, $qx, $qy, $sel4", + [(int_xtensa_ee_cmul_s16 timm:$qz, timm:$qx, timm:$qy, timm:$sel4)]>; + +def EE_CMUL_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy, select_4:$sel4), + "ee.cmul.s16.ld.incp\t $qu, $as, $qz, $qx, $qy, $sel4", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + bits<2> sel4; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-6} = 0x3; + let Inst{5-4} = sel4{1-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_CMUL_S16_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy, select_4:$sel4), + "!xtensa_ee_cmul_s16_ld_incp_p, $qu, $as, $qz, $qx, $qy, $sel4", + [(int_xtensa_ee_cmul_s16_ld_incp timm:$qu, AR:$as, timm:$qz, timm:$qx, timm:$qy, timm:$sel4)]>; + +def EE_CMUL_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy, select_4:$sel4), + "ee.cmul.s16.st.incp\t $qv, $as, $qz, $qx, $qy, $sel4", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + bits<2> sel4; + + let mayStore = 1; + + let Inst{28-20} = 0x1c8; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-6} = 0x0; + let Inst{5-4} = sel4{1-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_CMUL_S16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy, select_4:$sel4), + "!xtensa_ee_cmul_s16_st_incp_p, $qv, $as, $qz, $qx, $qy, $sel4", + [(int_xtensa_ee_cmul_s16_st_incp timm:$qv, AR:$as, timm:$qz, timm:$qx, timm:$qy, timm:$sel4)]>; + +def EE_FFT_AMS_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz, QR:$qz1), (ins AR:$as, QR:$qx, QR:$qy, QR:$qm, select_2:$sel2), + "ee.fft.ams.s16.ld.incp\t $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qz; + bits<3> qz1; + bits<3> qx; + bits<3> qy; + bits<3> qm; + bits<1> sel2; + + let mayLoad = 1; + + let Inst{28-23} = 0x34; + let Inst{22} = sel2{0}; + let Inst{21-20} = qz1{2-1}; + let Inst{19-17} = qm{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qz{2-0}; + let Inst{10-8} = qy{2-0}; + let Inst{7} = qz1{0}; + let Inst{6-4} = qu{2-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_FFT_AMS_S16_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qz, imm8:$qz1, imm8:$qx, imm8:$qy, imm8:$qm, select_2:$sel2), + "!xtensa_ee_fft_ams_s16_ld_incp_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", + [(int_xtensa_ee_fft_ams_s16_ld_incp timm:$qu, AR:$as, timm:$qz, timm:$qz1, timm:$qx, timm:$qy, timm:$qm, timm:$sel2)]>; + +def EE_FFT_AMS_S16_LD_INCP_UAUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz, QR:$qz1), (ins AR:$as, QR:$qx, QR:$qy, QR:$qm, select_2:$sel2), + "ee.fft.ams.s16.ld.incp.uaup\t $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qz; + bits<3> qz1; + bits<3> qx; + bits<3> qy; + bits<3> qm; + bits<1> sel2; + + let mayLoad = 1; + + let Inst{28-23} = 0x35; + let Inst{22} = sel2{0}; + let Inst{21-20} = qz1{2-1}; + let Inst{19-17} = qm{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qz{2-0}; + let Inst{10-8} = qy{2-0}; + let Inst{7} = qz1{0}; + let Inst{6-4} = qu{2-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_FFT_AMS_S16_LD_INCP_UAUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qz, imm8:$qz1, imm8:$qx, imm8:$qy, imm8:$qm, select_2:$sel2), + "!xtensa_ee_fft_ams_s16_ld_incp_uaup_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", + [(int_xtensa_ee_fft_ams_s16_ld_incp_uaup timm:$qu, AR:$as, timm:$qz, timm:$qz1, timm:$qx, timm:$qy, timm:$qm, timm:$sel2)]>; + +def EE_FFT_AMS_S16_LD_R32_DECP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz, QR:$qz1), (ins AR:$as, QR:$qx, QR:$qy, QR:$qm, select_2:$sel2), + "ee.fft.ams.s16.ld.r32.decp\t $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qz; + bits<3> qz1; + bits<3> qx; + bits<3> qy; + bits<3> qm; + bits<1> sel2; + + let mayLoad = 1; + + let Inst{28-23} = 0x36; + let Inst{22} = sel2{0}; + let Inst{21-20} = qz1{2-1}; + let Inst{19-17} = qm{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qz{2-0}; + let Inst{10-8} = qy{2-0}; + let Inst{7} = qz1{0}; + let Inst{6-4} = qu{2-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_FFT_AMS_S16_LD_R32_DECP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qz, imm8:$qz1, imm8:$qx, imm8:$qy, imm8:$qm, select_2:$sel2), + "!xtensa_ee_fft_ams_s16_ld_r32_decp_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", + [(int_xtensa_ee_fft_ams_s16_ld_r32_decp timm:$qu, AR:$as, timm:$qz, timm:$qz1, timm:$qx, timm:$qy, timm:$qm, timm:$sel2)]>; + +def EE_FFT_AMS_S16_ST_INCP: EE_Inst32<(outs QR:$qz1, AR:$as0r, AR:$asr), (ins QR:$qv, AR:$as0, AR:$as, QR:$qx, QR:$qy, QR:$qm, select_2:$sel2), + "ee.fft.ams.s16.st.incp\t $qv, $qz1, $as0, $as, $qx, $qy, $qm, $sel2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<3> qz1; + bits<4> as0; + bits<4> as; + bits<3> qx; + bits<3> qy; + bits<3> qm; + bits<1> sel2; + + let mayStore = 1; + + let Inst{28-24} = 0x14; + let Inst{23} = sel2{0}; + let Inst{22-20} = qz1{2-0}; + let Inst{19-17} = qx{2-0}; + let Inst{16-14} = qy{2-0}; + let Inst{13-11} = qm{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = as0{3-0}; +} + +let usesCustomInserter = 1 in +def EE_FFT_AMS_S16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, imm8:$qz1, AR:$as0, AR:$as, imm8:$qx, imm8:$qy, imm8:$qm, select_2:$sel2), + "!xtensa_ee_fft_ams_s16_st_incp_p, $qv, $qz1, $as0, $as, $qx, $qy, $qm, $sel2", + [(int_xtensa_ee_fft_ams_s16_st_incp timm:$qv, timm:$qz1, AR:$as0, AR:$as, timm:$qx, timm:$qy, timm:$qm, timm:$sel2)]>; + +def EE_FFT_CMUL_S16_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, select_8:$sel8), + "ee.fft.cmul.s16.ld.xp\t $qu, $as, $ad, $qz, $qx, $qy, $sel8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qz; + bits<3> qx; + bits<3> qy; + bits<3> sel8; + + let mayLoad = 1; + + let Inst{28-23} = 0x37; + let Inst{22-20} = sel8{2-0}; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qu{2-0}; + let Inst{10-8} = qy{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_FFT_CMUL_S16_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qz, imm8:$qx, imm8:$qy, select_8:$sel8), + "!xtensa_ee_fft_cmul_s16_ld_xp_p, $qu, $as, $ad, $qz, $qx, $qy, $sel8", + [(int_xtensa_ee_fft_cmul_s16_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qz, timm:$qx, timm:$qy, timm:$sel8)]>; + +def EE_FFT_CMUL_S16_ST_XP: EE_Inst32<(outs AR:$asr), (ins QR:$qx, QR:$qy, QR:$qv, AR:$as, AR:$ad, select_8:$sel8, select_4:$upd4, select_4:$sar4), + "ee.fft.cmul.s16.st.xp\t $qx, $qy, $qv, $as, $ad, $sel8, $upd4, $sar4", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + bits<4> as; + bits<4> ad; + bits<3> sel8; + bits<2> upd4; + bits<2> sar4; + + let mayStore = 1; + + let Inst{28-24} = 0x15; + let Inst{23-22} = sar4{1-0}; + let Inst{21-20} = upd4{1-0}; + let Inst{19-17} = qv{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = sel8{2-0}; + let Inst{10-8} = qy{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_FFT_CMUL_S16_ST_XP_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv, AR:$as, AR:$ad, select_8:$sel8, select_4:$upd4, select_4:$sar4), + "!xtensa_ee_fft_cmul_s16_st_xp_p, $qx, $qy, $qv, $as, $ad, $sel8, $upd4, $sar4", + [(int_xtensa_ee_fft_cmul_s16_st_xp timm:$qx, timm:$qy, timm:$qv, AR:$as, AR:$ad, timm:$sel8, timm:$upd4, timm:$sar4)]>; + +def EE_FFT_R2BF_S16: EE_Inst24<(outs QR:$qa0, QR:$qa1), (ins QR:$qx, QR:$qy, select_2:$sel2), + "ee.fft.r2bf.s16\t $qa0, $qa1, $qx, $qy, $sel2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa0; + bits<3> qa1; + bits<3> qx; + bits<3> qy; + bits<1> sel2; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qa0{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qa0{0}; + let Inst{14-12} = qa1{2-0}; + let Inst{11-10} = qy{2-1}; + let Inst{9} = 0x0; + let Inst{8} = sel2{0}; + let Inst{7-6} = qx{2-1}; + let Inst{5} = qy{0}; + let Inst{4} = qx{0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_FFT_R2BF_S16_P : Pseudo<(outs), (ins imm8:$qa0, imm8:$qa1, imm8:$qx, imm8:$qy, select_2:$sel2), + "!xtensa_ee_fft_r2bf_s16_p, $qa0, $qa1, $qx, $qy, $sel2", + [(int_xtensa_ee_fft_r2bf_s16 timm:$qa0, timm:$qa1, timm:$qx, timm:$qy, timm:$sel2)]>; + +def EE_FFT_R2BF_S16_ST_INCP: EE_Inst32<(outs QR:$qa0, AR:$asr), (ins QR:$qx, QR:$qy, AR:$as, select_4:$sar4), + "ee.fft.r2bf.s16.st.incp\t $qa0, $qx, $qy, $as, $sar4", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa0; + bits<3> qx; + bits<3> qy; + bits<4> as; + bits<2> sar4; + + let mayStore = 1; + + let Inst{28-20} = 0x1d1; + let Inst{19-17} = qa0{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13} = 0x0; + let Inst{12-11} = sar4{1-0}; + let Inst{10-8} = qy{2-0}; + let Inst{7-4} = 0x4; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_FFT_R2BF_S16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qa0, imm8:$qx, imm8:$qy, AR:$as, select_4:$sar4), + "!xtensa_ee_fft_r2bf_s16_st_incp_p, $qa0, $qx, $qy, $as, $sar4", + [(int_xtensa_ee_fft_r2bf_s16_st_incp timm:$qa0, timm:$qx, timm:$qy, AR:$as, timm:$sar4)]>; + +def EE_FFT_VST_R32_DECP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, select_2:$sar2), + "ee.fft.vst.r32.decp\t $qv, $as, $sar2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<1> sar2; + + let mayStore = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qv{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qv{0}; + let Inst{14-11} = 0x6; + let Inst{10} = sar2{0}; + let Inst{9-8} = 0x3; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_FFT_VST_R32_DECP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, select_2:$sar2), + "!xtensa_ee_fft_vst_r32_decp_p, $qv, $as, $sar2", + [(int_xtensa_ee_fft_vst_r32_decp timm:$qv, AR:$as, timm:$sar2)]>; + +def EE_LDF_128_IP: EE_Inst32<(outs FPR:$fu3, FPR:$fu2, FPR:$fu1, FPR:$fu0, AR:$asr), (ins AR:$as, offset_16_16:$imm16f), + "ee.ldf.128.ip\t $fu3, $fu2, $fu1, $fu0, $as, $imm16f", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> fu3; + bits<4> fu2; + bits<4> fu1; + bits<4> fu0; + bits<4> as; + bits<4> imm16f; + + let mayLoad = 1; + + let Inst{28-24} = 0x10; + let Inst{23-20} = fu3{3-0}; + let Inst{19-16} = fu2{3-0}; + let Inst{15-12} = fu1{3-0}; + let Inst{11-8} = fu0{3-0}; + let Inst{7-4} = imm16f{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_LDF_128_IP_P : Pseudo<(outs), (ins FPR:$fu3, FPR:$fu2, FPR:$fu1, FPR:$fu0, AR:$as, offset_16_16:$imm16f), + "!xtensa_ee_ldf_128_ip_p, $fu3, $fu2, $fu1, $fu0, $as, $imm16f", + [(int_xtensa_ee_ldf_128_ip FPR:$fu3, FPR:$fu2, FPR:$fu1, FPR:$fu0, AR:$as, timm:$imm16f)]>; + +def EE_LDF_128_XP: EE_Inst32<(outs FPR:$fu3, FPR:$fu2, FPR:$fu1, FPR:$fu0, AR:$asr), (ins AR:$as, AR:$ad), + "ee.ldf.128.xp\t $fu3, $fu2, $fu1, $fu0, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> fu3; + bits<4> fu2; + bits<4> fu1; + bits<4> fu0; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{28-24} = 0x11; + let Inst{23-20} = fu3{3-0}; + let Inst{19-16} = fu2{3-0}; + let Inst{15-12} = fu1{3-0}; + let Inst{11-8} = fu0{3-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_LDF_128_XP_P : Pseudo<(outs), (ins FPR:$fu3, FPR:$fu2, FPR:$fu1, FPR:$fu0, AR:$as, AR:$ad), + "!xtensa_ee_ldf_128_xp_p, $fu3, $fu2, $fu1, $fu0, $as, $ad", + [(int_xtensa_ee_ldf_128_xp FPR:$fu3, FPR:$fu2, FPR:$fu1, FPR:$fu0, AR:$as, AR:$ad)]>; + +def EE_LDF_64_IP: EE_Inst32<(outs FPR:$fu1, FPR:$fu0, AR:$asr), (ins AR:$as, offset_256_8:$imm8), + "ee.ldf.64.ip\t $fu1, $fu0, $as, $imm8", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> fu1; + bits<4> fu0; + bits<4> as; + bits<8> imm8; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-16} = imm8{7-1}; + let Inst{15-12} = fu1{3-0}; + let Inst{11-8} = fu0{3-0}; + let Inst{7-5} = 0x2; + let Inst{4} = imm8{0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_LDF_64_IP_P : Pseudo<(outs), (ins FPR:$fu1, FPR:$fu0, AR:$as, offset_256_8:$imm8), + "!xtensa_ee_ldf_64_ip_p, $fu1, $fu0, $as, $imm8", + [(int_xtensa_ee_ldf_64_ip FPR:$fu1, FPR:$fu0, AR:$as, timm:$imm8)]>; + +def EE_LDF_64_XP: EE_Inst24<(outs FPR:$fu1, FPR:$fu0, AR:$asr), (ins AR:$as, AR:$ad), + "ee.ldf.64.xp\t $fu1, $fu0, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> fu1; + bits<4> fu0; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-20} = fu0{3-0}; + let Inst{19-16} = 0x6; + let Inst{15-12} = fu1{3-0}; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x0; +} + +let usesCustomInserter = 1 in +def EE_LDF_64_XP_P : Pseudo<(outs), (ins FPR:$fu1, FPR:$fu0, AR:$as, AR:$ad), + "!xtensa_ee_ldf_64_xp_p, $fu1, $fu0, $as, $ad", + [(int_xtensa_ee_ldf_64_xp FPR:$fu1, FPR:$fu0, AR:$as, AR:$ad)]>; + +def EE_LDQA_S16_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.ldqa.s16.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0x2; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LDQA_S16_128_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_ldqa_s16_128_ip_p, $as, $imm16", + [(int_xtensa_ee_ldqa_s16_128_ip AR:$as, timm:$imm16)]>; + +def EE_LDQA_S16_128_XP: EE_Inst24<(outs AR:$asr), (ins AR:$as, AR:$ad), + "ee.ldqa.s16.128.xp\t $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-12} = 0x7e4; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LDQA_S16_128_XP_P : Pseudo<(outs), (ins AR:$as, AR:$ad), + "!xtensa_ee_ldqa_s16_128_xp_p, $as, $ad", + [(int_xtensa_ee_ldqa_s16_128_xp AR:$as, AR:$ad)]>; + +def EE_LDQA_S8_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.ldqa.s8.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0x22; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LDQA_S8_128_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_ldqa_s8_128_ip_p, $as, $imm16", + [(int_xtensa_ee_ldqa_s8_128_ip AR:$as, timm:$imm16)]>; + +def EE_LDQA_S8_128_XP: EE_Inst24<(outs AR:$asr), (ins AR:$as, AR:$ad), + "ee.ldqa.s8.128.xp\t $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-12} = 0x714; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LDQA_S8_128_XP_P : Pseudo<(outs), (ins AR:$as, AR:$ad), + "!xtensa_ee_ldqa_s8_128_xp_p, $as, $ad", + [(int_xtensa_ee_ldqa_s8_128_xp AR:$as, AR:$ad)]>; + +def EE_LDQA_U16_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.ldqa.u16.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0xa; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LDQA_U16_128_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_ldqa_u16_128_ip_p, $as, $imm16", + [(int_xtensa_ee_ldqa_u16_128_ip AR:$as, timm:$imm16)]>; + +def EE_LDQA_U16_128_XP: EE_Inst24<(outs AR:$asr), (ins AR:$as, AR:$ad), + "ee.ldqa.u16.128.xp\t $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-12} = 0x7a4; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LDQA_U16_128_XP_P : Pseudo<(outs), (ins AR:$as, AR:$ad), + "!xtensa_ee_ldqa_u16_128_xp_p, $as, $ad", + [(int_xtensa_ee_ldqa_u16_128_xp AR:$as, AR:$ad)]>; + +def EE_LDQA_U8_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.ldqa.u8.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0x2a; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LDQA_U8_128_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_ldqa_u8_128_ip_p, $as, $imm16", + [(int_xtensa_ee_ldqa_u8_128_ip AR:$as, timm:$imm16)]>; + +def EE_LDQA_U8_128_XP: EE_Inst24<(outs AR:$asr), (ins AR:$as, AR:$ad), + "ee.ldqa.u8.128.xp\t $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-12} = 0x704; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LDQA_U8_128_XP_P : Pseudo<(outs), (ins AR:$as, AR:$ad), + "!xtensa_ee_ldqa_u8_128_xp_p, $as, $ad", + [(int_xtensa_ee_ldqa_u8_128_xp AR:$as, AR:$ad)]>; + +def EE_LDXQ_32: EE_Inst32<(outs QR:$qu), (ins QR:$qs, AR:$as, select_4:$sel4, select_8:$sel8), + "ee.ldxq.32\t $qu, $qs, $as, $sel4, $sel8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<3> qs; + bits<4> as; + bits<2> sel4; + bits<3> sel8; + + let mayLoad = 1; + + let Inst{28-22} = 0x70; + let Inst{21-20} = sel4{1-0}; + let Inst{19-17} = qu{2-0}; + let Inst{16-14} = qs{2-0}; + let Inst{13-11} = sel8{2-0}; + let Inst{10-4} = 0x7d; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_LDXQ_32_P : Pseudo<(outs), (ins imm8:$qu, imm8:$qs, AR:$as, select_4:$sel4, select_8:$sel8), + "!xtensa_ee_ldxq_32_p, $qu, $qs, $as, $sel4, $sel8", + [(int_xtensa_ee_ldxq_32 timm:$qu, timm:$qs, AR:$as, timm:$sel4, timm:$sel8)]>; + +def EE_LD_128_USAR_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.ld.128.usar.ip\t $qu, $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x1; + let Inst{22} = imm16{7}; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0x1; + let Inst{15} = qu{0}; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LD_128_USAR_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_256_16:$imm16), + "!xtensa_ee_ld_128_usar_ip_p, $qu, $as, $imm16", + [(int_xtensa_ee_ld_128_usar_ip timm:$qu, AR:$as, timm:$imm16)]>; + +def EE_LD_128_USAR_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad), + "ee.ld.128.usar.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-12} = 0x0; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LD_128_USAR_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad), + "!xtensa_ee_ld_128_usar_xp_p, $qu, $as, $ad", + [(int_xtensa_ee_ld_128_usar_xp timm:$qu, AR:$as, AR:$ad)]>; + +def EE_LD_ACCX_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_8:$imm8), + "ee.ld.accx.ip\t $as, $imm8", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm8; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm8{7}; + let Inst{21-15} = 0x1c; + let Inst{14-8} = imm8{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LD_ACCX_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_8:$imm8), + "!xtensa_ee_ld_accx_ip_p, $as, $imm8", + [(int_xtensa_ee_ld_accx_ip AR:$as, timm:$imm8)]>; + +def EE_LD_QACC_H_H_32_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_4:$imm4), + "ee.ld.qacc_h.h.32.ip\t $as, $imm4", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm4; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm4{7}; + let Inst{21-15} = 0x3c; + let Inst{14-8} = imm4{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LD_QACC_H_H_32_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_4:$imm4), + "!xtensa_ee_ld_qacc_h_h_32_ip_p, $as, $imm4", + [(int_xtensa_ee_ld_qacc_h_h_32_ip AR:$as, timm:$imm4)]>; + +def EE_LD_QACC_H_L_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.ld.qacc_h.l.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0xc; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LD_QACC_H_L_128_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_ld_qacc_h_l_128_ip_p, $as, $imm16", + [(int_xtensa_ee_ld_qacc_h_l_128_ip AR:$as, timm:$imm16)]>; + +def EE_LD_QACC_L_H_32_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_4:$imm4), + "ee.ld.qacc_l.h.32.ip\t $as, $imm4", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm4; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm4{7}; + let Inst{21-15} = 0x2c; + let Inst{14-8} = imm4{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LD_QACC_L_H_32_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_4:$imm4), + "!xtensa_ee_ld_qacc_l_h_32_ip_p, $as, $imm4", + [(int_xtensa_ee_ld_qacc_l_h_32_ip AR:$as, timm:$imm4)]>; + +def EE_LD_QACC_L_L_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.ld.qacc_l.l.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0x0; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LD_QACC_L_L_128_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_ld_qacc_l_l_128_ip_p, $as, $imm16", + [(int_xtensa_ee_ld_qacc_l_l_128_ip AR:$as, timm:$imm16)]>; + +def EE_LD_UA_STATE_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.ld.ua_state.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0x20; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_LD_UA_STATE_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_ld_ua_state_ip_p, $as, $imm16", + [(int_xtensa_ee_ld_ua_state_ip AR:$as, timm:$imm16)]>; + +def EE_MOVI_32_A: EE_Inst24<(outs AR:$au), (ins QR:$qs, select_4:$sel4), + "ee.movi.32.a\t $qs, $au, $sel4", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs; + bits<4> au; + bits<2> sel4; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-12} = 0x7; + let Inst{11-10} = sel4{1-0}; + let Inst{9-8} = 0x1; + let Inst{7-4} = au{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_MOVI_32_A_P : Pseudo<(outs), (ins imm8:$qs, AR:$au, select_4:$sel4), + "!xtensa_ee_movi_32_a_p, $qs, $au, $sel4", + [(int_xtensa_ee_movi_32_a timm:$qs, AR:$au, timm:$sel4)]>; + +def EE_MOVI_32_Q: EE_Inst24<(outs QR:$qu), (ins AR:$as, select_4:$sel4), + "ee.movi.32.q\t $qu, $as, $sel4", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<2> sel4; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-12} = 0x3; + let Inst{11-10} = sel4{1-0}; + let Inst{9-8} = 0x2; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_MOVI_32_Q_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, select_4:$sel4), + "!xtensa_ee_movi_32_q_p, $qu, $as, $sel4", + [(int_xtensa_ee_movi_32_q timm:$qu, AR:$as, timm:$sel4)]>; + +def EE_MOV_S16_QACC: EE_Inst24<(outs), (ins QR:$qs), + "ee.mov.s16.qacc\t $qs", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-0} = 0x7f24; +} + +let usesCustomInserter = 1 in +def EE_MOV_S16_QACC_P : Pseudo<(outs), (ins imm8:$qs), + "!xtensa_ee_mov_s16_qacc_p, $qs", + [(int_xtensa_ee_mov_s16_qacc timm:$qs)]>; + +def EE_MOV_S8_QACC: EE_Inst24<(outs), (ins QR:$qs), + "ee.mov.s8.qacc\t $qs", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-0} = 0x7f34; +} + +let usesCustomInserter = 1 in +def EE_MOV_S8_QACC_P : Pseudo<(outs), (ins imm8:$qs), + "!xtensa_ee_mov_s8_qacc_p, $qs", + [(int_xtensa_ee_mov_s8_qacc timm:$qs)]>; + +def EE_MOV_U16_QACC: EE_Inst24<(outs), (ins QR:$qs), + "ee.mov.u16.qacc\t $qs", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-0} = 0x7f64; +} + +let usesCustomInserter = 1 in +def EE_MOV_U16_QACC_P : Pseudo<(outs), (ins imm8:$qs), + "!xtensa_ee_mov_u16_qacc_p, $qs", + [(int_xtensa_ee_mov_u16_qacc timm:$qs)]>; + +def EE_MOV_U8_QACC: EE_Inst24<(outs), (ins QR:$qs), + "ee.mov.u8.qacc\t $qs", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-0} = 0x7f74; +} + +let usesCustomInserter = 1 in +def EE_MOV_U8_QACC_P : Pseudo<(outs), (ins imm8:$qs), + "!xtensa_ee_mov_u8_qacc_p, $qs", + [(int_xtensa_ee_mov_u8_qacc timm:$qs)]>; + +def EE_NOTQ: EE_Inst24<(outs QR:$qa), (ins QR:$qx), + "ee.notq\t $qa, $qx", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qa{0}; + let Inst{14-8} = 0x7f; + let Inst{7-6} = qx{2-1}; + let Inst{5} = 0x0; + let Inst{4} = qx{0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_NOTQ_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx), + "!xtensa_ee_notq_p, $qa, $qx", + [(int_xtensa_ee_notq timm:$qa, timm:$qx)]>; + +def EE_ORQ: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.orq\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qa{0}; + let Inst{14-12} = 0x7; + let Inst{11-10} = qy{2-1}; + let Inst{9-8} = 0x0; + let Inst{7-6} = qx{2-1}; + let Inst{5} = qy{0}; + let Inst{4} = qx{0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_ORQ_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_orq_p, $qa, $qx, $qy", + [(int_xtensa_ee_orq timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_SLCI_2Q: EE_Inst24<(outs QR:$qs1r, QR:$qs0r), (ins QR:$qs1, QR:$qs0, select_16:$sar16), + "ee.slci.2q\t $qs1, $qs0, $sar16", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs1; + bits<3> qs0; + bits<4> sar16; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-8} = 0x6; + let Inst{7-4} = sar16{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SLCI_2Q_P : Pseudo<(outs), (ins imm8:$qs1, imm8:$qs0, select_16:$sar16), + "!xtensa_ee_slci_2q_p, $qs1, $qs0, $sar16", + [(int_xtensa_ee_slci_2q timm:$qs1, timm:$qs0, timm:$sar16)]>; + +def EE_SLCXXP_2Q: EE_Inst24<(outs QR:$qs1r, QR:$qs0r, AR:$asr), (ins QR:$qs1, QR:$qs0, AR:$as, AR:$ad), + "ee.slcxxp.2q\t $qs1, $qs0, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs1; + bits<3> qs0; + bits<4> as; + bits<4> ad; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0x6; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SLCXXP_2Q_P : Pseudo<(outs), (ins imm8:$qs1, imm8:$qs0, AR:$as, AR:$ad), + "!xtensa_ee_slcxxp_2q_p, $qs1, $qs0, $as, $ad", + [(int_xtensa_ee_slcxxp_2q timm:$qs1, timm:$qs0, AR:$as, AR:$ad)]>; + +def EE_SRCI_2Q: EE_Inst24<(outs QR:$qs1r, QR:$qs0r), (ins QR:$qs1, QR:$qs0, select_16:$sar16), + "ee.srci.2q\t $qs1, $qs0, $sar16", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs1; + bits<3> qs0; + bits<4> sar16; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-8} = 0xa; + let Inst{7-4} = sar16{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SRCI_2Q_P : Pseudo<(outs), (ins imm8:$qs1, imm8:$qs0, select_16:$sar16), + "!xtensa_ee_srci_2q_p, $qs1, $qs0, $sar16", + [(int_xtensa_ee_srci_2q timm:$qs1, timm:$qs0, timm:$sar16)]>; + +def EE_SRCMB_S16_QACC: EE_Inst24<(outs QR:$qu), (ins AR:$as, select_2:$sel2), + "ee.srcmb.s16.qacc\t $qu, $as, $sel2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<1> sel2; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-11} = 0xe; + let Inst{10} = sel2{0}; + let Inst{9-8} = 0x2; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SRCMB_S16_QACC_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, select_2:$sel2), + "!xtensa_ee_srcmb_s16_qacc_p, $qu, $as, $sel2", + [(int_xtensa_ee_srcmb_s16_qacc timm:$qu, AR:$as, timm:$sel2)]>; + +def EE_SRCMB_S8_QACC: EE_Inst24<(outs QR:$qu), (ins AR:$as, select_2:$sel2), + "ee.srcmb.s8.qacc\t $qu, $as, $sel2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<1> sel2; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-11} = 0xf; + let Inst{10} = sel2{0}; + let Inst{9-8} = 0x2; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SRCMB_S8_QACC_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, select_2:$sel2), + "!xtensa_ee_srcmb_s8_qacc_p, $qu, $as, $sel2", + [(int_xtensa_ee_srcmb_s8_qacc timm:$qu, AR:$as, timm:$sel2)]>; + +def EE_SRCQ_128_ST_INCP: EE_Inst24<(outs AR:$asr), (ins QR:$qs0, QR:$qs1, AR:$as), + "ee.srcq.128.st.incp\t $qs0, $qs1, $as", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs0; + bits<3> qs1; + bits<4> as; + + let mayStore = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-8} = 0xe; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SRCQ_128_ST_INCP_P : Pseudo<(outs), (ins imm8:$qs0, imm8:$qs1, AR:$as), + "!xtensa_ee_srcq_128_st_incp_p, $qs0, $qs1, $as", + [(int_xtensa_ee_srcq_128_st_incp timm:$qs0, timm:$qs1, AR:$as)]>; + +def EE_SRCXXP_2Q: EE_Inst24<(outs QR:$qs1r, QR:$qs0r, AR:$asr), (ins QR:$qs1, QR:$qs0, AR:$as, AR:$ad), + "ee.srcxxp.2q\t $qs1, $qs0, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs1; + bits<3> qs0; + bits<4> as; + bits<4> ad; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0x6; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SRCXXP_2Q_P : Pseudo<(outs), (ins imm8:$qs1, imm8:$qs0, AR:$as, AR:$ad), + "!xtensa_ee_srcxxp_2q_p, $qs1, $qs0, $as, $ad", + [(int_xtensa_ee_srcxxp_2q timm:$qs1, timm:$qs0, AR:$as, AR:$ad)]>; + +def EE_SRC_Q: EE_Inst24<(outs QR:$qa), (ins QR:$qs0, QR:$qs1), + "ee.src.q\t $qa, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qs0; + bits<3> qs1; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-7} = 0x6; + let Inst{6-4} = qa{2-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SRC_Q_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_src_q_p, $qa, $qs0, $qs1", + [(int_xtensa_ee_src_q timm:$qa, timm:$qs0, timm:$qs1)]>; + +def EE_SRC_Q_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_256_16:$imm16, QR:$qs0, QR:$qs1), + "ee.src.q.ld.ip\t $qu, $as, $imm16, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = imm16{7-5}; + let Inst{19-17} = qu{2-0}; + let Inst{16-14} = qs0{2-0}; + let Inst{13-11} = imm16{4-2}; + let Inst{10-8} = qs1{2-0}; + let Inst{7-6} = 0x0; + let Inst{5-4} = imm16{1-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_SRC_Q_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_256_16:$imm16, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_src_q_ld_ip_p, $qu, $as, $imm16, $qs0, $qs1", + [(int_xtensa_ee_src_q_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qs0, timm:$qs1)]>; + +def EE_SRC_Q_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qs0, QR:$qs1), + "ee.src.q.ld.xp\t $qu, $as, $ad, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-20} = 0x1d0; + let Inst{19-17} = qu{2-0}; + let Inst{16-14} = qs0{2-0}; + let Inst{13-11} = 0x0; + let Inst{10-8} = qs1{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_SRC_Q_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_src_q_ld_xp_p, $qu, $as, $ad, $qs0, $qs1", + [(int_xtensa_ee_src_q_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qs0, timm:$qs1)]>; + +def EE_SRC_Q_QUP: EE_Inst24<(outs QR:$qa, QR:$qs0r), (ins QR:$qs0, QR:$qs1), + "ee.src.q.qup\t $qa, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qs0; + bits<3> qs1; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-7} = 0xe; + let Inst{6-4} = qa{2-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SRC_Q_QUP_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_src_q_qup_p, $qa, $qs0, $qs1", + [(int_xtensa_ee_src_q_qup timm:$qa, timm:$qs0, timm:$qs1)]>; + +def EE_SRS_ACCX: EE_Inst24<(outs AR:$au), (ins AR:$as, select_2:$sel2), + "ee.srs.accx\t $au, $as, $sel2", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> au; + bits<4> as; + bits<1> sel2; + + + let Inst{23-15} = 0xfc; + let Inst{14} = sel2{0}; + let Inst{13-12} = 0x1; + let Inst{11-8} = au{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_SRS_ACCX_P : Pseudo<(outs), (ins AR:$au, AR:$as, select_2:$sel2), + "!xtensa_ee_srs_accx_p, $au, $as, $sel2", + [(int_xtensa_ee_srs_accx AR:$au, AR:$as, timm:$sel2)]>; + +def EE_STF_128_IP: EE_Inst32<(outs AR:$asr), (ins FPR:$fv3, FPR:$fv2, FPR:$fv1, FPR:$fv0, AR:$as, offset_16_16:$imm16f), + "ee.stf.128.ip\t $fv3, $fv2, $fv1, $fv0, $as, $imm16f", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> fv3; + bits<4> fv2; + bits<4> fv1; + bits<4> fv0; + bits<4> as; + bits<4> imm16f; + + let mayStore = 1; + + let Inst{28-24} = 0x12; + let Inst{23-20} = fv3{3-0}; + let Inst{19-16} = fv2{3-0}; + let Inst{15-12} = fv1{3-0}; + let Inst{11-8} = fv0{3-0}; + let Inst{7-4} = imm16f{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_STF_128_IP_P : Pseudo<(outs), (ins FPR:$fv3, FPR:$fv2, FPR:$fv1, FPR:$fv0, AR:$as, offset_16_16:$imm16f), + "!xtensa_ee_stf_128_ip_p, $fv3, $fv2, $fv1, $fv0, $as, $imm16f", + [(int_xtensa_ee_stf_128_ip FPR:$fv3, FPR:$fv2, FPR:$fv1, FPR:$fv0, AR:$as, timm:$imm16f)]>; + +def EE_STF_128_XP: EE_Inst32<(outs AR:$asr), (ins FPR:$fv3, FPR:$fv2, FPR:$fv1, FPR:$fv0, AR:$as, AR:$ad), + "ee.stf.128.xp\t $fv3, $fv2, $fv1, $fv0, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> fv3; + bits<4> fv2; + bits<4> fv1; + bits<4> fv0; + bits<4> as; + bits<4> ad; + + let mayStore = 1; + + let Inst{28-24} = 0x13; + let Inst{23-20} = fv3{3-0}; + let Inst{19-16} = fv2{3-0}; + let Inst{15-12} = fv1{3-0}; + let Inst{11-8} = fv0{3-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_STF_128_XP_P : Pseudo<(outs), (ins FPR:$fv3, FPR:$fv2, FPR:$fv1, FPR:$fv0, AR:$as, AR:$ad), + "!xtensa_ee_stf_128_xp_p, $fv3, $fv2, $fv1, $fv0, $as, $ad", + [(int_xtensa_ee_stf_128_xp FPR:$fv3, FPR:$fv2, FPR:$fv1, FPR:$fv0, AR:$as, AR:$ad)]>; + +def EE_STF_64_IP: EE_Inst32<(outs AR:$asr), (ins FPR:$fv1, FPR:$fv0, AR:$as, offset_256_8:$imm8), + "ee.stf.64.ip\t $fv1, $fv0, $as, $imm8", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> fv1; + bits<4> fv0; + bits<4> as; + bits<8> imm8; + + let mayStore = 1; + + let Inst{28-23} = 0x38; + let Inst{22-16} = imm8{7-1}; + let Inst{15-12} = fv1{3-0}; + let Inst{11-8} = fv0{3-0}; + let Inst{7-5} = 0x3; + let Inst{4} = imm8{0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_STF_64_IP_P : Pseudo<(outs), (ins FPR:$fv1, FPR:$fv0, AR:$as, offset_256_8:$imm8), + "!xtensa_ee_stf_64_ip_p, $fv1, $fv0, $as, $imm8", + [(int_xtensa_ee_stf_64_ip FPR:$fv1, FPR:$fv0, AR:$as, timm:$imm8)]>; + +def EE_STF_64_XP: EE_Inst24<(outs AR:$asr), (ins FPR:$fv1, FPR:$fv0, AR:$as, AR:$ad), + "ee.stf.64.xp\t $fv1, $fv0, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> fv1; + bits<4> fv0; + bits<4> as; + bits<4> ad; + + let mayStore = 1; + + let Inst{23-20} = fv0{3-0}; + let Inst{19-16} = 0x7; + let Inst{15-12} = fv1{3-0}; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x0; +} + +let usesCustomInserter = 1 in +def EE_STF_64_XP_P : Pseudo<(outs), (ins FPR:$fv1, FPR:$fv0, AR:$as, AR:$ad), + "!xtensa_ee_stf_64_xp_p, $fv1, $fv0, $as, $ad", + [(int_xtensa_ee_stf_64_xp FPR:$fv1, FPR:$fv0, AR:$as, AR:$ad)]>; + +def EE_STXQ_32: EE_Inst32<(outs), (ins QR:$qv, QR:$qs, AR:$as, select_4:$sel4, select_8:$sel8), + "ee.stxq.32\t $qv, $qs, $as, $sel4, $sel8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<3> qs; + bits<4> as; + bits<2> sel4; + bits<3> sel8; + + let mayStore = 1; + + let Inst{28-22} = 0x73; + let Inst{21-20} = sel4{1-0}; + let Inst{19-17} = 0x0; + let Inst{16-14} = qs{2-0}; + let Inst{13-11} = sel8{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x0; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_STXQ_32_P : Pseudo<(outs), (ins imm8:$qv, imm8:$qs, AR:$as, select_4:$sel4, select_8:$sel8), + "!xtensa_ee_stxq_32_p, $qv, $qs, $as, $sel4, $sel8", + [(int_xtensa_ee_stxq_32 timm:$qv, timm:$qs, AR:$as, timm:$sel4, timm:$sel8)]>; + +def EE_ST_ACCX_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_8:$imm8), + "ee.st.accx.ip\t $as, $imm8", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm8; + + let mayStore = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm8{7}; + let Inst{21-15} = 0x4; + let Inst{14-8} = imm8{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_ST_ACCX_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_8:$imm8), + "!xtensa_ee_st_accx_ip_p, $as, $imm8", + [(int_xtensa_ee_st_accx_ip AR:$as, timm:$imm8)]>; + +def EE_ST_QACC_H_H_32_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_4:$imm4), + "ee.st.qacc_h.h.32.ip\t $as, $imm4", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm4; + + let mayStore = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm4{7}; + let Inst{21-15} = 0x24; + let Inst{14-8} = imm4{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_ST_QACC_H_H_32_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_4:$imm4), + "!xtensa_ee_st_qacc_h_h_32_ip_p, $as, $imm4", + [(int_xtensa_ee_st_qacc_h_h_32_ip AR:$as, timm:$imm4)]>; + +def EE_ST_QACC_H_L_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.st.qacc_h.l.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayStore = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0x1a; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_ST_QACC_H_L_128_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_st_qacc_h_l_128_ip_p, $as, $imm16", + [(int_xtensa_ee_st_qacc_h_l_128_ip AR:$as, timm:$imm16)]>; + +def EE_ST_QACC_L_H_32_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_4:$imm4), + "ee.st.qacc_l.h.32.ip\t $as, $imm4", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm4; + + let mayStore = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm4{7}; + let Inst{21-15} = 0x3a; + let Inst{14-8} = imm4{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_ST_QACC_L_H_32_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_4:$imm4), + "!xtensa_ee_st_qacc_l_h_32_ip_p, $as, $imm4", + [(int_xtensa_ee_st_qacc_l_h_32_ip AR:$as, timm:$imm4)]>; + +def EE_ST_QACC_L_L_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.st.qacc_l.l.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayStore = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0x18; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_ST_QACC_L_L_128_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_st_qacc_l_l_128_ip_p, $as, $imm16", + [(int_xtensa_ee_st_qacc_l_l_128_ip AR:$as, timm:$imm16)]>; + +def EE_ST_UA_STATE_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.st.ua_state.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> as; + bits<8> imm16; + + let mayStore = 1; + + let Inst{23} = 0x0; + let Inst{22} = imm16{7}; + let Inst{21-15} = 0x38; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_ST_UA_STATE_IP_P : Pseudo<(outs), (ins AR:$as, offset_256_16:$imm16), + "!xtensa_ee_st_ua_state_ip_p, $as, $imm16", + [(int_xtensa_ee_st_ua_state_ip AR:$as, timm:$imm16)]>; + +def EE_VADDS_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vadds.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x64; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S16_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s16_p, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s16 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VADDS_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vadds.s16.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x2d; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S16_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s16_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VADDS_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vadds.s16.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1c9; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x0; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s16_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s16_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VADDS_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vadds.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x74; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s32_p, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s32 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VADDS_S32_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vadds.s32.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x3d; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S32_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s32_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VADDS_S32_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vadds.s32.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1c9; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x1; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S32_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s32_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s32_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VADDS_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vadds.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x84; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S8_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s8_p, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s8 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VADDS_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vadds.s8.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x1c; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S8_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s8_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VADDS_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vadds.s8.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1c9; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x2; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VADDS_S8_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vadds_s8_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vadds_s8_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_EQ_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.eq.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x94; +} + +let usesCustomInserter = 1 in +def EE_VCMP_EQ_S16_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_eq_s16_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_eq_s16 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_EQ_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.eq.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xa4; +} + +let usesCustomInserter = 1 in +def EE_VCMP_EQ_S32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_eq_s32_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_eq_s32 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_EQ_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.eq.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xb4; +} + +let usesCustomInserter = 1 in +def EE_VCMP_EQ_S8_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_eq_s8_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_eq_s8 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_GT_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.gt.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xc4; +} + +let usesCustomInserter = 1 in +def EE_VCMP_GT_S16_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_gt_s16_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_gt_s16 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_GT_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.gt.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xd4; +} + +let usesCustomInserter = 1 in +def EE_VCMP_GT_S32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_gt_s32_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_gt_s32 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_GT_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.gt.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xe4; +} + +let usesCustomInserter = 1 in +def EE_VCMP_GT_S8_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_gt_s8_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_gt_s8 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_LT_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.lt.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xf4; +} + +let usesCustomInserter = 1 in +def EE_VCMP_LT_S16_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_lt_s16_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_lt_s16 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_LT_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.lt.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VCMP_LT_S32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_lt_s32_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_lt_s32 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VCMP_LT_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vcmp.lt.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x14; +} + +let usesCustomInserter = 1 in +def EE_VCMP_LT_S8_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vcmp_lt_s8_p, $qa, $qx, $qy", + [(int_xtensa_ee_vcmp_lt_s8 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VLDBC_16: EE_Inst24<(outs QR:$qu), (ins AR:$as), + "ee.vldbc.16\t $qu, $as", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + + let mayLoad = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-8} = 0x73; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_16_P : Pseudo<(outs), (ins imm8:$qu, AR:$as), + "!xtensa_ee_vldbc_16_p, $qu, $as", + [(int_xtensa_ee_vldbc_16 timm:$qu, AR:$as)]>; + +def EE_VLDBC_16_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_128_2:$imm2), + "ee.vldbc.16.ip\t $qu, $as, $imm2", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<7> imm2; + + let mayLoad = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0x5; + let Inst{15} = qu{0}; + let Inst{14-8} = imm2{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_16_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_128_2:$imm2), + "!xtensa_ee_vldbc_16_ip_p, $qu, $as, $imm2", + [(int_xtensa_ee_vldbc_16_ip timm:$qu, AR:$as, timm:$imm2)]>; + +def EE_VLDBC_16_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad), + "ee.vldbc.16.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-12} = 0x4; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_16_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad), + "!xtensa_ee_vldbc_16_xp_p, $qu, $as, $ad", + [(int_xtensa_ee_vldbc_16_xp timm:$qu, AR:$as, AR:$ad)]>; + +def EE_VLDBC_32: EE_Inst24<(outs QR:$qu), (ins AR:$as), + "ee.vldbc.32\t $qu, $as", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + + let mayLoad = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-8} = 0x77; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_32_P : Pseudo<(outs), (ins imm8:$qu, AR:$as), + "!xtensa_ee_vldbc_32_p, $qu, $as", + [(int_xtensa_ee_vldbc_32 timm:$qu, AR:$as)]>; + +def EE_VLDBC_32_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_4:$imm4), + "ee.vldbc.32.ip\t $qu, $as, $imm4", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm4; + + let mayLoad = 1; + + let Inst{23} = 0x1; + let Inst{22} = imm4{7}; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0x2; + let Inst{15} = qu{0}; + let Inst{14-8} = imm4{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_32_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_256_4:$imm4), + "!xtensa_ee_vldbc_32_ip_p, $qu, $as, $imm4", + [(int_xtensa_ee_vldbc_32_ip timm:$qu, AR:$as, timm:$imm4)]>; + +def EE_VLDBC_32_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad), + "ee.vldbc.32.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-12} = 0x1; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_32_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad), + "!xtensa_ee_vldbc_32_xp_p, $qu, $as, $ad", + [(int_xtensa_ee_vldbc_32_xp timm:$qu, AR:$as, AR:$ad)]>; + +def EE_VLDBC_8: EE_Inst24<(outs QR:$qu), (ins AR:$as), + "ee.vldbc.8\t $qu, $as", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + + let mayLoad = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-8} = 0x3b; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_8_P : Pseudo<(outs), (ins imm8:$qu, AR:$as), + "!xtensa_ee_vldbc_8_p, $qu, $as", + [(int_xtensa_ee_vldbc_8 timm:$qu, AR:$as)]>; + +def EE_VLDBC_8_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_128_1:$imm1), + "ee.vldbc.8.ip\t $qu, $as, $imm1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<7> imm1; + + let mayLoad = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0x5; + let Inst{15} = qu{0}; + let Inst{14-8} = imm1{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_8_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_128_1:$imm1), + "!xtensa_ee_vldbc_8_ip_p, $qu, $as, $imm1", + [(int_xtensa_ee_vldbc_8_ip timm:$qu, AR:$as, timm:$imm1)]>; + +def EE_VLDBC_8_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad), + "ee.vldbc.8.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-12} = 0x5; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDBC_8_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad), + "!xtensa_ee_vldbc_8_xp_p, $qu, $as, $ad", + [(int_xtensa_ee_vldbc_8_xp timm:$qu, AR:$as, AR:$ad)]>; + +def EE_VLDHBC_16_INCP: EE_Inst24<(outs QR:$qu, QR:$qu1, AR:$asr), (ins AR:$as), + "ee.vldhbc.16.incp\t $qu, $qu1, $as", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<3> qu1; + bits<4> as; + + let mayLoad = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qu{0}; + let Inst{14-12} = qu1{2-0}; + let Inst{11-8} = 0x2; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLDHBC_16_INCP_P : Pseudo<(outs), (ins imm8:$qu, imm8:$qu1, AR:$as), + "!xtensa_ee_vldhbc_16_incp_p, $qu, $qu1, $as", + [(int_xtensa_ee_vldhbc_16_incp timm:$qu, timm:$qu1, AR:$as)]>; + +def EE_VLD_128_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_16:$imm16), + "ee.vld.128.ip\t $qu, $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + + let mayLoad = 1; + + let Inst{23} = 0x1; + let Inst{22} = imm16{7}; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0x3; + let Inst{15} = qu{0}; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLD_128_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_256_16:$imm16), + "!xtensa_ee_vld_128_ip_p, $qu, $as, $imm16", + [(int_xtensa_ee_vld_128_ip timm:$qu, AR:$as, timm:$imm16)]>; + +def EE_VLD_128_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad), + "ee.vld.128.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-12} = 0x2; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLD_128_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad), + "!xtensa_ee_vld_128_xp_p, $qu, $as, $ad", + [(int_xtensa_ee_vld_128_xp timm:$qu, AR:$as, AR:$ad)]>; + +def EE_VLD_H_64_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_8:$imm8), + "ee.vld.h.64.ip\t $qu, $as, $imm8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm8; + + let mayLoad = 1; + + let Inst{23} = 0x1; + let Inst{22} = imm8{7}; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0x8; + let Inst{15} = qu{0}; + let Inst{14-8} = imm8{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLD_H_64_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_256_8:$imm8), + "!xtensa_ee_vld_h_64_ip_p, $qu, $as, $imm8", + [(int_xtensa_ee_vld_h_64_ip timm:$qu, AR:$as, timm:$imm8)]>; + +def EE_VLD_H_64_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad), + "ee.vld.h.64.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-12} = 0x6; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLD_H_64_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad), + "!xtensa_ee_vld_h_64_xp_p, $qu, $as, $ad", + [(int_xtensa_ee_vld_h_64_xp timm:$qu, AR:$as, AR:$ad)]>; + +def EE_VLD_L_64_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_8:$imm8), + "ee.vld.l.64.ip\t $qu, $as, $imm8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm8; + + let mayLoad = 1; + + let Inst{23} = 0x1; + let Inst{22} = imm8{7}; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0x9; + let Inst{15} = qu{0}; + let Inst{14-8} = imm8{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLD_L_64_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_256_8:$imm8), + "!xtensa_ee_vld_l_64_ip_p, $qu, $as, $imm8", + [(int_xtensa_ee_vld_l_64_ip timm:$qu, AR:$as, timm:$imm8)]>; + +def EE_VLD_L_64_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad), + "ee.vld.l.64.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + + let mayLoad = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qu{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qu{0}; + let Inst{14-12} = 0x3; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VLD_L_64_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad), + "!xtensa_ee_vld_l_64_xp_p, $qu, $as, $ad", + [(int_xtensa_ee_vld_l_64_xp timm:$qu, AR:$as, AR:$ad)]>; + +def EE_VMAX_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vmax.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x24; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S16_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s16_p, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s16 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMAX_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmax.s16.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x1d; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S16_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s16_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMAX_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmax.s16.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1c9; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x3; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s16_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s16_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMAX_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vmax.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x34; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s32_p, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s32 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMAX_S32_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmax.s32.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x1e; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S32_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s32_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMAX_S32_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmax.s32.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1ca; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x0; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S32_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s32_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s32_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMAX_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vmax.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x44; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S8_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s8_p, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s8 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMAX_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmax.s8.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x1f; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S8_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s8_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMAX_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmax.s8.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1cb; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x0; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMAX_S8_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmax_s8_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmax_s8_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vmin.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x54; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S16_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s16_p, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s16 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmin.s16.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x2e; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S16_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s16_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmin.s16.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1ca; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x1; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s16_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s16_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vmin.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x64; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s32_p, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s32 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S32_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmin.s32.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x3e; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S32_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s32_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S32_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmin.s32.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1cb; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x1; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S32_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s32_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s32_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vmin.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x74; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S8_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s8_p, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s8 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmin.s8.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x2f; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S8_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s8_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMIN_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmin.s8.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1ca; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x2; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMIN_S8_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmin_s8_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vmin_s8_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S16_ACCX: EE_Inst24<(outs), (ins QR:$qx, QR:$qy), + "ee.vmulas.s16.accx\t $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + + + let Inst{23-15} = 0x34; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x84; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_ACCX_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s16_accx_p, $qx, $qy", + [(int_xtensa_ee_vmulas_s16_accx timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S16_ACCX_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy), + "ee.vmulas.s16.accx.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-25} = 0xf; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x0; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x0; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_ACCX_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s16_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy", + [(int_xtensa_ee_vmulas_s16_accx_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S16_ACCX_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s16.accx.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-25} = 0x0; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_ACCX_LD_IP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s16_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s16_accx_ld_ip_qup timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S16_ACCX_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy), + "ee.vmulas.s16.accx.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x3c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x0; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x1; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_ACCX_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s16_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy", + [(int_xtensa_ee_vmulas_s16_accx_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S16_ACCX_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s16.accx.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x2c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_ACCX_LD_XP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s16_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s16_accx_ld_xp_qup timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S16_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy), + "ee.vmulas.s16.qacc\t $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + + + let Inst{23-15} = 0x34; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x84; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_QACC_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s16_qacc_p, $qx, $qy", + [(int_xtensa_ee_vmulas_s16_qacc timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S16_QACC_LDBC_INCP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmulas.s16.qacc.ldbc.incp\t $qu, $as, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{23-21} = 0x4; + let Inst{20} = qu{2}; + let Inst{19-16} = 0x7; + let Inst{15} = qu{1}; + let Inst{14} = qy{2}; + let Inst{13} = qu{0}; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_QACC_LDBC_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s16_qacc_ldbc_incp_p, $qu, $as, $qx, $qy", + [(int_xtensa_ee_vmulas_s16_qacc_ldbc_incp timm:$qu, AR:$as, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S16_QACC_LDBC_INCP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s16.qacc.ldbc.incp.qup\t $qu, $as, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = 0x8; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup timm:$qu, AR:$as, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S16_QACC_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy), + "ee.vmulas.s16.qacc.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-25} = 0xf; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x1; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x0; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_QACC_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s16_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy", + [(int_xtensa_ee_vmulas_s16_qacc_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S16_QACC_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s16.qacc.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-25} = 0x1; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_QACC_LD_IP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s16_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s16_qacc_ld_ip_qup timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S16_QACC_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy), + "ee.vmulas.s16.qacc.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x3c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x1; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x1; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_QACC_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s16_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy", + [(int_xtensa_ee_vmulas_s16_qacc_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S16_QACC_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s16.qacc.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x2d; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S16_QACC_LD_XP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s16_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s16_qacc_ld_xp_qup timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S8_ACCX: EE_Inst24<(outs), (ins QR:$qx, QR:$qy), + "ee.vmulas.s8.accx\t $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + + + let Inst{23-15} = 0x34; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xc4; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_ACCX_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s8_accx_p, $qx, $qy", + [(int_xtensa_ee_vmulas_s8_accx timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S8_ACCX_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy), + "ee.vmulas.s8.accx.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-25} = 0xf; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x2; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x0; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_ACCX_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s8_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy", + [(int_xtensa_ee_vmulas_s8_accx_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S8_ACCX_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s8.accx.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-25} = 0x2; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_ACCX_LD_IP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s8_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s8_accx_ld_ip_qup timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S8_ACCX_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy), + "ee.vmulas.s8.accx.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x3c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x2; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x1; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_ACCX_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s8_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy", + [(int_xtensa_ee_vmulas_s8_accx_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S8_ACCX_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s8.accx.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x2e; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_ACCX_LD_XP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s8_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s8_accx_ld_xp_qup timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S8_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy), + "ee.vmulas.s8.qacc\t $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + + + let Inst{23-15} = 0x34; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xc4; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_QACC_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s8_qacc_p, $qx, $qy", + [(int_xtensa_ee_vmulas_s8_qacc timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S8_QACC_LDBC_INCP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmulas.s8.qacc.ldbc.incp\t $qu, $as, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{23-21} = 0x5; + let Inst{20} = qu{2}; + let Inst{19-16} = 0x7; + let Inst{15} = qu{1}; + let Inst{14} = qy{2}; + let Inst{13} = qu{0}; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_QACC_LDBC_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s8_qacc_ldbc_incp_p, $qu, $as, $qx, $qy", + [(int_xtensa_ee_vmulas_s8_qacc_ldbc_incp timm:$qu, AR:$as, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S8_QACC_LDBC_INCP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s8.qacc.ldbc.incp.qup\t $qu, $as, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = 0x9; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup timm:$qu, AR:$as, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S8_QACC_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy), + "ee.vmulas.s8.qacc.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-25} = 0xf; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x3; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x0; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_QACC_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s8_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy", + [(int_xtensa_ee_vmulas_s8_qacc_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S8_QACC_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s8.qacc.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-25} = 0x3; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_QACC_LD_IP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s8_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s8_qacc_ld_ip_qup timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_S8_QACC_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy), + "ee.vmulas.s8.qacc.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x3c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x3; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x1; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_QACC_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_s8_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy", + [(int_xtensa_ee_vmulas_s8_qacc_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_S8_QACC_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.s8.qacc.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x2f; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_S8_QACC_LD_XP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_s8_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_s8_qacc_ld_xp_qup timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U16_ACCX: EE_Inst24<(outs), (ins QR:$qx, QR:$qy), + "ee.vmulas.u16.accx\t $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + + + let Inst{23-15} = 0x14; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x84; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_ACCX_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u16_accx_p, $qx, $qy", + [(int_xtensa_ee_vmulas_u16_accx timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U16_ACCX_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy), + "ee.vmulas.u16.accx.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-25} = 0xf; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x4; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x0; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_ACCX_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u16_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy", + [(int_xtensa_ee_vmulas_u16_accx_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U16_ACCX_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u16.accx.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-25} = 0x4; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_ACCX_LD_IP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u16_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u16_accx_ld_ip_qup timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U16_ACCX_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy), + "ee.vmulas.u16.accx.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x3c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x4; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x1; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_ACCX_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u16_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy", + [(int_xtensa_ee_vmulas_u16_accx_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U16_ACCX_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u16.accx.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x30; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_ACCX_LD_XP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u16_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u16_accx_ld_xp_qup timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U16_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy), + "ee.vmulas.u16.qacc\t $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + + + let Inst{23-15} = 0x14; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x84; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_QACC_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u16_qacc_p, $qx, $qy", + [(int_xtensa_ee_vmulas_u16_qacc timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U16_QACC_LDBC_INCP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmulas.u16.qacc.ldbc.incp\t $qu, $as, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{23-21} = 0x6; + let Inst{20} = qu{2}; + let Inst{19-16} = 0x7; + let Inst{15} = qu{1}; + let Inst{14} = qy{2}; + let Inst{13} = qu{0}; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_QACC_LDBC_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u16_qacc_ldbc_incp_p, $qu, $as, $qx, $qy", + [(int_xtensa_ee_vmulas_u16_qacc_ldbc_incp timm:$qu, AR:$as, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U16_QACC_LDBC_INCP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u16.qacc.ldbc.incp.qup\t $qu, $as, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = 0xa; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup timm:$qu, AR:$as, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U16_QACC_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy), + "ee.vmulas.u16.qacc.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-25} = 0xf; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x5; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x0; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_QACC_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u16_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy", + [(int_xtensa_ee_vmulas_u16_qacc_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U16_QACC_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u16.qacc.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-25} = 0x5; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_QACC_LD_IP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u16_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u16_qacc_ld_ip_qup timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U16_QACC_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy), + "ee.vmulas.u16.qacc.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x3c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x5; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x1; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_QACC_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u16_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy", + [(int_xtensa_ee_vmulas_u16_qacc_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U16_QACC_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u16.qacc.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x31; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U16_QACC_LD_XP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u16_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u16_qacc_ld_xp_qup timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U8_ACCX: EE_Inst24<(outs), (ins QR:$qx, QR:$qy), + "ee.vmulas.u8.accx\t $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + + + let Inst{23-15} = 0x14; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xc4; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_ACCX_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u8_accx_p, $qx, $qy", + [(int_xtensa_ee_vmulas_u8_accx timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U8_ACCX_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy), + "ee.vmulas.u8.accx.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-25} = 0xf; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x6; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x0; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_ACCX_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u8_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy", + [(int_xtensa_ee_vmulas_u8_accx_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U8_ACCX_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u8.accx.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-25} = 0x6; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_ACCX_LD_IP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u8_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u8_accx_ld_ip_qup timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U8_ACCX_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy), + "ee.vmulas.u8.accx.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x3c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x6; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x1; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_ACCX_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u8_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy", + [(int_xtensa_ee_vmulas_u8_accx_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U8_ACCX_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u8.accx.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x32; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_ACCX_LD_XP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u8_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u8_accx_ld_xp_qup timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U8_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy), + "ee.vmulas.u8.qacc\t $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + + + let Inst{23-15} = 0x14; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xc4; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_QACC_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u8_qacc_p, $qx, $qy", + [(int_xtensa_ee_vmulas_u8_qacc timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U8_QACC_LDBC_INCP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmulas.u8.qacc.ldbc.incp\t $qu, $as, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{23-21} = 0x7; + let Inst{20} = qu{2}; + let Inst{19-16} = 0x7; + let Inst{15} = qu{1}; + let Inst{14} = qy{2}; + let Inst{13} = qu{0}; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_QACC_LDBC_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u8_qacc_ldbc_incp_p, $qu, $as, $qx, $qy", + [(int_xtensa_ee_vmulas_u8_qacc_ldbc_incp timm:$qu, AR:$as, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U8_QACC_LDBC_INCP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u8.qacc.ldbc.incp.qup\t $qu, $as, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = 0xb; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup timm:$qu, AR:$as, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U8_QACC_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy), + "ee.vmulas.u8.qacc.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-25} = 0xf; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x7; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x0; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_QACC_LD_IP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u8_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy", + [(int_xtensa_ee_vmulas_u8_qacc_ld_ip timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U8_QACC_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u8.qacc.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<8> imm16; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-25} = 0x7; + let Inst{24-23} = imm16{5-4}; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = imm16{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_QACC_LD_IP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, offset_64_16:$imm16, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u8_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u8_qacc_ld_ip_qup timm:$qu, AR:$as, timm:$imm16, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMULAS_U8_QACC_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy), + "ee.vmulas.u8.qacc.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x3c; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = 0x7; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = 0x1; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_QACC_LD_XP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmulas_u8_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy", + [(int_xtensa_ee_vmulas_u8_qacc_ld_xp timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy)]>; + +def EE_VMULAS_U8_QACC_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1), + "ee.vmulas.u8.qacc.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<4> ad; + bits<3> qx; + bits<3> qy; + bits<3> qs0; + bits<3> qs1; + + let mayLoad = 1; + + let Inst{28-23} = 0x33; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qs1{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qs0{2-0}; + let Inst{7-4} = ad{3-0}; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMULAS_U8_QACC_LD_XP_QUP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, AR:$ad, imm8:$qx, imm8:$qy, imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vmulas_u8_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1", + [(int_xtensa_ee_vmulas_u8_qacc_ld_xp_qup timm:$qu, AR:$as, AR:$ad, timm:$qx, timm:$qy, timm:$qs0, timm:$qs1)]>; + +def EE_VMUL_S16: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "ee.vmul.s16\t $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qz; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qz{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qz{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x84; +} + +let usesCustomInserter = 1 in +def EE_VMUL_S16_P : Pseudo<(outs), (ins imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_s16_p, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_s16 timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmul.s16.ld.incp\t $qu, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x3f; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMUL_S16_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_s16_ld_incp_p, $qu, $as, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_s16_ld_incp timm:$qu, AR:$as, timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmul.s16.st.incp\t $qv, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1cb; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x2; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMUL_S16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_s16_st_incp_p, $qv, $as, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_s16_st_incp timm:$qv, AR:$as, timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_S8: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "ee.vmul.s8\t $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qz; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qz{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qz{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0x94; +} + +let usesCustomInserter = 1 in +def EE_VMUL_S8_P : Pseudo<(outs), (ins imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_s8_p, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_s8 timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmul.s8.ld.incp\t $qu, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x4c; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMUL_S8_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_s8_ld_incp_p, $qu, $as, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_s8_ld_incp timm:$qu, AR:$as, timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmul.s8.st.incp\t $qv, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1ca; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x3; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMUL_S8_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_s8_st_incp_p, $qv, $as, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_s8_st_incp timm:$qv, AR:$as, timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_U16: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "ee.vmul.u16\t $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qz; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qz{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qz{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xa4; +} + +let usesCustomInserter = 1 in +def EE_VMUL_U16_P : Pseudo<(outs), (ins imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_u16_p, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_u16 timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_U16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmul.u16.ld.incp\t $qu, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x5c; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMUL_U16_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_u16_ld_incp_p, $qu, $as, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_u16_ld_incp timm:$qu, AR:$as, timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_U16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmul.u16.st.incp\t $qv, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1cb; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x3; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMUL_U16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_u16_st_incp_p, $qv, $as, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_u16_st_incp timm:$qv, AR:$as, timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_U8: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "ee.vmul.u8\t $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qz; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qz{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qz{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xb4; +} + +let usesCustomInserter = 1 in +def EE_VMUL_U8_P : Pseudo<(outs), (ins imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_u8_p, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_u8 timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_U8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vmul.u8.ld.incp\t $qu, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x6c; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMUL_U8_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_u8_ld_incp_p, $qu, $as, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_u8_ld_incp timm:$qu, AR:$as, timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VMUL_U8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vmul.u8.st.incp\t $qv, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qz; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1d1; + let Inst{19-17} = qz{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x0; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VMUL_U8_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qz, imm8:$qx, imm8:$qy), + "!xtensa_ee_vmul_u8_st_incp_p, $qv, $as, $qz, $qx, $qy", + [(int_xtensa_ee_vmul_u8_st_incp timm:$qv, AR:$as, timm:$qz, timm:$qx, timm:$qy)]>; + +def EE_VPRELU_S16: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy, AR:$ay), + "ee.vprelu.s16\t $qz, $qx, $qy, $ay", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qz; + bits<3> qx; + bits<3> qy; + bits<4> ay; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qz{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qz{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-4} = ay{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VPRELU_S16_P : Pseudo<(outs), (ins imm8:$qz, imm8:$qx, imm8:$qy, AR:$ay), + "!xtensa_ee_vprelu_s16_p, $qz, $qx, $qy, $ay", + [(int_xtensa_ee_vprelu_s16 timm:$qz, timm:$qx, timm:$qy, AR:$ay)]>; + +def EE_VPRELU_S8: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy, AR:$ay), + "ee.vprelu.s8\t $qz, $qx, $qy, $ay", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qz; + bits<3> qx; + bits<3> qy; + bits<4> ay; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qz{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qz{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-4} = ay{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VPRELU_S8_P : Pseudo<(outs), (ins imm8:$qz, imm8:$qx, imm8:$qy, AR:$ay), + "!xtensa_ee_vprelu_s8_p, $qz, $qx, $qy, $ay", + [(int_xtensa_ee_vprelu_s8 timm:$qz, timm:$qx, timm:$qy, AR:$ay)]>; + +def EE_VRELU_S16: EE_Inst24<(outs QR:$qsr), (ins QR:$qs, AR:$ax, AR:$ay), + "ee.vrelu.s16\t $qs, $ax, $ay", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs; + bits<4> ax; + bits<4> ay; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-12} = 0x1; + let Inst{11-8} = ax{3-0}; + let Inst{7-4} = ay{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VRELU_S16_P : Pseudo<(outs), (ins imm8:$qs, AR:$ax, AR:$ay), + "!xtensa_ee_vrelu_s16_p, $qs, $ax, $ay", + [(int_xtensa_ee_vrelu_s16 timm:$qs, AR:$ax, AR:$ay)]>; + +def EE_VRELU_S8: EE_Inst24<(outs QR:$qsr), (ins QR:$qs, AR:$ax, AR:$ay), + "ee.vrelu.s8\t $qs, $ax, $ay", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs; + bits<4> ax; + bits<4> ay; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-12} = 0x5; + let Inst{11-8} = ax{3-0}; + let Inst{7-4} = ay{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VRELU_S8_P : Pseudo<(outs), (ins imm8:$qs, AR:$ax, AR:$ay), + "!xtensa_ee_vrelu_s8_p, $qs, $ax, $ay", + [(int_xtensa_ee_vrelu_s8 timm:$qs, AR:$ax, AR:$ay)]>; + +def EE_VSL_32: EE_Inst24<(outs QR:$qa), (ins QR:$qs), + "ee.vsl.32\t $qa, $qs", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qs; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-7} = 0x7e; + let Inst{6-4} = qa{2-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VSL_32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qs), + "!xtensa_ee_vsl_32_p, $qa, $qs", + [(int_xtensa_ee_vsl_32 timm:$qa, timm:$qs)]>; + +def EE_VSMULAS_S16_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy, select_8:$sel8), + "ee.vsmulas.s16.qacc\t $qx, $qy, $sel8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + bits<3> sel8; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = sel8{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = sel8{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xc4; +} + +let usesCustomInserter = 1 in +def EE_VSMULAS_S16_QACC_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy, select_8:$sel8), + "!xtensa_ee_vsmulas_s16_qacc_p, $qx, $qy, $sel8", + [(int_xtensa_ee_vsmulas_s16_qacc timm:$qx, timm:$qy, timm:$sel8)]>; + +def EE_VSMULAS_S16_QACC_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy, select_8:$sel8), + "ee.vsmulas.s16.qacc.ld.incp\t $qu, $as, $qx, $qy, $sel8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + bits<3> sel8; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = sel8{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x7c; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VSMULAS_S16_QACC_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy, select_8:$sel8), + "!xtensa_ee_vsmulas_s16_qacc_ld_incp_p, $qu, $as, $qx, $qy, $sel8", + [(int_xtensa_ee_vsmulas_s16_qacc_ld_incp timm:$qu, AR:$as, timm:$qx, timm:$qy, timm:$sel8)]>; + +def EE_VSMULAS_S8_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy, select_16:$sel16), + "ee.vsmulas.s8.qacc\t $qx, $qy, $sel16", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qx; + bits<3> qy; + bits<4> sel16; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = sel16{3-2}; + let Inst{19-16} = 0xe; + let Inst{15} = sel16{1}; + let Inst{14} = qy{2}; + let Inst{13} = 0x0; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-5} = 0x2; + let Inst{4} = sel16{0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VSMULAS_S8_QACC_P : Pseudo<(outs), (ins imm8:$qx, imm8:$qy, select_16:$sel16), + "!xtensa_ee_vsmulas_s8_qacc_p, $qx, $qy, $sel16", + [(int_xtensa_ee_vsmulas_s8_qacc timm:$qx, timm:$qy, timm:$sel16)]>; + +def EE_VSMULAS_S8_QACC_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy, select_16:$sel16), + "ee.vsmulas.s8.qacc.ld.incp\t $qu, $as, $qx, $qy, $sel16", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qx; + bits<3> qy; + bits<4> sel16; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = sel16{3-1}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-9} = 0x1; + let Inst{8} = sel16{0}; + let Inst{7-4} = 0xc; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VSMULAS_S8_QACC_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qx, imm8:$qy, select_16:$sel16), + "!xtensa_ee_vsmulas_s8_qacc_ld_incp_p, $qu, $as, $qx, $qy, $sel16", + [(int_xtensa_ee_vsmulas_s8_qacc_ld_incp timm:$qu, AR:$as, timm:$qx, timm:$qy, timm:$sel16)]>; + +def EE_VSR_32: EE_Inst24<(outs QR:$qa), (ins QR:$qs), + "ee.vsr.32\t $qa, $qs", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qs; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qs{0}; + let Inst{14-7} = 0x7f; + let Inst{6-4} = qa{2-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VSR_32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qs), + "!xtensa_ee_vsr_32_p, $qa, $qs", + [(int_xtensa_ee_vsr_32 timm:$qa, timm:$qs)]>; + +def EE_VST_128_IP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, offset_256_16:$imm16), + "ee.vst.128.ip\t $qv, $as, $imm16", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<8> imm16; + + let mayStore = 1; + + let Inst{23} = 0x1; + let Inst{22} = imm16{7}; + let Inst{21-20} = qv{2-1}; + let Inst{19-16} = 0xa; + let Inst{15} = qv{0}; + let Inst{14-8} = imm16{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VST_128_IP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, offset_256_16:$imm16), + "!xtensa_ee_vst_128_ip_p, $qv, $as, $imm16", + [(int_xtensa_ee_vst_128_ip timm:$qv, AR:$as, timm:$imm16)]>; + +def EE_VST_128_XP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, AR:$ad), + "ee.vst.128.xp\t $qv, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<4> ad; + + let mayStore = 1; + + let Inst{23-22} = 0x2; + let Inst{21-20} = qv{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qv{0}; + let Inst{14-12} = 0x7; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VST_128_XP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, AR:$ad), + "!xtensa_ee_vst_128_xp_p, $qv, $as, $ad", + [(int_xtensa_ee_vst_128_xp timm:$qv, AR:$as, AR:$ad)]>; + +def EE_VST_H_64_IP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, offset_256_8:$imm8), + "ee.vst.h.64.ip\t $qv, $as, $imm8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<8> imm8; + + let mayStore = 1; + + let Inst{23} = 0x1; + let Inst{22} = imm8{7}; + let Inst{21-20} = qv{2-1}; + let Inst{19-16} = 0xb; + let Inst{15} = qv{0}; + let Inst{14-8} = imm8{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VST_H_64_IP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, offset_256_8:$imm8), + "!xtensa_ee_vst_h_64_ip_p, $qv, $as, $imm8", + [(int_xtensa_ee_vst_h_64_ip timm:$qv, AR:$as, timm:$imm8)]>; + +def EE_VST_H_64_XP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, AR:$ad), + "ee.vst.h.64.xp\t $qv, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<4> ad; + + let mayStore = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qv{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qv{0}; + let Inst{14-12} = 0x0; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VST_H_64_XP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, AR:$ad), + "!xtensa_ee_vst_h_64_xp_p, $qv, $as, $ad", + [(int_xtensa_ee_vst_h_64_xp timm:$qv, AR:$as, AR:$ad)]>; + +def EE_VST_L_64_IP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, offset_256_8:$imm8), + "ee.vst.l.64.ip\t $qv, $as, $imm8", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<8> imm8; + + let mayStore = 1; + + let Inst{23} = 0x1; + let Inst{22} = imm8{7}; + let Inst{21-20} = qv{2-1}; + let Inst{19-16} = 0x4; + let Inst{15} = qv{0}; + let Inst{14-8} = imm8{6-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VST_L_64_IP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, offset_256_8:$imm8), + "!xtensa_ee_vst_l_64_ip_p, $qv, $as, $imm8", + [(int_xtensa_ee_vst_l_64_ip timm:$qv, AR:$as, timm:$imm8)]>; + +def EE_VST_L_64_XP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, AR:$ad), + "ee.vst.l.64.xp\t $qv, $as, $ad", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<4> ad; + + let mayStore = 1; + + let Inst{23-22} = 0x3; + let Inst{21-20} = qv{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qv{0}; + let Inst{14-12} = 0x4; + let Inst{11-8} = ad{3-0}; + let Inst{7-4} = as{3-0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_VST_L_64_XP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, AR:$ad), + "!xtensa_ee_vst_l_64_xp_p, $qv, $as, $ad", + [(int_xtensa_ee_vst_l_64_xp timm:$qv, AR:$as, AR:$ad)]>; + +def EE_VSUBS_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vsubs.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xd4; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S16_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s16_p, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s16 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VSUBS_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vsubs.s16.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x4d; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S16_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s16_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VSUBS_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vsubs.s16.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1d1; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x1; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S16_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s16_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s16_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VSUBS_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vsubs.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xe4; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S32_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s32_p, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s32 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VSUBS_S32_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vsubs.s32.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x5d; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S32_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s32_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VSUBS_S32_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vsubs.s32.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1d1; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x2; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S32_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s32_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s32_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VSUBS_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.vsubs.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xe; + let Inst{15} = qa{0}; + let Inst{14} = qy{2}; + let Inst{13} = 0x1; + let Inst{12-11} = qy{1-0}; + let Inst{10-8} = qx{2-0}; + let Inst{7-0} = 0xf4; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S8_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s8_p, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s8 timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VSUBS_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy), + "ee.vsubs.s8.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qu; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayLoad = 1; + + let Inst{28-23} = 0x38; + let Inst{22-20} = qu{2-0}; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-4} = 0x6d; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S8_LD_INCP_P : Pseudo<(outs), (ins imm8:$qu, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s8_ld_incp timm:$qu, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VSUBS_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy), + "ee.vsubs.s8.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qv; + bits<4> as; + bits<3> qa; + bits<3> qx; + bits<3> qy; + + let mayStore = 1; + + let Inst{28-20} = 0x1d1; + let Inst{19-17} = qa{2-0}; + let Inst{16-14} = qx{2-0}; + let Inst{13-11} = qy{2-0}; + let Inst{10-8} = qv{2-0}; + let Inst{7-4} = 0x3; + let Inst{3-0} = as{3-0}; +} + +let usesCustomInserter = 1 in +def EE_VSUBS_S8_ST_INCP_P : Pseudo<(outs), (ins imm8:$qv, AR:$as, imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_vsubs_s8_st_incp_p, $qv, $as, $qa, $qx, $qy", + [(int_xtensa_ee_vsubs_s8_st_incp timm:$qv, AR:$as, timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_VUNZIP_16: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1), + "ee.vunzip.16\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs0; + bits<3> qs1; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-0} = 0x384; +} + +let usesCustomInserter = 1 in +def EE_VUNZIP_16_P : Pseudo<(outs), (ins imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vunzip_16_p, $qs0, $qs1", + [(int_xtensa_ee_vunzip_16 timm:$qs0, timm:$qs1)]>; + +def EE_VUNZIP_32: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1), + "ee.vunzip.32\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs0; + bits<3> qs1; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-0} = 0x394; +} + +let usesCustomInserter = 1 in +def EE_VUNZIP_32_P : Pseudo<(outs), (ins imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vunzip_32_p, $qs0, $qs1", + [(int_xtensa_ee_vunzip_32 timm:$qs0, timm:$qs1)]>; + +def EE_VUNZIP_8: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1), + "ee.vunzip.8\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs0; + bits<3> qs1; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-0} = 0x3a4; +} + +let usesCustomInserter = 1 in +def EE_VUNZIP_8_P : Pseudo<(outs), (ins imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vunzip_8_p, $qs0, $qs1", + [(int_xtensa_ee_vunzip_8 timm:$qs0, timm:$qs1)]>; + +def EE_VZIP_16: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1), + "ee.vzip.16\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs0; + bits<3> qs1; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-0} = 0x3b4; +} + +let usesCustomInserter = 1 in +def EE_VZIP_16_P : Pseudo<(outs), (ins imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vzip_16_p, $qs0, $qs1", + [(int_xtensa_ee_vzip_16 timm:$qs0, timm:$qs1)]>; + +def EE_VZIP_32: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1), + "ee.vzip.32\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs0; + bits<3> qs1; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-0} = 0x3c4; +} + +let usesCustomInserter = 1 in +def EE_VZIP_32_P : Pseudo<(outs), (ins imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vzip_32_p, $qs0, $qs1", + [(int_xtensa_ee_vzip_32 timm:$qs0, timm:$qs1)]>; + +def EE_VZIP_8: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1), + "ee.vzip.8\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qs0; + bits<3> qs1; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qs1{2-1}; + let Inst{19-16} = 0xc; + let Inst{15} = qs1{0}; + let Inst{14-12} = qs0{2-0}; + let Inst{11-0} = 0x3d4; +} + +let usesCustomInserter = 1 in +def EE_VZIP_8_P : Pseudo<(outs), (ins imm8:$qs0, imm8:$qs1), + "!xtensa_ee_vzip_8_p, $qs0, $qs1", + [(int_xtensa_ee_vzip_8 timm:$qs0, timm:$qs1)]>; + +def EE_XORQ: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy), + "ee.xorq\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + bits<3> qx; + bits<3> qy; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qa{0}; + let Inst{14-12} = 0x3; + let Inst{11-10} = qy{2-1}; + let Inst{9-8} = 0x1; + let Inst{7-6} = qx{2-1}; + let Inst{5} = qy{0}; + let Inst{4} = qx{0}; + let Inst{3-0} = 0x4; +} + +let usesCustomInserter = 1 in +def EE_XORQ_P : Pseudo<(outs), (ins imm8:$qa, imm8:$qx, imm8:$qy), + "!xtensa_ee_xorq_p, $qa, $qx, $qy", + [(int_xtensa_ee_xorq timm:$qa, timm:$qx, timm:$qy)]>; + +def EE_ZERO_ACCX: EE_Inst24<(outs), (ins), + "ee.zero.accx\t", []>, Requires<[HasESP32S3Ops]> +{ + + + let Inst{23-0} = 0x250804; +} + +let usesCustomInserter = 1 in +def EE_ZERO_ACCX_P : Pseudo<(outs), (ins), + "!xtensa_ee_zero_accx_p", + [(int_xtensa_ee_zero_accx)]>; + +def EE_ZERO_Q: EE_Inst24<(outs QR:$qa), (ins), + "ee.zero.q\t $qa", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> qa; + + + let Inst{23-22} = 0x3; + let Inst{21-20} = qa{2-1}; + let Inst{19-16} = 0xd; + let Inst{15} = qa{0}; + let Inst{14-0} = 0x7fa4; +} + +let usesCustomInserter = 1 in +def EE_ZERO_Q_P : Pseudo<(outs), (ins imm8:$qa), + "!xtensa_ee_zero_q_p, $qa", + [(int_xtensa_ee_zero_q timm:$qa)]>; + +def EE_ZERO_QACC: EE_Inst24<(outs), (ins), + "ee.zero.qacc\t", []>, Requires<[HasESP32S3Ops]> +{ + + + let Inst{23-0} = 0x250844; +} + +let usesCustomInserter = 1 in +def EE_ZERO_QACC_P : Pseudo<(outs), (ins), + "!xtensa_ee_zero_qacc_p", + [(int_xtensa_ee_zero_qacc)]>; + +def RUR_ACCX_0: EE_Inst24<(outs AR:$arr), (ins), + "rur.accx_0\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x0; +} + +def : Pat<(i32 (int_xtensa_rur_accx_0)), (RUR_ACCX_0)>; + +def RUR_ACCX_1: EE_Inst24<(outs AR:$arr), (ins), + "rur.accx_1\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x10; +} + +def : Pat<(i32 (int_xtensa_rur_accx_1)), (RUR_ACCX_1)>; + +def RUR_FFT_BIT_WIDTH: EE_Inst24<(outs AR:$arr), (ins), + "rur.fft_bit_width\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0xe0; +} + +def : Pat<(i32 (int_xtensa_rur_fft_bit_width)), (RUR_FFT_BIT_WIDTH)>; + +def RUR_GPIO_OUT: EE_Inst24<(outs AR:$arr), (ins), + "rur.gpio_out\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0xc0; +} + +def : Pat<(i32 (int_xtensa_rur_gpio_out)), (RUR_GPIO_OUT)>; + +def RUR_QACC_H_0: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_h_0\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x20; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_h_0)), (RUR_QACC_H_0)>; + +def RUR_QACC_H_1: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_h_1\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x30; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_h_1)), (RUR_QACC_H_1)>; + +def RUR_QACC_H_2: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_h_2\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x40; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_h_2)), (RUR_QACC_H_2)>; + +def RUR_QACC_H_3: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_h_3\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x50; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_h_3)), (RUR_QACC_H_3)>; + +def RUR_QACC_H_4: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_h_4\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x60; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_h_4)), (RUR_QACC_H_4)>; + +def RUR_QACC_L_0: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_l_0\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x70; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_l_0)), (RUR_QACC_L_0)>; + +def RUR_QACC_L_1: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_l_1\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x80; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_l_1)), (RUR_QACC_L_1)>; + +def RUR_QACC_L_2: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_l_2\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x90; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_l_2)), (RUR_QACC_L_2)>; + +def RUR_QACC_L_3: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_l_3\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0xa0; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_l_3)), (RUR_QACC_L_3)>; + +def RUR_QACC_L_4: EE_Inst24<(outs AR:$arr), (ins), + "rur.qacc_l_4\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0xb0; +} + +def : Pat<(i32 (int_xtensa_rur_qacc_l_4)), (RUR_QACC_L_4)>; + +def RUR_SAR_BYTE: EE_Inst24<(outs AR:$arr), (ins), + "rur.sar_byte\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0xd0; +} + +def : Pat<(i32 (int_xtensa_rur_sar_byte)), (RUR_SAR_BYTE)>; + +def RUR_UA_STATE_0: EE_Inst24<(outs AR:$arr), (ins), + "rur.ua_state_0\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0xf0; +} + +def : Pat<(i32 (int_xtensa_rur_ua_state_0)), (RUR_UA_STATE_0)>; + +def RUR_UA_STATE_1: EE_Inst24<(outs AR:$arr), (ins), + "rur.ua_state_1\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x100; +} + +def : Pat<(i32 (int_xtensa_rur_ua_state_1)), (RUR_UA_STATE_1)>; + +def RUR_UA_STATE_2: EE_Inst24<(outs AR:$arr), (ins), + "rur.ua_state_2\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x110; +} + +def : Pat<(i32 (int_xtensa_rur_ua_state_2)), (RUR_UA_STATE_2)>; + +def RUR_UA_STATE_3: EE_Inst24<(outs AR:$arr), (ins), + "rur.ua_state_3\t $arr", []>, Requires<[HasESP32S3Ops]> +{ + bits<4> arr; + + + let Inst{23-16} = 0xe3; + let Inst{15-12} = arr{3-0}; + let Inst{11-0} = 0x120; +} + +def : Pat<(i32 (int_xtensa_rur_ua_state_3)), (RUR_UA_STATE_3)>; + +def WUR_ACCX_0: EE_Inst24<(outs), (ins AR:$art), + "wur.accx_0\t $art", [(int_xtensa_wur_accx_0 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf300; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_ACCX_1: EE_Inst24<(outs), (ins AR:$art), + "wur.accx_1\t $art", [(int_xtensa_wur_accx_1 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf301; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_FFT_BIT_WIDTH: EE_Inst24<(outs), (ins AR:$art), + "wur.fft_bit_width\t $art", [(int_xtensa_wur_fft_bit_width AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf30e; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_GPIO_OUT: EE_Inst24<(outs), (ins AR:$art), + "wur.gpio_out\t $art", [(int_xtensa_wur_gpio_out AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf30c; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_H_0: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_h_0\t $art", [(int_xtensa_wur_qacc_h_0 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf302; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_H_1: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_h_1\t $art", [(int_xtensa_wur_qacc_h_1 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf303; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_H_2: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_h_2\t $art", [(int_xtensa_wur_qacc_h_2 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf304; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_H_3: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_h_3\t $art", [(int_xtensa_wur_qacc_h_3 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf305; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_H_4: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_h_4\t $art", [(int_xtensa_wur_qacc_h_4 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf306; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_L_0: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_l_0\t $art", [(int_xtensa_wur_qacc_l_0 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf307; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_L_1: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_l_1\t $art", [(int_xtensa_wur_qacc_l_1 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf308; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_L_2: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_l_2\t $art", [(int_xtensa_wur_qacc_l_2 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf309; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_L_3: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_l_3\t $art", [(int_xtensa_wur_qacc_l_3 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf30a; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_QACC_L_4: EE_Inst24<(outs), (ins AR:$art), + "wur.qacc_l_4\t $art", [(int_xtensa_wur_qacc_l_4 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf30b; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_SAR_BYTE: EE_Inst24<(outs), (ins AR:$art), + "wur.sar_byte\t $art", [(int_xtensa_wur_sar_byte AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf30d; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_UA_STATE_0: EE_Inst24<(outs), (ins AR:$art), + "wur.ua_state_0\t $art", [(int_xtensa_wur_ua_state_0 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf30f; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_UA_STATE_1: EE_Inst24<(outs), (ins AR:$art), + "wur.ua_state_1\t $art", [(int_xtensa_wur_ua_state_1 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf310; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_UA_STATE_2: EE_Inst24<(outs), (ins AR:$art), + "wur.ua_state_2\t $art", [(int_xtensa_wur_ua_state_2 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf311; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def WUR_UA_STATE_3: EE_Inst24<(outs), (ins AR:$art), + "wur.ua_state_3\t $art", [(int_xtensa_wur_ua_state_3 AR:$art)]>, Requires<[HasESP32S3Ops]> +{ + bits<4> art; + + + let Inst{23-8} = 0xf312; + let Inst{7-4} = art{3-0}; + let Inst{3-0} = 0x0; +} + +def mv_QR: EE_Inst24<(outs QR:$a), (ins QR:$b), + "mv.qr\t $a, $b", []>, Requires<[HasESP32S3Ops]> +{ + bits<3> a; + bits<3> b; + + + let Inst{23-22} = 0x2; + let Inst{21-20} = a{2-1}; + let Inst{19-16} = 0xf; + let Inst{15} = a{0}; + let Inst{14-12} = 0x0; + let Inst{11-10} = b{2-1}; + let Inst{9-6} = 0x0; + let Inst{5} = b{0}; + let Inst{4-0} = 0x4; +} + +let usesCustomInserter = 1 in +def mv_QR_P : Pseudo<(outs), (ins imm8:$a, imm8:$b), + "!xtensa_mv_qr_p, $a, $b", + [(int_xtensa_mv_qr timm:$a, timm:$b)]>; \ No newline at end of file diff --git a/llvm/lib/Target/Xtensa/XtensaS3ISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaS3ISelLowering.cpp new file mode 100644 index 00000000000000..301d225c6442e5 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaS3ISelLowering.cpp @@ -0,0 +1,5262 @@ +//===- XtensaS3ISelLowering.cpp - Xtensa S3 DAG Lowering Implementation ---===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the interfaces that Xtensa uses to lower LLVM code into a +// selection DAG. +// +//===----------------------------------------------------------------------===// + +#include "XtensaISelLowering.h" +#include "XtensaSubtarget.h" + +using namespace llvm; + +MachineBasicBlock *XtensaTargetLowering::EmitDSPInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *MBB, const TargetInstrInfo &TII, + MachineFunction *MF, MachineRegisterInfo &MRI, DebugLoc DL) const { + switch (MI.getOpcode()) { + default: + llvm_unreachable("Unexpected instr type to insert"); + case Xtensa::EE_ANDQ_P: { + unsigned Opc = Xtensa::EE_ANDQ; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_andq first argument, it must " + "be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_andq first argument, it must " + "be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_andq first argument, it must " + "be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_BITREV_P: { + unsigned Opc = Xtensa::EE_BITREV; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_bitrev first argument, it must " + "be in range [0,7]"); + MachineOperand &AX = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(R1, RegState::Undef) + .addReg(AX.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_CMUL_S16_P: { + unsigned Opc = Xtensa::EE_CMUL_S16; + MachineOperand &QZ = MI.getOperand(0); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_cmul_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_cmul_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_cmul_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &SEL4 = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_CMUL_S16_LD_INCP_P: { + unsigned Opc = Xtensa::EE_CMUL_S16_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_cmul_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_cmul_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_cmul_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_cmul_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL4 = MI.getOperand(5); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_CMUL_S16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_CMUL_S16_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_cmul_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_cmul_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_cmul_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_cmul_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL4 = MI.getOperand(5); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_AMS_S16_LD_INCP_P: { + unsigned Opc = Xtensa::EE_FFT_AMS_S16_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QZ1 = MI.getOperand(3); + unsigned QZ1Val = QZ1.getImm(); + assert(QZ1Val < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(4); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(5); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QM = MI.getOperand(6); + unsigned QMVal = QM.getImm(); + assert(QMVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL2 = MI.getOperand(7); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QZ1Val) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QMVal) + .addImm(SEL2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_AMS_S16_LD_INCP_UAUP_P: { + unsigned Opc = Xtensa::EE_FFT_AMS_S16_LD_INCP_UAUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp_uaup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp_uaup first " + "argument, it must be in range [0,7]"); + MachineOperand &QZ1 = MI.getOperand(3); + unsigned QZ1Val = QZ1.getImm(); + assert(QZ1Val < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp_uaup " + "first argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(4); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp_uaup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(5); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp_uaup first " + "argument, it must be in range [0,7]"); + MachineOperand &QM = MI.getOperand(6); + unsigned QMVal = QM.getImm(); + assert(QMVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_incp_uaup first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL2 = MI.getOperand(7); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QZ1Val) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QMVal) + .addImm(SEL2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_AMS_S16_LD_R32_DECP_P: { + unsigned Opc = Xtensa::EE_FFT_AMS_S16_LD_R32_DECP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_r32_decp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_r32_decp first " + "argument, it must be in range [0,7]"); + MachineOperand &QZ1 = MI.getOperand(3); + unsigned QZ1Val = QZ1.getImm(); + assert(QZ1Val < 8 && "Unexpected value of ee_fft_ams_s16_ld_r32_decp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(4); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_r32_decp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(5); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_r32_decp first " + "argument, it must be in range [0,7]"); + MachineOperand &QM = MI.getOperand(6); + unsigned QMVal = QM.getImm(); + assert(QMVal < 8 && "Unexpected value of ee_fft_ams_s16_ld_r32_decp first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL2 = MI.getOperand(7); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QZ1Val) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QMVal) + .addImm(SEL2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_AMS_S16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_FFT_AMS_S16_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_fft_ams_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QZ1 = MI.getOperand(1); + unsigned QZ1Val = QZ1.getImm(); + assert(QZ1Val < 8 && "Unexpected value of ee_fft_ams_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS0 = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AS = MI.getOperand(3); + unsigned R2 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(4); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_fft_ams_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(5); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_fft_ams_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QM = MI.getOperand(6); + unsigned QMVal = QM.getImm(); + assert(QMVal < 8 && "Unexpected value of ee_fft_ams_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL2 = MI.getOperand(7); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QZ1Val) + .addReg(R1, RegState::Undef) + .addReg(R2, RegState::Undef) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS0.getReg()) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QMVal) + .addImm(SEL2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_CMUL_S16_LD_XP_P: { + unsigned Opc = Xtensa::EE_FFT_CMUL_S16_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_fft_cmul_s16_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_fft_cmul_s16_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(4); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_fft_cmul_s16_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(5); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_fft_cmul_s16_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL8 = MI.getOperand(6); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_CMUL_S16_ST_XP_P: { + unsigned Opc = Xtensa::EE_FFT_CMUL_S16_ST_XP; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_fft_cmul_s16_st_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_fft_cmul_s16_st_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_fft_cmul_s16_st_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(3); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(4); + MachineOperand &SEL8 = MI.getOperand(5); + MachineOperand &UPD4 = MI.getOperand(6); + MachineOperand &SAR4 = MI.getOperand(7); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addImm(SEL8.getImm()) + .addImm(UPD4.getImm()) + .addImm(SAR4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_R2BF_S16_P: { + unsigned Opc = Xtensa::EE_FFT_R2BF_S16; + MachineOperand &QA0 = MI.getOperand(0); + unsigned QA0Val = QA0.getImm(); + assert(QA0Val < 8 && "Unexpected value of ee_fft_r2bf_s16 first argument, " + "it must be in range [0,7]"); + MachineOperand &QA1 = MI.getOperand(1); + unsigned QA1Val = QA1.getImm(); + assert(QA1Val < 8 && "Unexpected value of ee_fft_r2bf_s16 first argument, " + "it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_fft_r2bf_s16 first argument, " + "it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_fft_r2bf_s16 first argument, " + "it must be in range [0,7]"); + MachineOperand &SEL2 = MI.getOperand(4); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QA0Val) + .addReg(Xtensa::Q0 + QA1Val) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_R2BF_S16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_FFT_R2BF_S16_ST_INCP; + MachineOperand &QA0 = MI.getOperand(0); + unsigned QA0Val = QA0.getImm(); + assert(QA0Val < 8 && "Unexpected value of ee_fft_r2bf_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_fft_r2bf_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_fft_r2bf_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(3); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &SAR4 = MI.getOperand(4); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QA0Val) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(AS.getReg()) + .addImm(SAR4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_FFT_VST_R32_DECP_P: { + unsigned Opc = Xtensa::EE_FFT_VST_R32_DECP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_fft_vst_r32_decp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &SAR2 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addImm(SAR2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDF_128_IP_P: { + unsigned Opc = Xtensa::EE_LDF_128_IP; + MachineOperand &FU3 = MI.getOperand(0); + MachineOperand &FU2 = MI.getOperand(1); + MachineOperand &FU1 = MI.getOperand(2); + MachineOperand &FU0 = MI.getOperand(3); + MachineOperand &AS = MI.getOperand(4); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16F = MI.getOperand(5); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(FU3.getReg()) + .addReg(FU2.getReg()) + .addReg(FU1.getReg()) + .addReg(FU0.getReg()) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16F.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDF_128_XP_P: { + unsigned Opc = Xtensa::EE_LDF_128_XP; + MachineOperand &FU3 = MI.getOperand(0); + MachineOperand &FU2 = MI.getOperand(1); + MachineOperand &FU1 = MI.getOperand(2); + MachineOperand &FU0 = MI.getOperand(3); + MachineOperand &AS = MI.getOperand(4); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(5); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(FU3.getReg()) + .addReg(FU2.getReg()) + .addReg(FU1.getReg()) + .addReg(FU0.getReg()) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDF_64_IP_P: { + unsigned Opc = Xtensa::EE_LDF_64_IP; + MachineOperand &FU1 = MI.getOperand(0); + MachineOperand &FU0 = MI.getOperand(1); + MachineOperand &AS = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM8 = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(FU1.getReg()) + .addReg(FU0.getReg()) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDF_64_XP_P: { + unsigned Opc = Xtensa::EE_LDF_64_XP; + MachineOperand &FU1 = MI.getOperand(0); + MachineOperand &FU0 = MI.getOperand(1); + MachineOperand &AS = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(FU1.getReg()) + .addReg(FU0.getReg()) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDQA_S16_128_IP_P: { + unsigned Opc = Xtensa::EE_LDQA_S16_128_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDQA_S16_128_XP_P: { + unsigned Opc = Xtensa::EE_LDQA_S16_128_XP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDQA_S8_128_IP_P: { + unsigned Opc = Xtensa::EE_LDQA_S8_128_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDQA_S8_128_XP_P: { + unsigned Opc = Xtensa::EE_LDQA_S8_128_XP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDQA_U16_128_IP_P: { + unsigned Opc = Xtensa::EE_LDQA_U16_128_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDQA_U16_128_XP_P: { + unsigned Opc = Xtensa::EE_LDQA_U16_128_XP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDQA_U8_128_IP_P: { + unsigned Opc = Xtensa::EE_LDQA_U8_128_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDQA_U8_128_XP_P: { + unsigned Opc = Xtensa::EE_LDQA_U8_128_XP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LDXQ_32_P: { + unsigned Opc = Xtensa::EE_LDXQ_32; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_ldxq_32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QS = MI.getOperand(1); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_ldxq_32 first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(2); + MachineOperand &SEL4 = MI.getOperand(3); + MachineOperand &SEL8 = MI.getOperand(4); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(Xtensa::Q0 + QSVal) + .addReg(AS.getReg()) + .addImm(SEL4.getImm()) + .addImm(SEL8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LD_128_USAR_IP_P: { + unsigned Opc = Xtensa::EE_LD_128_USAR_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_ld_128_usar_ip first argument, " + "it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LD_128_USAR_XP_P: { + unsigned Opc = Xtensa::EE_LD_128_USAR_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_ld_128_usar_xp first argument, " + "it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LD_ACCX_IP_P: { + unsigned Opc = Xtensa::EE_LD_ACCX_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM8 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LD_QACC_H_H_32_IP_P: { + unsigned Opc = Xtensa::EE_LD_QACC_H_H_32_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM4 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LD_QACC_H_L_128_IP_P: { + unsigned Opc = Xtensa::EE_LD_QACC_H_L_128_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LD_QACC_L_H_32_IP_P: { + unsigned Opc = Xtensa::EE_LD_QACC_L_H_32_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM4 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LD_QACC_L_L_128_IP_P: { + unsigned Opc = Xtensa::EE_LD_QACC_L_L_128_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_LD_UA_STATE_IP_P: { + unsigned Opc = Xtensa::EE_LD_UA_STATE_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_MOVI_32_A_P: { + unsigned Opc = Xtensa::EE_MOVI_32_A; + MachineOperand &QS = MI.getOperand(0); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_movi_32_a first argument, it " + "must be in range [0,7]"); + MachineOperand &AU = MI.getOperand(1); + MachineOperand &SEL4 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(AU.getReg()) + .addReg(Xtensa::Q0 + QSVal) + .addImm(SEL4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_MOVI_32_Q_P: { + unsigned Opc = Xtensa::EE_MOVI_32_Q; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_movi_32_q first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + MachineOperand &SEL4 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(AS.getReg()) + .addImm(SEL4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_MOV_S16_QACC_P: { + unsigned Opc = Xtensa::EE_MOV_S16_QACC; + MachineOperand &QS = MI.getOperand(0); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_mov_s16_qacc first argument, " + "it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(Xtensa::Q0 + QSVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_MOV_S8_QACC_P: { + unsigned Opc = Xtensa::EE_MOV_S8_QACC; + MachineOperand &QS = MI.getOperand(0); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_mov_s8_qacc first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(Xtensa::Q0 + QSVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_MOV_U16_QACC_P: { + unsigned Opc = Xtensa::EE_MOV_U16_QACC; + MachineOperand &QS = MI.getOperand(0); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_mov_u16_qacc first argument, " + "it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(Xtensa::Q0 + QSVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_MOV_U8_QACC_P: { + unsigned Opc = Xtensa::EE_MOV_U8_QACC; + MachineOperand &QS = MI.getOperand(0); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_mov_u8_qacc first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(Xtensa::Q0 + QSVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_NOTQ_P: { + unsigned Opc = Xtensa::EE_NOTQ; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_notq first argument, it must " + "be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_notq first argument, it must " + "be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ORQ_P: { + unsigned Opc = Xtensa::EE_ORQ; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert( + QAVal < 8 && + "Unexpected value of ee_orq first argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert( + QXVal < 8 && + "Unexpected value of ee_orq first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert( + QYVal < 8 && + "Unexpected value of ee_orq first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SLCI_2Q_P: { + unsigned Opc = Xtensa::EE_SLCI_2Q; + MachineOperand &QS1 = MI.getOperand(0); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_slci_2q first argument, it " + "must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(1); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_slci_2q first argument, it " + "must be in range [0,7]"); + MachineOperand &SAR16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addImm(SAR16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SLCXXP_2Q_P: { + unsigned Opc = Xtensa::EE_SLCXXP_2Q; + MachineOperand &QS1 = MI.getOperand(0); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_slcxxp_2q first argument, it " + "must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(1); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_slcxxp_2q first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRCI_2Q_P: { + unsigned Opc = Xtensa::EE_SRCI_2Q; + MachineOperand &QS1 = MI.getOperand(0); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_srci_2q first argument, it " + "must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(1); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_srci_2q first argument, it " + "must be in range [0,7]"); + MachineOperand &SAR16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addImm(SAR16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRCMB_S16_QACC_P: { + unsigned Opc = Xtensa::EE_SRCMB_S16_QACC; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_srcmb_s16_qacc first argument, " + "it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + MachineOperand &SEL2 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(AS.getReg()) + .addImm(SEL2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRCMB_S8_QACC_P: { + unsigned Opc = Xtensa::EE_SRCMB_S8_QACC; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_srcmb_s8_qacc first argument, " + "it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + MachineOperand &SEL2 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(AS.getReg()) + .addImm(SEL2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRCQ_128_ST_INCP_P: { + unsigned Opc = Xtensa::EE_SRCQ_128_ST_INCP; + MachineOperand &QS0 = MI.getOperand(0); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_srcq_128_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(1); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_srcq_128_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(AS.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRCXXP_2Q_P: { + unsigned Opc = Xtensa::EE_SRCXXP_2Q; + MachineOperand &QS1 = MI.getOperand(0); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_srcxxp_2q first argument, it " + "must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(1); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_srcxxp_2q first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRC_Q_P: { + unsigned Opc = Xtensa::EE_SRC_Q; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_src_q first argument, it must " + "be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(1); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_src_q first argument, it must " + "be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(2); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_src_q first argument, it must " + "be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRC_Q_LD_IP_P: { + unsigned Opc = Xtensa::EE_SRC_Q_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_src_q_ld_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QS0 = MI.getOperand(3); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_src_q_ld_ip first argument, " + "it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(4); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_src_q_ld_ip first argument, " + "it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRC_Q_LD_XP_P: { + unsigned Opc = Xtensa::EE_SRC_Q_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_src_q_ld_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QS0 = MI.getOperand(3); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_src_q_ld_xp first argument, " + "it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(4); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_src_q_ld_xp first argument, " + "it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRC_Q_QUP_P: { + unsigned Opc = Xtensa::EE_SRC_Q_QUP; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_src_q_qup first argument, it " + "must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(1); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_src_q_qup first argument, it " + "must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(2); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_src_q_qup first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_SRS_ACCX_P: { + unsigned Opc = Xtensa::EE_SRS_ACCX; + MachineOperand &AU = MI.getOperand(0); + MachineOperand &AS = MI.getOperand(1); + MachineOperand &SEL2 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(AU.getReg()) + .addReg(AS.getReg()) + .addImm(SEL2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_STF_128_IP_P: { + unsigned Opc = Xtensa::EE_STF_128_IP; + MachineOperand &FV3 = MI.getOperand(0); + MachineOperand &FV2 = MI.getOperand(1); + MachineOperand &FV1 = MI.getOperand(2); + MachineOperand &FV0 = MI.getOperand(3); + MachineOperand &AS = MI.getOperand(4); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16F = MI.getOperand(5); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(FV3.getReg()) + .addReg(FV2.getReg()) + .addReg(FV1.getReg()) + .addReg(FV0.getReg()) + .addReg(AS.getReg()) + .addImm(IMM16F.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_STF_128_XP_P: { + unsigned Opc = Xtensa::EE_STF_128_XP; + MachineOperand &FV3 = MI.getOperand(0); + MachineOperand &FV2 = MI.getOperand(1); + MachineOperand &FV1 = MI.getOperand(2); + MachineOperand &FV0 = MI.getOperand(3); + MachineOperand &AS = MI.getOperand(4); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(5); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(FV3.getReg()) + .addReg(FV2.getReg()) + .addReg(FV1.getReg()) + .addReg(FV0.getReg()) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_STF_64_IP_P: { + unsigned Opc = Xtensa::EE_STF_64_IP; + MachineOperand &FV1 = MI.getOperand(0); + MachineOperand &FV0 = MI.getOperand(1); + MachineOperand &AS = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM8 = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(FV1.getReg()) + .addReg(FV0.getReg()) + .addReg(AS.getReg()) + .addImm(IMM8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_STF_64_XP_P: { + unsigned Opc = Xtensa::EE_STF_64_XP; + MachineOperand &FV1 = MI.getOperand(0); + MachineOperand &FV0 = MI.getOperand(1); + MachineOperand &AS = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(FV1.getReg()) + .addReg(FV0.getReg()) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_STXQ_32_P: { + unsigned Opc = Xtensa::EE_STXQ_32; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_stxq_32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QS = MI.getOperand(1); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_stxq_32 first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(2); + MachineOperand &SEL4 = MI.getOperand(3); + MachineOperand &SEL8 = MI.getOperand(4); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QVVal) + .addReg(Xtensa::Q0 + QSVal) + .addReg(AS.getReg()) + .addImm(SEL4.getImm()) + .addImm(SEL8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ST_ACCX_IP_P: { + unsigned Opc = Xtensa::EE_ST_ACCX_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM8 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ST_QACC_H_H_32_IP_P: { + unsigned Opc = Xtensa::EE_ST_QACC_H_H_32_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM4 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ST_QACC_H_L_128_IP_P: { + unsigned Opc = Xtensa::EE_ST_QACC_H_L_128_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ST_QACC_L_H_32_IP_P: { + unsigned Opc = Xtensa::EE_ST_QACC_L_H_32_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM4 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ST_QACC_L_L_128_IP_P: { + unsigned Opc = Xtensa::EE_ST_QACC_L_L_128_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ST_UA_STATE_IP_P: { + unsigned Opc = Xtensa::EE_ST_UA_STATE_IP; + MachineOperand &AS = MI.getOperand(0); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S16_P: { + unsigned Opc = Xtensa::EE_VADDS_S16; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S16_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VADDS_S16_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vadds_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s16_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VADDS_S16_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vadds_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s16_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S32_P: { + unsigned Opc = Xtensa::EE_VADDS_S32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S32_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VADDS_S32_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vadds_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s32_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S32_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VADDS_S32_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vadds_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s32_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S8_P: { + unsigned Opc = Xtensa::EE_VADDS_S8; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S8_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VADDS_S8_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vadds_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s8_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VADDS_S8_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VADDS_S8_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vadds_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vadds_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vadds_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vadds_s8_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_EQ_S16_P: { + unsigned Opc = Xtensa::EE_VCMP_EQ_S16; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_eq_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_eq_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_eq_s16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_EQ_S32_P: { + unsigned Opc = Xtensa::EE_VCMP_EQ_S32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_eq_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_eq_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_eq_s32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_EQ_S8_P: { + unsigned Opc = Xtensa::EE_VCMP_EQ_S8; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_eq_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_eq_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_eq_s8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_GT_S16_P: { + unsigned Opc = Xtensa::EE_VCMP_GT_S16; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_gt_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_gt_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_gt_s16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_GT_S32_P: { + unsigned Opc = Xtensa::EE_VCMP_GT_S32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_gt_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_gt_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_gt_s32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_GT_S8_P: { + unsigned Opc = Xtensa::EE_VCMP_GT_S8; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_gt_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_gt_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_gt_s8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_LT_S16_P: { + unsigned Opc = Xtensa::EE_VCMP_LT_S16; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_lt_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_lt_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_lt_s16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_LT_S32_P: { + unsigned Opc = Xtensa::EE_VCMP_LT_S32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_lt_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_lt_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_lt_s32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VCMP_LT_S8_P: { + unsigned Opc = Xtensa::EE_VCMP_LT_S8; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vcmp_lt_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vcmp_lt_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vcmp_lt_s8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_16_P: { + unsigned Opc = Xtensa::EE_VLDBC_16; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_16 first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(AS.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_16_IP_P: { + unsigned Opc = Xtensa::EE_VLDBC_16_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_16_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM2 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_16_XP_P: { + unsigned Opc = Xtensa::EE_VLDBC_16_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_16_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_32_P: { + unsigned Opc = Xtensa::EE_VLDBC_32; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_32 first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(AS.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_32_IP_P: { + unsigned Opc = Xtensa::EE_VLDBC_32_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_32_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM4 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_32_XP_P: { + unsigned Opc = Xtensa::EE_VLDBC_32_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_32_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_8_P: { + unsigned Opc = Xtensa::EE_VLDBC_8; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_8 first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(AS.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_8_IP_P: { + unsigned Opc = Xtensa::EE_VLDBC_8_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_8_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM1 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM1.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDBC_8_XP_P: { + unsigned Opc = Xtensa::EE_VLDBC_8_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldbc_8_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLDHBC_16_INCP_P: { + unsigned Opc = Xtensa::EE_VLDHBC_16_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vldhbc_16_incp first argument, " + "it must be in range [0,7]"); + MachineOperand &QU1 = MI.getOperand(1); + unsigned QU1Val = QU1.getImm(); + assert(QU1Val < 8 && "Unexpected value of ee_vldhbc_16_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(2); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(Xtensa::Q0 + QU1Val) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLD_128_IP_P: { + unsigned Opc = Xtensa::EE_VLD_128_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vld_128_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLD_128_XP_P: { + unsigned Opc = Xtensa::EE_VLD_128_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vld_128_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLD_H_64_IP_P: { + unsigned Opc = Xtensa::EE_VLD_H_64_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vld_h_64_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM8 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLD_H_64_XP_P: { + unsigned Opc = Xtensa::EE_VLD_H_64_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vld_h_64_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLD_L_64_IP_P: { + unsigned Opc = Xtensa::EE_VLD_L_64_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vld_l_64_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM8 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VLD_L_64_XP_P: { + unsigned Opc = Xtensa::EE_VLD_L_64_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vld_l_64_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S16_P: { + unsigned Opc = Xtensa::EE_VMAX_S16; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S16_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMAX_S16_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmax_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s16_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMAX_S16_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmax_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s16_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S32_P: { + unsigned Opc = Xtensa::EE_VMAX_S32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S32_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMAX_S32_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmax_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s32_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S32_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMAX_S32_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmax_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s32_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S8_P: { + unsigned Opc = Xtensa::EE_VMAX_S8; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S8_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMAX_S8_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmax_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s8_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMAX_S8_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMAX_S8_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmax_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmax_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmax_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmax_s8_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S16_P: { + unsigned Opc = Xtensa::EE_VMIN_S16; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S16_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMIN_S16_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmin_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s16_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMIN_S16_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmin_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s16_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S32_P: { + unsigned Opc = Xtensa::EE_VMIN_S32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S32_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMIN_S32_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmin_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s32_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S32_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMIN_S32_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmin_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s32_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S8_P: { + unsigned Opc = Xtensa::EE_VMIN_S8; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S8_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMIN_S8_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmin_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s8_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMIN_S8_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMIN_S8_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmin_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vmin_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmin_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmin_s8_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_ACCX_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_ACCX; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_accx first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_accx first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_ACCX_LD_IP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_ACCX_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_ip first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_ACCX_LD_IP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_ACCX_LD_IP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_ACCX_LD_XP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_ACCX_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_xp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_ACCX_LD_XP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_ACCX_LD_XP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_QACC_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_QACC; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_qacc first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_qacc first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_QACC_LDBC_INCP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_QACC_LDBC_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ldbc_incp " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ldbc_incp " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ldbc_incp " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_QACC_LDBC_INCP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(4); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(5); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_QACC_LD_IP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_QACC_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_QACC_LD_IP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_QACC_LD_IP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_QACC_LD_XP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_QACC_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S16_QACC_LD_XP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S16_QACC_LD_XP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_ACCX_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_ACCX; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_accx first argument, " + "it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_accx first argument, " + "it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_ACCX_LD_IP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_ACCX_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_ip first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_ACCX_LD_IP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_ACCX_LD_IP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_ACCX_LD_XP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_ACCX_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_xp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_ACCX_LD_XP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_ACCX_LD_XP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s8_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_QACC_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_QACC; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_qacc first argument, " + "it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_qacc first argument, " + "it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_QACC_LDBC_INCP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_QACC_LDBC_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ldbc_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ldbc_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ldbc_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_QACC_LDBC_INCP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(4); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(5); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_QACC_LD_IP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_QACC_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_QACC_LD_IP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_QACC_LD_IP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_QACC_LD_XP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_QACC_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_S8_QACC_LD_XP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_S8_QACC_LD_XP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_s8_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_ACCX_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_ACCX; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_accx first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_accx first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_ACCX_LD_IP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_ACCX_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_ip first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_ACCX_LD_IP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_ACCX_LD_IP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_ACCX_LD_XP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_ACCX_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_xp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_ACCX_LD_XP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_ACCX_LD_XP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u16_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_QACC_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_QACC; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_qacc first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_qacc first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_QACC_LDBC_INCP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_QACC_LDBC_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ldbc_incp " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ldbc_incp " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ldbc_incp " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_QACC_LDBC_INCP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(4); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(5); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u16_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_QACC_LD_IP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_QACC_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_QACC_LD_IP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_QACC_LD_IP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_QACC_LD_XP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_QACC_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U16_QACC_LD_XP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U16_QACC_LD_XP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u16_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_ACCX_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_ACCX; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_accx first argument, " + "it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_accx first argument, " + "it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_ACCX_LD_IP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_ACCX_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_ip first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_ACCX_LD_IP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_ACCX_LD_IP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_ip_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_ACCX_LD_XP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_ACCX_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_xp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_ACCX_LD_XP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_ACCX_LD_XP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u8_accx_ld_xp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_QACC_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_QACC; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_qacc first argument, " + "it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_qacc first argument, " + "it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_QACC_LDBC_INCP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_QACC_LDBC_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ldbc_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ldbc_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ldbc_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_QACC_LDBC_INCP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(4); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(5); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u8_qacc_ldbc_incp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_QACC_LD_IP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_QACC_LD_IP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_ip first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_QACC_LD_IP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_QACC_LD_IP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_ip_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_ip_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_QACC_LD_XP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_QACC_LD_XP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_xp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMULAS_U8_QACC_LD_XP_QUP_P: { + unsigned Opc = Xtensa::EE_VMULAS_U8_QACC_LD_XP_QUP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_xp_qup first " + "argument, it must be in range [0,7]"); + MachineOperand &QS0 = MI.getOperand(5); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(6); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vmulas_u8_qacc_ld_xp_qup " + "first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(AS.getReg()) + .addReg(AD.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_S16_P: { + unsigned Opc = Xtensa::EE_VMUL_S16; + MachineOperand &QZ = MI.getOperand(0); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_s16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_S16_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMUL_S16_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmul_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_s16_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_S16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMUL_S16_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmul_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_s16_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_S8_P: { + unsigned Opc = Xtensa::EE_VMUL_S8; + MachineOperand &QZ = MI.getOperand(0); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_s8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_S8_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMUL_S8_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmul_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_s8_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_S8_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMUL_S8_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmul_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_s8_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_U16_P: { + unsigned Opc = Xtensa::EE_VMUL_U16; + MachineOperand &QZ = MI.getOperand(0); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_u16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_u16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_u16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_U16_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMUL_U16_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmul_u16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_u16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_u16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_u16_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_U16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMUL_U16_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmul_u16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_u16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_u16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_u16_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_U8_P: { + unsigned Opc = Xtensa::EE_VMUL_U8; + MachineOperand &QZ = MI.getOperand(0); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_u8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_u8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_u8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_U8_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VMUL_U8_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vmul_u8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_u8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_u8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_u8_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VMUL_U8_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VMUL_U8_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vmul_u8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vmul_u8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vmul_u8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vmul_u8_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VPRELU_S16_P: { + unsigned Opc = Xtensa::EE_VPRELU_S16; + MachineOperand &QZ = MI.getOperand(0); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vprelu_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vprelu_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vprelu_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &AY = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(AY.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VPRELU_S8_P: { + unsigned Opc = Xtensa::EE_VPRELU_S8; + MachineOperand &QZ = MI.getOperand(0); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of ee_vprelu_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vprelu_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vprelu_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &AY = MI.getOperand(3); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addReg(AY.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VRELU_S16_P: { + unsigned Opc = Xtensa::EE_VRELU_S16; + MachineOperand &QS = MI.getOperand(0); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_vrelu_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &AX = MI.getOperand(1); + MachineOperand &AY = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QSVal) + .addReg(Xtensa::Q0 + QSVal) + .addReg(AX.getReg()) + .addReg(AY.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VRELU_S8_P: { + unsigned Opc = Xtensa::EE_VRELU_S8; + MachineOperand &QS = MI.getOperand(0); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_vrelu_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &AX = MI.getOperand(1); + MachineOperand &AY = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QSVal) + .addReg(Xtensa::Q0 + QSVal) + .addReg(AX.getReg()) + .addReg(AY.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSL_32_P: { + unsigned Opc = Xtensa::EE_VSL_32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsl_32 first argument, it must " + "be in range [0,7]"); + MachineOperand &QS = MI.getOperand(1); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_vsl_32 first argument, it must " + "be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QSVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSMULAS_S16_QACC_P: { + unsigned Opc = Xtensa::EE_VSMULAS_S16_QACC; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsmulas_s16_qacc first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsmulas_s16_qacc first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL8 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSMULAS_S16_QACC_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VSMULAS_S16_QACC_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vsmulas_s16_qacc_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsmulas_s16_qacc_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsmulas_s16_qacc_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL8 = MI.getOperand(4); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSMULAS_S8_QACC_P: { + unsigned Opc = Xtensa::EE_VSMULAS_S8_QACC; + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsmulas_s8_qacc first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsmulas_s8_qacc first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSMULAS_S8_QACC_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VSMULAS_S8_QACC_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vsmulas_s8_qacc_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsmulas_s8_qacc_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(3); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsmulas_s8_qacc_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &SEL16 = MI.getOperand(4); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal) + .addImm(SEL16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSR_32_P: { + unsigned Opc = Xtensa::EE_VSR_32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsr_32 first argument, it must " + "be in range [0,7]"); + MachineOperand &QS = MI.getOperand(1); + unsigned QSVal = QS.getImm(); + assert(QSVal < 8 && "Unexpected value of ee_vsr_32 first argument, it must " + "be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QSVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VST_128_IP_P: { + unsigned Opc = Xtensa::EE_VST_128_IP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vst_128_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addImm(IMM16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VST_128_XP_P: { + unsigned Opc = Xtensa::EE_VST_128_XP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vst_128_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VST_H_64_IP_P: { + unsigned Opc = Xtensa::EE_VST_H_64_IP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vst_h_64_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM8 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addImm(IMM8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VST_H_64_XP_P: { + unsigned Opc = Xtensa::EE_VST_H_64_XP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vst_h_64_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VST_L_64_IP_P: { + unsigned Opc = Xtensa::EE_VST_L_64_IP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vst_l_64_ip first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &IMM8 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addImm(IMM8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VST_L_64_XP_P: { + unsigned Opc = Xtensa::EE_VST_L_64_XP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vst_l_64_xp first argument, it " + "must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &AD = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(AD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S16_P: { + unsigned Opc = Xtensa::EE_VSUBS_S16; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S16_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VSUBS_S16_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vsubs_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s16_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s16_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S16_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VSUBS_S16_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vsubs_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s16_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s16_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S32_P: { + unsigned Opc = Xtensa::EE_VSUBS_S32; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S32_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VSUBS_S32_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vsubs_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s32_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s32_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S32_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VSUBS_S32_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vsubs_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s32_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s32_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S8_P: { + unsigned Opc = Xtensa::EE_VSUBS_S8; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S8_LD_INCP_P: { + unsigned Opc = Xtensa::EE_VSUBS_S8_LD_INCP; + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of ee_vsubs_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s8_ld_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s8_ld_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QUVal) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VSUBS_S8_ST_INCP_P: { + unsigned Opc = Xtensa::EE_VSUBS_S8_ST_INCP; + MachineOperand &QV = MI.getOperand(0); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of ee_vsubs_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &AS = MI.getOperand(1); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + unsigned R1 = MRI.createVirtualRegister(RC); + MachineOperand &QA = MI.getOperand(2); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_vsubs_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QX = MI.getOperand(3); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_vsubs_s8_st_incp first " + "argument, it must be in range [0,7]"); + MachineOperand &QY = MI.getOperand(4); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_vsubs_s8_st_incp first " + "argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QVVal) + .addReg(AS.getReg()) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VUNZIP_16_P: { + unsigned Opc = Xtensa::EE_VUNZIP_16; + MachineOperand &QS0 = MI.getOperand(0); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vunzip_16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(1); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vunzip_16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VUNZIP_32_P: { + unsigned Opc = Xtensa::EE_VUNZIP_32; + MachineOperand &QS0 = MI.getOperand(0); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vunzip_32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(1); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vunzip_32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VUNZIP_8_P: { + unsigned Opc = Xtensa::EE_VUNZIP_8; + MachineOperand &QS0 = MI.getOperand(0); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vunzip_8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(1); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vunzip_8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VZIP_16_P: { + unsigned Opc = Xtensa::EE_VZIP_16; + MachineOperand &QS0 = MI.getOperand(0); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vzip_16 first argument, it " + "must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(1); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vzip_16 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VZIP_32_P: { + unsigned Opc = Xtensa::EE_VZIP_32; + MachineOperand &QS0 = MI.getOperand(0); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vzip_32 first argument, it " + "must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(1); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vzip_32 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_VZIP_8_P: { + unsigned Opc = Xtensa::EE_VZIP_8; + MachineOperand &QS0 = MI.getOperand(0); + unsigned QS0Val = QS0.getImm(); + assert(QS0Val < 8 && "Unexpected value of ee_vzip_8 first argument, it " + "must be in range [0,7]"); + MachineOperand &QS1 = MI.getOperand(1); + unsigned QS1Val = QS1.getImm(); + assert(QS1Val < 8 && "Unexpected value of ee_vzip_8 first argument, it " + "must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val) + .addReg(Xtensa::Q0 + QS0Val) + .addReg(Xtensa::Q0 + QS1Val); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_XORQ_P: { + unsigned Opc = Xtensa::EE_XORQ; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_xorq first argument, it must " + "be in range [0,7]"); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of ee_xorq first argument, it must " + "be in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of ee_xorq first argument, it must " + "be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QXVal) + .addReg(Xtensa::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ZERO_ACCX_P: { + unsigned Opc = Xtensa::EE_ZERO_ACCX; + BuildMI(*MBB, MI, DL, TII.get(Opc)); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ZERO_Q_P: { + unsigned Opc = Xtensa::EE_ZERO_Q; + MachineOperand &QA = MI.getOperand(0); + unsigned QAVal = QA.getImm(); + assert(QAVal < 8 && "Unexpected value of ee_zero_q first argument, it must " + "be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(Xtensa::Q0 + QAVal); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::EE_ZERO_QACC_P: { + unsigned Opc = Xtensa::EE_ZERO_QACC; + BuildMI(*MBB, MI, DL, TII.get(Opc)); + + MI.eraseFromParent(); + return MBB; + } + case Xtensa::mv_QR_P: { + unsigned Opc = Xtensa::mv_QR; + MachineOperand &A = MI.getOperand(0); + unsigned AVal = A.getImm(); + assert( + AVal < 8 && + "Unexpected value of mv_qr first argument, it must be in range [0,7]"); + MachineOperand &B = MI.getOperand(1); + unsigned BVal = B.getImm(); + assert( + BVal < 8 && + "Unexpected value of mv_qr first argument, it must be in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(Xtensa::Q0 + AVal) + .addReg(Xtensa::Q0 + BVal); + + MI.eraseFromParent(); + return MBB; + } + } +} diff --git a/llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll b/llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll new file mode 100644 index 00000000000000..9d339f00e539bd --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll @@ -0,0 +1,148 @@ +; RUN: llc -mtriple=xtensa -mcpu=esp32s3 < %s | FileCheck %s + +; Function Attrs: nounwind +define dso_local void @test(i32 noundef %ptr.coerce, i32 noundef %ptr2.coerce) local_unnamed_addr #0 { +entry: + %coerce.val.ip = inttoptr i32 %ptr.coerce to ptr + %0 = load i32, ptr %coerce.val.ip, align 4, !tbaa !2 + tail call void @llvm.xtensa.ee.vld.128.ip(i32 1, i32 16, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 1, i32 16, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 1, i32 16, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 1, i32 %0, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 2, i32 %0, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 3, i32 %0, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 3, i32 %0, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 3, i32 %0, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 3, i32 %0, i32 0) + tail call void @llvm.xtensa.ee.vld.128.ip(i32 3, i32 %0, i32 0) + tail call void @llvm.xtensa.ee.vmax.s8(i32 1, i32 2, i32 3) + tail call void @llvm.xtensa.ee.vmax.s16(i32 4, i32 5, i32 7) + tail call void @llvm.xtensa.ee.stf.128.ip(float 0x40099999A0000000, float 0x4002666660000000, float 0x4011CCCCC0000000, float 0x401AA8F5C0000000, i32 %0, i32 16) + tail call void @llvm.xtensa.ee.stf.128.ip(float undef, float undef, float undef, float undef, i32 %0, i32 16) + tail call void @llvm.xtensa.ee.stf.128.xp(float undef, float undef, float undef, float undef, i32 16, i32 %0) + br label %for.body + +for.cond.cleanup: ; preds = %for.body + tail call void @llvm.xtensa.wur.sar.byte(i32 0) + tail call void @llvm.xtensa.wur.accx.0(i32 0) + tail call void @llvm.xtensa.wur.accx.1(i32 0) + ret void + +for.body: ; preds = %entry, %for.body + %i.029 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + tail call void @llvm.xtensa.ee.ld.128.usar.ip(i32 4, i32 %0, i32 16) + tail call void @llvm.xtensa.ee.src.q.ld.ip(i32 3, i32 %0, i32 16, i32 4, i32 2) + tail call void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip(i32 0, i32 10, i32 16, i32 4, i32 6) + tail call void @llvm.xtensa.ee.vmulas.s16.accx.ld.xp.qup(i32 4, i32 %0, i32 16, i32 0, i32 4, i32 2, i32 3) + tail call void @llvm.xtensa.ee.ld.128.usar.xp(i32 4, i32 %0, i32 16) + tail call void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip.qup(i32 3, i32 %0, i32 16, i32 0, i32 3, i32 4, i32 2) + %inc = add nuw nsw i32 %i.029, 1 + %exitcond.not = icmp eq i32 %inc, 32 + br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !6 +} + +; CHECK-LABEL: test: # @test +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: entry a1, 32 +; CHECK-NEXT: l32i.n a8, a2, 0 +; CHECK-NEXT: movi.n a9, 16 +; CHECK-NEXT: ee.vld.128.ip q1, a9, 0 +; CHECK-NEXT: ee.vld.128.ip q1, a9, 0 +; CHECK-NEXT: ee.vld.128.ip q1, a9, 0 +; CHECK-NEXT: ee.vld.128.ip q1, a8, 0 +; CHECK-NEXT: ee.vld.128.ip q2, a8, 0 +; CHECK-NEXT: ee.vld.128.ip q3, a8, 0 +; CHECK-NEXT: ee.vld.128.ip q3, a8, 0 +; CHECK-NEXT: ee.vld.128.ip q3, a8, 0 +; CHECK-NEXT: ee.vld.128.ip q3, a8, 0 +; CHECK-NEXT: ee.vld.128.ip q3, a8, 0 +; CHECK-NEXT: ee.vmax.s8 q1, q2, q3 +; CHECK-NEXT: ee.vmax.s16 q4, q5, q7 +; CHECK-NEXT: l32r a10, .LCPI0_0 +; CHECK-NEXT: wfr f8, a10 +; CHECK-NEXT: l32r a10, .LCPI0_1 +; CHECK-NEXT: wfr f9, a10 +; CHECK-NEXT: l32r a10, .LCPI0_2 +; CHECK-NEXT: wfr f10, a10 +; CHECK-NEXT: l32r a10, .LCPI0_3 +; CHECK-NEXT: wfr f11, a10 +; CHECK-NEXT: ee.stf.128.ip f11, f10, f9, f8, a8, 16 +; CHECK-NEXT: ee.stf.128.ip f8, f8, f8, f8, a8, 16 +; CHECK-NEXT: ee.stf.128.xp f8, f8, f8, f8, a9, a8 +; CHECK-NEXT: movi.n a10, 0 +; CHECK-NEXT: movi.n a11, 10 +; CHECK-NEXT: .LBB0_1: # %for.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: ee.ld.128.usar.ip q4, a8, 16 +; CHECK-NEXT: ee.src.q.ld.ip q3, a8, 16, q4, q2 +; CHECK-NEXT: ee.vmulas.s16.accx.ld.ip q0, a11, 16, q4, q6 +; CHECK-NEXT: ee.vmulas.s16.accx.ld.xp.qup q4, a8, a9, q0, q4, q2, q3 +; CHECK-NEXT: ee.ld.128.usar.xp q4, a8, a9 +; CHECK-NEXT: ee.vmulas.s16.accx.ld.ip.qup q3, a8, 16, q0, q3, q4, q2 +; CHECK-NEXT: addi.n a10, a10, 1 +; CHECK-NEXT: bnei a10, 32, .LBB0_1 +; CHECK-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-NEXT: movi.n a8, 0 +; CHECK-NEXT: wur.sar_byte a8 +; CHECK-NEXT: wur.accx_0 a8 +; CHECK-NEXT: wur.accx_1 a8 +; CHECK-NEXT: retw.n + + + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.vld.128.ip(i32 immarg, i32, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.vmax.s8(i32 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.vmax.s16(i32 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.stf.128.ip(float, float, float, float, i32, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.stf.128.xp(float, float, float, float, i32, i32) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.ld.128.usar.ip(i32 immarg, i32, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.src.q.ld.ip(i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip(i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.vmulas.s16.accx.ld.xp.qup(i32 immarg, i32, i32, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.ld.128.usar.xp(i32 immarg, i32, i32) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip.qup(i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.wur.sar.byte(i32) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.wur.accx.0(i32) #1 + +; Function Attrs: nounwind +declare void @llvm.xtensa.wur.accx.1(i32) #1 + +attributes #0 = { nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+atomctl,+bool,+coprocessor,+debug,+density,+dfpaccel,+div32,+exception,+fp,+highpriinterrupts,+interrupt,+loop,+mac16,+memctl,+miscsr,+mul32,+mul32high,+nsa,+prid,+regprotect,+rvector,+s32c1i,+sext,+threadptr,+timerint,+windowed" } +attributes #1 = { nounwind } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 1} +!1 = !{!"clang version 15.0.0 (https://github.com/espressif/llvm-project.git a69f9a9e5e52d92f584c8268b1d041b2dfaee1e8)"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} +!6 = distinct !{!6, !7} +!7 = !{!"llvm.loop.mustprogress"} diff --git a/llvm/test/CodeGen/Xtensa/xtensa-s3-dsp.ll b/llvm/test/CodeGen/Xtensa/xtensa-s3-dsp.ll new file mode 100644 index 00000000000000..b1782c92dff0b3 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-s3-dsp.ll @@ -0,0 +1,764 @@ +; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32s3 %s -o - | FileCheck %s + +; CHECK: @test +define void @test(){ + tail call void @llvm.xtensa.ee.andq(i32 7, i32 0, i32 1) + ; CHECK: ee.andq + tail call void @llvm.xtensa.ee.bitrev(i32 0, i32 3) + ; CHECK: ee.bitrev + tail call void @llvm.xtensa.ee.cmul.s16(i32 2, i32 3, i32 2, i32 1) + ; CHECK: ee.cmul.s16 + tail call void @llvm.xtensa.ee.cmul.s16.ld.incp(i32 2, i32 1, i32 7, i32 5, i32 0, i32 3) + ; CHECK: ee.cmul.s16.ld.incp + tail call void @llvm.xtensa.ee.cmul.s16.st.incp(i32 1, i32 6, i32 6, i32 1, i32 1, i32 1) + ; CHECK: ee.cmul.s16.st.incp + tail call void @llvm.xtensa.ee.fft.ams.s16.ld.incp(i32 4, i32 10, i32 4, i32 2, i32 2, i32 2, i32 0, i32 1) + ; CHECK: ee.fft.ams.s16.ld.incp + tail call void @llvm.xtensa.ee.fft.ams.s16.ld.incp.uaup(i32 0, i32 6, i32 1, i32 6, i32 2, i32 2, i32 6, i32 1) + ; CHECK: ee.fft.ams.s16.ld.incp.uaup + tail call void @llvm.xtensa.ee.fft.ams.s16.ld.r32.decp(i32 7, i32 2, i32 5, i32 6, i32 1, i32 4, i32 0, i32 1) + ; CHECK: ee.fft.ams.s16.ld.r32.decp + tail call void @llvm.xtensa.ee.fft.ams.s16.st.incp(i32 1, i32 1, i32 14, i32 2, i32 7, i32 0, i32 1, i32 0) + ; CHECK: ee.fft.ams.s16.st.incp + tail call void @llvm.xtensa.ee.fft.cmul.s16.ld.xp(i32 7, i32 4, i32 9, i32 0, i32 2, i32 7, i32 1) + ; CHECK: ee.fft.cmul.s16.ld.xp + tail call void @llvm.xtensa.ee.fft.cmul.s16.st.xp(i32 3, i32 0, i32 5, i32 11, i32 8, i32 7, i32 1, i32 0) + ; CHECK: ee.fft.cmul.s16.st.xp + tail call void @llvm.xtensa.ee.fft.r2bf.s16(i32 7, i32 7, i32 2, i32 0, i32 1) + ; CHECK: ee.fft.r2bf.s16 + tail call void @llvm.xtensa.ee.fft.r2bf.s16.st.incp(i32 0, i32 5, i32 1, i32 10, i32 0) + ; CHECK: ee.fft.r2bf.s16.st.incp + tail call void @llvm.xtensa.ee.fft.vst.r32.decp(i32 0, i32 10, i32 1) + ; CHECK: ee.fft.vst.r32.decp + tail call void @llvm.xtensa.ee.ldf.128.ip(float 0x40099999A0000000, float 0x40099999A0000000, float 0x40099999A0000000, float 0x40099999A0000000, i32 0, i32 64) + ; CHECK: ee.ldf.128.ip + tail call void @llvm.xtensa.ee.ldf.128.xp(float 0x40099999A0000000, float 0x40099999A0000000, float 0x40099999A0000000, float 0x40099999A0000000, i32 2, i32 13) + ; CHECK: ee.ldf.128.xp + tail call void @llvm.xtensa.ee.ldf.64.ip(float 0x40099999A0000000, float 0x40099999A0000000, i32 10, i32 -232) + ; CHECK: ee.ldf.64.ip + tail call void @llvm.xtensa.ee.ldf.64.xp(float 0x40099999A0000000, float 0x40099999A0000000, i32 13, i32 8) + ; CHECK: ee.ldf.64.xp + tail call void @llvm.xtensa.ee.ldqa.s16.128.ip(i32 5, i32 160) + ; CHECK: ee.ldqa.s16.128.ip + tail call void @llvm.xtensa.ee.ldqa.s16.128.xp(i32 13, i32 5) + ; CHECK: ee.ldqa.s16.128.xp + tail call void @llvm.xtensa.ee.ldqa.s8.128.ip(i32 13, i32 640) + ; CHECK: ee.ldqa.s8.128.ip + tail call void @llvm.xtensa.ee.ldqa.s8.128.xp(i32 2, i32 13) + ; CHECK: ee.ldqa.s8.128.xp + tail call void @llvm.xtensa.ee.ldqa.u16.128.ip(i32 11, i32 -1184) + ; CHECK: ee.ldqa.u16.128.ip + tail call void @llvm.xtensa.ee.ldqa.u16.128.xp(i32 1, i32 14) + ; CHECK: ee.ldqa.u16.128.xp + tail call void @llvm.xtensa.ee.ldqa.u8.128.ip(i32 14, i32 736) + ; CHECK: ee.ldqa.u8.128.ip + tail call void @llvm.xtensa.ee.ldqa.u8.128.xp(i32 2, i32 13) + ; CHECK: ee.ldqa.u8.128.xp + tail call void @llvm.xtensa.ee.ldxq.32(i32 2, i32 4, i32 0, i32 1, i32 0) + ; CHECK: ee.ldxq.32 + tail call void @llvm.xtensa.ee.ld.128.usar.ip(i32 6, i32 7, i32 1904) + ; CHECK: ee.ld.128.usar.ip + tail call void @llvm.xtensa.ee.ld.128.usar.xp(i32 0, i32 10, i32 8) + ; CHECK: ee.ld.128.usar.xp + tail call void @llvm.xtensa.ee.ld.accx.ip(i32 6, i32 -560) + ; CHECK: ee.ld.accx.ip + tail call void @llvm.xtensa.ee.ld.qacc.h.h.32.ip(i32 6, i32 68) + ; CHECK: ee.ld.qacc_h.h.32.ip + tail call void @llvm.xtensa.ee.ld.qacc.h.l.128.ip(i32 7, i32 304) + ; CHECK: ee.ld.qacc_h.l.128.ip + tail call void @llvm.xtensa.ee.ld.qacc.l.h.32.ip(i32 4, i32 52) + ; CHECK: ee.ld.qacc_l.h.32.ip + tail call void @llvm.xtensa.ee.ld.qacc.l.l.128.ip(i32 7, i32 1040) + ; CHECK: ee.ld.qacc_l.l.128.ip + tail call void @llvm.xtensa.ee.ld.ua.state.ip(i32 7, i32 -1760) + ; CHECK: ee.ld.ua_state.ip + tail call void @llvm.xtensa.ee.movi.32.a(i32 0, i32 7, i32 0) + ; CHECK: ee.movi.32.a + tail call void @llvm.xtensa.ee.movi.32.q(i32 0, i32 1, i32 2) + ; CHECK: ee.movi.32.q + tail call void @llvm.xtensa.ee.mov.s16.qacc(i32 0) + ; CHECK: ee.mov.s16.qacc + tail call void @llvm.xtensa.ee.mov.s8.qacc(i32 0) + ; CHECK: ee.mov.s8.qacc + tail call void @llvm.xtensa.ee.mov.u16.qacc(i32 2) + ; CHECK: ee.mov.u16.qacc + tail call void @llvm.xtensa.ee.mov.u8.qacc(i32 6) + ; CHECK: ee.mov.u8.qacc + tail call void @llvm.xtensa.ee.notq(i32 6, i32 7) + ; CHECK: ee.notq + tail call void @llvm.xtensa.ee.orq(i32 1, i32 2, i32 5) + ; CHECK: ee.orq + tail call void @llvm.xtensa.ee.slci.2q(i32 5, i32 2, i32 8) + ; CHECK: ee.slci.2q + tail call void @llvm.xtensa.ee.slcxxp.2q(i32 2, i32 4, i32 2, i32 11) + ; CHECK: ee.slcxxp.2q + tail call void @llvm.xtensa.ee.srci.2q(i32 4, i32 0, i32 7) + ; CHECK: ee.srci.2q + tail call void @llvm.xtensa.ee.srcmb.s16.qacc(i32 6, i32 5, i32 0) + ; CHECK: ee.srcmb.s16.qacc + tail call void @llvm.xtensa.ee.srcmb.s8.qacc(i32 1, i32 7, i32 1) + ; CHECK: ee.srcmb.s8.qacc + tail call void @llvm.xtensa.ee.srcq.128.st.incp(i32 5, i32 3, i32 6) + ; CHECK: ee.srcq.128.st.incp + tail call void @llvm.xtensa.ee.srcxxp.2q(i32 1, i32 1, i32 1, i32 11) + ; CHECK: ee.srcxxp.2q + tail call void @llvm.xtensa.ee.src.q(i32 7, i32 3, i32 0) + ; CHECK: ee.src.q + tail call void @llvm.xtensa.ee.src.q.ld.ip(i32 1, i32 10, i32 1856, i32 4, i32 0) + ; CHECK: ee.src.q.ld.ip + tail call void @llvm.xtensa.ee.src.q.ld.xp(i32 7, i32 1, i32 1, i32 0, i32 3) + ; CHECK: ee.src.q.ld.xp + tail call void @llvm.xtensa.ee.src.q.qup(i32 5, i32 2, i32 0) + ; CHECK: ee.src.q.qup + tail call void @llvm.xtensa.ee.srs.accx(i32 3, i32 6, i32 1) + ; CHECK: ee.srs.accx + tail call void @llvm.xtensa.ee.stf.128.ip(float 0x40099999A0000000, float 0x40099999A0000000, float 0x40099999A0000000, float 0x40099999A0000000, i32 10, i32 -96) + ; CHECK: ee.stf.128.ip + tail call void @llvm.xtensa.ee.stf.128.xp(float 0x40099999A0000000, float 0x40099999A0000000, float 0x40099999A0000000, float 0x40099999A0000000, i32 1, i32 6) + ; CHECK: ee.stf.128.xp + tail call void @llvm.xtensa.ee.stf.64.ip(float 0x40099999A0000000, float 0x40099999A0000000, i32 8, i32 184) + ; CHECK: ee.stf.64.ip + tail call void @llvm.xtensa.ee.stf.64.xp(float 0x40099999A0000000, float 0x40099999A0000000, i32 1, i32 7) + ; CHECK: ee.stf.64.xp + tail call void @llvm.xtensa.ee.stxq.32(i32 2, i32 5, i32 2, i32 0, i32 4) + ; CHECK: ee.stxq.32 + tail call void @llvm.xtensa.ee.st.accx.ip(i32 4, i32 -136) + ; CHECK: ee.st.accx.ip + tail call void @llvm.xtensa.ee.st.qacc.h.h.32.ip(i32 14, i32 96) + ; CHECK: ee.st.qacc_h.h.32.ip + tail call void @llvm.xtensa.ee.st.qacc.h.l.128.ip(i32 5, i32 -496) + ; CHECK: ee.st.qacc_h.l.128.ip + tail call void @llvm.xtensa.ee.st.qacc.l.h.32.ip(i32 12, i32 348) + ; CHECK: ee.st.qacc_l.h.32.ip + tail call void @llvm.xtensa.ee.st.qacc.l.l.128.ip(i32 9, i32 592) + ; CHECK: ee.st.qacc_l.l.128.ip + tail call void @llvm.xtensa.ee.st.ua.state.ip(i32 11, i32 -1568) + ; CHECK: ee.st.ua_state.ip + tail call void @llvm.xtensa.ee.vadds.s16(i32 2, i32 3, i32 6) + ; CHECK: ee.vadds.s16 + tail call void @llvm.xtensa.ee.vadds.s16.ld.incp(i32 6, i32 5, i32 4, i32 6, i32 1) + ; CHECK: ee.vadds.s16.ld.incp + tail call void @llvm.xtensa.ee.vadds.s16.st.incp(i32 6, i32 9, i32 7, i32 6, i32 2) + ; CHECK: ee.vadds.s16.st.incp + tail call void @llvm.xtensa.ee.vadds.s32(i32 7, i32 3, i32 1) + ; CHECK: ee.vadds.s32 + tail call void @llvm.xtensa.ee.vadds.s32.ld.incp(i32 1, i32 8, i32 7, i32 1, i32 3) + ; CHECK: ee.vadds.s32.ld.incp + tail call void @llvm.xtensa.ee.vadds.s32.st.incp(i32 5, i32 4, i32 3, i32 1, i32 7) + ; CHECK: ee.vadds.s32.st.incp + tail call void @llvm.xtensa.ee.vadds.s8(i32 7, i32 2, i32 2) + ; CHECK: ee.vadds.s8 + tail call void @llvm.xtensa.ee.vadds.s8.ld.incp(i32 6, i32 2, i32 0, i32 3, i32 0) + ; CHECK: ee.vadds.s8.ld.incp + tail call void @llvm.xtensa.ee.vadds.s8.st.incp(i32 1, i32 7, i32 2, i32 3, i32 4) + ; CHECK: ee.vadds.s8.st.incp + tail call void @llvm.xtensa.ee.vcmp.eq.s16(i32 5, i32 3, i32 2) + ; CHECK: ee.vcmp.eq.s16 + tail call void @llvm.xtensa.ee.vcmp.eq.s32(i32 3, i32 3, i32 5) + ; CHECK: ee.vcmp.eq.s32 + tail call void @llvm.xtensa.ee.vcmp.eq.s8(i32 2, i32 6, i32 0) + ; CHECK: ee.vcmp.eq.s8 + tail call void @llvm.xtensa.ee.vcmp.gt.s16(i32 6, i32 2, i32 0) + ; CHECK: ee.vcmp.gt.s16 + tail call void @llvm.xtensa.ee.vcmp.gt.s32(i32 6, i32 7, i32 2) + ; CHECK: ee.vcmp.gt.s32 + tail call void @llvm.xtensa.ee.vcmp.gt.s8(i32 0, i32 3, i32 5) + ; CHECK: ee.vcmp.gt.s8 + tail call void @llvm.xtensa.ee.vcmp.lt.s16(i32 6, i32 6, i32 6) + ; CHECK: ee.vcmp.lt.s16 + tail call void @llvm.xtensa.ee.vcmp.lt.s32(i32 2, i32 2, i32 6) + ; CHECK: ee.vcmp.lt.s32 + tail call void @llvm.xtensa.ee.vcmp.lt.s8(i32 0, i32 3, i32 4) + ; CHECK: ee.vcmp.lt.s8 + tail call void @llvm.xtensa.ee.vldbc.16(i32 0, i32 7) + ; CHECK: ee.vldbc.16 + tail call void @llvm.xtensa.ee.vldbc.16.ip(i32 6, i32 10, i32 220) + ; CHECK: ee.vldbc.16.ip + tail call void @llvm.xtensa.ee.vldbc.16.xp(i32 5, i32 10, i32 9) + ; CHECK: ee.vldbc.16.xp + tail call void @llvm.xtensa.ee.vldbc.32(i32 1, i32 6) + ; CHECK: ee.vldbc.32 + tail call void @llvm.xtensa.ee.vldbc.32.ip(i32 4, i32 9, i32 -352) + ; CHECK: ee.vldbc.32.ip + tail call void @llvm.xtensa.ee.vldbc.32.xp(i32 7, i32 10, i32 7) + ; CHECK: ee.vldbc.32.xp + tail call void @llvm.xtensa.ee.vldbc.8(i32 6, i32 7) + ; CHECK: ee.vldbc.8 + tail call void @llvm.xtensa.ee.vldbc.8.ip(i32 1, i32 8, i32 124) + ; CHECK: ee.vldbc.8.ip + tail call void @llvm.xtensa.ee.vldbc.8.xp(i32 1, i32 9, i32 14) + ; CHECK: ee.vldbc.8.xp + tail call void @llvm.xtensa.ee.vldhbc.16.incp(i32 5, i32 0, i32 0) + ; CHECK: ee.vldhbc.16.incp + tail call void @llvm.xtensa.ee.vld.128.ip(i32 5, i32 4, i32 1344) + ; CHECK: ee.vld.128.ip + tail call void @llvm.xtensa.ee.vld.128.xp(i32 6, i32 9, i32 8) + ; CHECK: ee.vld.128.xp + tail call void @llvm.xtensa.ee.vld.h.64.ip(i32 6, i32 3, i32 408) + ; CHECK: ee.vld.h.64.ip + tail call void @llvm.xtensa.ee.vld.h.64.xp(i32 7, i32 6, i32 7) + ; CHECK: ee.vld.h.64.xp + tail call void @llvm.xtensa.ee.vld.l.64.ip(i32 6, i32 4, i32 -752) + ; CHECK: ee.vld.l.64.ip + tail call void @llvm.xtensa.ee.vld.l.64.xp(i32 6, i32 9, i32 8) + ; CHECK: ee.vld.l.64.xp + tail call void @llvm.xtensa.ee.vmax.s16(i32 5, i32 6, i32 7) + ; CHECK: ee.vmax.s16 + tail call void @llvm.xtensa.ee.vmax.s16.ld.incp(i32 7, i32 5, i32 7, i32 5, i32 3) + ; CHECK: ee.vmax.s16.ld.incp + tail call void @llvm.xtensa.ee.vmax.s16.st.incp(i32 2, i32 0, i32 7, i32 5, i32 2) + ; CHECK: ee.vmax.s16.st.incp + tail call void @llvm.xtensa.ee.vmax.s32(i32 5, i32 5, i32 3) + ; CHECK: ee.vmax.s32 + tail call void @llvm.xtensa.ee.vmax.s32.ld.incp(i32 3, i32 8, i32 5, i32 2, i32 5) + ; CHECK: ee.vmax.s32.ld.incp + tail call void @llvm.xtensa.ee.vmax.s32.st.incp(i32 0, i32 1, i32 2, i32 7, i32 3) + ; CHECK: ee.vmax.s32.st.incp + tail call void @llvm.xtensa.ee.vmax.s8(i32 5, i32 2, i32 5) + ; CHECK: ee.vmax.s8 + tail call void @llvm.xtensa.ee.vmax.s8.ld.incp(i32 6, i32 7, i32 5, i32 4, i32 2) + ; CHECK: ee.vmax.s8.ld.incp + tail call void @llvm.xtensa.ee.vmax.s8.st.incp(i32 2, i32 1, i32 1, i32 3, i32 1) + ; CHECK: ee.vmax.s8.st.incp + tail call void @llvm.xtensa.ee.vmin.s16(i32 0, i32 1, i32 0) + ; CHECK: ee.vmin.s16 + tail call void @llvm.xtensa.ee.vmin.s16.ld.incp(i32 7, i32 0, i32 4, i32 7, i32 6) + ; CHECK: ee.vmin.s16.ld.incp + tail call void @llvm.xtensa.ee.vmin.s16.st.incp(i32 4, i32 3, i32 7, i32 4, i32 5) + ; CHECK: ee.vmin.s16.st.incp + tail call void @llvm.xtensa.ee.vmin.s32(i32 4, i32 0, i32 4) + ; CHECK: ee.vmin.s32 + tail call void @llvm.xtensa.ee.vmin.s32.ld.incp(i32 3, i32 8, i32 1, i32 0, i32 3) + ; CHECK: ee.vmin.s32.ld.incp + tail call void @llvm.xtensa.ee.vmin.s32.st.incp(i32 4, i32 9, i32 7, i32 6, i32 6) + ; CHECK: ee.vmin.s32.st.incp + tail call void @llvm.xtensa.ee.vmin.s8(i32 5, i32 7, i32 6) + ; CHECK: ee.vmin.s8 + tail call void @llvm.xtensa.ee.vmin.s8.ld.incp(i32 3, i32 3, i32 6, i32 1, i32 0) + ; CHECK: ee.vmin.s8.ld.incp + tail call void @llvm.xtensa.ee.vmin.s8.st.incp(i32 4, i32 3, i32 7, i32 5, i32 1) + ; CHECK: ee.vmin.s8.st.incp + tail call void @llvm.xtensa.ee.vmulas.s16.accx(i32 6, i32 7) + ; CHECK: ee.vmulas.s16.accx + tail call void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip(i32 2, i32 2, i32 96, i32 2, i32 5) + ; CHECK: ee.vmulas.s16.accx.ld.ip + tail call void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip.qup(i32 5, i32 5, i32 -96, i32 3, i32 5, i32 0, i32 5) + ; CHECK: ee.vmulas.s16.accx.ld.ip.qup + tail call void @llvm.xtensa.ee.vmulas.s16.accx.ld.xp(i32 7, i32 1, i32 3, i32 2, i32 6) + ; CHECK: ee.vmulas.s16.accx.ld.xp + tail call void @llvm.xtensa.ee.vmulas.s16.accx.ld.xp.qup(i32 5, i32 7, i32 8, i32 1, i32 3, i32 2, i32 5) + ; CHECK: ee.vmulas.s16.accx.ld.xp.qup + tail call void @llvm.xtensa.ee.vmulas.s16.qacc(i32 5, i32 7) + ; CHECK: ee.vmulas.s16.qacc + tail call void @llvm.xtensa.ee.vmulas.s16.qacc.ldbc.incp(i32 0, i32 8, i32 4, i32 3) + ; CHECK: ee.vmulas.s16.qacc.ldbc.incp + tail call void @llvm.xtensa.ee.vmulas.s16.qacc.ldbc.incp.qup(i32 5, i32 12, i32 1, i32 7, i32 7, i32 4) + ; CHECK: ee.vmulas.s16.qacc.ldbc.incp.qup + tail call void @llvm.xtensa.ee.vmulas.s16.qacc.ld.ip(i32 3, i32 9, i32 -112, i32 1, i32 6) + ; CHECK: ee.vmulas.s16.qacc.ld.ip + tail call void @llvm.xtensa.ee.vmulas.s16.qacc.ld.ip.qup(i32 2, i32 12, i32 -112, i32 0, i32 2, i32 7, i32 0) + ; CHECK: ee.vmulas.s16.qacc.ld.ip.qup + tail call void @llvm.xtensa.ee.vmulas.s16.qacc.ld.xp(i32 1, i32 1, i32 10, i32 0, i32 5) + ; CHECK: ee.vmulas.s16.qacc.ld.xp + tail call void @llvm.xtensa.ee.vmulas.s16.qacc.ld.xp.qup(i32 5, i32 4, i32 14, i32 7, i32 1, i32 1, i32 6) + ; CHECK: ee.vmulas.s16.qacc.ld.xp.qup + tail call void @llvm.xtensa.ee.vmulas.s8.accx(i32 5, i32 1) + ; CHECK: ee.vmulas.s8.accx + tail call void @llvm.xtensa.ee.vmulas.s8.accx.ld.ip(i32 4, i32 1, i32 -112, i32 0, i32 1) + ; CHECK: ee.vmulas.s8.accx.ld.ip + tail call void @llvm.xtensa.ee.vmulas.s8.accx.ld.ip.qup(i32 3, i32 11, i32 64, i32 6, i32 0, i32 1, i32 1) + ; CHECK: ee.vmulas.s8.accx.ld.ip.qup + tail call void @llvm.xtensa.ee.vmulas.s8.accx.ld.xp(i32 1, i32 0, i32 9, i32 7, i32 7) + ; CHECK: ee.vmulas.s8.accx.ld.xp + tail call void @llvm.xtensa.ee.vmulas.s8.accx.ld.xp.qup(i32 0, i32 6, i32 12, i32 2, i32 3, i32 6, i32 5) + ; CHECK: ee.vmulas.s8.accx.ld.xp.qup + tail call void @llvm.xtensa.ee.vmulas.s8.qacc(i32 4, i32 0) + ; CHECK: ee.vmulas.s8.qacc + tail call void @llvm.xtensa.ee.vmulas.s8.qacc.ldbc.incp(i32 6, i32 12, i32 6, i32 3) + ; CHECK: ee.vmulas.s8.qacc.ldbc.incp + tail call void @llvm.xtensa.ee.vmulas.s8.qacc.ldbc.incp.qup(i32 7, i32 14, i32 2, i32 3, i32 1, i32 6) + ; CHECK: ee.vmulas.s8.qacc.ldbc.incp.qup + tail call void @llvm.xtensa.ee.vmulas.s8.qacc.ld.ip(i32 6, i32 3, i32 0, i32 6, i32 1) + ; CHECK: ee.vmulas.s8.qacc.ld.ip + tail call void @llvm.xtensa.ee.vmulas.s8.qacc.ld.ip.qup(i32 2, i32 14, i32 16, i32 1, i32 4, i32 0, i32 1) + ; CHECK: ee.vmulas.s8.qacc.ld.ip.qup + tail call void @llvm.xtensa.ee.vmulas.s8.qacc.ld.xp(i32 0, i32 2, i32 5, i32 7, i32 4) + ; CHECK: ee.vmulas.s8.qacc.ld.xp + tail call void @llvm.xtensa.ee.vmulas.s8.qacc.ld.xp.qup(i32 3, i32 2, i32 7, i32 5, i32 4, i32 3, i32 0) + ; CHECK: ee.vmulas.s8.qacc.ld.xp.qup + tail call void @llvm.xtensa.ee.vmulas.u16.accx(i32 0, i32 0) + ; CHECK: ee.vmulas.u16.accx + tail call void @llvm.xtensa.ee.vmulas.u16.accx.ld.ip(i32 0, i32 0, i32 64, i32 7, i32 2) + ; CHECK: ee.vmulas.u16.accx.ld.ip + tail call void @llvm.xtensa.ee.vmulas.u16.accx.ld.ip.qup(i32 5, i32 3, i32 96, i32 1, i32 1, i32 0, i32 0) + ; CHECK: ee.vmulas.u16.accx.ld.ip.qup + tail call void @llvm.xtensa.ee.vmulas.u16.accx.ld.xp(i32 6, i32 12, i32 9, i32 1, i32 5) + ; CHECK: ee.vmulas.u16.accx.ld.xp + tail call void @llvm.xtensa.ee.vmulas.u16.accx.ld.xp.qup(i32 7, i32 11, i32 14, i32 3, i32 3, i32 3, i32 0) + ; CHECK: ee.vmulas.u16.accx.ld.xp.qup + tail call void @llvm.xtensa.ee.vmulas.u16.qacc(i32 5, i32 7) + ; CHECK: ee.vmulas.u16.qacc + tail call void @llvm.xtensa.ee.vmulas.u16.qacc.ldbc.incp(i32 6, i32 8, i32 0, i32 3) + ; CHECK: ee.vmulas.u16.qacc.ldbc.incp + tail call void @llvm.xtensa.ee.vmulas.u16.qacc.ldbc.incp.qup(i32 6, i32 9, i32 7, i32 7, i32 6, i32 0) + ; CHECK: ee.vmulas.u16.qacc.ldbc.incp.qup + tail call void @llvm.xtensa.ee.vmulas.u16.qacc.ld.ip(i32 4, i32 9, i32 16, i32 0, i32 4) + ; CHECK: ee.vmulas.u16.qacc.ld.ip + tail call void @llvm.xtensa.ee.vmulas.u16.qacc.ld.ip.qup(i32 2, i32 8, i32 64, i32 6, i32 2, i32 6, i32 6) + ; CHECK: ee.vmulas.u16.qacc.ld.ip.qup + tail call void @llvm.xtensa.ee.vmulas.u16.qacc.ld.xp(i32 4, i32 7, i32 14, i32 3, i32 2) + ; CHECK: ee.vmulas.u16.qacc.ld.xp + tail call void @llvm.xtensa.ee.vmulas.u16.qacc.ld.xp.qup(i32 2, i32 9, i32 9, i32 2, i32 4, i32 5, i32 3) + ; CHECK: ee.vmulas.u16.qacc.ld.xp.qup + tail call void @llvm.xtensa.ee.vmulas.u8.accx(i32 7, i32 6) + ; CHECK: ee.vmulas.u8.accx + tail call void @llvm.xtensa.ee.vmulas.u8.accx.ld.ip(i32 2, i32 7, i32 -48, i32 1, i32 1) + ; CHECK: ee.vmulas.u8.accx.ld.ip + tail call void @llvm.xtensa.ee.vmulas.u8.accx.ld.ip.qup(i32 5, i32 8, i32 16, i32 2, i32 3, i32 5, i32 5) + ; CHECK: ee.vmulas.u8.accx.ld.ip.qup + tail call void @llvm.xtensa.ee.vmulas.u8.accx.ld.xp(i32 3, i32 8, i32 14, i32 3, i32 4) + ; CHECK: ee.vmulas.u8.accx.ld.xp + tail call void @llvm.xtensa.ee.vmulas.u8.accx.ld.xp.qup(i32 4, i32 12, i32 3, i32 1, i32 6, i32 1, i32 7) + ; CHECK: ee.vmulas.u8.accx.ld.xp.qup + tail call void @llvm.xtensa.ee.vmulas.u8.qacc(i32 0, i32 3) + ; CHECK: ee.vmulas.u8.qacc + tail call void @llvm.xtensa.ee.vmulas.u8.qacc.ldbc.incp(i32 4, i32 8, i32 2, i32 4) + ; CHECK: ee.vmulas.u8.qacc.ldbc.incp + tail call void @llvm.xtensa.ee.vmulas.u8.qacc.ldbc.incp.qup(i32 0, i32 2, i32 4, i32 5, i32 6, i32 7) + ; CHECK: ee.vmulas.u8.qacc.ldbc.incp.qup + tail call void @llvm.xtensa.ee.vmulas.u8.qacc.ld.ip(i32 6, i32 2, i32 -128, i32 5, i32 3) + ; CHECK: ee.vmulas.u8.qacc.ld.ip + tail call void @llvm.xtensa.ee.vmulas.u8.qacc.ld.ip.qup(i32 7, i32 1, i32 48, i32 5, i32 6, i32 5, i32 5) + ; CHECK: ee.vmulas.u8.qacc.ld.ip.qup + tail call void @llvm.xtensa.ee.vmulas.u8.qacc.ld.xp(i32 1, i32 9, i32 12, i32 4, i32 2) + ; CHECK: ee.vmulas.u8.qacc.ld.xp + tail call void @llvm.xtensa.ee.vmulas.u8.qacc.ld.xp.qup(i32 7, i32 13, i32 13, i32 0, i32 4, i32 2, i32 6) + ; CHECK: ee.vmulas.u8.qacc.ld.xp.qup + tail call void @llvm.xtensa.ee.vmul.s16(i32 4, i32 1, i32 0) + ; CHECK: ee.vmul.s16 + tail call void @llvm.xtensa.ee.vmul.s16.ld.incp(i32 0, i32 5, i32 1, i32 3, i32 5) + ; CHECK: ee.vmul.s16.ld.incp + tail call void @llvm.xtensa.ee.vmul.s16.st.incp(i32 3, i32 9, i32 3, i32 7, i32 7) + ; CHECK: ee.vmul.s16.st.incp + tail call void @llvm.xtensa.ee.vmul.s8(i32 3, i32 7, i32 7) + ; CHECK: ee.vmul.s8 + tail call void @llvm.xtensa.ee.vmul.s8.ld.incp(i32 3, i32 0, i32 4, i32 3, i32 1) + ; CHECK: ee.vmul.s8.ld.incp + tail call void @llvm.xtensa.ee.vmul.s8.st.incp(i32 7, i32 14, i32 1, i32 4, i32 4) + ; CHECK: ee.vmul.s8.st.incp + tail call void @llvm.xtensa.ee.vmul.u16(i32 5, i32 6, i32 3) + ; CHECK: ee.vmul.u16 + tail call void @llvm.xtensa.ee.vmul.u16.ld.incp(i32 0, i32 12, i32 3, i32 0, i32 6) + ; CHECK: ee.vmul.u16.ld.incp + tail call void @llvm.xtensa.ee.vmul.u16.st.incp(i32 0, i32 14, i32 0, i32 5, i32 7) + ; CHECK: ee.vmul.u16.st.incp + tail call void @llvm.xtensa.ee.vmul.u8(i32 5, i32 1, i32 2) + ; CHECK: ee.vmul.u8 + tail call void @llvm.xtensa.ee.vmul.u8.ld.incp(i32 3, i32 6, i32 4, i32 4, i32 0) + ; CHECK: ee.vmul.u8.ld.incp + tail call void @llvm.xtensa.ee.vmul.u8.st.incp(i32 4, i32 13, i32 4, i32 4, i32 2) + ; CHECK: ee.vmul.u8.st.incp + tail call void @llvm.xtensa.ee.vprelu.s16(i32 5, i32 2, i32 5, i32 3) + ; CHECK: ee.vprelu.s16 + tail call void @llvm.xtensa.ee.vprelu.s8(i32 7, i32 7, i32 0, i32 14) + ; CHECK: ee.vprelu.s8 + tail call void @llvm.xtensa.ee.vrelu.s16(i32 3, i32 4, i32 4) + ; CHECK: ee.vrelu.s16 + tail call void @llvm.xtensa.ee.vrelu.s8(i32 5, i32 8, i32 5) + ; CHECK: ee.vrelu.s8 + tail call void @llvm.xtensa.ee.vsl.32(i32 6, i32 6) + ; CHECK: ee.vsl.32 + tail call void @llvm.xtensa.ee.vsmulas.s16.qacc(i32 2, i32 3, i32 5) + ; CHECK: ee.vsmulas.s16.qacc + tail call void @llvm.xtensa.ee.vsmulas.s16.qacc.ld.incp(i32 5, i32 11, i32 7, i32 6, i32 6) + ; CHECK: ee.vsmulas.s16.qacc.ld.incp + tail call void @llvm.xtensa.ee.vsmulas.s8.qacc(i32 6, i32 4, i32 9) + ; CHECK: ee.vsmulas.s8.qacc + tail call void @llvm.xtensa.ee.vsmulas.s8.qacc.ld.incp(i32 3, i32 10, i32 7, i32 1, i32 2) + ; CHECK: ee.vsmulas.s8.qacc.ld.incp + tail call void @llvm.xtensa.ee.vsr.32(i32 6, i32 6) + ; CHECK: ee.vsr.32 + tail call void @llvm.xtensa.ee.vst.128.ip(i32 1, i32 2, i32 160) + ; CHECK: ee.vst.128.ip + tail call void @llvm.xtensa.ee.vst.128.xp(i32 1, i32 12, i32 0) + ; CHECK: ee.vst.128.xp + tail call void @llvm.xtensa.ee.vst.h.64.ip(i32 5, i32 3, i32 400) + ; CHECK: ee.vst.h.64.ip + tail call void @llvm.xtensa.ee.vst.h.64.xp(i32 7, i32 2, i32 0) + ; CHECK: ee.vst.h.64.xp + tail call void @llvm.xtensa.ee.vst.l.64.ip(i32 0, i32 12, i32 -952) + ; CHECK: ee.vst.l.64.ip + tail call void @llvm.xtensa.ee.vst.l.64.xp(i32 2, i32 7, i32 10) + ; CHECK: ee.vst.l.64.xp + tail call void @llvm.xtensa.ee.vsubs.s16(i32 0, i32 3, i32 1) + ; CHECK: ee.vsubs.s16 + tail call void @llvm.xtensa.ee.vsubs.s16.ld.incp(i32 0, i32 13, i32 1, i32 2, i32 1) + ; CHECK: ee.vsubs.s16.ld.incp + tail call void @llvm.xtensa.ee.vsubs.s16.st.incp(i32 4, i32 7, i32 6, i32 6, i32 3) + ; CHECK: ee.vsubs.s16.st.incp + tail call void @llvm.xtensa.ee.vsubs.s32(i32 1, i32 6, i32 7) + ; CHECK: ee.vsubs.s32 + tail call void @llvm.xtensa.ee.vsubs.s32.ld.incp(i32 5, i32 11, i32 0, i32 6, i32 7) + ; CHECK: ee.vsubs.s32.ld.incp + tail call void @llvm.xtensa.ee.vsubs.s32.st.incp(i32 4, i32 9, i32 0, i32 0, i32 2) + ; CHECK: ee.vsubs.s32.st.incp + tail call void @llvm.xtensa.ee.vsubs.s8(i32 6, i32 1, i32 0) + ; CHECK: ee.vsubs.s8 + tail call void @llvm.xtensa.ee.vsubs.s8.ld.incp(i32 5, i32 12, i32 5, i32 4, i32 7) + ; CHECK: ee.vsubs.s8.ld.incp + tail call void @llvm.xtensa.ee.vsubs.s8.st.incp(i32 1, i32 11, i32 5, i32 2, i32 3) + ; CHECK: ee.vsubs.s8.st.incp + tail call void @llvm.xtensa.ee.vunzip.16(i32 3, i32 4) + ; CHECK: ee.vunzip.16 + tail call void @llvm.xtensa.ee.vunzip.32(i32 7, i32 3) + ; CHECK: ee.vunzip.32 + tail call void @llvm.xtensa.ee.vunzip.8(i32 4, i32 2) + ; CHECK: ee.vunzip.8 + tail call void @llvm.xtensa.ee.vzip.16(i32 2, i32 0) + ; CHECK: ee.vzip.16 + tail call void @llvm.xtensa.ee.vzip.32(i32 0, i32 3) + ; CHECK: ee.vzip.32 + tail call void @llvm.xtensa.ee.vzip.8(i32 5, i32 6) + ; CHECK: ee.vzip.8 + tail call void @llvm.xtensa.ee.xorq(i32 0, i32 7, i32 7) + ; CHECK: ee.xorq + tail call void @llvm.xtensa.ee.zero.accx() + ; CHECK: ee.zero.accx + tail call void @llvm.xtensa.ee.zero.q(i32 4) + ; CHECK: ee.zero.q + tail call void @llvm.xtensa.ee.zero.qacc() + ; CHECK: ee.zero.qacc + tail call i32 @llvm.xtensa.rur.accx.0() + ; CHECK: rur.accx_0 + tail call i32 @llvm.xtensa.rur.accx.1() + ; CHECK: rur.accx_1 + tail call i32 @llvm.xtensa.rur.fft.bit.width() + ; CHECK: rur.fft_bit_width + tail call i32 @llvm.xtensa.rur.gpio.out() + ; CHECK: rur.gpio_out + tail call i32 @llvm.xtensa.rur.qacc.h.0() + ; CHECK: rur.qacc_h_0 + tail call i32 @llvm.xtensa.rur.qacc.h.1() + ; CHECK: rur.qacc_h_1 + tail call i32 @llvm.xtensa.rur.qacc.h.2() + ; CHECK: rur.qacc_h_2 + tail call i32 @llvm.xtensa.rur.qacc.h.3() + ; CHECK: rur.qacc_h_3 + tail call i32 @llvm.xtensa.rur.qacc.h.4() + ; CHECK: rur.qacc_h_4 + tail call i32 @llvm.xtensa.rur.qacc.l.0() + ; CHECK: rur.qacc_l_0 + tail call i32 @llvm.xtensa.rur.qacc.l.1() + ; CHECK: rur.qacc_l_1 + tail call i32 @llvm.xtensa.rur.qacc.l.2() + ; CHECK: rur.qacc_l_2 + tail call i32 @llvm.xtensa.rur.qacc.l.3() + ; CHECK: rur.qacc_l_3 + tail call i32 @llvm.xtensa.rur.qacc.l.4() + ; CHECK: rur.qacc_l_4 + tail call i32 @llvm.xtensa.rur.sar.byte() + ; CHECK: rur.sar_byte + tail call i32 @llvm.xtensa.rur.ua.state.0() + ; CHECK: rur.ua_state_0 + tail call i32 @llvm.xtensa.rur.ua.state.1() + ; CHECK: rur.ua_state_1 + tail call i32 @llvm.xtensa.rur.ua.state.2() + ; CHECK: rur.ua_state_2 + tail call i32 @llvm.xtensa.rur.ua.state.3() + ; CHECK: rur.ua_state_3 + tail call void @llvm.xtensa.wur.accx.0(i32 13) + ; CHECK: wur.accx_0 + tail call void @llvm.xtensa.wur.accx.1(i32 4) + ; CHECK: wur.accx_1 + tail call void @llvm.xtensa.wur.fft.bit.width(i32 7) + ; CHECK: wur.fft_bit_width + tail call void @llvm.xtensa.wur.gpio.out(i32 0) + ; CHECK: wur.gpio_out + tail call void @llvm.xtensa.wur.qacc.h.0(i32 8) + ; CHECK: wur.qacc_h_0 + tail call void @llvm.xtensa.wur.qacc.h.1(i32 6) + ; CHECK: wur.qacc_h_1 + tail call void @llvm.xtensa.wur.qacc.h.2(i32 12) + ; CHECK: wur.qacc_h_2 + tail call void @llvm.xtensa.wur.qacc.h.3(i32 7) + ; CHECK: wur.qacc_h_3 + tail call void @llvm.xtensa.wur.qacc.h.4(i32 2) + ; CHECK: wur.qacc_h_4 + tail call void @llvm.xtensa.wur.qacc.l.0(i32 0) + ; CHECK: wur.qacc_l_0 + tail call void @llvm.xtensa.wur.qacc.l.1(i32 6) + ; CHECK: wur.qacc_l_1 + tail call void @llvm.xtensa.wur.qacc.l.2(i32 10) + ; CHECK: wur.qacc_l_2 + tail call void @llvm.xtensa.wur.qacc.l.3(i32 2) + ; CHECK: wur.qacc_l_3 + tail call void @llvm.xtensa.wur.qacc.l.4(i32 6) + ; CHECK: wur.qacc_l_4 + tail call void @llvm.xtensa.wur.sar.byte(i32 13) + ; CHECK: wur.sar_byte + tail call void @llvm.xtensa.wur.ua.state.0(i32 0) + ; CHECK: wur.ua_state_0 + tail call void @llvm.xtensa.wur.ua.state.1(i32 9) + ; CHECK: wur.ua_state_1 + tail call void @llvm.xtensa.wur.ua.state.2(i32 3) + ; CHECK: wur.ua_state_2 + tail call void @llvm.xtensa.wur.ua.state.3(i32 3) + ; CHECK: wur.ua_state_3 + tail call void @llvm.xtensa.mv.qr(i32 0, i32 1) + ; CHECK: mv.qr + ret void +} + +declare void @llvm.xtensa.ee.andq(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.bitrev(i32, i32) nounwind +declare void @llvm.xtensa.ee.cmul.s16(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.cmul.s16.ld.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.cmul.s16.st.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.ams.s16.ld.incp(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.ams.s16.ld.incp.uaup(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.ams.s16.ld.r32.decp(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.ams.s16.st.incp(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.cmul.s16.ld.xp(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.cmul.s16.st.xp(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.r2bf.s16(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.r2bf.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.fft.vst.r32.decp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.ldf.128.ip(float, float, float, float, i32, i32) nounwind +declare void @llvm.xtensa.ee.ldf.128.xp(float, float, float, float, i32, i32) nounwind +declare void @llvm.xtensa.ee.ldf.64.ip(float, float, i32, i32) nounwind +declare void @llvm.xtensa.ee.ldf.64.xp(float, float, i32, i32) nounwind +declare void @llvm.xtensa.ee.ldqa.s16.128.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ldqa.s16.128.xp(i32, i32) nounwind +declare void @llvm.xtensa.ee.ldqa.s8.128.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ldqa.s8.128.xp(i32, i32) nounwind +declare void @llvm.xtensa.ee.ldqa.u16.128.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ldqa.u16.128.xp(i32, i32) nounwind +declare void @llvm.xtensa.ee.ldqa.u8.128.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ldqa.u8.128.xp(i32, i32) nounwind +declare void @llvm.xtensa.ee.ldxq.32(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.ld.128.usar.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.ld.128.usar.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.ld.accx.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ld.qacc.h.h.32.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ld.qacc.h.l.128.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ld.qacc.l.h.32.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ld.qacc.l.l.128.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.ld.ua.state.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.movi.32.a(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.movi.32.q(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.mov.s16.qacc(i32) nounwind +declare void @llvm.xtensa.ee.mov.s8.qacc(i32) nounwind +declare void @llvm.xtensa.ee.mov.u16.qacc(i32) nounwind +declare void @llvm.xtensa.ee.mov.u8.qacc(i32) nounwind +declare void @llvm.xtensa.ee.notq(i32, i32) nounwind +declare void @llvm.xtensa.ee.orq(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.slci.2q(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.slcxxp.2q(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.srci.2q(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.srcmb.s16.qacc(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.srcmb.s8.qacc(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.srcq.128.st.incp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.srcxxp.2q(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.src.q(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.src.q.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.src.q.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.src.q.qup(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.srs.accx(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.stf.128.ip(float, float, float, float, i32, i32) nounwind +declare void @llvm.xtensa.ee.stf.128.xp(float, float, float, float, i32, i32) nounwind +declare void @llvm.xtensa.ee.stf.64.ip(float, float, i32, i32) nounwind +declare void @llvm.xtensa.ee.stf.64.xp(float, float, i32, i32) nounwind +declare void @llvm.xtensa.ee.stxq.32(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.st.accx.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.st.qacc.h.h.32.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.st.qacc.h.l.128.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.st.qacc.l.h.32.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.st.qacc.l.l.128.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.st.ua.state.ip(i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s32(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vadds.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.eq.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.eq.s32(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.eq.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.gt.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.gt.s32(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.gt.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.lt.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.lt.s32(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vcmp.lt.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.16(i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.16.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.16.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.32(i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.32.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.32.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.8(i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.8.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vldbc.8.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vldhbc.16.incp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vld.128.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vld.128.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vld.h.64.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vld.h.64.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vld.l.64.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vld.l.64.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s32(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmax.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s32(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmin.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.accx(i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.accx.ld.ip.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.accx.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.accx.ld.xp.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.qacc(i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.qacc.ldbc.incp(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.qacc.ldbc.incp.qup(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.qacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.qacc.ld.ip.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.qacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s16.qacc.ld.xp.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.accx(i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.accx.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.accx.ld.ip.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.accx.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.accx.ld.xp.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.qacc(i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.qacc.ldbc.incp(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.qacc.ldbc.incp.qup(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.qacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.qacc.ld.ip.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.qacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.s8.qacc.ld.xp.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.accx(i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.accx.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.accx.ld.ip.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.accx.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.accx.ld.xp.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.qacc(i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.qacc.ldbc.incp(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.qacc.ldbc.incp.qup(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.qacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.qacc.ld.ip.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.qacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u16.qacc.ld.xp.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.accx(i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.accx.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.accx.ld.ip.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.accx.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.accx.ld.xp.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.qacc(i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.qacc.ldbc.incp(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.qacc.ldbc.incp.qup(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.qacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.qacc.ld.ip.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.qacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmulas.u8.qacc.ld.xp.qup(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.u16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.u16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.u16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.u8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.u8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vmul.u8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vprelu.s16(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vprelu.s8(i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vrelu.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vrelu.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsl.32(i32, i32) nounwind +declare void @llvm.xtensa.ee.vsmulas.s16.qacc(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsmulas.s16.qacc.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsmulas.s8.qacc(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsmulas.s8.qacc.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsr.32(i32, i32) nounwind +declare void @llvm.xtensa.ee.vst.128.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vst.128.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vst.h.64.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vst.h.64.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vst.l.64.ip(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vst.l.64.xp(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s16(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s32(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s8(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vsubs.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.vunzip.16(i32, i32) nounwind +declare void @llvm.xtensa.ee.vunzip.32(i32, i32) nounwind +declare void @llvm.xtensa.ee.vunzip.8(i32, i32) nounwind +declare void @llvm.xtensa.ee.vzip.16(i32, i32) nounwind +declare void @llvm.xtensa.ee.vzip.32(i32, i32) nounwind +declare void @llvm.xtensa.ee.vzip.8(i32, i32) nounwind +declare void @llvm.xtensa.ee.xorq(i32, i32, i32) nounwind +declare void @llvm.xtensa.ee.zero.accx() nounwind +declare void @llvm.xtensa.ee.zero.q(i32) nounwind +declare void @llvm.xtensa.ee.zero.qacc() nounwind +declare i32 @llvm.xtensa.rur.accx.0() nounwind +declare i32 @llvm.xtensa.rur.accx.1() nounwind +declare i32 @llvm.xtensa.rur.fft.bit.width() nounwind +declare i32 @llvm.xtensa.rur.gpio.out() nounwind +declare i32 @llvm.xtensa.rur.qacc.h.0() nounwind +declare i32 @llvm.xtensa.rur.qacc.h.1() nounwind +declare i32 @llvm.xtensa.rur.qacc.h.2() nounwind +declare i32 @llvm.xtensa.rur.qacc.h.3() nounwind +declare i32 @llvm.xtensa.rur.qacc.h.4() nounwind +declare i32 @llvm.xtensa.rur.qacc.l.0() nounwind +declare i32 @llvm.xtensa.rur.qacc.l.1() nounwind +declare i32 @llvm.xtensa.rur.qacc.l.2() nounwind +declare i32 @llvm.xtensa.rur.qacc.l.3() nounwind +declare i32 @llvm.xtensa.rur.qacc.l.4() nounwind +declare i32 @llvm.xtensa.rur.sar.byte() nounwind +declare i32 @llvm.xtensa.rur.ua.state.0() nounwind +declare i32 @llvm.xtensa.rur.ua.state.1() nounwind +declare i32 @llvm.xtensa.rur.ua.state.2() nounwind +declare i32 @llvm.xtensa.rur.ua.state.3() nounwind +declare void @llvm.xtensa.wur.accx.0(i32) nounwind +declare void @llvm.xtensa.wur.accx.1(i32) nounwind +declare void @llvm.xtensa.wur.fft.bit.width(i32) nounwind +declare void @llvm.xtensa.wur.gpio.out(i32) nounwind +declare void @llvm.xtensa.wur.qacc.h.0(i32) nounwind +declare void @llvm.xtensa.wur.qacc.h.1(i32) nounwind +declare void @llvm.xtensa.wur.qacc.h.2(i32) nounwind +declare void @llvm.xtensa.wur.qacc.h.3(i32) nounwind +declare void @llvm.xtensa.wur.qacc.h.4(i32) nounwind +declare void @llvm.xtensa.wur.qacc.l.0(i32) nounwind +declare void @llvm.xtensa.wur.qacc.l.1(i32) nounwind +declare void @llvm.xtensa.wur.qacc.l.2(i32) nounwind +declare void @llvm.xtensa.wur.qacc.l.3(i32) nounwind +declare void @llvm.xtensa.wur.qacc.l.4(i32) nounwind +declare void @llvm.xtensa.wur.sar.byte(i32) nounwind +declare void @llvm.xtensa.wur.ua.state.0(i32) nounwind +declare void @llvm.xtensa.wur.ua.state.1(i32) nounwind +declare void @llvm.xtensa.wur.ua.state.2(i32) nounwind +declare void @llvm.xtensa.wur.ua.state.3(i32) nounwind +declare void @llvm.xtensa.mv.qr(i32, i32) nounwind + diff --git a/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s b/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s index 50037ea38df156..ee37f4bca7b1b5 100644 --- a/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s +++ b/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc %s -triple=xtensa -mattr=+esp32s3 -show-encoding \ +# RUN: llvm-mc %s -triple=xtensa -mcpu=esp32s3 -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s .align 4 @@ -19,3 +19,509 @@ ee.set_bit_gpio_out 18 # CHECK-INST: ee.wr_mask_gpio_out a3, a2 # CHECK: encoding: [0x34,0x42,0x72] ee.wr_mask_gpio_out a3, a2 + +ee.andq q5, q6, q4 +# CHECK: ee.andq q5, q6, q4 # encoding: [0xc4,0xb8,0xed] +ee.bitrev q2, a6 +# CHECK: ee.bitrev q2, a6 # encoding: [0x64,0x7b,0xdd] +ee.cmul.s16 q3, q6, q2, 3 +# CHECK: ee.cmul.s16 q3, q6, q2, 3 # encoding: [0x34,0x96,0x9e] +ee.cmul.s16.ld.incp q2, a7, q5, q1, q4, 2 +# CHECK: ee.cmul.s16.ld.incp q2, a7, q5, q1, q4, 2 # encoding: [0xe7,0x60,0x2a,0x1c] +ee.cmul.s16.st.incp q7, a11, q1, q5, q2, 3 +# CHECK: ee.cmul.s16.st.incp q7, a11, q1, q5, q2, 3 # encoding: [0x3b,0x57,0x83,0x1c] +ee.fft.ams.s16.ld.incp q5, a5, q3, q1, q1, q2, q5, 1 +# CHECK: ee.fft.ams.s16.ld.incp q5, a5, q3, q1, q1, q2, q5, 1 # encoding: [0xd5,0x5a,0x4a,0x1a] +ee.fft.ams.s16.ld.incp.uaup q7, a12, q4, q1, q5, q6, q3, 0 +# CHECK: ee.fft.ams.s16.ld.incp.uaup q7, a12, q4, q1, q5, q6, q3, 0 # encoding: [0xfc,0x66,0x87,0x1a] +ee.fft.ams.s16.ld.r32.decp q6, a5, q0, q2, q7, q2, q0, 0 +# CHECK: ee.fft.ams.s16.ld.r32.decp q6, a5, q0, q2, q7, q2, q0, 0 # encoding: [0x65,0xc2,0x11,0x1b] +ee.fft.ams.s16.st.incp q3, q6, a7, a6, q5, q5, q1, 1 +# CHECK: ee.fft.ams.s16.st.incp q3, q6, a7, a6, q5, q5, q1, 1 # encoding: [0x67,0x4b,0xeb,0x14] +ee.fft.cmul.s16.ld.xp q3, a12, a6, q7, q0, q7, 2 +# CHECK: ee.fft.cmul.s16.ld.xp q3, a12, a6, q7, q0, q7, 2 # encoding: [0x6c,0x1f,0xae,0x1b] +ee.fft.cmul.s16.st.xp q4, q0, q0, a2, a8, 6, 1, 1 +# CHECK: ee.fft.cmul.s16.st.xp q4, q0, q0, a2, a8, 6, 1, 1 # encoding: [0x82,0x30,0x51,0x15] +ee.fft.r2bf.s16 q7, q1, q3, q6, 1 +# CHECK: ee.fft.r2bf.s16 q7, q1, q3, q6, 1 # encoding: [0x54,0x9d,0xfc] +ee.fft.r2bf.s16.st.incp q7, q3, q7, a2, 2 +# CHECK: ee.fft.r2bf.s16.st.incp q7, q3, q7, a2, 2 # encoding: [0x42,0xd7,0x1e,0x1d] +ee.fft.vst.r32.decp q3, a14, 0 +# CHECK: ee.fft.vst.r32.decp q3, a14, 0 # encoding: [0xe4,0xb3,0xdd] +ee.ldf.128.ip f3, f5, f8, f0, a13, 64 +# CHECK: ee.ldf.128.ip f3, f5, f8, f0, a13, 64 # encoding: [0x0d,0x80,0x35,0x10] +ee.ldf.128.xp f5, f2, f4, f4, a7, a8 +# CHECK: ee.ldf.128.xp f5, f2, f4, f4, a7, a8 # encoding: [0x87,0x44,0x52,0x11] +ee.ldf.64.ip f6, f5, a1, 488 +# CHECK: ee.ldf.64.ip f6, f5, a1, 488 # encoding: [0x41,0x65,0x74,0x1c] +ee.ldf.64.xp f0, f6, a3, a8 +# CHECK: ee.ldf.64.xp f0, f6, a3, a8 # encoding: [0x30,0x08,0x66] +ee.ldqa.s16.128.ip a11, 1904 +# CHECK: ee.ldqa.s16.128.ip a11, 1904 # encoding: [0xb4,0x70,0x01] +ee.ldqa.s16.128.xp a6, a2 +# CHECK: ee.ldqa.s16.128.xp a6, a2 # encoding: [0x64,0x42,0x7e] +ee.ldqa.s8.128.ip a8, 320 +# CHECK: ee.ldqa.s8.128.ip a8, 320 # encoding: [0x84,0x40,0x11] +ee.ldqa.s8.128.xp a6, a11 +# CHECK: ee.ldqa.s8.128.xp a6, a11 # encoding: [0x64,0x4b,0x71] +ee.ldqa.u16.128.ip a2, -1424 +# CHECK: ee.ldqa.u16.128.ip a2, -1424 # encoding: [0x24,0x70,0x05] +ee.ldqa.u16.128.xp a3, a4 +# CHECK: ee.ldqa.u16.128.xp a3, a4 # encoding: [0x34,0x44,0x7a] +ee.ldqa.u8.128.ip a4, 784 +# CHECK: ee.ldqa.u8.128.ip a4, 784 # encoding: [0x44,0x10,0x15] +ee.ldqa.u8.128.xp a4, a9 +# CHECK: ee.ldqa.u8.128.xp a4, a9 # encoding: [0x44,0x49,0x70] +ee.ldxq.32 q2, q6, a11, 2, 1 +# CHECK: ee.ldxq.32 q2, q6, a11, 2, 1 # encoding: [0xdb,0x8f,0x25,0x1c] +ee.ld.128.usar.ip q4, a8, -592 +# CHECK: ee.ld.128.usar.ip q4, a8, -592 # encoding: [0x84,0x30,0xe1] +ee.ld.128.usar.xp q1, a9, a7 +# CHECK: ee.ld.128.usar.xp q1, a9, a7 # encoding: [0x94,0x87,0x8d] +ee.ld.accx.ip a2, 720 +# CHECK: ee.ld.accx.ip a2, 720 # encoding: [0x24,0x50,0x4e] +ee.ld.qacc_h.h.32.ip a6, -292 +# CHECK: ee.ld.qacc_h.h.32.ip a6, -292 # encoding: [0x64,0x5c,0x5e] +ee.ld.qacc_h.l.128.ip a14, 96 +# CHECK: ee.ld.qacc_h.l.128.ip a14, 96 # encoding: [0xe4,0x60,0x06] +ee.ld.qacc_l.h.32.ip a0, -184 +# CHECK: ee.ld.qacc_l.h.32.ip a0, -184 # encoding: [0x04,0x48,0x16] +ee.ld.qacc_l.l.128.ip a5, -352 +# CHECK: ee.ld.qacc_l.l.128.ip a5, -352 # encoding: [0x54,0x20,0x40] +ee.ld.ua_state.ip a3, 864 +# CHECK: ee.ld.ua_state.ip a3, 864 # encoding: [0x34,0x60,0x10] +ee.movi.32.a q7, a0, 1 +# CHECK: ee.movi.32.a q7, a0, 1 # encoding: [0x04,0xf5,0xfd] +ee.movi.32.q q5, a5, 3 +# CHECK: ee.movi.32.q q5, a5, 3 # encoding: [0x54,0xbe,0xed] +ee.mov.s16.qacc q1 +# CHECK: ee.mov.s16.qacc q1 # encoding: [0x24,0xff,0xcd] +ee.mov.s8.qacc q7 +# CHECK: ee.mov.s8.qacc q7 # encoding: [0x34,0xff,0xfd] +ee.mov.u16.qacc q2 +# CHECK: ee.mov.u16.qacc q2 # encoding: [0x64,0x7f,0xdd] +ee.mov.u8.qacc q2 +# CHECK: ee.mov.u8.qacc q2 # encoding: [0x74,0x7f,0xdd] +ee.notq q7, q0 +# CHECK: ee.notq q7, q0 # encoding: [0x04,0xff,0xfd] +ee.orq q1, q5, q3 +# CHECK: ee.orq q1, q5, q3 # encoding: [0xb4,0xf4,0xcd] +ee.slci.2q q7, q4, 2 +# CHECK: ee.slci.2q q7, q4, 2 # encoding: [0x24,0xc6,0xfc] +ee.slcxxp.2q q6, q7, a11, a4 +# CHECK: ee.slcxxp.2q q6, q7, a11, a4 # encoding: [0xb4,0x74,0xb6] +ee.srci.2q q6, q6, 14 +# CHECK: ee.srci.2q q6, q6, 14 # encoding: [0xe4,0x6a,0xfc] +ee.srcmb.s16.qacc q3, a7, 0 +# CHECK: ee.srcmb.s16.qacc q3, a7, 0 # encoding: [0x74,0xf2,0xdd] +ee.srcmb.s8.qacc q4, a1, 1 +# CHECK: ee.srcmb.s8.qacc q4, a1, 1 # encoding: [0x14,0x7e,0xed] +ee.srcq.128.st.incp q1, q4, a6 +# CHECK: ee.srcq.128.st.incp q1, q4, a6 # encoding: [0x64,0x1e,0xec] +ee.srcxxp.2q q6, q0, a2, a14 +# CHECK: ee.srcxxp.2q q6, q0, a2, a14 # encoding: [0x24,0x0e,0xf6] +ee.src.q q6, q7, q5 +# CHECK: ee.src.q q6, q7, q5 # encoding: [0x64,0xf3,0xec] +ee.src.q.ld.ip q2, a2, 1792, q6, q7 +# CHECK: ee.src.q.ld.ip q2, a2, 1792, q6, q7 # encoding: [0x02,0x87,0x05,0x1c] +ee.src.q.ld.xp q2, a4, a9, q1, q7 +# CHECK: ee.src.q.ld.xp q2, a4, a9, q1, q7 # encoding: [0x94,0x47,0x04,0x1d] +ee.src.q.qup q4, q3, q7 +# CHECK: ee.src.q.qup q4, q3, q7 # encoding: [0x44,0xb7,0xfc] +ee.srs.accx a12, a1, 0 +# CHECK: ee.srs.accx a12, a1, 0 # encoding: [0x14,0x1c,0x7e] +ee.stf.128.ip f4, f3, f8, f2, a4, -128 +# CHECK: ee.stf.128.ip f4, f3, f8, f2, a4, -128 # encoding: [0x04,0x82,0x43,0x12] +ee.stf.128.xp f2, f0, f5, f8, a11, a5 +# CHECK: ee.stf.128.xp f2, f0, f5, f8, a11, a5 # encoding: [0x5b,0x58,0x20,0x13] +ee.stf.64.ip f3, f6, a10, -848 +# CHECK: ee.stf.64.ip f3, f6, a10, -848 # encoding: [0x6a,0x36,0x58,0x1c] +ee.stf.64.xp f2, f1, a1, a14 +# CHECK: ee.stf.64.xp f2, f1, a1, a14 # encoding: [0x10,0x2e,0x17] +ee.stxq.32 q5, q2, a5, 0, 1 +# CHECK: ee.stxq.32 q5, q2, a5, 0, 1 # encoding: [0x05,0x8d,0xc0,0x1c] +ee.st.accx.ip a10, 24 +# CHECK: ee.st.accx.ip a10, 24 # encoding: [0xa4,0x18,0x02] +ee.st.qacc_h.h.32.ip a14, 380 +# CHECK: ee.st.qacc_h.h.32.ip a14, 380 # encoding: [0xe4,0x7c,0x12] +ee.st.qacc_h.l.128.ip a7, -624 +# CHECK: ee.st.qacc_h.l.128.ip a7, -624 # encoding: [0x74,0x10,0x4d] +ee.st.qacc_l.h.32.ip a10, -20 +# CHECK: ee.st.qacc_l.h.32.ip a10, -20 # encoding: [0xa4,0x6c,0x5d] +ee.st.qacc_l.l.128.ip a4, 1936 +# CHECK: ee.st.qacc_l.l.128.ip a4, 1936 # encoding: [0x44,0x10,0x4c] +ee.st.ua_state.ip a4, -1728 +# CHECK: ee.st.ua_state.ip a4, -1728 # encoding: [0x44,0x40,0x1c] +ee.vadds.s16 q5, q1, q4 +# CHECK: ee.vadds.s16 q5, q1, q4 # encoding: [0x64,0xc1,0xae] +ee.vadds.s16.ld.incp q6, a6, q1, q3, q1 +# CHECK: ee.vadds.s16.ld.incp q6, a6, q1, q3, q1 # encoding: [0xd6,0xca,0x62,0x1c] +ee.vadds.s16.st.incp q4, a0, q1, q3, q1 +# CHECK: ee.vadds.s16.st.incp q4, a0, q1, q3, q1 # encoding: [0x00,0xcc,0x92,0x1c] +ee.vadds.s32 q3, q5, q2 +# CHECK: ee.vadds.s32 q3, q5, q2 # encoding: [0x74,0x95,0x9e] +ee.vadds.s32.ld.incp q4, a4, q1, q6, q5 +# CHECK: ee.vadds.s32.ld.incp q4, a4, q1, q6, q5 # encoding: [0xd4,0xab,0x43,0x1c] +ee.vadds.s32.st.incp q5, a1, q0, q6, q0 +# CHECK: ee.vadds.s32.st.incp q5, a1, q0, q6, q0 # encoding: [0x11,0x85,0x91,0x1c] +ee.vadds.s8 q4, q4, q5 +# CHECK: ee.vadds.s8 q4, q4, q5 # encoding: [0x84,0x4c,0xae] +ee.vadds.s8.ld.incp q2, a14, q0, q3, q3 +# CHECK: ee.vadds.s8.ld.incp q2, a14, q0, q3, q3 # encoding: [0xce,0xd9,0x20,0x1c] +ee.vadds.s8.st.incp q0, a9, q4, q7, q0 +# CHECK: ee.vadds.s8.st.incp q0, a9, q4, q7, q0 # encoding: [0x29,0xc0,0x99,0x1c] +ee.vcmp.eq.s16 q5, q3, q0 +# CHECK: ee.vcmp.eq.s16 q5, q3, q0 # encoding: [0x94,0x83,0xae] +ee.vcmp.eq.s32 q5, q5, q4 +# CHECK: ee.vcmp.eq.s32 q5, q5, q4 # encoding: [0xa4,0xc5,0xae] +ee.vcmp.eq.s8 q0, q4, q2 +# CHECK: ee.vcmp.eq.s8 q0, q4, q2 # encoding: [0xb4,0x14,0x8e] +ee.vcmp.gt.s16 q1, q5, q2 +# CHECK: ee.vcmp.gt.s16 q1, q5, q2 # encoding: [0xc4,0x95,0x8e] +ee.vcmp.gt.s32 q4, q1, q5 +# CHECK: ee.vcmp.gt.s32 q4, q1, q5 # encoding: [0xd4,0x49,0xae] +ee.vcmp.gt.s8 q3, q6, q3 +# CHECK: ee.vcmp.gt.s8 q3, q6, q3 # encoding: [0xe4,0x9e,0x9e] +ee.vcmp.lt.s16 q3, q7, q0 +# CHECK: ee.vcmp.lt.s16 q3, q7, q0 # encoding: [0xf4,0x87,0x9e] +ee.vcmp.lt.s32 q2, q2, q1 +# CHECK: ee.vcmp.lt.s32 q2, q2, q1 # encoding: [0x04,0x2a,0x9e] +ee.vcmp.lt.s8 q7, q1, q6 +# CHECK: ee.vcmp.lt.s8 q7, q1, q6 # encoding: [0x14,0xf1,0xbe] +ee.vldbc.16 q6, a11 +# CHECK: ee.vldbc.16 q6, a11 # encoding: [0xb4,0x73,0xfd] +ee.vldbc.16.ip q6, a4, 124 +# CHECK: ee.vldbc.16.ip q6, a4, 124 # encoding: [0x44,0x7c,0xb5] +ee.vldbc.16.xp q2, a0, a7 +# CHECK: ee.vldbc.16.xp q2, a0, a7 # encoding: [0x04,0x47,0x9d] +ee.vldbc.32 q4, a0 +# CHECK: ee.vldbc.32 q4, a0 # encoding: [0x04,0x77,0xed] +ee.vldbc.32.ip q6, a12, 308 +# CHECK: ee.vldbc.32.ip q6, a12, 308 # encoding: [0xc4,0x34,0xb2] +ee.vldbc.32.xp q1, a11, a0 +# CHECK: ee.vldbc.32.xp q1, a11, a0 # encoding: [0xb4,0x90,0x8d] +ee.vldbc.8 q2, a3 +# CHECK: ee.vldbc.8 q2, a3 # encoding: [0x34,0x3b,0xdd] +ee.vldbc.8.ip q3, a3, 103 +# CHECK: ee.vldbc.8.ip q3, a3, 103 # encoding: [0x34,0xe7,0xd5] +ee.vldbc.8.xp q2, a0, a13 +# CHECK: ee.vldbc.8.xp q2, a0, a13 # encoding: [0x04,0x5d,0x9d] +ee.vldhbc.16.incp q5, q5, a14 +# CHECK: ee.vldhbc.16.incp q5, q5, a14 # encoding: [0xe4,0xd2,0xec] +ee.vld.128.ip q3, a14, 1248 +# CHECK: ee.vld.128.ip q3, a14, 1248 # encoding: [0xe4,0xe0,0xd3] +ee.vld.128.xp q5, a10, a12 +# CHECK: ee.vld.128.xp q5, a10, a12 # encoding: [0xa4,0xac,0xad] +ee.vld.h.64.ip q4, a14, 240 +# CHECK: ee.vld.h.64.ip q4, a14, 240 # encoding: [0xe4,0x70,0xe8] +ee.vld.h.64.xp q7, a4, a8 +# CHECK: ee.vld.h.64.xp q7, a4, a8 # encoding: [0x44,0xe8,0xbd] +ee.vld.l.64.ip q1, a8, 8 +# CHECK: ee.vld.l.64.ip q1, a8, 8 # encoding: [0x84,0x88,0x89] +ee.vld.l.64.xp q1, a2, a9 +# CHECK: ee.vld.l.64.xp q1, a2, a9 # encoding: [0x24,0xb9,0x8d] +ee.vmax.s16 q2, q5, q6 +# CHECK: ee.vmax.s16 q2, q5, q6 # encoding: [0x24,0x75,0x9e] +ee.vmax.s16.ld.incp q0, a0, q6, q1, q2 +# CHECK: ee.vmax.s16.ld.incp q0, a0, q6, q1, q2 # encoding: [0xd0,0x51,0x0c,0x1c] +ee.vmax.s16.st.incp q5, a10, q6, q6, q7 +# CHECK: ee.vmax.s16.st.incp q5, a10, q6, q6, q7 # encoding: [0x3a,0xbd,0x9d,0x1c] +ee.vmax.s32 q3, q2, q7 +# CHECK: ee.vmax.s32 q3, q2, q7 # encoding: [0x34,0xfa,0x9e] +ee.vmax.s32.ld.incp q1, a3, q1, q1, q0 +# CHECK: ee.vmax.s32.ld.incp q1, a3, q1, q1, q0 # encoding: [0xe3,0x41,0x12,0x1c] +ee.vmax.s32.st.incp q3, a12, q4, q6, q3 +# CHECK: ee.vmax.s32.st.incp q3, a12, q4, q6, q3 # encoding: [0x0c,0x9b,0xa9,0x1c] +ee.vmax.s8 q4, q1, q6 +# CHECK: ee.vmax.s8 q4, q1, q6 # encoding: [0x44,0x71,0xae] +ee.vmax.s8.ld.incp q3, a10, q5, q1, q5 +# CHECK: ee.vmax.s8.ld.incp q3, a10, q5, q1, q5 # encoding: [0xfa,0x69,0x3a,0x1c] +ee.vmax.s8.st.incp q3, a9, q3, q6, q7 +# CHECK: ee.vmax.s8.st.incp q3, a9, q3, q6, q7 # encoding: [0x09,0xbb,0xb7,0x1c] +ee.vmin.s16 q6, q2, q5 +# CHECK: ee.vmin.s16 q6, q2, q5 # encoding: [0x54,0x6a,0xbe] +ee.vmin.s16.ld.incp q5, a3, q2, q4, q0 +# CHECK: ee.vmin.s16.ld.incp q5, a3, q2, q4, q0 # encoding: [0xe3,0x02,0x55,0x1c] +ee.vmin.s16.st.incp q4, a9, q4, q6, q0 +# CHECK: ee.vmin.s16.st.incp q4, a9, q4, q6, q0 # encoding: [0x19,0x84,0xa9,0x1c] +ee.vmin.s32 q1, q1, q6 +# CHECK: ee.vmin.s32 q1, q1, q6 # encoding: [0x64,0xf1,0x8e] +ee.vmin.s32.ld.incp q0, a1, q3, q2, q0 +# CHECK: ee.vmin.s32.ld.incp q0, a1, q3, q2, q0 # encoding: [0xe1,0x83,0x06,0x1c] +ee.vmin.s32.st.incp q0, a12, q4, q4, q3 +# CHECK: ee.vmin.s32.st.incp q0, a12, q4, q4, q3 # encoding: [0x1c,0x18,0xb9,0x1c] +ee.vmin.s8 q7, q6, q0 +# CHECK: ee.vmin.s8 q7, q6, q0 # encoding: [0x74,0xa6,0xbe] +ee.vmin.s8.ld.incp q2, a13, q7, q7, q3 +# CHECK: ee.vmin.s8.ld.incp q2, a13, q7, q7, q3 # encoding: [0xfd,0xda,0x2f,0x1c] +ee.vmin.s8.st.incp q2, a4, q4, q7, q1 +# CHECK: ee.vmin.s8.st.incp q2, a4, q4, q7, q1 # encoding: [0x24,0xca,0xa9,0x1c] +ee.vmulas.s16.accx q0, q7 +# CHECK: ee.vmulas.s16.accx q0, q7 # encoding: [0x84,0x58,0x1a] +ee.vmulas.s16.accx.ld.ip q7, a7, -16, q2, q0 +# CHECK: ee.vmulas.s16.accx.ld.ip q7, a7, -16, q2, q0 # encoding: [0x07,0x80,0xf0,0x1f] +ee.vmulas.s16.accx.ld.ip.qup q5, a14, 32, q0, q2, q0, q2 +# CHECK: ee.vmulas.s16.accx.ld.ip.qup q5, a14, 32, q0, q2, q0, q2 # encoding: [0x0e,0x10,0x54,0x01] +ee.vmulas.s16.accx.ld.xp q1, a0, a1, q2, q6 +# CHECK: ee.vmulas.s16.accx.ld.xp q1, a0, a1, q2, q6 # encoding: [0x10,0xb1,0x10,0x1e] +ee.vmulas.s16.accx.ld.xp.qup q4, a8, a10, q4, q0, q0, q3 +# CHECK: ee.vmulas.s16.accx.ld.xp.qup q4, a8, a10, q4, q0, q0, q3 # encoding: [0xa8,0x00,0x47,0x16] +ee.vmulas.s16.qacc q0, q6 +# CHECK: ee.vmulas.s16.qacc q0, q6 # encoding: [0x84,0x70,0x1a] +ee.vmulas.s16.qacc.ldbc.incp q2, a6, q3, q4 +# CHECK: ee.vmulas.s16.qacc.ldbc.incp q2, a6, q3, q4 # encoding: [0x64,0xc3,0x87] +ee.vmulas.s16.qacc.ldbc.incp.qup q0, a4, q1, q6, q4, q5 +# CHECK: ee.vmulas.s16.qacc.ldbc.incp.qup q0, a4, q1, q6, q4, q5 # encoding: [0x84,0x74,0x0a,0x1c] +ee.vmulas.s16.qacc.ld.ip q7, a7, -64, q7, q7 +# CHECK: ee.vmulas.s16.qacc.ld.ip q7, a7, -64, q7, q7 # encoding: [0x07,0xf8,0x73,0x1e] +ee.vmulas.s16.qacc.ld.ip.qup q0, a10, 48, q3, q6, q3, q6 +# CHECK: ee.vmulas.s16.qacc.ld.ip.qup q0, a10, 48, q3, q6, q3, q6 # encoding: [0x0a,0xf3,0x8c,0x03] +ee.vmulas.s16.qacc.ld.xp q3, a11, a4, q4, q5 +# CHECK: ee.vmulas.s16.qacc.ld.xp q3, a11, a4, q4, q5 # encoding: [0x4b,0x29,0x33,0x1e] +ee.vmulas.s16.qacc.ld.xp.qup q2, a9, a1, q3, q2, q1, q7 +# CHECK: ee.vmulas.s16.qacc.ld.xp.qup q2, a9, a1, q3, q2, q1, q7 # encoding: [0x19,0xd1,0xae,0x16] +ee.vmulas.s8.accx q1, q0 +# CHECK: ee.vmulas.s8.accx q1, q0 # encoding: [0xc4,0x01,0x1a] +ee.vmulas.s8.accx.ld.ip q2, a8, 80, q3, q0 +# CHECK: ee.vmulas.s8.accx.ld.ip q2, a8, 80, q3, q0 # encoding: [0x08,0xc0,0xa4,0x1e] +ee.vmulas.s8.accx.ld.ip.qup q2, a9, -80, q1, q2, q6, q3 +# CHECK: ee.vmulas.s8.accx.ld.ip.qup q2, a9, -80, q1, q2, q6, q3 # encoding: [0x09,0x56,0xa6,0x05] +ee.vmulas.s8.accx.ld.xp q3, a3, a4, q4, q7 +# CHECK: ee.vmulas.s8.accx.ld.xp q3, a3, a4, q4, q7 # encoding: [0x43,0x39,0x35,0x1e] +ee.vmulas.s8.accx.ld.xp.qup q0, a3, a1, q4, q5, q3, q3 +# CHECK: ee.vmulas.s8.accx.ld.xp.qup q0, a3, a1, q4, q5, q3, q3 # encoding: [0x13,0x2b,0x07,0x17] +ee.vmulas.s8.qacc q5, q7 +# CHECK: ee.vmulas.s8.qacc q5, q7 # encoding: [0xc4,0x7d,0x1a] +ee.vmulas.s8.qacc.ldbc.incp q7, a1, q6, q1 +# CHECK: ee.vmulas.s8.qacc.ldbc.incp q7, a1, q6, q1 # encoding: [0x14,0xae,0xb7] +ee.vmulas.s8.qacc.ldbc.incp.qup q3, a11, q4, q6, q5, q6 +# CHECK: ee.vmulas.s8.qacc.ldbc.incp.qup q3, a11, q4, q6, q5, q6 # encoding: [0x9b,0x35,0x3d,0x1c] +ee.vmulas.s8.qacc.ld.ip q5, a10, -16, q0, q0 +# CHECK: ee.vmulas.s8.qacc.ld.ip q5, a10, -16, q0, q0 # encoding: [0x0a,0x00,0xd6,0x1f] +ee.vmulas.s8.qacc.ld.ip.qup q7, a9, -48, q6, q2, q1, q2 +# CHECK: ee.vmulas.s8.qacc.ld.ip.qup q7, a9, -48, q6, q2, q1, q2 # encoding: [0x09,0x91,0xf5,0x06] +ee.vmulas.s8.qacc.ld.xp q1, a1, a12, q5, q0 +# CHECK: ee.vmulas.s8.qacc.ld.xp q1, a1, a12, q5, q0 # encoding: [0xc1,0x41,0x17,0x1e] +ee.vmulas.s8.qacc.ld.xp.qup q0, a1, a14, q1, q6, q2, q4 +# CHECK: ee.vmulas.s8.qacc.ld.xp.qup q0, a1, a14, q1, q6, q2, q4 # encoding: [0xe1,0x72,0x88,0x17] +ee.vmulas.u16.accx q7, q1 +# CHECK: ee.vmulas.u16.accx q7, q1 # encoding: [0x84,0x0f,0x0a] +ee.vmulas.u16.accx.ld.ip q5, a8, -32, q1, q4 +# CHECK: ee.vmulas.u16.accx.ld.ip q5, a8, -32, q1, q4 # encoding: [0x08,0x60,0x58,0x1f] +ee.vmulas.u16.accx.ld.ip.qup q1, a0, 48, q7, q4, q4, q0 +# CHECK: ee.vmulas.u16.accx.ld.ip.qup q1, a0, 48, q7, q4, q4, q0 # encoding: [0x00,0xe4,0x91,0x09] +ee.vmulas.u16.accx.ld.xp q3, a14, a4, q5, q4 +# CHECK: ee.vmulas.u16.accx.ld.xp q3, a14, a4, q5, q4 # encoding: [0x4e,0x61,0x39,0x1e] +ee.vmulas.u16.accx.ld.xp.qup q4, a3, a7, q6, q2, q4, q4 +# CHECK: ee.vmulas.u16.accx.ld.xp.qup q4, a3, a7, q6, q2, q4, q4 # encoding: [0x73,0x94,0x49,0x18] +ee.vmulas.u16.qacc q5, q5 +# CHECK: ee.vmulas.u16.qacc q5, q5 # encoding: [0x84,0x6d,0x0a] +ee.vmulas.u16.qacc.ldbc.incp q6, a7, q0, q3 +# CHECK: ee.vmulas.u16.qacc.ldbc.incp q6, a7, q0, q3 # encoding: [0x74,0x98,0xd7] +ee.vmulas.u16.qacc.ldbc.incp.qup q0, a12, q6, q3, q2, q0 +# CHECK: ee.vmulas.u16.qacc.ldbc.incp.qup q0, a12, q6, q3, q2, q0 # encoding: [0xac,0x9a,0x01,0x1c] +ee.vmulas.u16.qacc.ld.ip q4, a10, 16, q3, q2 +# CHECK: ee.vmulas.u16.qacc.ld.ip q4, a10, 16, q3, q2 # encoding: [0x0a,0xd0,0xca,0x1e] +ee.vmulas.u16.qacc.ld.ip.qup q2, a4, 0, q5, q4, q2, q6 +# CHECK: ee.vmulas.u16.qacc.ld.ip.qup q2, a4, 0, q5, q4, q2, q6 # encoding: [0x04,0x62,0x2d,0x0a] +ee.vmulas.u16.qacc.ld.xp q6, a14, a2, q4, q0 +# CHECK: ee.vmulas.u16.qacc.ld.xp q6, a14, a2, q4, q0 # encoding: [0x2e,0x01,0x6b,0x1e] +ee.vmulas.u16.qacc.ld.xp.qup q6, a12, a11, q6, q7, q4, q1 +# CHECK: ee.vmulas.u16.qacc.ld.xp.qup q6, a12, a11, q6, q7, q4, q1 # encoding: [0xbc,0xbc,0xe3,0x18] +ee.vmulas.u8.accx q2, q1 +# CHECK: ee.vmulas.u8.accx q2, q1 # encoding: [0xc4,0x0a,0x0a] +ee.vmulas.u8.accx.ld.ip q6, a3, -112, q2, q7 +# CHECK: ee.vmulas.u8.accx.ld.ip q6, a3, -112, q2, q7 # encoding: [0x03,0xb8,0xec,0x1e] +ee.vmulas.u8.accx.ld.ip.qup q7, a3, -32, q3, q3, q7, q5 +# CHECK: ee.vmulas.u8.accx.ld.ip.qup q7, a3, -32, q3, q3, q7, q5 # encoding: [0x03,0xdf,0x7a,0x0d] +ee.vmulas.u8.accx.ld.xp q4, a4, a9, q4, q0 +# CHECK: ee.vmulas.u8.accx.ld.xp q4, a4, a9, q4, q0 # encoding: [0x94,0x01,0x4d,0x1e] +ee.vmulas.u8.accx.ld.xp.qup q5, a7, a13, q4, q7, q2, q6 +# CHECK: ee.vmulas.u8.accx.ld.xp.qup q5, a7, a13, q4, q7, q2, q6 # encoding: [0xd7,0x3a,0x5d,0x19] +ee.vmulas.u8.qacc q3, q6 +# CHECK: ee.vmulas.u8.qacc q3, q6 # encoding: [0xc4,0x73,0x0a] +ee.vmulas.u8.qacc.ldbc.incp q4, a1, q0, q5 +# CHECK: ee.vmulas.u8.qacc.ldbc.incp q4, a1, q0, q5 # encoding: [0x14,0x48,0xf7] +ee.vmulas.u8.qacc.ldbc.incp.qup q2, a1, q5, q7, q6, q4 +# CHECK: ee.vmulas.u8.qacc.ldbc.incp.qup q2, a1, q5, q7, q6, q4 # encoding: [0xb1,0x7e,0x29,0x1c] +ee.vmulas.u8.qacc.ld.ip q2, a12, 32, q1, q4 +# CHECK: ee.vmulas.u8.qacc.ld.ip q2, a12, 32, q1, q4 # encoding: [0x0c,0x60,0x2e,0x1f] +ee.vmulas.u8.qacc.ld.ip.qup q0, a6, 48, q0, q0, q6, q0 +# CHECK: ee.vmulas.u8.qacc.ld.ip.qup q0, a6, 48, q0, q0, q6, q0 # encoding: [0x06,0x06,0x80,0x0f] +ee.vmulas.u8.qacc.ld.xp q6, a1, a1, q2, q5 +# CHECK: ee.vmulas.u8.qacc.ld.xp q6, a1, a1, q2, q5 # encoding: [0x11,0xa9,0x6e,0x1e] +ee.vmulas.u8.qacc.ld.xp.qup q1, a8, a10, q3, q7, q1, q3 +# CHECK: ee.vmulas.u8.qacc.ld.xp.qup q1, a8, a10, q3, q7, q1, q3 # encoding: [0xa8,0xf9,0x96,0x19] +ee.vmul.s16 q0, q4, q1 +# CHECK: ee.vmul.s16 q0, q4, q1 # encoding: [0x84,0x2c,0x8e] +ee.vmul.s16.ld.incp q4, a5, q1, q5, q5 +# CHECK: ee.vmul.s16.ld.incp q4, a5, q1, q5, q5 # encoding: [0xf5,0x6b,0x43,0x1c] +ee.vmul.s16.st.incp q4, a4, q2, q5, q0 +# CHECK: ee.vmul.s16.st.incp q4, a4, q2, q5, q0 # encoding: [0x24,0x44,0xb5,0x1c] +ee.vmul.s8 q5, q3, q2 +# CHECK: ee.vmul.s8 q5, q3, q2 # encoding: [0x94,0xb3,0xae] +ee.vmul.s8.ld.incp q6, a11, q3, q6, q4 +# CHECK: ee.vmul.s8.ld.incp q6, a11, q3, q6, q4 # encoding: [0xcb,0xa4,0x67,0x1c] +ee.vmul.s8.st.incp q5, a5, q5, q2, q4 +# CHECK: ee.vmul.s8.st.incp q5, a5, q5, q2, q4 # encoding: [0x35,0xa5,0xaa,0x1c] +ee.vmul.u16 q0, q0, q5 +# CHECK: ee.vmul.u16 q0, q0, q5 # encoding: [0xa4,0x68,0x8e] +ee.vmul.u16.ld.incp q4, a2, q0, q1, q1 +# CHECK: ee.vmul.u16.ld.incp q4, a2, q0, q1, q1 # encoding: [0xc2,0x4d,0x40,0x1c] +ee.vmul.u16.st.incp q6, a5, q1, q2, q7 +# CHECK: ee.vmul.u16.st.incp q6, a5, q1, q2, q7 # encoding: [0x35,0xbe,0xb2,0x1c] +ee.vmul.u8 q6, q4, q5 +# CHECK: ee.vmul.u8 q6, q4, q5 # encoding: [0xb4,0x6c,0xbe] +ee.vmul.u8.ld.incp q1, a5, q4, q1, q1 +# CHECK: ee.vmul.u8.ld.incp q1, a5, q4, q1, q1 # encoding: [0xc5,0x4e,0x18,0x1c] +ee.vmul.u8.st.incp q4, a12, q5, q0, q4 +# CHECK: ee.vmul.u8.st.incp q4, a12, q5, q0, q4 # encoding: [0x0c,0x24,0x1a,0x1d] +ee.vprelu.s16 q2, q7, q0, a1 +# CHECK: ee.vprelu.s16 q2, q7, q0, a1 # encoding: [0x14,0x07,0x9c] +ee.vprelu.s8 q5, q6, q5, a13 +# CHECK: ee.vprelu.s8 q5, q6, q5, a13 # encoding: [0xd4,0xee,0xac] +ee.vrelu.s16 q2, a14, a5 +# CHECK: ee.vrelu.s16 q2, a14, a5 # encoding: [0x54,0x1e,0xdd] +ee.vrelu.s8 q4, a14, a1 +# CHECK: ee.vrelu.s8 q4, a14, a1 # encoding: [0x14,0x5e,0xed] +ee.vsl.32 q0, q1 +# CHECK: ee.vsl.32 q0, q1 # encoding: [0x04,0xbf,0xcd] +ee.vsmulas.s16.qacc q2, q7, 2 +# CHECK: ee.vsmulas.s16.qacc q2, q7, 2 # encoding: [0xc4,0x7a,0x9e] +ee.vsmulas.s16.qacc.ld.incp q7, a3, q3, q4, 3 +# CHECK: ee.vsmulas.s16.qacc.ld.incp q7, a3, q3, q4, 3 # encoding: [0xc3,0xe7,0x76,0x1c] +ee.vsmulas.s8.qacc q3, q6, 3 +# CHECK: ee.vsmulas.s8.qacc q3, q6, 3 # encoding: [0x54,0xd3,0x8e] +ee.vsmulas.s8.qacc.ld.incp q1, a8, q1, q1, 4 +# CHECK: ee.vsmulas.s8.qacc.ld.incp q1, a8, q1, q1, 4 # encoding: [0xc8,0x4a,0x14,0x1c] +ee.vsr.32 q4, q3 +# CHECK: ee.vsr.32 q4, q3 # encoding: [0xc4,0xbf,0xdd] +ee.vst.128.ip q3, a6, -816 +# CHECK: ee.vst.128.ip q3, a6, -816 # encoding: [0x64,0xd0,0xda] +ee.vst.128.xp q6, a12, a14 +# CHECK: ee.vst.128.xp q6, a12, a14 # encoding: [0xc4,0x7e,0xbd] +ee.vst.h.64.ip q2, a5, 40 +# CHECK: ee.vst.h.64.ip q2, a5, 40 # encoding: [0x54,0x28,0x9b] +ee.vst.h.64.xp q2, a13, a6 +# CHECK: ee.vst.h.64.xp q2, a13, a6 # encoding: [0xd4,0x06,0xdd] +ee.vst.l.64.ip q5, a8, 16 +# CHECK: ee.vst.l.64.ip q5, a8, 16 # encoding: [0x84,0x90,0xa4] +ee.vst.l.64.xp q0, a13, a6 +# CHECK: ee.vst.l.64.xp q0, a13, a6 # encoding: [0xd4,0x46,0xcd] +ee.vsubs.s16 q5, q1, q4 +# CHECK: ee.vsubs.s16 q5, q1, q4 # encoding: [0xd4,0xe1,0xae] +ee.vsubs.s16.ld.incp q1, a4, q6, q0, q1 +# CHECK: ee.vsubs.s16.ld.incp q1, a4, q6, q0, q1 # encoding: [0xd4,0x0c,0x1c,0x1c] +ee.vsubs.s16.st.incp q7, a13, q7, q5, q2 +# CHECK: ee.vsubs.s16.st.incp q7, a13, q7, q5, q2 # encoding: [0x1d,0x57,0x1f,0x1d] +ee.vsubs.s32 q2, q7, q6 +# CHECK: ee.vsubs.s32 q2, q7, q6 # encoding: [0xe4,0x77,0x9e] +ee.vsubs.s32.ld.incp q1, a8, q1, q4, q0 +# CHECK: ee.vsubs.s32.ld.incp q1, a8, q1, q4, q0 # encoding: [0xd8,0x05,0x13,0x1c] +ee.vsubs.s32.st.incp q1, a5, q7, q4, q0 +# CHECK: ee.vsubs.s32.st.incp q1, a5, q7, q4, q0 # encoding: [0x25,0x01,0x1f,0x1d] +ee.vsubs.s8 q7, q1, q5 +# CHECK: ee.vsubs.s8 q7, q1, q5 # encoding: [0xf4,0xe9,0xbe] +ee.vsubs.s8.ld.incp q4, a2, q6, q1, q6 +# CHECK: ee.vsubs.s8.ld.incp q4, a2, q6, q1, q6 # encoding: [0xd2,0x76,0x4c,0x1c] +ee.vsubs.s8.st.incp q6, a1, q6, q2, q3 +# CHECK: ee.vsubs.s8.st.incp q6, a1, q6, q2, q3 # encoding: [0x31,0x9e,0x1c,0x1d] +ee.vunzip.16 q6, q5 +# CHECK: ee.vunzip.16 q6, q5 # encoding: [0x84,0xe3,0xec] +ee.vunzip.32 q0, q6 +# CHECK: ee.vunzip.32 q0, q6 # encoding: [0x94,0x03,0xfc] +ee.vunzip.8 q5, q1 +# CHECK: ee.vunzip.8 q5, q1 # encoding: [0xa4,0xd3,0xcc] +ee.vzip.16 q2, q0 +# CHECK: ee.vzip.16 q2, q0 # encoding: [0xb4,0x23,0xcc] +ee.vzip.32 q0, q3 +# CHECK: ee.vzip.32 q0, q3 # encoding: [0xc4,0x83,0xdc] +ee.vzip.8 q4, q5 +# CHECK: ee.vzip.8 q4, q5 # encoding: [0xd4,0xc3,0xec] +ee.xorq q1, q3, q4 +# CHECK: ee.xorq q1, q3, q4 # encoding: [0x54,0xb9,0xcd] +ee.zero.accx +# CHECK: ee.zero.accx # encoding: [0x04,0x08,0x25] +ee.zero.q q0 +# CHECK: ee.zero.q q0 # encoding: [0xa4,0x7f,0xcd] +ee.zero.qacc +# CHECK: ee.zero.qacc # encoding: [0x44,0x08,0x25] + +rur.accx_0 a11 +# CHECK: rur a11, accx # encoding: [0xd0,0xbe,0xe3] +rur.accx_1 a11 +# CHECK: rur a11, accx # encoding: [0xd0,0xbe,0xe3] +rur.fft_bit_width a11 +# CHECK: rur a11, fft_bit_width # encoding: [0xf0,0xbe,0xe3] +rur.gpio_out a3 +# CHECK: rur a3, gpio_out # encoding: [0x00,0x30,0xe3] +rur.qacc_h_0 a1 +# CHECK: rur a1, qacc # encoding: [0xe0,0x1e,0xe3] +rur.qacc_h_1 a10 +# CHECK: rur a10, qacc # encoding: [0xe0,0xae,0xe3] +rur.qacc_h_2 a2 +# CHECK: rur a2, qacc # encoding: [0xe0,0x2e,0xe3] +rur.qacc_h_3 a11 +# CHECK: rur a11, qacc # encoding: [0xe0,0xbe,0xe3] +rur.qacc_h_4 a13 +# CHECK: rur a13, qacc # encoding: [0xe0,0xde,0xe3] +rur.qacc_l_0 a8 +# CHECK: rur a8, qacc # encoding: [0xe0,0x8e,0xe3] +rur.qacc_l_1 a7 +# CHECK: rur a7, qacc # encoding: [0xe0,0x7e,0xe3] +rur.qacc_l_2 a2 +# CHECK: rur a2, qacc # encoding: [0xe0,0x2e,0xe3] +rur.qacc_l_3 a13 +# CHECK: rur a13, qacc # encoding: [0xe0,0xde,0xe3] +rur.qacc_l_4 a7 +# CHECK: rur a7, qacc # encoding: [0xe0,0x7e,0xe3] +rur.sar_byte a9 +# CHECK: rur a9, sar_byte # encoding: [0x00,0x9f,0xe3] +rur.ua_state_0 a12 +# CHECK: rur a12, ua_state # encoding: [0x10,0xcf,0xe3] +rur.ua_state_1 a2 +# CHECK: rur a2, ua_state # encoding: [0x10,0x2f,0xe3] +rur.ua_state_2 a5 +# CHECK: rur a5, ua_state # encoding: [0x10,0x5f,0xe3] +rur.ua_state_3 a3 +# CHECK: rur a3, ua_state # encoding: [0x10,0x3f,0xe3] +wur.accx_0 a6 +# CHECK: wur a6, accx # encoding: [0x60,0xed,0xf3] +wur.accx_1 a6 +# CHECK: wur a6, accx # encoding: [0x60,0xed,0xf3] +wur.fft_bit_width a13 +# CHECK: wur a13, fft_bit_width # encoding: [0xd0,0xef,0xf3] +wur.gpio_out a0 +# CHECK: wur a0, gpio_out # encoding: [0x00,0x00,0xf3] +wur.qacc_h_0 a12 +# CHECK: wur a12, qacc # encoding: [0xc0,0xee,0xf3] +wur.qacc_h_1 a1 +# CHECK: wur a1, qacc # encoding: [0x10,0xee,0xf3] +wur.qacc_h_2 a2 +# CHECK: wur a2, qacc # encoding: [0x20,0xee,0xf3] +wur.qacc_h_3 a12 +# CHECK: wur a12, qacc # encoding: [0xc0,0xee,0xf3] +wur.qacc_h_4 a14 +# CHECK: wur a14, qacc # encoding: [0xe0,0xee,0xf3] +wur.qacc_l_0 a6 +# CHECK: wur a6, qacc # encoding: [0x60,0xee,0xf3] +wur.qacc_l_1 a5 +# CHECK: wur a5, qacc # encoding: [0x50,0xee,0xf3] +wur.qacc_l_2 a6 +# CHECK: wur a6, qacc # encoding: [0x60,0xee,0xf3] +wur.qacc_l_3 a6 +# CHECK: wur a6, qacc # encoding: [0x60,0xee,0xf3] +wur.qacc_l_4 a7 +# CHECK: wur a7, qacc # encoding: [0x70,0xee,0xf3] +wur.sar_byte a9 +# CHECK: wur a9, sar_byte # encoding: [0x90,0xf0,0xf3] +wur.ua_state_0 a8 +# CHECK: wur a8, ua_state # encoding: [0x80,0xf1,0xf3] +wur.ua_state_1 a14 +# CHECK: wur a14, ua_state # encoding: [0xe0,0xf1,0xf3] +wur.ua_state_2 a9 +# CHECK: wur a9, ua_state # encoding: [0x90,0xf1,0xf3] +wur.ua_state_3 a10 +# CHECK: wur a10, ua_state # encoding: [0xa0,0xf1,0xf3] +mv.qr q4, q7 +# CHECK: mv.qr q4, q7 # encoding: [0x24,0x0c,0xaf] From ab418bf58e500d1c63326eae789f5928a376c4d9 Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Tue, 8 Aug 2023 19:29:45 +0200 Subject: [PATCH 164/261] [Xtensa][esp32s3] Fix encoding for immediates with step increment --- .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 14 +-- llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s | 90 +++++++++---------- 2 files changed, 52 insertions(+), 52 deletions(-) diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 1e960cdce26fde..02d4d91bf1af74 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -711,7 +711,7 @@ XtensaMCCodeEmitter::getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo, assert(((Res >= -128) && (Res <= 112) && ((Res & 0xf) == 0)) && "Unexpected operand value!"); - return Res; + return Res / 16; } int16_t @@ -724,7 +724,7 @@ XtensaMCCodeEmitter::getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo, assert(((Res >= -1024) && (Res <= 1016) && ((Res & 0x7) == 0)) && "Unexpected operand value!"); - return Res; + return Res / 8; } int16_t @@ -736,8 +736,8 @@ XtensaMCCodeEmitter::getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo, assert(((Res >= -2048) && (Res <= 2032) && ((Res & 0xf) == 0)) && "Unexpected operand value!"); - - return Res; + + return Res / 16; } int16_t @@ -750,7 +750,7 @@ XtensaMCCodeEmitter::getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo, assert(((Res >= -512) && (Res <= 508) && ((Res & 0x3) == 0)) && "Unexpected operand value!"); - return Res; + return Res / 4; } uint8_t @@ -763,7 +763,7 @@ XtensaMCCodeEmitter::getOffset_128_2OpValue(const MCInst &MI, unsigned OpNo, assert(((Res >= 0) && (Res <= 254) && ((Res & 0x1) == 0)) && "Unexpected operand value!"); - return Res; + return Res / 2; } uint8_t @@ -788,7 +788,7 @@ XtensaMCCodeEmitter::getOffset_64_16OpValue(const MCInst &MI, unsigned OpNo, assert(((Res >= -512) && (Res <= 496) && ((Res & 0xf) == 0)) && "Unexpected operand value!"); - return Res; + return Res / 16; } #include "XtensaGenMCCodeEmitter.inc" diff --git a/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s b/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s index ee37f4bca7b1b5..c5ed22386ec0cc 100644 --- a/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s +++ b/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s @@ -49,47 +49,47 @@ ee.fft.r2bf.s16.st.incp q7, q3, q7, a2, 2 ee.fft.vst.r32.decp q3, a14, 0 # CHECK: ee.fft.vst.r32.decp q3, a14, 0 # encoding: [0xe4,0xb3,0xdd] ee.ldf.128.ip f3, f5, f8, f0, a13, 64 -# CHECK: ee.ldf.128.ip f3, f5, f8, f0, a13, 64 # encoding: [0x0d,0x80,0x35,0x10] +# CHECK: ee.ldf.128.ip f3, f5, f8, f0, a13, 64 # encoding: [0x4d,0x80,0x35,0x10] ee.ldf.128.xp f5, f2, f4, f4, a7, a8 # CHECK: ee.ldf.128.xp f5, f2, f4, f4, a7, a8 # encoding: [0x87,0x44,0x52,0x11] ee.ldf.64.ip f6, f5, a1, 488 -# CHECK: ee.ldf.64.ip f6, f5, a1, 488 # encoding: [0x41,0x65,0x74,0x1c] +# CHECK: ee.ldf.64.ip f6, f5, a1, 488 # encoding: [0x51,0x65,0x1e,0x1c] ee.ldf.64.xp f0, f6, a3, a8 # CHECK: ee.ldf.64.xp f0, f6, a3, a8 # encoding: [0x30,0x08,0x66] ee.ldqa.s16.128.ip a11, 1904 -# CHECK: ee.ldqa.s16.128.ip a11, 1904 # encoding: [0xb4,0x70,0x01] +# CHECK: ee.ldqa.s16.128.ip a11, 1904 # encoding: [0xb4,0x77,0x01] ee.ldqa.s16.128.xp a6, a2 # CHECK: ee.ldqa.s16.128.xp a6, a2 # encoding: [0x64,0x42,0x7e] ee.ldqa.s8.128.ip a8, 320 -# CHECK: ee.ldqa.s8.128.ip a8, 320 # encoding: [0x84,0x40,0x11] +# CHECK: ee.ldqa.s8.128.ip a8, 320 # encoding: [0x84,0x14,0x11] ee.ldqa.s8.128.xp a6, a11 # CHECK: ee.ldqa.s8.128.xp a6, a11 # encoding: [0x64,0x4b,0x71] ee.ldqa.u16.128.ip a2, -1424 -# CHECK: ee.ldqa.u16.128.ip a2, -1424 # encoding: [0x24,0x70,0x05] +# CHECK: ee.ldqa.u16.128.ip a2, -1424 # encoding: [0x24,0x27,0x45] ee.ldqa.u16.128.xp a3, a4 # CHECK: ee.ldqa.u16.128.xp a3, a4 # encoding: [0x34,0x44,0x7a] ee.ldqa.u8.128.ip a4, 784 -# CHECK: ee.ldqa.u8.128.ip a4, 784 # encoding: [0x44,0x10,0x15] +# CHECK: ee.ldqa.u8.128.ip a4, 784 # encoding: [0x44,0x31,0x15] ee.ldqa.u8.128.xp a4, a9 # CHECK: ee.ldqa.u8.128.xp a4, a9 # encoding: [0x44,0x49,0x70] ee.ldxq.32 q2, q6, a11, 2, 1 # CHECK: ee.ldxq.32 q2, q6, a11, 2, 1 # encoding: [0xdb,0x8f,0x25,0x1c] ee.ld.128.usar.ip q4, a8, -592 -# CHECK: ee.ld.128.usar.ip q4, a8, -592 # encoding: [0x84,0x30,0xe1] +# CHECK: ee.ld.128.usar.ip q4, a8, -592 # encoding: [0x84,0x5b,0xe1] ee.ld.128.usar.xp q1, a9, a7 # CHECK: ee.ld.128.usar.xp q1, a9, a7 # encoding: [0x94,0x87,0x8d] ee.ld.accx.ip a2, 720 -# CHECK: ee.ld.accx.ip a2, 720 # encoding: [0x24,0x50,0x4e] +# CHECK: ee.ld.accx.ip a2, 720 # encoding: [0x24,0x5a,0x0e] ee.ld.qacc_h.h.32.ip a6, -292 -# CHECK: ee.ld.qacc_h.h.32.ip a6, -292 # encoding: [0x64,0x5c,0x5e] +# CHECK: ee.ld.qacc_h.h.32.ip a6, -292 # encoding: [0x64,0x37,0x5e] ee.ld.qacc_h.l.128.ip a14, 96 -# CHECK: ee.ld.qacc_h.l.128.ip a14, 96 # encoding: [0xe4,0x60,0x06] +# CHECK: ee.ld.qacc_h.l.128.ip a14, 96 # encoding: [0xe4,0x06,0x06] ee.ld.qacc_l.h.32.ip a0, -184 -# CHECK: ee.ld.qacc_l.h.32.ip a0, -184 # encoding: [0x04,0x48,0x16] +# CHECK: ee.ld.qacc_l.h.32.ip a0, -184 # encoding: [0x04,0x52,0x56] ee.ld.qacc_l.l.128.ip a5, -352 -# CHECK: ee.ld.qacc_l.l.128.ip a5, -352 # encoding: [0x54,0x20,0x40] +# CHECK: ee.ld.qacc_l.l.128.ip a5, -352 # encoding: [0x54,0x6a,0x40] ee.ld.ua_state.ip a3, 864 -# CHECK: ee.ld.ua_state.ip a3, 864 # encoding: [0x34,0x60,0x10] +# CHECK: ee.ld.ua_state.ip a3, 864 # encoding: [0x34,0x36,0x10] ee.movi.32.a q7, a0, 1 # CHECK: ee.movi.32.a q7, a0, 1 # encoding: [0x04,0xf5,0xfd] ee.movi.32.q q5, a5, 3 @@ -123,7 +123,7 @@ ee.srcxxp.2q q6, q0, a2, a14 ee.src.q q6, q7, q5 # CHECK: ee.src.q q6, q7, q5 # encoding: [0x64,0xf3,0xec] ee.src.q.ld.ip q2, a2, 1792, q6, q7 -# CHECK: ee.src.q.ld.ip q2, a2, 1792, q6, q7 # encoding: [0x02,0x87,0x05,0x1c] +# CHECK: ee.src.q.ld.ip q2, a2, 1792, q6, q7 # encoding: [0x02,0xa7,0x35,0x1c] ee.src.q.ld.xp q2, a4, a9, q1, q7 # CHECK: ee.src.q.ld.xp q2, a4, a9, q1, q7 # encoding: [0x94,0x47,0x04,0x1d] ee.src.q.qup q4, q3, q7 @@ -131,27 +131,27 @@ ee.src.q.qup q4, q3, q7 ee.srs.accx a12, a1, 0 # CHECK: ee.srs.accx a12, a1, 0 # encoding: [0x14,0x1c,0x7e] ee.stf.128.ip f4, f3, f8, f2, a4, -128 -# CHECK: ee.stf.128.ip f4, f3, f8, f2, a4, -128 # encoding: [0x04,0x82,0x43,0x12] +# CHECK: ee.stf.128.ip f4, f3, f8, f2, a4, -128 # encoding: [0x84,0x82,0x43,0x12] ee.stf.128.xp f2, f0, f5, f8, a11, a5 # CHECK: ee.stf.128.xp f2, f0, f5, f8, a11, a5 # encoding: [0x5b,0x58,0x20,0x13] ee.stf.64.ip f3, f6, a10, -848 -# CHECK: ee.stf.64.ip f3, f6, a10, -848 # encoding: [0x6a,0x36,0x58,0x1c] +# CHECK: ee.stf.64.ip f3, f6, a10, -848 # encoding: [0x6a,0x36,0x4b,0x1c] ee.stf.64.xp f2, f1, a1, a14 # CHECK: ee.stf.64.xp f2, f1, a1, a14 # encoding: [0x10,0x2e,0x17] ee.stxq.32 q5, q2, a5, 0, 1 # CHECK: ee.stxq.32 q5, q2, a5, 0, 1 # encoding: [0x05,0x8d,0xc0,0x1c] ee.st.accx.ip a10, 24 -# CHECK: ee.st.accx.ip a10, 24 # encoding: [0xa4,0x18,0x02] +# CHECK: ee.st.accx.ip a10, 24 # encoding: [0xa4,0x03,0x02] ee.st.qacc_h.h.32.ip a14, 380 -# CHECK: ee.st.qacc_h.h.32.ip a14, 380 # encoding: [0xe4,0x7c,0x12] +# CHECK: ee.st.qacc_h.h.32.ip a14, 380 # encoding: [0xe4,0x5f,0x12] ee.st.qacc_h.l.128.ip a7, -624 -# CHECK: ee.st.qacc_h.l.128.ip a7, -624 # encoding: [0x74,0x10,0x4d] +# CHECK: ee.st.qacc_h.l.128.ip a7, -624 # encoding: [0x74,0x59,0x4d] ee.st.qacc_l.h.32.ip a10, -20 -# CHECK: ee.st.qacc_l.h.32.ip a10, -20 # encoding: [0xa4,0x6c,0x5d] +# CHECK: ee.st.qacc_l.h.32.ip a10, -20 # encoding: [0xa4,0x7b,0x5d] ee.st.qacc_l.l.128.ip a4, 1936 -# CHECK: ee.st.qacc_l.l.128.ip a4, 1936 # encoding: [0x44,0x10,0x4c] +# CHECK: ee.st.qacc_l.l.128.ip a4, 1936 # encoding: [0x44,0x79,0x0c] ee.st.ua_state.ip a4, -1728 -# CHECK: ee.st.ua_state.ip a4, -1728 # encoding: [0x44,0x40,0x1c] +# CHECK: ee.st.ua_state.ip a4, -1728 # encoding: [0x44,0x14,0x5c] ee.vadds.s16 q5, q1, q4 # CHECK: ee.vadds.s16 q5, q1, q4 # encoding: [0x64,0xc1,0xae] ee.vadds.s16.ld.incp q6, a6, q1, q3, q1 @@ -191,13 +191,13 @@ ee.vcmp.lt.s8 q7, q1, q6 ee.vldbc.16 q6, a11 # CHECK: ee.vldbc.16 q6, a11 # encoding: [0xb4,0x73,0xfd] ee.vldbc.16.ip q6, a4, 124 -# CHECK: ee.vldbc.16.ip q6, a4, 124 # encoding: [0x44,0x7c,0xb5] +# CHECK: ee.vldbc.16.ip q6, a4, 124 # encoding: [0x44,0x3e,0xb5] ee.vldbc.16.xp q2, a0, a7 # CHECK: ee.vldbc.16.xp q2, a0, a7 # encoding: [0x04,0x47,0x9d] ee.vldbc.32 q4, a0 # CHECK: ee.vldbc.32 q4, a0 # encoding: [0x04,0x77,0xed] ee.vldbc.32.ip q6, a12, 308 -# CHECK: ee.vldbc.32.ip q6, a12, 308 # encoding: [0xc4,0x34,0xb2] +# CHECK: ee.vldbc.32.ip q6, a12, 308 # encoding: [0xc4,0x4d,0xb2] ee.vldbc.32.xp q1, a11, a0 # CHECK: ee.vldbc.32.xp q1, a11, a0 # encoding: [0xb4,0x90,0x8d] ee.vldbc.8 q2, a3 @@ -209,15 +209,15 @@ ee.vldbc.8.xp q2, a0, a13 ee.vldhbc.16.incp q5, q5, a14 # CHECK: ee.vldhbc.16.incp q5, q5, a14 # encoding: [0xe4,0xd2,0xec] ee.vld.128.ip q3, a14, 1248 -# CHECK: ee.vld.128.ip q3, a14, 1248 # encoding: [0xe4,0xe0,0xd3] +# CHECK: ee.vld.128.ip q3, a14, 1248 # encoding: [0xe4,0xce,0x93] ee.vld.128.xp q5, a10, a12 # CHECK: ee.vld.128.xp q5, a10, a12 # encoding: [0xa4,0xac,0xad] ee.vld.h.64.ip q4, a14, 240 -# CHECK: ee.vld.h.64.ip q4, a14, 240 # encoding: [0xe4,0x70,0xe8] +# CHECK: ee.vld.h.64.ip q4, a14, 240 # encoding: [0xe4,0x1e,0xa8] ee.vld.h.64.xp q7, a4, a8 # CHECK: ee.vld.h.64.xp q7, a4, a8 # encoding: [0x44,0xe8,0xbd] ee.vld.l.64.ip q1, a8, 8 -# CHECK: ee.vld.l.64.ip q1, a8, 8 # encoding: [0x84,0x88,0x89] +# CHECK: ee.vld.l.64.ip q1, a8, 8 # encoding: [0x84,0x81,0x89] ee.vld.l.64.xp q1, a2, a9 # CHECK: ee.vld.l.64.xp q1, a2, a9 # encoding: [0x24,0xb9,0x8d] ee.vmax.s16 q2, q5, q6 @@ -259,9 +259,9 @@ ee.vmin.s8.st.incp q2, a4, q4, q7, q1 ee.vmulas.s16.accx q0, q7 # CHECK: ee.vmulas.s16.accx q0, q7 # encoding: [0x84,0x58,0x1a] ee.vmulas.s16.accx.ld.ip q7, a7, -16, q2, q0 -# CHECK: ee.vmulas.s16.accx.ld.ip q7, a7, -16, q2, q0 # encoding: [0x07,0x80,0xf0,0x1f] +# CHECK: ee.vmulas.s16.accx.ld.ip q7, a7, -16, q2, q0 # encoding: [0xf7,0x80,0xf0,0x1f] ee.vmulas.s16.accx.ld.ip.qup q5, a14, 32, q0, q2, q0, q2 -# CHECK: ee.vmulas.s16.accx.ld.ip.qup q5, a14, 32, q0, q2, q0, q2 # encoding: [0x0e,0x10,0x54,0x01] +# CHECK: ee.vmulas.s16.accx.ld.ip.qup q5, a14, 32, q0, q2, q0, q2 # encoding: [0x2e,0x10,0x54,0x00] ee.vmulas.s16.accx.ld.xp q1, a0, a1, q2, q6 # CHECK: ee.vmulas.s16.accx.ld.xp q1, a0, a1, q2, q6 # encoding: [0x10,0xb1,0x10,0x1e] ee.vmulas.s16.accx.ld.xp.qup q4, a8, a10, q4, q0, q0, q3 @@ -273,9 +273,9 @@ ee.vmulas.s16.qacc.ldbc.incp q2, a6, q3, q4 ee.vmulas.s16.qacc.ldbc.incp.qup q0, a4, q1, q6, q4, q5 # CHECK: ee.vmulas.s16.qacc.ldbc.incp.qup q0, a4, q1, q6, q4, q5 # encoding: [0x84,0x74,0x0a,0x1c] ee.vmulas.s16.qacc.ld.ip q7, a7, -64, q7, q7 -# CHECK: ee.vmulas.s16.qacc.ld.ip q7, a7, -64, q7, q7 # encoding: [0x07,0xf8,0x73,0x1e] +# CHECK: ee.vmulas.s16.qacc.ld.ip q7, a7, -64, q7, q7 # encoding: [0xc7,0xf8,0xf3,0x1f] ee.vmulas.s16.qacc.ld.ip.qup q0, a10, 48, q3, q6, q3, q6 -# CHECK: ee.vmulas.s16.qacc.ld.ip.qup q0, a10, 48, q3, q6, q3, q6 # encoding: [0x0a,0xf3,0x8c,0x03] +# CHECK: ee.vmulas.s16.qacc.ld.ip.qup q0, a10, 48, q3, q6, q3, q6 # encoding: [0x3a,0xf3,0x0c,0x02] ee.vmulas.s16.qacc.ld.xp q3, a11, a4, q4, q5 # CHECK: ee.vmulas.s16.qacc.ld.xp q3, a11, a4, q4, q5 # encoding: [0x4b,0x29,0x33,0x1e] ee.vmulas.s16.qacc.ld.xp.qup q2, a9, a1, q3, q2, q1, q7 @@ -283,9 +283,9 @@ ee.vmulas.s16.qacc.ld.xp.qup q2, a9, a1, q3, q2, q1, q7 ee.vmulas.s8.accx q1, q0 # CHECK: ee.vmulas.s8.accx q1, q0 # encoding: [0xc4,0x01,0x1a] ee.vmulas.s8.accx.ld.ip q2, a8, 80, q3, q0 -# CHECK: ee.vmulas.s8.accx.ld.ip q2, a8, 80, q3, q0 # encoding: [0x08,0xc0,0xa4,0x1e] +# CHECK: ee.vmulas.s8.accx.ld.ip q2, a8, 80, q3, q0 # encoding: [0x58,0xc0,0x24,0x1e] ee.vmulas.s8.accx.ld.ip.qup q2, a9, -80, q1, q2, q6, q3 -# CHECK: ee.vmulas.s8.accx.ld.ip.qup q2, a9, -80, q1, q2, q6, q3 # encoding: [0x09,0x56,0xa6,0x05] +# CHECK: ee.vmulas.s8.accx.ld.ip.qup q2, a9, -80, q1, q2, q6, q3 # encoding: [0xb9,0x56,0xa6,0x05] ee.vmulas.s8.accx.ld.xp q3, a3, a4, q4, q7 # CHECK: ee.vmulas.s8.accx.ld.xp q3, a3, a4, q4, q7 # encoding: [0x43,0x39,0x35,0x1e] ee.vmulas.s8.accx.ld.xp.qup q0, a3, a1, q4, q5, q3, q3 @@ -297,9 +297,9 @@ ee.vmulas.s8.qacc.ldbc.incp q7, a1, q6, q1 ee.vmulas.s8.qacc.ldbc.incp.qup q3, a11, q4, q6, q5, q6 # CHECK: ee.vmulas.s8.qacc.ldbc.incp.qup q3, a11, q4, q6, q5, q6 # encoding: [0x9b,0x35,0x3d,0x1c] ee.vmulas.s8.qacc.ld.ip q5, a10, -16, q0, q0 -# CHECK: ee.vmulas.s8.qacc.ld.ip q5, a10, -16, q0, q0 # encoding: [0x0a,0x00,0xd6,0x1f] +# CHECK: ee.vmulas.s8.qacc.ld.ip q5, a10, -16, q0, q0 # encoding: [0xfa,0x00,0xd6,0x1f] ee.vmulas.s8.qacc.ld.ip.qup q7, a9, -48, q6, q2, q1, q2 -# CHECK: ee.vmulas.s8.qacc.ld.ip.qup q7, a9, -48, q6, q2, q1, q2 # encoding: [0x09,0x91,0xf5,0x06] +# CHECK: ee.vmulas.s8.qacc.ld.ip.qup q7, a9, -48, q6, q2, q1, q2 # encoding: [0xd9,0x91,0xf5,0x07] ee.vmulas.s8.qacc.ld.xp q1, a1, a12, q5, q0 # CHECK: ee.vmulas.s8.qacc.ld.xp q1, a1, a12, q5, q0 # encoding: [0xc1,0x41,0x17,0x1e] ee.vmulas.s8.qacc.ld.xp.qup q0, a1, a14, q1, q6, q2, q4 @@ -307,9 +307,9 @@ ee.vmulas.s8.qacc.ld.xp.qup q0, a1, a14, q1, q6, q2, q4 ee.vmulas.u16.accx q7, q1 # CHECK: ee.vmulas.u16.accx q7, q1 # encoding: [0x84,0x0f,0x0a] ee.vmulas.u16.accx.ld.ip q5, a8, -32, q1, q4 -# CHECK: ee.vmulas.u16.accx.ld.ip q5, a8, -32, q1, q4 # encoding: [0x08,0x60,0x58,0x1f] +# CHECK: ee.vmulas.u16.accx.ld.ip q5, a8, -32, q1, q4 # encoding: [0xe8,0x60,0xd8,0x1f] ee.vmulas.u16.accx.ld.ip.qup q1, a0, 48, q7, q4, q4, q0 -# CHECK: ee.vmulas.u16.accx.ld.ip.qup q1, a0, 48, q7, q4, q4, q0 # encoding: [0x00,0xe4,0x91,0x09] +# CHECK: ee.vmulas.u16.accx.ld.ip.qup q1, a0, 48, q7, q4, q4, q0 # encoding: [0x30,0xe4,0x11,0x08] ee.vmulas.u16.accx.ld.xp q3, a14, a4, q5, q4 # CHECK: ee.vmulas.u16.accx.ld.xp q3, a14, a4, q5, q4 # encoding: [0x4e,0x61,0x39,0x1e] ee.vmulas.u16.accx.ld.xp.qup q4, a3, a7, q6, q2, q4, q4 @@ -321,7 +321,7 @@ ee.vmulas.u16.qacc.ldbc.incp q6, a7, q0, q3 ee.vmulas.u16.qacc.ldbc.incp.qup q0, a12, q6, q3, q2, q0 # CHECK: ee.vmulas.u16.qacc.ldbc.incp.qup q0, a12, q6, q3, q2, q0 # encoding: [0xac,0x9a,0x01,0x1c] ee.vmulas.u16.qacc.ld.ip q4, a10, 16, q3, q2 -# CHECK: ee.vmulas.u16.qacc.ld.ip q4, a10, 16, q3, q2 # encoding: [0x0a,0xd0,0xca,0x1e] +# CHECK: ee.vmulas.u16.qacc.ld.ip q4, a10, 16, q3, q2 # encoding: [0x1a,0xd0,0x4a,0x1e] ee.vmulas.u16.qacc.ld.ip.qup q2, a4, 0, q5, q4, q2, q6 # CHECK: ee.vmulas.u16.qacc.ld.ip.qup q2, a4, 0, q5, q4, q2, q6 # encoding: [0x04,0x62,0x2d,0x0a] ee.vmulas.u16.qacc.ld.xp q6, a14, a2, q4, q0 @@ -331,9 +331,9 @@ ee.vmulas.u16.qacc.ld.xp.qup q6, a12, a11, q6, q7, q4, q1 ee.vmulas.u8.accx q2, q1 # CHECK: ee.vmulas.u8.accx q2, q1 # encoding: [0xc4,0x0a,0x0a] ee.vmulas.u8.accx.ld.ip q6, a3, -112, q2, q7 -# CHECK: ee.vmulas.u8.accx.ld.ip q6, a3, -112, q2, q7 # encoding: [0x03,0xb8,0xec,0x1e] +# CHECK: ee.vmulas.u8.accx.ld.ip q6, a3, -112, q2, q7 # encoding: [0x93,0xb8,0xec,0x1f] ee.vmulas.u8.accx.ld.ip.qup q7, a3, -32, q3, q3, q7, q5 -# CHECK: ee.vmulas.u8.accx.ld.ip.qup q7, a3, -32, q3, q3, q7, q5 # encoding: [0x03,0xdf,0x7a,0x0d] +# CHECK: ee.vmulas.u8.accx.ld.ip.qup q7, a3, -32, q3, q3, q7, q5 # encoding: [0xe3,0xdf,0xfa,0x0d] ee.vmulas.u8.accx.ld.xp q4, a4, a9, q4, q0 # CHECK: ee.vmulas.u8.accx.ld.xp q4, a4, a9, q4, q0 # encoding: [0x94,0x01,0x4d,0x1e] ee.vmulas.u8.accx.ld.xp.qup q5, a7, a13, q4, q7, q2, q6 @@ -345,9 +345,9 @@ ee.vmulas.u8.qacc.ldbc.incp q4, a1, q0, q5 ee.vmulas.u8.qacc.ldbc.incp.qup q2, a1, q5, q7, q6, q4 # CHECK: ee.vmulas.u8.qacc.ldbc.incp.qup q2, a1, q5, q7, q6, q4 # encoding: [0xb1,0x7e,0x29,0x1c] ee.vmulas.u8.qacc.ld.ip q2, a12, 32, q1, q4 -# CHECK: ee.vmulas.u8.qacc.ld.ip q2, a12, 32, q1, q4 # encoding: [0x0c,0x60,0x2e,0x1f] +# CHECK: ee.vmulas.u8.qacc.ld.ip q2, a12, 32, q1, q4 # encoding: [0x2c,0x60,0x2e,0x1e] ee.vmulas.u8.qacc.ld.ip.qup q0, a6, 48, q0, q0, q6, q0 -# CHECK: ee.vmulas.u8.qacc.ld.ip.qup q0, a6, 48, q0, q0, q6, q0 # encoding: [0x06,0x06,0x80,0x0f] +# CHECK: ee.vmulas.u8.qacc.ld.ip.qup q0, a6, 48, q0, q0, q6, q0 # encoding: [0x36,0x06,0x00,0x0e] ee.vmulas.u8.qacc.ld.xp q6, a1, a1, q2, q5 # CHECK: ee.vmulas.u8.qacc.ld.xp q6, a1, a1, q2, q5 # encoding: [0x11,0xa9,0x6e,0x1e] ee.vmulas.u8.qacc.ld.xp.qup q1, a8, a10, q3, q7, q1, q3 @@ -397,15 +397,15 @@ ee.vsmulas.s8.qacc.ld.incp q1, a8, q1, q1, 4 ee.vsr.32 q4, q3 # CHECK: ee.vsr.32 q4, q3 # encoding: [0xc4,0xbf,0xdd] ee.vst.128.ip q3, a6, -816 -# CHECK: ee.vst.128.ip q3, a6, -816 # encoding: [0x64,0xd0,0xda] +# CHECK: ee.vst.128.ip q3, a6, -816 # encoding: [0x64,0xcd,0xda] ee.vst.128.xp q6, a12, a14 # CHECK: ee.vst.128.xp q6, a12, a14 # encoding: [0xc4,0x7e,0xbd] ee.vst.h.64.ip q2, a5, 40 -# CHECK: ee.vst.h.64.ip q2, a5, 40 # encoding: [0x54,0x28,0x9b] +# CHECK: ee.vst.h.64.ip q2, a5, 40 # encoding: [0x54,0x05,0x9b] ee.vst.h.64.xp q2, a13, a6 # CHECK: ee.vst.h.64.xp q2, a13, a6 # encoding: [0xd4,0x06,0xdd] ee.vst.l.64.ip q5, a8, 16 -# CHECK: ee.vst.l.64.ip q5, a8, 16 # encoding: [0x84,0x90,0xa4] +# CHECK: ee.vst.l.64.ip q5, a8, 16 # encoding: [0x84,0x82,0xa4] ee.vst.l.64.xp q0, a13, a6 # CHECK: ee.vst.l.64.xp q0, a13, a6 # encoding: [0xd4,0x46,0xcd] ee.vsubs.s16 q5, q1, q4 From 41d18a5662dd2e3ccefea3e6c5e75b5d42fb253b Mon Sep 17 00:00:00 2001 From: Ronen Ulanovsky Date: Thu, 13 Jul 2023 19:57:30 +0300 Subject: [PATCH 165/261] [Xtensa] Fix FP mul-sub fusion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit `performMADD_MSUBCombine` treats `x * y ± z` and `z ± x * y` interchangeably which is wrong for `msub.s` which expects the latter. Added a check to determine that the orientation is correct, and if not, negate the result. --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 27 +++++++++++-------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 54edf6c5fa3b6b..e0ee38f10eb0f0 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -518,32 +518,37 @@ void XtensaTargetLowering::LowerAsmOperandForConstraint( static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, const XtensaSubtarget &Subtarget) { - if (ROOTNode->getOperand(0).getValueType() != MVT::f32) - return SDValue(); + SDValue LHS = ROOTNode->getOperand(0); + SDValue RHS = ROOTNode->getOperand(1); - if (ROOTNode->getOperand(0).getOpcode() != ISD::FMUL && - ROOTNode->getOperand(1).getOpcode() != ISD::FMUL) + if (LHS.getValueType() != MVT::f32) return SDValue(); - SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::FMUL - ? ROOTNode->getOperand(0) - : ROOTNode->getOperand(1); + bool IsAdd = ROOTNode->getOpcode() == ISD::FADD; + + SDValue Mult = LHS, AddOperand = RHS; + bool NegRes = !IsAdd; - SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::FMUL - ? ROOTNode->getOperand(1) - : ROOTNode->getOperand(0); + if (LHS.getOpcode() != ISD::FMUL && RHS.getOpcode() != ISD::FMUL) + return SDValue(); + else if (RHS.getOpcode() == ISD::FMUL) { + Mult = RHS; + AddOperand = LHS; + NegRes = false; + } if (!Mult.hasOneUse()) return SDValue(); SDLoc DL(ROOTNode); - bool IsAdd = ROOTNode->getOpcode() == ISD::FADD; unsigned Opcode = IsAdd ? XtensaISD::MADD : XtensaISD::MSUB; SDValue MAddOps[3] = {AddOperand, Mult->getOperand(0), Mult->getOperand(1)}; EVT VTs[3] = {MVT::f32, MVT::f32, MVT::f32}; SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); + if (NegRes) + return CurDAG.getNode(ISD::FNEG, DL, MVT::f32, MAdd); return MAdd; } From 370da796530c4ca9cccbbf0353ff49202babca0e Mon Sep 17 00:00:00 2001 From: Ronen Ulanovsky Date: Sun, 16 Jul 2023 01:22:50 +0300 Subject: [PATCH 166/261] [Xtensa] Add more valid FMA patterns and tests 1. Prefer `fneg.s` to `l32r ar, 0x80000000; xor ar, as, ar` when `wfr/rfr` are used anyway 2. Add Patterns for fma/madd/msub to automatically generate msub when it's the better choice 3. XtensaISelLowering.cpp: Rely on LLVM to lower FMA to madd.s/msub.s instead of hardcoding 4. Add float-fma.ll with various fused multiply add/subtract permutations --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 49 ++++-- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 2 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 9 +- llvm/test/CodeGen/Xtensa/float-fma.ll | 146 ++++++++++++++++++ 4 files changed, 187 insertions(+), 19 deletions(-) create mode 100644 llvm/test/CodeGen/Xtensa/float-fma.ll diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index e0ee38f10eb0f0..b2fd26b44ea2dd 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -381,6 +381,20 @@ MVT XtensaTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); } +bool XtensaTargetLowering::isFNegFree(EVT VT) const { + if (!VT.isSimple()) + return false; + + switch (VT.getSimpleVT().SimpleTy) { + case MVT::f32: + return Subtarget.hasSingleFloat(); + default: + break; + } + + return false; +} + bool XtensaTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const { if (!VT.isSimple()) @@ -521,35 +535,36 @@ static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, SDValue LHS = ROOTNode->getOperand(0); SDValue RHS = ROOTNode->getOperand(1); - if (LHS.getValueType() != MVT::f32) + if (LHS.getValueType() != MVT::f32 || (LHS.getOpcode() != ISD::FMUL && RHS.getOpcode() != ISD::FMUL)) return SDValue(); + SDLoc DL(ROOTNode); bool IsAdd = ROOTNode->getOpcode() == ISD::FADD; - SDValue Mult = LHS, AddOperand = RHS; - bool NegRes = !IsAdd; + SDValue Mult, AddOperand; + bool Inverted; - if (LHS.getOpcode() != ISD::FMUL && RHS.getOpcode() != ISD::FMUL) - return SDValue(); - else if (RHS.getOpcode() == ISD::FMUL) { - Mult = RHS; - AddOperand = LHS; - NegRes = false; - } + if (LHS.getOpcode() == ISD::FMUL) + Mult = LHS, AddOperand = RHS, Inverted = false; + else + Mult = RHS, AddOperand = LHS, Inverted = true; if (!Mult.hasOneUse()) return SDValue(); - SDLoc DL(ROOTNode); + SDValue MultOperand0 = Mult->getOperand(0), MultOperand1 = Mult->getOperand(1); + + if (!IsAdd) { + if (Inverted) + MultOperand0 = CurDAG.getNode(ISD::FNEG, DL, MVT::f32, MultOperand0); + else + AddOperand = CurDAG.getNode(ISD::FNEG, DL, MVT::f32, AddOperand); + } - unsigned Opcode = IsAdd ? XtensaISD::MADD : XtensaISD::MSUB; - SDValue MAddOps[3] = {AddOperand, Mult->getOperand(0), Mult->getOperand(1)}; + SDValue FMAOps[3] = {MultOperand0, MultOperand1, AddOperand}; EVT VTs[3] = {MVT::f32, MVT::f32, MVT::f32}; - SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); - if (NegRes) - return CurDAG.getNode(ISD::FNEG, DL, MVT::f32, MAdd); - return MAdd; + return CurDAG.getNode(ISD::FMA, DL, VTs, FMAOps); } static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 965e32f2675642..455ff0ad29f71b 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -120,6 +120,8 @@ class XtensaTargetLowering : public TargetLowering { bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override; + bool isFNegFree(EVT VT) const override; + /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. Register diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 5f92e869f68eaf..c5e6d760e0c965 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1112,15 +1112,16 @@ def FLOOR_S : RRR_Inst<0x00, 0x0A, 0x0A, (outs AR:$r), (ins FPR:$s, uimm4:$imm), let t = imm; } -def MADDN_S : RRR_Inst<0x00, 0x0A, 0x06, (outs FPR:$r), (ins FPR:$s, FPR:$t), +def MADDN_S : RRR_Inst<0x00, 0x0A, 0x06, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), "maddn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]> { let isCommutable = 0; + let Constraints = "$r = $a"; } // FP multipy-add def MADD_S : RRR_Inst<0x00, 0x0A, 0x04, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), "madd.s\t$r, $s, $t", - [(set FPR:$r, (Xtensa_madd FPR:$a, FPR:$s, FPR:$t))]>, + [(set FPR:$r, (Xtensa_madd FPR:$a, FPR:$s, FPR:$t))]>, Requires<[HasSingleFloat]> { let isCommutable = 0; let isReMaterializable = 0; @@ -1175,6 +1176,10 @@ def MSUB_S : RRR_Inst<0x00, 0x0A, 0x05, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR: let Constraints = "$r = $a"; } +// fmsub: -r1 * r2 + r3 +def : Pat<(fma (fneg FPR:$r1), FPR:$r2, FPR:$r3), + (MSUB_S $r3, $r1, $r2)>; + def NEXP01_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "nexp01.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0B; diff --git a/llvm/test/CodeGen/Xtensa/float-fma.ll b/llvm/test/CodeGen/Xtensa/float-fma.ll new file mode 100644 index 00000000000000..484b2705a18c68 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/float-fma.ll @@ -0,0 +1,146 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=XTENSA %s + +define float @fmadd_s(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fmadd_s: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: madd.s f10, f9, f8 +; XTENSA-NEXT: rfr a2, f10 +; XTENSA-NEXT: retw.n + %mul = fmul float %a, %b + %add = fadd float %mul, %c + ret float %add +} + +define float @fmsub_s(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fmsub_s: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: neg.s f10, f10 +; XTENSA-NEXT: madd.s f10, f9, f8 +; XTENSA-NEXT: rfr a2, f10 +; XTENSA-NEXT: retw.n + %mul = fmul float %a, %b + %sub = fsub float %mul, %c + ret float %sub +} + +define float @fnmadd_s(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fnmadd_s: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: madd.s f10, f9, f8 +; XTENSA-NEXT: neg.s f8, f10 +; XTENSA-NEXT: rfr a2, f8 +; XTENSA-NEXT: retw.n + %mul = fmul float %a, %b + %add = fadd float %mul, %c + %negadd = fneg float %add + ret float %negadd +} + + +define float @fnmsub_s(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fnmsub_s: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: msub.s f10, f9, f8 +; XTENSA-NEXT: rfr a2, f10 +; XTENSA-NEXT: retw.n + %nega = fneg float %a + %mul = fmul float %nega, %b + %add = fadd float %mul, %c + ret float %add +} + +declare float @llvm.fma.f32(float, float, float) + +define float @fmadd_s_intrinsics(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fmadd_s_intrinsics: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: madd.s f10, f9, f8 +; XTENSA-NEXT: rfr a2, f10 +; XTENSA-NEXT: retw.n + %fma = call float @llvm.fma.f32(float %a, float %b, float %c) + ret float %fma +} + +define float @fmsub_s_intrinsics(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fmsub_s_intrinsics: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: neg.s f10, f10 +; XTENSA-NEXT: madd.s f10, f9, f8 +; XTENSA-NEXT: rfr a2, f10 +; XTENSA-NEXT: retw.n + %negc = fneg float %c + %fma = call float @llvm.fma.f32(float %a, float %b, float %negc) + ret float %fma +} + +define float @fnmadd_s_intrinsics(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fnmadd_s_intrinsics: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: madd.s f10, f9, f8 +; XTENSA-NEXT: neg.s f8, f10 +; XTENSA-NEXT: rfr a2, f8 +; XTENSA-NEXT: retw.n + %fma = call float @llvm.fma.f32(float %a, float %b, float %c) + %neg = fneg float %fma + ret float %neg +} + +define float @fnmsub_s_intrinsics(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fnmsub_s_intrinsics: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a3 +; XTENSA-NEXT: wfr f9, a2 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: msub.s f10, f9, f8 +; XTENSA-NEXT: rfr a2, f10 +; XTENSA-NEXT: retw.n + %nega = fneg float %a + %fma = call float @llvm.fma.f32(float %nega, float %b, float %c) + ret float %fma +} + +define float @fnmsub_s_swap_intrinsics(float %a, float %b, float %c) nounwind { +; XTENSA-LABEL: fnmsub_s_swap_intrinsics: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: wfr f8, a2 +; XTENSA-NEXT: wfr f9, a3 +; XTENSA-NEXT: wfr f10, a4 +; XTENSA-NEXT: msub.s f10, f9, f8 +; XTENSA-NEXT: rfr a2, f10 +; XTENSA-NEXT: retw.n + %negb = fneg float %b + %fma = call float @llvm.fma.f32(float %a, float %negb, float %c) + ret float %fma +} From 9023e52277472c38c2a7e6aab3179ed2fc92a492 Mon Sep 17 00:00:00 2001 From: Ronen Ulanovsky Date: Sun, 16 Jul 2023 23:05:33 +0300 Subject: [PATCH 167/261] [Xtensa] Add MINMAX feature --- llvm/lib/Target/Xtensa/Xtensa.td | 13 ++++- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 3 + llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 9 +++ llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 ++ llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll | 55 +++++++++++++++++++ llvm/test/MC/Xtensa/xtensa-valid-minmax.s | 22 ++++++++ 7 files changed, 105 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-minmax.s diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 363bb45a72f76b..c31fa019fd5b8e 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -52,6 +52,11 @@ def FeatureNSA : SubtargetFeature<"nsa", "HasNSA", "true", def HasNSA : Predicate<"Subtarget->hasNSA()">, AssemblerPredicate<(all_of FeatureNSA)>; +def FeatureMINMAX : SubtargetFeature<"minmax", "HasMINMAX", "true", + "Enable Xtensa MINMAX option">; +def HasMINMAX : Predicate<"Subtarget->hasMINMAX()">, + AssemblerPredicate<(all_of FeatureMINMAX)>; + def FeatureMul16 : SubtargetFeature<"mul16", "HasMul16", "true", "Enable Xtensa Mul16 option">; def HasMul16 : Predicate<"Subtarget->hasMul16()">, @@ -179,20 +184,22 @@ def : Proc<"generic", []>; def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, - FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR]>; + FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, + FeatureMINMAX]>; def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>; def : Proc<"esp32s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, FeatureDiv32, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, - FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureESP32S2Ops]>; + FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureMINMAX, + FeatureESP32S2Ops]>; def : Proc<"esp32s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, - FeatureESP32S3Ops]>; + FeatureMINMAX, FeatureESP32S3Ops]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index b2fd26b44ea2dd..abb0c6bed5f00e 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -203,6 +203,9 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); + setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, + MVT::i32, Subtarget.hasMINMAX() ? Legal : Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index c5e6d760e0c965..bddc21e4865449 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1355,6 +1355,15 @@ def NSAU : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s), let r = 0xF; } +//===----------------------------------------------------------------------===// +// MINMAX Instructions +//===----------------------------------------------------------------------===// + +def MIN : ArithLogic_RRR<0x04, 0x03, "min", smin, 1>, Requires<[HasMINMAX]>; +def MAX : ArithLogic_RRR<0x05, 0x03, "max", smax, 1>, Requires<[HasMINMAX]>; +def MINU : ArithLogic_RRR<0x06, 0x03, "minu", umin, 1>, Requires<[HasMINMAX]>; +def MAXU : ArithLogic_RRR<0x07, 0x03, "maxu", umax, 1>, Requires<[HasMINMAX]>; + //===----------------------------------------------------------------------===// // Mul16 Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 311b757d55be12..9bee61c9f84e98 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -52,6 +52,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasLoop = false; HasSEXT = false; HasNSA = false; + HasMINMAX = false; HasMul16 = false; HasMul32 = false; HasMul32High = false; diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index a6647b52096136..46db59fb495288 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -59,6 +59,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa NSA option bool HasNSA; + // Enable Xtensa MINMAX option + bool HasMINMAX; + // Enable Xtensa Mul16 option bool HasMul16; @@ -159,6 +162,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasNSA() const { return HasNSA; } + bool hasMINMAX() const { return HasMINMAX; } + bool hasMul16() const { return HasMul16; } bool hasMul32() const { return HasMul32; } diff --git a/llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll b/llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll new file mode 100644 index 00000000000000..e6faa89c0ec592 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll @@ -0,0 +1,55 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=XTENSA %s + +declare i32 @llvm.smin.i32(i32, i32) + +define i32 @smin_i32(i32 %a, i32 %b) { +; XTENSA-LABEL: smin_i32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: min a2, a2, a3 +; XTENSA-NEXT: retw.n + %1 = tail call i32 @llvm.smin.i32(i32 %a, i32 %b) + ret i32 %1 +} + +declare i32 @llvm.smax.i32(i32, i32) + +define i32 @smax_i32(i32 %a, i32 %b) { +; XTENSA-LABEL: smax_i32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: max a2, a2, a3 +; XTENSA-NEXT: retw.n + %1 = tail call i32 @llvm.smax.i32(i32 %a, i32 %b) + ret i32 %1 +} + +declare i32 @llvm.umin.i32(i32, i32) + +define i32 @umin_i32(i32 %a, i32 %b) { +; XTENSA-LABEL: umin_i32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: minu a2, a2, a3 +; XTENSA-NEXT: retw.n + %1 = tail call i32 @llvm.umin.i32(i32 %a, i32 %b) + ret i32 %1 +} + +declare i32 @llvm.umax.i32(i32, i32) + +define i32 @umax_i32(i32 %a, i32 %b) { +; XTENSA-LABEL: umax_i32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: maxu a2, a2, a3 +; XTENSA-NEXT: retw.n + %1 = tail call i32 @llvm.umax.i32(i32 %a, i32 %b) + ret i32 %1 +} diff --git a/llvm/test/MC/Xtensa/xtensa-valid-minmax.s b/llvm/test/MC/Xtensa/xtensa-valid-minmax.s new file mode 100644 index 00000000000000..7fa7b6c31dbb37 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-minmax.s @@ -0,0 +1,22 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+minmax -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +# Instruction format RRR +# CHECK-INST: min a2, a3, a4 +# CHECK: encoding: [0x40,0x23,0x43] +min a2, a3, a4 + +# Instruction format RRR +# CHECK-INST: max a2, a3, a4 +# CHECK: encoding: [0x40,0x23,0x53] +max a2, a3, a4 + +# Instruction format RRR +# CHECK-INST: minu a2, a3, a4 +# CHECK: encoding: [0x40,0x23,0x63] +minu a2, a3, a4 + +# Instruction format RRR +# CHECK-INST: maxu a2, a3, a4 +# CHECK: encoding: [0x40,0x23,0x73] +maxu a2, a3, a4 From 0be7683a12246ca746d9734e88343fb3b2b29743 Mon Sep 17 00:00:00 2001 From: Ronen Ulanovsky Date: Sun, 16 Jul 2023 23:06:43 +0300 Subject: [PATCH 168/261] [Xtensa] Add CLAMPS feature --- .../lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp | 4 ++-- .../Xtensa/Disassembler/XtensaDisassembler.cpp | 6 +++--- .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 4 ++-- .../Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h | 2 +- .../Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp | 12 ++++++------ llvm/lib/Target/Xtensa/Xtensa.td | 11 ++++++++--- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 13 ++++++++++++- llvm/lib/Target/Xtensa/XtensaOperands.td | 10 +++++----- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 +++++ llvm/test/MC/Xtensa/xtensa-clamps-invalid.s | 9 +++++++++ llvm/test/MC/Xtensa/xtensa-clamps-valid.s | 12 ++++++++++++ llvm/test/MC/Xtensa/xtensa-sext-invalid.s | 9 +++++++++ llvm/test/MC/Xtensa/xtensa-sext-valid.s | 12 ++++++++++++ 14 files changed, 87 insertions(+), 23 deletions(-) create mode 100644 llvm/test/MC/Xtensa/xtensa-clamps-invalid.s create mode 100644 llvm/test/MC/Xtensa/xtensa-clamps-valid.s create mode 100644 llvm/test/MC/Xtensa/xtensa-sext-invalid.s create mode 100644 llvm/test/MC/Xtensa/xtensa-sext-valid.s diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index c1fdd96f6c0ad3..db35d3377bbfb4 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -379,7 +379,7 @@ struct XtensaOperand : public MCParsedAsmOperand { return false; } - bool isseimm7_22() const { return isImm(7, 22); } + bool isimm7_22() const { return isImm(7, 22); } bool isSelect_2() const { return isImm(0, 1); } @@ -739,7 +739,7 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_Invalidentry_imm12: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [0, 32760]"); - case Match_Invalidseimm7_22: + case Match_Invalidimm7_22: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [7, 22]"); case Match_InvalidSelect_2: diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 0c78d30ea1ab87..e0c9186bbec8cf 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -576,9 +576,9 @@ static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } -static DecodeStatus decodeSeimm7_22Operand(MCInst &Inst, uint64_t Imm, - int64_t Address, - const void *Decoder) { +static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { assert(isUInt<4>(Imm) && "Invalid immediate"); Inst.addOperand(MCOperand::createImm(Imm + 7)); return MCDisassembler::Success; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index 5919ef54014318..a8c1aaed10b1a6 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -438,8 +438,8 @@ void XtensaInstPrinter::printB4constu_AsmOperand(const MCInst *MI, int OpNum, printOperand(MI, OpNum, O); } -void XtensaInstPrinter::printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { +void XtensaInstPrinter::printImm7_22_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { if (MI->getOperand(OpNum).isImm()) { int64_t Value = MI->getOperand(OpNum).getImm(); assert((Value >= 7 && Value <= 22) && diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index a8416279d6ae0d..9224d0a98c14b5 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -69,7 +69,7 @@ class XtensaInstPrinter : public MCInstPrinter { void printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printImm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printSelect_2_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printSelect_4_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printSelect_8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 02d4d91bf1af74..185507a93c410f 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -139,9 +139,9 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; - uint32_t getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const; + uint32_t getImm7_22OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint8_t getSelect_2OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, @@ -629,9 +629,9 @@ XtensaMCCodeEmitter::getB4constuOpValue(const MCInst &MI, unsigned OpNo, } uint32_t -XtensaMCCodeEmitter::getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const { +XtensaMCCodeEmitter::getImm7_22OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); uint32_t res = static_cast(MO.getImm()); diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index c31fa019fd5b8e..7d03565751e6e9 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -47,6 +47,11 @@ def FeatureSEXT : SubtargetFeature<"sext", "HasSEXT", "true", def HasSEXT : Predicate<"Subtarget->hasSEXT()">, AssemblerPredicate<(all_of FeatureSEXT)>; +def FeatureCLAMPS : SubtargetFeature<"clamps", "HasCLAMPS", "true", + "Enable Xtensa CLAMPS option">; +def HasCLAMPS : Predicate<"Subtarget->hasCLAMPS()">, + AssemblerPredicate<(all_of FeatureCLAMPS)>; + def FeatureNSA : SubtargetFeature<"nsa", "HasNSA", "true", "Enable Xtensa NSA option">; def HasNSA : Predicate<"Subtarget->hasNSA()">, @@ -185,7 +190,7 @@ def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, - FeatureMINMAX]>; + FeatureMINMAX, FeatureCLAMPS]>; def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>; @@ -193,13 +198,13 @@ def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, F def : Proc<"esp32s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, FeatureDiv32, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureMINMAX, - FeatureESP32S2Ops]>; + FeatureCLAMPS, FeatureESP32S2Ops]>; def : Proc<"esp32s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32, FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, - FeatureMINMAX, FeatureESP32S3Ops]>; + FeatureMINMAX, FeatureCLAMPS, FeatureESP32S3Ops]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index bddc21e4865449..dd373a49f7ee09 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1334,13 +1334,24 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 0, Size = // SEXT Instructions //===----------------------------------------------------------------------===// -def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, seimm7_22:$imm), +def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, imm7_22:$imm), "sext\t$r, $s, $imm", []>, Requires<[HasSEXT]> { bits<4> imm; let t = imm; } +//===----------------------------------------------------------------------===// +// CLAMPS Instructions +//===----------------------------------------------------------------------===// + +def CLAMPS : RRR_Inst<0x00, 0x03, 0x03, (outs AR:$r), (ins AR:$s, imm7_22:$imm), + "clamps\t$r, $s, $imm", []>, Requires<[HasSEXT]> { + bits<4> imm; + + let t = imm; +} + //===----------------------------------------------------------------------===// // NSA Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 7810d0a36a354a..6a9bf514be8d3a 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -168,11 +168,11 @@ def b4constu: Immediate; -def seimm7_22: Immediate= 7 && Imm <= 22; }], "Seimm7_22_AsmOperand"> { - let EncoderMethod = "getSeimm7_22OpValue"; - let DecoderMethod = "decodeSeimm7_22Operand"; +// imm7_22 predicate - Immediate in the range [7,22] for sign extend and clamps +def Imm7_22_AsmOperand: ImmAsmOperand<"imm7_22">; +def imm7_22: Immediate= 7 && Imm <= 22; }], "Imm7_22_AsmOperand"> { + let EncoderMethod = "getImm7_22OpValue"; + let DecoderMethod = "decodeImm7_22Operand"; } // select_256 predicate - Immediate in the range [0,255] diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 9bee61c9f84e98..e267b71385c0f9 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -51,6 +51,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasBoolean = false; HasLoop = false; HasSEXT = false; + HasCLAMPS = false; HasNSA = false; HasMINMAX = false; HasMul16 = false; diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index 46db59fb495288..03378d8ea032a7 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -56,6 +56,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa Sign Extend option bool HasSEXT; + // Enable Xtensa CLAMPS option + bool HasCLAMPS; + // Enable Xtensa NSA option bool HasNSA; @@ -160,6 +163,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool hasSEXT() const { return HasSEXT; } + bool hasCLAMPS() const { return HasCLAMPS; } + bool hasNSA() const { return HasNSA; } bool hasMINMAX() const { return HasMINMAX; } diff --git a/llvm/test/MC/Xtensa/xtensa-clamps-invalid.s b/llvm/test/MC/Xtensa/xtensa-clamps-invalid.s new file mode 100644 index 00000000000000..524880a638afb3 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-clamps-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc %s -triple=xtensa -mattr=+clamps 2>&1 | FileCheck %s + +# imm7_22 +clamps a3, a2, 6 +# CHECK: :[[#@LINE-1]]:16: error: expected immediate in range [7, 22] + +# imm7_22 +clamps a3, a2, 23 +# CHECK: :[[#@LINE-1]]:16: error: expected immediate in range [7, 22] diff --git a/llvm/test/MC/Xtensa/xtensa-clamps-valid.s b/llvm/test/MC/Xtensa/xtensa-clamps-valid.s new file mode 100644 index 00000000000000..62b2858f04122f --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-clamps-valid.s @@ -0,0 +1,12 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+clamps -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +# Instruction format RRR +# CHECK-INST: clamps a3, a2, 7 +# CHECK: encoding: [0x00,0x32,0x33] +clamps a3, a2, 7 + +# Instruction format RRR +# CHECK-INST: clamps a3, a2, 22 +# CHECK: encoding: [0xf0,0x32,0x33] +clamps a3, a2, 22 diff --git a/llvm/test/MC/Xtensa/xtensa-sext-invalid.s b/llvm/test/MC/Xtensa/xtensa-sext-invalid.s new file mode 100644 index 00000000000000..aaf99e40549d13 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-sext-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc %s -triple=xtensa -mattr=+sext 2>&1 | FileCheck %s + +# imm7_22 +sext a3, a2, 6 +# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [7, 22] + +# imm7_22 +sext a3, a2, 23 +# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [7, 22] diff --git a/llvm/test/MC/Xtensa/xtensa-sext-valid.s b/llvm/test/MC/Xtensa/xtensa-sext-valid.s new file mode 100644 index 00000000000000..34111d5dadb9b7 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-sext-valid.s @@ -0,0 +1,12 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+sext -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +# Instruction format RRR +# CHECK-INST: sext a3, a2, 7 +# CHECK: encoding: [0x00,0x32,0x23] +sext a3, a2, 7 + +# Instruction format RRR +# CHECK-INST: sext a3, a2, 22 +# CHECK: encoding: [0xf0,0x32,0x23] +sext a3, a2, 22 From a58f52c545e889dd60d61b120013ceae8f0c4993 Mon Sep 17 00:00:00 2001 From: Ronen Ulanovsky Date: Thu, 20 Jul 2023 18:21:57 +0300 Subject: [PATCH 169/261] [Xtensa] Connect `abs` to `llvm.abs` --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 2 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 2 +- llvm/test/CodeGen/Xtensa/arith-intrinsics.ll | 27 +++++++++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/Xtensa/arith-intrinsics.ll diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index abb0c6bed5f00e..a41d8dd3daf221 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -180,6 +180,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::SUBC, MVT::i32, Expand); setOperationAction(ISD::SUBE, MVT::i32, Expand); + setOperationAction(ISD::ABS, MVT::i32, Legal); + setOperationAction(ISD::ADD, MVT::i64, Expand); setOperationAction(ISD::SUB, MVT::i64, Expand); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index dd373a49f7ee09..048075c6e5ecb2 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -52,7 +52,7 @@ def SUBX4 : SUBX<0x0E, "subx4", [(set AR:$r, (sub (shl AR:$s, (i32 2)), AR:$t))] def SUBX8 : SUBX<0x0F, "subx8", [(set AR:$r, (sub (shl AR:$s, (i32 3)), AR:$t))]>; def ABS : RRR_Inst<0x00, 0x00, 0x06, (outs AR:$r), (ins AR:$t), - "abs\t$r, $t", []> { + "abs\t$r, $t", [(set AR:$r, (abs AR:$t))]> { let s = 0x1; } diff --git a/llvm/test/CodeGen/Xtensa/arith-intrinsics.ll b/llvm/test/CodeGen/Xtensa/arith-intrinsics.ll new file mode 100644 index 00000000000000..c4a0749a0ed1e9 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/arith-intrinsics.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=XTENSA %s + +declare i32 @llvm.abs.i32(i32, i1) + +define i32 @abs_i32(i32 %a) { +; XTENSA-LABEL: abs_i32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: abs a2, a2 +; XTENSA-NEXT: retw.n + %1 = tail call i32 @llvm.abs.i32(i32 %a, i1 false) + ret i32 %1 +} + +define i32 @abs_poison_i32(i32 %a) { +; XTENSA-LABEL: abs_poison_i32: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: abs a2, a2 +; XTENSA-NEXT: retw.n + %1 = tail call i32 @llvm.abs.i32(i32 %a, i1 true) + ret i32 %1 +} From 3a71d2b5e8dab9e256e107c21185147f4a936069 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Sat, 29 Jul 2023 19:59:00 +0300 Subject: [PATCH 170/261] [Xtensa] ADD support of the CLAMPS/MINMAX in target parser. Implement support of the CLAMPS/MINMAX in Xtensa target parser. Fix clang CPUs test. --- clang/test/Driver/xtensa-cpus.c | 15 +++--- .../llvm/TargetParser/XtensaTargetParser.def | 20 ++++---- .../llvm/TargetParser/XtensaTargetParser.h | 46 ++++++++++--------- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 2 +- 4 files changed, 45 insertions(+), 38 deletions(-) diff --git a/clang/test/Driver/xtensa-cpus.c b/clang/test/Driver/xtensa-cpus.c index 7a93f4cba4b0c8..44e380adbf7cac 100644 --- a/clang/test/Driver/xtensa-cpus.c +++ b/clang/test/Driver/xtensa-cpus.c @@ -10,8 +10,9 @@ // RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32 | FileCheck -check-prefix=MCPU-ESP32 %s // MCPU-ESP32: "-target-cpu" "esp32" // MCPU-ESP32: "-target-feature" "+density" "-target-feature" "+fp" "-target-feature" "+windowed" "-target-feature" "+bool" -// MCPU-ESP32: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+mul32" -// MCPU-ESP32: "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+mac16" "-target-feature" "+dfpaccel" +// MCPU-ESP32: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+clamps" +// MCPU-ESP32: "-target-feature" "+minmax" "-target-feature" "+mul32" "-target-feature" "+mul32high" +// MCPU-ESP32: "-target-feature" "+div32" "-target-feature" "+mac16" "-target-feature" "+dfpaccel" // MCPU-ESP32: "-target-feature" "+s32c1i" "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl" // MCPU-ESP32: "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts" // MCPU-ESP32: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint" @@ -20,7 +21,8 @@ // RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32s2 | FileCheck -check-prefix=MCPU-ESP32S2 %s // MCPU-ESP32S2: "-target-cpu" "esp32s2" // MCPU-ESP32S2: "-target-feature" "+density" "-target-feature" "+windowed" "-target-feature" "+sext" "-target-feature" "+nsa" -// MCPU-ESP32S2: "-target-feature" "+mul32" "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+threadptr" +// MCPU-ESP32S2: "-target-feature" "+clamps" "-target-feature" "+minmax" "-target-feature" "+mul32" +// MCPU-ESP32S2: "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+threadptr" // MCPU-ESP32S2: "-target-feature" "+memctl" "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts" // MCPU-ESP32S2: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint" // MCPU-ESP32S2: "-target-feature" "+prid" "-target-feature" "+regprotect" "-target-feature" "+miscsr" "-target-feature" "+esp32s2" @@ -28,9 +30,10 @@ // RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32s3 | FileCheck -check-prefix=MCPU-ESP32S3 %s // MCPU-ESP32S3: "-target-cpu" "esp32s3" // MCPU-ESP32S3: "-target-feature" "+density" "-target-feature" "+fp" "-target-feature" "+windowed" "-target-feature" "+bool" -// MCPU-ESP32S3: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+mul32" -// MCPU-ESP32S3: "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+mac16" "-target-feature" "+dfpaccel" -// MCPU-ESP32S3: "-target-feature" "+s32c1i" "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl" +// MCPU-ESP32S3: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+clamps" +// MCPU-ESP32S3: "-target-feature" "+minmax" "-target-feature" "+mul32" "-target-feature" "+mul32high" "-target-feature" "+div32" +// MCPU-ESP32S3: "-target-feature" "+mac16" "-target-feature" "+dfpaccel" "-target-feature" "+s32c1i" +// MCPU-ESP32S3: "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl" // MCPU-ESP32S3: "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts" // MCPU-ESP32S3: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint" // MCPU-ESP32S3: "-target-feature" "+prid" "-target-feature" "+regprotect" "-target-feature" "+miscsr" "-target-feature" "+esp32s3" diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.def b/llvm/include/llvm/TargetParser/XtensaTargetParser.def index e46020700f2e2a..b765b015c12652 100644 --- a/llvm/include/llvm/TargetParser/XtensaTargetParser.def +++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.def @@ -21,6 +21,8 @@ XTENSA_FEATURE(FK_BOOLEAN, "bool") XTENSA_FEATURE(FK_LOOP, "loop") XTENSA_FEATURE(FK_SEXT, "sext") XTENSA_FEATURE(FK_NSA, "nsa") +XTENSA_FEATURE(FK_CLAMPS, "clamps") +XTENSA_FEATURE(FK_MINMAX, "minmax") XTENSA_FEATURE(FK_MUL32, "mul32") XTENSA_FEATURE(FK_MUL32HIGH, "mul32high") XTENSA_FEATURE(FK_DIV32, "div32") @@ -57,18 +59,18 @@ XTENSA_CPU(ESP8266, {"esp8266"}, FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_REGPROTECT | FK_PRID)) XTENSA_CPU(ESP32, {"esp32"}, (FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN | - FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | FK_THREADPTR | FK_DIV32 | - FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | - FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR)) + FK_SEXT | FK_NSA | FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | + FK_THREADPTR | FK_DIV32 | FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | + FK_COPROCESSOR | FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR)) XTENSA_CPU(ESP32S2, {"esp32s2"}, - (FK_DENSITY | FK_WINDOWED | FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_THREADPTR | FK_DIV32 | - FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | FK_INTERRUPT | - FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S2OPS)) + (FK_DENSITY | FK_WINDOWED | FK_SEXT | FK_NSA | FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH | + FK_THREADPTR | FK_DIV32 | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | + FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S2OPS)) XTENSA_CPU(ESP32S3, {"esp32s3"}, (FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN | - FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | FK_THREADPTR | FK_DIV32 | - FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | - FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | + FK_SEXT | FK_NSA | FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | + FK_THREADPTR | FK_DIV32 | FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | + FK_COPROCESSOR | FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S3OPS)) #undef XTENSA_CPU diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.h b/llvm/include/llvm/TargetParser/XtensaTargetParser.h index b2d642b2d63ef5..d4e639005a5a27 100644 --- a/llvm/include/llvm/TargetParser/XtensaTargetParser.h +++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.h @@ -36,28 +36,30 @@ enum FeatureKind : uint64_t { FK_LOOP = 1 << 5, FK_SEXT = 1 << 6, FK_NSA = 1 << 7, - FK_MUL32 = 1 << 8, - FK_MUL32HIGH = 1 << 9, - FK_DIV32 = 1 << 10, - FK_MAC16 = 1 << 11, - FK_DFPACCEL = 1 << 12, - FK_S32C1I = 1 << 13, - FK_THREADPTR = 1 << 14, - FK_EXTENDEDL32R = 1 << 15, - FK_ATOMCTL = 1 << 16, - FK_MEMCTL = 1 << 17, - FK_DEBUG = 1 << 18, - FK_EXCEPTION = 1 << 19, - FK_HIGHPRIINTERRUPTS = 1 << 20, - FK_COPROCESSOR = 1 << 21, - FK_INTERRUPT = 1 << 22, - FK_RVECTOR = 1 << 23, - FK_TIMERINT = 1 << 24, - FK_PRID = 1 << 25, - FK_REGPROTECT = 1 << 26, - FK_MISCSR = 1 << 27, - FK_ESP32S2OPS = 1 << 28, - FK_ESP32S3OPS = 1 << 29 + FK_CLAMPS = 1 << 8, + FK_MINMAX = 1 << 9, + FK_MUL32 = 1 << 10, + FK_MUL32HIGH = 1 << 11, + FK_DIV32 = 1 << 12, + FK_MAC16 = 1 << 13, + FK_DFPACCEL = 1 << 14, + FK_S32C1I = 1 << 15, + FK_THREADPTR = 1 << 16, + FK_EXTENDEDL32R = 1 << 17, + FK_ATOMCTL = 1 << 18, + FK_MEMCTL = 1 << 19, + FK_DEBUG = 1 << 20, + FK_EXCEPTION = 1 << 21, + FK_HIGHPRIINTERRUPTS = 1 << 22, + FK_COPROCESSOR = 1 << 23, + FK_INTERRUPT = 1 << 24, + FK_RVECTOR = 1 << 25, + FK_TIMERINT = 1 << 26, + FK_PRID = 1 << 27, + FK_REGPROTECT = 1 << 28, + FK_MISCSR = 1 << 29, + FK_ESP32S2OPS = 1 << 30, + FK_ESP32S3OPS = 1ULL << 31 }; CPUKind parseCPUKind(StringRef CPU); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 048075c6e5ecb2..20b36155eb9906 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1346,7 +1346,7 @@ def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, imm7_22:$imm), //===----------------------------------------------------------------------===// def CLAMPS : RRR_Inst<0x00, 0x03, 0x03, (outs AR:$r), (ins AR:$s, imm7_22:$imm), - "clamps\t$r, $s, $imm", []>, Requires<[HasSEXT]> { + "clamps\t$r, $s, $imm", []>, Requires<[HasCLAMPS]> { bits<4> imm; let t = imm; From af79bce707164edc5edd2a40ed41ff71aafd70b3 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 6 Jul 2023 11:22:03 +0300 Subject: [PATCH 171/261] [Xtensa] Handle musttail --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index a41d8dd3daf221..06e99a715074f0 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -23,6 +23,7 @@ #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/IR/DiagnosticInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -1051,6 +1052,12 @@ SDValue XtensaTargetLowering::getAddrPCRel(SDValue Op, return DAG.getNode(XtensaISD::PCREL_WRAPPER, DL, Ty, Op); } +static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg) { + MachineFunction &MF = DAG.getMachineFunction(); + DAG.getContext()->diagnose( + DiagnosticInfoUnsupported(MF.getFunction(), Msg, DL.getDebugLoc())); +} + SDValue XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl &InVals) const { @@ -1070,7 +1077,11 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); // TODO: Support tail call optimization. - IsTailCall = false; + if (IsTailCall) { + if (CLI.CB && CLI.CB->isMustTailCall()) + fail(DL, DAG, "tail call is not implemented"); + IsTailCall = false; + } // Analyze the operands of the call, assigning locations to each operand. SmallVector ArgLocs; From 40bcb37434d0cc8cec1783a0db2abef02bec345a Mon Sep 17 00:00:00 2001 From: Ronen Ulanovsky Date: Sun, 16 Jul 2023 04:58:04 +0300 Subject: [PATCH 172/261] [Xtensa] Implement CTLZ/CTTZ with NSAU Close https://github.com/espressif/llvm-project/pull/77 --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 22 ++++-- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 5 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 3 +- llvm/test/CodeGen/Xtensa/ctlz-cttz.ll | 67 +++++++++++++++++++ llvm/test/MC/Xtensa/xtensa-valid-nsa.s | 12 ++++ 5 files changed, 104 insertions(+), 5 deletions(-) create mode 100644 llvm/test/CodeGen/Xtensa/ctlz-cttz.ll create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-nsa.s diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 06e99a715074f0..f801df409f6a14 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -201,10 +201,12 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::ROTL, MVT::i32, Expand); setOperationAction(ISD::ROTR, MVT::i32, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand); - setOperationAction(ISD::CTTZ, MVT::i32, Expand); - setOperationAction(ISD::CTLZ, MVT::i32, Expand); - setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); - setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); + setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Expand); + if (Subtarget.hasNSA()) + setOperationAction(ISD::CTLZ, MVT::i32, Legal); + else + setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Expand); + setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32, Subtarget.hasMINMAX() ? Legal : Expand); @@ -416,6 +418,18 @@ bool XtensaTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, return false; } +bool XtensaTargetLowering::isCheapToSpeculateCtlz(Type *) const { + return Subtarget.hasNSA(); +} + +bool XtensaTargetLowering::isCheapToSpeculateCttz(Type *) const { + return Subtarget.hasNSA(); +} + +bool XtensaTargetLowering::isCtlzFast() const { + return Subtarget.hasNSA(); +} + /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. Register XtensaTargetLowering::getExceptionPointerRegister( diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 455ff0ad29f71b..3ca6fad904b802 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -121,6 +121,11 @@ class XtensaTargetLowering : public TargetLowering { EVT VT) const override; bool isFNegFree(EVT VT) const override; + bool isCheapToSpeculateCtlz(Type *Ty) const override; + + bool isCheapToSpeculateCttz(Type *Ty) const override; + + bool isCtlzFast() const override; /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 20b36155eb9906..51b0dd9a0cba58 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1362,7 +1362,8 @@ def NSA : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s), } def NSAU : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s), - "nsau\t$t, $s", []>, Requires<[HasNSA]> { + "nsau\t$t, $s", + [(set AR:$t, (ctlz AR:$s))]>, Requires<[HasNSA]> { let r = 0xF; } diff --git a/llvm/test/CodeGen/Xtensa/ctlz-cttz.ll b/llvm/test/CodeGen/Xtensa/ctlz-cttz.ll new file mode 100644 index 00000000000000..8008ba354e6ab8 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/ctlz-cttz.ll @@ -0,0 +1,67 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=XTENSA %s + +declare i32 @llvm.ctlz.i32(i32, i1) + +define i32 @test1_ctlz(i32 %v) { +; XTENSA-LABEL: test1_ctlz: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: nsau a2, a2 +; XTENSA-NEXT: retw.n + %1 = tail call i32 @llvm.ctlz.i32(i32 %v, i1 false) + ret i32 %1 +} + +define i32 @test2_ctlz(i32 %v) { +; XTENSA-LABEL: test2_ctlz: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: nsau a2, a2 +; XTENSA-NEXT: retw.n + %cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true) + %tobool = icmp eq i32 %v, 0 + %cond = select i1 %tobool, i32 32, i32 %cnt + ret i32 %cond +} + +declare i32 @llvm.cttz.i32(i32, i1) + +define i32 @test1_cttz(i32 %v) { +; XTENSA-LABEL: test1_cttz: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: movi.n a8, -1 +; XTENSA-NEXT: xor a8, a2, a8 +; XTENSA-NEXT: addi.n a9, a2, -1 +; XTENSA-NEXT: and a8, a8, a9 +; XTENSA-NEXT: nsau a8, a8 +; XTENSA-NEXT: movi.n a9, 32 +; XTENSA-NEXT: sub a2, a9, a8 +; XTENSA-NEXT: retw.n + %1 = tail call i32 @llvm.cttz.i32(i32 %v, i1 false) + ret i32 %1 +} + +define i32 @test2_cttz(i32 %v) { +; XTENSA-LABEL: test2_cttz: +; XTENSA: # %bb.0: +; XTENSA-NEXT: entry a1, 32 +; XTENSA-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-NEXT: movi.n a8, -1 +; XTENSA-NEXT: xor a8, a2, a8 +; XTENSA-NEXT: addi.n a9, a2, -1 +; XTENSA-NEXT: and a8, a8, a9 +; XTENSA-NEXT: nsau a8, a8 +; XTENSA-NEXT: movi.n a9, 32 +; XTENSA-NEXT: sub a2, a9, a8 +; XTENSA-NEXT: retw.n + %cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true) + %tobool = icmp eq i32 %v, 0 + %cond = select i1 %tobool, i32 32, i32 %cnt + ret i32 %cond +} diff --git a/llvm/test/MC/Xtensa/xtensa-valid-nsa.s b/llvm/test/MC/Xtensa/xtensa-valid-nsa.s new file mode 100644 index 00000000000000..150818b2dbaa99 --- /dev/null +++ b/llvm/test/MC/Xtensa/xtensa-valid-nsa.s @@ -0,0 +1,12 @@ +# RUN: llvm-mc %s -triple=xtensa -mattr=+nsa -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s + +# Instruction format RRR +# CHECK-INST: nsa a3, a2 +# CHECK: encoding: [0x30,0xe2,0x40] +nsa a3, a2 + +# Instruction format RRR +# CHECK-INST: nsau a3, a2 +# CHECK: encoding: [0x30,0xf2,0x40] +nsau a3, a2 From bc03515836409f69a5fba04ff4f645af329157e1 Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Wed, 14 Jun 2023 14:57:35 +0200 Subject: [PATCH 173/261] [Xtensa] Add spill slot for smaller estimaded stack size. --- llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index aabdc73b2f6ec1..9c67b0d4195715 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -22,6 +22,8 @@ #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/IR/Function.h" +#define STACK_SIZE_THRESHOLD 100 + using namespace llvm; XtensaFrameLowering::XtensaFrameLowering() @@ -375,7 +377,8 @@ void XtensaFrameLowering::processFunctionBeforeFrameFinalized( // In WinABI mode add register scavenging slot // FIXME: It may be posssible to add spill slot by more optimal way - if (STI.isWinABI() && (MF.getFrameInfo().estimateStackSize(MF) > 256)) { + if (STI.isWinABI() && + (MF.getFrameInfo().estimateStackSize(MF) > STACK_SIZE_THRESHOLD)) { MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterClass &RC = Xtensa::ARRegClass; const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); From 111f603d04f740476564363f92123cf9f94d7a55 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Sep 2023 13:51:47 +0300 Subject: [PATCH 174/261] [Xtensa] Fix decoder namespace for ESP32S3. Set decoder namespace to "ESP32S3" for ESP32S3 instructions to avoid possible decoding conflicts in future. --- .../Disassembler/XtensaDisassembler.cpp | 57 ++++++++++++++++++- llvm/lib/Target/Xtensa/XtensaInstrFormats.td | 2 + 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index e0c9186bbec8cf..8ea0991b5040ed 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -42,6 +42,10 @@ class XtensaDisassembler : public MCDisassembler { return STI.hasFeature(Xtensa::FeatureDensity); } + bool hasESP32S3Ops() const { + return STI.getFeatureBits()[Xtensa::FeatureESP32S3Ops]; + } + DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef Bytes, uint64_t Address, raw_ostream &CStream) const override; @@ -787,7 +791,25 @@ static DecodeStatus readInstruction24(ArrayRef Bytes, uint64_t Address, Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); } - Size = 3; + return MCDisassembler::Success; +} + +/// Read three bytes from the ArrayRef and return 32 bit data +static DecodeStatus readInstruction32(ArrayRef Bytes, uint64_t Address, + uint64_t &Size, uint32_t &Insn, + bool IsLittleEndian) { + // We want to read exactly 4 Bytes of data. + if (Bytes.size() < 4) { + Size = 0; + return MCDisassembler::Fail; + } + + if (!IsLittleEndian) { + report_fatal_error("Big-endian mode currently is not supported!"); + } else { + Insn = (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); + } + return MCDisassembler::Success; } @@ -800,6 +822,7 @@ DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size, uint32_t Insn; DecodeStatus Result; + // Parse 16-bit instructions if (hasDensity()) { Result = readInstruction16(Bytes, Address, Size, Insn, IsLittleEndian); if (Result == MCDisassembler::Fail) @@ -812,10 +835,42 @@ DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size, } } + // Parse Core 24-bit instructions Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; LLVM_DEBUG(dbgs() << "Trying Xtensa 24-bit instruction table :\n"); Result = decodeInstruction(DecoderTable24, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 3; + return Result; + } + + if (hasESP32S3Ops()) { + // Parse ESP32S3 24-bit instructions + Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + LLVM_DEBUG(dbgs() << "Trying ESP32S3 table (24-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableESP32S324, MI, Insn, + Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 3; + return Result; + } + + // Parse ESP32S3 32-bit instructions + Result = readInstruction32(Bytes, Address, Size, Insn, IsLittleEndian); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + LLVM_DEBUG(dbgs() << "Trying ESP32S3 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableESP32S332, MI, Insn, + Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + return Result; } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrFormats.td b/llvm/lib/Target/Xtensa/XtensaInstrFormats.td index beb15c3c5647b9..2590c90688b8e3 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrFormats.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrFormats.td @@ -213,6 +213,7 @@ class RI6_Inst op0, bits<1> i, bits<1> z, dag outs, dag ins, class EE_Inst24 pattern, InstrItinClass itin = NoItinerary> : XtensaInst24 { + let DecoderNamespace = "ESP32S3"; } class EE_Inst32 pattern, @@ -220,6 +221,7 @@ class EE_Inst32 pattern, : XtensaInst<4, outs, ins, asmstr, pattern, itin> { field bits<32> Inst; field bits<32> SoftFail = 0; + let DecoderNamespace = "ESP32S3"; } // Pseudo instructions From 549abfc4fbe4edfc16bf44f3c2d902c35bdd34b7 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 22 Aug 2023 23:34:08 +0300 Subject: [PATCH 175/261] [Xtensa] Fix hardware loop --- llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp | 43 +++++++++++++++++-- .../lib/Target/Xtensa/XtensaHardwareLoops.cpp | 2 +- 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp b/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp index 3089d7ee59fbff..4997401f9fda8c 100644 --- a/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFixupHWLoops.cpp @@ -302,10 +302,45 @@ bool XtensaFixupHwLoops::fixupLoopInstrs(MachineLoop *L) { .addMBB(LoopEnd); LoopEnd->addSuccessor(LoopEnd); } else { - BuildMI(*PMBB, PII, DL, TII->get(Xtensa::LOOPEND)).addMBB(PMBB); - PMBB->addSuccessor(PMBB); - BuildMI(*PMBB, PII, DL, TII->get(Xtensa::NOP)); - LoopEnd = PMBB; + bool NeedBlockForJump = false; + // Check for branches to the loop end basic block from + // predecessors + for (auto I = PMBB->pred_begin(), E = PMBB->pred_end(); I != E; + ++I) { + MachineBasicBlock *PLEMBB = *I; + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; + SmallVector Cond; + if (!TII->analyzeBranch(*PLEMBB, TBB, FBB, Cond)) { + if (TBB == PMBB) { + NeedBlockForJump = true; + break; + } + } else { + NeedBlockForJump = true; + break; + } + } + // Create block and insert it before loop end address as + // target for jump/branch instruction to avoid premature exit from + // loop + if (NeedBlockForJump) { + LoopEnd = MF->CreateMachineBasicBlock(); + MF->insert(++(PMBB->getIterator()), LoopEnd); + LoopEnd->transferSuccessors(PMBB); + LoopEnd->splice(LoopEnd->end(), PMBB, PII, PMBB->end()); + PMBB->addSuccessor(LoopEnd); + BuildMI(*PMBB, PMBB->end(), DL, TII->get(Xtensa::NOP)); + + BuildMI(*LoopEnd, LoopEnd->begin(), DL, + TII->get(Xtensa::LOOPEND)) + .addMBB(LoopEnd); + LoopEnd->addSuccessor(LoopEnd); + } else { + BuildMI(*PMBB, PII, DL, TII->get(Xtensa::LOOPEND)).addMBB(PMBB); + PMBB->addSuccessor(PMBB); + BuildMI(*PMBB, PII, DL, TII->get(Xtensa::NOP)); + LoopEnd = PMBB; + } } Changed = true; diff --git a/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp b/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp index 34dc193995594d..f77a98486ec3fa 100644 --- a/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp +++ b/llvm/lib/Target/Xtensa/XtensaHardwareLoops.cpp @@ -360,7 +360,7 @@ bool XtensaHardwareLoops::processLoop(MachineLoop *L) { } bool XtensaHardwareLoops::checkLoopSize(MachineLoop *L) { - uint64_t LoopSize = 0; + uint64_t LoopSize = 3; //Reserve space for possible NOP for (auto *MBB : L->getBlocks()) { uint64_t BlockSize = 0; From f48707fc676030cbaa73858605077712d5dcb3dc Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Mar 2024 01:41:55 +0300 Subject: [PATCH 176/261] [Xtensa] Fix _FAST_ int types. --- clang/include/clang/Basic/LangOptions.def | 2 + clang/include/clang/Driver/Options.td | 5 + clang/lib/Driver/ToolChains/Clang.cpp | 3 + clang/lib/Frontend/InitPreprocessor.cpp | 27 +- clang/test/Preprocessor/init.c | 606 ++++++++++++++++++++++ 5 files changed, 633 insertions(+), 10 deletions(-) diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 4942dcaa086eac..71a152eb5a4422 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -472,6 +472,8 @@ LANGOPT(RelativeCXXABIVTables, 1, 0, LANGOPT(OmitVTableRTTI, 1, 0, "Use an ABI-incompatible v-table layout that omits the RTTI component") +LANGOPT(FastIntMin32, 1, 0, "Minimum width of _FAST_ int type") + LANGOPT(VScaleMin, 32, 0, "Minimum vscale value") LANGOPT(VScaleMax, 32, 0, "Maximum vscale value") diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index aa8969799a7dc9..c2919dfd8af3be 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6110,6 +6110,11 @@ def mfix_esp32_psram_cache_strategy_EQ : Joined<["-"], "mfix-esp32-psram-cache-s Values<"memw, nops">; def mlongcalls : Flag<["-"], "mlongcalls">, Group; def mtext_section_literals : Flag<["-"], "mtext-section-literals">, Group; +def mfast_int_min32 : Flag<["-"], "mfast-int-min32">, Group, + Flags<[NoXarchOption]>, + Visibility<[ClangOption, CC1Option]>, + HelpText<"Set bit width of the _FAST_ int type to 32">, + MarshallingInfoFlag>; // These are legacy user-facing driver-level option spellings. They are always // aliases for options that are spelled using the more common Unix / GNU flag diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index beead97a8c35da..57f7458d485754 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2369,6 +2369,9 @@ void Clang::AddXtensaTargetArgs(const ArgList &Args, CmdArgs.push_back("-mllvm"); CmdArgs.push_back("-mtext-section-literals"); } + + if (Args.getLastArg(options::OPT_mfast_int_min32)) + CmdArgs.push_back("-mfast-int-min32"); } void Clang::DumpCompilationDatabase(Compilation &C, StringRef Filename, diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index 1b91c86f91398c..6b978a5e8603fe 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -278,10 +278,14 @@ static void DefineLeastWidthIntType(unsigned TypeWidth, bool IsSigned, } static void DefineFastIntType(unsigned TypeWidth, bool IsSigned, - const TargetInfo &TI, MacroBuilder &Builder) { + const TargetInfo &TI, MacroBuilder &Builder, + unsigned MinFastTypeWidth) { + if (MinFastTypeWidth < TypeWidth) + MinFastTypeWidth = TypeWidth; // stdint.h currently defines the fast int types as equivalent to the least // types. - TargetInfo::IntType Ty = TI.getLeastIntTypeByWidth(TypeWidth, IsSigned); + TargetInfo::IntType Ty = + TI.getLeastIntTypeByWidth(MinFastTypeWidth, IsSigned); if (Ty == TargetInfo::NoInt) return; @@ -1170,14 +1174,17 @@ static void InitializePredefinedMacros(const TargetInfo &TI, DefineLeastWidthIntType(64, true, TI, Builder); DefineLeastWidthIntType(64, false, TI, Builder); - DefineFastIntType(8, true, TI, Builder); - DefineFastIntType(8, false, TI, Builder); - DefineFastIntType(16, true, TI, Builder); - DefineFastIntType(16, false, TI, Builder); - DefineFastIntType(32, true, TI, Builder); - DefineFastIntType(32, false, TI, Builder); - DefineFastIntType(64, true, TI, Builder); - DefineFastIntType(64, false, TI, Builder); + unsigned MinFastTypeWidth = 8; + if (LangOpts.FastIntMin32) + MinFastTypeWidth = 32; + DefineFastIntType(8, true, TI, Builder, MinFastTypeWidth); + DefineFastIntType(8, false, TI, Builder, MinFastTypeWidth); + DefineFastIntType(16, true, TI, Builder, MinFastTypeWidth); + DefineFastIntType(16, false, TI, Builder, MinFastTypeWidth); + DefineFastIntType(32, true, TI, Builder, MinFastTypeWidth); + DefineFastIntType(32, false, TI, Builder, MinFastTypeWidth); + DefineFastIntType(64, true, TI, Builder, MinFastTypeWidth); + DefineFastIntType(64, false, TI, Builder, MinFastTypeWidth); Builder.defineMacro("__USER_LABEL_PREFIX__", TI.getUserLabelPrefix()); diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index c3dbd94b2f741b..814d366dbc7372 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -2660,3 +2660,609 @@ // RISCV64-LINUX: #define __unix__ 1 // RISCV64-LINUX: #define linux 1 // RISCV64-LINUX: #define unix 1 + +// RUN: %clang_cc1 -E -dM -ffreestanding -triple=xtensa-esp-unknown-elf < /dev/null \ +// RUN: | FileCheck -match-full-lines -check-prefix=XTENSA %s +// XTENSA: #define _ILP32 1 +// XTENSA: #define __ATOMIC_ACQUIRE 2 +// XTENSA: #define __ATOMIC_ACQ_REL 4 +// XTENSA: #define __ATOMIC_CONSUME 1 +// XTENSA: #define __ATOMIC_RELAXED 0 +// XTENSA: #define __ATOMIC_RELEASE 3 +// XTENSA: #define __ATOMIC_SEQ_CST 5 +// XTENSA: #define __BIGGEST_ALIGNMENT__ 4 +// XTENSA: #define __BITINT_MAXWIDTH__ 128 +// XTENSA: #define __BOOL_WIDTH__ 8 +// XTENSA: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ +// XTENSA: #define __CHAR16_TYPE__ unsigned short +// XTENSA: #define __CHAR32_TYPE__ unsigned int +// XTENSA: #define __CHAR_BIT__ 8 +// XTENSA: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_INT_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1 +// XTENSA: #define __CLANG_ATOMIC_LONG_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 2 +// XTENSA: #define __CONSTANT_CFSTRINGS__ 1 +// XTENSA: #define __DBL_DECIMAL_DIG__ 17 +// XTENSA: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324 +// XTENSA: #define __DBL_DIG__ 15 +// XTENSA: #define __DBL_EPSILON__ 2.2204460492503131e-16 +// XTENSA: #define __DBL_HAS_DENORM__ 1 +// XTENSA: #define __DBL_HAS_INFINITY__ 1 +// XTENSA: #define __DBL_HAS_QUIET_NAN__ 1 +// XTENSA: #define __DBL_MANT_DIG__ 53 +// XTENSA: #define __DBL_MAX_10_EXP__ 308 +// XTENSA: #define __DBL_MAX_EXP__ 1024 +// XTENSA: #define __DBL_MAX__ 1.7976931348623157e+308 +// XTENSA: #define __DBL_MIN_10_EXP__ (-307) +// XTENSA: #define __DBL_MIN_EXP__ (-1021) +// XTENSA: #define __DBL_MIN__ 2.2250738585072014e-308 +// XTENSA: #define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__ +// XTENSA: #define __ELF__ 1 +// XTENSA: #define __FINITE_MATH_ONLY__ 0 +// XTENSA: #define __FLT_DECIMAL_DIG__ 9 +// XTENSA: #define __FLT_DENORM_MIN__ 1.40129846e-45F +// XTENSA: #define __FLT_DIG__ 6 +// XTENSA: #define __FLT_EPSILON__ 1.19209290e-7F +// XTENSA: #define __FLT_HAS_DENORM__ 1 +// XTENSA: #define __FLT_HAS_INFINITY__ 1 +// XTENSA: #define __FLT_HAS_QUIET_NAN__ 1 +// XTENSA: #define __FLT_MANT_DIG__ 24 +// XTENSA: #define __FLT_MAX_10_EXP__ 38 +// XTENSA: #define __FLT_MAX_EXP__ 128 +// XTENSA: #define __FLT_MAX__ 3.40282347e+38F +// XTENSA: #define __FLT_MIN_10_EXP__ (-37) +// XTENSA: #define __FLT_MIN_EXP__ (-125) +// XTENSA: #define __FLT_MIN__ 1.17549435e-38F +// XTENSA: #define __FLT_RADIX__ 2 +// XTENSA: #define __ILP32__ 1 +// XTENSA: #define __INT16_C_SUFFIX__ +// XTENSA: #define __INT16_FMTd__ "hd" +// XTENSA: #define __INT16_FMTi__ "hi" +// XTENSA: #define __INT16_MAX__ 32767 +// XTENSA: #define __INT16_TYPE__ short +// XTENSA: #define __INT32_C_SUFFIX__ +// XTENSA: #define __INT32_FMTd__ "d" +// XTENSA: #define __INT32_FMTi__ "i" +// XTENSA: #define __INT32_MAX__ 2147483647 +// XTENSA: #define __INT32_TYPE__ int +// XTENSA: #define __INT64_C_SUFFIX__ LL +// XTENSA: #define __INT64_FMTd__ "lld" +// XTENSA: #define __INT64_FMTi__ "lli" +// XTENSA: #define __INT64_MAX__ 9223372036854775807LL +// XTENSA: #define __INT64_TYPE__ long long int +// XTENSA: #define __INT8_C_SUFFIX__ +// XTENSA: #define __INT8_FMTd__ "hhd" +// XTENSA: #define __INT8_FMTi__ "hhi" +// XTENSA: #define __INT8_MAX__ 127 +// XTENSA: #define __INT8_TYPE__ signed char +// XTENSA: #define __INTMAX_C_SUFFIX__ LL +// XTENSA: #define __INTMAX_FMTd__ "lld" +// XTENSA: #define __INTMAX_FMTi__ "lli" +// XTENSA: #define __INTMAX_MAX__ 9223372036854775807LL +// XTENSA: #define __INTMAX_TYPE__ long long int +// XTENSA: #define __INTMAX_WIDTH__ 64 +// XTENSA: #define __INTPTR_FMTd__ "d" +// XTENSA: #define __INTPTR_FMTi__ "i" +// XTENSA: #define __INTPTR_MAX__ 2147483647 +// XTENSA: #define __INTPTR_TYPE__ int +// XTENSA: #define __INTPTR_WIDTH__ 32 +// XTENSA: #define __INT_FAST16_FMTd__ "hd" +// XTENSA: #define __INT_FAST16_FMTi__ "hi" +// XTENSA: #define __INT_FAST16_MAX__ 32767 +// XTENSA: #define __INT_FAST16_TYPE__ short +// XTENSA: #define __INT_FAST16_WIDTH__ 16 +// XTENSA: #define __INT_FAST32_FMTd__ "d" +// XTENSA: #define __INT_FAST32_FMTi__ "i" +// XTENSA: #define __INT_FAST32_MAX__ 2147483647 +// XTENSA: #define __INT_FAST32_TYPE__ int +// XTENSA: #define __INT_FAST32_WIDTH__ 32 +// XTENSA: #define __INT_FAST64_FMTd__ "lld" +// XTENSA: #define __INT_FAST64_FMTi__ "lli" +// XTENSA: #define __INT_FAST64_MAX__ 9223372036854775807LL +// XTENSA: #define __INT_FAST64_TYPE__ long long int +// XTENSA: #define __INT_FAST64_WIDTH__ 64 +// XTENSA: #define __INT_FAST8_FMTd__ "hhd" +// XTENSA: #define __INT_FAST8_FMTi__ "hhi" +// XTENSA: #define __INT_FAST8_MAX__ 127 +// XTENSA: #define __INT_FAST8_TYPE__ signed char +// XTENSA: #define __INT_FAST8_WIDTH__ 8 +// XTENSA: #define __INT_LEAST16_FMTd__ "hd" +// XTENSA: #define __INT_LEAST16_FMTi__ "hi" +// XTENSA: #define __INT_LEAST16_MAX__ 32767 +// XTENSA: #define __INT_LEAST16_TYPE__ short +// XTENSA: #define __INT_LEAST16_WIDTH__ 16 +// XTENSA: #define __INT_LEAST32_FMTd__ "d" +// XTENSA: #define __INT_LEAST32_FMTi__ "i" +// XTENSA: #define __INT_LEAST32_MAX__ 2147483647 +// XTENSA: #define __INT_LEAST32_TYPE__ int +// XTENSA: #define __INT_LEAST32_WIDTH__ 32 +// XTENSA: #define __INT_LEAST64_FMTd__ "lld" +// XTENSA: #define __INT_LEAST64_FMTi__ "lli" +// XTENSA: #define __INT_LEAST64_MAX__ 9223372036854775807LL +// XTENSA: #define __INT_LEAST64_TYPE__ long long int +// XTENSA: #define __INT_LEAST64_WIDTH__ 64 +// XTENSA: #define __INT_LEAST8_FMTd__ "hhd" +// XTENSA: #define __INT_LEAST8_FMTi__ "hhi" +// XTENSA: #define __INT_LEAST8_MAX__ 127 +// XTENSA: #define __INT_LEAST8_TYPE__ signed char +// XTENSA: #define __INT_LEAST8_WIDTH__ 8 +// XTENSA: #define __INT_MAX__ 2147483647 +// XTENSA: #define __INT_WIDTH__ 32 +// XTENSA: #define __LDBL_DECIMAL_DIG__ 17 +// XTENSA: #define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L +// XTENSA: #define __LDBL_DIG__ 15 +// XTENSA: #define __LDBL_EPSILON__ 2.2204460492503131e-16L +// XTENSA: #define __LDBL_HAS_DENORM__ 1 +// XTENSA: #define __LDBL_HAS_INFINITY__ 1 +// XTENSA: #define __LDBL_HAS_QUIET_NAN__ 1 +// XTENSA: #define __LDBL_MANT_DIG__ 53 +// XTENSA: #define __LDBL_MAX_10_EXP__ 308 +// XTENSA: #define __LDBL_MAX_EXP__ 1024 +// XTENSA: #define __LDBL_MAX__ 1.7976931348623157e+308L +// XTENSA: #define __LDBL_MIN_10_EXP__ (-307) +// XTENSA: #define __LDBL_MIN_EXP__ (-1021) +// XTENSA: #define __LDBL_MIN__ 2.2250738585072014e-308L +// XTENSA: #define __LITTLE_ENDIAN__ 1 +// XTENSA: #define __LLONG_WIDTH__ 64 +// XTENSA: #define __LONG_LONG_MAX__ 9223372036854775807LL +// XTENSA: #define __LONG_MAX__ 2147483647L +// XTENSA: #define __LONG_WIDTH__ 32 +// XTENSA: #define __NO_INLINE__ 1 +// XTENSA: #define __NO_MATH_ERRNO__ 1 +// XTENSA: #define __OBJC_BOOL_IS_BOOL 0 +// XTENSA: #define __OPENCL_MEMORY_SCOPE_ALL_SVM_DEVICES 3 +// XTENSA: #define __OPENCL_MEMORY_SCOPE_DEVICE 2 +// XTENSA: #define __OPENCL_MEMORY_SCOPE_SUB_GROUP 4 +// XTENSA: #define __OPENCL_MEMORY_SCOPE_WORK_GROUP 1 +// XTENSA: #define __OPENCL_MEMORY_SCOPE_WORK_ITEM 0 +// XTENSA: #define __ORDER_BIG_ENDIAN__ 4321 +// XTENSA: #define __ORDER_LITTLE_ENDIAN__ 1234 +// XTENSA: #define __ORDER_PDP_ENDIAN__ 3412 +// XTENSA: #define __POINTER_WIDTH__ 32 +// XTENSA: #define __PRAGMA_REDEFINE_EXTNAME 1 +// XTENSA: #define __PTRDIFF_FMTd__ "d" +// XTENSA: #define __PTRDIFF_FMTi__ "i" +// XTENSA: #define __PTRDIFF_MAX__ 2147483647 +// XTENSA: #define __PTRDIFF_TYPE__ int +// XTENSA: #define __PTRDIFF_WIDTH__ 32 +// XTENSA: #define __SCHAR_MAX__ 127 +// XTENSA: #define __SHRT_MAX__ 32767 +// XTENSA: #define __SHRT_WIDTH__ 16 +// XTENSA: #define __SIG_ATOMIC_MAX__ 2147483647 +// XTENSA: #define __SIG_ATOMIC_WIDTH__ 32 +// XTENSA: #define __SIZEOF_DOUBLE__ 8 +// XTENSA: #define __SIZEOF_FLOAT__ 4 +// XTENSA: #define __SIZEOF_INT__ 4 +// XTENSA: #define __SIZEOF_LONG_DOUBLE__ 8 +// XTENSA: #define __SIZEOF_LONG_LONG__ 8 +// XTENSA: #define __SIZEOF_LONG__ 4 +// XTENSA: #define __SIZEOF_POINTER__ 4 +// XTENSA: #define __SIZEOF_PTRDIFF_T__ 4 +// XTENSA: #define __SIZEOF_SHORT__ 2 +// XTENSA: #define __SIZEOF_SIZE_T__ 4 +// XTENSA: #define __SIZEOF_WCHAR_T__ 1 +// XTENSA: #define __SIZEOF_WINT_T__ 4 +// XTENSA: #define __SIZE_FMTX__ "X" +// XTENSA: #define __SIZE_FMTo__ "o" +// XTENSA: #define __SIZE_FMTu__ "u" +// XTENSA: #define __SIZE_FMTx__ "x" +// XTENSA: #define __SIZE_MAX__ 4294967295U +// XTENSA: #define __SIZE_TYPE__ unsigned int +// XTENSA: #define __SIZE_WIDTH__ 32 +// XTENSA: #define __STDC_HOSTED__ 0 +// XTENSA: #define __STDC_UTF_16__ 1 +// XTENSA: #define __STDC_UTF_32__ 1 +// XTENSA: #define __STDC_VERSION__ 201710L +// XTENSA: #define __STDC__ 1 +// XTENSA: #define __UINT16_C_SUFFIX__ +// XTENSA: #define __UINT16_FMTX__ "hX" +// XTENSA: #define __UINT16_FMTo__ "ho" +// XTENSA: #define __UINT16_FMTu__ "hu" +// XTENSA: #define __UINT16_FMTx__ "hx" +// XTENSA: #define __UINT16_MAX__ 65535 +// XTENSA: #define __UINT16_TYPE__ unsigned short +// XTENSA: #define __UINT32_C_SUFFIX__ U +// XTENSA: #define __UINT32_FMTX__ "X" +// XTENSA: #define __UINT32_FMTo__ "o" +// XTENSA: #define __UINT32_FMTu__ "u" +// XTENSA: #define __UINT32_FMTx__ "x" +// XTENSA: #define __UINT32_MAX__ 4294967295U +// XTENSA: #define __UINT32_TYPE__ unsigned int +// XTENSA: #define __UINT64_C_SUFFIX__ ULL +// XTENSA: #define __UINT64_FMTX__ "llX" +// XTENSA: #define __UINT64_FMTo__ "llo" +// XTENSA: #define __UINT64_FMTu__ "llu" +// XTENSA: #define __UINT64_FMTx__ "llx" +// XTENSA: #define __UINT64_MAX__ 18446744073709551615ULL +// XTENSA: #define __UINT64_TYPE__ long long unsigned int +// XTENSA: #define __UINT8_C_SUFFIX__ +// XTENSA: #define __UINT8_FMTX__ "hhX" +// XTENSA: #define __UINT8_FMTo__ "hho" +// XTENSA: #define __UINT8_FMTu__ "hhu" +// XTENSA: #define __UINT8_FMTx__ "hhx" +// XTENSA: #define __UINT8_MAX__ 255 +// XTENSA: #define __UINT8_TYPE__ unsigned char +// XTENSA: #define __UINTMAX_C_SUFFIX__ ULL +// XTENSA: #define __UINTMAX_FMTX__ "llX" +// XTENSA: #define __UINTMAX_FMTo__ "llo" +// XTENSA: #define __UINTMAX_FMTu__ "llu" +// XTENSA: #define __UINTMAX_FMTx__ "llx" +// XTENSA: #define __UINTMAX_MAX__ 18446744073709551615ULL +// XTENSA: #define __UINTMAX_TYPE__ long long unsigned int +// XTENSA: #define __UINTMAX_WIDTH__ 64 +// XTENSA: #define __UINTPTR_FMTX__ "X" +// XTENSA: #define __UINTPTR_FMTo__ "o" +// XTENSA: #define __UINTPTR_FMTu__ "u" +// XTENSA: #define __UINTPTR_FMTx__ "x" +// XTENSA: #define __UINTPTR_MAX__ 4294967295U +// XTENSA: #define __UINTPTR_TYPE__ unsigned int +// XTENSA: #define __UINTPTR_WIDTH__ 32 +// XTENSA: #define __UINT_FAST16_FMTX__ "hX" +// XTENSA: #define __UINT_FAST16_FMTo__ "ho" +// XTENSA: #define __UINT_FAST16_FMTu__ "hu" +// XTENSA: #define __UINT_FAST16_FMTx__ "hx" +// XTENSA: #define __UINT_FAST16_MAX__ 65535 +// XTENSA: #define __UINT_FAST16_TYPE__ unsigned short +// XTENSA: #define __UINT_FAST32_FMTX__ "X" +// XTENSA: #define __UINT_FAST32_FMTo__ "o" +// XTENSA: #define __UINT_FAST32_FMTu__ "u" +// XTENSA: #define __UINT_FAST32_FMTx__ "x" +// XTENSA: #define __UINT_FAST32_MAX__ 4294967295U +// XTENSA: #define __UINT_FAST32_TYPE__ unsigned int +// XTENSA: #define __UINT_FAST64_FMTX__ "llX" +// XTENSA: #define __UINT_FAST64_FMTo__ "llo" +// XTENSA: #define __UINT_FAST64_FMTu__ "llu" +// XTENSA: #define __UINT_FAST64_FMTx__ "llx" +// XTENSA: #define __UINT_FAST64_MAX__ 18446744073709551615ULL +// XTENSA: #define __UINT_FAST64_TYPE__ long long unsigned int +// XTENSA: #define __UINT_FAST8_FMTX__ "hhX" +// XTENSA: #define __UINT_FAST8_FMTo__ "hho" +// XTENSA: #define __UINT_FAST8_FMTu__ "hhu" +// XTENSA: #define __UINT_FAST8_FMTx__ "hhx" +// XTENSA: #define __UINT_FAST8_MAX__ 255 +// XTENSA: #define __UINT_FAST8_TYPE__ unsigned char +// XTENSA: #define __UINT_LEAST16_FMTX__ "hX" +// XTENSA: #define __UINT_LEAST16_FMTo__ "ho" +// XTENSA: #define __UINT_LEAST16_FMTu__ "hu" +// XTENSA: #define __UINT_LEAST16_FMTx__ "hx" +// XTENSA: #define __UINT_LEAST16_MAX__ 65535 +// XTENSA: #define __UINT_LEAST16_TYPE__ unsigned short +// XTENSA: #define __UINT_LEAST32_FMTX__ "X" +// XTENSA: #define __UINT_LEAST32_FMTo__ "o" +// XTENSA: #define __UINT_LEAST32_FMTu__ "u" +// XTENSA: #define __UINT_LEAST32_FMTx__ "x" +// XTENSA: #define __UINT_LEAST32_MAX__ 4294967295U +// XTENSA: #define __UINT_LEAST32_TYPE__ unsigned int +// XTENSA: #define __UINT_LEAST64_FMTX__ "llX" +// XTENSA: #define __UINT_LEAST64_FMTo__ "llo" +// XTENSA: #define __UINT_LEAST64_FMTu__ "llu" +// XTENSA: #define __UINT_LEAST64_FMTx__ "llx" +// XTENSA: #define __UINT_LEAST64_MAX__ 18446744073709551615ULL +// XTENSA: #define __UINT_LEAST64_TYPE__ long long unsigned int +// XTENSA: #define __UINT_LEAST8_FMTX__ "hhX" +// XTENSA: #define __UINT_LEAST8_FMTo__ "hho" +// XTENSA: #define __UINT_LEAST8_FMTu__ "hhu" +// XTENSA: #define __UINT_LEAST8_FMTx__ "hhx" +// XTENSA: #define __UINT_LEAST8_MAX__ 255 +// XTENSA: #define __UINT_LEAST8_TYPE__ unsigned char +// XTENSA: #define __WCHAR_MAX__ 255 +// XTENSA: #define __WCHAR_TYPE__ unsigned char +// XTENSA: #define __WCHAR_UNSIGNED__ 1 +// XTENSA: #define __WCHAR_WIDTH__ 8 +// XTENSA: #define __WINT_MAX__ 4294967295U +// XTENSA: #define __WINT_TYPE__ unsigned int +// XTENSA: #define __WINT_UNSIGNED__ 1 +// XTENSA: #define __WINT_WIDTH__ 32 +// XTENSA: #define __XTENSA_EL__ 1 +// XTENSA: #define __XTENSA_WINDOWED_ABI__ 1 +// XTENSA: #define __XTENSA__ 1 +// XTENSA: #define __xtensa__ 1 + +// RUN: %clang_cc1 -E -dM -ffreestanding -triple=xtensa-esp-unknown-elf -mfast-int-min32 < /dev/null \ +// RUN: | FileCheck -match-full-lines -check-prefix=XTENSA_FAST32 %s +// XTENSA_FAST32: #define _ILP32 1 +// XTENSA_FAST32: #define __ATOMIC_ACQUIRE 2 +// XTENSA_FAST32: #define __ATOMIC_ACQ_REL 4 +// XTENSA_FAST32: #define __ATOMIC_CONSUME 1 +// XTENSA_FAST32: #define __ATOMIC_RELAXED 0 +// XTENSA_FAST32: #define __ATOMIC_RELEASE 3 +// XTENSA_FAST32: #define __ATOMIC_SEQ_CST 5 +// XTENSA_FAST32: #define __BIGGEST_ALIGNMENT__ 4 +// XTENSA_FAST32: #define __BITINT_MAXWIDTH__ 128 +// XTENSA_FAST32: #define __BOOL_WIDTH__ 8 +// XTENSA_FAST32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ +// XTENSA_FAST32: #define __CHAR16_TYPE__ unsigned short +// XTENSA_FAST32: #define __CHAR32_TYPE__ unsigned int +// XTENSA_FAST32: #define __CHAR_BIT__ 8 +// XTENSA_FAST32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 2 +// XTENSA_FAST32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 2 +// XTENSA_FAST32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 2 +// XTENSA_FAST32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 2 +// XTENSA_FAST32: #define __CLANG_ATOMIC_INT_LOCK_FREE 2 +// XTENSA_FAST32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1 +// XTENSA_FAST32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 2 +// XTENSA_FAST32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 2 +// XTENSA_FAST32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 2 +// XTENSA_FAST32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 2 +// XTENSA_FAST32: #define __CONSTANT_CFSTRINGS__ 1 +// XTENSA_FAST32: #define __DBL_DECIMAL_DIG__ 17 +// XTENSA_FAST32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324 +// XTENSA_FAST32: #define __DBL_DIG__ 15 +// XTENSA_FAST32: #define __DBL_EPSILON__ 2.2204460492503131e-16 +// XTENSA_FAST32: #define __DBL_HAS_DENORM__ 1 +// XTENSA_FAST32: #define __DBL_HAS_INFINITY__ 1 +// XTENSA_FAST32: #define __DBL_HAS_QUIET_NAN__ 1 +// XTENSA_FAST32: #define __DBL_MANT_DIG__ 53 +// XTENSA_FAST32: #define __DBL_MAX_10_EXP__ 308 +// XTENSA_FAST32: #define __DBL_MAX_EXP__ 1024 +// XTENSA_FAST32: #define __DBL_MAX__ 1.7976931348623157e+308 +// XTENSA_FAST32: #define __DBL_MIN_10_EXP__ (-307) +// XTENSA_FAST32: #define __DBL_MIN_EXP__ (-1021) +// XTENSA_FAST32: #define __DBL_MIN__ 2.2250738585072014e-308 +// XTENSA_FAST32: #define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__ +// XTENSA_FAST32: #define __ELF__ 1 +// XTENSA_FAST32: #define __FINITE_MATH_ONLY__ 0 +// XTENSA_FAST32: #define __FLT_DECIMAL_DIG__ 9 +// XTENSA_FAST32: #define __FLT_DENORM_MIN__ 1.40129846e-45F +// XTENSA_FAST32: #define __FLT_DIG__ 6 +// XTENSA_FAST32: #define __FLT_EPSILON__ 1.19209290e-7F +// XTENSA_FAST32: #define __FLT_HAS_DENORM__ 1 +// XTENSA_FAST32: #define __FLT_HAS_INFINITY__ 1 +// XTENSA_FAST32: #define __FLT_HAS_QUIET_NAN__ 1 +// XTENSA_FAST32: #define __FLT_MANT_DIG__ 24 +// XTENSA_FAST32: #define __FLT_MAX_10_EXP__ 38 +// XTENSA_FAST32: #define __FLT_MAX_EXP__ 128 +// XTENSA_FAST32: #define __FLT_MAX__ 3.40282347e+38F +// XTENSA_FAST32: #define __FLT_MIN_10_EXP__ (-37) +// XTENSA_FAST32: #define __FLT_MIN_EXP__ (-125) +// XTENSA_FAST32: #define __FLT_MIN__ 1.17549435e-38F +// XTENSA_FAST32: #define __FLT_RADIX__ 2 +// XTENSA_FAST32: #define __ILP32__ 1 +// XTENSA_FAST32: #define __INT16_C_SUFFIX__ +// XTENSA_FAST32: #define __INT16_FMTd__ "hd" +// XTENSA_FAST32: #define __INT16_FMTi__ "hi" +// XTENSA_FAST32: #define __INT16_MAX__ 32767 +// XTENSA_FAST32: #define __INT16_TYPE__ short +// XTENSA_FAST32: #define __INT32_C_SUFFIX__ +// XTENSA_FAST32: #define __INT32_FMTd__ "d" +// XTENSA_FAST32: #define __INT32_FMTi__ "i" +// XTENSA_FAST32: #define __INT32_MAX__ 2147483647 +// XTENSA_FAST32: #define __INT32_TYPE__ int +// XTENSA_FAST32: #define __INT64_C_SUFFIX__ LL +// XTENSA_FAST32: #define __INT64_FMTd__ "lld" +// XTENSA_FAST32: #define __INT64_FMTi__ "lli" +// XTENSA_FAST32: #define __INT64_MAX__ 9223372036854775807LL +// XTENSA_FAST32: #define __INT64_TYPE__ long long int +// XTENSA_FAST32: #define __INT8_C_SUFFIX__ +// XTENSA_FAST32: #define __INT8_FMTd__ "hhd" +// XTENSA_FAST32: #define __INT8_FMTi__ "hhi" +// XTENSA_FAST32: #define __INT8_MAX__ 127 +// XTENSA_FAST32: #define __INT8_TYPE__ signed char +// XTENSA_FAST32: #define __INTMAX_C_SUFFIX__ LL +// XTENSA_FAST32: #define __INTMAX_FMTd__ "lld" +// XTENSA_FAST32: #define __INTMAX_FMTi__ "lli" +// XTENSA_FAST32: #define __INTMAX_MAX__ 9223372036854775807LL +// XTENSA_FAST32: #define __INTMAX_TYPE__ long long int +// XTENSA_FAST32: #define __INTMAX_WIDTH__ 64 +// XTENSA_FAST32: #define __INTPTR_FMTd__ "d" +// XTENSA_FAST32: #define __INTPTR_FMTi__ "i" +// XTENSA_FAST32: #define __INTPTR_MAX__ 2147483647 +// XTENSA_FAST32: #define __INTPTR_TYPE__ int +// XTENSA_FAST32: #define __INTPTR_WIDTH__ 32 +// XTENSA_FAST32: #define __INT_FAST16_FMTd__ "d" +// XTENSA_FAST32: #define __INT_FAST16_FMTi__ "i" +// XTENSA_FAST32: #define __INT_FAST16_MAX__ 2147483647 +// XTENSA_FAST32: #define __INT_FAST16_TYPE__ int +// XTENSA_FAST32: #define __INT_FAST16_WIDTH__ 32 +// XTENSA_FAST32: #define __INT_FAST32_FMTd__ "d" +// XTENSA_FAST32: #define __INT_FAST32_FMTi__ "i" +// XTENSA_FAST32: #define __INT_FAST32_MAX__ 2147483647 +// XTENSA_FAST32: #define __INT_FAST32_TYPE__ int +// XTENSA_FAST32: #define __INT_FAST32_WIDTH__ 32 +// XTENSA_FAST32: #define __INT_FAST64_FMTd__ "lld" +// XTENSA_FAST32: #define __INT_FAST64_FMTi__ "lli" +// XTENSA_FAST32: #define __INT_FAST64_MAX__ 9223372036854775807LL +// XTENSA_FAST32: #define __INT_FAST64_TYPE__ long long int +// XTENSA_FAST32: #define __INT_FAST64_WIDTH__ 64 +// XTENSA_FAST32: #define __INT_FAST8_FMTd__ "d" +// XTENSA_FAST32: #define __INT_FAST8_FMTi__ "i" +// XTENSA_FAST32: #define __INT_FAST8_MAX__ 2147483647 +// XTENSA_FAST32: #define __INT_FAST8_TYPE__ int +// XTENSA_FAST32: #define __INT_FAST8_WIDTH__ 32 +// XTENSA_FAST32: #define __INT_LEAST16_FMTd__ "hd" +// XTENSA_FAST32: #define __INT_LEAST16_FMTi__ "hi" +// XTENSA_FAST32: #define __INT_LEAST16_MAX__ 32767 +// XTENSA_FAST32: #define __INT_LEAST16_TYPE__ short +// XTENSA_FAST32: #define __INT_LEAST16_WIDTH__ 16 +// XTENSA_FAST32: #define __INT_LEAST32_FMTd__ "d" +// XTENSA_FAST32: #define __INT_LEAST32_FMTi__ "i" +// XTENSA_FAST32: #define __INT_LEAST32_MAX__ 2147483647 +// XTENSA_FAST32: #define __INT_LEAST32_TYPE__ int +// XTENSA_FAST32: #define __INT_LEAST32_WIDTH__ 32 +// XTENSA_FAST32: #define __INT_LEAST64_FMTd__ "lld" +// XTENSA_FAST32: #define __INT_LEAST64_FMTi__ "lli" +// XTENSA_FAST32: #define __INT_LEAST64_MAX__ 9223372036854775807LL +// XTENSA_FAST32: #define __INT_LEAST64_TYPE__ long long int +// XTENSA_FAST32: #define __INT_LEAST64_WIDTH__ 64 +// XTENSA_FAST32: #define __INT_LEAST8_FMTd__ "hhd" +// XTENSA_FAST32: #define __INT_LEAST8_FMTi__ "hhi" +// XTENSA_FAST32: #define __INT_LEAST8_MAX__ 127 +// XTENSA_FAST32: #define __INT_LEAST8_TYPE__ signed char +// XTENSA_FAST32: #define __INT_LEAST8_WIDTH__ 8 +// XTENSA_FAST32: #define __INT_MAX__ 2147483647 +// XTENSA_FAST32: #define __INT_WIDTH__ 32 +// XTENSA_FAST32: #define __LDBL_DECIMAL_DIG__ 17 +// XTENSA_FAST32: #define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L +// XTENSA_FAST32: #define __LDBL_DIG__ 15 +// XTENSA_FAST32: #define __LDBL_EPSILON__ 2.2204460492503131e-16L +// XTENSA_FAST32: #define __LDBL_HAS_DENORM__ 1 +// XTENSA_FAST32: #define __LDBL_HAS_INFINITY__ 1 +// XTENSA_FAST32: #define __LDBL_HAS_QUIET_NAN__ 1 +// XTENSA_FAST32: #define __LDBL_MANT_DIG__ 53 +// XTENSA_FAST32: #define __LDBL_MAX_10_EXP__ 308 +// XTENSA_FAST32: #define __LDBL_MAX_EXP__ 1024 +// XTENSA_FAST32: #define __LDBL_MAX__ 1.7976931348623157e+308L +// XTENSA_FAST32: #define __LDBL_MIN_10_EXP__ (-307) +// XTENSA_FAST32: #define __LDBL_MIN_EXP__ (-1021) +// XTENSA_FAST32: #define __LDBL_MIN__ 2.2250738585072014e-308L +// XTENSA_FAST32: #define __LITTLE_ENDIAN__ 1 +// XTENSA_FAST32: #define __LLONG_WIDTH__ 64 +// XTENSA_FAST32: #define __LONG_LONG_MAX__ 9223372036854775807LL +// XTENSA_FAST32: #define __LONG_MAX__ 2147483647L +// XTENSA_FAST32: #define __LONG_WIDTH__ 32 +// XTENSA_FAST32: #define __NO_INLINE__ 1 +// XTENSA_FAST32: #define __NO_MATH_ERRNO__ 1 +// XTENSA_FAST32: #define __OBJC_BOOL_IS_BOOL 0 +// XTENSA_FAST32: #define __OPENCL_MEMORY_SCOPE_ALL_SVM_DEVICES 3 +// XTENSA_FAST32: #define __OPENCL_MEMORY_SCOPE_DEVICE 2 +// XTENSA_FAST32: #define __OPENCL_MEMORY_SCOPE_SUB_GROUP 4 +// XTENSA_FAST32: #define __OPENCL_MEMORY_SCOPE_WORK_GROUP 1 +// XTENSA_FAST32: #define __OPENCL_MEMORY_SCOPE_WORK_ITEM 0 +// XTENSA_FAST32: #define __ORDER_BIG_ENDIAN__ 4321 +// XTENSA_FAST32: #define __ORDER_LITTLE_ENDIAN__ 1234 +// XTENSA_FAST32: #define __ORDER_PDP_ENDIAN__ 3412 +// XTENSA_FAST32: #define __POINTER_WIDTH__ 32 +// XTENSA_FAST32: #define __PRAGMA_REDEFINE_EXTNAME 1 +// XTENSA_FAST32: #define __PTRDIFF_FMTd__ "d" +// XTENSA_FAST32: #define __PTRDIFF_FMTi__ "i" +// XTENSA_FAST32: #define __PTRDIFF_MAX__ 2147483647 +// XTENSA_FAST32: #define __PTRDIFF_TYPE__ int +// XTENSA_FAST32: #define __PTRDIFF_WIDTH__ 32 +// XTENSA_FAST32: #define __SCHAR_MAX__ 127 +// XTENSA_FAST32: #define __SHRT_MAX__ 32767 +// XTENSA_FAST32: #define __SHRT_WIDTH__ 16 +// XTENSA_FAST32: #define __SIG_ATOMIC_MAX__ 2147483647 +// XTENSA_FAST32: #define __SIG_ATOMIC_WIDTH__ 32 +// XTENSA_FAST32: #define __SIZEOF_DOUBLE__ 8 +// XTENSA_FAST32: #define __SIZEOF_FLOAT__ 4 +// XTENSA_FAST32: #define __SIZEOF_INT__ 4 +// XTENSA_FAST32: #define __SIZEOF_LONG_DOUBLE__ 8 +// XTENSA_FAST32: #define __SIZEOF_LONG_LONG__ 8 +// XTENSA_FAST32: #define __SIZEOF_LONG__ 4 +// XTENSA_FAST32: #define __SIZEOF_POINTER__ 4 +// XTENSA_FAST32: #define __SIZEOF_PTRDIFF_T__ 4 +// XTENSA_FAST32: #define __SIZEOF_SHORT__ 2 +// XTENSA_FAST32: #define __SIZEOF_SIZE_T__ 4 +// XTENSA_FAST32: #define __SIZEOF_WCHAR_T__ 1 +// XTENSA_FAST32: #define __SIZEOF_WINT_T__ 4 +// XTENSA_FAST32: #define __SIZE_FMTX__ "X" +// XTENSA_FAST32: #define __SIZE_FMTo__ "o" +// XTENSA_FAST32: #define __SIZE_FMTu__ "u" +// XTENSA_FAST32: #define __SIZE_FMTx__ "x" +// XTENSA_FAST32: #define __SIZE_MAX__ 4294967295U +// XTENSA_FAST32: #define __SIZE_TYPE__ unsigned int +// XTENSA_FAST32: #define __SIZE_WIDTH__ 32 +// XTENSA_FAST32: #define __STDC_HOSTED__ 0 +// XTENSA_FAST32: #define __STDC_UTF_16__ 1 +// XTENSA_FAST32: #define __STDC_UTF_32__ 1 +// XTENSA_FAST32: #define __STDC_VERSION__ 201710L +// XTENSA_FAST32: #define __STDC__ 1 +// XTENSA_FAST32: #define __UINT16_C_SUFFIX__ +// XTENSA_FAST32: #define __UINT16_FMTX__ "hX" +// XTENSA_FAST32: #define __UINT16_FMTo__ "ho" +// XTENSA_FAST32: #define __UINT16_FMTu__ "hu" +// XTENSA_FAST32: #define __UINT16_FMTx__ "hx" +// XTENSA_FAST32: #define __UINT16_MAX__ 65535 +// XTENSA_FAST32: #define __UINT16_TYPE__ unsigned short +// XTENSA_FAST32: #define __UINT32_C_SUFFIX__ U +// XTENSA_FAST32: #define __UINT32_FMTX__ "X" +// XTENSA_FAST32: #define __UINT32_FMTo__ "o" +// XTENSA_FAST32: #define __UINT32_FMTu__ "u" +// XTENSA_FAST32: #define __UINT32_FMTx__ "x" +// XTENSA_FAST32: #define __UINT32_MAX__ 4294967295U +// XTENSA_FAST32: #define __UINT32_TYPE__ unsigned int +// XTENSA_FAST32: #define __UINT64_C_SUFFIX__ ULL +// XTENSA_FAST32: #define __UINT64_FMTX__ "llX" +// XTENSA_FAST32: #define __UINT64_FMTo__ "llo" +// XTENSA_FAST32: #define __UINT64_FMTu__ "llu" +// XTENSA_FAST32: #define __UINT64_FMTx__ "llx" +// XTENSA_FAST32: #define __UINT64_MAX__ 18446744073709551615ULL +// XTENSA_FAST32: #define __UINT64_TYPE__ long long unsigned int +// XTENSA_FAST32: #define __UINT8_C_SUFFIX__ +// XTENSA_FAST32: #define __UINT8_FMTX__ "hhX" +// XTENSA_FAST32: #define __UINT8_FMTo__ "hho" +// XTENSA_FAST32: #define __UINT8_FMTu__ "hhu" +// XTENSA_FAST32: #define __UINT8_FMTx__ "hhx" +// XTENSA_FAST32: #define __UINT8_MAX__ 255 +// XTENSA_FAST32: #define __UINT8_TYPE__ unsigned char +// XTENSA_FAST32: #define __UINTMAX_C_SUFFIX__ ULL +// XTENSA_FAST32: #define __UINTMAX_FMTX__ "llX" +// XTENSA_FAST32: #define __UINTMAX_FMTo__ "llo" +// XTENSA_FAST32: #define __UINTMAX_FMTu__ "llu" +// XTENSA_FAST32: #define __UINTMAX_FMTx__ "llx" +// XTENSA_FAST32: #define __UINTMAX_MAX__ 18446744073709551615ULL +// XTENSA_FAST32: #define __UINTMAX_TYPE__ long long unsigned int +// XTENSA_FAST32: #define __UINTMAX_WIDTH__ 64 +// XTENSA_FAST32: #define __UINTPTR_FMTX__ "X" +// XTENSA_FAST32: #define __UINTPTR_FMTo__ "o" +// XTENSA_FAST32: #define __UINTPTR_FMTu__ "u" +// XTENSA_FAST32: #define __UINTPTR_FMTx__ "x" +// XTENSA_FAST32: #define __UINTPTR_MAX__ 4294967295U +// XTENSA_FAST32: #define __UINTPTR_TYPE__ unsigned int +// XTENSA_FAST32: #define __UINTPTR_WIDTH__ 32 +// XTENSA_FAST32: #define __UINT_FAST16_FMTX__ "X" +// XTENSA_FAST32: #define __UINT_FAST16_FMTo__ "o" +// XTENSA_FAST32: #define __UINT_FAST16_FMTu__ "u" +// XTENSA_FAST32: #define __UINT_FAST16_FMTx__ "x" +// XTENSA_FAST32: #define __UINT_FAST16_MAX__ 4294967295U +// XTENSA_FAST32: #define __UINT_FAST16_TYPE__ unsigned int +// XTENSA_FAST32: #define __UINT_FAST32_FMTX__ "X" +// XTENSA_FAST32: #define __UINT_FAST32_FMTo__ "o" +// XTENSA_FAST32: #define __UINT_FAST32_FMTu__ "u" +// XTENSA_FAST32: #define __UINT_FAST32_FMTx__ "x" +// XTENSA_FAST32: #define __UINT_FAST32_MAX__ 4294967295U +// XTENSA_FAST32: #define __UINT_FAST32_TYPE__ unsigned int +// XTENSA_FAST32: #define __UINT_FAST64_FMTX__ "llX" +// XTENSA_FAST32: #define __UINT_FAST64_FMTo__ "llo" +// XTENSA_FAST32: #define __UINT_FAST64_FMTu__ "llu" +// XTENSA_FAST32: #define __UINT_FAST64_FMTx__ "llx" +// XTENSA_FAST32: #define __UINT_FAST64_MAX__ 18446744073709551615ULL +// XTENSA_FAST32: #define __UINT_FAST64_TYPE__ long long unsigned int +// XTENSA_FAST32: #define __UINT_FAST8_FMTX__ "X" +// XTENSA_FAST32: #define __UINT_FAST8_FMTo__ "o" +// XTENSA_FAST32: #define __UINT_FAST8_FMTu__ "u" +// XTENSA_FAST32: #define __UINT_FAST8_FMTx__ "x" +// XTENSA_FAST32: #define __UINT_FAST8_MAX__ 4294967295U +// XTENSA_FAST32: #define __UINT_FAST8_TYPE__ unsigned int +// XTENSA_FAST32: #define __UINT_LEAST16_FMTX__ "hX" +// XTENSA_FAST32: #define __UINT_LEAST16_FMTo__ "ho" +// XTENSA_FAST32: #define __UINT_LEAST16_FMTu__ "hu" +// XTENSA_FAST32: #define __UINT_LEAST16_FMTx__ "hx" +// XTENSA_FAST32: #define __UINT_LEAST16_MAX__ 65535 +// XTENSA_FAST32: #define __UINT_LEAST16_TYPE__ unsigned short +// XTENSA_FAST32: #define __UINT_LEAST32_FMTX__ "X" +// XTENSA_FAST32: #define __UINT_LEAST32_FMTo__ "o" +// XTENSA_FAST32: #define __UINT_LEAST32_FMTu__ "u" +// XTENSA_FAST32: #define __UINT_LEAST32_FMTx__ "x" +// XTENSA_FAST32: #define __UINT_LEAST32_MAX__ 4294967295U +// XTENSA_FAST32: #define __UINT_LEAST32_TYPE__ unsigned int +// XTENSA_FAST32: #define __UINT_LEAST64_FMTX__ "llX" +// XTENSA_FAST32: #define __UINT_LEAST64_FMTo__ "llo" +// XTENSA_FAST32: #define __UINT_LEAST64_FMTu__ "llu" +// XTENSA_FAST32: #define __UINT_LEAST64_FMTx__ "llx" +// XTENSA_FAST32: #define __UINT_LEAST64_MAX__ 18446744073709551615ULL +// XTENSA_FAST32: #define __UINT_LEAST64_TYPE__ long long unsigned int +// XTENSA_FAST32: #define __UINT_LEAST8_FMTX__ "hhX" +// XTENSA_FAST32: #define __UINT_LEAST8_FMTo__ "hho" +// XTENSA_FAST32: #define __UINT_LEAST8_FMTu__ "hhu" +// XTENSA_FAST32: #define __UINT_LEAST8_FMTx__ "hhx" +// XTENSA_FAST32: #define __UINT_LEAST8_MAX__ 255 +// XTENSA_FAST32: #define __UINT_LEAST8_TYPE__ unsigned char +// XTENSA_FAST32: #define __WCHAR_MAX__ 255 +// XTENSA_FAST32: #define __WCHAR_TYPE__ unsigned char +// XTENSA_FAST32: #define __WCHAR_UNSIGNED__ 1 +// XTENSA_FAST32: #define __WCHAR_WIDTH__ 8 +// XTENSA_FAST32: #define __WINT_MAX__ 4294967295U +// XTENSA_FAST32: #define __WINT_TYPE__ unsigned int +// XTENSA_FAST32: #define __WINT_UNSIGNED__ 1 +// XTENSA_FAST32: #define __WINT_WIDTH__ 32 +// XTENSA_FAST32: #define __XTENSA_EL__ 1 +// XTENSA_FAST32: #define __XTENSA_WINDOWED_ABI__ 1 +// XTENSA_FAST32: #define __XTENSA__ 1 +// XTENSA_FAST32: #define __xtensa__ 1 From 2fabfc2b89f7b186c412d51229274a0d34217b13 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Thu, 31 Aug 2023 23:33:08 +0300 Subject: [PATCH 177/261] esp/ci: Makes use of MacOS codesign scripts from external repo --- .gitlab-ci.yml | 2 +- .universal-toolchain-release.yml | 80 +++++++++++--------------------- 2 files changed, 27 insertions(+), 55 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 8601675f3b7fd4..644da08a100ff6 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,7 @@ stages: - build - pack - - sign + - macos_codesign - private_deploy - test - public_deploy diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 4628e486d6e4c2..baf1891c4b73d6 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -31,14 +31,14 @@ ${ARCHIVE_TOOL} ${ARCHIVE_NAME} esp-clang/ mkdir -p ${DISTRO_DIR} mv ${ARCHIVE_NAME} ${DISTRO_DIR}/ - echo "${ARCHIVE_NAME}" > ${DISTRO_DIR}/file_${PLATFORM_NAME} + echo "${ARCHIVE_NAME}" > ${DISTRO_DIR}/dist_name_${PLATFORM_NAME} # Pack libs to be used for Rust, Go etc. .package_libs: &package_libs | eval ${ARCHIVE_TOOL} ${LIBS_ARCHIVE_NAME} esp-clang/lib/clang/${CLANG_VER}/include esp-clang/lib/lib{clang,LLVM}* ${LIBS_PACK_EXTRA_PATHS:-} mkdir -p ${DISTRO_DIR} mv ${LIBS_ARCHIVE_NAME} ${DISTRO_DIR}/ - echo "${LIBS_ARCHIVE_NAME}" > ${DISTRO_DIR}/file_libs-${PLATFORM_NAME} + echo "${LIBS_ARCHIVE_NAME}" > ${DISTRO_DIR}/dist_name_libs-${PLATFORM_NAME} .get_binutils: &get_binutils | git clone -b ${BINUTILS_REF} --single-branch ${GITLAB_SSH_SERVER}/idf/${BINUTILS_REPO}.git @@ -150,7 +150,7 @@ build_x86_64-w64-mingw32: - !reference [.use_ci_tools, script] - !reference [.add_gitlab_key, script] # get ARCHIVE_NAME for Linux release. Modify vars to make get_release_name working properly - - CLANG_LINUX_ARCHIVE=$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) + - CLANG_LINUX_ARCHIVE=$(cat ${DIST_DIR}/dist_name_${PLATFORM_NAME_LINUX}) # unpack x86_64-linux-gnu toolchain to re-use it as native Clang for Windows build - mkdir -p esp-clang-${PLATFORM_NAME_LINUX} - ${UNARCHIVE_TOOL_LINUX} ${DIST_DIR}/${CLANG_LINUX_ARCHIVE} -C esp-clang-${PLATFORM_NAME_LINUX} @@ -208,7 +208,7 @@ build_newlib: ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" script: # get ARCHIVE_NAME for Linux release. - - CLANG_ARCHIVE=$PWD/${DIST_DIR}/$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) + - CLANG_ARCHIVE=$PWD/${DIST_DIR}/$(cat ${DIST_DIR}/dist_name_${PLATFORM_NAME_LINUX}) - mkdir -p ${DOWNLOADS_DIR} - pushd ${DOWNLOADS_DIR} - *get_xtensa_overlays @@ -252,7 +252,7 @@ build_compiler-rt: script: - LLVM_PROJECT_PATH=$PWD # get ARCHIVE_NAME for Linux release. - - CLANG_ARCHIVE=$PWD/${DIST_DIR}/$(cat ${DIST_DIR}/file_${PLATFORM_NAME_LINUX}) + - CLANG_ARCHIVE=$PWD/${DIST_DIR}/$(cat ${DIST_DIR}/dist_name_${PLATFORM_NAME_LINUX}) - NEWLIB_ARCHIVE=$PWD/${DIST_DIR}/esp-clang-newlib-overlay.${ARCHIVE_EXT_NEWLIB} - mkdir -p ${DOWNLOADS_DIR} - pushd ${DOWNLOADS_DIR} @@ -414,56 +414,29 @@ test_x86_64-linux-gnu: # run testsuite for esp32 - ./run_esp32_tests.sh 2>&1 > ${BUILD_PATH}/tests.log -.macos_codesign: &macos_codesign - stage: sign - tags: [ "darwin", "amd64" ] +macos_codesign: + stage: macos_codesign + when: on_success resource_group: macos_codesign + tags: [ "darwin", "codesign" ] + # list all jobs that produces macos distros + needs: [ pack_x86_64-apple-darwin, pack_aarch64-apple-darwin ] artifacts: paths: - - ${DIST_DIR}/ - when: always - expire_in: 3 day + - ${DIST_DIR} variables: - KEYCHAIN_NAME: "llvm.keychain" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" - ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" + # directory with distro archives + DIST_ART_DIR: ${DIST_DIR} + # command to unarchive distro + ARCHIVE_TOOL: ${ARCHIVE_TOOL_MACOS} + # command to unarchive distro + UNARCHIVE_TOOL: ${UNARCHIVE_TOOL_MACOS} + # URL to macos codesign repo + NOTARIZATION_SCRIPTS_GIT: "${CI_SERVER_PROTOCOL}://gitlab-ci-token:${CI_JOB_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/espressif/macos_codesign_notarization.git" script: - - *get_release_name - - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} - - rm -rf ${DIST_DIR} - - TOOLCHAIN_PATH=$PWD/esp-clang - - echo $MACOS_CERTIFICATE | base64 --decode > $PWD/certificate.p12 - - security create-keychain -p $KEYCHAIN_PWD $KEYCHAIN_NAME || true - - security import $PWD/certificate.p12 -k $KEYCHAIN_NAME -P $MACOS_CERTIFICATE_PWD -T /usr/bin/codesign - - security set-key-partition-list -S apple-tool:,apple:,codesign -s -k $KEYCHAIN_PWD $KEYCHAIN_NAME - - security list-keychains -d user -s ~/Library/Keychains/$KEYCHAIN_NAME - - security find-identity -v -p codesigning - - security unlock-keychain -p $KEYCHAIN_PWD $KEYCHAIN_NAME - - /usr/bin/codesign -v --force --options runtime -s $IDENTITY_ID $TOOLCHAIN_PATH/bin/* $TOOLCHAIN_PATH/lib/*.dylib - - security delete-keychain $KEYCHAIN_NAME - - codesign -dvv $TOOLCHAIN_PATH/bin/* - - DISTRO_DIR=$PWD/${DIST_DIR} - - *package_toolchain - - *package_libs - after_script: - - security find-identity -v - - security delete-keychain $KEYCHAIN_NAME - - security find-identity -v - -sign_x86_64-apple-darwin: - extends: .macos_codesign - needs: - - pack_x86_64-apple-darwin - variables: - PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" - -sign_aarch64-apple-darwin: - extends: .macos_codesign - needs: - - pack_aarch64-apple-darwin - variables: - PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" + - git clone -q --depth=1 ${NOTARIZATION_SCRIPTS_GIT} -b ${CI_COMMIT_REF_NAME} || + git clone -q --depth=1 ${NOTARIZATION_SCRIPTS_GIT} + - ./macos_codesign_notarization/run.sh upload_to_http: stage: private_deploy @@ -480,7 +453,7 @@ upload_to_http: script: - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" # List of archives - - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) + - FILES=$(find ${DIST_DIR} -name dist_name_\* -exec cat {} \+) - cd ${DIST_DIR} - ls -l $FILES - scp ${FILES} ${HTTP_UPLOAD_DIR}/ct-ng/llvm-builds @@ -505,15 +478,14 @@ upload_to_github: - job: pack_arm-linux-gnueabihf - job: pack_aarch64-linux-gnu - job: pack_x86_64-w64-mingw32 - - job: sign_x86_64-apple-darwin - - job: sign_aarch64-apple-darwin + - job: macos_codesign before_script: [] script: - ls -l dist*/ - git remote add github ${GH_REPO_HTTPS} - hub release show ${TAG} || { echo "Please create a release on GitHub with ${TAG} tag at first"; exit 1; } # List of archives - - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) + - FILES=$(find ${DIST_DIR} -name dist_name_\* -exec cat {} \+) - cd ${DIST_DIR} - ls -l $FILES # Upload archives From 62e6e725c271ea1124a6bf5f40eedc457f3d2ae1 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 1 Sep 2023 14:33:04 +0300 Subject: [PATCH 178/261] esp/ci: Use gold linker for Linux builds --- .universal-toolchain-release.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index baf1891c4b73d6..4d14ff174bb558 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -88,6 +88,7 @@ - BUILD_PATH=$PWD/${BUILD_DIR} - mkdir -p ${BUILD_PATH} - export USE_PARALLEL_LINK_JOBS=2 + - export USE_PARALLEL_COMPILE_JOBS=2 # build Clang toolchain w/o newlib - ${BUILD_TOOLCHAIN_CMD} --llvm-path=${LLVM_PROJECT_PATH} --gcc-toolchains-path=${ESP_GCC_TOOLCHAIN_DIST_BASE} --binutils-path=${BINUTILS_PATH} @@ -120,6 +121,7 @@ GCC_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" GCC_ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" BUILD_TOOLCHAIN_CMD: "./build-toolchain.sh" + USE_LINKER: "gold" build_x86_64-linux-gnu: extends: .build_linux-gnu_template From 625fc0ec501ab502b5d7e3ad78984866a6d9c3bb Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 1 Sep 2023 16:29:07 +0300 Subject: [PATCH 179/261] esp/ci: Adds cmake err/log artifacts --- .universal-toolchain-release.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 4d14ff174bb558..2d2260df9b10c1 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -61,6 +61,8 @@ - ${BUILD_DIR}/lld-tests.log - ${BUILD_DIR}/tests.log - ${BUILD_DIR}/build.log + - "${BUILD_DIR}/**/CMakeError.log" + - "${BUILD_DIR}/**/CMakeOutput.log" when: always expire_in: 1 day variables: From 737368f5fe3a28fdca4986dcc6538b52c2c71a8d Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 12 Oct 2023 01:53:02 +0300 Subject: [PATCH 180/261] [lld][Xtensa] Fix sections placements. --- lld/ELF/Writer.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index 8a08b0fcc90dbc..914bc1139145e3 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -1471,6 +1471,10 @@ static void sortSection(OutputSection &osec, if (auto *isd = dyn_cast(b)) sortISDBySectionOrder(isd, order, osec.flags & SHF_EXECINSTR); + if (config->emachine == EM_XTENSA) { + osec.sort([](InputSectionBase *s) { return s->name.contains(".literal") ? 0 : 1; }); + } + if (script->hasSectionsCommand) return; From e7cd296234ab1874484ff5c410177994986cf77c Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 18 Oct 2023 17:29:11 +0300 Subject: [PATCH 181/261] [lld][Xtensa] Improve literal sections placement. Improve sections sort to place literal section closer to code section which uses literals. Fix l32r relocation check. --- lld/ELF/Arch/Xtensa.cpp | 10 +++++--- lld/ELF/Writer.cpp | 55 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 60 insertions(+), 5 deletions(-) diff --git a/lld/ELF/Arch/Xtensa.cpp b/lld/ELF/Arch/Xtensa.cpp index fef4d2c06b8995..301901ab89990d 100644 --- a/lld/ELF/Arch/Xtensa.cpp +++ b/lld/ELF/Arch/Xtensa.cpp @@ -127,10 +127,12 @@ void Xtensa::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { // Look at the instruction to determine how to do the relocation. uint8_t opcode = loc[0] & 0x0f; if (opcode == 0b0001) { // RI16 format: l32r - uint64_t val = dest - ((p + 3) & (uint64_t)0xfffffffc); - checkInt(loc, static_cast(val) >> 2, 16, rel); - checkAlignment(loc, val, 4, rel); - write16le(loc + 1, static_cast(val) >> 2); + int64_t val = dest - ((p + 3) & (uint64_t)0xfffffffc); + if ((val < -262144 || val > -4)) + reportRangeError(loc, rel, Twine(static_cast(val)), -262141, + -4); + checkAlignment(loc, static_cast(val), 4, rel); + write16le(loc + 1, val >> 2); } else if (opcode == 0b0101) { // call0, call4, call8, call12 (CALL format) uint64_t val = dest - ((p + 4) & (uint64_t)0xfffffffc); checkInt(loc, static_cast(val) >> 2, 18, rel); diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index 914bc1139145e3..816369c0106cba 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -31,6 +31,7 @@ #include "llvm/Support/TimeProfiler.h" #include "llvm/Support/xxhash.h" #include +#include #define DEBUG_TYPE "lld" @@ -1446,6 +1447,58 @@ sortISDBySectionOrder(InputSectionDescription *isd, isd->sections.push_back(isec); } +// Sort Xtensa literal sections in OutputSection. For each literal section we try +// to find by name text(code) section, which uses these literals. The literal +// section should always be placed before code section. +// Also we try to place literal section just before code section. +static void sortSectionXtensa(OutputSection &osec) { + for (SectionCommand *b : osec.commands) { + if (auto *isd = dyn_cast(b)) { + std::map orderedNames; + SmallVector, 0> orderedSections; + int sidx = 0; + + for (InputSection *isec : isd->sections) { + if (orderedNames.count(isec->name.str())) { + orderedSections.push_back({isec, orderedNames[isec->name.str()]}); + continue; + } + //Check if current section contains literals + if (isec->name.contains(".literal")) { + std::string literalName = isec->name.str(); + std::size_t pos = literalName.find(".literal"); + std::string textName; + // Reconstructing text(code) section name by literal section name + if (pos == 0) { + textName = ".text"; + } else { + textName = literalName.substr(0, pos); + } + textName += literalName.substr(pos + 8, std::string::npos); + if (orderedNames.count(textName)) { + int textIdx = orderedNames[textName]; + int literalIdx = textIdx - 1; + orderedSections.push_back({isec, literalIdx}); + orderedNames[isec->name.str()] = literalIdx; + } else { + orderedSections.push_back({isec, sidx}); + orderedNames[isec->name.str()] = sidx; + } + } else { + orderedSections.push_back({isec, sidx}); + orderedNames[isec->name.str()] = sidx; + } + sidx += 2; + } + + llvm::sort(orderedSections, llvm::less_second()); + isd->sections.clear(); + for (std::pair p : orderedSections) + isd->sections.push_back(p.first); + } + } +} + static void sortSection(OutputSection &osec, const DenseMap &order) { StringRef name = osec.name; @@ -1472,7 +1525,7 @@ static void sortSection(OutputSection &osec, sortISDBySectionOrder(isd, order, osec.flags & SHF_EXECINSTR); if (config->emachine == EM_XTENSA) { - osec.sort([](InputSectionBase *s) { return s->name.contains(".literal") ? 0 : 1; }); + sortSectionXtensa(osec); } if (script->hasSectionsCommand) From 74617d47440c54d8493fd47a9e3accc022f7b5e2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 31 Oct 2023 00:51:37 +0300 Subject: [PATCH 182/261] [lld][Xtensa] Fix loop instruction relocation --- lld/ELF/Arch/Xtensa.cpp | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/lld/ELF/Arch/Xtensa.cpp b/lld/ELF/Arch/Xtensa.cpp index 301901ab89990d..9734eedc672744 100644 --- a/lld/ELF/Arch/Xtensa.cpp +++ b/lld/ELF/Arch/Xtensa.cpp @@ -105,9 +105,31 @@ static inline bool isRRI8Branch(uint8_t *loc) { // instructions: bgeui, bltui if ((loc[0] & 0b1011'1111) == 0b1011'0110) return true; - // instruction: bt - if ((loc[0] & 0b0111'1111) == 0b0111'0110) - return true; + if ((loc[0] & 0b0111'1111) == 0b0111'0110) { + // instruction: bf + if ((loc[1] & 0b1111'0000) == 0b0000'0000) + return true; + // instruction: bt + if ((loc[1] & 0b1111'0000) == 0b0001'0000) + return true; + } + // some other instruction + return false; +} + +static inline bool isLoop(uint8_t *loc) { + // instructions: loop, loopgtz, loopnez + if ((loc[0] & 0b1111'1111) == 0b0111'0110) { + // instruction: loop + if ((loc[1] & 0b1111'0000) == 0b1000'0000) + return true; + // instruction: loopgtz + if ((loc[1] & 0b1111'0000) == 0b1010'0000) + return true; + // instruction: loopnez + if ((loc[1] & 0b1111'0000) == 0b1001'0000) + return true; + } // some other instruction return false; } @@ -151,6 +173,10 @@ void Xtensa::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { uint64_t v = val - 4; checkInt(loc, static_cast(v), 8, rel); loc[2] = v & 0xff; + } else if (isLoop(loc)) { // loop instructions + uint64_t v = val - 4; + checkUInt(loc, v, 8, rel); + loc[2] = v & 0xff; } else if ((loc[0] & 0b1000'1111) == 0b1000'1100) { // RI16 format: beqz.n, bnez.n uint64_t v = val - 4; checkUInt(loc, v, 6, rel); From 52bc4da8f099799c6a3bfebd905986f73a3c428b Mon Sep 17 00:00:00 2001 From: Ayke van Laethem Date: Tue, 24 Oct 2023 15:15:10 +0200 Subject: [PATCH 183/261] [Xtensa] Fix Clang builtins include directory This fixes https://github.com/espressif/llvm-project/issues/83 In short, it adjusts the include path logic to include the builtins directory as long as `-nostdinc` or `-nobuiltininc` isn't specified. Previously, the builtins directory would not be included if either the GCC installation wasn't found, or `-nostdlibinc` was specified (both of which aren't related to the builtins directory). --- clang/lib/Driver/ToolChains/Xtensa.cpp | 41 +++++++++++++++----------- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index 3a2231e9dd6ead..e7d01eefda6f64 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -132,29 +132,34 @@ Tool *XtensaToolChain::buildAssembler() const { void XtensaToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { - if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc) || - DriverArgs.hasArg(options::OPT_nostdlibinc)) + if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc)) return; - if (!getDriver().SysRoot.empty()) { - SmallString<128> Dir(getDriver().SysRoot); - llvm::sys::path::append(Dir, "include"); - addSystemInclude(DriverArgs, CC1Args, Dir.str()); - } else if (GCCInstallation.isValid()) { - SmallString<128> Path1(getDriver().ResourceDir); - llvm::sys::path::append(Path1, "include"); - SmallString<128> Path2(GCCToolchainDir); - llvm::sys::path::append(Path2, GCCToolchainName, "sys-include"); - SmallString<128> Path3(GCCToolchainDir); - llvm::sys::path::append(Path3, GCCToolchainName, "include"); - - const StringRef Paths[] = {Path1, Path2, Path3}; - addSystemIncludes(DriverArgs, CC1Args, Paths); - } else { - SmallString<128> Dir(computeSysRoot()); + if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) { + SmallString<128> Dir(getDriver().ResourceDir); llvm::sys::path::append(Dir, "include"); addSystemInclude(DriverArgs, CC1Args, Dir.str()); } + + if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) { + if (!getDriver().SysRoot.empty()) { + SmallString<128> Dir(getDriver().SysRoot); + llvm::sys::path::append(Dir, "include"); + addSystemInclude(DriverArgs, CC1Args, Dir.str()); + } else if (GCCInstallation.isValid()) { + SmallString<128> Path1(GCCToolchainDir); + llvm::sys::path::append(Path1, GCCToolchainName, "sys-include"); + SmallString<128> Path2(GCCToolchainDir); + llvm::sys::path::append(Path2, GCCToolchainName, "include"); + + const StringRef Paths[] = {Path1, Path2}; + addSystemIncludes(DriverArgs, CC1Args, Paths); + } else { + SmallString<128> Dir(computeSysRoot()); + llvm::sys::path::append(Dir, "include"); + addSystemInclude(DriverArgs, CC1Args, Dir.str()); + } + } } void XtensaToolChain::addLibStdCxxIncludePaths( From 6ca30e54ad94cb3b02ea9af52bb259d2c491b41a Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Fri, 1 Dec 2023 20:12:18 +0300 Subject: [PATCH 184/261] [Utils][UpdateTestChecks] Add Xtensa support to update_llc_test_checks.py --- llvm/utils/UpdateTestChecks/asm.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/llvm/utils/UpdateTestChecks/asm.py b/llvm/utils/UpdateTestChecks/asm.py index f0c456a1648df4..fd144f592fb7ef 100644 --- a/llvm/utils/UpdateTestChecks/asm.py +++ b/llvm/utils/UpdateTestChecks/asm.py @@ -256,6 +256,13 @@ class string: flags=(re.M | re.S), ) +ASM_FUNCTION_XTENSA_RE = re.compile( + r'^_?(?P[^.:]+):[ \t]*#+[ \t]*@"?(?P=func)"?\n\s?\.?(cfi_startproc\s)?# %bb.0:.*?\n' + r'(?P.*?)\n' + r'^\.Lfunc_end\d+:\n', # Match the end label + flags=(re.M | re.S) +) + SCRUB_X86_SHUFFLES_RE = re.compile( r"^(\s*\w+) [^#\n]+#+ ((?:[xyz]mm\d+|mem)( \{%k\d+\}( \{z\})?)? = .*)$", flags=re.M ) @@ -524,6 +531,15 @@ def scrub_asm_loongarch(asm, args): asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r"", asm) return asm +def scrub_asm_xtensa(asm, args): + # Scrub runs of whitespace out of the assembly, but leave the leading + # whitespace in place. + asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm) + # Expand the tabs used for indentation. + asm = string.expandtabs(asm, 2) + # Strip trailing whitespace. + asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm) + return asm # Returns a tuple of a scrub function and a function regex. Scrub function is # used to alter function body in some way, for example, remove trailing spaces. @@ -582,6 +598,7 @@ def get_run_handler(triple): "nvptx": (scrub_asm_nvptx, ASM_FUNCTION_NVPTX_RE), "loongarch32": (scrub_asm_loongarch, ASM_FUNCTION_LOONGARCH_RE), "loongarch64": (scrub_asm_loongarch, ASM_FUNCTION_LOONGARCH_RE), + "xtensa": (scrub_asm_xtensa, ASM_FUNCTION_XTENSA_RE) } handler = None best_prefix = "" From 69184d94a102bdd71ef18cdc7a014ca3ed7df63a Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 8 Nov 2023 00:08:56 +0300 Subject: [PATCH 185/261] [Xtensa] Fix wchar type. Add absent IR passes. --- clang/lib/Basic/Targets/Xtensa.h | 2 +- clang/test/Preprocessor/init.c | 18 ++++++++---------- llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp | 5 ++++- llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll | 6 +++--- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index 0e7d054ff47a8f..1d777f9014d121 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -45,7 +45,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { SizeType = UnsignedInt; PtrDiffType = SignedInt; IntPtrType = SignedInt; - WCharType = UnsignedChar; + WCharType = SignedInt; WIntType = UnsignedInt; UseZeroLengthBitfieldAlignment = true; MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index 814d366dbc7372..a2c175a5eae875 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -2846,7 +2846,7 @@ // XTENSA: #define __SIZEOF_PTRDIFF_T__ 4 // XTENSA: #define __SIZEOF_SHORT__ 2 // XTENSA: #define __SIZEOF_SIZE_T__ 4 -// XTENSA: #define __SIZEOF_WCHAR_T__ 1 +// XTENSA: #define __SIZEOF_WCHAR_T__ 4 // XTENSA: #define __SIZEOF_WINT_T__ 4 // XTENSA: #define __SIZE_FMTX__ "X" // XTENSA: #define __SIZE_FMTo__ "o" @@ -2951,10 +2951,9 @@ // XTENSA: #define __UINT_LEAST8_FMTx__ "hhx" // XTENSA: #define __UINT_LEAST8_MAX__ 255 // XTENSA: #define __UINT_LEAST8_TYPE__ unsigned char -// XTENSA: #define __WCHAR_MAX__ 255 -// XTENSA: #define __WCHAR_TYPE__ unsigned char -// XTENSA: #define __WCHAR_UNSIGNED__ 1 -// XTENSA: #define __WCHAR_WIDTH__ 8 +// XTENSA: #define __WCHAR_MAX__ 2147483647 +// XTENSA: #define __WCHAR_TYPE__ int +// XTENSA: #define __WCHAR_WIDTH__ 32 // XTENSA: #define __WINT_MAX__ 4294967295U // XTENSA: #define __WINT_TYPE__ unsigned int // XTENSA: #define __WINT_UNSIGNED__ 1 @@ -3149,7 +3148,7 @@ // XTENSA_FAST32: #define __SIZEOF_PTRDIFF_T__ 4 // XTENSA_FAST32: #define __SIZEOF_SHORT__ 2 // XTENSA_FAST32: #define __SIZEOF_SIZE_T__ 4 -// XTENSA_FAST32: #define __SIZEOF_WCHAR_T__ 1 +// XTENSA_FAST32: #define __SIZEOF_WCHAR_T__ 4 // XTENSA_FAST32: #define __SIZEOF_WINT_T__ 4 // XTENSA_FAST32: #define __SIZE_FMTX__ "X" // XTENSA_FAST32: #define __SIZE_FMTo__ "o" @@ -3254,10 +3253,9 @@ // XTENSA_FAST32: #define __UINT_LEAST8_FMTx__ "hhx" // XTENSA_FAST32: #define __UINT_LEAST8_MAX__ 255 // XTENSA_FAST32: #define __UINT_LEAST8_TYPE__ unsigned char -// XTENSA_FAST32: #define __WCHAR_MAX__ 255 -// XTENSA_FAST32: #define __WCHAR_TYPE__ unsigned char -// XTENSA_FAST32: #define __WCHAR_UNSIGNED__ 1 -// XTENSA_FAST32: #define __WCHAR_WIDTH__ 8 +// XTENSA_FAST32: #define __WCHAR_MAX__ 2147483647 +// XTENSA_FAST32: #define __WCHAR_TYPE__ int +// XTENSA_FAST32: #define __WCHAR_WIDTH__ 32 // XTENSA_FAST32: #define __WINT_MAX__ 4294967295U // XTENSA_FAST32: #define __WINT_TYPE__ unsigned int // XTENSA_FAST32: #define __WINT_UNSIGNED__ 1 diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 564c57d06c1a97..910b9401c64159 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -130,7 +130,10 @@ bool XtensaPassConfig::addInstSelector() { return false; } -void XtensaPassConfig::addIRPasses() { addPass(createAtomicExpandPass()); } +void XtensaPassConfig::addIRPasses() { + addPass(createAtomicExpandPass()); + TargetPassConfig::addIRPasses(); +} void XtensaPassConfig::addPreRegAlloc() { addPass(createXtensaHardwareLoops()); diff --git a/llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll b/llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll index 9d339f00e539bd..ff5c5389d83e0c 100644 --- a/llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll +++ b/llvm/test/CodeGen/Xtensa/ee-intrinsics-loop.ll @@ -69,7 +69,7 @@ for.body: ; preds = %entry, %for.body ; CHECK-NEXT: ee.stf.128.ip f11, f10, f9, f8, a8, 16 ; CHECK-NEXT: ee.stf.128.ip f8, f8, f8, f8, a8, 16 ; CHECK-NEXT: ee.stf.128.xp f8, f8, f8, f8, a9, a8 -; CHECK-NEXT: movi.n a10, 0 +; CHECK-NEXT: movi.n a10, 32 ; CHECK-NEXT: movi.n a11, 10 ; CHECK-NEXT: .LBB0_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 @@ -79,8 +79,8 @@ for.body: ; preds = %entry, %for.body ; CHECK-NEXT: ee.vmulas.s16.accx.ld.xp.qup q4, a8, a9, q0, q4, q2, q3 ; CHECK-NEXT: ee.ld.128.usar.xp q4, a8, a9 ; CHECK-NEXT: ee.vmulas.s16.accx.ld.ip.qup q3, a8, 16, q0, q3, q4, q2 -; CHECK-NEXT: addi.n a10, a10, 1 -; CHECK-NEXT: bnei a10, 32, .LBB0_1 +; CHECK-NEXT: addi.n a10, a10, -1 +; CHECK-NEXT: bnez a10, .LBB0_1 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: movi.n a8, 0 ; CHECK-NEXT: wur.sar_byte a8 From 6be8cfcfc2f93cfca7db982af97783e5a11a432b Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Mar 2024 01:49:52 +0300 Subject: [PATCH 186/261] [Xtensa][Tests]: Fix call abi test. --- clang/test/CodeGen/xtensa-abi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/test/CodeGen/xtensa-abi.c b/clang/test/CodeGen/xtensa-abi.c index 25b1fbd2d1b97c..e858f8e88044d8 100644 --- a/clang/test/CodeGen/xtensa-abi.c +++ b/clang/test/CodeGen/xtensa-abi.c @@ -25,4 +25,4 @@ void callee_struct_a16b_2(struct S16 a, int b) {} void callee_struct_a16b_3(int a, struct S16 b) {} -// CHECK: define dso_local void @callee_struct_a16b_3(i32 noundef %a, %struct.S16* noundef byval(%struct.S16) align 16 %b) +// CHECK: define dso_local void @callee_struct_a16b_3(i32 noundef %a, ptr noundef byval(%struct.S16) align 16 %b) From 2e39012710847b52b8c074637eec15db24679b31 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 12 Dec 2023 16:39:28 +0800 Subject: [PATCH 187/261] esp/ci: Modify ci script to support Clang release 17.0.4 --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 644da08a100ff6..471d4af4e3282c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -12,7 +12,7 @@ variables: # move all these to CI/CD settings REL_SFX: "llvm" - CLANG_VER: "16" + CLANG_VER: "17" GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" NEWLIB_REF: "esp-4.1.0_20230425" From bed848c59cfa14829072c2b25373a50098ba633e Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 12 Dec 2023 11:53:04 +0800 Subject: [PATCH 188/261] esp/ci: Bump binutils version to esp-2.39.0_20230208 --- .gitlab-ci.yml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 471d4af4e3282c..909fa159782014 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -16,10 +16,7 @@ variables: GCC_REL_NAME: "esp-2022r1" GCC_REL_VER: "gcc11_2_0" NEWLIB_REF: "esp-4.1.0_20230425" - # TODO: LLVM-248. Upgrade binutils above 2.36 when Clang will be upgraded to >=17.x - # which supports 'zicsr' or 'zifencei' RISCV extensions via '-march=' - # https://www.spinics.net/lists/stable/msg645015.html - BINUTILS_REF: "esp-2022r1-binutils" + BINUTILS_REF: "esp-2.39.0_20230208" XTENSA_OVERLAYS_REF: "master" LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230425" XTENSA_CLANG_TOOLCHAIN_REF: "esp-16.0.0-20230516" From 2834506327f1a00b08472a2da3537f8bcf302106 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 12 Dec 2023 12:21:56 +0800 Subject: [PATCH 189/261] esp/ci: Use GNU components from GCC release 12.2.0_20230208 --- .gitlab-ci.yml | 10 ++++++++-- .universal-toolchain-release.yml | 14 ++++++++++---- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 909fa159782014..b92d9c4558eca7 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -13,8 +13,7 @@ variables: # move all these to CI/CD settings REL_SFX: "llvm" CLANG_VER: "17" - GCC_REL_NAME: "esp-2022r1" - GCC_REL_VER: "gcc11_2_0" + GCC_REL_VER: "12.2.0_20230208" NEWLIB_REF: "esp-4.1.0_20230425" BINUTILS_REF: "esp-2.39.0_20230208" XTENSA_OVERLAYS_REF: "master" @@ -29,6 +28,13 @@ variables: PLATFORM_NAME_MACOS: "macos" PLATFORM_NAME_MACOS_ARM64: "macos-arm64" + GCC_PLATFORM_NAME_LINUX: "i686-linux-gnu" + GCC_PLATFORM_NAME_LINUX_ARMHF: "arm-linux-gnueabihf" + GCC_PLATFORM_NAME_LINUX_ARM64: "aarch64-linux-gnu" + GCC_PLATFORM_NAME_WIN: "i686-w64-mingw32" + GCC_PLATFORM_NAME_MACOS: "x86_64-apple-darwin" + GCC_PLATFORM_NAME_MACOS_ARM64: "aarch64-apple-darwin" + ARCHIVE_TOOL_LINUX: "tar -cJf" UNARCHIVE_TOOL_LINUX: "tar -xf" ARCHIVE_EXT_LINUX: "tar.xz" diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 2d2260df9b10c1..6279866f2aa113 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -18,12 +18,12 @@ "esp32s3") for ((i = 0; i < ${#XTENSA_CPUS[@]}; i++)); do XTENSA_CPU=${XTENSA_CPUS[$i]} - GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${GCC_ARCHIVE_EXT} - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} + GCC_TOOLCHAIN_ARCH=xtensa-${XTENSA_CPU}-elf-${GCC_REL_VER}-${GCC_PLATFORM_NAME}.${GCC_ARCHIVE_EXT} + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-${GCC_REL_VER}/${GCC_TOOLCHAIN_ARCH} ${GCC_UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} done; - GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_REL_NAME}-${PLATFORM_NAME}.${GCC_ARCHIVE_EXT} - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/${GCC_REL_NAME}/${GCC_TOOLCHAIN_ARCH} + GCC_TOOLCHAIN_ARCH=riscv32-esp-elf-${GCC_REL_VER}-${GCC_PLATFORM_NAME}.${GCC_ARCHIVE_EXT} + wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-${GCC_REL_VER}/${GCC_TOOLCHAIN_ARCH} ${GCC_UNARCHIVE_TOOL} ${GCC_TOOLCHAIN_ARCH} # Pack the toolchain @@ -130,6 +130,7 @@ build_x86_64-linux-gnu: variables: CONF_HOST: "x86_64-linux-gnu" PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" + GCC_PLATFORM_NAME: "${GCC_PLATFORM_NAME_LINUX}" build_arm-linux-gnueabihf: extends: .build_linux-gnu_template @@ -137,6 +138,7 @@ build_arm-linux-gnueabihf: variables: CONF_HOST: "arm-linux-gnueabihf" PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARMHF}" + GCC_PLATFORM_NAME: "${GCC_PLATFORM_NAME_LINUX_ARMHF}" build_aarch64-linux-gnu: extends: .build_linux-gnu_template @@ -144,6 +146,7 @@ build_aarch64-linux-gnu: variables: CONF_HOST: "aarch64-linux-gnu" PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" + GCC_PLATFORM_NAME: "${GCC_PLATFORM_NAME_LINUX_ARM64}" build_x86_64-w64-mingw32: extends: .build_template @@ -166,6 +169,7 @@ build_x86_64-w64-mingw32: variables: CONF_HOST: "x86_64-w64-mingw32" PLATFORM_NAME: "${PLATFORM_NAME_WIN}" + GCC_PLATFORM_NAME: "${GCC_PLATFORM_NAME_WIN}" ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" GCC_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" @@ -186,12 +190,14 @@ build_x86_64-apple-darwin: variables: CONF_HOST: "x86_64-apple-darwin21.1" PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" + GCC_PLATFORM_NAME: "${GCC_PLATFORM_NAME_MACOS}" build_aarch64-apple-darwin: extends: .build_apple-darwin_template variables: CONF_HOST: "aarch64-apple-darwin21.1" PLATFORM_NAME: "${PLATFORM_NAME_MACOS_ARM64}" + GCC_PLATFORM_NAME: "${GCC_PLATFORM_NAME_MACOS_ARM64}" build_newlib: stage: build From 53f83504a0c044e376a304b3fcc8606991912354 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 12 Dec 2023 12:38:59 +0800 Subject: [PATCH 190/261] [Toolchain][RISCV]: Add support for ISA 2.1 compliant multilib naming --- clang/lib/Driver/ToolChains/Gnu.cpp | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index e8187332c89d15..20be92f1322fb1 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1852,10 +1852,13 @@ static void findRISCVBareMetalMultilibs(const Driver &D, // currently only support the set of multilibs like riscv-gnu-toolchain does. // TODO: support MULTILIB_REUSE constexpr RiscvMultilib RISCVMultilibSet[] = { - {"rv32i", "ilp32"}, {"rv32im", "ilp32"}, {"rv32iac", "ilp32"}, - {"rv32imc", "ilp32"}, - {"rv32imac", "ilp32"}, {"rv32imafc", "ilp32f"}, {"rv64imac", "lp64"}, - {"rv64imafdc", "lp64d"}}; + {"rv32i", "ilp32"}, {"rv32im", "ilp32"}, {"rv32iac", "ilp32"}, + {"rv32imc", "ilp32"}, {"rv32imac", "ilp32"}, {"rv32imafc", "ilp32f"}, + {"rv64imac", "lp64"}, {"rv64imafdc", "lp64d"}, + // Add ISA 2.1 naming variants to support more modern GCC installations + {"rv32i_zicsr_zifencei", "ilp32"}, {"rv32im_zicsr_zifencei", "ilp32"}, {"rv32iac_zicsr_zifencei", "ilp32"}, + {"rv32imc_zicsr_zifencei", "ilp32"}, {"rv32imac_zicsr_zifencei", "ilp32"}, {"rv32imafc_zicsr_zifencei", "ilp32f"}, + {"rv64imac_zicsr_zifencei", "lp64"}, {"rv64imafdc_zicsr_zifencei", "lp64d"}}; std::vector Ms; From 3bbeb620699761a59fe726a1be065b3ecca8ea29 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 12 Dec 2023 13:10:14 +0800 Subject: [PATCH 191/261] esp/ci: Remove legacy release CI code --- .gitlab-ci.yml | 5 -- .legacy-release.yml | 164 -------------------------------------------- 2 files changed, 169 deletions(-) delete mode 100644 .legacy-release.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b92d9c4558eca7..4e11284b1b001c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -112,8 +112,3 @@ before_script: include: - local: .universal-toolchain-release.yml - rules: - - if: $ESP_CLANG_LEGACY_RELEASE != "true" - - local: .legacy-release.yml - rules: - - if: $ESP_CLANG_LEGACY_RELEASE == "true" diff --git a/.legacy-release.yml b/.legacy-release.yml deleted file mode 100644 index 2042369e9049d7..00000000000000 --- a/.legacy-release.yml +++ /dev/null @@ -1,164 +0,0 @@ - -.get_release_name_legacy: &get_release_name_legacy | - # using annotated tags - REL_NUM=$(git describe --abbrev=7) - REL_SFX="llvm15_0_0" - REL_NAME=${CONF_TARGET}-${REL_SFX}-${REL_NUM}-${PLATFORM_NAME} - ARCHIVE_NAME=${REL_NAME}.${ARCHIVE_EXT} - echo "PLATFORM_NAME: $PLATFORM_NAME" - echo "REL_NUM: $REL_NUM" - echo "REL_NAME: $REL_NAME" - echo "ARCHIVE_NAME: $ARCHIVE_NAME" - -.get_gcc_toolchain_legacy: &get_gcc_toolchain_legacy | - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/${XTENSA_GCC_TOOLCHAIN} - ${UNARCHIVE_TOOL} ${XTENSA_GCC_TOOLCHAIN} - if [[ "$XTENSA_GCC_TOOLCHAIN" == *"linux-amd64"* ]]; then - cp -r xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} - else - mv xtensa-esp32-elf ${XTENSA_CLANG_TOOLCHAIN} - wget --no-verbose https://dl.espressif.com/github_assets/espressif/crosstool-NG/releases/download/esp-2021r2-patch3/xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz - tar -xf xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz - fi - export GCC_ESP32_LINUX_TOOLCHAIN="xtensa-esp32-elf" - -.package_toolchain_legacy: &package_toolchain_legacy | - ${ARCHIVE_TOOL} ${ARCHIVE_NAME} ${XTENSA_CLANG_TOOLCHAIN}/ - mkdir -p ${DIST_DIR} - mv ${ARCHIVE_NAME} ${DIST_DIR}/ - echo "${ARCHIVE_NAME}" > ${DIST_DIR}/file_${PLATFORM_NAME}_${CONF_TARGET} - -.build_template_legacy: - stage: build - tags: [ "amd64", "build" ] - artifacts: - paths: - - ${DIST_DIR}/ - when: always - expire_in: 10 day - variables: - XTENSA_CLANG_TOOLCHAIN_REF: "release_esp32_clang_15.0.0_gcc_8.4.0" - GCC_REL_NAME: "gcc8_4_0-esp-2021r2-patch3" - script: - - *get_release_name_legacy - - *get_gcc_toolchain_legacy - - !reference [.fix_origin_remote_for_public, script] - - !reference [.get_clang_toolchain_build_scripts, script] - - ${BUILD_TOOLCHAIN_CMD} "${XTENSA_CLANG_TOOLCHAIN}" - - *package_toolchain_legacy - -linux_amd64_build: - extends: .build_template_legacy - variables: - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-amd64.tar.gz" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux.sh" - -linux_arm64_build: - extends: .build_template_legacy - image: ${CROSS_ARM_IMAGE} - variables: - PLATFORM_NAME: "${PLATFORM_NAME_LINUX_ARM64}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-linux-arm64.tar.gz" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-linux-arm64.sh" - -win64_build: - extends: .build_template_legacy - variables: - PLATFORM_NAME: "${PLATFORM_NAME_WIN}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_WIN}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_WIN}" - ARCHIVE_EXT: "${ARCHIVE_EXT_WIN}" - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-win64.zip" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-win.sh" - -macos_amd64_build: - extends: .build_template_legacy - variables: - PLATFORM_NAME: "${PLATFORM_NAME_MACOS}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_MACOS}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_MACOS}" - ARCHIVE_EXT: "${ARCHIVE_EXT_MACOS}" - XTENSA_GCC_TOOLCHAIN: "xtensa-esp32-elf-${GCC_REL_NAME}-macos.tar.gz" - BUILD_TOOLCHAIN_CMD: "./build-toolchain-macos.sh" - -linux_amd64_testsuite: - stage: test - tags: [ "amd64", "build" ] - needs: - - job: linux_amd64_build - variables: - PLATFORM_NAME: "${PLATFORM_NAME_LINUX}" - ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - LLVM_GCC_TESTSUITE_REF: "feature/ci_llvm_multitarget_crt_tests" - script: - - *get_release_name_legacy - - ${UNARCHIVE_TOOL} ${DIST_DIR}/${ARCHIVE_NAME} - - # getting testsuite - - git clone -b ${LLVM_GCC_TESTSUITE_REF} --depth 1 $GITLAB_SSH_SERVER/idf/${LLVM_TESTSUITE_REPO}.git - - # preparing testsuite - - export PATH=${PWD}/${XTENSA_CLANG_TOOLCHAIN}/bin/:$PATH - - cd ${LLVM_TESTSUITE_REPO} - - # qemu - - ./qemu_esp32_install.sh - - # run testsuite for esp32 - - ./run_esp32_tests.sh - - # run testsuite for compiler_rt library - - ./run_esp32_crt_tests.sh ../$XTENSA_CLANG_TOOLCHAIN - -upload_to_http_legacy: - stage: private_deploy - when: manual - allow_failure: true - tags: [ "deploy", "shiny" ] - variables: - # force the fetch strategy to clean old archives up in dist/ dir - GIT_STRATEGY: fetch - before_script: - - !reference [.use_ci_tools, script] - script: - - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" - # List of archives - - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) - - cd ${DIST_DIR} - - scp ${FILES} ${HTTP_UPLOAD_DIR}/ct-ng/llvm-builds - # Show info - - echo -e "\nArchives were published there:\n\n$(for n in ${FILES}; do echo "${HTTP_PUBLIC_DIR}/ct-ng/llvm-builds/${n}"; done)\n" - -upload_to_github_legacy: - stage: public_deploy - when: manual - allow_failure: true - only: - - tags - tags: [ "amd64", "internet" ] - image: espressif/github-hub:2 - variables: - GIT_STRATEGY: fetch - GITHUB_TOKEN: "${GH_TOKEN}" - GITHUB_REPO: "${GH_REPO_HTTPS}" - TAG: "${CI_COMMIT_TAG}" - before_script: [] - script: - - ls -l dist*/ - - git remote add github ${GH_REPO_HTTPS} - - hub release show ${TAG} || { echo "Please create a release on GitHub with ${TAG} tag at first"; exit 1; } - # List of archives - - FILES=$(find ${DIST_DIR} -name file_\* -exec cat {} \+) - - cd ${DIST_DIR} - - ls -l $FILES - # Upload archives - - for n in ${FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done From df7b3ac2790bd949c8dcde2e43bba0da057e7462 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Mar 2024 14:44:20 +0300 Subject: [PATCH 192/261] [Xtensa][RISCV] Fix multilib support Fix multilib support for Espressif RISCV and Xtensa chips. Fix multilib tests. --- clang/lib/Driver/ToolChains/Gnu.cpp | 121 +++++++++++----------------- 1 file changed, 48 insertions(+), 73 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index 20be92f1322fb1..ef3e9e87667d31 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1862,45 +1862,28 @@ static void findRISCVBareMetalMultilibs(const Driver &D, std::vector Ms; - if (TargetTriple.getVendor() == llvm::Triple::Espressif) - Ms.emplace_back(MultilibBuilder()); - if (TargetTriple.getVendor() == llvm::Triple::Espressif) { - Ms.emplace_back(MultilibBuilder()); - Ms.emplace_back(MultilibBuilder("no-rtti") - .flag("-fno-rtti") - .flag("-frtti", /*Disallow=*/true)); + for (auto Element : RISCVMultilibSet) { + // multilib path rule is ${march}/${mabi} + Ms.emplace_back( + MultilibBuilder( + (Twine(Element.march) + "/" + Twine(Element.mabi)).str()) + .flag(Twine("-march=", Element.march).str()) + .flag(Twine("-mabi=", Element.mabi).str())); } - for (auto Element : RISCVMultilibSet) { - if (TargetTriple.getVendor() == llvm::Triple::Espressif) { - // multilib path rule is ${march}/${mabi} - Ms.emplace_back( - MultilibBuilder( - (Twine(Element.march) + "/" + Twine(Element.mabi)).str()) - .flag(Twine("-march=", Element.march).str()) - .flag(Twine("-mabi=", Element.mabi).str())); - /* no-rtti version for every ${march}/${mabi} */ - Ms.emplace_back( - MultilibBuilder( - (Twine(Element.march) + "/" + Twine(Element.mabi) + "/no-rtti").str()) - .flag(Twine("-march=", Element.march).str()) - .flag(Twine("-mabi=", Element.mabi).str()) - .flag("-fno-rtti") - .flag("-frtti", /*Disallow=*/true)); - } else { - // multilib path rule is ${march}/${mabi} - Ms.emplace_back( - MultilibBuilder( - (Twine(Element.march) + "/" + Twine(Element.mabi)).str()) - .flag(Twine("-march=", Element.march).str()) - .flag(Twine("-mabi=", Element.mabi).str())); - } + MultilibSet RISCVMultilibs; + if (TargetTriple.getVendor() == llvm::Triple::Espressif) { + MultilibBuilder NoRTTI = MultilibBuilder("/no-rtti").flag("-fno-rtti"); + RISCVMultilibs = MultilibSetBuilder() + .Either(Ms) + .Maybe(NoRTTI) + .makeMultilibSet() + .FilterOut(NonExistent); + } else { + RISCVMultilibs = + MultilibSetBuilder().Either(Ms).makeMultilibSet().FilterOut( + NonExistent); } - MultilibSet RISCVMultilibs = - MultilibSetBuilder() - .Either(Ms) - .makeMultilibSet() - .FilterOut(NonExistent); if (TargetTriple.getVendor() == llvm::Triple::Espressif) { RISCVMultilibs.setFilePathsCallback([](const Multilib &M) { @@ -1932,8 +1915,8 @@ static void findRISCVBareMetalMultilibs(const Driver &D, if (TargetTriple.getVendor() == llvm::Triple::Espressif) { addMultilibFlag( - Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, true), "frtti", - Flags); + Args.hasFlag(options::OPT_fno_rtti, options::OPT_frtti, false), + "-fno-rtti", Flags); } if (selectRISCVMultilib(RISCVMultilibs, MArch, Flags, @@ -1984,49 +1967,41 @@ static void findRISCVMultilibs(const Driver &D, } static void findXtensaMultilibs(const Driver &D, - const llvm::Triple &TargetTriple, StringRef Path, - const ArgList &Args, DetectedMultilibs &Result) { + const llvm::Triple &TargetTriple, + StringRef Path, const ArgList &Args, + DetectedMultilibs &Result) { + FilterNonExistent NonExistent(Path, "/crtbegin.o", D.getVFS()); - MultilibSet XtensaMultilibs = MultilibSet(); StringRef cpu = Args.getLastArgValue(options::OPT_mcpu_EQ, "esp32"); bool IsESP32 = cpu.equals("esp32"); - XtensaMultilibs.push_back(Multilib()); - XtensaMultilibs.push_back(MultilibBuilder("no-rtti", {}, {}) - .flag("-fno-rtti") - .flag("-frtti", /*Disallow=*/true) - .makeMultilib()); + Multilib::flags_list Flags; - if (IsESP32) { - XtensaMultilibs.push_back(MultilibBuilder("esp32-psram", {}, {}) - .flag("-mfix-esp32-psram-cache-issue") - .makeMultilib()); + addMultilibFlag( + Args.hasFlag(options::OPT_fno_rtti, options::OPT_frtti, false), + "-fno-rtti", Flags); - XtensaMultilibs.push_back(MultilibBuilder("esp32-psram/no-rtti", {}, {}) - .flag("-mfix-esp32-psram-cache-issue") - .flag("-fno-rtti") - .flag("-frtti", /*Disallow=*/true) - .makeMultilib()); - } + addMultilibFlag( + IsESP32 && Args.hasFlag(options::OPT_mfix_esp32_psram_cache_issue, + options::OPT_mfix_esp32_psram_cache_issue, false), + "-mfix-esp32-psram-cache-issue", Flags); - std::string cpu_name = cpu.str(); - XtensaMultilibs - .setFilePathsCallback([cpu_name](const Multilib &M) { - return std::vector( - {M.gccSuffix(), - "/../../../../xtensa-" + cpu_name + "-elf/lib" + M.gccSuffix()}); - }); + MultilibBuilder NoRTTI = MultilibBuilder("/no-rtti").flag("-fno-rtti"); + MultilibBuilder FixPSRAM = + MultilibBuilder("/esp32-psram").flag("-mfix-esp32-psram-cache-issue"); - Multilib::flags_list Flags; - addMultilibFlag( - Args.hasFlag(options::OPT_frtti, options::OPT_fno_rtti, true), "frtti", - Flags); - - if (IsESP32) - addMultilibFlag(Args.hasFlag(options::OPT_mfix_esp32_psram_cache_issue, - options::OPT_mfix_esp32_psram_cache_issue, - false), - "mfix-esp32-psram-cache-issue", Flags); + MultilibSet XtensaMultilibs = MultilibSetBuilder() + .Maybe(FixPSRAM) + .Maybe(NoRTTI) + .makeMultilibSet() + .FilterOut(NonExistent); + + std::string cpu_name = cpu.str(); + XtensaMultilibs.setFilePathsCallback([cpu_name](const Multilib &M) { + return std::vector( + {M.gccSuffix(), + "/../../../../xtensa-" + cpu_name + "-elf/lib" + M.gccSuffix()}); + }); if (XtensaMultilibs.select(Flags, Result.SelectedMultilibs)) Result.Multilibs = XtensaMultilibs; From 9133085b4eb6599941ee8cd9585f4fc9c84d679c Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Thu, 28 Dec 2023 10:37:20 +0300 Subject: [PATCH 193/261] esp/ci: Split MacOS sign job (one per arch) to fit into artifacts size limit --- .universal-toolchain-release.yml | 33 +++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/.universal-toolchain-release.yml b/.universal-toolchain-release.yml index 6279866f2aa113..cd899df8a7ba00 100644 --- a/.universal-toolchain-release.yml +++ b/.universal-toolchain-release.yml @@ -424,13 +424,39 @@ test_x86_64-linux-gnu: # run testsuite for esp32 - ./run_esp32_tests.sh 2>&1 > ${BUILD_PATH}/tests.log -macos_codesign: +sign_pack_x86_64-apple-darwin: stage: macos_codesign when: on_success resource_group: macos_codesign tags: [ "darwin", "codesign" ] # list all jobs that produces macos distros - needs: [ pack_x86_64-apple-darwin, pack_aarch64-apple-darwin ] + needs: + - job: pack_x86_64-apple-darwin + artifacts: + paths: + - ${DIST_DIR} + variables: + # directory with distro archives + DIST_ART_DIR: ${DIST_DIR} + # command to unarchive distro + ARCHIVE_TOOL: ${ARCHIVE_TOOL_MACOS} + # command to unarchive distro + UNARCHIVE_TOOL: ${UNARCHIVE_TOOL_MACOS} + # URL to macos codesign repo + NOTARIZATION_SCRIPTS_GIT: "${CI_SERVER_PROTOCOL}://gitlab-ci-token:${CI_JOB_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/espressif/macos_codesign_notarization.git" + script: + - git clone -q --depth=1 ${NOTARIZATION_SCRIPTS_GIT} -b ${CI_COMMIT_REF_NAME} || + git clone -q --depth=1 ${NOTARIZATION_SCRIPTS_GIT} + - ./macos_codesign_notarization/run.sh + +sign_aarch64-apple-darwin: + stage: macos_codesign + when: on_success + resource_group: macos_codesign + tags: [ "darwin", "codesign" ] + # list all jobs that produces macos distros + needs: + - job: pack_aarch64-apple-darwin artifacts: paths: - ${DIST_DIR} @@ -488,7 +514,8 @@ upload_to_github: - job: pack_arm-linux-gnueabihf - job: pack_aarch64-linux-gnu - job: pack_x86_64-w64-mingw32 - - job: macos_codesign + - job: sign_pack_x86_64-apple-darwin + - job: sign_aarch64-apple-darwin before_script: [] script: - ls -l dist*/ From 47c7839bf4fd7a8a9491eaf18db3d129df823886 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Thu, 28 Dec 2023 18:05:23 +0300 Subject: [PATCH 194/261] esp/ci: Adds GH PR workflow to run tests --- .github/workflows/esp-clang-tests.yml | 40 +++++++++++++++++++++++ .github/workflows/esp-llvm-tests.yml | 46 +++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) create mode 100644 .github/workflows/esp-clang-tests.yml create mode 100644 .github/workflows/esp-llvm-tests.yml diff --git a/.github/workflows/esp-clang-tests.yml b/.github/workflows/esp-clang-tests.yml new file mode 100644 index 00000000000000..a982ca753c3831 --- /dev/null +++ b/.github/workflows/esp-clang-tests.yml @@ -0,0 +1,40 @@ +name: Clang Tests + +permissions: + contents: read + +on: + workflow_dispatch: + push: + ignore-forks: true + branches: + - '**_release_**' + paths: + - 'clang/**' + - '.github/workflows/esp-clang-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!llvm/**' + pull_request: + ignore-forks: true + branches: + - '**_release_**' + paths: + - 'clang/**' + - '.github/workflows/esp-clang-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!llvm/**' + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + +jobs: + check_clang: + if: github.repository_owner == 'espressif' + name: Test clang + uses: ./.github/workflows/llvm-project-tests.yml + with: + build_target: check-clang + projects: clang diff --git a/.github/workflows/esp-llvm-tests.yml b/.github/workflows/esp-llvm-tests.yml new file mode 100644 index 00000000000000..42143b2695ec51 --- /dev/null +++ b/.github/workflows/esp-llvm-tests.yml @@ -0,0 +1,46 @@ +name: LLVM Tests + +permissions: + contents: read + +on: + workflow_dispatch: + push: + ignore-forks: true + branches: + - '**_release_**' + paths: + - 'llvm/**' + - '.github/workflows/esp-llvm-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + pull_request: + ignore-forks: true + branches: + - '**_release_**' + paths: + - 'llvm/**' + - '.github/workflows/esp-llvm-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + +jobs: + check_all: + if: github.repository_owner == 'espressif' + name: Test llvm,clang + uses: ./.github/workflows/llvm-project-tests.yml + with: + build_target: check-all + projects: clang + + check_lld: + if: github.repository_owner == 'espressif' + name: Test lld + uses: ./.github/workflows/llvm-project-tests.yml + with: + build_target: check-lld + projects: lld From 39a455affb7a3bbc01b38720a9c3a95eb1558308 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 29 Dec 2023 11:11:30 +0300 Subject: [PATCH 195/261] [Toolchain][Xtensa][Tests] Fix calling clang++ in tests --- clang/test/Driver/xtensa-toolchain.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/xtensa-toolchain.c b/clang/test/Driver/xtensa-toolchain.c index 77f23c284cf526..234495b0cda0ae 100644 --- a/clang/test/Driver/xtensa-toolchain.c +++ b/clang/test/Driver/xtensa-toolchain.c @@ -103,7 +103,7 @@ // C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" // C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" -// RUN: %clang++ %s -### -no-canonical-prefixes \ +// RUN: %clangxx %s -### -no-canonical-prefixes \ // RUN: -target xtensa-esp-elf -mcpu=esp32 -stdlib=libstdc++ --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ // RUN: | FileCheck -check-prefix=CXX-XTENSA-ESP32-BAREMETAL %s @@ -113,7 +113,7 @@ // CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" // CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" -// RUN: %clang++ %s -### -no-canonical-prefixes \ +// RUN: %clangxx %s -### -no-canonical-prefixes \ // RUN: -target xtensa-esp-elf -mcpu=esp32 -stdlib=libstdc++ --rtlib=platform \ // RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree \ // RUN: --sysroot=%S/Inputs/multilib_xtensa_tree/xtensa-esp32-elf 2>&1 \ From e5e8a12c4a9e4813c84e9336ca0c183d232c875e Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 11 Sep 2023 16:19:32 +0000 Subject: [PATCH 196/261] [Xtensa] Add definition of S3 output registers. Xtensa S3 DSP instructions are coded using explicit register allocation. However, some instructions miss RegState:Define flag for output registers. This leads MachineVerifier to raise errors. This commit adds missing definitions. --- llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 9 +++++++++ llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td | 4 ++++ .../lib/Target/Xtensa/XtensaS3ISelLowering.cpp | 18 +++++++++--------- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index 6ec817e30ddd3a..d49849a6819b7d 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -61,6 +61,15 @@ BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // Reserve stack pointer. Reserved.set(Xtensa::SP); + //Reserve QR regs + Reserved.set(Xtensa::Q0); + Reserved.set(Xtensa::Q1); + Reserved.set(Xtensa::Q2); + Reserved.set(Xtensa::Q3); + Reserved.set(Xtensa::Q4); + Reserved.set(Xtensa::Q5); + Reserved.set(Xtensa::Q6); + Reserved.set(Xtensa::Q7); return Reserved; } diff --git a/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td index 557463fd461c42..b384c8f42c426e 100644 --- a/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td @@ -113,6 +113,8 @@ def EE_CMUL_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, let Inst{10-6} = 0x3; let Inst{5-4} = sel4{1-0}; let Inst{3-0} = as{3-0}; + + let Constraints = "$asr = $as"; } let usesCustomInserter = 1 in @@ -140,6 +142,8 @@ def EE_CMUL_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, let Inst{7-6} = 0x0; let Inst{5-4} = sel4{1-0}; let Inst{3-0} = as{3-0}; + + let Constraints = "$asr = $as"; } let usesCustomInserter = 1 in diff --git a/llvm/lib/Target/Xtensa/XtensaS3ISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaS3ISelLowering.cpp index 301d225c6442e5..181a5ae59ee319 100644 --- a/llvm/lib/Target/Xtensa/XtensaS3ISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaS3ISelLowering.cpp @@ -39,7 +39,7 @@ MachineBasicBlock *XtensaTargetLowering::EmitDSPInstrWithCustomInserter( assert(QYVal < 8 && "Unexpected value of ee_andq first argument, it must " "be in range [0,7]"); BuildMI(*MBB, MI, DL, TII.get(Opc)) - .addReg(Xtensa::Q0 + QAVal) + .addReg(Xtensa::Q0 + QAVal, RegState::Define) .addReg(Xtensa::Q0 + QXVal) .addReg(Xtensa::Q0 + QYVal); @@ -56,8 +56,8 @@ MachineBasicBlock *XtensaTargetLowering::EmitDSPInstrWithCustomInserter( const TargetRegisterClass *RC = getRegClassFor(MVT::i32); unsigned R1 = MRI.createVirtualRegister(RC); BuildMI(*MBB, MI, DL, TII.get(Opc)) - .addReg(Xtensa::Q0 + QAVal) - .addReg(R1, RegState::Undef) + .addReg(Xtensa::Q0 + QAVal, RegState::Define) + .addReg(R1, RegState::Define) .addReg(AX.getReg()); MI.eraseFromParent(); @@ -79,7 +79,7 @@ MachineBasicBlock *XtensaTargetLowering::EmitDSPInstrWithCustomInserter( "must be in range [0,7]"); MachineOperand &SEL4 = MI.getOperand(3); BuildMI(*MBB, MI, DL, TII.get(Opc)) - .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QZVal, RegState::Define) .addReg(Xtensa::Q0 + QXVal) .addReg(Xtensa::Q0 + QYVal) .addImm(SEL4.getImm()); @@ -110,9 +110,9 @@ MachineBasicBlock *XtensaTargetLowering::EmitDSPInstrWithCustomInserter( "argument, it must be in range [0,7]"); MachineOperand &SEL4 = MI.getOperand(5); BuildMI(*MBB, MI, DL, TII.get(Opc)) - .addReg(Xtensa::Q0 + QUVal) - .addReg(R1, RegState::Undef) - .addReg(Xtensa::Q0 + QZVal) + .addReg(Xtensa::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(Xtensa::Q0 + QZVal, RegState::Define) .addReg(AS.getReg()) .addReg(Xtensa::Q0 + QXVal) .addReg(Xtensa::Q0 + QYVal) @@ -144,8 +144,8 @@ MachineBasicBlock *XtensaTargetLowering::EmitDSPInstrWithCustomInserter( "argument, it must be in range [0,7]"); MachineOperand &SEL4 = MI.getOperand(5); BuildMI(*MBB, MI, DL, TII.get(Opc)) - .addReg(R1, RegState::Undef) - .addReg(Xtensa::Q0 + QZVal) + .addReg(R1, RegState::Define) + .addReg(Xtensa::Q0 + QZVal, RegState::Define) .addReg(Xtensa::Q0 + QVVal) .addReg(AS.getReg()) .addReg(Xtensa::Q0 + QXVal) From bf252f408ad3867ba39576f11ba7567f61802af9 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:02 +0000 Subject: [PATCH 197/261] [Xtensa] Add Boolean Extension feature Boolean Extension support consists of: - v1i1 boolean vector type backed by BR boolean register class - calling convection for boolean variables - boolean instructions implementing logical operators - truncation and zero-extension operations for conversion to scalars - register spill and fill logic --- clang/lib/Basic/Targets/Xtensa.cpp | 3 + clang/lib/Basic/Targets/Xtensa.h | 3 +- clang/lib/CodeGen/Targets/Xtensa.cpp | 7 ++ llvm/lib/Target/Xtensa/XtensaCallingConv.td | 5 + .../lib/Target/Xtensa/XtensaFrameLowering.cpp | 21 +++- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 41 +++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 11 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 75 +++++++++++-- llvm/lib/Target/Xtensa/XtensaOperators.td | 4 +- llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 101 +++++++++++++++++- llvm/lib/Target/Xtensa/XtensaRegisterInfo.h | 6 +- llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 9 +- .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 2 +- 13 files changed, 265 insertions(+), 23 deletions(-) diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp index 3bc8cc531069d6..3c00be659c092c 100644 --- a/clang/lib/Basic/Targets/Xtensa.cpp +++ b/clang/lib/Basic/Targets/Xtensa.cpp @@ -75,6 +75,7 @@ bool XtensaTargetInfo::hasFeature(StringRef Feature) const { return llvm::StringSwitch(Feature) .Case("fp", HasFP) .Case("windowed", HasWindowed) + .Case("bool", HasBoolean) .Default(false); } @@ -84,6 +85,8 @@ bool XtensaTargetInfo::handleTargetFeatures(std::vector &Features, for (const auto &Feature : Features) { if (Feature == "+fp") HasFP = true; + else if (Feature == "+bool") + HasBoolean = true; else if (Feature == "+windowed") HasWindowed = true; } diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index 1d777f9014d121..c969f182c63d69 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -33,6 +33,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { std::string CPU; bool HasFP = false; bool HasWindowed = false; + bool HasBoolean = false; public: XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &) @@ -49,7 +50,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { WIntType = UnsignedInt; UseZeroLengthBitfieldAlignment = true; MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; - resetDataLayout("e-m:e-p:32:32-i64:64-i128:128-n32"); + resetDataLayout("e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32"); } void getTargetDefines(const LangOptions &Opts, diff --git a/clang/lib/CodeGen/Targets/Xtensa.cpp b/clang/lib/CodeGen/Targets/Xtensa.cpp index f3e0170dda6d26..f53039e5e90a56 100644 --- a/clang/lib/CodeGen/Targets/Xtensa.cpp +++ b/clang/lib/CodeGen/Targets/Xtensa.cpp @@ -98,6 +98,13 @@ ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty, return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size)); } + // xtbool + if (getTarget().hasFeature("bool") && Size == 1 && Ty->isVectorType()) { + llvm::Type *ResType = + llvm::FixedVectorType::get(llvm::Type::getInt1Ty(getVMContext()), 1); + return ABIArgInfo::getDirect(ResType); + } + // Aggregates which are <= 6*32 will be passed in registers if possible, // so coerce to integers. if ((Size <= (MaxNumArgGPRs * 32)) && (!MustUseStack)) { diff --git a/llvm/lib/Target/Xtensa/XtensaCallingConv.td b/llvm/lib/Target/Xtensa/XtensaCallingConv.td index adfb8656b32d38..6c4feff9c108b7 100644 --- a/llvm/lib/Target/Xtensa/XtensaCallingConv.td +++ b/llvm/lib/Target/Xtensa/XtensaCallingConv.td @@ -14,11 +14,15 @@ class CCIfAlign : CCIf; +class CCIfFeature: + CCIf().has", Feature, "()"), A>; + //===----------------------------------------------------------------------===// // Xtensa return value calling convention //===----------------------------------------------------------------------===// def RetCC_Xtensa : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, + CCIfFeature<"Boolean",CCIfType<[v1i1], CCAssignToReg<[B0]>>>, CCIfType<[f32], CCBitConvertToType>, //First two return values go in a2, a3, a4, a5 @@ -39,6 +43,7 @@ def CSRWE_Xtensa : CalleeSavedRegs<(add)> { def RetCCW_Xtensa : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, + CCIfFeature<"Boolean",CCIfType<[v1i1], CCAssignToReg<[B0]>>>, CCIfType<[f32], CCBitConvertToType>, //First two return values go in a10, a11, a12, a13 diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index 9c67b0d4195715..f1db383620b376 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -375,15 +375,32 @@ void XtensaFrameLowering::processFunctionBeforeFrameFinalized( MachineFunction &MF, RegScavenger *RS) const { const XtensaSubtarget &STI = MF.getSubtarget(); + // Presence of SPILL_* pseudo-instructions requires spill slots + int NeedRegs = 0; + for (const MachineBasicBlock &MBB : MF) { + for (const MachineInstr &MI : MBB) { + unsigned Opcode = MI.getOpcode(); + if (Opcode == Xtensa::SPILL_BOOL) + NeedRegs += 1; + + if (Opcode == Xtensa::RESTORE_BOOL) + NeedRegs += 3; + } + } + NeedRegs = std::min(16, NeedRegs); + // In WinABI mode add register scavenging slot // FIXME: It may be posssible to add spill slot by more optimal way if (STI.isWinABI() && - (MF.getFrameInfo().estimateStackSize(MF) > STACK_SIZE_THRESHOLD)) { + ((MF.getFrameInfo().estimateStackSize(MF) > STACK_SIZE_THRESHOLD) || + (NeedRegs > 0))) { MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterClass &RC = Xtensa::ARRegClass; const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); unsigned Size = TRI.getSpillSize(RC); Align Alignment = TRI.getSpillAlign(RC); - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); + for (int i = 0; i < NeedRegs; i++) + RS->addScavengingFrameIndex( + MFI.CreateStackObject(Size, Alignment, false)); } } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index f801df409f6a14..7fa83454a7cfd7 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -64,6 +64,16 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, addRegisterClass(MVT::f32, &Xtensa::FPRRegClass); } + if (Subtarget.hasBoolean()) { + addRegisterClass(MVT::v1i1, &Xtensa::BRRegClass); + setOperationAction(ISD::Constant, MVT::v1i1, Expand); + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v1i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v1i1, Promote); + setLoadExtAction(ISD::EXTLOAD, VT, MVT::v1i1, Promote); + } + } + // Set up special registers. setStackPointerRegisterToSaveRestore(Xtensa::SP); @@ -775,6 +785,11 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, ISD::ArgFlagsTy ArgFlags, CCState &State) { static const MCPhysReg IntRegs[] = {Xtensa::A2, Xtensa::A3, Xtensa::A4, Xtensa::A5, Xtensa::A6, Xtensa::A7}; + static const MCPhysReg BoolRegs[] = { + Xtensa::B0, Xtensa::B1, Xtensa::B2, Xtensa::B3, + Xtensa::B4, Xtensa::B5, Xtensa::B6, Xtensa::B7, + Xtensa::B8, Xtensa::B9, Xtensa::B10, Xtensa::B11, + Xtensa::B12, Xtensa::B13, Xtensa::B14, Xtensa::B15}; if (ArgFlags.isByVal()) { Align ByValAlign = ArgFlags.getNonZeroByValAlign(); @@ -831,6 +846,9 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, Reg = State.AllocateReg(IntRegs); State.AllocateReg(IntRegs); LocVT = MVT::i32; + } else if (ValVT == MVT::v1i1) { + Reg = State.AllocateReg(BoolRegs); + LocVT = ValVT; } else llvm_unreachable("Cannot handle this ValVT."); @@ -925,6 +943,8 @@ SDValue XtensaTargetLowering::LowerFormalArguments( if (RegVT == MVT::i32) { RC = &Xtensa::ARRegClass; + } else if (RegVT == MVT::v1i1) { + RC = &Xtensa::BRRegClass; } else llvm_unreachable("RegVT not supported by FormalArguments Lowering"); @@ -3410,6 +3430,27 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( } return MBB; } + case Xtensa::MOVBA_P: { + const TargetRegisterClass *AR = getRegClassFor(MVT::i32); + + Register Dst1 = MRI.createVirtualRegister(AR); + Register Dst2 = MRI.createVirtualRegister(AR); + MachineOperand Breg = MI.getOperand(0); + MachineOperand Src = MI.getOperand(1); + + /* + MOVBA_P2 Breg, Dst1, Dest2, Src + */ + + BuildMI(*MBB, MI, DL, TII.get(Xtensa::MOVBA_P2), Breg.getReg()) + .addReg(Dst1, RegState::Define | RegState::EarlyClobber) + .addReg(Dst2, RegState::Define | RegState::EarlyClobber) + .addReg(Src.getReg()); + + MI.eraseFromParent(); + + return MBB; + } default: return EmitDSPInstrWithCustomInserter(MI, MBB, TII, MF, MRI, DL); // llvm_unreachable("Unexpected instr type to insert"); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 04d3d2d3c04119..dfaa5d285bcb90 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -105,7 +105,13 @@ void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB, else if (STI.hasSingleFloat() && Xtensa::ARRegClass.contains(SrcReg) && Xtensa::FPRRegClass.contains(DestReg)) Opcode = Xtensa::WFR; - else + else if (STI.hasBoolean() && Xtensa::BRRegClass.contains(SrcReg) && + Xtensa::BRRegClass.contains(DestReg)) { + BuildMI(MBB, MBBI, DL, get(Xtensa::ORB), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; + } else llvm_unreachable("Impossible reg-to-reg copy"); BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) @@ -148,6 +154,9 @@ void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, } else if (RC == &Xtensa::FPRRegClass) { LoadOpcode = Xtensa::LSI; StoreOpcode = Xtensa::SSI; + } else if (RC == &Xtensa::BRRegClass) { + LoadOpcode = Xtensa::RESTORE_BOOL; + StoreOpcode = Xtensa::SPILL_BOOL; } else llvm_unreachable("Unsupported regclass to load or store"); } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 51b0dd9a0cba58..4da7fb687187a5 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -892,6 +892,11 @@ def ROTW : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins imm8n_7:$imm), //===----------------------------------------------------------------------===// // Boolean Instructions //===----------------------------------------------------------------------===// +class BIN_PAT + : Pat<(dst_vt (node src_vt:$f1, src_vt:$f2)), + (inst src_vt:$f1, src_vt:$f2)>; + def ALL4 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s), "all4\t$t, $s", []>, Requires<[HasBoolean]> { @@ -907,6 +912,12 @@ def ANDB : RRR_Inst<0x00, 0x02, 0x00, (outs BR:$r), (ins BR:$s, BR:$t), "andb\t$r, $s, $t", []>, Requires<[HasBoolean]>; def ANDBC : RRR_Inst<0x00, 0x02, 0x01, (outs BR:$r), (ins BR:$s, BR:$t), "andbc\t$r, $s, $t", []>, Requires<[HasBoolean]>; +def ORB : RRR_Inst<0x00, 0x02, 0x02, (outs BR:$r), (ins BR:$s, BR:$t), + "orb\t$r, $s, $t", []>, Requires<[HasBoolean]>; +def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t), + "orbc\t$r, $s, $t", []>, Requires<[HasBoolean]>; +def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t), + "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>; def ANY4 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s), "any4\t$t, $s", []>, Requires<[HasBoolean]> { @@ -942,21 +953,67 @@ let isBranch = 1, isTerminator = 1, Predicates = [HasBoolean] in { } } -def MOVF : RRR_Inst<0x00, 0x03, 0x0C, (outs AR:$r), (ins AR:$s, BR:$t), +let Constraints = "$dr = $r,@earlyclobber $dr" in { + def MOVF : RRR_Inst<0x00, 0x03, 0x0C, (outs AR:$dr), (ins AR:$r, AR:$s, BR:$t), "movf\t$r, $s, $t", []>, Requires<[HasBoolean]>; -def MOVT : RRR_Inst<0x00, 0x03, 0x0D, (outs AR:$r), (ins AR:$s, BR:$t), - "movt\t$r, $s, $t", []>, Requires<[HasBoolean]>; -def ORB : RRR_Inst<0x00, 0x02, 0x02, (outs BR:$r), (ins BR:$s, BR:$t), - "orb\t$r, $s, $t", []>, Requires<[HasBoolean]>; -def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t), - "orbc\t$r, $s, $t", []>, Requires<[HasBoolean]>; -def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t), - "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>; + def MOVT : RRR_Inst<0x00, 0x03, 0x0D, (outs AR:$dr), (ins AR:$r, AR:$s, BR:$t), + "movt\t$r, $s, $t", []>, Requires<[HasBoolean]>; +} def : Pat<(Xtensa_br_t BR:$b, bb:$target), (BT BR:$b, bb:$target)>; def : Pat<(Xtensa_br_f BR:$b, bb:$target), (BF BR:$b, bb:$target)>; +let Predicates = [HasBoolean] in { + + def OR_BR_PAT: BIN_PAT; + def XOR_BR_PAT: BIN_PAT; + def AND_BR_PAT: BIN_PAT; + + // vselect C T F = C * T + ~C * F + def : Pat<(v1i1 (vselect v1i1:$c, v1i1:$t, v1i1:$f)), + (ORB (ANDB $t, $f), (ANDBC $f, $c))>; + + + def MOVBA_P2: Pseudo<(outs BR:$r, AR:$x, AR:$y), (ins AR:$s), + "!movba $r, $x, $y, $s", []> { + let Defs = [BREG]; + } + + def MOVBA_P: Pseudo<(outs BR:$r), (ins AR:$s), + "!movba $r, $s", []> { + let usesCustomInserter = 1; + let Defs = [BREG]; + //let Uses = [BREG]; + } + + def EXTUI_BR_P: Pseudo<(outs AR:$r), (ins AR:$s, BR:$b), + "!extui_br $r, $s, $b", []>; + def SLLI_BR_P: Pseudo<(outs AR:$r), (ins AR:$s, BR:$b), + "!slli_br $r, $s, $b", []>; + + def : Pat<(v1i1 (build_vector AR:$a)), (MOVBA_P AR:$a)>; + + def : Pat<(i32 (vector_extract (v1i1 BR:$b), (i32 0))), + (EXTUI_BR_P (RSR BREG), BR:$b)>; + + def : Pat<(v1i1 (load addr_ish1:$addr)), (MOVBA_P (L8UI mem8:$addr))>; + + def : Pat<(store BR:$b, addr_ish1:$addr), (S8I (EXTUI_BR_P (RSR BREG), BR:$b), mem32:$addr)>; + + def SPILL_BOOL: Pseudo<(outs), (ins BR:$b, mem8:$mem), + "!spill_bool $b, $mem",[]> { + let mayStore = 1; + } + + def RESTORE_BOOL: Pseudo<(outs BR:$out), (ins mem8:$mem), + "!restore_bool $out, $mem",[]> { + let mayLoad = 1; + let Defs = [BREG]; + } +} + + //===----------------------------------------------------------------------===// // Floating-Point Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index cdc29be5deb3bb..684ae7b894f239 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -25,9 +25,9 @@ def SDT_XtensaSelectCC : SDTypeProfile<1, 5, SDTCisVT<5, i32>]>; def SDT_XtensaMOVSP : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>; -def SDT_XtensaBrBool : SDTypeProfile<0, 2, [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]>; +def SDT_XtensaBrBool : SDTypeProfile<0, 2, [SDTCisVT<0, v1i1>, SDTCisVT<1, OtherVT>]>; def SDT_XtensaBrCCFP : SDTypeProfile<0, 4, [SDTCisVT<0, i32>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, SDTCisVT<3, OtherVT>]>; -def SDT_XtensaCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>; +def SDT_XtensaCmp : SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>; def SDT_XtensaMADD : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, f32>]>; def SDT_XtensaMOVS : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, f32>]>; def SDT_XtensaSelectCCFP : SDTypeProfile<1, 5, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>; diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index d49849a6819b7d..351f02a4c0fbf0 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -18,6 +18,7 @@ #include "XtensaSubtarget.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -70,16 +71,21 @@ BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(Xtensa::Q5); Reserved.set(Xtensa::Q6); Reserved.set(Xtensa::Q7); + Reserved.set(Xtensa::BREG); return Reserved; } bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, - uint64_t StackSize, - int64_t SPOffset) const { + uint64_t StackSize, int64_t SPOffset, + RegScavenger *RS) const { MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); + MachineBasicBlock &MBB = *MI.getParent(); + DebugLoc DL = II->getDebugLoc(); + const XtensaInstrInfo &TII = *static_cast( + MBB.getParent()->getSubtarget().getInstrInfo()); const std::vector &CSI = MFI.getCalleeSavedInfo(); int MinCSFI = 0; @@ -125,6 +131,8 @@ bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II, case Xtensa::L8I_P: case Xtensa::L8UI: case Xtensa::S8I: + case Xtensa::SPILL_BOOL: + case Xtensa::RESTORE_BOOL: Valid = (Offset >= 0 && Offset <= 255); break; case Xtensa::L16SI: @@ -161,6 +169,85 @@ bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II, IsKill = true; } + unsigned BRegBase = Xtensa::B0; + switch (MI.getOpcode()) { + case Xtensa::SPILL_BOOL: { + Register TempAR = RS->scavengeRegisterBackwards(Xtensa::ARRegClass, II, false, 0); + RS->setRegUsed(TempAR); + + BuildMI(MBB, II, DL, TII.get(Xtensa::RSR), TempAR).addReg(Xtensa::BREG); + MachineOperand &Breg = MI.getOperand(0); + unsigned RegNo = Breg.getReg().id() - BRegBase; + + BuildMI(MBB, II, DL, TII.get(Xtensa::EXTUI), TempAR) + .addReg(TempAR) + .addImm(RegNo) + .addImm(1); + + BuildMI(MBB, II, DL, TII.get(Xtensa::S8I)) + .addReg(TempAR, RegState::Kill) + .addReg(FrameReg, getKillRegState(IsKill)) + .addImm(Offset); + + MI.eraseFromParent(); + return true; + } + case Xtensa::RESTORE_BOOL: { + + Register SrcAR = RS->scavengeRegisterBackwards(Xtensa::ARRegClass, II, false, 0); + RS->setRegUsed(SrcAR); + Register MaskAR = RS->scavengeRegisterBackwards(Xtensa::ARRegClass, II, false, 0); + RS->setRegUsed(MaskAR); + Register BRegAR = RS->scavengeRegisterBackwards(Xtensa::ARRegClass, II, false, 0); + RS->setRegUsed(BRegAR); + + MachineOperand &Breg = MI.getOperand(0); + unsigned RegNo = Breg.getReg().id() - BRegBase; + + BuildMI(MBB, II, DL, TII.get(Xtensa::L8UI), SrcAR) + .addReg(FrameReg, getKillRegState(IsKill)) + .addImm(Offset); + + BuildMI(MBB, II, DL, TII.get(Xtensa::EXTUI), SrcAR) + .addReg(SrcAR) + .addImm(0) + .addImm(1); + + if (RegNo != 0) { + BuildMI(MBB, II, DL, TII.get(Xtensa::SLLI), SrcAR) + .addReg(SrcAR) + .addImm(RegNo); + } + + BuildMI(MBB, II, DL, TII.get(Xtensa::RSR), BRegAR).addReg(Xtensa::BREG); + + unsigned Mask = ~(1 << RegNo) & 0x3ff; + BuildMI(MBB, II, DL, TII.get(Xtensa::MOVI), MaskAR) + .addImm(RegNo < 12 ? Mask : 1); + if (RegNo >= 12) { + BuildMI(MBB, II, DL, TII.get(Xtensa::SLLI), MaskAR) + .addReg(MaskAR) + .addImm(RegNo); + } + BuildMI(MBB, II, DL, TII.get(Xtensa::AND), BRegAR) + .addReg(BRegAR) + .addReg(MaskAR); + + BuildMI(MBB, II, DL, TII.get(Xtensa::OR), BRegAR) + .addReg(SrcAR) + .addReg(BRegAR); + + BuildMI(MBB, II, DL, TII.get(Xtensa::WSR)) + .addReg(Xtensa::BREG, RegState::Define) + .addReg(BRegAR) + .addDef(Breg.getReg(), RegState::Implicit); + + MI.eraseFromParent(); + return true; + } + default: + break; + } MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); MI.getOperand(OpNo + 1).ChangeToImmediate(Offset); @@ -173,6 +260,8 @@ bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); + assert(RS && "Need register scavenger"); + LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; errs() << "<--------->\n" << MI); @@ -185,7 +274,7 @@ bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, << "spOffset : " << spOffset << "\n" << "stackSize : " << stackSize << "\n"); - return eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); + return eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset, RS); } Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const { @@ -193,3 +282,9 @@ Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const { return TFI->hasFP(MF) ? (Subtarget.isWinABI() ? Xtensa::A7 : Xtensa::A15) : Xtensa::SP; } + +bool XtensaRegisterInfo::requiresFrameIndexReplacementScavenging( + const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + return MFI.hasStackObjects(); +} \ No newline at end of file diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h index d5403ff35a197a..4e46199e8c3cf7 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h @@ -56,8 +56,10 @@ struct XtensaRegisterInfo : public XtensaGenRegisterInfo { private: bool eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, - int FrameIndex, uint64_t StackSize, - int64_t SPOffset) const; + int FrameIndex, uint64_t StackSize, int64_t SPOffset, + RegScavenger *RS) const; + + bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index dc2d5abc48758f..7f2de9814da902 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -308,5 +308,10 @@ foreach i = 0-15 in { } // Boolean register class -def BR : RegisterClass<"Xtensa", [i1], 0, (add B0, B1, -B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15)>; +def BR : RegisterClass<"Xtensa", [v1i1], 8, (add B0, B1, +B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15)> { + let Size = 8; +} + + + diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 910b9401c64159..b345215de8c1ae 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -34,7 +34,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTarget() { static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool IsLittle) { - std::string Ret = "e-m:e-p:32:32-i64:64-i128:128-n32"; + std::string Ret = "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32"; return Ret; } From afe05945df4841106e730a1ba7120072675ac6cc Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:02 +0000 Subject: [PATCH 198/261] [Xtensa] Refactor loadImmediate loadImmediate is split into two functions: - buildLoadImmediate which accepts allocated registers as params - loadImmediate which allocates virtual registers buildLoadImmediate is inteded to be used in post-RA passes. --- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 32 +++++++++++++++------- llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 4 +++ 2 files changed, 26 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index dfaa5d285bcb90..09ee11a9666ac9 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -161,23 +161,22 @@ void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, llvm_unreachable("Unsupported regclass to load or store"); } -void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB, +MachineInstrBuilder +XtensaInstrInfo::buildLoadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned *Reg, int64_t Value) const { + unsigned Reg, int64_t Value) const { DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); - const TargetRegisterClass *RC = &Xtensa::ARRegClass; - // create virtual reg to store immediate - *Reg = RegInfo.createVirtualRegister(RC); if (Value >= -2048 && Value <= 2047) { - BuildMI(MBB, MBBI, DL, get(Xtensa::MOVI), *Reg).addImm(Value); + return BuildMI(MBB, MBBI, DL, get(Xtensa::MOVI), Reg).addImm(Value); } else if (Value >= -32768 && Value <= 32767) { int Low = Value & 0xFF; int High = Value & ~0xFF; - BuildMI(MBB, MBBI, DL, get(Xtensa::MOVI), *Reg).addImm(Low); - BuildMI(MBB, MBBI, DL, get(Xtensa::ADDMI), *Reg).addReg(*Reg).addImm(High); + BuildMI(MBB, MBBI, DL, get(Xtensa::MOVI), Reg).addImm(Low); + return BuildMI(MBB, MBBI, DL, get(Xtensa::ADDMI), Reg) + .addReg(Reg) + .addImm(High); } else if (Value >= -4294967296LL && Value <= 4294967295LL) { // 32 bit arbirary constant MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); @@ -187,7 +186,8 @@ void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB, false); unsigned Idx = MCP->getConstantPoolIndex(CVal, Align(2U)); // MCSymbol MSym - BuildMI(MBB, MBBI, DL, get(Xtensa::L32R), *Reg).addConstantPoolIndex(Idx); + return BuildMI(MBB, MBBI, DL, get(Xtensa::L32R), Reg) + .addConstantPoolIndex(Idx); } else { // use L32R to let assembler load immediate best // TODO replace to L32R @@ -195,6 +195,18 @@ void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB, } } +void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned *Reg, int64_t Value) const { + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); + const TargetRegisterClass *RC = &Xtensa::ARRegClass; + + // create virtual reg to store immediate + *Reg = RegInfo.createVirtualRegister(RC); + buildLoadImmediate(MBB, MBBI, *Reg, Value); +} + unsigned XtensaInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { switch (MI.getOpcode()) { case TargetOpcode::INLINEASM: { // Inline Asm: Variable size. diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h index f2d50c3abafe40..b3925ec03de58a 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h @@ -65,6 +65,10 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { // physical register Reg. void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned *Reg, int64_t Value) const; + + MachineInstrBuilder buildLoadImmediate(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned Reg, int64_t Value) const; bool reverseBranchCondition(SmallVectorImpl &Cond) const override; MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; From 112442d6c4b0b450bf604940ef810e50760ea1b2 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:03 +0000 Subject: [PATCH 199/261] [Xtensa] Implement BRegFixupPass BRegFixupPass implements post-RA transformations for boolean instructions: - selecting the right constant for SLLI shift instruction based on physical register number. The number is unknown before regster allocation. - selecting the right constant for EXTUI bit extract operation based on physical BR register - emulating MOVBA (reg copy from AR to BR) operation --- llvm/lib/Target/Xtensa/CMakeLists.txt | 1 + llvm/lib/Target/Xtensa/Xtensa.h | 1 + .../lib/Target/Xtensa/XtensaBRegFixupPass.cpp | 188 ++++++++++++++++++ .../lib/Target/Xtensa/XtensaTargetMachine.cpp | 1 + 4 files changed, 191 insertions(+) create mode 100644 llvm/lib/Target/Xtensa/XtensaBRegFixupPass.cpp diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index 93a133be9dff85..10e957be5f3812 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -34,6 +34,7 @@ add_llvm_target(XtensaCodeGen XtensaTargetMachine.cpp XtensaTargetObjectFile.cpp XtensaTargetTransformInfo.cpp + XtensaBRegFixupPass.cpp LINK_COMPONENTS AsmPrinter diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h index 5a1560db519d94..76d5ec19a5e9f6 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.h +++ b/llvm/lib/Target/Xtensa/Xtensa.h @@ -31,5 +31,6 @@ FunctionPass *createXtensaHardwareLoops(); FunctionPass *createXtensaFixupHwLoops(); FunctionPass *createXtensaPSRAMCacheFixPass(); FunctionPass *createXtensaConstantIslandPass(); +FunctionPass *createXtensaBRegFixupPass(); } // namespace llvm #endif /* LLVM_LIB_TARGET_XTENSA_XTENSA_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaBRegFixupPass.cpp b/llvm/lib/Target/Xtensa/XtensaBRegFixupPass.cpp new file mode 100644 index 00000000000000..87077c96fd81d6 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaBRegFixupPass.cpp @@ -0,0 +1,188 @@ +//===- XtensaBRegFixup.cpp - Xtensa boolean register fixup ----------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "XtensaInstrInfo.h" +#include "XtensaSubtarget.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen//MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +#define DEBUG_TYPE "xtensa-breg-fixup-pass" + +class XtensaBRegFixup : public MachineFunctionPass { +public: + static char ID; + XtensaBRegFixup() : MachineFunctionPass(ID) {} + + const XtensaSubtarget *Subtarget; + static const XtensaInstrInfo *XtensaII; + + bool runOnMachineFunction(MachineFunction &MF) override; + + llvm::StringRef getPassName() const override { + return "Xtensa bool reg fixup pass"; + } + +private: + bool VisitMBB(MachineBasicBlock &MBB); + bool VisitInstruction(const MachineBasicBlock::instr_iterator &MII); +}; + +char XtensaBRegFixup::ID = 0; +const XtensaInstrInfo *XtensaBRegFixup::XtensaII; + +bool XtensaBRegFixup::runOnMachineFunction(MachineFunction &MF) { + + Subtarget = &static_cast(MF.getSubtarget()); + XtensaII = static_cast(Subtarget->getInstrInfo()); + bool Modified = false; + + MachineFunction::iterator I = MF.begin(), E = MF.end(); + + LLVM_DEBUG(dbgs() << "********* " << getPassName() << " *********\n"); + + for (; I != E; ++I) + Modified |= VisitMBB(*I); + return Modified; +} + +FunctionPass *llvm::createXtensaBRegFixupPass() { + return new XtensaBRegFixup(); +} + +bool XtensaBRegFixup::VisitMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::instr_iterator MII = MBB.instr_begin(), + E = MBB.instr_end(); + MachineBasicBlock::instr_iterator NextMII; + + // Iterate through the instructions in the basic block + for (; MII != E; MII = NextMII) { + NextMII = std::next(MII); + MachineInstr *MI = &*MII; + + // Don't reduce bundled instructions or pseudo operations + if (MI->isBundle() || MI->isTransient()) + continue; + + Modified |= VisitInstruction(MII); + } + + return Modified; +} + +bool XtensaBRegFixup::VisitInstruction( + const MachineBasicBlock::instr_iterator &MII) { + MachineInstr *MI = &*MII; + MachineBasicBlock &MBB = *MI->getParent(); + MachineFunction *MF = MBB.getParent(); + const XtensaInstrInfo &TII = + *static_cast(MF->getSubtarget().getInstrInfo()); + unsigned Opcode = MI->getOpcode(); + unsigned RegBase = Xtensa::B0; + + switch (Opcode) { + case Xtensa::MOVBA_P2: { + /* + MOVBA_P2 Breg, Dst1, Dst2, Src + | + V + RSR Dst1, BREG + LoadImmediate Dst2, BregMask + AND Dst2, Dst2, Dst1 + SLLI Dst1, Src, BregShift + OR Dst2, Dst2, Dst1 + WSR BREG, Dst2 + */ + MachineOperand Breg = MI->getOperand(0); + MachineOperand Dst1 = MI->getOperand(1); + MachineOperand Dst2 = MI->getOperand(2); + MachineOperand Src = MI->getOperand(3); + DebugLoc DL = MI->getDebugLoc(); + unsigned RegNo = Breg.getReg().id() - RegBase; + int64_t Mask = 0xffff & (~(1 << RegNo)); + + MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Xtensa::RSR)).add(Dst1).addReg(Xtensa::BREG); + + TII.buildLoadImmediate(MBB, MI, Dst2.getReg(), Mask); + + BuildMI(MBB, MI, DL, TII.get(Xtensa::AND)).add(Dst2).add(Dst2).add(Dst1); + + if (RegNo > 0) { + BuildMI(MBB, MI, DL, TII.get(Xtensa::SLLI)) + .add(Dst1) + .add(Src) + .addImm(RegNo); + } else { + Dst1.setReg(Src.getReg()); + } + + BuildMI(MBB, MI, DL, TII.get(Xtensa::OR)).add(Dst2).add(Dst2).add(Dst1); + + BuildMI(MBB, MI, DL, TII.get(Xtensa::WSR)).addReg(Xtensa::BREG).add(Dst2); + + LLVM_DEBUG(dbgs() << " Fixed MOVBA_P2: " << *MIB); + MBB.erase_instr(MI); + return true; + } break; + case Xtensa::EXTUI_BR_P: { + + MachineOperand Breg = MI->getOperand(2); + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::EXTUI); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + MIB.add(MI->getOperand(0)); + MIB.add(MI->getOperand(1)); + unsigned RegNo = Breg.getReg().id() - RegBase; + MIB.addImm(RegNo); + MIB.addImm(1); + + LLVM_DEBUG(dbgs() << " Fixed EXTUI: " << *MIB); + MBB.erase_instr(MI); + return true; + + } break; + + case Xtensa::SLLI_BR_P: { + + MachineOperand Breg = MI->getOperand(2); + unsigned RegNo = Breg.getReg().id() - RegBase; + if (RegNo != 0) { + DebugLoc dl = MI->getDebugLoc(); + const MCInstrDesc &NewMCID = XtensaII->get(Xtensa::SLLI); + MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + MIB.add(MI->getOperand(0)); + MIB.add(MI->getOperand(1)); + MIB.addImm(RegNo); + + LLVM_DEBUG(dbgs() << " Fixed SLLI: " << *MIB); + } else { + LLVM_DEBUG(dbgs() << " Fixed SLLI: SLLI 0 => NOP"); + } + MBB.erase_instr(MI); + return true; + + } break; + default: + break; + } + + return false; +} \ No newline at end of file diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index b345215de8c1ae..293c3cdf22534f 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -141,6 +141,7 @@ void XtensaPassConfig::addPreRegAlloc() { void XtensaPassConfig::addPreEmitPass() { addPass(createXtensaPSRAMCacheFixPass()); + addPass(createXtensaBRegFixupPass()); addPass(createXtensaSizeReductionPass()); addPass(createXtensaFixupHwLoops()); addPass(&BranchRelaxationPassID); From 2fe4e1399c1ddffbdf5ebc19b1a57a160b5c9a96 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:03 +0000 Subject: [PATCH 200/261] [Xtensa] Add LLVM tests for Boolean Extension LLVM bitcode tests verify that Xtensa backend can: - convert between v1i1 and scalar - generate code for v1i1 vselect - spill & restore BR registers - load and store v1i1 values --- .../CodeGen/Xtensa/xtensa-xtbool-convert.ll | 21 +++++++++ .../CodeGen/Xtensa/xtensa-xtbool-select.ll | 10 ++++ .../CodeGen/Xtensa/xtensa-xtbool-spill.ll | 46 +++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-xtbool-convert.ll create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-xtbool-select.ll create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll diff --git a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-convert.ll b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-convert.ll new file mode 100644 index 00000000000000..c2428cead69d7e --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-convert.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +define <1 x i1> @test_xtbool_trunc(i32 %a) { + ; CHECK-LABEL: test_xtbool_trunc + ; CHECK: rsr [[BREG:a[0-9]+]], br + ; CHECK: and [[AND:a[0-9]+]], {{a[0-9]+}}, {{a[0-9]+}} + ; CHECK: or [[OR:a[0-9]+]], [[AND]], a2 + ; CHECK: wsr [[OR]], br + %trunc = trunc i32 %a to i1 + %vec = insertelement <1 x i1> poison, i1 %trunc, i64 0 + ret <1 x i1> %vec +} + +define i32 @test_xtbool_zext(<1 x i1> %b) { + ; CHECK-LABEL: test_xtbool_zext + ; CHECK: rsr [[BREG:a[0-9]+]], br + ; CHECK: extui {{a[0-9]+}}, [[BREG]], 0, 1 + %bit = extractelement <1 x i1> %b, i64 0 + %int = zext i1 %bit to i32 + ret i32 %int +} diff --git a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-select.ll b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-select.ll new file mode 100644 index 00000000000000..b3f4b0e3dfa6a6 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-select.ll @@ -0,0 +1,10 @@ +; RUN: llc -O0 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +define <1 x i1> @test_select(<1 x i1> %cc, <1 x i1> %t, <1 x i1> %f) { + ; CHECK-LABEL: test_select + ; CHECK-DAG: andb [[EQ:b[0-9]+]], {{b[0-9]+}}, {{b[0-9]+}} + ; CHECK-DAG: andbc [[NE:b[0-9]+]], {{b[0-9]+}}, {{b[0-9]+}} + ; CHECK: orb {{b[0-9]+}}, [[EQ]], [[NE]] + %r = select <1 x i1> %cc, <1 x i1> %t, <1 x i1> %f + ret <1 x i1> %r +} diff --git a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll new file mode 100644 index 00000000000000..321e955be6cd96 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll @@ -0,0 +1,46 @@ +; RUN: llc -O0 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +define <1 x i1> @test_spill(<1 x i1> %b0, <1 x i1> %b1) +{ + ; CHECK-LABEL: test_spill + ; CHECK: rsr {{a[0-9]+}}, br + ; CHECK: s8i {{a[0-9]+}} + ; CHECK: callx8 a8 + %b2 = call <1 x i1> @get_xtbool() + + ; CHECK: l8ui {{a[0-9]+}} + ; CHECK: rsr {{a[0-9]+}}, br + ; CHECK: wsr {{a[0-9]+}}, br + ; CHECK: orb {{b[0-9]+}} + %r0 = or <1 x i1> %b0, %b1 + ret <1 x i1> %r0 +} + +declare <1 x i1> @get_xtbool() + +define <1 x i1> @test_xtbool_load(i32 %addr) { + ; CHECK-LABEL: test_xtbool_load + ; CHECK: l8ui {{a[0-9]+}} + ; CHECK: movi.n [[C:a[0-9]+]], 1 + ; CHECK: and [[SRC:a[0-9]+]], {{a[0-9]+}}, [[C]] + ; CHECK: rsr [[BREG:a[0-9]+]], br + ; CHECK: and [[AND:a[0-9]+]], {{a[0-9]+}}, [[BREG]] + ; CHECK: or [[OR:a[0-9]+]], [[AND]], [[SRC]] + ; CHECK: wsr [[OR]], br + %ptr = inttoptr i32 %addr to ptr + %load_bits = load <8 x i1>, ptr %ptr, align 1 + %extractvec = shufflevector <8 x i1> %load_bits, <8 x i1> poison, <1 x i32> zeroinitializer + ret <1 x i1> %extractvec +} + +define void @test_xtbool_store(i32 %addr, <1 x i1> %b) { +entry: + ; CHECK-LABEL: test_xtbool_store + ; CHECK: rsr [[BREG:a[0-9]+]], br + ; CHECK: extui [[DST:a[0-9]+]], [[BREG]], 0, 1 + ; CHECK: s8i [[DST]], {{a[0-9]+}}, {{[0-9]+}} + %ptr = inttoptr i32 %addr to ptr + %insertvec = shufflevector <1 x i1> %b, <1 x i1> poison, <8 x i32> + store <8 x i1> %insertvec, ptr %ptr, align 1 + ret void +} From aee6c192f917546653a82575047fc62840ee1103 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:03 +0000 Subject: [PATCH 201/261] [Xtensa] Separate directory for Clang CodeGen tests Prepare a separate directory for Xtensa-specific Clang CodeGen tests. --- clang/test/CodeGen/{ => Xtensa}/xtensa-abi.c | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename clang/test/CodeGen/{ => Xtensa}/xtensa-abi.c (100%) diff --git a/clang/test/CodeGen/xtensa-abi.c b/clang/test/CodeGen/Xtensa/xtensa-abi.c similarity index 100% rename from clang/test/CodeGen/xtensa-abi.c rename to clang/test/CodeGen/Xtensa/xtensa-abi.c From 89eee79822c352c63d3575f90d0f4428af1d3e7c Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:04 +0000 Subject: [PATCH 202/261] [Xtensa] Add ABI test for xtbool Extend Xtensa C ABI test to include v1i1 parameters. --- clang/test/CodeGen/Xtensa/xtensa-abi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/clang/test/CodeGen/Xtensa/xtensa-abi.c b/clang/test/CodeGen/Xtensa/xtensa-abi.c index e858f8e88044d8..297df864abc881 100644 --- a/clang/test/CodeGen/Xtensa/xtensa-abi.c +++ b/clang/test/CodeGen/Xtensa/xtensa-abi.c @@ -1,5 +1,7 @@ // RUN: %clang_cc1 -triple xtensa -O0 -emit-llvm %s -o - | FileCheck %s +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; + #define __malloc_like __attribute__((__malloc__)) char *bufalloc () __malloc_like ;//__result_use_check; extern void* malloc (unsigned size); @@ -26,3 +28,7 @@ void callee_struct_a16b_2(struct S16 a, int b) {} void callee_struct_a16b_3(int a, struct S16 b) {} // CHECK: define dso_local void @callee_struct_a16b_3(i32 noundef %a, ptr noundef byval(%struct.S16) align 16 %b) + +xtbool test_xtbool(xtbool a) {} + +// CHECK: define dso_local <1 x i1> @test_xtbool(<1 x i1> noundef %a) From 19493cf673d10ba90a918b7b25c60fb8b27de8b3 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:04 +0000 Subject: [PATCH 203/261] [Xtensa] Implement conditional move instrinsics Adding __builtin_xtensa_movt_s and __builtin_xtensa_movf_s intrinsics. Adding intrincic patterns to MOVT_S anf MOVF_S definitions. --- clang/include/clang/Basic/BuiltinsXtensa.def | 6 ++++++ .../CodeGen/Xtensa/xtensa-xtbool-intrinsics.c | 13 +++++++++++++ llvm/include/llvm/IR/Intrinsics.td | 1 + llvm/include/llvm/IR/IntrinsicsXtensa.td | 11 ++++++++++- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 16 +++++++++++----- .../Xtensa/xtensa-xtbool-intrinsics.ll | 19 +++++++++++++++++++ 6 files changed, 60 insertions(+), 6 deletions(-) create mode 100644 clang/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.c create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.ll diff --git a/clang/include/clang/Basic/BuiltinsXtensa.def b/clang/include/clang/Basic/BuiltinsXtensa.def index bc852bfc984a21..aac0d95f3c9b32 100644 --- a/clang/include/clang/Basic/BuiltinsXtensa.def +++ b/clang/include/clang/Basic/BuiltinsXtensa.def @@ -124,6 +124,12 @@ BUILTIN(__builtin_xtensa_wsr_m3, "vUi", "n") BUILTIN(__builtin_xtensa_rsr_m3, "Ui", "n") BUILTIN(__builtin_xtensa_xsr_m3, "vUi*", "n") +// Float intrinsics + +// float __builtin_xtensa_xt_movt_s(float frr, float frs, xtbool bt) +BUILTIN(__builtin_xtensa_xt_movt_s, "fffE1b", "n") +BUILTIN(__builtin_xtensa_xt_movf_s, "fffE1b", "n") + // generated code #include "clang/Basic/BuiltinsXtensaESP32S3.def" diff --git a/clang/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.c b/clang/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.c new file mode 100644 index 00000000000000..40a1274a61e408 --- /dev/null +++ b/clang/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.c @@ -0,0 +1,13 @@ +// RUN: %clang_cc1 -no-opaque-pointers -triple xtensa -O0 -emit-llvm %s -o - | FileCheck %s + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; + +xtbool test_xtbool_movt(float a, float b, xtbool c) { + // CHECK: %{{.*}} = call float @llvm.xtensa.xt.movt.s(float %{{.*}}, float {{.*}}, <1 x i1> {{.*}}) + return __builtin_xtensa_xt_movt_s(a, b, c); +} + +xtbool test_xtbool_movf(float a, float b, xtbool c) { + // CHECK: %{{.*}} = call float @llvm.xtensa.xt.movf.s(float %{{.*}}, float {{.*}}, <1 x i1> {{.*}}) + return __builtin_xtensa_xt_movf_s(a, b, c); +} \ No newline at end of file diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index c889a6c4121999..e24fc62f6d4a4c 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -500,6 +500,7 @@ def llvm_aarch64_svcount_ty : LLVMType; def llvm_x86amx_ty : LLVMType; +def llvm_v1i1_ty : LLVMType; // 1 x i1 def llvm_v2i1_ty : LLVMType; // 2 x i1 def llvm_v4i1_ty : LLVMType; // 4 x i1 def llvm_v8i1_ty : LLVMType; // 8 x i1 diff --git a/llvm/include/llvm/IR/IntrinsicsXtensa.td b/llvm/include/llvm/IR/IntrinsicsXtensa.td index 046df476967f3a..6092deeeb85783 100644 --- a/llvm/include/llvm/IR/IntrinsicsXtensa.td +++ b/llvm/include/llvm/IR/IntrinsicsXtensa.td @@ -249,7 +249,16 @@ def int_xtensa_xsr_m3: ClangBuiltin<"__builtin_xtensa_xsr_m3">, Intrinsic<[], [llvm_ptr_ty], []>; +//===----------------------------------------------------------------------===// +// Float operations + +def int_xtensa_xt_movt_s: ClangBuiltin<"__builtin_xtensa_xt_movt_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_v1i1_ty], [IntrNoMem]>; + +def int_xtensa_xt_movf_s: ClangBuiltin<"__builtin_xtensa_xt_movf_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_v1i1_ty], [IntrNoMem]>; + // Generated code // --------------- include "llvm/IR/IntrinsicsXtensaESP32S3.td" -} \ No newline at end of file +} diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 4da7fb687187a5..b5a0694e739b02 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1209,9 +1209,6 @@ def MOV_S : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins FPR:$s), def MOVEQZ_S : RRR_Inst<0x00, 0x0B, 0x08, (outs FPR:$r), (ins FPR:$s, AR:$t), "moveqz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; -def MOVF_S : RRR_Inst<0x00, 0x0B, 0x0C, (outs FPR:$r), (ins FPR:$s, BR:$t), - "movf.s\t$r, $s, $t", []>, Requires<[HasBoolean, HasSingleFloat]>; - def MOVGEZ_S : RRR_Inst<0x00, 0x0B, 0x0B, (outs FPR:$r), (ins FPR:$s, AR:$t), "movgez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; @@ -1221,8 +1218,17 @@ def MOVLTZ_S : RRR_Inst<0x00, 0x0B, 0x0A, (outs FPR:$r), (ins FPR:$s, AR:$t), def MOVNEZ_S : RRR_Inst<0x00, 0x0B, 0x09, (outs FPR:$r), (ins FPR:$s, AR:$t), "movnez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; -def MOVT_S : RRR_Inst<0x00, 0x0B, 0x0D, (outs FPR:$r), (ins FPR:$s, BR:$t), - "movt.s\t$r, $s, $t", []>, Requires<[HasBoolean, HasSingleFloat]>; +let Constraints = "$dr = $r,@earlyclobber $dr" in { + def MOVT_S : RRR_Inst<0x00, 0x0B, 0x0D, (outs FPR:$dr), (ins FPR:$r, FPR:$s, BR:$t), + "movt.s\t$r, $s, $t", + [(set FPR:$dr, (int_xtensa_xt_movt_s FPR:$r, FPR:$s, BR:$t))]>, + Requires<[HasBoolean, HasSingleFloat]>; + + def MOVF_S : RRR_Inst<0x00, 0x0B, 0x0C, (outs FPR:$dr), (ins FPR:$r, FPR:$s, BR:$t), + "movf.s\t$r, $s, $t", + [(set FPR:$dr, (int_xtensa_xt_movf_s FPR:$r, FPR:$s, BR:$t))]>, + Requires<[HasBoolean, HasSingleFloat]>; +} // FP multipy-sub def MSUB_S : RRR_Inst<0x00, 0x0A, 0x05, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t), diff --git a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.ll b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.ll new file mode 100644 index 00000000000000..3ccda04cf83fe3 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.ll @@ -0,0 +1,19 @@ +; RUN: llc -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + +define float @test_xtbool_movt(float %a, float %b, <1 x i1> %c) { + ; CHECK-LABEL: test_xtbool_movt + ; CHECK: movt.s {{f[0-9]+}}, {{f[0-9]+}}, b0 + %f = call float @llvm.xtensa.xt.movt.s(float %a, float %b, <1 x i1> %c) + ret float %f +} + +define float @test_xtbool_movf(float %a, float %b, <1 x i1> %c) { + ; CHECK-LABEL: test_xtbool_movf + ; CHECK: movf.s {{f[0-9]+}}, {{f[0-9]+}}, b0 + %f = call float @llvm.xtensa.xt.movf.s(float %a, float %b, <1 x i1> %c) + ret float %f +} + + +declare float @llvm.xtensa.xt.movt.s(float, float, <1 x i1>); +declare float @llvm.xtensa.xt.movf.s(float, float, <1 x i1>); From 0c47d5ab093c2a1c122856b90b20247b1553d611 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:05 +0000 Subject: [PATCH 204/261] [Xtensa] Add basic float intrinsics --- clang/include/clang/Basic/BuiltinsXtensa.def | 47 +++++++++++++++ clang/lib/Sema/SemaChecking.cpp | 8 +++ .../CodeGen/Xtensa/xtensa-float-intrinsics.c | 38 ++++++++++++ .../CodeGen/Xtensa/xtensa-xtbool-intrinsics.c | 37 +++++++++++- llvm/include/llvm/IR/IntrinsicsXtensa.td | 45 ++++++++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 41 +++++++++++++ .../CodeGen/Xtensa/xtensa-float-intrinsics.ll | 60 +++++++++++++++++++ .../Xtensa/xtensa-xtbool-intrinsics.ll | 55 +++++++++++++++++ 8 files changed, 330 insertions(+), 1 deletion(-) create mode 100644 clang/test/CodeGen/Xtensa/xtensa-float-intrinsics.c create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-float-intrinsics.ll diff --git a/clang/include/clang/Basic/BuiltinsXtensa.def b/clang/include/clang/Basic/BuiltinsXtensa.def index aac0d95f3c9b32..2df5d7370c6aeb 100644 --- a/clang/include/clang/Basic/BuiltinsXtensa.def +++ b/clang/include/clang/Basic/BuiltinsXtensa.def @@ -128,8 +128,55 @@ BUILTIN(__builtin_xtensa_xsr_m3, "vUi*", "n") // float __builtin_xtensa_xt_movt_s(float frr, float frs, xtbool bt) BUILTIN(__builtin_xtensa_xt_movt_s, "fffE1b", "n") + +// float __builtin_xtensa_xt_movf_s(float frr, float frs, xtbool bt) BUILTIN(__builtin_xtensa_xt_movf_s, "fffE1b", "n") +// xtbool __builtin_xtensa_xt_oeq_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_oeq_s, "E1bff", "n") + +// xtbool __builtin_xtensa_xt_ole_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_ole_s, "E1bff", "n") + +// xtbool __builtin_xtensa_xt_olt_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_olt_s, "E1bff", "n") + +// xtbool __builtin_xtensa_xt_ueq_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_ueq_s, "E1bff", "n") + +// xtbool __builtin_xtensa_xt_ule_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_ule_s, "E1bff", "n") + +// xtbool __builtin_xtensa_xt_ult_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_ult_s, "E1bff", "n") + +// xtbool __builtin_xtensa_xt_un_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_un_s, "E1bff", "n") + +// xtfloat __builtin_xtensa_xt_sub_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_sub_s, "fff", "n") + +// xtfloat __builtin_xtensa_xt_add_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_add_s, "fff", "n") + +// xtfloat __builtin_xtensa_xt_abs_s(xtfloat frs) +BUILTIN(__builtin_xtensa_xt_abs_s, "ff", "n") + +// xtfloat __builtin_xtensa_xt_mul_s(xtfloat frs,xtfloat frt) +BUILTIN(__builtin_xtensa_xt_mul_s, "fff", "n") + +// int __builtin_xtensa_xt_trunc_s(xtfloat frs,immediate imm_t) +BUILTIN(__builtin_xtensa_xt_trunc_s, "ifi", "n") + +// int __builtin_xtensa_xt_utrunc_s(xtfloat frs,immediate imm_t) +BUILTIN(__builtin_xtensa_xt_utrunc_s, "ifi", "n") + +// xtfloat __builtin_xtensa_xt_float_s(int ars,immediate imm_t) +BUILTIN(__builtin_xtensa_xt_float_s, "fii", "n") + +// xtfloat __builtin_xtensa_xt_ufloat_s(int ars,immediate imm_t) +BUILTIN(__builtin_xtensa_xt_ufloat_s, "fii", "n") + // generated code #include "clang/Basic/BuiltinsXtensaESP32S3.def" diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 9d0ebad6a448b3..fa7812d9db8b9c 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -6285,6 +6285,14 @@ bool Sema::CheckXtensaBuiltinFunctionCall(unsigned BuiltinID, return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || SemaBuiltinConstantArgRange(TheCall, 2, 0, 1) || SemaBuiltinConstantArgRange(TheCall, 3, 2, 3); + case Xtensa::BI__builtin_xtensa_xt_trunc_s: + case Xtensa::BI__builtin_xtensa_xt_utrunc_s: + case Xtensa::BI__builtin_xtensa_xt_float_s: + case Xtensa::BI__builtin_xtensa_xt_ufloat_s: + i = 1; + l = 0; + u = 15; + break; case Xtensa::BI__builtin_xtensa_ee_andq: case Xtensa::BI__builtin_xtensa_ee_cmul_s16: case Xtensa::BI__builtin_xtensa_ee_fft_cmul_s16_st_xp: diff --git a/clang/test/CodeGen/Xtensa/xtensa-float-intrinsics.c b/clang/test/CodeGen/Xtensa/xtensa-float-intrinsics.c new file mode 100644 index 00000000000000..97282730c7e369 --- /dev/null +++ b/clang/test/CodeGen/Xtensa/xtensa-float-intrinsics.c @@ -0,0 +1,38 @@ +// RUN: %clang_cc1 -no-opaque-pointers -triple xtensa -O0 -emit-llvm %s -o - | FileCheck %s + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; + +float test_float_s(int a) { + // CHECK: %{{.*}} = call float @llvm.xtensa.xt.float.s(i32 %{{.*}}, i32 1) + return __builtin_xtensa_xt_float_s(a, 1); +} + +float test_ufloat_s(int a) { + // CHECK: %{{.*}} = call float @llvm.xtensa.xt.ufloat.s(i32 %{{.*}}, i32 1) + return __builtin_xtensa_xt_ufloat_s(a, 1); +} + +int test_trunc_s(float a) { + // CHECK: %{{.*}} = call i32 @llvm.xtensa.xt.trunc.s(float %{{.*}}, i32 1) + return __builtin_xtensa_xt_trunc_s(a, 1); +} + +int test_utrunc_s(float a) { + // CHECK: %{{.*}} = call i32 @llvm.xtensa.xt.utrunc.s(float %{{.*}}, i32 1) + return __builtin_xtensa_xt_utrunc_s(a, 1); +} + +float test_add_s(float a, float b) { + // CHECK: %{{.*}} = call float @llvm.xtensa.xt.add.s(float %{{.*}}, float %{{.*}}) + return __builtin_xtensa_xt_add_s(a, b); +} + +float test_sub_s(float a, float b) { + // CHECK: %{{.*}} = call float @llvm.xtensa.xt.sub.s(float %{{.*}}, float %{{.*}}) + return __builtin_xtensa_xt_sub_s(a, b); +} + +float test_mul_s(float a, float b) { + // CHECK: %{{.*}} = call float @llvm.xtensa.xt.mul.s(float %{{.*}}, float %{{.*}}) + return __builtin_xtensa_xt_mul_s(a, b); +} diff --git a/clang/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.c b/clang/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.c index 40a1274a61e408..62689e9b591daa 100644 --- a/clang/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.c +++ b/clang/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple xtensa -O0 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple xtensa -O0 -emit-llvm %s -o - | FileCheck %s typedef __attribute__((ext_vector_type(1))) _Bool xtbool; @@ -10,4 +10,39 @@ xtbool test_xtbool_movt(float a, float b, xtbool c) { xtbool test_xtbool_movf(float a, float b, xtbool c) { // CHECK: %{{.*}} = call float @llvm.xtensa.xt.movf.s(float %{{.*}}, float {{.*}}, <1 x i1> {{.*}}) return __builtin_xtensa_xt_movf_s(a, b, c); +} + +xtbool test_xtbool_oeq_s(float a, float b) { + // CHECK: %{{.*}} = call <1 x i1> @llvm.xtensa.xt.oeq.s(float %{{.*}}, float {{.*}}) + return __builtin_xtensa_xt_oeq_s(a, b); +} + +xtbool test_xtbool_ueq_s(float a, float b) { + // CHECK: %{{.*}} = call <1 x i1> @llvm.xtensa.xt.ueq.s(float %{{.*}}, float {{.*}}) + return __builtin_xtensa_xt_ueq_s(a, b); +} + +xtbool test_xtbool_olt_s(float a, float b) { + // CHECK: %{{.*}} = call <1 x i1> @llvm.xtensa.xt.olt.s(float %{{.*}}, float {{.*}}) + return __builtin_xtensa_xt_olt_s(a, b); +} + +xtbool test_xtbool_ult_s(float a, float b) { + // CHECK: %{{.*}} = call <1 x i1> @llvm.xtensa.xt.ult.s(float %{{.*}}, float {{.*}}) + return __builtin_xtensa_xt_ult_s(a, b); +} + +xtbool test_xtbool_ole_s(float a, float b) { + // CHECK: %{{.*}} = call <1 x i1> @llvm.xtensa.xt.ole.s(float %{{.*}}, float {{.*}}) + return __builtin_xtensa_xt_ole_s(a, b); +} + +xtbool test_xtbool_ule_s(float a, float b) { + // CHECK: %{{.*}} = call <1 x i1> @llvm.xtensa.xt.ule.s(float %{{.*}}, float {{.*}}) + return __builtin_xtensa_xt_ule_s(a, b); +} + +xtbool test_xtbool_un_s(float a, float b) { + // CHECK: %{{.*}} = call <1 x i1> @llvm.xtensa.xt.un.s(float %{{.*}}, float {{.*}}) + return __builtin_xtensa_xt_un_s(a, b); } \ No newline at end of file diff --git a/llvm/include/llvm/IR/IntrinsicsXtensa.td b/llvm/include/llvm/IR/IntrinsicsXtensa.td index 6092deeeb85783..2b9c8dd62cb7c6 100644 --- a/llvm/include/llvm/IR/IntrinsicsXtensa.td +++ b/llvm/include/llvm/IR/IntrinsicsXtensa.td @@ -258,6 +258,51 @@ def int_xtensa_xt_movt_s: ClangBuiltin<"__builtin_xtensa_xt_movt_s">, def int_xtensa_xt_movf_s: ClangBuiltin<"__builtin_xtensa_xt_movf_s">, Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_v1i1_ty], [IntrNoMem]>; +def int_xtensa_xt_oeq_s: ClangBuiltin<"__builtin_xtensa_xt_oeq_s">, + Intrinsic<[llvm_v1i1_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_ole_s: ClangBuiltin<"__builtin_xtensa_xt_ole_s">, + Intrinsic<[llvm_v1i1_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_olt_s: ClangBuiltin<"__builtin_xtensa_xt_olt_s">, + Intrinsic<[llvm_v1i1_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_ueq_s: ClangBuiltin<"__builtin_xtensa_xt_ueq_s">, + Intrinsic<[llvm_v1i1_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_ule_s: ClangBuiltin<"__builtin_xtensa_xt_ule_s">, + Intrinsic<[llvm_v1i1_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_ult_s: ClangBuiltin<"__builtin_xtensa_xt_ult_s">, + Intrinsic<[llvm_v1i1_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_un_s: ClangBuiltin<"__builtin_xtensa_xt_un_s">, + Intrinsic<[llvm_v1i1_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_add_s: ClangBuiltin<"__builtin_xtensa_xt_add_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_abs_s: ClangBuiltin<"__builtin_xtensa_xt_abs_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_mul_s: ClangBuiltin<"__builtin_xtensa_xt_mul_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_sub_s: ClangBuiltin<"__builtin_xtensa_xt_sub_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_trunc_s: ClangBuiltin<"__builtin_xtensa_xt_trunc_s">, + Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_xt_utrunc_s: ClangBuiltin<"__builtin_xtensa_xt_utrunc_s">, + Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_xt_float_s: ClangBuiltin<"__builtin_xtensa_xt_float_s">, + Intrinsic<[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_xt_ufloat_s: ClangBuiltin<"__builtin_xtensa_xt_ufloat_s">, + Intrinsic<[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + // Generated code // --------------- include "llvm/IR/IntrinsicsXtensaESP32S3.td" diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index b5a0694e739b02..df6b50930cb52a 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -29,6 +29,11 @@ class ArithLogic_RRR oper2, bits<4> oper1, string instrAsm, let isReMaterializable = 0; } +class Arith_Pat + : Pat<(res_vt (opNode op_vt:$r, op_vt:$t)), + (inst op_vt:$r, op_vt:$t)>; + def ADD : ArithLogic_RRR<0x08, 0x00, "add", add, 1>; def SUB : ArithLogic_RRR<0x0C, 0x00, "sub", sub>; def AND : ArithLogic_RRR<0x01, 0x00, "and", and, 1>; @@ -1032,6 +1037,12 @@ def ADD_S : FPArith_RRR<0x00, 0x0A, "add.s", fadd, 1>; def SUB_S : FPArith_RRR<0x01, 0x0A, "sub.s", fsub>; def MUL_S : FPArith_RRR<0x02, 0x0A, "mul.s", fmul, 1>; +let Predicates = [HasSingleFloat] in { + def : Arith_Pat; + def : Arith_Pat; + def : Arith_Pat; +} + // FP load instructions let mayLoad = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { def LSI : RRI8_Inst<0x03, (outs FPR:$t), (ins mem32:$addr), @@ -1112,6 +1123,16 @@ def ULT_S : FCompare<0x05, 0x0b, "ult.s", Xtensa_cmpult, 0>; def ULE_S : FCompare<0x07, 0x0b, "ule.s", Xtensa_cmpule, 0>; def UN_S : FCompare<0x01, 0x0b, "un.s", Xtensa_cmpuo, 1>; +let Predicates = [HasSingleFloat] in { + def : Arith_Pat; + def : Arith_Pat; + def : Arith_Pat; + def : Arith_Pat; + def : Arith_Pat; + def : Arith_Pat; + def : Arith_Pat; +} + def ABS_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "abs.s\t$r, $s", [(set FPR:$r, (fabs FPR:$s))]>, Requires<[HasSingleFloat]> { @@ -1120,6 +1141,10 @@ def ABS_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), def : Pat<(fabs FPR:$s), (ABS_S $s)>; +def : Pat<(f32 (int_xtensa_xt_abs_s FPR:$frs)), + (ABS_S FPR:$frs)>, + Requires<[HasSingleFloat]>; + def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), "addexp.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0E; @@ -1162,6 +1187,10 @@ def FLOAT_S : RRR_Inst<0x00, 0x0A, 0x0c, (outs FPR:$r), (ins AR:$s, uimm4:$imm), def : Pat<(f32 (sint_to_fp AR:$s)), (FLOAT_S AR:$s, 0)>; +def : Pat<(f32 (int_xtensa_xt_float_s i32:$s, timm:$imm)), + (FLOAT_S AR:$s, uimm4:$imm)>, + Requires<[HasSingleFloat]>; + def FLOOR_S : RRR_Inst<0x00, 0x0A, 0x0A, (outs AR:$r), (ins FPR:$s, uimm4:$imm), "floor.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { bits<4> imm; @@ -1291,6 +1320,10 @@ def TRUNC_S : RRR_Inst<0x00, 0x0A, 0x09, (outs AR:$r), (ins FPR:$s, uimm4:$imm), def : Pat<(i32 (any_fp_to_sint FPR:$s)), (TRUNC_S FPR:$s, 0)>; +def : Pat<(i32 (int_xtensa_xt_trunc_s f32:$frs, timm:$imm)), + (TRUNC_S FPR:$frs, uimm4:$imm)>, + Requires<[HasSingleFloat]>; + def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s, uimm4:$imm), "ufloat.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { bits<4> imm; @@ -1300,6 +1333,10 @@ def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s, uimm4:$imm) def : Pat<(f32 (uint_to_fp AR:$s)), (UFLOAT_S AR:$s, 0)>; +def : Pat<(f32 (int_xtensa_xt_ufloat_s i32:$s, timm:$imm)), + (UFLOAT_S AR:$s, uimm4:$imm)>, + Requires<[HasSingleFloat]>; + def UTRUNC_S : RRR_Inst<0x00, 0x0A, 0x0e, (outs AR:$r), (ins FPR:$s, uimm4:$imm), "utrunc.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { bits<4> imm; @@ -1309,6 +1346,10 @@ def UTRUNC_S : RRR_Inst<0x00, 0x0A, 0x0e, (outs AR:$r), (ins FPR:$s, uimm4:$imm) def : Pat<(i32 (any_fp_to_uint FPR:$s)), (UTRUNC_S FPR:$s, 0)>; +def : Pat<(i32 (int_xtensa_xt_utrunc_s f32:$frs, timm:$imm)), + (UTRUNC_S FPR:$frs, uimm4:$imm)>, + Requires<[HasSingleFloat]>; + def WFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins AR:$s), "wfr\t$r, $s", [(set FPR:$r, (bitconvert AR:$s))]>, Requires<[HasSingleFloat]> { diff --git a/llvm/test/CodeGen/Xtensa/xtensa-float-intrinsics.ll b/llvm/test/CodeGen/Xtensa/xtensa-float-intrinsics.ll new file mode 100644 index 00000000000000..73d54e2a51210e --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-float-intrinsics.ll @@ -0,0 +1,60 @@ +; RUN: llc -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s + + + +define float @test_float_s(i32 %a) { + ; CHECK-LABEL: test_float_s + ; CHECK: float.s {{f[0-9]+}}, a2, 1 + %r = call float @llvm.xtensa.xt.float.s(i32 %a, i32 1) + ret float %r +} + +define float @test_ufloat_s(i32 %a) { + ; CHECK-LABEL: test_ufloat_s + ; CHECK: ufloat.s {{f[0-9]+}}, a2, 1 + %r = call float @llvm.xtensa.xt.ufloat.s(i32 %a, i32 1) + ret float %r +} + +define i32 @test_trunc_s(float %a) { + ; CHECK-LABEL: test_trunc_s + ; CHECK: trunc.s a2, {{f[0-9]+}}, 1 + %r = call i32 @llvm.xtensa.xt.trunc.s(float %a, i32 1) + ret i32 %r +} + +define i32 @test_utrunc_s(float %a) { + ; CHECK-LABEL: test_utrunc_s + ; CHECK: trunc.s a2, {{f[0-9]+}}, 1 + %r = call i32 @llvm.xtensa.xt.utrunc.s(float %a, i32 1) + ret i32 %r +} + +define float @test_add_s(float %a, float %b) { + ; CHECK-LABEL: test_add_s + ; CHECK: add.s {{f[0-9]+}}, {{f[0-9]+}}, {{f[0-9]+}} + %r = call float @llvm.xtensa.xt.add.s(float %a, float %b) + ret float %r +} + +define float @test_sub_s(float %a, float %b) { + ; CHECK-LABEL: test_sub_s + ; CHECK: sub.s {{f[0-9]+}}, {{f[0-9]+}}, {{f[0-9]+}} + %r = call float @llvm.xtensa.xt.sub.s(float %a, float %b) + ret float %r +} + +define float @test_mul_s(float %a, float %b) { + ; CHECK-LABEL: test_mul_s + ; CHECK: mul.s {{f[0-9]+}}, {{f[0-9]+}}, {{f[0-9]+}} + %r = call float @llvm.xtensa.xt.mul.s(float %a, float %b) + ret float %r +} + +declare float @llvm.xtensa.xt.float.s(i32, i32); +declare float @llvm.xtensa.xt.ufloat.s(i32, i32); +declare i32 @llvm.xtensa.xt.trunc.s(float , i32); +declare i32 @llvm.xtensa.xt.utrunc.s(float, i32); +declare float @llvm.xtensa.xt.add.s(float %a, float %b); +declare float @llvm.xtensa.xt.sub.s(float %a, float %b); +declare float @llvm.xtensa.xt.mul.s(float %a, float %b); diff --git a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.ll b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.ll index 3ccda04cf83fe3..cdb36c4667465b 100644 --- a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.ll +++ b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-intrinsics.ll @@ -14,6 +14,61 @@ define float @test_xtbool_movf(float %a, float %b, <1 x i1> %c) { ret float %f } +define <1 x i1> @test_xtbool_oeq_s(float %a, float %b) { + ; CHECK-LABEL: test_xtbool_oeq_s + ; CHECK: oeq.s b0, {{f[0-9]+}}, {{f[0-9]+}} + %r = call <1 x i1> @llvm.xtensa.xt.oeq.s(float %a, float %b) + ret <1 x i1> %r +} + +define <1 x i1> @test_xtbool_ueq_s(float %a, float %b) { + ; CHECK-LABEL: test_xtbool_ueq_s + ; CHECK: ueq.s b0, {{f[0-9]+}}, {{f[0-9]+}} + %r = call <1 x i1> @llvm.xtensa.xt.ueq.s(float %a, float %b) + ret <1 x i1> %r +} + +define <1 x i1> @test_xtbool_ole_s(float %a, float %b) { + ; CHECK-LABEL: test_xtbool_ole_s + ; CHECK: ole.s b0, {{f[0-9]+}}, {{f[0-9]+}} + %r = call <1 x i1> @llvm.xtensa.xt.ole.s(float %a, float %b) + ret <1 x i1> %r +} + +define <1 x i1> @test_xtbool_ule_s(float %a, float %b) { + ; CHECK-LABEL: test_xtbool_ule_s + ; CHECK: ule.s b0, {{f[0-9]+}}, {{f[0-9]+}} + %r = call <1 x i1> @llvm.xtensa.xt.ule.s(float %a, float %b) + ret <1 x i1> %r +} + +define <1 x i1> @test_xtbool_olt_s(float %a, float %b) { + ; CHECK-LABEL: test_xtbool_olt_s + ; CHECK: olt.s b0, {{f[0-9]+}}, {{f[0-9]+}} + %r = call <1 x i1> @llvm.xtensa.xt.olt.s(float %a, float %b) + ret <1 x i1> %r +} + +define <1 x i1> @test_xtbool_ult_s(float %a, float %b) { + ; CHECK-LABEL: test_xtbool_ult_s + ; CHECK: ult.s b0, {{f[0-9]+}}, {{f[0-9]+}} + %r = call <1 x i1> @llvm.xtensa.xt.ult.s(float %a, float %b) + ret <1 x i1> %r +} + +define <1 x i1> @test_un_s(float %a, float %b) { + ; CHECK-LABEL: test_un_s + ; CHECK: un.s b0, {{f[0-9]+}}, {{f[0-9]+}} + %r = call <1 x i1> @llvm.xtensa.xt.un.s(float %a, float %b) + ret <1 x i1> %r +} declare float @llvm.xtensa.xt.movt.s(float, float, <1 x i1>); declare float @llvm.xtensa.xt.movf.s(float, float, <1 x i1>); +declare <1 x i1> @llvm.xtensa.xt.oeq.s(float, float); +declare <1 x i1> @llvm.xtensa.xt.ueq.s(float, float); +declare <1 x i1> @llvm.xtensa.xt.ole.s(float, float); +declare <1 x i1> @llvm.xtensa.xt.ule.s(float, float); +declare <1 x i1> @llvm.xtensa.xt.olt.s(float, float); +declare <1 x i1> @llvm.xtensa.xt.ult.s(float, float); +declare <1 x i1> @llvm.xtensa.xt.un.s(float %a, float %b); \ No newline at end of file From 93b16cb6b15320171f2628c461b08dbcdf17f4ff Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Mar 2024 15:37:13 +0300 Subject: [PATCH 205/261] [Xtensa] Implement remaining floating point intrinsics --- clang/include/clang/Basic/BuiltinsXtensa.def | 106 ++++++++++ clang/lib/CodeGen/CGBuiltin.cpp | 46 +++++ clang/lib/CodeGen/CodeGenFunction.h | 3 + clang/lib/Sema/SemaChecking.cpp | 11 + .../CodeGen/Xtensa/xtensa-float-intrinsics.c | 12 +- .../CodeGen/Xtensa/xtensa-gen-intrinsics.c | 88 ++++++++ llvm/include/llvm/IR/IntrinsicsXtensa.td | 111 ++++++++++ .../Disassembler/XtensaDisassembler.cpp | 8 + .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 16 ++ llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 35 ++++ llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 8 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 192 +++++++++++++++--- llvm/lib/Target/Xtensa/XtensaOperands.td | 5 +- .../CodeGen/Xtensa/xtensa-float-intrinsics.ll | 18 ++ .../CodeGen/Xtensa/xtensa-gen-intrinsics.ll | 80 ++++++++ 15 files changed, 705 insertions(+), 34 deletions(-) create mode 100644 clang/test/CodeGen/Xtensa/xtensa-gen-intrinsics.c create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-gen-intrinsics.ll diff --git a/clang/include/clang/Basic/BuiltinsXtensa.def b/clang/include/clang/Basic/BuiltinsXtensa.def index 2df5d7370c6aeb..b03e31412ffe61 100644 --- a/clang/include/clang/Basic/BuiltinsXtensa.def +++ b/clang/include/clang/Basic/BuiltinsXtensa.def @@ -177,6 +177,112 @@ BUILTIN(__builtin_xtensa_xt_float_s, "fii", "n") // xtfloat __builtin_xtensa_xt_ufloat_s(int ars,immediate imm_t) BUILTIN(__builtin_xtensa_xt_ufloat_s, "fii", "n") +// xtfloat __builtin_xtensa___builtin_xtensa_xt_addexp_s(xtfloat,xtfloat) +BUILTIN(__builtin_xtensa_xt_addexp_s, "fff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_addexpm_s(xtfloat,xtfloat) +BUILTIN(__builtin_xtensa_xt_addexpm_s, "fff", "n") + +// int __builtin_xtensa___builtin_xtensa_xt_ceil_s(xtfloat,immediate) +BUILTIN(__builtin_xtensa_xt_ceil_s, "ifi", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_div0_s(xtfloat) +BUILTIN(__builtin_xtensa_xt_div0_s, "ff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_divn_s(xtfloat,xtfloat,xtfloat) +BUILTIN(__builtin_xtensa_xt_divn_s, "ffff", "n") + +// int __builtin_xtensa___builtin_xtensa_xt_floor_s(xtfloat,immediate) +BUILTIN(__builtin_xtensa_xt_floor_s, "ifi", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_lsi(const xtfloat*,immediate) +BUILTIN(__builtin_xtensa_xt_lsi, "ff*i", "n") + +BUILTIN(__builtin_xtensa_xt_lsip, "ff**i", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_lsx(const xtfloat*,int) +BUILTIN(__builtin_xtensa_xt_lsx, "ff*i", "n") + +BUILTIN(__builtin_xtensa_xt_lsxp, "ff*i", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_madd_s(xtfloat,xtfloat,xtfloat) +BUILTIN(__builtin_xtensa_xt_madd_s, "ffff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_maddn_s(xtfloat,xtfloat,xtfloat) +BUILTIN(__builtin_xtensa_xt_maddn_s, "ffff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_mkdadj_s(xtfloat,xtfloat) +BUILTIN(__builtin_xtensa_xt_mkdadj_s, "fff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_mksadj_s(xtfloat) +BUILTIN(__builtin_xtensa_xt_mksadj_s, "ff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_mov_s(xtfloat) +BUILTIN(__builtin_xtensa_xt_mov_s, "ff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_moveqz_s(xtfloat,xtfloat,int) +BUILTIN(__builtin_xtensa_xt_moveqz_s, "fffi", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_movgez_s(xtfloat,xtfloat,int) +BUILTIN(__builtin_xtensa_xt_movgez_s, "fffi", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_movltz_s(xtfloat,xtfloat,int) +BUILTIN(__builtin_xtensa_xt_movltz_s, "fffi", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_movnez_s(xtfloat,xtfloat,int) +BUILTIN(__builtin_xtensa_xt_movnez_s, "fffi", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_msub_s(xtfloat,xtfloat,xtfloat) +BUILTIN(__builtin_xtensa_xt_msub_s, "ffff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_neg_s(xtfloat) +BUILTIN(__builtin_xtensa_xt_neg_s, "ff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_nexp01_s(xtfloat) +BUILTIN(__builtin_xtensa_xt_nexp01_s, "ff", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_recip0_s(xtfloat) +BUILTIN(__builtin_xtensa_xt_recip0_s, "ff", "n") + +// int __builtin_xtensa___builtin_xtensa_xt_rfr(xtfloat) +BUILTIN(__builtin_xtensa_xt_rfr, "if", "n") + +// int __builtin_xtensa___builtin_xtensa_xt_round_s(xtfloat,immediate) +BUILTIN(__builtin_xtensa_xt_round_s, "ifi", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_rsqrt0_s(xtfloat) +BUILTIN(__builtin_xtensa_xt_rsqrt0_s, "ff", "n") + +// int __builtin_xtensa___builtin_xtensa_xt_rur_fcr() +BUILTIN(__builtin_xtensa_xt_rur_fcr, "i", "n") + +// int __builtin_xtensa___builtin_xtensa_xt_rur_fsr() +BUILTIN(__builtin_xtensa_xt_rur_fsr, "i", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_sqrt0_s(xtfloat) +BUILTIN(__builtin_xtensa_xt_sqrt0_s, "ff", "n") + +// void __builtin_xtensa___builtin_xtensa_xt_ssi(xtfloat,xtfloat*,immediate) +BUILTIN(__builtin_xtensa_xt_ssi, "vff*i", "n") + +// xtfloat* __builtin_xtensa___builtin_xtensa_xt_ssip(xtfloat,xtfloat*,immediate) +BUILTIN(__builtin_xtensa_xt_ssip, "f*ff*i", "n") + +// void __builtin_xtensa___builtin_xtensa_xt_ssx(xtfloat,xtfloat*,int) +BUILTIN(__builtin_xtensa_xt_ssx, "vff*i", "n") + +// xtfloat* __builtin_xtensa___builtin_xtensa_xt_ssxp(xtfloat,xtfloat*,int) +BUILTIN(__builtin_xtensa_xt_ssxp, "f*ff*i", "n") + +// xtfloat __builtin_xtensa___builtin_xtensa_xt_wfr(int) +BUILTIN(__builtin_xtensa_xt_wfr, "fi", "n") + +// void __builtin_xtensa___builtin_xtensa_xt_wur_fcr(int) +BUILTIN(__builtin_xtensa_xt_wur_fcr, "vi", "n") + +// void __builtin_xtensa___builtin_xtensa_xt_wur_fsr(int) +BUILTIN(__builtin_xtensa_xt_wur_fsr, "vi", "n") + // generated code #include "clang/Basic/BuiltinsXtensaESP32S3.def" diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index a4f26a6f0eb19b..fb8798f82ace75 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -53,6 +53,7 @@ #include "llvm/IR/IntrinsicsVE.h" #include "llvm/IR/IntrinsicsWebAssembly.h" #include "llvm/IR/IntrinsicsX86.h" +#include "llvm/IR/IntrinsicsXtensa.h" #include "llvm/IR/MDBuilder.h" #include "llvm/IR/MatrixBuilder.h" #include "llvm/Support/ConvertUTF.h" @@ -6041,6 +6042,8 @@ static Value *EmitTargetArchBuiltinExpr(CodeGenFunction *CGF, case llvm::Triple::riscv32: case llvm::Triple::riscv64: return CGF->EmitRISCVBuiltinExpr(BuiltinID, E, ReturnValue); + case llvm::Triple::xtensa: + return CGF->EmitXtensaBuiltinExpr(BuiltinID, E, ReturnValue, Arch); default: return nullptr; } @@ -21319,3 +21322,46 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); return Builder.CreateCall(F, Ops, ""); } + +llvm::Value * +CodeGenFunction::EmitXtensaBuiltinExpr(unsigned BuiltinID, const CallExpr *E, + ReturnValueSlot ReturnValue, + llvm::Triple::ArchType Arch) { + + unsigned IntrinsicID; + switch (BuiltinID) { + case Xtensa::BI__builtin_xtensa_xt_lsxp: + IntrinsicID = Intrinsic::xtensa_xt_lsxp; + break; + case Xtensa::BI__builtin_xtensa_xt_lsip: + IntrinsicID = Intrinsic::xtensa_xt_lsip; + break; + default: + llvm_unreachable("unexpected builtin ID"); + } + + llvm::Function *F = CGM.getIntrinsic(IntrinsicID); + // 1st argument is passed by pointer + /* float lsip(float **a, int off) => float p = *a + ret, p' = @int.xtensa.lsip(p, off) + *a = p' + */ + auto InoutPtrTy = F->getArg(0)->getType()->getPointerTo(); + Address InoutPtrAddr = Builder.CreateElementBitCast( + EmitPointerWithAlignment(E->getArg(0)), InoutPtrTy); + + unsigned NumArgs = E->getNumArgs(); + Value *InoutVal = Builder.CreateLoad(InoutPtrAddr); + SmallVector Args; + + Args.push_back(InoutVal); + for (unsigned i = 1; i < NumArgs; i++) + Args.push_back(EmitScalarExpr(E->getArg(i))); + + Value *Val = Builder.CreateCall(F, Args, "retval"); + Value *Val0 = Builder.CreateExtractValue(Val, 0); + Value *Val1 = Builder.CreateExtractValue(Val, 1); + // ret store + Builder.CreateStore(Val1, InoutPtrAddr); + return Val0; +} diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 143ad64e8816b1..4c0ac975f03fff 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -4503,6 +4503,9 @@ class CodeGenFunction : public CodeGenTypeCache { /// Emits a reference binding to the passed in expression. RValue EmitReferenceBindingToExpr(const Expr *E); + llvm::Value *EmitXtensaBuiltinExpr(unsigned BuiltinID, const CallExpr *E, + ReturnValueSlot ReturnValue, + llvm::Triple::ArchType Arch); //===--------------------------------------------------------------------===// // Expression Emission //===--------------------------------------------------------------------===// diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index fa7812d9db8b9c..72efbb6e507d85 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -6289,10 +6289,21 @@ bool Sema::CheckXtensaBuiltinFunctionCall(unsigned BuiltinID, case Xtensa::BI__builtin_xtensa_xt_utrunc_s: case Xtensa::BI__builtin_xtensa_xt_float_s: case Xtensa::BI__builtin_xtensa_xt_ufloat_s: + case Xtensa::BI__builtin_xtensa_xt_ceil_s: + case Xtensa::BI__builtin_xtensa_xt_floor_s: + case Xtensa::BI__builtin_xtensa_xt_round_s: i = 1; l = 0; u = 15; break; + case Xtensa::BI__builtin_xtensa_xt_lsi: + case Xtensa::BI__builtin_xtensa_xt_lsip: + return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1020) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 4); + case Xtensa::BI__builtin_xtensa_xt_ssi: + case Xtensa::BI__builtin_xtensa_xt_ssip: + return SemaBuiltinConstantArgRange(TheCall, 2, 0, 1020) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); case Xtensa::BI__builtin_xtensa_ee_andq: case Xtensa::BI__builtin_xtensa_ee_cmul_s16: case Xtensa::BI__builtin_xtensa_ee_fft_cmul_s16_st_xp: diff --git a/clang/test/CodeGen/Xtensa/xtensa-float-intrinsics.c b/clang/test/CodeGen/Xtensa/xtensa-float-intrinsics.c index 97282730c7e369..150eface40a0b3 100644 --- a/clang/test/CodeGen/Xtensa/xtensa-float-intrinsics.c +++ b/clang/test/CodeGen/Xtensa/xtensa-float-intrinsics.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple xtensa -O0 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple xtensa -O0 -emit-llvm %s -o - | FileCheck %s typedef __attribute__((ext_vector_type(1))) _Bool xtbool; @@ -36,3 +36,13 @@ float test_mul_s(float a, float b) { // CHECK: %{{.*}} = call float @llvm.xtensa.xt.mul.s(float %{{.*}}, float %{{.*}}) return __builtin_xtensa_xt_mul_s(a, b); } + +float test_xt_lsip(float * a0) { + // CHECK: %{{.*}} = call { float, ptr } @llvm.xtensa.xt.lsip(ptr %{{.*}}, i32 0) + return __builtin_xtensa_xt_lsip(&a0, 0); +} + +float test_xt_lsxp(float * a0, int a1) { + // CHECK: %{{.*}} = call { float, ptr } @llvm.xtensa.xt.lsxp(ptr %{{.*}}, i32 %{{.*}}) + return __builtin_xtensa_xt_lsxp(&a0, a1); +} diff --git a/clang/test/CodeGen/Xtensa/xtensa-gen-intrinsics.c b/clang/test/CodeGen/Xtensa/xtensa-gen-intrinsics.c new file mode 100644 index 00000000000000..2b8de3d7b6d339 --- /dev/null +++ b/clang/test/CodeGen/Xtensa/xtensa-gen-intrinsics.c @@ -0,0 +1,88 @@ +# Fails on Winodws due to incorrectly built command line: `'(': command not found`, so disable it temporarily +# UNSUPPORTED: system-windows + +# RUN: python3 %s > %t && ( %clang_cc1 -Dxtfloat=float -O0 -triple=xtensa %t -o - -emit-llvm | FileCheck %t ) + +FIXTURES = [ +('xtfloat', 'xt_addexp_s', ['xtfloat', 'xtfloat']) , +('xtfloat', 'xt_addexpm_s', ['xtfloat', 'xtfloat']) , +('int', 'xt_ceil_s', ['xtfloat', 0]) , +('xtfloat', 'xt_div0_s', ['xtfloat']) , +('xtfloat', 'xt_divn_s', ['xtfloat', 'xtfloat', 'xtfloat']) , +('int', 'xt_floor_s', ['xtfloat', 0]) , +('xtfloat', 'xt_lsi', ['xtfloat*', 0]) , +('xtfloat', 'xt_lsx', ['xtfloat*', 'int']) , +('xtfloat', 'xt_madd_s', ['xtfloat', 'xtfloat', 'xtfloat']) , +('xtfloat', 'xt_maddn_s', ['xtfloat', 'xtfloat', 'xtfloat']) , +('xtfloat', 'xt_mkdadj_s', ['xtfloat', 'xtfloat']) , +('xtfloat', 'xt_mksadj_s', ['xtfloat']) , +('xtfloat', 'xt_mov_s', ['xtfloat']) , +('xtfloat', 'xt_moveqz_s', ['xtfloat', 'xtfloat', 'int']) , +('xtfloat', 'xt_movgez_s', ['xtfloat', 'xtfloat', 'int']) , +('xtfloat', 'xt_movltz_s', ['xtfloat', 'xtfloat', 'int']) , +('xtfloat', 'xt_movnez_s', ['xtfloat', 'xtfloat', 'int']) , +('xtfloat', 'xt_msub_s', ['xtfloat', 'xtfloat', 'xtfloat']) , +('xtfloat', 'xt_neg_s', ['xtfloat']) , +('xtfloat', 'xt_nexp01_s', ['xtfloat']) , +('xtfloat', 'xt_recip0_s', ['xtfloat']) , +('int', 'xt_rfr', ['xtfloat']) , +('int', 'xt_round_s', ['xtfloat', 0]) , +('xtfloat', 'xt_rsqrt0_s', ['xtfloat']) , +('int', 'xt_rur_fcr', []) , +('int', 'xt_rur_fsr', []) , +('xtfloat', 'xt_sqrt0_s', ['xtfloat']) , +('void', 'xt_ssi', ['xtfloat', 'xtfloat*', 0]) , +('xtfloat*', 'xt_ssip', ['xtfloat', 'xtfloat*', 0]) , +('void', 'xt_ssx', ['xtfloat', 'xtfloat*', 'int']) , +('xtfloat*', 'xt_ssxp', ['xtfloat', 'xtfloat*', 'int']) , +('xtfloat', 'xt_wfr', ['int']) , +('void', 'xt_wur_fcr', ['int']) , +('void', 'xt_wur_fsr', ['int']) , +] + +from dataclasses import dataclass + +TYPES = { + 'xtfloat' : 'float', + 'int' : 'i32', + 'void':'void' +} + +def ctype2llvm(typ): + if '*' in typ: + return 'ptr' + else: + return TYPES[typ] + + +template = """ +{ret} test_{fun}({fun_args}) {{ + // CHECK: {assign} call {llvm_ret} @llvm.xtensa.{builtin}({llvm_args}) + return __builtin_xtensa_{fun}({call_args}); +}} +""" + +@dataclass +class F: + ret: str + fun : str + args: [str] + #builtin + #llvm_ret + #llvm_args + #call_args + +for f in FIXTURES: + f = F(*f) + args = f.args + f.fun_args = ", ".join( + ['%s a%d' % (a,i) for i,a, in enumerate(args) if isinstance(a,str)]) + f.builtin = f.fun.replace('_','.') + f.llvm_args = ", ".join( + [('%s {{.*}}' % ctype2llvm(a)) if isinstance(a,str) else ('i32 %d' % a) + for i,a, in enumerate(args)]) + f.call_args = ", ".join(['a%d' % i if isinstance(a,str) else str(a) + for i,a in enumerate(args)]) + f.llvm_ret = ctype2llvm(f.ret) + f.assign = '' if f.ret == 'void' else '{{.*}} =' + print(template.format(**f.__dict__)) diff --git a/llvm/include/llvm/IR/IntrinsicsXtensa.td b/llvm/include/llvm/IR/IntrinsicsXtensa.td index 2b9c8dd62cb7c6..36b9571ee4b4b3 100644 --- a/llvm/include/llvm/IR/IntrinsicsXtensa.td +++ b/llvm/include/llvm/IR/IntrinsicsXtensa.td @@ -303,6 +303,117 @@ def int_xtensa_xt_float_s: ClangBuiltin<"__builtin_xtensa_xt_float_s">, def int_xtensa_xt_ufloat_s: ClangBuiltin<"__builtin_xtensa_xt_ufloat_s">, Intrinsic<[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; +def int_xtensa_xt_addexp_s: ClangBuiltin<"__builtin_xtensa_xt_addexp_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_addexpm_s: ClangBuiltin<"__builtin_xtensa_xt_addexpm_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_ceil_s: ClangBuiltin<"__builtin_xtensa_xt_ceil_s">, + Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_xt_conjc_s: ClangBuiltin<"__builtin_xtensa_xt_conjc_s">, + Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty], [IntrNoMem]>; + +def int_xtensa_xt_div0_s: ClangBuiltin<"__builtin_xtensa_xt_div0_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_divn_s: ClangBuiltin<"__builtin_xtensa_xt_divn_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_floor_s: ClangBuiltin<"__builtin_xtensa_xt_floor_s">, + Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_xt_lsi: ClangBuiltin<"__builtin_xtensa_xt_lsi">, + Intrinsic<[llvm_float_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_xt_lsip: + Intrinsic<[llvm_float_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_xt_lsx: ClangBuiltin<"__builtin_xtensa_xt_lsx">, + Intrinsic<[llvm_float_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_xt_lsxp: + Intrinsic<[llvm_float_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_xt_madd_s: ClangBuiltin<"__builtin_xtensa_xt_madd_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_maddn_s: ClangBuiltin<"__builtin_xtensa_xt_maddn_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_mkdadj_s: ClangBuiltin<"__builtin_xtensa_xt_mkdadj_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_mksadj_s: ClangBuiltin<"__builtin_xtensa_xt_mksadj_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_mov_s: ClangBuiltin<"__builtin_xtensa_xt_mov_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_moveqz_s: ClangBuiltin<"__builtin_xtensa_xt_moveqz_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_xt_movgez_s: ClangBuiltin<"__builtin_xtensa_xt_movgez_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_xt_movltz_s: ClangBuiltin<"__builtin_xtensa_xt_movltz_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_xt_movnez_s: ClangBuiltin<"__builtin_xtensa_xt_movnez_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_xt_msub_s: ClangBuiltin<"__builtin_xtensa_xt_msub_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_neg_s: ClangBuiltin<"__builtin_xtensa_xt_neg_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_nexp01_s: ClangBuiltin<"__builtin_xtensa_xt_nexp01_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_recip0_s: ClangBuiltin<"__builtin_xtensa_xt_recip0_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_rfr: ClangBuiltin<"__builtin_xtensa_xt_rfr">, + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_round_s: ClangBuiltin<"__builtin_xtensa_xt_round_s">, + Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_xt_rsqrt0_s: ClangBuiltin<"__builtin_xtensa_xt_rsqrt0_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_rur_fcr: ClangBuiltin<"__builtin_xtensa_xt_rur_fcr">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_xt_rur_fsr: ClangBuiltin<"__builtin_xtensa_xt_rur_fsr">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_xt_sqrt0_s: ClangBuiltin<"__builtin_xtensa_xt_sqrt0_s">, + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; + +def int_xtensa_xt_ssi: ClangBuiltin<"__builtin_xtensa_xt_ssi">, + Intrinsic<[], [llvm_float_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_xt_ssip: ClangBuiltin<"__builtin_xtensa_xt_ssip">, + Intrinsic<[llvm_ptr_ty], [llvm_float_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_xt_ssx: ClangBuiltin<"__builtin_xtensa_xt_ssx">, + Intrinsic<[], [llvm_float_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_xt_ssxp: ClangBuiltin<"__builtin_xtensa_xt_ssxp">, + Intrinsic<[llvm_ptr_ty], [llvm_float_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_xt_wfr: ClangBuiltin<"__builtin_xtensa_xt_wfr">, + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_xt_wur_fcr: ClangBuiltin<"__builtin_xtensa_xt_wur_fcr">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_xt_wur_fsr: ClangBuiltin<"__builtin_xtensa_xt_wur_fsr">, + Intrinsic<[], [llvm_i32_ty], []>; + // Generated code // --------------- include "llvm/IR/IntrinsicsXtensaESP32S3.td" diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 8ea0991b5040ed..5d76b2c88fead9 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -564,6 +564,14 @@ static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeOffset8m32Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm << 2)); + return MCDisassembler::Success; +} + static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 185507a93c410f..958dedbaaa2e51 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -123,6 +123,10 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + uint32_t getOffset8m32OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + uint32_t getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -518,6 +522,18 @@ XtensaMCCodeEmitter::getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo, return Res & 0x3f; } +uint32_t +XtensaMCCodeEmitter::getOffset8m32OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint32_t Res = static_cast(MO.getImm()); + + assert(((Res & 0x3) == 0) && "Unexpected operand value!"); + + return Res; +} + uint32_t XtensaMCCodeEmitter::getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index f702142e2d15ec..0e5dd349c2fcfb 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -383,6 +383,41 @@ void XtensaDAGToDAGISel::Select(SDNode *Node) { } break; } + + case ISD::INTRINSIC_W_CHAIN: { + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + unsigned OpCode = 0; + bool Skip = false; + + switch (IntNo) { + default: + Skip = true; + break; + case Intrinsic::xtensa_xt_lsxp: + OpCode = Xtensa::LSXP; + break; + case Intrinsic::xtensa_xt_lsip: + OpCode = Xtensa::LSIP; + break; + } + if (Skip) + break; + + SDValue Chain = Node->getOperand(0); + + auto ResTys = Node->getVTList(); + + SmallVector Ops; + for (unsigned i = 2; i < Node->getNumOperands(); i++) + Ops.push_back(Node->getOperand(i)); + Ops.push_back(Chain); + + SDNode *NewNode = CurDAG->getMachineNode(OpCode, DL, ResTys, Ops); + + ReplaceNode(Node, NewNode); + return; + } + default: break; } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 7fa83454a7cfd7..304ad799703ba3 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -3424,9 +3424,11 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( case Xtensa::LSIP: case Xtensa::LSX: case Xtensa::LSXP: { - const MachineMemOperand &MMO = **MI.memoperands_begin(); - if (MMO.isVolatile()) { - BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW)); + if (MI.memoperands().size() > 0) { + const MachineMemOperand &MMO = **MI.memoperands_begin(); + if (MMO.isVolatile()) { + BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW)); + } } return MBB; } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index df6b50930cb52a..935ea605e3eb48 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -651,6 +651,20 @@ def RUR : RRR_Inst<0x00, 0x03, 0x0E, (outs AR:$r), (ins UR:$ur), let t = ur{3-0}; } +def WUR_FCR :RRR_Inst<0x00, 0x03, 0x0F, (outs), (ins AR:$t), + "wur.fcr \t$t", []> { + let r = 232{7-4}; + let s = 232{3-0}; + let Defs = [FCR]; +} + +def WUR_FSR :RRR_Inst<0x00, 0x03, 0x0F, (outs), (ins AR:$t), + "wur.fsr\t $t", []> { + let r = 233{7-4}; + let s = 233{3-0}; + let Defs = [FSR]; +} + //===----------------------------------------------------------------------===// // External Registers read/write instructions //===----------------------------------------------------------------------===// @@ -1054,20 +1068,22 @@ let mayLoad = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { let s{3-0} = addr{3-0}; } - def LSIP : RRI8_Inst<0x03, (outs FPR:$t), (ins mem32:$addr), - "lsip\t$t, $addr", []> { - bits<12> addr; + def LSIP : RRI8_Inst<0x03, (outs FPR:$t, AR:$ds), (ins AR:$s, offset8m32:$off), + "lsip\t$t, $s, $off", []> { + bits<10> off; let r = 0x08; - let imm8{7-0} = addr{11-4}; - let s{3-0} = addr{3-0}; + let imm8{7-0} = off{9-2}; + let Constraints = "$ds = $s,@earlyclobber $ds"; } - def LSX : RRR_Inst<0x00, 0x08, 0x00, (outs), (ins FPR:$r, AR:$s, AR:$t), + def LSX : RRR_Inst<0x00, 0x08, 0x00, (outs FPR:$r), (ins AR:$s, AR:$t), "lsx\t$r, $s, $t", []>; - def LSXP : RRR_Inst<0x00, 0x08, 0x01, (outs), (ins FPR:$r, AR:$s, AR:$t), - "lsxp\t$r, $s, $t", []>; + def LSXP : RRR_Inst<0x00, 0x08, 0x01, (outs FPR:$r, AR:$ds), (ins AR:$s, AR:$t), + "lsxp\t$r, $s, $t", []> { + let Constraints = "$ds = $s,@earlyclobber $ds"; + } } def : Pat<(f32 (load addr_ish4:$addr)), (f32 (LSI mem32:$addr))>; @@ -1083,20 +1099,22 @@ let mayStore = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in { let s{3-0} = addr{3-0}; } - def SSIP : RRI8_Inst<0x03, (outs), (ins FPR:$t, mem32:$addr), - "ssip\t$t, $addr", []> { - bits<12> addr; + def SSIP : RRI8_Inst<0x03, (outs AR:$ds), (ins FPR:$t, AR:$s, offset8m32:$off), + "ssip\t$t, $s, $off", []> { + bits<10> off; let r = 0x0C; - let imm8{7-0} = addr{11-4}; - let s{3-0} = addr{3-0}; + let imm8{7-0} = off{9-2}; + let Constraints = "$ds = $s,@earlyclobber $ds"; } def SSX: RRR_Inst<0x00, 0x08, 0x04, (outs), (ins FPR:$r, AR:$s, AR:$t), "ssx\t$r, $s, $t", []>; - def SSXP: RRR_Inst<0x00, 0x08, 0x05, (outs), (ins FPR:$r, AR:$s, AR:$t), - "ssxp\t$r, $s, $t", []>; + def SSXP: RRR_Inst<0x00, 0x08, 0x05, (outs AR:$ds), (ins FPR:$r, AR:$s, AR:$t), + "ssxp\t$r, $s, $t", []> { + let Constraints = "$ds = $s,@earlyclobber $ds"; + } } def : Pat<(store FPR:$t, addr_ish4:$addr), (SSI FPR:$t, mem32:$addr)>; @@ -1145,15 +1163,18 @@ def : Pat<(f32 (int_xtensa_xt_abs_s FPR:$frs)), (ABS_S FPR:$frs)>, Requires<[HasSingleFloat]>; -def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), +let Constraints = "$dr = $r,@earlyclobber $dr" in { + +def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$dr), (ins FPR:$r, FPR:$s), "addexp.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0E; } -def ADDEXPM_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), +def ADDEXPM_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$dr), (ins FPR:$r, FPR:$s), "addexpm.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0F; } +} def CEIL_S : RRR_Inst<0x00, 0x0A, 0x0B, (outs AR:$r), (ins FPR:$s, uimm4:$imm), "ceil.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { @@ -1175,8 +1196,10 @@ def DIV0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), let t = 0x7; } -def DIVN_S : RRR_Inst<0x00, 0x0A, 0x07, (outs FPR:$r), (ins FPR:$s, FPR:$t), - "divn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; +def DIVN_S : RRR_Inst<0x00, 0x0A, 0x07, (outs FPR:$dr), (ins FPR:$r, FPR:$s, FPR:$t), + "divn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]> { +let Constraints = "$dr = $r,@earlyclobber $dr"; +} def FLOAT_S : RRR_Inst<0x00, 0x0A, 0x0c, (outs FPR:$r), (ins AR:$s, uimm4:$imm), "float.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> { @@ -1218,9 +1241,10 @@ def MADD_S : RRR_Inst<0x00, 0x0A, 0x04, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR: def : Pat<(fma FPR:$r1, FPR:$r2, FPR:$r3), (MADD_S $r3, $r1, $r2)>; -def MKDADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), +def MKDADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$dr), (ins FPR:$r, FPR:$s), "mkdadj.s\t$r, $s", []>, Requires<[HasSingleFloat]> { let t = 0x0D; + let Constraints = "$dr = $r,@earlyclobber $dr"; } def MKSADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s), @@ -1235,19 +1259,20 @@ def MOV_S : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins FPR:$s), let t = 0x00; } -def MOVEQZ_S : RRR_Inst<0x00, 0x0B, 0x08, (outs FPR:$r), (ins FPR:$s, AR:$t), - "moveqz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; +let Constraints = "$dr = $r,@earlyclobber $dr" in { + + def MOVEQZ_S : RRR_Inst<0x00, 0x0B, 0x08, (outs FPR:$dr), (ins FPR:$r, FPR:$s, AR:$t), + "moveqz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; -def MOVGEZ_S : RRR_Inst<0x00, 0x0B, 0x0B, (outs FPR:$r), (ins FPR:$s, AR:$t), - "movgez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; + def MOVGEZ_S : RRR_Inst<0x00, 0x0B, 0x0B, (outs FPR:$dr), (ins FPR:$r, FPR:$s, AR:$t), + "movgez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; -def MOVLTZ_S : RRR_Inst<0x00, 0x0B, 0x0A, (outs FPR:$r), (ins FPR:$s, AR:$t), - "movltz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; + def MOVLTZ_S : RRR_Inst<0x00, 0x0B, 0x0A, (outs FPR:$dr), (ins FPR:$r, FPR:$s, AR:$t), + "movltz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; -def MOVNEZ_S : RRR_Inst<0x00, 0x0B, 0x09, (outs FPR:$r), (ins FPR:$s, AR:$t), - "movnez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; + def MOVNEZ_S : RRR_Inst<0x00, 0x0B, 0x09, (outs FPR:$dr), (ins FPR:$r, FPR:$s, AR:$t), + "movnez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>; -let Constraints = "$dr = $r,@earlyclobber $dr" in { def MOVT_S : RRR_Inst<0x00, 0x0B, 0x0D, (outs FPR:$dr), (ins FPR:$r, FPR:$s, BR:$t), "movt.s\t$r, $s, $t", [(set FPR:$dr, (int_xtensa_xt_movt_s FPR:$r, FPR:$s, BR:$t))]>, @@ -1868,6 +1893,115 @@ let Predicates = [HasESP32S3Ops] in { } include "XtensaS3DSPInstrInfo.td" + +//===----------------------------------------------------------------------===// +// FP intrinsic patterns +//===----------------------------------------------------------------------===// +let Predicates = [HasSingleFloat] in { + + def ADDEXP_S_PAT :Pat<(f32 (int_xtensa_xt_addexp_s FPR:$frr, FPR:$frs)), + (ADDEXP_S FPR:$frr, FPR:$frs)>; + + def ADDEXPM_S_PAT :Pat<(f32 (int_xtensa_xt_addexpm_s FPR:$frr, FPR:$frs)), + (ADDEXPM_S FPR:$frr, FPR:$frs)>; + + def CEIL_S_PAT :Pat<(i32 (int_xtensa_xt_ceil_s FPR:$frs, timm:$imm_t)), + (CEIL_S FPR:$frs, timm:$imm_t)>; + + def DIV0_S_PAT :Pat<(f32 (int_xtensa_xt_div0_s FPR:$frs)), + (DIV0_S FPR:$frs)>; + + def DIVN_S_PAT :Pat<(f32 (int_xtensa_xt_divn_s FPR:$frr, FPR:$frs, FPR:$frt)), + (DIVN_S FPR:$frr, FPR:$frs, FPR:$frt)>; + + def FLOOR_S_PAT :Pat<(i32 (int_xtensa_xt_floor_s FPR:$frs, timm:$imm_t)), + (FLOOR_S FPR:$frs, timm:$imm_t)>; + + def LSI_PAT :Pat<(f32 (int_xtensa_xt_lsi AR:$ars, timm:$imm8x4)), + (LSI AR:$ars, timm:$imm8x4)>; + + def LSX_PAT :Pat<(f32 (int_xtensa_xt_lsx AR:$ars, AR:$art)), + (LSX AR:$ars, AR:$art)>; + + def MADD_S_PAT :Pat<(f32 (int_xtensa_xt_madd_s FPR:$frr, FPR:$frs, FPR:$frt)), + (MADD_S FPR:$frr, FPR:$frs, FPR:$frt)>; + + def MADDN_S_PAT :Pat<(f32 (int_xtensa_xt_maddn_s FPR:$frr, FPR:$frs, FPR:$frt)), + (MADDN_S FPR:$frr, FPR:$frs, FPR:$frt)>; + + def MKDADJ_S_PAT :Pat<(f32 (int_xtensa_xt_mkdadj_s FPR:$frr, FPR:$frs)), + (MKDADJ_S FPR:$frr, FPR:$frs)>; + + def MKSADJ_S_PAT :Pat<(f32 (int_xtensa_xt_mksadj_s FPR:$frs)), + (MKSADJ_S FPR:$frs)>; + + def MOV_S_PAT :Pat<(f32 (int_xtensa_xt_mov_s FPR:$frs)), + (MOV_S FPR:$frs)>; + + def MOVEQZ_S_PAT :Pat<(f32 (int_xtensa_xt_moveqz_s FPR:$frr, FPR:$frs, AR:$art)), + (MOVEQZ_S FPR:$frr, FPR:$frs, AR:$art)>; + + def MOVGEZ_S_PAT :Pat<(f32 (int_xtensa_xt_movgez_s FPR:$frr, FPR:$frs, AR:$art)), + (MOVGEZ_S FPR:$frr, FPR:$frs, AR:$art)>; + + def MOVLTZ_S_PAT :Pat<(f32 (int_xtensa_xt_movltz_s FPR:$frr, FPR:$frs, AR:$art)), + (MOVLTZ_S FPR:$frr, FPR:$frs, AR:$art)>; + + def MOVNEZ_S_PAT :Pat<(f32 (int_xtensa_xt_movnez_s FPR:$frr, FPR:$frs, AR:$art)), + (MOVNEZ_S FPR:$frr, FPR:$frs, AR:$art)>; + + def MSUB_S_PAT :Pat<(f32 (int_xtensa_xt_msub_s FPR:$frr, FPR:$frs, FPR:$frt)), + (MSUB_S FPR:$frr, FPR:$frs, FPR:$frt)>; + + def NEG_S_PAT :Pat<(f32 (int_xtensa_xt_neg_s FPR:$frs)), + (NEG_S FPR:$frs)>; + + def NEXP01_S_PAT :Pat<(f32 (int_xtensa_xt_nexp01_s FPR:$frs)), + (NEXP01_S FPR:$frs)>; + + def RECIP0_S_PAT :Pat<(f32 (int_xtensa_xt_recip0_s FPR:$frs)), + (RECIP0_S FPR:$frs)>; + + def RFR_PAT :Pat<(i32 (int_xtensa_xt_rfr FPR:$frs)), + (RFR FPR:$frs)>; + + def ROUND_S_PAT :Pat<(i32 (int_xtensa_xt_round_s FPR:$frs, timm:$imm_t)), + (ROUND_S FPR:$frs, timm:$imm_t)>; + + def RSQRT0_S_PAT :Pat<(f32 (int_xtensa_xt_rsqrt0_s FPR:$frs)), + (RSQRT0_S FPR:$frs)>; + + def RUR_FCR_PAT :Pat<(i32 (int_xtensa_xt_rur_fcr )), + (RUR FCR)>; + + def RUR_FSR_PAT :Pat<(i32 (int_xtensa_xt_rur_fsr )), + (RUR FSR )>; + + def SQRT0_S_PAT :Pat<(f32 (int_xtensa_xt_sqrt0_s FPR:$frs)), + (SQRT0_S FPR:$frs)>; + + def SSI_PAT :Pat<(int_xtensa_xt_ssi FPR:$frt, AR:$ars, timm:$imm8x4), + (SSI FPR:$frt, AR:$ars, timm:$imm8x4)>; + + def SSIP_PAT :Pat<(i32 (int_xtensa_xt_ssip FPR:$frt, AR:$ars, timm:$imm8x4)), + (SSIP FPR:$frt, AR:$ars, timm:$imm8x4)>; + + def SSX_PAT :Pat<(int_xtensa_xt_ssx FPR:$frr, AR:$ars, AR:$art), + (SSX FPR:$frr, AR:$ars, AR:$art)>; + + def SSXP_PAT :Pat<(i32 (int_xtensa_xt_ssxp FPR:$frr, AR:$ars, AR:$art)), + (SSXP FPR:$frr, AR:$ars, AR:$art)>; + + def WFR_PAT :Pat<(f32 (int_xtensa_xt_wfr AR:$ars)), + (WFR AR:$ars)>; + + def WUR_FCR_PAT :Pat<(int_xtensa_xt_wur_fcr AR:$art), + (WUR_FCR AR:$art)>; + + def WUR_FSR_PAT :Pat<(int_xtensa_xt_wur_fsr AR:$art), + (WUR_FSR AR:$art)>; + +} //===----------------------------------------------------------------------===// // DSP Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 6a9bf514be8d3a..ad22bac40ea764 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -123,7 +123,10 @@ def offset8m16 : Immediate; def offset8m32 : Immediate= 0 && Imm <= 1020 && (Imm & 0x3 == 0); }], - "Offset8m32_AsmOperand">; + "Offset8m32_AsmOperand"> { + let EncoderMethod = "getOffset8m32OpValue"; + let DecoderMethod = "decodeOffset8m32Operand"; +} // Memory offset 0..60 for 32-bit memory accesses def Offset4m32_AsmOperand : ImmAsmOperand<"Offset4m32">; diff --git a/llvm/test/CodeGen/Xtensa/xtensa-float-intrinsics.ll b/llvm/test/CodeGen/Xtensa/xtensa-float-intrinsics.ll index 73d54e2a51210e..48d3424a8c62f2 100644 --- a/llvm/test/CodeGen/Xtensa/xtensa-float-intrinsics.ll +++ b/llvm/test/CodeGen/Xtensa/xtensa-float-intrinsics.ll @@ -51,6 +51,24 @@ define float @test_mul_s(float %a, float %b) { ret float %r } +define float @test_lsxp(ptr %a, i32 %b) { + ; CHECK-LABEL: test_lsxp + ; CHECK: lsxp {{f[0-9]+}}, {{a[0-9]+}}, {{a[0-9]+}} + %s = call {float,ptr} @llvm.xtensa.xt.lsxp(ptr %a, i32 %b) + %r = extractvalue {float,ptr} %s , 0 + ret float %r +} + +define float @test_lsip(ptr %a) { + ; CHECK-LABEL: test_lsip + ; CHECK: lsip {{f[0-9]+}}, {{a[0-9]+}}, 4 + %s = call {float,ptr} @llvm.xtensa.xt.lsip(ptr %a, i32 4) + %r = extractvalue {float,ptr} %s , 0 + ret float %r +} + +declare {float,ptr} @llvm.xtensa.xt.lsip(ptr, i32); +declare {float,ptr} @llvm.xtensa.xt.lsxp(ptr, i32); declare float @llvm.xtensa.xt.float.s(i32, i32); declare float @llvm.xtensa.xt.ufloat.s(i32, i32); declare i32 @llvm.xtensa.xt.trunc.s(float , i32); diff --git a/llvm/test/CodeGen/Xtensa/xtensa-gen-intrinsics.ll b/llvm/test/CodeGen/Xtensa/xtensa-gen-intrinsics.ll new file mode 100644 index 00000000000000..e3d3ff9b925163 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-gen-intrinsics.ll @@ -0,0 +1,80 @@ +# RUN: python3 %s > %t && ( llc -O0 -mtriple=xtensa -mcpu=esp32 %t -o - | FileCheck %t ) + +from dataclasses import dataclass + +@dataclass +class F: + ret: str + fun : str + instr: str + args : [str] + +FIXTURES = [ +('float', 'xt_addexp_s', 'addexp.s {{f[0-9]+}}, {{f[0-9]+}}', ['float', 'float']) , +('float', 'xt_addexpm_s', 'addexpm.s {{f[0-9]+}}, {{f[0-9]+}}', ['float', 'float']) , +('i32', 'xt_ceil_s', 'ceil.s {{a[0-9]+}}, {{f[0-9]+}}, 0', ['float', 0]) , +('float', 'xt_div0_s', 'div0.s {{f[0-9]+}}, {{f[0-9]+}}', ['float']) , +('float', 'xt_divn_s', 'divn.s {{f[0-9]+}}, {{f[0-9]+}}, {{f[0-9]+}}', ['float', 'float', 'float']) , +('i32', 'xt_floor_s', 'floor.s {{a[0-9]+}}, {{f[0-9]+}}, 0', ['float', 0]) , +('float', 'xt_lsi', 'lsi {{f[0-9]+}}, {{a[0-9]+}}, 0', ['ptr', 0]) , +# skip xt_lsip , +('float', 'xt_lsx', 'lsx {{f[0-9]+}}, {{a[0-9]+}}, {{a[0-9]+}}', ['ptr', 'i32']) , +# skip xt_lsxp , +('float', 'xt_madd_s', 'madd.s {{f[0-9]+}}, {{f[0-9]+}}, {{f[0-9]+}}', ['float', 'float', 'float']) , +('float', 'xt_maddn_s', 'maddn.s {{f[0-9]+}}, {{f[0-9]+}}, {{f[0-9]+}}', ['float', 'float', 'float']) , +('float', 'xt_mkdadj_s', 'mkdadj.s {{f[0-9]+}}, {{f[0-9]+}}', ['float', 'float']) , +('float', 'xt_mksadj_s', 'mksadj.s {{f[0-9]+}}, {{f[0-9]+}}', ['float']) , +('float', 'xt_mov_s', 'mov.s {{f[0-9]+}}, {{f[0-9]+}}', ['float']) , +('float', 'xt_moveqz_s', 'moveqz.s {{f[0-9]+}}, {{f[0-9]+}}, {{a[0-9]+}}', ['float', 'float', 'i32']) , +('float', 'xt_movgez_s', 'movgez.s {{f[0-9]+}}, {{f[0-9]+}}, {{a[0-9]+}}', ['float', 'float', 'i32']) , +('float', 'xt_movltz_s', 'movltz.s {{f[0-9]+}}, {{f[0-9]+}}, {{a[0-9]+}}', ['float', 'float', 'i32']) , +('float', 'xt_movnez_s', 'movnez.s {{f[0-9]+}}, {{f[0-9]+}}, {{a[0-9]+}}', ['float', 'float', 'i32']) , +('float', 'xt_msub_s', 'msub.s {{f[0-9]+}}, {{f[0-9]+}}, {{f[0-9]+}}', ['float', 'float', 'float']) , +('float', 'xt_neg_s', 'neg.s {{f[0-9]+}}, {{f[0-9]+}}', ['float']) , +('float', 'xt_nexp01_s', 'nexp01.s {{f[0-9]+}}, {{f[0-9]+}}', ['float']) , +('float', 'xt_recip0_s', 'recip0.s {{f[0-9]+}}, {{f[0-9]+}}', ['float']) , +('i32', 'xt_rfr', 'rfr {{a[0-9]+}}, {{f[0-9]+}}', ['float']) , +('i32', 'xt_round_s', 'round.s {{a[0-9]+}}, {{f[0-9]+}}, 0', ['float', 0]) , +('float', 'xt_rsqrt0_s', 'rsqrt0.s {{f[0-9]+}}, {{f[0-9]+}}', ['float']) , +('i32', 'xt_rur_fcr', 'rur {{a[0-9]+}}, fcr', []) , +('i32', 'xt_rur_fsr', 'rur {{a[0-9]+}}, fsr', []) , +('float', 'xt_sqrt0_s', 'sqrt0.s {{f[0-9]+}}, {{f[0-9]+}}', ['float']) , +('void', 'xt_ssi', 'ssi {{f[0-9]+}}, {{a[0-9]+}}, 0', ['float', 'ptr', 0]) , +('ptr', 'xt_ssip', 'ssip {{f[0-9]+}}, {{a[0-9]+}}, 0', ['float', 'ptr', 0]) , +('void', 'xt_ssx', 'ssx {{f[0-9]+}}, {{a[0-9]+}}, {{a[0-9]+}}', ['float', 'ptr', 'i32']) , +('ptr', 'xt_ssxp', 'ssxp {{f[0-9]+}}, {{a[0-9]+}}, {{a[0-9]+}}', ['float', 'ptr', 'i32']) , +('float', 'xt_wfr', 'wfr {{f[0-9]+}}, {{a[0-9]+}}', ['i32']) , +('void', 'xt_wur_fcr', 'wur.fcr {{a[0-9]+}}', ['i32']) , +('void', 'xt_wur_fsr', 'wur.fsr {{a[0-9]+}}', ['i32']) , +] + +template = """ +define {ret} @test_{fun}({fun_args}) {{ + ; CHECK-LABEL: {fun} + ; CHECK: {instr} + {ret_var} {assign} call {ret} @llvm.xtensa.{builtin}({call_args}) + ret {ret} {ret_var} +}} +declare {ret} @llvm.xtensa.{builtin}({call_types}); +""" + +for f in FIXTURES: + if isinstance(f, dict): + f = F(**f) + elif isinstance(f, tuple): + f = F(*f) + args = f.args + f.fun_args = ",".join( + ['%s %%a%d' % (a,i) for i,a, in enumerate(args) if isinstance(a,str)]) + f.builtin = f.fun.replace('_','.') + f.call_args = ",".join( + [('%s %%a%d' % (a, i)) if isinstance(a,str) else ('i32 %d' % a) + for i,a, in enumerate(args)]) + f.call_types = ",".join([a if isinstance(a,str) else 'i32' for a in args]) + if f.ret == 'void': + f.assign = "" + f.ret_var = "" + else: + f.assign = "=" + f.ret_var = "%r" + print(template.format(**f.__dict__)) From e44778080c2ac560d06034fea8aea06dbbf09c3f Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 27 Mar 2023 13:09:06 +0000 Subject: [PATCH 206/261] [Xtensa] Add Cannonlake CPU This patch adds a definition of Xtensa LX6 CPU variant present in Intel Cannonlake and Tigerlake SOC platforms. --- llvm/include/llvm/TargetParser/XtensaTargetParser.def | 7 +++++++ llvm/lib/Target/Xtensa/Xtensa.td | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.def b/llvm/include/llvm/TargetParser/XtensaTargetParser.def index b765b015c12652..3fe9b2760b773c 100644 --- a/llvm/include/llvm/TargetParser/XtensaTargetParser.def +++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.def @@ -73,6 +73,13 @@ XTENSA_CPU(ESP32S3, {"esp32s3"}, FK_COPROCESSOR | FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S3OPS)) +XTENSA_CPU(CNL, {"cnl"}, (FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN | + FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_S32C1I | + FK_THREADPTR | FK_DIV32 | FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | + FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | + FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR)) + + #undef XTENSA_CPU #ifndef XTENSA_CPU_ALIAS diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 7d03565751e6e9..d3719d7a301236 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -206,6 +206,13 @@ def : Proc<"esp32s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureM FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureMINMAX, FeatureCLAMPS, FeatureESP32S3Ops]>; +def : Proc<"cnl", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureWindowed, FeatureBoolean, + FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureS32C1I, + FeatureTHREADPTR, FeatureDiv32, FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, + FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, + FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, + FeatureRegionProtection, FeatureMiscSR]>; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// From 7215a08ef48d5647e3db28ab176a76839e53ffd4 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Mar 2024 15:40:33 +0300 Subject: [PATCH 207/261] [Xtensa] Make assembler output compatible with GAS Some Xtensa targets may still use GAS as a default assemblwr through -fno-integrated-as option. These changes make the assembly output compatible with GAS by default. - GAS does not recognize .word but .2byte works for both - Dwarf CFI is not supported by GAS. Option -fdwarf-exceptions can still turn it on but there is no option to turn it off, so an opt-in approach is more portable. --- llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp | 3 +-- llvm/test/CodeGen/Xtensa/arith-intrinsics.ll | 2 +- llvm/test/CodeGen/Xtensa/calling-conv-call8.ll | 4 ++-- llvm/test/CodeGen/Xtensa/ctlz-cttz.ll | 2 +- llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll | 2 +- 5 files changed, 6 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp index 4537369b017d0f..1dc3fca572fe8d 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp @@ -23,12 +23,11 @@ XtensaMCAsmInfo::XtensaMCAsmInfo(const Triple &TT) { PrivateGlobalPrefix = ".L"; CommentString = "#"; ZeroDirective = "\t.space\t"; - Data16bitsDirective = "\t.half\t"; + Data16bitsDirective = "\t.2byte\t"; Data32bitsDirective = "\t.word\t"; Data64bitsDirective = "\t.quad\t"; GlobalDirective = "\t.global\t"; UsesELFSectionDirectiveForBSS = true; SupportsDebugInformation = true; - ExceptionsType = ExceptionHandling::DwarfCFI; AlignmentIsInBytes = true; } diff --git a/llvm/test/CodeGen/Xtensa/arith-intrinsics.ll b/llvm/test/CodeGen/Xtensa/arith-intrinsics.ll index c4a0749a0ed1e9..ee492583bd72da 100644 --- a/llvm/test/CodeGen/Xtensa/arith-intrinsics.ll +++ b/llvm/test/CodeGen/Xtensa/arith-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=xtensa -mcpu=esp32 --exception-model=dwarf -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=XTENSA %s declare i32 @llvm.abs.i32(i32, i1) diff --git a/llvm/test/CodeGen/Xtensa/calling-conv-call8.ll b/llvm/test/CodeGen/Xtensa/calling-conv-call8.ll index 16056b99101fb8..5ad2d4e471fc24 100644 --- a/llvm/test/CodeGen/Xtensa/calling-conv-call8.ll +++ b/llvm/test/CodeGen/Xtensa/calling-conv-call8.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=xtensa -mcpu=esp32 -O1 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs --exception-model=dwarf < %s \ ; RUN: | FileCheck -check-prefix=XTENSA-STRUCT16 %s -; RUN: llc -mtriple=xtensa -mcpu=esp32 -O1 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs --exception-model=dwarf < %s \ ; RUN: | FileCheck -check-prefix=XTENSA-I128 %s %struct.S = type { [4 x i32] } diff --git a/llvm/test/CodeGen/Xtensa/ctlz-cttz.ll b/llvm/test/CodeGen/Xtensa/ctlz-cttz.ll index 8008ba354e6ab8..a265b1f79913a4 100644 --- a/llvm/test/CodeGen/Xtensa/ctlz-cttz.ll +++ b/llvm/test/CodeGen/Xtensa/ctlz-cttz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=xtensa -mcpu=esp32 --exception-model=dwarf -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=XTENSA %s declare i32 @llvm.ctlz.i32(i32, i1) diff --git a/llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll b/llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll index e6faa89c0ec592..0206120729abe3 100644 --- a/llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll +++ b/llvm/test/CodeGen/Xtensa/minmax-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=xtensa -mcpu=esp32 --exception-model=dwarf -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=XTENSA %s declare i32 @llvm.smin.i32(i32, i32) From ab4deb3323287a661332aa7a5d9589d91961b1ff Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 10:17:18 +0000 Subject: [PATCH 208/261] [Xtensa] Add HIFI3 intrinsic functions --- llvm/include/llvm/IR/IntrinsicsXtensa.td | 19 + llvm/include/llvm/IR/IntrinsicsXtensaHIFI.td | 2613 ++++++++++++++++++ 2 files changed, 2632 insertions(+) create mode 100644 llvm/include/llvm/IR/IntrinsicsXtensaHIFI.td diff --git a/llvm/include/llvm/IR/IntrinsicsXtensa.td b/llvm/include/llvm/IR/IntrinsicsXtensa.td index 36b9571ee4b4b3..e805a02f624554 100644 --- a/llvm/include/llvm/IR/IntrinsicsXtensa.td +++ b/llvm/include/llvm/IR/IntrinsicsXtensa.td @@ -417,4 +417,23 @@ def int_xtensa_xt_wur_fsr: ClangBuiltin<"__builtin_xtensa_xt_wur_fsr">, // Generated code // --------------- include "llvm/IR/IntrinsicsXtensaESP32S3.td" + +//===----------------------------------------------------------------------===// +// HiFi3 Intrinsics +//===----------------------------------------------------------------------===// + +//Extended Access +def int_xtensa_xt_l32ex: ClangBuiltin<"__builtin_xtensa_xt_l32ex">, + Intrinsic<[llvm_i32_ty], [LLVMQualPointerType<0>],[]>; + +def int_xtensa_xt_s32ex: + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, LLVMQualPointerType<0>],[]>; + +def int_xtensa_xt_getex: + Intrinsic<[llvm_i32_ty], [llvm_i32_ty],[]>; + +def int_xtensa_xt_clrex: ClangBuiltin<"__builtin_xtensa_xt_clrex">, + Intrinsic<[], [],[]>; + +include "llvm/IR/IntrinsicsXtensaHIFI.td" } diff --git a/llvm/include/llvm/IR/IntrinsicsXtensaHIFI.td b/llvm/include/llvm/IR/IntrinsicsXtensaHIFI.td new file mode 100644 index 00000000000000..662e942829cc8b --- /dev/null +++ b/llvm/include/llvm/IR/IntrinsicsXtensaHIFI.td @@ -0,0 +1,2613 @@ +//===- IntrinsicsXtensaHIFI.td - Defines Xtensa HIFI intrinsics -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the intrinsics for Xtensa HIFI extension. +// +//===----------------------------------------------------------------------===// + +def int_xtensa_ae_abs16s: ClangBuiltin<"__builtin_xtensa_ae_abs16s">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_abs24s: ClangBuiltin<"__builtin_xtensa_ae_abs24s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_abs32: ClangBuiltin<"__builtin_xtensa_ae_abs32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_abs32s: ClangBuiltin<"__builtin_xtensa_ae_abs32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_abs64: ClangBuiltin<"__builtin_xtensa_ae_abs64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_abs64s: ClangBuiltin<"__builtin_xtensa_ae_abs64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_add16: ClangBuiltin<"__builtin_xtensa_ae_add16">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_add16s: ClangBuiltin<"__builtin_xtensa_ae_add16s">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_add24s: ClangBuiltin<"__builtin_xtensa_ae_add24s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_add32: ClangBuiltin<"__builtin_xtensa_ae_add32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_add32_hl_lh: ClangBuiltin<"__builtin_xtensa_ae_add32_hl_lh">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_add32s: ClangBuiltin<"__builtin_xtensa_ae_add32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_add64: ClangBuiltin<"__builtin_xtensa_ae_add64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_add64s: ClangBuiltin<"__builtin_xtensa_ae_add64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_addbrba32: ClangBuiltin<"__builtin_xtensa_ae_addbrba32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_addsub32: ClangBuiltin<"__builtin_xtensa_ae_addsub32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_addsub32s: ClangBuiltin<"__builtin_xtensa_ae_addsub32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_and: ClangBuiltin<"__builtin_xtensa_ae_and">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvt32x2f16_10: ClangBuiltin<"__builtin_xtensa_ae_cvt32x2f16_10">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvt32x2f16_32: ClangBuiltin<"__builtin_xtensa_ae_cvt32x2f16_32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvt48a32: ClangBuiltin<"__builtin_xtensa_ae_cvt48a32">, + Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvt64a32: ClangBuiltin<"__builtin_xtensa_ae_cvt64a32">, + Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvt64f32_h: ClangBuiltin<"__builtin_xtensa_ae_cvt64f32_h">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvta32f24s_h: ClangBuiltin<"__builtin_xtensa_ae_cvta32f24s_h">, + Intrinsic<[llvm_i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvta32f24s_l: ClangBuiltin<"__builtin_xtensa_ae_cvta32f24s_l">, + Intrinsic<[llvm_i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvtq56a32s: ClangBuiltin<"__builtin_xtensa_ae_cvtq56a32s">, + Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvtq56p32s_h: ClangBuiltin<"__builtin_xtensa_ae_cvtq56p32s_h">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_cvtq56p32s_l: ClangBuiltin<"__builtin_xtensa_ae_cvtq56p32s_l">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_db: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_db_ic: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_db_ip: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_dbi: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_dbi_ic: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_dbi_ip: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_div64d32_h: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_div64d32_l: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_eq16: + Intrinsic<[llvm_v4i1_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_eq32: + Intrinsic<[llvm_v2i1_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_eq64: + Intrinsic<[llvm_v1i1_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_l16_i: ClangBuiltin<"__builtin_xtensa_ae_l16_i">, + Intrinsic<[llvm_v4i16_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l16_ip: + Intrinsic<[llvm_v4i16_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l16_x: ClangBuiltin<"__builtin_xtensa_ae_l16_x">, + Intrinsic<[llvm_v4i16_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16_xc: + Intrinsic<[llvm_v4i16_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16_xp: + Intrinsic<[llvm_v4i16_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16m_i: ClangBuiltin<"__builtin_xtensa_ae_l16m_i">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l16m_iu: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l16m_x: ClangBuiltin<"__builtin_xtensa_ae_l16m_x">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16m_xc: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16m_xu: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16x2m_i: ClangBuiltin<"__builtin_xtensa_ae_l16x2m_i">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l16x2m_iu: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l16x2m_x: ClangBuiltin<"__builtin_xtensa_ae_l16x2m_x">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16x2m_xc: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16x2m_xu: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16x4_i: ClangBuiltin<"__builtin_xtensa_ae_l16x4_i">, + Intrinsic<[llvm_v4i16_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l16x4_ip: + Intrinsic<[llvm_v4i16_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l16x4_ric: + Intrinsic<[llvm_v4i16_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_l16x4_rip: + Intrinsic<[llvm_v4i16_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_l16x4_x: ClangBuiltin<"__builtin_xtensa_ae_l16x4_x">, + Intrinsic<[llvm_v4i16_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16x4_xc: + Intrinsic<[llvm_v4i16_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l16x4_xp: + Intrinsic<[llvm_v4i16_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32_i: ClangBuiltin<"__builtin_xtensa_ae_l32_i">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32_ip: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32_x: ClangBuiltin<"__builtin_xtensa_ae_l32_x">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32_xc: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32_xp: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32f24_i: ClangBuiltin<"__builtin_xtensa_ae_l32f24_i">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32f24_ip: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32f24_x: ClangBuiltin<"__builtin_xtensa_ae_l32f24_x">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32f24_xc: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32f24_xp: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32m_i: ClangBuiltin<"__builtin_xtensa_ae_l32m_i">, + Intrinsic<[llvm_v1i64_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32m_iu: + Intrinsic<[llvm_v1i64_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32m_x: ClangBuiltin<"__builtin_xtensa_ae_l32m_x">, + Intrinsic<[llvm_v1i64_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32m_xc: + Intrinsic<[llvm_v1i64_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32m_xu: + Intrinsic<[llvm_v1i64_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32x2_i: ClangBuiltin<"__builtin_xtensa_ae_l32x2_i">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32x2_ip: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32x2_ric: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_l32x2_rip: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_l32x2_x: ClangBuiltin<"__builtin_xtensa_ae_l32x2_x">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32x2_xc: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32x2_xp: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32x2f24_i: ClangBuiltin<"__builtin_xtensa_ae_l32x2f24_i">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32x2f24_ip: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l32x2f24_ric: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_l32x2f24_rip: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_l32x2f24_x: ClangBuiltin<"__builtin_xtensa_ae_l32x2f24_x">, + Intrinsic<[llvm_v2i32_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32x2f24_xc: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l32x2f24_xp: + Intrinsic<[llvm_v2i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l64_i: ClangBuiltin<"__builtin_xtensa_ae_l64_i">, + Intrinsic<[llvm_v1i64_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l64_ip: + Intrinsic<[llvm_v1i64_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_l64_x: ClangBuiltin<"__builtin_xtensa_ae_l64_x">, + Intrinsic<[llvm_v1i64_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l64_xc: + Intrinsic<[llvm_v1i64_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_l64_xp: + Intrinsic<[llvm_v1i64_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_la16x4_ic: + Intrinsic<[llvm_v4i16_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la16x4_ip: + Intrinsic<[llvm_v4i16_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la16x4_ric: + Intrinsic<[llvm_v4i16_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la16x4_rip: + Intrinsic<[llvm_v4i16_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la16x4neg_pc: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_la16x4pos_pc: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_la24_ic: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la24_ip: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la24_ric: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la24_rip: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la24neg_pc: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_la24pos_pc: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_la24x2_ic: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la24x2_ip: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la24x2_ric: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la24x2_rip: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la24x2neg_pc: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_la24x2pos_pc: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2_ic: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2_ip: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2_ric: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2_rip: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2f24_ic: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2f24_ip: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2f24_ric: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2f24_rip: + Intrinsic<[llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2neg_pc: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_la32x2pos_pc: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_la64_pp: ClangBuiltin<"__builtin_xtensa_ae_la64_pp">, + Intrinsic<[llvm_v8i8_ty], [llvm_ptr_ty], []>; + +def int_xtensa_ae_lalign64_i: ClangBuiltin<"__builtin_xtensa_ae_lalign64_i">, + Intrinsic<[llvm_v8i8_ty], [llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_lb: ClangBuiltin<"__builtin_xtensa_ae_lb">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_lbi: ClangBuiltin<"__builtin_xtensa_ae_lbi">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_lbk: ClangBuiltin<"__builtin_xtensa_ae_lbk">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_lbki: ClangBuiltin<"__builtin_xtensa_ae_lbki">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_lbs: ClangBuiltin<"__builtin_xtensa_ae_lbs">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_lbsi: ClangBuiltin<"__builtin_xtensa_ae_lbsi">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_le16: + Intrinsic<[llvm_v4i1_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_le32: + Intrinsic<[llvm_v2i1_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_le64: + Intrinsic<[llvm_v1i1_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_lt16: + Intrinsic<[llvm_v4i1_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_lt32: + Intrinsic<[llvm_v2i1_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_lt64: + Intrinsic<[llvm_v1i1_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_max32: ClangBuiltin<"__builtin_xtensa_ae_max32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_max64: ClangBuiltin<"__builtin_xtensa_ae_max64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_maxabs32s: ClangBuiltin<"__builtin_xtensa_ae_maxabs32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_maxabs64s: ClangBuiltin<"__builtin_xtensa_ae_maxabs64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_min32: ClangBuiltin<"__builtin_xtensa_ae_min32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_min64: ClangBuiltin<"__builtin_xtensa_ae_min64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_minabs32s: ClangBuiltin<"__builtin_xtensa_ae_minabs32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_minabs64s: ClangBuiltin<"__builtin_xtensa_ae_minabs64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_mov: ClangBuiltin<"__builtin_xtensa_ae_mov">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_movad16_0: ClangBuiltin<"__builtin_xtensa_ae_movad16_0">, + Intrinsic<[llvm_i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_movad16_1: ClangBuiltin<"__builtin_xtensa_ae_movad16_1">, + Intrinsic<[llvm_i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_movad16_2: ClangBuiltin<"__builtin_xtensa_ae_movad16_2">, + Intrinsic<[llvm_i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_movad16_3: ClangBuiltin<"__builtin_xtensa_ae_movad16_3">, + Intrinsic<[llvm_i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_movad32_h: ClangBuiltin<"__builtin_xtensa_ae_movad32_h">, + Intrinsic<[llvm_i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_movad32_l: ClangBuiltin<"__builtin_xtensa_ae_movad32_l">, + Intrinsic<[llvm_i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_movalign: ClangBuiltin<"__builtin_xtensa_ae_movalign">, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty], [IntrNoMem]>; + +def int_xtensa_ae_movda16: ClangBuiltin<"__builtin_xtensa_ae_movda16">, + Intrinsic<[llvm_v4i16_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_movda16x2: ClangBuiltin<"__builtin_xtensa_ae_movda16x2">, + Intrinsic<[llvm_v4i16_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_movda32: ClangBuiltin<"__builtin_xtensa_ae_movda32">, + Intrinsic<[llvm_v1i32_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_movda32x2: ClangBuiltin<"__builtin_xtensa_ae_movda32x2">, + Intrinsic<[llvm_v2i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_movf16x4: + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty, llvm_v4i1_ty], [IntrNoMem]>; + +def int_xtensa_ae_movf32x2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i1_ty], [IntrNoMem]>; + +def int_xtensa_ae_movf64: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v1i1_ty], [IntrNoMem]>; + +def int_xtensa_ae_movi: ClangBuiltin<"__builtin_xtensa_ae_movi">, + Intrinsic<[llvm_v2i32_ty], [llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_movt16x4: + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty, llvm_v4i1_ty], [IntrNoMem]>; + +def int_xtensa_ae_movt32x2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i1_ty], [IntrNoMem]>; + +def int_xtensa_ae_movt64: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v1i1_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul16x4: + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32_hh: ClangBuiltin<"__builtin_xtensa_ae_mul32_hh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32_lh: ClangBuiltin<"__builtin_xtensa_ae_mul32_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32_ll: ClangBuiltin<"__builtin_xtensa_ae_mul32_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32u_ll: ClangBuiltin<"__builtin_xtensa_ae_mul32u_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_h0: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_h0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_h0_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_h0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_h1: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_h1">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_h1_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_h1_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_h2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_h2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_h2_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_h2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_h3: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_h3">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_h3_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_h3_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_l0: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_l1: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_l1">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_l1_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_l1_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_l2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_l3: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_l3">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mul32x16_l3_s2: ClangBuiltin<"__builtin_xtensa_ae_mul32x16_l3_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula16x4: + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32_hh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32u_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_h0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_h0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_h1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_h1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_h2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_h2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_h3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_h3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_l1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_l1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_l3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mula32x16_l3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad24_hh_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad24_hh_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad24_hl_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad24_hl_lh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad32x16_h0_l1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad32x16_h0_l1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad32x16_h1_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad32x16_h1_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad32x16_h2_l3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad32x16_h2_l3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad32x16_h3_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaad32x16_h3_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd16ss_11_00: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd16ss_11_00_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd16ss_13_02: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd16ss_13_02_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd16ss_33_22: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd16ss_33_22_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd24_hh_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd24_hh_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd24_hl_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd24_hl_lh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd32x16_h0_l1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd32x16_h0_l1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd32x16_h1_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd32x16_h1_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd32x16_h2_l3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd32x16_h2_l3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd32x16_h3_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaafd32x16_h3_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulac24: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulac32x16_h: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulac32x16_l: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_00: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_00_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_10: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_11: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_20: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_21: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_22: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_30: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_31: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_32: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16ss_33: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf16x4ss: + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32r_hh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32r_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32r_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32r_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32s_hh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32s_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32s_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32s_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_h0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_h0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_h1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_h1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_h2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_h2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_h3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_h3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_l1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_l1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_l3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf32x16_l3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf48q32sp16s_l: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf48q32sp16s_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf48q32sp16u_l: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaf48q32sp16u_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafc24ra: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafc32x16ras_h: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafc32x16ras_l: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafd24x2_fir_h: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafd24x2_fir_l: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafd32x16x2_fir_hh: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafd32x16x2_fir_hl: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafd32x16x2_fir_lh: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafd32x16x2_fir_ll: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp24x2r: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp24x2r_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp24x2ra: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp24x2ra_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x16x2ras_h: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x16x2ras_h_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x16x2ras_l: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x16x2ras_l_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x16x2rs_h: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x16x2rs_h_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x16x2rs_l: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x16x2rs_l_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x2ras: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafp32x2rs: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafq32sp24s_h_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulafq32sp24s_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulap24x2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulap24x2_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulap32x16x2_h: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulap32x16x2_l: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulap32x2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaq32sp16s_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulaq32sp16u_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mularfq32sp24s_h_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mularfq32sp24s_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulas32f48p16s_hh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulas32f48p16s_hh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulas32f48p16s_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulas32f48p16s_lh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulas32f48p16s_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulas32f48p16s_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasd24_hh_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasd24_hh_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasd24_hl_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasd24_hl_lh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasd32x16_h1_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasd32x16_h1_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasd32x16_h3_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasd32x16_h3_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasfd24_hh_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasfd24_hh_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasfd24_hl_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasfd24_hl_lh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasfd32x16_h1_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasfd32x16_h1_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasfd32x16_h3_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulasfd32x16_h3_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulc24: ClangBuiltin<"__builtin_xtensa_ae_mulc24">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulc32x16_h: ClangBuiltin<"__builtin_xtensa_ae_mulc32x16_h">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulc32x16_l: ClangBuiltin<"__builtin_xtensa_ae_mulc32x16_l">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_00: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_00">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_00_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_00_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_10: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_10">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_11: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_11">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_20: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_20">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_21: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_21">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_22: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_22">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_30: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_30">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_31: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_31">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_32: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16ss_33: ClangBuiltin<"__builtin_xtensa_ae_mulf16ss_33">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf16x4ss: + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32r_hh: ClangBuiltin<"__builtin_xtensa_ae_mulf32r_hh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32r_lh: ClangBuiltin<"__builtin_xtensa_ae_mulf32r_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32r_ll: ClangBuiltin<"__builtin_xtensa_ae_mulf32r_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32r_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32r_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32s_hh: ClangBuiltin<"__builtin_xtensa_ae_mulf32s_hh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32s_lh: ClangBuiltin<"__builtin_xtensa_ae_mulf32s_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32s_ll: ClangBuiltin<"__builtin_xtensa_ae_mulf32s_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32s_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32s_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_h0: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_h0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_h0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_h0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_h1: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_h1">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_h1_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_h1_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_h2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_h2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_h2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_h2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_h3: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_h3">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_h3_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_h3_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_l0: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_l1: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_l1">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_l1_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_l1_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_l2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_l3: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_l3">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf32x16_l3_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf32x16_l3_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf48q32sp16s_l: ClangBuiltin<"__builtin_xtensa_ae_mulf48q32sp16s_l">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf48q32sp16s_l_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf48q32sp16s_l_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf48q32sp16u_l: ClangBuiltin<"__builtin_xtensa_ae_mulf48q32sp16u_l">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulf48q32sp16u_l_s2: ClangBuiltin<"__builtin_xtensa_ae_mulf48q32sp16u_l_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfc24ra: ClangBuiltin<"__builtin_xtensa_ae_mulfc24ra">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfc32x16ras_h: ClangBuiltin<"__builtin_xtensa_ae_mulfc32x16ras_h">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfc32x16ras_l: ClangBuiltin<"__builtin_xtensa_ae_mulfc32x16ras_l">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfd24x2_fir_h: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfd24x2_fir_l: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfd32x16x2_fir_hh: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfd32x16x2_fir_hl: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfd32x16x2_fir_lh: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfd32x16x2_fir_ll: + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp16x4ras: ClangBuiltin<"__builtin_xtensa_ae_mulfp16x4ras">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp16x4s: ClangBuiltin<"__builtin_xtensa_ae_mulfp16x4s">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp24x2r: ClangBuiltin<"__builtin_xtensa_ae_mulfp24x2r">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp24x2r_s2: ClangBuiltin<"__builtin_xtensa_ae_mulfp24x2r_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp24x2ra: ClangBuiltin<"__builtin_xtensa_ae_mulfp24x2ra">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp24x2ra_s2: ClangBuiltin<"__builtin_xtensa_ae_mulfp24x2ra_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x16x2ras_h: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x16x2ras_h">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x16x2ras_h_s2: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x16x2ras_h_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x16x2ras_l: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x16x2ras_l">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x16x2ras_l_s2: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x16x2ras_l_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x16x2rs_h: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x16x2rs_h">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x16x2rs_h_s2: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x16x2rs_h_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x16x2rs_l: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x16x2rs_l">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x16x2rs_l_s2: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x16x2rs_l_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x2ras: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x2ras">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfp32x2rs: ClangBuiltin<"__builtin_xtensa_ae_mulfp32x2rs">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfq32sp24s_h_s2: ClangBuiltin<"__builtin_xtensa_ae_mulfq32sp24s_h_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulfq32sp24s_l_s2: ClangBuiltin<"__builtin_xtensa_ae_mulfq32sp24s_l_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulp24x2: ClangBuiltin<"__builtin_xtensa_ae_mulp24x2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulp24x2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulp24x2_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulp32x16x2_h: ClangBuiltin<"__builtin_xtensa_ae_mulp32x16x2_h">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulp32x16x2_l: ClangBuiltin<"__builtin_xtensa_ae_mulp32x16x2_l">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulp32x2: ClangBuiltin<"__builtin_xtensa_ae_mulp32x2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulq32sp16s_l_s2: ClangBuiltin<"__builtin_xtensa_ae_mulq32sp16s_l_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulq32sp16u_l_s2: ClangBuiltin<"__builtin_xtensa_ae_mulq32sp16u_l_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulrfq32sp24s_h_s2: ClangBuiltin<"__builtin_xtensa_ae_mulrfq32sp24s_h_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulrfq32sp24s_l_s2: ClangBuiltin<"__builtin_xtensa_ae_mulrfq32sp24s_l_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls16x4: + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32_hh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32f48p16s_hh: ClangBuiltin<"__builtin_xtensa_ae_muls32f48p16s_hh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32f48p16s_hh_s2: ClangBuiltin<"__builtin_xtensa_ae_muls32f48p16s_hh_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32f48p16s_lh: ClangBuiltin<"__builtin_xtensa_ae_muls32f48p16s_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32f48p16s_lh_s2: ClangBuiltin<"__builtin_xtensa_ae_muls32f48p16s_lh_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32f48p16s_ll: ClangBuiltin<"__builtin_xtensa_ae_muls32f48p16s_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32f48p16s_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_muls32f48p16s_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32u_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_h0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_h0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_h1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_h1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_h2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_h2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_h3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_h3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_l1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_l1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_l3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_muls32x16_l3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsad24_hh_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsad24_hh_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsad32x16_h1_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsad32x16_h1_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsad32x16_h3_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsad32x16_h3_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsafd24_hh_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsafd24_hh_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsafd32x16_h1_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsafd32x16_h1_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsafd32x16_h3_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsafd32x16_h3_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_00: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_00_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_10: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_11: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_20: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_21: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_22: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_30: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_31: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_32: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16ss_33: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf16x4ss: + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32r_hh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32r_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32r_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32r_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32s_hh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32s_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32s_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_h0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_h0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_h1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_h1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_h2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_h2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_h3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_h3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_l1: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_l1_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_l3: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf32x16_l3_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf48q32sp16s_l: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf48q32sp16s_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf48q32sp16u_l: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsf48q32sp16u_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp24x2r: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp24x2r_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp24x2ra: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp24x2ra_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x16x2ras_h: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x16x2ras_h_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x16x2ras_l: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x16x2ras_l_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x16x2rs_h: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x16x2rs_h_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x16x2rs_l: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x16x2rs_l_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x2ras: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfp32x2rs: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfq32sp24s_h_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsfq32sp24s_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsp24x2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsp24x2_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsp32x16x2_h: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsp32x16x2_l: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsp32x2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsq32sp16s_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsq32sp16u_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsrfq32sp24s_h_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulsrfq32sp24s_l_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulss32f48p16s_hh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulss32f48p16s_hh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulss32f48p16s_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulss32f48p16s_lh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulss32f48p16s_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulss32f48p16s_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssd24_hh_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssd24_hh_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssd24_hl_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssd24_hl_lh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssd32x16_h1_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssd32x16_h1_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssd32x16_h3_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssd32x16_h3_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd16ss_11_00: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd16ss_11_00_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd16ss_13_02: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd16ss_13_02_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd16ss_33_22: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd16ss_33_22_s2: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd24_hh_ll: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd24_hh_ll_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd24_hl_lh: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd24_hl_lh_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd32x16_h1_l0: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd32x16_h1_l0_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd32x16_h3_l2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulssfd32x16_h3_l2_s2: + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad24_hh_ll: ClangBuiltin<"__builtin_xtensa_ae_mulzaad24_hh_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad24_hh_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaad24_hh_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad24_hl_lh: ClangBuiltin<"__builtin_xtensa_ae_mulzaad24_hl_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad24_hl_lh_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaad24_hl_lh_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad32x16_h0_l1: ClangBuiltin<"__builtin_xtensa_ae_mulzaad32x16_h0_l1">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad32x16_h0_l1_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaad32x16_h0_l1_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad32x16_h1_l0: ClangBuiltin<"__builtin_xtensa_ae_mulzaad32x16_h1_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad32x16_h1_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaad32x16_h1_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad32x16_h2_l3: ClangBuiltin<"__builtin_xtensa_ae_mulzaad32x16_h2_l3">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad32x16_h2_l3_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaad32x16_h2_l3_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad32x16_h3_l2: ClangBuiltin<"__builtin_xtensa_ae_mulzaad32x16_h3_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaad32x16_h3_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaad32x16_h3_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd16ss_11_00: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd16ss_11_00">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd16ss_11_00_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd16ss_11_00_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd16ss_13_02: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd16ss_13_02">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd16ss_13_02_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd16ss_13_02_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd16ss_33_22: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd16ss_33_22">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd16ss_33_22_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd16ss_33_22_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd24_hh_ll: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd24_hh_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd24_hh_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd24_hh_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd24_hl_lh: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd24_hl_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd24_hl_lh_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd24_hl_lh_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd32x16_h0_l1: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd32x16_h0_l1">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd32x16_h0_l1_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd32x16_h0_l1_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd32x16_h1_l0: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd32x16_h1_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd32x16_h1_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd32x16_h1_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd32x16_h2_l3: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd32x16_h2_l3">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd32x16_h2_l3_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd32x16_h2_l3_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd32x16_h3_l2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd32x16_h3_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzaafd32x16_h3_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzaafd32x16_h3_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasd24_hh_ll: ClangBuiltin<"__builtin_xtensa_ae_mulzasd24_hh_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasd24_hh_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzasd24_hh_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasd24_hl_lh: ClangBuiltin<"__builtin_xtensa_ae_mulzasd24_hl_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasd24_hl_lh_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzasd24_hl_lh_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasd32x16_h1_l0: ClangBuiltin<"__builtin_xtensa_ae_mulzasd32x16_h1_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasd32x16_h1_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzasd32x16_h1_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasd32x16_h3_l2: ClangBuiltin<"__builtin_xtensa_ae_mulzasd32x16_h3_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasd32x16_h3_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzasd32x16_h3_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasfd24_hh_ll: ClangBuiltin<"__builtin_xtensa_ae_mulzasfd24_hh_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasfd24_hh_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzasfd24_hh_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasfd24_hl_lh: ClangBuiltin<"__builtin_xtensa_ae_mulzasfd24_hl_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasfd24_hl_lh_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzasfd24_hl_lh_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasfd32x16_h1_l0: ClangBuiltin<"__builtin_xtensa_ae_mulzasfd32x16_h1_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasfd32x16_h1_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzasfd32x16_h1_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasfd32x16_h3_l2: ClangBuiltin<"__builtin_xtensa_ae_mulzasfd32x16_h3_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzasfd32x16_h3_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzasfd32x16_h3_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsad24_hh_ll: ClangBuiltin<"__builtin_xtensa_ae_mulzsad24_hh_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsad24_hh_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzsad24_hh_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsad32x16_h1_l0: ClangBuiltin<"__builtin_xtensa_ae_mulzsad32x16_h1_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsad32x16_h1_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzsad32x16_h1_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsad32x16_h3_l2: ClangBuiltin<"__builtin_xtensa_ae_mulzsad32x16_h3_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsad32x16_h3_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzsad32x16_h3_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsafd24_hh_ll: ClangBuiltin<"__builtin_xtensa_ae_mulzsafd24_hh_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsafd24_hh_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzsafd24_hh_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsafd32x16_h1_l0: ClangBuiltin<"__builtin_xtensa_ae_mulzsafd32x16_h1_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsafd32x16_h1_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzsafd32x16_h1_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsafd32x16_h3_l2: ClangBuiltin<"__builtin_xtensa_ae_mulzsafd32x16_h3_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzsafd32x16_h3_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzsafd32x16_h3_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssd24_hh_ll: ClangBuiltin<"__builtin_xtensa_ae_mulzssd24_hh_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssd24_hh_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssd24_hh_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssd24_hl_lh: ClangBuiltin<"__builtin_xtensa_ae_mulzssd24_hl_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssd24_hl_lh_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssd24_hl_lh_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssd32x16_h1_l0: ClangBuiltin<"__builtin_xtensa_ae_mulzssd32x16_h1_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssd32x16_h1_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssd32x16_h1_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssd32x16_h3_l2: ClangBuiltin<"__builtin_xtensa_ae_mulzssd32x16_h3_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssd32x16_h3_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssd32x16_h3_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd16ss_11_00: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd16ss_11_00">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd16ss_11_00_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd16ss_11_00_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd16ss_13_02: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd16ss_13_02">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd16ss_13_02_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd16ss_13_02_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd16ss_33_22: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd16ss_33_22">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd16ss_33_22_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd16ss_33_22_s2">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd24_hh_ll: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd24_hh_ll">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd24_hh_ll_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd24_hh_ll_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd24_hl_lh: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd24_hl_lh">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd24_hl_lh_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd24_hl_lh_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd32x16_h1_l0: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd32x16_h1_l0">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd32x16_h1_l0_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd32x16_h1_l0_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd32x16_h3_l2: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd32x16_h3_l2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_mulzssfd32x16_h3_l2_s2: ClangBuiltin<"__builtin_xtensa_ae_mulzssfd32x16_h3_l2_s2">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_nand: ClangBuiltin<"__builtin_xtensa_ae_nand">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_neg16s: ClangBuiltin<"__builtin_xtensa_ae_neg16s">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_neg24s: ClangBuiltin<"__builtin_xtensa_ae_neg24s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_neg32: ClangBuiltin<"__builtin_xtensa_ae_neg32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_neg32s: ClangBuiltin<"__builtin_xtensa_ae_neg32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_neg64: ClangBuiltin<"__builtin_xtensa_ae_neg64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_neg64s: ClangBuiltin<"__builtin_xtensa_ae_neg64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_nsa64: ClangBuiltin<"__builtin_xtensa_ae_nsa64">, + Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_nsaz16_0: ClangBuiltin<"__builtin_xtensa_ae_nsaz16_0">, + Intrinsic<[llvm_i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_nsaz32_l: ClangBuiltin<"__builtin_xtensa_ae_nsaz32_l">, + Intrinsic<[llvm_i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_or: ClangBuiltin<"__builtin_xtensa_ae_or">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_pksr24: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_pksr32: + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_round16x4f32sasym: ClangBuiltin<"__builtin_xtensa_ae_round16x4f32sasym">, + Intrinsic<[llvm_v4i16_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_round16x4f32ssym: ClangBuiltin<"__builtin_xtensa_ae_round16x4f32ssym">, + Intrinsic<[llvm_v4i16_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_round24x2f48sasym: ClangBuiltin<"__builtin_xtensa_ae_round24x2f48sasym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_round24x2f48ssym: ClangBuiltin<"__builtin_xtensa_ae_round24x2f48ssym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_round32x2f48sasym: ClangBuiltin<"__builtin_xtensa_ae_round32x2f48sasym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_round32x2f48ssym: ClangBuiltin<"__builtin_xtensa_ae_round32x2f48ssym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_round32x2f64sasym: ClangBuiltin<"__builtin_xtensa_ae_round32x2f64sasym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_round32x2f64ssym: ClangBuiltin<"__builtin_xtensa_ae_round32x2f64ssym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_roundsp16f24asym: ClangBuiltin<"__builtin_xtensa_ae_roundsp16f24asym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_roundsp16f24sym: ClangBuiltin<"__builtin_xtensa_ae_roundsp16f24sym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_roundsp16q48x2asym: ClangBuiltin<"__builtin_xtensa_ae_roundsp16q48x2asym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_roundsp16q48x2sym: ClangBuiltin<"__builtin_xtensa_ae_roundsp16q48x2sym">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_roundsq32f48asym: ClangBuiltin<"__builtin_xtensa_ae_roundsq32f48asym">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_roundsq32f48sym: ClangBuiltin<"__builtin_xtensa_ae_roundsq32f48sym">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_s16_0_i: ClangBuiltin<"__builtin_xtensa_ae_s16_0_i">, + Intrinsic<[], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s16_0_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s16_0_x: ClangBuiltin<"__builtin_xtensa_ae_s16_0_x">, + Intrinsic<[], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16_0_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16_0_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16m_l_i: ClangBuiltin<"__builtin_xtensa_ae_s16m_l_i">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s16m_l_iu: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s16m_l_x: ClangBuiltin<"__builtin_xtensa_ae_s16m_l_x">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16m_l_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16m_l_xu: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16x2m_i: ClangBuiltin<"__builtin_xtensa_ae_s16x2m_i">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s16x2m_iu: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s16x2m_x: ClangBuiltin<"__builtin_xtensa_ae_s16x2m_x">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16x2m_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16x2m_xu: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16x4_i: ClangBuiltin<"__builtin_xtensa_ae_s16x4_i">, + Intrinsic<[], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s16x4_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s16x4_ric: + Intrinsic<[llvm_ptr_ty], [llvm_v4i16_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_s16x4_rip: + Intrinsic<[llvm_ptr_ty], [llvm_v4i16_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_s16x4_x: ClangBuiltin<"__builtin_xtensa_ae_s16x4_x">, + Intrinsic<[], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16x4_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s16x4_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v4i16_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s24ra64s_i: ClangBuiltin<"__builtin_xtensa_ae_s24ra64s_i">, + Intrinsic<[], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s24ra64s_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s24ra64s_x: ClangBuiltin<"__builtin_xtensa_ae_s24ra64s_x">, + Intrinsic<[], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s24ra64s_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s24ra64s_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s24x2ra64s_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_s32_l_i: ClangBuiltin<"__builtin_xtensa_ae_s32_l_i">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32_l_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32_l_x: ClangBuiltin<"__builtin_xtensa_ae_s32_l_x">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32_l_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32_l_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32f24_l_i: ClangBuiltin<"__builtin_xtensa_ae_s32f24_l_i">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32f24_l_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32f24_l_x: ClangBuiltin<"__builtin_xtensa_ae_s32f24_l_x">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32f24_l_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32f24_l_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32m_i: ClangBuiltin<"__builtin_xtensa_ae_s32m_i">, + Intrinsic<[], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32m_iu: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32m_x: ClangBuiltin<"__builtin_xtensa_ae_s32m_x">, + Intrinsic<[], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32m_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32m_xu: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32ra64s_i: ClangBuiltin<"__builtin_xtensa_ae_s32ra64s_i">, + Intrinsic<[], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32ra64s_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32ra64s_x: ClangBuiltin<"__builtin_xtensa_ae_s32ra64s_x">, + Intrinsic<[], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32ra64s_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32ra64s_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32x2_i: ClangBuiltin<"__builtin_xtensa_ae_s32x2_i">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32x2_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32x2_ric: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_s32x2_rip: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_s32x2_x: ClangBuiltin<"__builtin_xtensa_ae_s32x2_x">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32x2_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32x2_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32x2f24_i: ClangBuiltin<"__builtin_xtensa_ae_s32x2f24_i">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32x2f24_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s32x2f24_ric: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_s32x2f24_rip: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_s32x2f24_x: ClangBuiltin<"__builtin_xtensa_ae_s32x2f24_x">, + Intrinsic<[], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32x2f24_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32x2f24_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v2i32_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s32x2ra64s_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_s64_i: ClangBuiltin<"__builtin_xtensa_ae_s64_i">, + Intrinsic<[], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s64_ip: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_s64_x: ClangBuiltin<"__builtin_xtensa_ae_s64_x">, + Intrinsic<[], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s64_xc: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_s64_xp: + Intrinsic<[llvm_ptr_ty], [llvm_v1i64_ty, llvm_ptr_ty, llvm_i32_ty], []>; + +def int_xtensa_ae_sa16x4_ic: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v4i16_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa16x4_ip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v4i16_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa16x4_ric: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v4i16_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa16x4_rip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v4i16_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa24_l_ic: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa24_l_ip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa24_l_ric: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa24_l_rip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa24x2_ic: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa24x2_ip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa24x2_ric: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa24x2_rip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa32x2_ic: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa32x2_ip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa32x2_ric: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa32x2_rip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa32x2f24_ic: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa32x2f24_ip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa32x2f24_ric: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa32x2f24_rip: + Intrinsic<[llvm_v8i8_ty, llvm_ptr_ty], [llvm_v2i32_ty, llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa64neg_fp: + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_sa64pos_fp: + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_ptr_ty], []>; + +def int_xtensa_ae_salign64_i: ClangBuiltin<"__builtin_xtensa_ae_salign64_i">, + Intrinsic<[], [llvm_v8i8_ty, llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; + +def int_xtensa_ae_sat16x4: ClangBuiltin<"__builtin_xtensa_ae_sat16x4">, + Intrinsic<[llvm_v4i16_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sat24s: ClangBuiltin<"__builtin_xtensa_ae_sat24s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sat48s: ClangBuiltin<"__builtin_xtensa_ae_sat48s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_satq56s: ClangBuiltin<"__builtin_xtensa_ae_satq56s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_sb: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sb_ic: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sb_ip: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sbf: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_sbf_ic: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_sbf_ip: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_sbi: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_sbi_ic: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_sbi_ip: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_sel16i: ClangBuiltin<"__builtin_xtensa_ae_sel16i">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_sel16i_n: ClangBuiltin<"__builtin_xtensa_ae_sel16i_n">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_sext32: ClangBuiltin<"__builtin_xtensa_ae_sext32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_sext32x2d16_10: ClangBuiltin<"__builtin_xtensa_ae_sext32x2d16_10">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_sext32x2d16_32: ClangBuiltin<"__builtin_xtensa_ae_sext32x2d16_32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_sha32: ClangBuiltin<"__builtin_xtensa_ae_sha32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_shortswap: ClangBuiltin<"__builtin_xtensa_ae_shortswap">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_slaa16s: ClangBuiltin<"__builtin_xtensa_ae_slaa16s">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slaa32: ClangBuiltin<"__builtin_xtensa_ae_slaa32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slaa32s: ClangBuiltin<"__builtin_xtensa_ae_slaa32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slaa64: ClangBuiltin<"__builtin_xtensa_ae_slaa64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slaa64s: ClangBuiltin<"__builtin_xtensa_ae_slaa64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slaaq56: ClangBuiltin<"__builtin_xtensa_ae_slaaq56">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slai16s: ClangBuiltin<"__builtin_xtensa_ae_slai16s">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_slai24: ClangBuiltin<"__builtin_xtensa_ae_slai24">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_slai24s: ClangBuiltin<"__builtin_xtensa_ae_slai24s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_slai32: ClangBuiltin<"__builtin_xtensa_ae_slai32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_slai32s: ClangBuiltin<"__builtin_xtensa_ae_slai32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_slai64: ClangBuiltin<"__builtin_xtensa_ae_slai64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_slai64s: ClangBuiltin<"__builtin_xtensa_ae_slai64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_slaisq56s: ClangBuiltin<"__builtin_xtensa_ae_slaisq56s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_slas24: ClangBuiltin<"__builtin_xtensa_ae_slas24">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slas24s: ClangBuiltin<"__builtin_xtensa_ae_slas24s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slas32: ClangBuiltin<"__builtin_xtensa_ae_slas32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slas32s: ClangBuiltin<"__builtin_xtensa_ae_slas32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_slas64: ClangBuiltin<"__builtin_xtensa_ae_slas64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_slas64s: ClangBuiltin<"__builtin_xtensa_ae_slas64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_slasq56: ClangBuiltin<"__builtin_xtensa_ae_slasq56">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_slassq56s: ClangBuiltin<"__builtin_xtensa_ae_slassq56s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_sra64_32: ClangBuiltin<"__builtin_xtensa_ae_sra64_32">, + Intrinsic<[llvm_v1i64_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sraa16rs: ClangBuiltin<"__builtin_xtensa_ae_sraa16rs">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sraa16s: ClangBuiltin<"__builtin_xtensa_ae_sraa16s">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sraa32: ClangBuiltin<"__builtin_xtensa_ae_sraa32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sraa32rs: ClangBuiltin<"__builtin_xtensa_ae_sraa32rs">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sraa32s: ClangBuiltin<"__builtin_xtensa_ae_sraa32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sraa64: ClangBuiltin<"__builtin_xtensa_ae_sraa64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_srai16: ClangBuiltin<"__builtin_xtensa_ae_srai16">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_srai16r: ClangBuiltin<"__builtin_xtensa_ae_srai16r">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_srai24: ClangBuiltin<"__builtin_xtensa_ae_srai24">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_srai32: ClangBuiltin<"__builtin_xtensa_ae_srai32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_srai32r: ClangBuiltin<"__builtin_xtensa_ae_srai32r">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_srai64: ClangBuiltin<"__builtin_xtensa_ae_srai64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_sras24: ClangBuiltin<"__builtin_xtensa_ae_sras24">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sras32: ClangBuiltin<"__builtin_xtensa_ae_sras32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sras64: ClangBuiltin<"__builtin_xtensa_ae_sras64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_srla32: ClangBuiltin<"__builtin_xtensa_ae_srla32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_srla64: ClangBuiltin<"__builtin_xtensa_ae_srla64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_srli24: ClangBuiltin<"__builtin_xtensa_ae_srli24">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_srli32: ClangBuiltin<"__builtin_xtensa_ae_srli32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_srli64: ClangBuiltin<"__builtin_xtensa_ae_srli64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_srls24: ClangBuiltin<"__builtin_xtensa_ae_srls24">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_srls32: ClangBuiltin<"__builtin_xtensa_ae_srls32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_srls64: ClangBuiltin<"__builtin_xtensa_ae_srls64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_sub16: ClangBuiltin<"__builtin_xtensa_ae_sub16">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_sub16s: ClangBuiltin<"__builtin_xtensa_ae_sub16s">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + +def int_xtensa_ae_sub24s: ClangBuiltin<"__builtin_xtensa_ae_sub24s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sub32: ClangBuiltin<"__builtin_xtensa_ae_sub32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sub32s: ClangBuiltin<"__builtin_xtensa_ae_sub32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_sub64: ClangBuiltin<"__builtin_xtensa_ae_sub64">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_sub64s: ClangBuiltin<"__builtin_xtensa_ae_sub64s">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_subadd32: ClangBuiltin<"__builtin_xtensa_ae_subadd32">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_subadd32s: ClangBuiltin<"__builtin_xtensa_ae_subadd32s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_trunca32f64s_l: ClangBuiltin<"__builtin_xtensa_ae_trunca32f64s_l">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_trunca32x2f64s: ClangBuiltin<"__builtin_xtensa_ae_trunca32x2f64s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; + +def int_xtensa_ae_trunci32f64s_l: ClangBuiltin<"__builtin_xtensa_ae_trunci32f64s_l">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_trunci32x2f64s: ClangBuiltin<"__builtin_xtensa_ae_trunci32x2f64s">, + Intrinsic<[llvm_v2i32_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; + +def int_xtensa_ae_vldl16c: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vldl16c_ic: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vldl16c_ip: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vldl16t: + Intrinsic<[llvm_v1i1_ty, llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vldl32t: + Intrinsic<[llvm_v1i1_ty, llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vldsht: ClangBuiltin<"__builtin_xtensa_ae_vldsht">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_ae_vlel16t: + Intrinsic<[llvm_v1i1_ty, llvm_i32_ty], [llvm_i32_ty, llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vlel32t: + Intrinsic<[llvm_v1i1_ty, llvm_i32_ty], [llvm_i32_ty, llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vles16c: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vles16c_ic: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_vles16c_ip: + Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty], [IntrNoMem]>; + +def int_xtensa_ae_xor: ClangBuiltin<"__builtin_xtensa_ae_xor">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + +def int_xtensa_ae_zalign64: ClangBuiltin<"__builtin_xtensa_ae_zalign64">, + Intrinsic<[llvm_v8i8_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_bithead: ClangBuiltin<"__builtin_xtensa_rur_ae_bithead">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_bitptr: ClangBuiltin<"__builtin_xtensa_rur_ae_bitptr">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_bitsused: ClangBuiltin<"__builtin_xtensa_rur_ae_bitsused">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_cbegin0: ClangBuiltin<"__builtin_xtensa_rur_ae_cbegin0">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_cend0: ClangBuiltin<"__builtin_xtensa_rur_ae_cend0">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_cw_sd_no: ClangBuiltin<"__builtin_xtensa_rur_ae_cw_sd_no">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_cwrap: ClangBuiltin<"__builtin_xtensa_rur_ae_cwrap">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_first_ts: ClangBuiltin<"__builtin_xtensa_rur_ae_first_ts">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_nextoffset: ClangBuiltin<"__builtin_xtensa_rur_ae_nextoffset">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_overflow: ClangBuiltin<"__builtin_xtensa_rur_ae_overflow">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_ovf_sar: ClangBuiltin<"__builtin_xtensa_rur_ae_ovf_sar">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_sar: ClangBuiltin<"__builtin_xtensa_rur_ae_sar">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_searchdone: ClangBuiltin<"__builtin_xtensa_rur_ae_searchdone">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_tablesize: ClangBuiltin<"__builtin_xtensa_rur_ae_tablesize">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_rur_ae_ts_fts_bu_bp: ClangBuiltin<"__builtin_xtensa_rur_ae_ts_fts_bu_bp">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + +def int_xtensa_wur_ae_bithead: ClangBuiltin<"__builtin_xtensa_wur_ae_bithead">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_bitptr: ClangBuiltin<"__builtin_xtensa_wur_ae_bitptr">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_bitsused: ClangBuiltin<"__builtin_xtensa_wur_ae_bitsused">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_cbegin0: ClangBuiltin<"__builtin_xtensa_wur_ae_cbegin0">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_cend0: ClangBuiltin<"__builtin_xtensa_wur_ae_cend0">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_cw_sd_no: ClangBuiltin<"__builtin_xtensa_wur_ae_cw_sd_no">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_cwrap: ClangBuiltin<"__builtin_xtensa_wur_ae_cwrap">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_first_ts: ClangBuiltin<"__builtin_xtensa_wur_ae_first_ts">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_nextoffset: ClangBuiltin<"__builtin_xtensa_wur_ae_nextoffset">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_overflow: ClangBuiltin<"__builtin_xtensa_wur_ae_overflow">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_ovf_sar: ClangBuiltin<"__builtin_xtensa_wur_ae_ovf_sar">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_sar: ClangBuiltin<"__builtin_xtensa_wur_ae_sar">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_searchdone: ClangBuiltin<"__builtin_xtensa_wur_ae_searchdone">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_tablesize: ClangBuiltin<"__builtin_xtensa_wur_ae_tablesize">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_xtensa_wur_ae_ts_fts_bu_bp: ClangBuiltin<"__builtin_xtensa_wur_ae_ts_fts_bu_bp">, + Intrinsic<[], [llvm_i32_ty], []>; + From 6a0033cebda6640a066691a65548dc5885b4baf0 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 10:33:40 +0000 Subject: [PATCH 209/261] [Xtensa] Add HIFI3 register classes --- .../Disassembler/XtensaDisassembler.cpp | 66 +++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 61 +++++++++++++++++ 2 files changed, 127 insertions(+) diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 5d76b2c88fead9..2265dd99b609d7 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -68,6 +68,38 @@ static const unsigned ARDecoderTable[] = { Xtensa::A6, Xtensa::A7, Xtensa::A8, Xtensa::A9, Xtensa::A10, Xtensa::A11, Xtensa::A12, Xtensa::A13, Xtensa::A14, Xtensa::A15}; +static const unsigned AE_DRDecoderTable[] = { + Xtensa::AED0, Xtensa::AED1, Xtensa::AED2, Xtensa::AED3, + Xtensa::AED4, Xtensa::AED5, Xtensa::AED6, Xtensa::AED7, + Xtensa::AED8, Xtensa::AED9, Xtensa::AED10, Xtensa::AED11, + Xtensa::AED12, Xtensa::AED13, Xtensa::AED14, Xtensa::AED15}; + +static const unsigned AE_VALIGNDecoderTable[] = {Xtensa::U0, Xtensa::U1, + Xtensa::U2, Xtensa::U3}; + + +static DecodeStatus DecodeAE_DRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= std::size(AE_DRDecoderTable)) + return MCDisassembler::Fail; + + unsigned Reg = AE_DRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeAE_VALIGNRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= std::size(AE_VALIGNDecoderTable)) + return MCDisassembler::Fail; + + unsigned Reg = AE_VALIGNDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { @@ -115,6 +147,40 @@ static const unsigned BRDecoderTable[] = { Xtensa::B6, Xtensa::B7, Xtensa::B8, Xtensa::B9, Xtensa::B10, Xtensa::B11, Xtensa::B12, Xtensa::B13, Xtensa::B14, Xtensa::B15}; +static const unsigned BR2DecoderTable[] = { + Xtensa::B0_B1, Xtensa::B2_B3, Xtensa::B4_B5, Xtensa::B6_B7, + Xtensa::B8_B9, Xtensa::B10_B11, Xtensa::B12_B13, Xtensa::B14_B15}; + + +static const unsigned BR4DecoderTable[] = { + Xtensa::B0_B1_B2_B3, Xtensa::B4_B5_B6_B7, + Xtensa::B8_B9_B10_B11, Xtensa::B12_B13_B14_B15}; + + +static DecodeStatus DecodeXtensaRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder, + ArrayRef DecoderTable) { + if (RegNo >= DecoderTable.size()) + return MCDisassembler::Fail; + + unsigned Reg = DecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeBR2RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return DecodeXtensaRegisterClass(Inst,RegNo,Address,Decoder,ArrayRef(BR2DecoderTable)); +} + +static DecodeStatus DecodeBR4RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return DecodeXtensaRegisterClass(Inst,RegNo,Address,Decoder,ArrayRef(BR4DecoderTable)); +} + static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td index 7f2de9814da902..45a3dfddf53be9 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td @@ -313,5 +313,66 @@ B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15)> { let Size = 8; } +let Namespace = "Xtensa" in { + def bsub0 : SubRegIndex<1>; + def bsub1 : SubRegIndex<1, 1>; + def bsub2 : SubRegIndex<1, 2>; + def bsub3 : SubRegIndex<1, 3>; + + +let SubRegIndices = [bsub0, bsub1] in { + def B0_B1 : RegisterWithSubRegs<"", [B0, B1]>; + def B2_B3 : RegisterWithSubRegs<"", [B2, B3]>; + def B4_B5 : RegisterWithSubRegs<"", [B4, B5]>; + def B6_B7 : RegisterWithSubRegs<"", [B6, B7]>; + def B8_B9 : RegisterWithSubRegs<"", [B8, B9]>; + def B10_B11 : RegisterWithSubRegs<"", [B10, B11]>; + def B12_B13 : RegisterWithSubRegs<"", [B12, B13]>; + def B14_B15 : RegisterWithSubRegs<"", [B14, B15]>; +} + +let SubRegIndices = [bsub0, bsub1, bsub2, bsub3] in { + def B0_B1_B2_B3 : RegisterWithSubRegs<"", [B0, B1, B2, B3]>; + def B4_B5_B6_B7 : RegisterWithSubRegs<"", [B4, B5, B6, B7]>; + def B8_B9_B10_B11 : RegisterWithSubRegs<"", [B8, B9, B10, B11]>; + def B12_B13_B14_B15 : RegisterWithSubRegs<"", [B12, B13, B14, B15]>; +} + +} + +def BR2 : RegisterClass<"Xtensa", [v2i1], 8, (add B0_B1, B2_B3, B4_B5, + B6_B7, B8_B9, B10_B11, + B12_B13, B14_B15)> { + let Size = 8; +} + +def BR4 : RegisterClass<"Xtensa", [v4i1], 8, (add B0_B1_B2_B3, B4_B5_B6_B7, + B8_B9_B10_B11, B12_B13_B14_B15)> { + let Size = 8; +} +//===----------------------------------------------------------------------===// +// HIFI3 vector registers AE_DR +//===----------------------------------------------------------------------===// +class AEDReg num, string n> : XtensaReg { + let HWEncoding{3-0} = num; +} + +foreach i = 0-15 in { + def AED#i : AEDReg, DwarfRegNum<[-1]>; +} +def AE_DR : RegisterClass<"Xtensa",[v4i16,v2i32,v1i64,v1i32],64, + (sequence "AED%u", 0, 15)>; + +//===----------------------------------------------------------------------===// +// HIFI3 vector alignment registers AE_VALIGN +//===----------------------------------------------------------------------===// +class AEVALIGNReg num, string n> : XtensaReg { + let HWEncoding{1-0} = num; +} + +foreach i = 0-3 in { + def U#i : AEVALIGNReg, DwarfRegNum<[-1]>; +} +def AE_VALIGN : RegisterClass<"Xtensa",[v8i8], 64, (sequence "U%u", 0, 3)>; \ No newline at end of file From 7080b873ad3c1c8954ec23838e06cdeb02b3a395 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 10:36:54 +0000 Subject: [PATCH 210/261] [Xtensa] Add HIFI3 target feature --- clang/lib/Basic/Targets/Xtensa.cpp | 3 +++ clang/lib/Basic/Targets/Xtensa.h | 1 + llvm/include/llvm/TargetParser/XtensaTargetParser.def | 4 +++- llvm/include/llvm/TargetParser/XtensaTargetParser.h | 3 ++- llvm/lib/Target/Xtensa/Xtensa.td | 7 ++++++- llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 1 + llvm/lib/Target/Xtensa/XtensaSubtarget.h | 5 +++++ 7 files changed, 21 insertions(+), 3 deletions(-) diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp index 3c00be659c092c..cded885966c896 100644 --- a/clang/lib/Basic/Targets/Xtensa.cpp +++ b/clang/lib/Basic/Targets/Xtensa.cpp @@ -76,6 +76,7 @@ bool XtensaTargetInfo::hasFeature(StringRef Feature) const { .Case("fp", HasFP) .Case("windowed", HasWindowed) .Case("bool", HasBoolean) + .Case("hifi3", HasHIFI3) .Default(false); } @@ -89,6 +90,8 @@ bool XtensaTargetInfo::handleTargetFeatures(std::vector &Features, HasBoolean = true; else if (Feature == "+windowed") HasWindowed = true; + else if (Feature == "+hifi3") + HasHIFI3 = true; } return true; diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index c969f182c63d69..b2c923b2cd24a0 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -34,6 +34,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { bool HasFP = false; bool HasWindowed = false; bool HasBoolean = false; + bool HasHIFI3 = false; public: XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &) diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.def b/llvm/include/llvm/TargetParser/XtensaTargetParser.def index 3fe9b2760b773c..edc178ac559f5d 100644 --- a/llvm/include/llvm/TargetParser/XtensaTargetParser.def +++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.def @@ -45,6 +45,7 @@ XTENSA_FEATURE(FK_REGPROTECT, "regprotect") XTENSA_FEATURE(FK_MISCSR, "miscsr") XTENSA_FEATURE(FK_ESP32S2OPS, "esp32s2") XTENSA_FEATURE(FK_ESP32S3OPS, "esp32s3") +XTENSA_FEATURE(FK_HIFI3, "hifi3") #undef XTENSA_FEATURE @@ -77,7 +78,8 @@ XTENSA_CPU(CNL, {"cnl"}, (FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_S32C1I | FK_THREADPTR | FK_DIV32 | FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | - FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR)) + FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | + FK_HIFI3)) #undef XTENSA_CPU diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.h b/llvm/include/llvm/TargetParser/XtensaTargetParser.h index d4e639005a5a27..8e1c55c6f9e217 100644 --- a/llvm/include/llvm/TargetParser/XtensaTargetParser.h +++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.h @@ -59,7 +59,8 @@ enum FeatureKind : uint64_t { FK_REGPROTECT = 1 << 28, FK_MISCSR = 1 << 29, FK_ESP32S2OPS = 1 << 30, - FK_ESP32S3OPS = 1ULL << 31 + FK_ESP32S3OPS = 1ULL << 31, + FK_HIFI3 = 1ULL << 32 }; CPUKind parseCPUKind(StringRef CPU); diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index d3719d7a301236..0bd57503d10103 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -178,6 +178,11 @@ def FeatureESP32S3Ops : SubtargetFeature<"esp32s3", "HasESP32S3Ops", "tru def HasESP32S3Ops : Predicate<"Subtarget->hasESP32S3Ops()">, AssemblerPredicate<(all_of FeatureESP32S3Ops)>; +def FeatureHIFI3 : SubtargetFeature<"hifi3", "HasHIFI3", "true", + "Enable Xtensa HIFI3 instructions">; +def HasHIFI3 : Predicate<"Subtarget->hasHIFI3()">, + AssemblerPredicate<(all_of FeatureHIFI3)>; + //===----------------------------------------------------------------------===// // Xtensa supported processors. //===----------------------------------------------------------------------===// @@ -211,7 +216,7 @@ def : Proc<"cnl", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureWind FeatureTHREADPTR, FeatureDiv32, FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, - FeatureRegionProtection, FeatureMiscSR]>; + FeatureRegionProtection, FeatureMiscSR, FeatureHIFI3]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index e267b71385c0f9..e5639ce706c864 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -77,6 +77,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HasMiscSR = false; HasESP32S2Ops = false; HasESP32S3Ops = false; + HasHIFI3 = false; // Parse features string. ParseSubtargetFeatures(CPUName, CPUName, FS); diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index 03378d8ea032a7..e794edec3f5c5a 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -134,6 +134,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { // Enable Xtensa esp32-s3 ISA extension bool HasESP32S3Ops; + // Enable Xtensa HIFI3 Extension + bool HasHIFI3; + XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: @@ -217,6 +220,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { bool useTextSectionLiterals() const; + bool hasHIFI3() const { return HasHIFI3; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; From 1b5c5c0885112a617bcfe77dd3b8cbef0f959d50 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 13 Nov 2023 12:29:24 +0000 Subject: [PATCH 211/261] [Xtensa] Add HIFI3 instructions --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 4 + .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 14 + .../Target/Xtensa/XtensaHIFIInstrFormats.td | 48 + llvm/lib/Target/Xtensa/XtensaHIFIInstrInfo.td | 34720 ++++++++++++++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 5 + llvm/lib/Target/Xtensa/XtensaOperands.td | 28 + 6 files changed, 34819 insertions(+) create mode 100644 llvm/lib/Target/Xtensa/XtensaHIFIInstrFormats.td create mode 100644 llvm/lib/Target/Xtensa/XtensaHIFIInstrInfo.td diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index db35d3377bbfb4..105e40c02e2a0e 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -255,6 +255,10 @@ struct XtensaOperand : public MCParsedAsmOperand { bool isImm() const override { return Kind == Immediate; } bool isMem() const override { return false; } + template bool isImmInRange() const { + return Kind == Immediate && inRange(getImm(), Lo, Hi); + } + bool isImm(int64_t MinValue, int64_t MaxValue) const { return Kind == Immediate && inRange(getImm(), MinValue, MaxValue); } diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index 9224d0a98c14b5..756554bcf09b96 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -16,7 +16,9 @@ #define LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAINSTPRINTER_H #include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInst.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/raw_ostream.h" namespace llvm { class MCOperand; @@ -82,6 +84,18 @@ class XtensaInstPrinter : public MCInstPrinter { void printOffset_128_2_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset_128_1_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printOffset_64_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + + template + void printImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= lo && Value <= hi && ((Value % step) == 0)) && + "Invalid argument"); + O << Value; + } else { + printOperand(MI, OpNum, O); + } + } }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaHIFIInstrFormats.td b/llvm/lib/Target/Xtensa/XtensaHIFIInstrFormats.td new file mode 100644 index 00000000000000..f06847a0da7ddd --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaHIFIInstrFormats.td @@ -0,0 +1,48 @@ +//===- XtensaHIFIInstrFormats.td - Instruction formats for Xtensa HIFI -*- tablegen -*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains Tablegen instruction formats for Xtensa HIFI extension +// +//===----------------------------------------------------------------------===// + +// Base class for Xtensa 64 bit Format +class XtensaInst64 pattern, + InstrItinClass itin = NoItinerary> + : XtensaInst<8, outs, ins, asmstr, pattern, itin> +{ + bits<64> Inst = 0; + bits<64> SoftFail = 0; + let DecoderNamespace = "HIFI3"; +} + +class XtensaInst48 pattern, + InstrItinClass itin = NoItinerary> + : XtensaInst<6, outs, ins, asmstr, pattern, itin> +{ + bits<48> Inst = 0; + bits<48> SoftFail = 0; + let DecoderNamespace = "HIFI3"; +} + +class XtensaInst88 pattern, + InstrItinClass itin = NoItinerary> + : XtensaInst<11, outs, ins, asmstr, pattern, itin> +{ + bits<88> Inst = 0; + bits<88> SoftFail = 0; + let DecoderNamespace = "HIFI3"; +} + +class XtensaAEInst24 pattern, + InstrItinClass itin = NoItinerary> + : XtensaInst24 { + let DecoderNamespace = "HIFI3"; + let Inst = 0; +} \ No newline at end of file diff --git a/llvm/lib/Target/Xtensa/XtensaHIFIInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaHIFIInstrInfo.td new file mode 100644 index 00000000000000..de373ede0efe12 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaHIFIInstrInfo.td @@ -0,0 +1,34720 @@ +//===- XtensaHIFIInstrInfo.td - Instruction definitions for Xtensa HIFI -*- tablegen -*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains Tablegen instruction definitiona for Xtensa HIFI extension +// +//===----------------------------------------------------------------------===// + +class AE_ABS16S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_abs16s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ABS16S : AE_ABS16S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_abs16s AE_DR:$ae_arth_v1))]>; + +class AE_ABS24S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_abs24s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ABS24S : AE_ABS24S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_abs24s AE_DR:$ae_arth_v1))]>; + +class AE_ABS32_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_abs32 $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{25} = 1; +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_ABS32 : AE_ABS32_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_abs32 AE_DR:$ae_arth_v1))]>; + +class AE_ABS32S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_abs32s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ABS32S : AE_ABS32S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_abs32s AE_DR:$ae_arth_v1))]>; + +class AE_ABS64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_abs64 $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ABS64 : AE_ABS64_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_abs64 AE_DR:$ae_arth_v1))]>; + +class AE_ABS64S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_abs64s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{24} = 1; +let Inst{26} = 1; +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_ABS64S : AE_ABS64S_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_abs64s AE_DR:$ae_arth_v1))]>; + +class AE_ADD16_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_add16 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{50} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_ADD16 : AE_ADD16_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_add16 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADD16S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_add16s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ADD16S : AE_ADD16S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_add16s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADD24S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_add24s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ADD24S : AE_ADD24S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_add24s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADD32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_add32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ADD32 : AE_ADD32_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_add32 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADD32_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_add32_hl_lh $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{51} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_ADD32_HL_LH : AE_ADD32_HL_LH_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_add32_hl_lh AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADD32S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_add32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ADD32S : AE_ADD32S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_add32s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADD64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_add64 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ADD64 : AE_ADD64_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_add64 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADD64S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_add64s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_ADD64S : AE_ADD64S_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_add64s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADDBRBA32_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$arr), (ins AR:$art, AR:$ars), "ae_addbrba32 $arr, $art, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> art; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{20} = arr{0}; +let Inst{21} = arr{1}; +let Inst{22} = arr{2}; +let Inst{23} = arr{3}; +let Inst{24} = art{0}; +let Inst{25} = art{1}; +let Inst{26} = art{2}; +let Inst{27} = art{3}; +let Inst{16} = ars{0}; +let Inst{17} = ars{1}; +let Inst{18} = ars{2}; +let Inst{19} = ars{3}; +} + + + +def AE_ADDBRBA32 : AE_ADDBRBA32_AE_FORMAT48<[(set AR:$arr, (int_xtensa_ae_addbrba32 AR:$art, AR:$ars))]>; + +class AE_ADDSUB32_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_addsub32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_ADDSUB32 : AE_ADDSUB32_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_addsub32 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ADDSUB32S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_addsub32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_ADDSUB32S : AE_ADDSUB32S_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_addsub32s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_AND_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1), "ae_and $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; +bits<4> ae_dr_to_dr_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_dr_to_dr_v{0}; +let Inst{13} = ae_dr_to_dr_v{1}; +let Inst{14} = ae_dr_to_dr_v{2}; +let Inst{15} = ae_dr_to_dr_v{3}; +let Inst{8} = ae_dr_to_dr_v0{0}; +let Inst{9} = ae_dr_to_dr_v0{1}; +let Inst{10} = ae_dr_to_dr_v0{2}; +let Inst{11} = ae_dr_to_dr_v0{3}; +let Inst{4} = ae_dr_to_dr_v1{0}; +let Inst{5} = ae_dr_to_dr_v1{1}; +let Inst{6} = ae_dr_to_dr_v1{2}; +let Inst{7} = ae_dr_to_dr_v1{3}; +} + + + +def AE_AND : AE_AND_X24<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_and AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1))]>; + +class AE_CVT32X2F16_10_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_to_dr_v), (ins AE_DR:$ae_to_dr_v0), "ae_cvt32x2f16.10 $ae_to_dr_v, $ae_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_to_dr_v; +bits<4> ae_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = ae_to_dr_v{0}; +let Inst{13} = ae_to_dr_v{1}; +let Inst{14} = ae_to_dr_v{2}; +let Inst{15} = ae_to_dr_v{3}; +let Inst{8} = ae_to_dr_v0{0}; +let Inst{9} = ae_to_dr_v0{1}; +let Inst{10} = ae_to_dr_v0{2}; +let Inst{11} = ae_to_dr_v0{3}; +} + + + +def AE_CVT32X2F16_10 : AE_CVT32X2F16_10_AE_FORMAT<[(set AE_DR:$ae_to_dr_v, (int_xtensa_ae_cvt32x2f16_10 AE_DR:$ae_to_dr_v0))]>; + +class AE_CVT32X2F16_32_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_to_dr_v), (ins AE_DR:$ae_to_dr_v0), "ae_cvt32x2f16.32 $ae_to_dr_v, $ae_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_to_dr_v; +bits<4> ae_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = ae_to_dr_v{0}; +let Inst{13} = ae_to_dr_v{1}; +let Inst{14} = ae_to_dr_v{2}; +let Inst{15} = ae_to_dr_v{3}; +let Inst{8} = ae_to_dr_v0{0}; +let Inst{9} = ae_to_dr_v0{1}; +let Inst{10} = ae_to_dr_v0{2}; +let Inst{11} = ae_to_dr_v0{3}; +} + + + +def AE_CVT32X2F16_32 : AE_CVT32X2F16_32_AE_FORMAT<[(set AE_DR:$ae_to_dr_v, (int_xtensa_ae_cvt32x2f16_32 AE_DR:$ae_to_dr_v0))]>; + +class AE_CVT48A32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ar_to_dr_v), (ins AR:$ars), "ae_cvt48a32 $ae_ar_to_dr_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ar_to_dr_v; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ar_to_dr_v{0}; +let Inst{13} = ae_ar_to_dr_v{1}; +let Inst{14} = ae_ar_to_dr_v{2}; +let Inst{15} = ae_ar_to_dr_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_CVT48A32 : AE_CVT48A32_X24<[(set AE_DR:$ae_ar_to_dr_v, (int_xtensa_ae_cvt48a32 AR:$ars))]>; + +class AE_CVT64A32_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ar_to_dr_v), (ins AR:$ars), "ae_cvt64a32 $ae_ar_to_dr_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ar_to_dr_v; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{25} = 1; +let Inst{27} = 1; +let Inst{38} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{20} = ae_ar_to_dr_v{0}; +let Inst{21} = ae_ar_to_dr_v{1}; +let Inst{22} = ae_ar_to_dr_v{2}; +let Inst{23} = ae_ar_to_dr_v{3}; +let Inst{16} = ars{0}; +let Inst{17} = ars{1}; +let Inst{18} = ars{2}; +let Inst{19} = ars{3}; +} + + + +def AE_CVT64A32 : AE_CVT64A32_AE_FORMAT48<[(set AE_DR:$ae_ar_to_dr_v, (int_xtensa_ae_cvt64a32 AR:$ars))]>; + +class AE_CVT64F32_H_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0), "ae_cvt64f32.h $ae_dr_to_dr_v, $ae_dr_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{28} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_dr_to_dr_v{0}; +let Inst{21} = ae_dr_to_dr_v{1}; +let Inst{22} = ae_dr_to_dr_v{2}; +let Inst{23} = ae_dr_to_dr_v{3}; +let Inst{36} = ae_dr_to_dr_v0{0}; +let Inst{37} = ae_dr_to_dr_v0{1}; +let Inst{38} = ae_dr_to_dr_v0{2}; +let Inst{39} = ae_dr_to_dr_v0{3}; +} + + + +def AE_CVT64F32_H : AE_CVT64F32_H_AE_FORMAT1<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_cvt64f32_h AE_DR:$ae_dr_to_dr_v0))]>; + +class AE_CVTA32F24S_H_AE_FORMAT pattern> + : XtensaInst64<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_cvta32f24s.h $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{5} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_CVTA32F24S_H : AE_CVTA32F24S_H_AE_FORMAT<[(set AR:$arr, (int_xtensa_ae_cvta32f24s_h AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_CVTA32F24S_L_AE_FORMAT pattern> + : XtensaInst64<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_cvta32f24s.l $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_CVTA32F24S_L : AE_CVTA32F24S_L_AE_FORMAT<[(set AR:$arr, (int_xtensa_ae_cvta32f24s_l AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_CVTQ56A32S_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ar_to_dr_v), (ins AR:$ars), "ae_cvtq56a32s $ae_ar_to_dr_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ar_to_dr_v; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{24} = 1; +let Inst{25} = 1; +let Inst{27} = 1; +let Inst{38} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{20} = ae_ar_to_dr_v{0}; +let Inst{21} = ae_ar_to_dr_v{1}; +let Inst{22} = ae_ar_to_dr_v{2}; +let Inst{23} = ae_ar_to_dr_v{3}; +let Inst{16} = ars{0}; +let Inst{17} = ars{1}; +let Inst{18} = ars{2}; +let Inst{19} = ars{3}; +} + + + +def AE_CVTQ56A32S : AE_CVTQ56A32S_AE_FORMAT48<[(set AE_DR:$ae_ar_to_dr_v, (int_xtensa_ae_cvtq56a32s AR:$ars))]>; + +class AE_CVTQ56P32S_H_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0), "ae_cvtq56p32s.h $ae_dr_to_dr_v, $ae_dr_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{5} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_dr_to_dr_v{0}; +let Inst{13} = ae_dr_to_dr_v{1}; +let Inst{14} = ae_dr_to_dr_v{2}; +let Inst{15} = ae_dr_to_dr_v{3}; +let Inst{8} = ae_dr_to_dr_v0{0}; +let Inst{9} = ae_dr_to_dr_v0{1}; +let Inst{10} = ae_dr_to_dr_v0{2}; +let Inst{11} = ae_dr_to_dr_v0{3}; +} + + + +def AE_CVTQ56P32S_H : AE_CVTQ56P32S_H_X24<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_cvtq56p32s_h AE_DR:$ae_dr_to_dr_v0))]>; + +class AE_CVTQ56P32S_L_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0), "ae_cvtq56p32s.l $ae_dr_to_dr_v, $ae_dr_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_dr_to_dr_v{0}; +let Inst{13} = ae_dr_to_dr_v{1}; +let Inst{14} = ae_dr_to_dr_v{2}; +let Inst{15} = ae_dr_to_dr_v{3}; +let Inst{8} = ae_dr_to_dr_v0{0}; +let Inst{9} = ae_dr_to_dr_v0{1}; +let Inst{10} = ae_dr_to_dr_v0{2}; +let Inst{11} = ae_dr_to_dr_v0{3}; +} + + + +def AE_CVTQ56P32S_L : AE_CVTQ56P32S_L_X24<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_cvtq56p32s_l AE_DR:$ae_dr_to_dr_v0))]>; + +class AE_DB_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art), "ae_db $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{14} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_DB : AE_DB_X24<[(set AR:$ars_out, (int_xtensa_ae_db AR:$ars, AR:$art))]>; + +class AE_DB_IC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art), "ae_db.ic $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_DB_IC : AE_DB_IC_X24<[(set AR:$ars_out, (int_xtensa_ae_db_ic AR:$ars, AR:$art))]>; + +class AE_DB_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art), "ae_db.ip $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_DB_IP : AE_DB_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_db_ip AR:$ars, AR:$art))]>; + +class AE_DBI_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, imm1_16:$ae_ohba), "ae_dbi $ars, $ae_ohba", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> ae_ohba; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{12} = 1; +let Inst{14} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_ohba{0}; +let Inst{5} = ae_ohba{1}; +let Inst{6} = ae_ohba{2}; +let Inst{7} = ae_ohba{3}; +} + + + +def AE_DBI : AE_DBI_X24<[(set AR:$ars_out, (int_xtensa_ae_dbi AR:$ars, timm:$ae_ohba))]>; + +class AE_DBI_IC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, imm1_16:$ae_ohba), "ae_dbi.ic $ars, $ae_ohba", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> ae_ohba; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_ohba{0}; +let Inst{5} = ae_ohba{1}; +let Inst{6} = ae_ohba{2}; +let Inst{7} = ae_ohba{3}; +} + + + +def AE_DBI_IC : AE_DBI_IC_X24<[(set AR:$ars_out, (int_xtensa_ae_dbi_ic AR:$ars, timm:$ae_ohba))]>; + +class AE_DBI_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, imm1_16:$ae_ohba), "ae_dbi.ip $ars, $ae_ohba", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> ae_ohba; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{12} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_ohba{0}; +let Inst{5} = ae_ohba{1}; +let Inst{6} = ae_ohba{2}; +let Inst{7} = ae_ohba{3}; +} + + + +def AE_DBI_IP : AE_DBI_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_dbi_ip AR:$ars, timm:$ae_ohba))]>; + +class AE_DIV64D32_H_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v_out), (ins AE_DR:$ae_arth_v, AE_DR:$ae_arth_v1), "ae_div64d32.h $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; +let Constraints = "$ae_arth_v = $ae_arth_v_out,@earlyclobber $ae_arth_v_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +} + + + +def AE_DIV64D32_H : AE_DIV64D32_H_AE_FORMAT1<[(set AE_DR:$ae_arth_v_out, (int_xtensa_ae_div64d32_h AE_DR:$ae_arth_v, AE_DR:$ae_arth_v1))]>; + +class AE_DIV64D32_L_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v_out), (ins AE_DR:$ae_arth_v, AE_DR:$ae_arth_v1), "ae_div64d32.l $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; +let Constraints = "$ae_arth_v = $ae_arth_v_out,@earlyclobber $ae_arth_v_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{10} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_DIV64D32_L : AE_DIV64D32_L_X24<[(set AE_DR:$ae_arth_v_out, (int_xtensa_ae_div64d32_l AE_DR:$ae_arth_v, AE_DR:$ae_arth_v1))]>; + +class AE_EQ16_AE_FORMAT1 pattern> + : XtensaInst64<(outs BR4:$br4), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_eq16 $br4, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> br4; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{20} = 1; +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{62} = 1; +//operands +let Inst{22} = br4{0}; +let Inst{23} = br4{1}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_EQ16 : AE_EQ16_AE_FORMAT1<[(set BR4:$br4, (int_xtensa_ae_eq16 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_EQ32_X24 pattern> + : XtensaAEInst24<(outs BR2:$br2), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_eq32 $br2, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<3> br2; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +//operands +let Inst{13} = br2{0}; +let Inst{14} = br2{1}; +let Inst{15} = br2{2}; +let Inst{8} = ae_cmpp_v0{0}; +let Inst{9} = ae_cmpp_v0{1}; +let Inst{10} = ae_cmpp_v0{2}; +let Inst{11} = ae_cmpp_v0{3}; +let Inst{4} = ae_cmpp_v1{0}; +let Inst{5} = ae_cmpp_v1{1}; +let Inst{6} = ae_cmpp_v1{2}; +let Inst{7} = ae_cmpp_v1{3}; +} + + + +def AE_EQ32 : AE_EQ32_X24<[(set BR2:$br2, (int_xtensa_ae_eq32 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_EQ64_AE_FORMAT1 pattern> + : XtensaInst64<(outs BR:$br), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_eq64 $br, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> br; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = br{0}; +let Inst{21} = br{1}; +let Inst{22} = br{2}; +let Inst{23} = br{3}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_EQ64 : AE_EQ64_AE_FORMAT1<[(set BR:$br, (int_xtensa_ae_eq64 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_L16_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm16n_14:$ae_immls16), "ae_l16.i $ae_ls_v, $ars, $ae_immls16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls16; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls16{0}; +let Inst{5} = ae_immls16{1}; +let Inst{6} = ae_immls16{2}; +let Inst{7} = ae_immls16{3}; +} + + + +def AE_L16_I : AE_L16_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l16_i AR:$ars, timm:$ae_immls16))]>; + +class AE_L16_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm16n_14:$ae_immls16), "ae_l16.ip $ae_ls_v, $ars, $ae_immls16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls16; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls16{0}; +let Inst{5} = ae_immls16{1}; +let Inst{6} = ae_immls16{2}; +let Inst{7} = ae_immls16{3}; +} + + + +def AE_L16_IP : AE_L16_IP_X24<[]>; + +class AE_L16_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l16.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{30} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16_X : AE_L16_X_AE_FORMAT48<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l16_x AR:$ars, AR:$art))]>; + +class AE_L16_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l16.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16_XC : AE_L16_XC_AE_FORMAT48<[]>; + +class AE_L16_XP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l16.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16_XP : AE_L16_XP_AE_FORMAT48<[]>; + +class AE_L16M_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm16n_14:$ae_immls16), "ae_l16m.i $ae_ls_v, $ars, $ae_immls16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls16; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls16{0}; +let Inst{5} = ae_immls16{1}; +let Inst{6} = ae_immls16{2}; +let Inst{7} = ae_immls16{3}; +} + + + +def AE_L16M_I : AE_L16M_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l16m_i AR:$ars, timm:$ae_immls16))]>; + +class AE_L16M_IU_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm16n_14:$ae_immls16), "ae_l16m.iu $ae_ls_v, $ars, $ae_immls16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls16; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls16{0}; +let Inst{5} = ae_immls16{1}; +let Inst{6} = ae_immls16{2}; +let Inst{7} = ae_immls16{3}; +} + + + +def AE_L16M_IU : AE_L16M_IU_X24<[]>; + +class AE_L16M_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l16m.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16M_X : AE_L16M_X_AE_FORMAT48<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l16m_x AR:$ars, AR:$art))]>; + +class AE_L16M_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l16m.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16M_XC : AE_L16M_XC_AE_FORMAT48<[]>; + +class AE_L16M_XU_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l16m.xu $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16M_XU : AE_L16M_XU_X24<[]>; + +class AE_L16X2M_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm32n_28:$ae_immls32), "ae_l16x2m.i $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_L16X2M_I : AE_L16X2M_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l16x2m_i AR:$ars, timm:$ae_immls32))]>; + +class AE_L16X2M_IU_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm32n_28:$ae_immls32), "ae_l16x2m.iu $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_L16X2M_IU : AE_L16X2M_IU_X24<[]>; + +class AE_L16X2M_X_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l16x2m.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16X2M_X : AE_L16X2M_X_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l16x2m_x AR:$ars, AR:$art))]>; + +class AE_L16X2M_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l16x2m.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16X2M_XC : AE_L16X2M_XC_AE_FORMAT48<[]>; + +class AE_L16X2M_XU_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l16x2m.xu $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16X2M_XU : AE_L16X2M_XU_X24<[]>; + +class AE_L16X4_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm64n_56:$ae_immls64), "ae_l16x4.i $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_L16X4_I : AE_L16X4_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l16x4_i AR:$ars, timm:$ae_immls64))]>; + +class AE_L16X4_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm0_56:$ae_immls64pos), "ae_l16x4.ip $ae_ls_v, $ars, $ae_immls64pos", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<3> ae_immls64pos; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{20} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64pos{0}; +let Inst{5} = ae_immls64pos{1}; +let Inst{6} = ae_immls64pos{2}; +} + + + +def AE_L16X4_IP : AE_L16X4_IP_X24<[]>; + +class AE_L16X4_RIC_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars), "ae_l16x4.ric $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{5} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_L16X4_RIC : AE_L16X4_RIC_AE_FORMAT<[]>; + +class AE_L16X4_RIP_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars), "ae_l16x4.rip $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_L16X4_RIP : AE_L16X4_RIP_AE_FORMAT<[]>; + +class AE_L16X4_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l16x4.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16X4_X : AE_L16X4_X_AE_FORMAT48<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l16x4_x AR:$ars, AR:$art))]>; + +class AE_L16X4_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l16x4.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16X4_XC : AE_L16X4_XC_AE_FORMAT48<[]>; + +class AE_L16X4_XP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l16x4.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L16X4_XP : AE_L16X4_XP_X24<[]>; + +class AE_L32_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm32n_28:$ae_immls32), "ae_l32.i $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_L32_I : AE_L32_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32_i AR:$ars, timm:$ae_immls32))]>; + +class AE_L32_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm32n_28:$ae_immls32), "ae_l32.ip $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_L32_IP : AE_L32_IP_X24<[]>; + +class AE_L32_X_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l32.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32_X : AE_L32_X_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32_x AR:$ars, AR:$art))]>; + +class AE_L32_XC_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32_XC : AE_L32_XC_X24<[]>; + +class AE_L32_XP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32_XP : AE_L32_XP_AE_FORMAT48<[]>; + +class AE_L32F24_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm32n_28:$ae_immls32), "ae_l32f24.i $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_L32F24_I : AE_L32F24_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32f24_i AR:$ars, timm:$ae_immls32))]>; + +class AE_L32F24_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm32n_28:$ae_immls32), "ae_l32f24.ip $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_L32F24_IP : AE_L32F24_IP_X24<[]>; + +class AE_L32F24_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l32f24.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32F24_X : AE_L32F24_X_AE_FORMAT48<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32f24_x AR:$ars, AR:$art))]>; + +class AE_L32F24_XC_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32f24.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32F24_XC : AE_L32F24_XC_X24<[]>; + +class AE_L32F24_XP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32f24.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{31} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32F24_XP : AE_L32F24_XP_AE_FORMAT48<[]>; + +class AE_L32M_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm32n_28:$ae_immls32), "ae_l32m.i $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_L32M_I : AE_L32M_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32m_i AR:$ars, timm:$ae_immls32))]>; + +class AE_L32M_IU_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm32n_28:$ae_immls32), "ae_l32m.iu $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_L32M_IU : AE_L32M_IU_X24<[]>; + +class AE_L32M_X_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l32m.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32M_X : AE_L32M_X_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32m_x AR:$ars, AR:$art))]>; + +class AE_L32M_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32m.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32M_XC : AE_L32M_XC_AE_FORMAT48<[]>; + +class AE_L32M_XU_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32m.xu $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32M_XU : AE_L32M_XU_X24<[]>; + +class AE_L32X2_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm64n_56:$ae_immls64), "ae_l32x2.i $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_L32X2_I : AE_L32X2_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32x2_i AR:$ars, timm:$ae_immls64))]>; + +class AE_L32X2_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm0_56:$ae_immls64pos), "ae_l32x2.ip $ae_ls_v, $ars, $ae_immls64pos", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<3> ae_immls64pos; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64pos{0}; +let Inst{5} = ae_immls64pos{1}; +let Inst{6} = ae_immls64pos{2}; +} + + + +def AE_L32X2_IP : AE_L32X2_IP_X24<[]>; + +class AE_L32X2_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars), "ae_l32x2.ric $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_L32X2_RIC : AE_L32X2_RIC_AE_FORMAT48<[]>; + +class AE_L32X2_RIP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars), "ae_l32x2.rip $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_L32X2_RIP : AE_L32X2_RIP_X24<[]>; + +class AE_L32X2_X_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l32x2.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32X2_X : AE_L32X2_X_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32x2_x AR:$ars, AR:$art))]>; + +class AE_L32X2_XC_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32x2.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32X2_XC : AE_L32X2_XC_X24<[]>; + +class AE_L32X2_XP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32x2.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32X2_XP : AE_L32X2_XP_X24<[]>; + +class AE_L32X2F24_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm64n_56:$ae_immls64), "ae_l32x2f24.i $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_L32X2F24_I : AE_L32X2F24_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32x2f24_i AR:$ars, timm:$ae_immls64))]>; + +class AE_L32X2F24_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm0_56:$ae_immls64pos), "ae_l32x2f24.ip $ae_ls_v, $ars, $ae_immls64pos", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<3> ae_immls64pos; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64pos{0}; +let Inst{5} = ae_immls64pos{1}; +let Inst{6} = ae_immls64pos{2}; +} + + + +def AE_L32X2F24_IP : AE_L32X2F24_IP_X24<[]>; + +class AE_L32X2F24_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars), "ae_l32x2f24.ric $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_L32X2F24_RIC : AE_L32X2F24_RIC_AE_FORMAT48<[]>; + +class AE_L32X2F24_RIP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars), "ae_l32x2f24.rip $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{5} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_L32X2F24_RIP : AE_L32X2F24_RIP_X24<[]>; + +class AE_L32X2F24_X_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l32x2f24.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32X2F24_X : AE_L32X2F24_X_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l32x2f24_x AR:$ars, AR:$art))]>; + +class AE_L32X2F24_XC_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32x2f24.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32X2F24_XC : AE_L32X2F24_XC_X24<[]>; + +class AE_L32X2F24_XP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l32x2f24.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L32X2F24_XP : AE_L32X2F24_XP_X24<[]>; + +class AE_L64_I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v), (ins AR:$ars, imm64n_56:$ae_immls64), "ae_l64.i $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_L64_I : AE_L64_I_X24<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l64_i AR:$ars, timm:$ae_immls64))]>; + +class AE_L64_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, imm64n_56:$ae_immls64), "ae_l64.ip $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_L64_IP : AE_L64_IP_X24<[]>; + +class AE_L64_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v), (ins AR:$ars, AR:$art), "ae_l64.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L64_X : AE_L64_X_AE_FORMAT48<[(set AE_DR:$ae_ls_v, (int_xtensa_ae_l64_x AR:$ars, AR:$art))]>; + +class AE_L64_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l64.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L64_XC : AE_L64_XC_AE_FORMAT48<[]>; + +class AE_L64_XP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_v, AR:$ars_out), (ins AR:$ars, AR:$art), "ae_l64.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_L64_XP : AE_L64_XP_AE_FORMAT48<[]>; + +class AE_LA16X4_IC_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la16x4.ic $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA16X4_IC : AE_LA16X4_IC_X24<[]>; + +class AE_LA16X4_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la16x4.ip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA16X4_IP : AE_LA16X4_IP_X24<[]>; + +class AE_LA16X4_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la16x4.ric $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA16X4_RIC : AE_LA16X4_RIC_AE_FORMAT48<[]>; + +class AE_LA16X4_RIP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la16x4.rip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA16X4_RIP : AE_LA16X4_RIP_X24<[]>; + +class AE_LA16X4NEG_PC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_uu, AR:$ars_out), (ins AR:$ars), "ae_la16x4neg.pc $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA16X4NEG_PC : AE_LA16X4NEG_PC_AE_FORMAT48<[]>; + +class AE_LA16X4POS_PC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_uu, AR:$ars_out), (ins AR:$ars), "ae_la16x4pos.pc $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA16X4POS_PC : AE_LA16X4POS_PC_AE_FORMAT48<[]>; + +class AE_LA24_IC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la24.ic $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24_IC : AE_LA24_IC_AE_FORMAT48<[]>; + +class AE_LA24_IP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la24.ip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24_IP : AE_LA24_IP_AE_FORMAT48<[]>; + +class AE_LA24_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la24.ric $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24_RIC : AE_LA24_RIC_AE_FORMAT48<[]>; + +class AE_LA24_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la24.rip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24_RIP : AE_LA24_RIP_AE_FORMAT48<[]>; + +class AE_LA24NEG_PC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_uu, AR:$ars_out), (ins AR:$ars), "ae_la24neg.pc $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24NEG_PC : AE_LA24NEG_PC_AE_FORMAT48<[]>; + +class AE_LA24POS_PC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_uu, AR:$ars_out), (ins AR:$ars), "ae_la24pos.pc $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24POS_PC : AE_LA24POS_PC_AE_FORMAT48<[]>; + +class AE_LA24X2_IC_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la24x2.ic $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24X2_IC : AE_LA24X2_IC_X24<[]>; + +class AE_LA24X2_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la24x2.ip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24X2_IP : AE_LA24X2_IP_X24<[]>; + +class AE_LA24X2_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la24x2.ric $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{29} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24X2_RIC : AE_LA24X2_RIC_AE_FORMAT48<[]>; + +class AE_LA24X2_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la24x2.rip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24X2_RIP : AE_LA24X2_RIP_AE_FORMAT48<[]>; + +class AE_LA24X2NEG_PC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_uu, AR:$ars_out), (ins AR:$ars), "ae_la24x2neg.pc $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24X2NEG_PC : AE_LA24X2NEG_PC_AE_FORMAT48<[]>; + +class AE_LA24X2POS_PC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_uu, AR:$ars_out), (ins AR:$ars), "ae_la24x2pos.pc $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA24X2POS_PC : AE_LA24X2POS_PC_AE_FORMAT48<[]>; + +class AE_LA32X2_IC_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la32x2.ic $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2_IC : AE_LA32X2_IC_X24<[]>; + +class AE_LA32X2_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la32x2.ip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2_IP : AE_LA32X2_IP_X24<[]>; + +class AE_LA32X2_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la32x2.ric $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2_RIC : AE_LA32X2_RIC_AE_FORMAT48<[]>; + +class AE_LA32X2_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la32x2.rip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2_RIP : AE_LA32X2_RIP_AE_FORMAT48<[]>; + +class AE_LA32X2F24_IC_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la32x2f24.ic $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2F24_IC : AE_LA32X2F24_IC_X24<[]>; + +class AE_LA32X2F24_IP_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la32x2f24.ip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2F24_IP : AE_LA32X2F24_IP_X24<[]>; + +class AE_LA32X2F24_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la32x2f24.ric $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2F24_RIC : AE_LA32X2F24_RIC_AE_FORMAT48<[]>; + +class AE_LA32X2F24_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_DR:$ae_ls_av, AE_VALIGN:$ae_ls_uu_out, AR:$ars_out), (ins AE_VALIGN:$ae_ls_uu, AR:$ars), "ae_la32x2f24.rip $ae_ls_av, $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_av; +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ae_ls_uu = $ae_ls_uu_out,@earlyclobber $ae_ls_uu_out, $ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_av{0}; +let Inst{13} = ae_ls_av{1}; +let Inst{14} = ae_ls_av{2}; +let Inst{15} = ae_ls_av{3}; +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2F24_RIP : AE_LA32X2F24_RIP_AE_FORMAT48<[]>; + +class AE_LA32X2NEG_PC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_uu, AR:$ars_out), (ins AR:$ars), "ae_la32x2neg.pc $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2NEG_PC : AE_LA32X2NEG_PC_AE_FORMAT48<[]>; + +class AE_LA32X2POS_PC_X24 pattern> + : XtensaAEInst24<(outs AE_VALIGN:$ae_ls_uu, AR:$ars_out), (ins AR:$ars), "ae_la32x2pos.pc $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{12} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA32X2POS_PC : AE_LA32X2POS_PC_X24<[]>; + +class AE_LA64_PP_X24 pattern> + : XtensaAEInst24<(outs AE_VALIGN:$ae_ls_uu), (ins AR:$ars), "ae_la64.pp $ae_ls_uu, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{13} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = ae_ls_uu{0}; +let Inst{5} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_LA64_PP : AE_LA64_PP_X24<[(set AE_VALIGN:$ae_ls_uu, (int_xtensa_ae_la64_pp AR:$ars))]>; + +class AE_LALIGN64_I_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_uu), (ins AR:$ars, imm64n_56:$ae_immls64), "ae_lalign64.i $ae_ls_uu, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_uu; +bits<4> ars; +bits<4> ae_immls64; + +let mayLoad = 1; +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{30} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_uu{0}; +let Inst{7} = ae_ls_uu{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{28} = ae_immls64{2}; +let Inst{29} = ae_immls64{3}; +} + + + +def AE_LALIGN64_I : AE_LALIGN64_I_AE_FORMAT48<[(set AE_VALIGN:$ae_ls_uu, (int_xtensa_ae_lalign64_i AR:$ars, timm:$ae_immls64))]>; + +class AE_LB_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AR:$art), "ae_lb $arr, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{16} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_LB : AE_LB_X24<[(set AR:$arr, (int_xtensa_ae_lb AR:$art))]>; + +class AE_LBI_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins imm1_16:$ae_ohba), "ae_lbi $arr, $ae_ohba", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_ohba; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{16} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{4} = ae_ohba{0}; +let Inst{5} = ae_ohba{1}; +let Inst{6} = ae_ohba{2}; +let Inst{7} = ae_ohba{3}; +} + + + +def AE_LBI : AE_LBI_X24<[(set AR:$arr, (int_xtensa_ae_lbi timm:$ae_ohba))]>; + +class AE_LBK_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AR:$ars, AR:$art), "ae_lbk $arr, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ars; +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_LBK : AE_LBK_X24<[(set AR:$arr, (int_xtensa_ae_lbk AR:$ars, AR:$art))]>; + +class AE_LBKI_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AR:$ars, imm1_16:$ae_ohba), "ae_lbki $arr, $ars, $ae_ohba", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ars; +bits<4> ae_ohba; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_ohba{0}; +let Inst{5} = ae_ohba{1}; +let Inst{6} = ae_ohba{2}; +let Inst{7} = ae_ohba{3}; +} + + + +def AE_LBKI : AE_LBKI_X24<[(set AR:$arr, (int_xtensa_ae_lbki AR:$ars, timm:$ae_ohba))]>; + +class AE_LBS_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AR:$art), "ae_lbs $arr, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{16} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_LBS : AE_LBS_X24<[(set AR:$arr, (int_xtensa_ae_lbs AR:$art))]>; + +class AE_LBSI_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins imm1_16:$ae_ohba), "ae_lbsi $arr, $ae_ohba", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_ohba; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{16} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{4} = ae_ohba{0}; +let Inst{5} = ae_ohba{1}; +let Inst{6} = ae_ohba{2}; +let Inst{7} = ae_ohba{3}; +} + + + +def AE_LBSI : AE_LBSI_X24<[(set AR:$arr, (int_xtensa_ae_lbsi timm:$ae_ohba))]>; + +class AE_LE16_AE_FORMAT1 pattern> + : XtensaInst64<(outs BR4:$br4), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_le16 $br4, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> br4; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{62} = 1; +//operands +let Inst{22} = br4{0}; +let Inst{23} = br4{1}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_LE16 : AE_LE16_AE_FORMAT1<[(set BR4:$br4, (int_xtensa_ae_le16 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_LE32_AE_FORMAT1 pattern> + : XtensaInst64<(outs BR2:$br2), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_le32 $br2, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<3> br2; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{20} = 1; +let Inst{57} = 1; +let Inst{62} = 1; +//operands +let Inst{21} = br2{0}; +let Inst{22} = br2{1}; +let Inst{23} = br2{2}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_LE32 : AE_LE32_AE_FORMAT1<[(set BR2:$br2, (int_xtensa_ae_le32 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_LE64_X24 pattern> + : XtensaAEInst24<(outs BR:$br), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_le64 $br, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> br; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = br{0}; +let Inst{13} = br{1}; +let Inst{14} = br{2}; +let Inst{15} = br{3}; +let Inst{8} = ae_cmpp_v0{0}; +let Inst{9} = ae_cmpp_v0{1}; +let Inst{10} = ae_cmpp_v0{2}; +let Inst{11} = ae_cmpp_v0{3}; +let Inst{4} = ae_cmpp_v1{0}; +let Inst{5} = ae_cmpp_v1{1}; +let Inst{6} = ae_cmpp_v1{2}; +let Inst{7} = ae_cmpp_v1{3}; +} + + + +def AE_LE64 : AE_LE64_X24<[(set BR:$br, (int_xtensa_ae_le64 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_LT16_AE_FORMAT1 pattern> + : XtensaInst64<(outs BR4:$br4), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_lt16 $br4, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> br4; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{22} = br4{0}; +let Inst{23} = br4{1}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_LT16 : AE_LT16_AE_FORMAT1<[(set BR4:$br4, (int_xtensa_ae_lt16 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_LT32_X24 pattern> + : XtensaAEInst24<(outs BR2:$br2), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_lt32 $br2, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<3> br2; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{12} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +//operands +let Inst{13} = br2{0}; +let Inst{14} = br2{1}; +let Inst{15} = br2{2}; +let Inst{8} = ae_cmpp_v0{0}; +let Inst{9} = ae_cmpp_v0{1}; +let Inst{10} = ae_cmpp_v0{2}; +let Inst{11} = ae_cmpp_v0{3}; +let Inst{4} = ae_cmpp_v1{0}; +let Inst{5} = ae_cmpp_v1{1}; +let Inst{6} = ae_cmpp_v1{2}; +let Inst{7} = ae_cmpp_v1{3}; +} + + + +def AE_LT32 : AE_LT32_X24<[(set BR2:$br2, (int_xtensa_ae_lt32 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_LT64_X24 pattern> + : XtensaAEInst24<(outs BR:$br), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_lt64 $br, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> br; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = br{0}; +let Inst{13} = br{1}; +let Inst{14} = br{2}; +let Inst{15} = br{3}; +let Inst{8} = ae_cmpp_v0{0}; +let Inst{9} = ae_cmpp_v0{1}; +let Inst{10} = ae_cmpp_v0{2}; +let Inst{11} = ae_cmpp_v0{3}; +let Inst{4} = ae_cmpp_v1{0}; +let Inst{5} = ae_cmpp_v1{1}; +let Inst{6} = ae_cmpp_v1{2}; +let Inst{7} = ae_cmpp_v1{3}; +} + + + +def AE_LT64 : AE_LT64_X24<[(set BR:$br, (int_xtensa_ae_lt64 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MAX32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_cmpp_v), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_max32 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmpp_v; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_cmpp_v{0}; +let Inst{13} = ae_cmpp_v{1}; +let Inst{14} = ae_cmpp_v{2}; +let Inst{15} = ae_cmpp_v{3}; +let Inst{8} = ae_cmpp_v0{0}; +let Inst{9} = ae_cmpp_v0{1}; +let Inst{10} = ae_cmpp_v0{2}; +let Inst{11} = ae_cmpp_v0{3}; +let Inst{4} = ae_cmpp_v1{0}; +let Inst{5} = ae_cmpp_v1{1}; +let Inst{6} = ae_cmpp_v1{2}; +let Inst{7} = ae_cmpp_v1{3}; +} + + + +def AE_MAX32 : AE_MAX32_X24<[(set AE_DR:$ae_cmpp_v, (int_xtensa_ae_max32 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MAX64_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmpp_v), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_max64 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmpp_v; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_cmpp_v{0}; +let Inst{21} = ae_cmpp_v{1}; +let Inst{22} = ae_cmpp_v{2}; +let Inst{23} = ae_cmpp_v{3}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_MAX64 : AE_MAX64_AE_FORMAT1<[(set AE_DR:$ae_cmpp_v, (int_xtensa_ae_max64 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MAXABS32S_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmpp_v), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_maxabs32s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmpp_v; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_cmpp_v{0}; +let Inst{21} = ae_cmpp_v{1}; +let Inst{22} = ae_cmpp_v{2}; +let Inst{23} = ae_cmpp_v{3}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_MAXABS32S : AE_MAXABS32S_AE_FORMAT1<[(set AE_DR:$ae_cmpp_v, (int_xtensa_ae_maxabs32s AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MAXABS64S_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmpp_v), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_maxabs64s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmpp_v; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_cmpp_v{0}; +let Inst{21} = ae_cmpp_v{1}; +let Inst{22} = ae_cmpp_v{2}; +let Inst{23} = ae_cmpp_v{3}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_MAXABS64S : AE_MAXABS64S_AE_FORMAT1<[(set AE_DR:$ae_cmpp_v, (int_xtensa_ae_maxabs64s AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MIN32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_cmpp_v), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_min32 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmpp_v; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_cmpp_v{0}; +let Inst{13} = ae_cmpp_v{1}; +let Inst{14} = ae_cmpp_v{2}; +let Inst{15} = ae_cmpp_v{3}; +let Inst{8} = ae_cmpp_v0{0}; +let Inst{9} = ae_cmpp_v0{1}; +let Inst{10} = ae_cmpp_v0{2}; +let Inst{11} = ae_cmpp_v0{3}; +let Inst{4} = ae_cmpp_v1{0}; +let Inst{5} = ae_cmpp_v1{1}; +let Inst{6} = ae_cmpp_v1{2}; +let Inst{7} = ae_cmpp_v1{3}; +} + + + +def AE_MIN32 : AE_MIN32_X24<[(set AE_DR:$ae_cmpp_v, (int_xtensa_ae_min32 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MIN64_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmpp_v), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_min64 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmpp_v; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_cmpp_v{0}; +let Inst{21} = ae_cmpp_v{1}; +let Inst{22} = ae_cmpp_v{2}; +let Inst{23} = ae_cmpp_v{3}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_MIN64 : AE_MIN64_AE_FORMAT1<[(set AE_DR:$ae_cmpp_v, (int_xtensa_ae_min64 AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MINABS32S_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmpp_v), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_minabs32s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmpp_v; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_cmpp_v{0}; +let Inst{21} = ae_cmpp_v{1}; +let Inst{22} = ae_cmpp_v{2}; +let Inst{23} = ae_cmpp_v{3}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_MINABS32S : AE_MINABS32S_AE_FORMAT1<[(set AE_DR:$ae_cmpp_v, (int_xtensa_ae_minabs32s AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MINABS64S_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmpp_v), (ins AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1), "ae_minabs64s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmpp_v; +bits<4> ae_cmpp_v0; +bits<4> ae_cmpp_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_cmpp_v{0}; +let Inst{21} = ae_cmpp_v{1}; +let Inst{22} = ae_cmpp_v{2}; +let Inst{23} = ae_cmpp_v{3}; +let Inst{36} = ae_cmpp_v0{0}; +let Inst{37} = ae_cmpp_v0{1}; +let Inst{38} = ae_cmpp_v0{2}; +let Inst{39} = ae_cmpp_v0{3}; +let Inst{28} = ae_cmpp_v1{0}; +let Inst{29} = ae_cmpp_v1{1}; +let Inst{30} = ae_cmpp_v1{2}; +let Inst{31} = ae_cmpp_v1{3}; +} + + + +def AE_MINABS64S : AE_MINABS64S_AE_FORMAT1<[(set AE_DR:$ae_cmpp_v, (int_xtensa_ae_minabs64s AE_DR:$ae_cmpp_v0, AE_DR:$ae_cmpp_v1))]>; + +class AE_MOV_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_to_dr_v), (ins AE_DR:$ae_to_dr_v0), "ae_mov $ae_to_dr_v, $ae_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_to_dr_v; +bits<4> ae_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_to_dr_v{0}; +let Inst{13} = ae_to_dr_v{1}; +let Inst{14} = ae_to_dr_v{2}; +let Inst{15} = ae_to_dr_v{3}; +let Inst{8} = ae_to_dr_v0{0}; +let Inst{9} = ae_to_dr_v0{1}; +let Inst{10} = ae_to_dr_v0{2}; +let Inst{11} = ae_to_dr_v0{3}; +} + + + +def AE_MOV : AE_MOV_X24<[(set AE_DR:$ae_to_dr_v, (int_xtensa_ae_mov AE_DR:$ae_to_dr_v0))]>; + +class AE_MOVAD16_0_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_movad16.0 $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_MOVAD16_0 : AE_MOVAD16_0_X24<[(set AR:$arr, (int_xtensa_ae_movad16_0 AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_MOVAD16_1_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_movad16.1 $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{11} = 1; +let Inst{31} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{4} = ae_dr_to_ar_v0{0}; +let Inst{5} = ae_dr_to_ar_v0{1}; +let Inst{6} = ae_dr_to_ar_v0{2}; +let Inst{7} = ae_dr_to_ar_v0{3}; +} + + + +def AE_MOVAD16_1 : AE_MOVAD16_1_AE_FORMAT48<[(set AR:$arr, (int_xtensa_ae_movad16_1 AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_MOVAD16_2_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_movad16.2 $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_MOVAD16_2 : AE_MOVAD16_2_X24<[(set AR:$arr, (int_xtensa_ae_movad16_2 AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_MOVAD16_3_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_movad16.3 $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{5} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_MOVAD16_3 : AE_MOVAD16_3_X24<[(set AR:$arr, (int_xtensa_ae_movad16_3 AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_MOVAD32_H_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_movad32.h $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_MOVAD32_H : AE_MOVAD32_H_X24<[(set AR:$arr, (int_xtensa_ae_movad32_h AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_MOVAD32_L_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_movad32.l $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_MOVAD32_L : AE_MOVAD32_L_X24<[(set AR:$arr, (int_xtensa_ae_movad32_l AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_MOVALIGN_X24 pattern> + : XtensaAEInst24<(outs AE_VALIGN:$ae_uu_uu), (ins AE_VALIGN:$ae_uu_v), "ae_movalign $ae_uu_uu, $ae_uu_v", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_uu_uu; +bits<2> ae_uu_v; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{6} = ae_uu_uu{0}; +let Inst{7} = ae_uu_uu{1}; +let Inst{4} = ae_uu_v{0}; +let Inst{5} = ae_uu_v{1}; +} + + + +def AE_MOVALIGN : AE_MOVALIGN_X24<[(set AE_VALIGN:$ae_uu_uu, (int_xtensa_ae_movalign AE_VALIGN:$ae_uu_v))]>; + +class AE_MOVDA16_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ar_to_dr_v), (ins AR:$ars), "ae_movda16 $ae_ar_to_dr_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ar_to_dr_v; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{5} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ar_to_dr_v{0}; +let Inst{13} = ae_ar_to_dr_v{1}; +let Inst{14} = ae_ar_to_dr_v{2}; +let Inst{15} = ae_ar_to_dr_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_MOVDA16 : AE_MOVDA16_X24<[(set AE_DR:$ae_ar_to_dr_v, (int_xtensa_ae_movda16 AR:$ars))]>; + +class AE_MOVDA16X2_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ar_to_dr_v), (ins AR:$ars, AR:$art), "ae_movda16x2 $ae_ar_to_dr_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ar_to_dr_v; +bits<4> ars; +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +//operands +let Inst{12} = ae_ar_to_dr_v{0}; +let Inst{13} = ae_ar_to_dr_v{1}; +let Inst{14} = ae_ar_to_dr_v{2}; +let Inst{15} = ae_ar_to_dr_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_MOVDA16X2 : AE_MOVDA16X2_X24<[(set AE_DR:$ae_ar_to_dr_v, (int_xtensa_ae_movda16x2 AR:$ars, AR:$art))]>; + +class AE_MOVDA32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ar_to_dr_v), (ins AR:$ars), "ae_movda32 $ae_ar_to_dr_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ar_to_dr_v; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ar_to_dr_v{0}; +let Inst{13} = ae_ar_to_dr_v{1}; +let Inst{14} = ae_ar_to_dr_v{2}; +let Inst{15} = ae_ar_to_dr_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_MOVDA32 : AE_MOVDA32_X24<[(set AE_DR:$ae_ar_to_dr_v, (int_xtensa_ae_movda32 AR:$ars))]>; + +class AE_MOVDA32X2_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ar_to_dr_v), (ins AR:$ars, AR:$art), "ae_movda32x2 $ae_ar_to_dr_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ar_to_dr_v; +bits<4> ars; +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +//operands +let Inst{12} = ae_ar_to_dr_v{0}; +let Inst{13} = ae_ar_to_dr_v{1}; +let Inst{14} = ae_ar_to_dr_v{2}; +let Inst{15} = ae_ar_to_dr_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_MOVDA32X2 : AE_MOVDA32X2_X24<[(set AE_DR:$ae_ar_to_dr_v, (int_xtensa_ae_movda32x2 AR:$ars, AR:$art))]>; + +class AE_MOVF16X4_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmov_v_out), (ins AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR4:$bt4), "ae_movf16x4 $ae_cmov_v, $ae_cmov_v0, $bt4", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmov_v; +bits<4> ae_cmov_v0; +bits<2> bt4; +let Constraints = "$ae_cmov_v = $ae_cmov_v_out,@earlyclobber $ae_cmov_v_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_cmov_v{0}; +let Inst{21} = ae_cmov_v{1}; +let Inst{22} = ae_cmov_v{2}; +let Inst{23} = ae_cmov_v{3}; +let Inst{36} = ae_cmov_v0{0}; +let Inst{37} = ae_cmov_v0{1}; +let Inst{38} = ae_cmov_v0{2}; +let Inst{39} = ae_cmov_v0{3}; +let Inst{30} = bt4{0}; +let Inst{31} = bt4{1}; +} + + + +def AE_MOVF16X4 : AE_MOVF16X4_AE_FORMAT1<[(set AE_DR:$ae_cmov_v_out, (int_xtensa_ae_movf16x4 AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR4:$bt4))]>; + +class AE_MOVF32X2_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_cmov_v_out), (ins AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR2:$bt2), "ae_movf32x2 $ae_cmov_v, $ae_cmov_v0, $bt2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmov_v; +bits<4> ae_cmov_v0; +bits<3> bt2; +let Constraints = "$ae_cmov_v = $ae_cmov_v_out,@earlyclobber $ae_cmov_v_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_cmov_v{0}; +let Inst{13} = ae_cmov_v{1}; +let Inst{14} = ae_cmov_v{2}; +let Inst{15} = ae_cmov_v{3}; +let Inst{8} = ae_cmov_v0{0}; +let Inst{9} = ae_cmov_v0{1}; +let Inst{10} = ae_cmov_v0{2}; +let Inst{11} = ae_cmov_v0{3}; +let Inst{5} = bt2{0}; +let Inst{6} = bt2{1}; +let Inst{7} = bt2{2}; +} + + + +def AE_MOVF32X2 : AE_MOVF32X2_X24<[(set AE_DR:$ae_cmov_v_out, (int_xtensa_ae_movf32x2 AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR2:$bt2))]>; + +class AE_MOVF64_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmov_v_out), (ins AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR:$bt), "ae_movf64 $ae_cmov_v, $ae_cmov_v0, $bt", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmov_v; +bits<4> ae_cmov_v0; +bits<4> bt; +let Constraints = "$ae_cmov_v = $ae_cmov_v_out,@earlyclobber $ae_cmov_v_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{62} = 1; +//operands +let Inst{20} = ae_cmov_v{0}; +let Inst{21} = ae_cmov_v{1}; +let Inst{22} = ae_cmov_v{2}; +let Inst{23} = ae_cmov_v{3}; +let Inst{36} = ae_cmov_v0{0}; +let Inst{37} = ae_cmov_v0{1}; +let Inst{38} = ae_cmov_v0{2}; +let Inst{39} = ae_cmov_v0{3}; +let Inst{28} = bt{0}; +let Inst{29} = bt{1}; +let Inst{30} = bt{2}; +let Inst{31} = bt{3}; +} + + + +def AE_MOVF64 : AE_MOVF64_AE_FORMAT1<[(set AE_DR:$ae_cmov_v_out, (int_xtensa_ae_movf64 AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR:$bt))]>; + +class AE_MOVI_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_ar_to_dr_v), (ins imm16n_47:$movi_imm), "ae_movi $ae_ar_to_dr_v, $movi_imm", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ar_to_dr_v; +bits<6> movi_imm; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ar_to_dr_v{0}; +let Inst{13} = ae_ar_to_dr_v{1}; +let Inst{14} = ae_ar_to_dr_v{2}; +let Inst{15} = ae_ar_to_dr_v{3}; +let Inst{4} = movi_imm{0}; +let Inst{5} = movi_imm{1}; +let Inst{8} = movi_imm{2}; +let Inst{9} = movi_imm{3}; +let Inst{10} = movi_imm{4}; +let Inst{11} = movi_imm{5}; +} + + + +def AE_MOVI : AE_MOVI_X24<[(set AE_DR:$ae_ar_to_dr_v, (int_xtensa_ae_movi timm:$movi_imm))]>; + +class AE_MOVT16X4_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_cmov_v_out), (ins AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR4:$bt4), "ae_movt16x4 $ae_cmov_v, $ae_cmov_v0, $bt4", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmov_v; +bits<4> ae_cmov_v0; +bits<2> bt4; +let Constraints = "$ae_cmov_v = $ae_cmov_v_out,@earlyclobber $ae_cmov_v_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{28} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_cmov_v{0}; +let Inst{21} = ae_cmov_v{1}; +let Inst{22} = ae_cmov_v{2}; +let Inst{23} = ae_cmov_v{3}; +let Inst{36} = ae_cmov_v0{0}; +let Inst{37} = ae_cmov_v0{1}; +let Inst{38} = ae_cmov_v0{2}; +let Inst{39} = ae_cmov_v0{3}; +let Inst{30} = bt4{0}; +let Inst{31} = bt4{1}; +} + + + +def AE_MOVT16X4 : AE_MOVT16X4_AE_FORMAT1<[(set AE_DR:$ae_cmov_v_out, (int_xtensa_ae_movt16x4 AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR4:$bt4))]>; + +class AE_MOVT32X2_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_cmov_v_out), (ins AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR2:$bt2), "ae_movt32x2 $ae_cmov_v, $ae_cmov_v0, $bt2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmov_v; +bits<4> ae_cmov_v0; +bits<3> bt2; +let Constraints = "$ae_cmov_v = $ae_cmov_v_out,@earlyclobber $ae_cmov_v_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_cmov_v{0}; +let Inst{13} = ae_cmov_v{1}; +let Inst{14} = ae_cmov_v{2}; +let Inst{15} = ae_cmov_v{3}; +let Inst{8} = ae_cmov_v0{0}; +let Inst{9} = ae_cmov_v0{1}; +let Inst{10} = ae_cmov_v0{2}; +let Inst{11} = ae_cmov_v0{3}; +let Inst{5} = bt2{0}; +let Inst{6} = bt2{1}; +let Inst{7} = bt2{2}; +} + + + +def AE_MOVT32X2 : AE_MOVT32X2_X24<[(set AE_DR:$ae_cmov_v_out, (int_xtensa_ae_movt32x2 AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR2:$bt2))]>; + +class AE_MOVT64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_cmov_v_out), (ins AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR:$bt), "ae_movt64 $ae_cmov_v, $ae_cmov_v0, $bt", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_cmov_v; +bits<4> ae_cmov_v0; +bits<4> bt; +let Constraints = "$ae_cmov_v = $ae_cmov_v_out,@earlyclobber $ae_cmov_v_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_cmov_v{0}; +let Inst{13} = ae_cmov_v{1}; +let Inst{14} = ae_cmov_v{2}; +let Inst{15} = ae_cmov_v{3}; +let Inst{8} = ae_cmov_v0{0}; +let Inst{9} = ae_cmov_v0{1}; +let Inst{10} = ae_cmov_v0{2}; +let Inst{11} = ae_cmov_v0{3}; +let Inst{4} = bt{0}; +let Inst{5} = bt{1}; +let Inst{6} = bt{2}; +let Inst{7} = bt{3}; +} + + + +def AE_MOVT64 : AE_MOVT64_X24<[(set AE_DR:$ae_cmov_v_out, (int_xtensa_ae_movt64 AE_DR:$ae_cmov_v, AE_DR:$ae_cmov_v0, BR:$bt))]>; + +class AE_MUL16X4_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q1, AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d0), "ae_mul16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q1; +bits<4> ae_mul_q0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +} + + + +def AE_MUL16X4 : AE_MUL16X4_AE_FORMAT2<[]>; + +class AE_MUL32_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32_HH : AE_MUL32_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32_hh AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32_LH : AE_MUL32_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32_lh AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32_LL : AE_MUL32_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32_ll AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32_LL_S2 : AE_MUL32_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MUL32U_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32U_LL : AE_MUL32U_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32u_ll AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_H0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32X16_H0 : AE_MUL32X16_H0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32x16_h0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_H0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32X16_H0_S2 : AE_MUL32X16_H0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32x16_h0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MUL32X16_H1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32X16_H1 : AE_MUL32X16_H1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32x16_h1 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_H1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32X16_H1_S2 : AE_MUL32X16_H1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32x16_h1_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MUL32X16_H2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32X16_H2 : AE_MUL32X16_H2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32x16_h2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_H2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32X16_H2_S2 : AE_MUL32X16_H2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32x16_h2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MUL32X16_H3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32X16_H3 : AE_MUL32X16_H3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32x16_h3 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_H3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32X16_H3_S2 : AE_MUL32X16_H3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32x16_h3_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MUL32X16_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32X16_L0 : AE_MUL32X16_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32x16_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32X16_L0_S2 : AE_MUL32X16_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32x16_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MUL32X16_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32X16_L1 : AE_MUL32X16_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32x16_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32X16_L1_S2 : AE_MUL32X16_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32x16_l1_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MUL32X16_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32X16_L2 : AE_MUL32X16_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32x16_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32X16_L2_S2 : AE_MUL32X16_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32x16_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MUL32X16_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mul32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MUL32X16_L3 : AE_MUL32X16_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mul32x16_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MUL32X16_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mul32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MUL32X16_L3_S2 : AE_MUL32X16_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mul32x16_l3_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA16X4_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q1_out, AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q1, AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d0), "ae_mula16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q1; +bits<4> ae_mul_q0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d0; +let Constraints = "$ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out, $ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +} + + + +def AE_MULA16X4 : AE_MULA16X4_AE_FORMAT2<[]>; + +class AE_MULA32_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32_HH : AE_MULA32_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32_hh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32_LH : AE_MULA32_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32_lh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32_LL : AE_MULA32_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32_LL_S2 : AE_MULA32_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA32U_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32U_LL : AE_MULA32U_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32u_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_H0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32X16_H0 : AE_MULA32X16_H0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32x16_h0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_H0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32X16_H0_S2 : AE_MULA32X16_H0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32x16_h0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA32X16_H1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32X16_H1 : AE_MULA32X16_H1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32x16_h1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_H1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32X16_H1_S2 : AE_MULA32X16_H1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32x16_h1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA32X16_H2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32X16_H2 : AE_MULA32X16_H2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32x16_h2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_H2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32X16_H2_S2 : AE_MULA32X16_H2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32x16_h2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA32X16_H3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32X16_H3 : AE_MULA32X16_H3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32x16_h3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_H3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32X16_H3_S2 : AE_MULA32X16_H3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32x16_h3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA32X16_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32X16_L0 : AE_MULA32X16_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32x16_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32X16_L0_S2 : AE_MULA32X16_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32x16_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA32X16_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32X16_L1 : AE_MULA32X16_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32x16_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32X16_L1_S2 : AE_MULA32X16_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32x16_l1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA32X16_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32X16_L2 : AE_MULA32X16_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32x16_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32X16_L2_S2 : AE_MULA32X16_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32x16_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULA32X16_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mula32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULA32X16_L3 : AE_MULA32X16_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mula32x16_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULA32X16_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mula32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULA32X16_L3_S2 : AE_MULA32X16_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mula32x16_l3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAAD24_HH_LL : AE_MULAAD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaad24_hh_ll AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAAD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAD24_HH_LL_S2 : AE_MULAAD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaad24_hh_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaad24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAAD24_HL_LH : AE_MULAAD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaad24_hl_lh AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAAD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaad24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAD24_HL_LH_S2 : AE_MULAAD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaad24_hl_lh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAD32X16_H0_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaad32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAD32X16_H0_L1 : AE_MULAAD32X16_H0_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaad32x16_h0_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAD32X16_H0_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaad32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAD32X16_H0_L1_S2 : AE_MULAAD32X16_H0_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaad32x16_h0_l1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaad32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAD32X16_H1_L0 : AE_MULAAD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaad32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAD32X16_H1_L0_S2 : AE_MULAAD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaad32x16_h1_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAD32X16_H2_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaad32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAD32X16_H2_L3 : AE_MULAAD32X16_H2_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaad32x16_h2_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAD32X16_H2_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaad32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAD32X16_H2_L3_S2 : AE_MULAAD32X16_H2_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaad32x16_h2_l3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaad32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAD32X16_H3_L2 : AE_MULAAD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaad32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAD32X16_H3_L2_S2 : AE_MULAAD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaad32x16_h3_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD16SS_11_00_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaafd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAFD16SS_11_00 : AE_MULAAFD16SS_11_00_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaafd16ss_11_00 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAFD16SS_11_00_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD16SS_11_00_S2 : AE_MULAAFD16SS_11_00_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd16ss_11_00_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD16SS_13_02_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaafd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAFD16SS_13_02 : AE_MULAAFD16SS_13_02_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaafd16ss_13_02 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAFD16SS_13_02_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD16SS_13_02_S2 : AE_MULAAFD16SS_13_02_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd16ss_13_02_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD16SS_33_22_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaafd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAFD16SS_33_22 : AE_MULAAFD16SS_33_22_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaafd16ss_33_22 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAFD16SS_33_22_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD16SS_33_22_S2 : AE_MULAAFD16SS_33_22_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd16ss_33_22_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{50} = 1; +let Inst{53} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAAFD24_HH_LL : AE_MULAAFD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaafd24_hh_ll AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAAFD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD24_HH_LL_S2 : AE_MULAAFD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd24_hh_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaafd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{53} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAAFD24_HL_LH : AE_MULAAFD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaafd24_hl_lh AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAAFD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD24_HL_LH_S2 : AE_MULAAFD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd24_hl_lh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD32X16_H0_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaafd32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAFD32X16_H0_L1 : AE_MULAAFD32X16_H0_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaafd32x16_h0_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAFD32X16_H0_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD32X16_H0_L1_S2 : AE_MULAAFD32X16_H0_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd32x16_h0_l1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAFD32X16_H1_L0 : AE_MULAAFD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaafd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAFD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD32X16_H1_L0_S2 : AE_MULAAFD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD32X16_H2_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaafd32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAFD32X16_H2_L3 : AE_MULAAFD32X16_H2_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaafd32x16_h2_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAFD32X16_H2_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD32X16_H2_L3_S2 : AE_MULAAFD32X16_H2_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd32x16_h2_l3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAAFD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAAFD32X16_H3_L2 : AE_MULAAFD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaafd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAAFD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAAFD32X16_H3_L2_S2 : AE_MULAAFD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaafd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAC24_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulac24 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{53} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAC24 : AE_MULAC24_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulac24 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAC32X16_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulac32x16.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; +let Constraints = "$opnd_ae_sem_mul_x4_q0 = $opnd_ae_sem_mul_x4_q0_out,@earlyclobber $opnd_ae_sem_mul_x4_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULAC32X16_H : AE_MULAC32X16_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0_out, (int_xtensa_ae_mulac32x16_h AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULAC32X16_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulac32x16.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; +let Constraints = "$opnd_ae_sem_mul_x4_q0 = $opnd_ae_sem_mul_x4_q0_out,@earlyclobber $opnd_ae_sem_mul_x4_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULAC32X16_L : AE_MULAC32X16_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0_out, (int_xtensa_ae_mulac32x16_l AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULAF16SS_00_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF16SS_00 : AE_MULAF16SS_00_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf16ss_00 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF16SS_00_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF16SS_00_S2 : AE_MULAF16SS_00_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf16ss_00_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF16SS_10_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_10 : AE_MULAF16SS_10_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_10 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16SS_11_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_11 : AE_MULAF16SS_11_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_11 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16SS_20_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_20 : AE_MULAF16SS_20_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_20 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16SS_21_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_21 : AE_MULAF16SS_21_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_21 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16SS_22_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_22 : AE_MULAF16SS_22_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_22 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16SS_30_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_30 : AE_MULAF16SS_30_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_30 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16SS_31_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_31 : AE_MULAF16SS_31_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_31 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16SS_32_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{36} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_32 : AE_MULAF16SS_32_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_32 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16SS_33_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulaf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{36} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAF16SS_33 : AE_MULAF16SS_33_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulaf16ss_33 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAF16X4SS_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q1_out, AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q1, AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d0), "ae_mulaf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q1; +bits<4> ae_mul_q0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d0; +let Constraints = "$ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out, $ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +} + + + +def AE_MULAF16X4SS : AE_MULAF16X4SS_AE_FORMAT2<[]>; + +class AE_MULAF32R_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32R_HH : AE_MULAF32R_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32r_hh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32R_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32R_LH : AE_MULAF32R_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32r_lh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32R_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32R_LL : AE_MULAF32R_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32r_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32R_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32R_LL_S2 : AE_MULAF32R_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32r_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32S_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32S_HH : AE_MULAF32S_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32s_hh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32S_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32S_LH : AE_MULAF32S_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32s_lh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32S_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32S_LL : AE_MULAF32S_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32s_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32S_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32S_LL_S2 : AE_MULAF32S_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32s_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32X16_H0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32X16_H0 : AE_MULAF32X16_H0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32x16_h0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32X16_H0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32X16_H0_S2 : AE_MULAF32X16_H0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32x16_h0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32X16_H1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32X16_H1 : AE_MULAF32X16_H1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32x16_h1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32X16_H1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32X16_H1_S2 : AE_MULAF32X16_H1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32x16_h1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32X16_H2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32X16_H2 : AE_MULAF32X16_H2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32x16_h2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32X16_H2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32X16_H2_S2 : AE_MULAF32X16_H2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32x16_h2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32X16_H3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32X16_H3 : AE_MULAF32X16_H3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32x16_h3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32X16_H3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32X16_H3_S2 : AE_MULAF32X16_H3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32x16_h3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32X16_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32X16_L0 : AE_MULAF32X16_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32x16_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32X16_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32X16_L0_S2 : AE_MULAF32X16_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32x16_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32X16_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32X16_L1 : AE_MULAF32X16_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32x16_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32X16_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32X16_L1_S2 : AE_MULAF32X16_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32x16_l1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32X16_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32X16_L2 : AE_MULAF32X16_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32x16_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32X16_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32X16_L2_S2 : AE_MULAF32X16_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32x16_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF32X16_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF32X16_L3 : AE_MULAF32X16_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf32x16_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF32X16_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF32X16_L3_S2 : AE_MULAF32X16_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf32x16_l3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF48Q32SP16S_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF48Q32SP16S_L : AE_MULAF48Q32SP16S_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf48q32sp16s_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF48Q32SP16S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF48Q32SP16S_L_S2 : AE_MULAF48Q32SP16S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf48q32sp16s_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAF48Q32SP16U_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulaf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAF48Q32SP16U_L : AE_MULAF48Q32SP16U_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulaf48q32sp16u_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAF48Q32SP16U_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAF48Q32SP16U_L_S2 : AE_MULAF48Q32SP16U_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaf48q32sp16u_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAFC24RA_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulafc24ra $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; +let Constraints = "$opnd_ae_sem_mul_x4_q0 = $opnd_ae_sem_mul_x4_q0_out,@earlyclobber $opnd_ae_sem_mul_x4_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULAFC24RA : AE_MULAFC24RA_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0_out, (int_xtensa_ae_mulafc24ra AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULAFC32X16RAS_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulafc32x16ras.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; +let Constraints = "$opnd_ae_sem_mul_x4_q0 = $opnd_ae_sem_mul_x4_q0_out,@earlyclobber $opnd_ae_sem_mul_x4_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULAFC32X16RAS_H : AE_MULAFC32X16RAS_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0_out, (int_xtensa_ae_mulafc32x16ras_h AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULAFC32X16RAS_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulafc32x16ras.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; +let Constraints = "$opnd_ae_sem_mul_x4_q0 = $opnd_ae_sem_mul_x4_q0_out,@earlyclobber $opnd_ae_sem_mul_x4_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULAFC32X16RAS_L : AE_MULAFC32X16RAS_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0_out, (int_xtensa_ae_mulafc32x16ras_l AE_DR:$opnd_ae_sem_mul_x4_q0, AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULAFD24X2_FIR_H_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out, AE_DR:$ae_mul_q1_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulafd24x2.fir.h $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out, $ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode + +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULAFD24X2_FIR_H : AE_MULAFD24X2_FIR_H_AE_FORMAT2<[]>; + +class AE_MULAFD24X2_FIR_L_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out, AE_DR:$ae_mul_q1_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulafd24x2.fir.l $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out, $ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULAFD24X2_FIR_L : AE_MULAFD24X2_FIR_L_AE_FORMAT2<[]>; + +class AE_MULAFD32X16X2_FIR_HH_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out, AE_DR:$ae_mul_q1_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulafd32x16x2.fir.hh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out, $ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULAFD32X16X2_FIR_HH : AE_MULAFD32X16X2_FIR_HH_AE_FORMAT2<[]>; + +class AE_MULAFD32X16X2_FIR_HL_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out, AE_DR:$ae_mul_q1_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulafd32x16x2.fir.hl $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out, $ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULAFD32X16X2_FIR_HL : AE_MULAFD32X16X2_FIR_HL_AE_FORMAT2<[]>; + +class AE_MULAFD32X16X2_FIR_LH_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out, AE_DR:$ae_mul_q1_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulafd32x16x2.fir.lh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out, $ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULAFD32X16X2_FIR_LH : AE_MULAFD32X16X2_FIR_LH_AE_FORMAT2<[]>; + +class AE_MULAFD32X16X2_FIR_LL_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out, AE_DR:$ae_mul_q1_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulafd32x16x2.fir.ll $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out, $ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULAFD32X16X2_FIR_LL : AE_MULAFD32X16X2_FIR_LL_AE_FORMAT2<[]>; + +class AE_MULAFP24X2R_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulafp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAFP24X2R : AE_MULAFP24X2R_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulafp24x2r AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAFP24X2R_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulafp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAFP24X2R_S2 : AE_MULAFP24X2R_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulafp24x2r_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAFP24X2RA_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulafp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAFP24X2RA : AE_MULAFP24X2RA_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulafp24x2ra AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAFP24X2RA_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulafp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAFP24X2RA_S2 : AE_MULAFP24X2RA_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulafp24x2ra_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAFP32X16X2RAS_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulafp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAFP32X16X2RAS_H : AE_MULAFP32X16X2RAS_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulafp32x16x2ras_h AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAFP32X16X2RAS_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulafp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAFP32X16X2RAS_H_S2 : AE_MULAFP32X16X2RAS_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulafp32x16x2ras_h_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAFP32X16X2RAS_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulafp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAFP32X16X2RAS_L : AE_MULAFP32X16X2RAS_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulafp32x16x2ras_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAFP32X16X2RAS_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulafp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAFP32X16X2RAS_L_S2 : AE_MULAFP32X16X2RAS_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulafp32x16x2ras_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAFP32X16X2RS_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulafp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAFP32X16X2RS_H : AE_MULAFP32X16X2RS_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulafp32x16x2rs_h AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAFP32X16X2RS_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulafp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAFP32X16X2RS_H_S2 : AE_MULAFP32X16X2RS_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulafp32x16x2rs_h_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAFP32X16X2RS_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulafp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAFP32X16X2RS_L : AE_MULAFP32X16X2RS_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulafp32x16x2rs_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAFP32X16X2RS_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulafp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAFP32X16X2RS_L_S2 : AE_MULAFP32X16X2RS_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulafp32x16x2rs_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAFP32X2RAS_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulafp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAFP32X2RAS : AE_MULAFP32X2RAS_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulafp32x2ras AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAFP32X2RS_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulafp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAFP32X2RS : AE_MULAFP32X2RS_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulafp32x2rs AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAFQ32SP24S_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulafq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAFQ32SP24S_H_S2 : AE_MULAFQ32SP24S_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulafq32sp24s_h_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAFQ32SP24S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulafq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAFQ32SP24S_L_S2 : AE_MULAFQ32SP24S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulafq32sp24s_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAP24X2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulap24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{54} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULAP24X2 : AE_MULAP24X2_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulap24x2 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULAP24X2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulap24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAP24X2_S2 : AE_MULAP24X2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulap24x2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAP32X16X2_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulap32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAP32X16X2_H : AE_MULAP32X16X2_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulap32x16x2_h AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAP32X16X2_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulap32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAP32X16X2_L : AE_MULAP32X16X2_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulap32x16x2_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAP32X2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulap32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAP32X2 : AE_MULAP32X2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulap32x2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAQ32SP16S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAQ32SP16S_L_S2 : AE_MULAQ32SP16S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaq32sp16s_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAQ32SP16U_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulaq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAQ32SP16U_L_S2 : AE_MULAQ32SP16U_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulaq32sp16u_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULARFQ32SP24S_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mularfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULARFQ32SP24S_H_S2 : AE_MULARFQ32SP24S_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mularfq32sp24s_h_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULARFQ32SP24S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mularfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULARFQ32SP24S_L_S2 : AE_MULARFQ32SP24S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mularfq32sp24s_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAS32F48P16S_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulas32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAS32F48P16S_HH : AE_MULAS32F48P16S_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulas32f48p16s_hh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAS32F48P16S_HH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulas32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAS32F48P16S_HH_S2 : AE_MULAS32F48P16S_HH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulas32f48p16s_hh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAS32F48P16S_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulas32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAS32F48P16S_LH : AE_MULAS32F48P16S_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulas32f48p16s_lh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAS32F48P16S_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulas32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAS32F48P16S_LH_S2 : AE_MULAS32F48P16S_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulas32f48p16s_lh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULAS32F48P16S_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulas32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULAS32F48P16S_LL : AE_MULAS32F48P16S_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulas32f48p16s_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULAS32F48P16S_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulas32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULAS32F48P16S_LL_S2 : AE_MULAS32F48P16S_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulas32f48p16s_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULASD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulasd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULASD24_HH_LL : AE_MULASD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulasd24_hh_ll AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULASD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulasd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULASD24_HH_LL_S2 : AE_MULASD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulasd24_hh_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULASD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulasd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULASD24_HL_LH : AE_MULASD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulasd24_hl_lh AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULASD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulasd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULASD24_HL_LH_S2 : AE_MULASD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulasd24_hl_lh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULASD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulasd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULASD32X16_H1_L0 : AE_MULASD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulasd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULASD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulasd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULASD32X16_H1_L0_S2 : AE_MULASD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulasd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULASD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulasd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULASD32X16_H3_L2 : AE_MULASD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulasd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULASD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulasd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULASD32X16_H3_L2_S2 : AE_MULASD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulasd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULASFD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulasfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{50} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULASFD24_HH_LL : AE_MULASFD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulasfd24_hh_ll AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULASFD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulasfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULASFD24_HH_LL_S2 : AE_MULASFD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulasfd24_hh_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULASFD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulasfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULASFD24_HL_LH : AE_MULASFD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulasfd24_hl_lh AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULASFD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulasfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULASFD24_HL_LH_S2 : AE_MULASFD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulasfd24_hl_lh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULASFD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulasfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULASFD32X16_H1_L0 : AE_MULASFD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulasfd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULASFD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulasfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULASFD32X16_H1_L0_S2 : AE_MULASFD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulasfd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULASFD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulasfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULASFD32X16_H3_L2 : AE_MULASFD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulasfd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULASFD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulasfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULASFD32X16_H3_L2_S2 : AE_MULASFD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulasfd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULC24_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulc24 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULC24 : AE_MULC24_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulc24 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULC32X16_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0), (ins AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulc32x16.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULC32X16_H : AE_MULC32X16_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0, (int_xtensa_ae_mulc32x16_h AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULC32X16_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0), (ins AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulc32x16.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULC32X16_L : AE_MULC32X16_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0, (int_xtensa_ae_mulc32x16_l AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULF16SS_00_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF16SS_00 : AE_MULF16SS_00_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf16ss_00 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF16SS_00_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF16SS_00_S2 : AE_MULF16SS_00_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf16ss_00_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF16SS_10_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_10 : AE_MULF16SS_10_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_10 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16SS_11_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_11 : AE_MULF16SS_11_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_11 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16SS_20_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_20 : AE_MULF16SS_20_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_20 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16SS_21_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_21 : AE_MULF16SS_21_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_21 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16SS_22_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_22 : AE_MULF16SS_22_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_22 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16SS_30_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_30 : AE_MULF16SS_30_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_30 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16SS_31_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_31 : AE_MULF16SS_31_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_31 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16SS_32_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_32 : AE_MULF16SS_32_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_32 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16SS_33_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULF16SS_33 : AE_MULF16SS_33_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulf16ss_33 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULF16X4SS_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q1, AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d0), "ae_mulf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q1; +bits<4> ae_mul_q0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +} + + + +def AE_MULF16X4SS : AE_MULF16X4SS_AE_FORMAT2<[]>; + +class AE_MULF32R_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32R_HH : AE_MULF32R_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32r_hh AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32R_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32R_LH : AE_MULF32R_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32r_lh AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32R_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32R_LL : AE_MULF32R_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32r_ll AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32R_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32R_LL_S2 : AE_MULF32R_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32r_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32S_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32S_HH : AE_MULF32S_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32s_hh AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32S_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32S_LH : AE_MULF32S_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32s_lh AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32S_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32S_LL : AE_MULF32S_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32s_ll AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32S_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32S_LL_S2 : AE_MULF32S_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32s_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32X16_H0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32X16_H0 : AE_MULF32X16_H0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32x16_h0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32X16_H0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32X16_H0_S2 : AE_MULF32X16_H0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32x16_h0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32X16_H1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32X16_H1 : AE_MULF32X16_H1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32x16_h1 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32X16_H1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32X16_H1_S2 : AE_MULF32X16_H1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32x16_h1_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32X16_H2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32X16_H2 : AE_MULF32X16_H2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32x16_h2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32X16_H2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32X16_H2_S2 : AE_MULF32X16_H2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32x16_h2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32X16_H3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32X16_H3 : AE_MULF32X16_H3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32x16_h3 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32X16_H3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32X16_H3_S2 : AE_MULF32X16_H3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32x16_h3_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32X16_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32X16_L0 : AE_MULF32X16_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32x16_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32X16_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32X16_L0_S2 : AE_MULF32X16_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32x16_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32X16_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32X16_L1 : AE_MULF32X16_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32x16_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32X16_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32X16_L1_S2 : AE_MULF32X16_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32x16_l1_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32X16_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32X16_L2 : AE_MULF32X16_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32x16_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32X16_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32X16_L2_S2 : AE_MULF32X16_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32x16_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF32X16_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF32X16_L3 : AE_MULF32X16_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf32x16_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF32X16_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF32X16_L3_S2 : AE_MULF32X16_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf32x16_l3_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF48Q32SP16S_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF48Q32SP16S_L : AE_MULF48Q32SP16S_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf48q32sp16s_l AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF48Q32SP16S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF48Q32SP16S_L_S2 : AE_MULF48Q32SP16S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf48q32sp16s_l_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULF48Q32SP16U_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULF48Q32SP16U_L : AE_MULF48Q32SP16U_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulf48q32sp16u_l AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULF48Q32SP16U_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULF48Q32SP16U_L_S2 : AE_MULF48Q32SP16U_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulf48q32sp16u_l_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULFC24RA_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0), (ins AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulfc24ra $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULFC24RA : AE_MULFC24RA_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0, (int_xtensa_ae_mulfc24ra AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULFC32X16RAS_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0), (ins AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulfc32x16ras.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULFC32X16RAS_H : AE_MULFC32X16RAS_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0, (int_xtensa_ae_mulfc32x16ras_h AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULFC32X16RAS_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x4_q0), (ins AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1), "ae_mulfc32x16ras.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x4_q0; +bits<4> opnd_ae_sem_mul_x4_d0; +bits<4> opnd_ae_sem_mul_x4_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x4_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x4_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x4_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x4_q0{3}; +let Inst{24} = opnd_ae_sem_mul_x4_d0{0}; +let Inst{25} = opnd_ae_sem_mul_x4_d0{1}; +let Inst{26} = opnd_ae_sem_mul_x4_d0{2}; +let Inst{27} = opnd_ae_sem_mul_x4_d0{3}; +let Inst{20} = opnd_ae_sem_mul_x4_d1{0}; +let Inst{21} = opnd_ae_sem_mul_x4_d1{1}; +let Inst{22} = opnd_ae_sem_mul_x4_d1{2}; +let Inst{23} = opnd_ae_sem_mul_x4_d1{3}; +} + + + +def AE_MULFC32X16RAS_L : AE_MULFC32X16RAS_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x4_q0, (int_xtensa_ae_mulfc32x16ras_l AE_DR:$opnd_ae_sem_mul_x4_d0, AE_DR:$opnd_ae_sem_mul_x4_d1))]>; + +class AE_MULFD24X2_FIR_H_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulfd24x2.fir.h $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULFD24X2_FIR_H : AE_MULFD24X2_FIR_H_AE_FORMAT2<[]>; + +class AE_MULFD24X2_FIR_L_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulfd24x2.fir.l $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULFD24X2_FIR_L : AE_MULFD24X2_FIR_L_AE_FORMAT2<[]>; + +class AE_MULFD32X16X2_FIR_HH_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulfd32x16x2.fir.hh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULFD32X16X2_FIR_HH : AE_MULFD32X16X2_FIR_HH_AE_FORMAT2<[]>; + +class AE_MULFD32X16X2_FIR_HL_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulfd32x16x2.fir.hl $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULFD32X16X2_FIR_HL : AE_MULFD32X16X2_FIR_HL_AE_FORMAT2<[]>; + +class AE_MULFD32X16X2_FIR_LH_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulfd32x16x2.fir.lh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULFD32X16X2_FIR_LH : AE_MULFD32X16X2_FIR_LH_AE_FORMAT2<[]>; + +class AE_MULFD32X16X2_FIR_LL_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0, AE_DR:$ae_mul_q1), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d2), "ae_mulfd32x16x2.fir.ll $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_q1; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d2; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{36} = ae_mul_d2{0}; +let Inst{37} = ae_mul_d2{1}; +let Inst{38} = ae_mul_d2{2}; +let Inst{39} = ae_mul_d2{3}; +} + + + +def AE_MULFD32X16X2_FIR_LL : AE_MULFD32X16X2_FIR_LL_AE_FORMAT2<[]>; + +class AE_MULFP16X4RAS_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulfp16x4ras $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{21} = 1; +let Inst{23} = 1; +let Inst{36} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULFP16X4RAS : AE_MULFP16X4RAS_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulfp16x4ras AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULFP16X4S_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulfp16x4s $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{21} = 1; +let Inst{23} = 1; +let Inst{36} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULFP16X4S : AE_MULFP16X4S_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulfp16x4s AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULFP24X2R_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulfp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULFP24X2R : AE_MULFP24X2R_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulfp24x2r AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULFP24X2R_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulfp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULFP24X2R_S2 : AE_MULFP24X2R_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulfp24x2r_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULFP24X2RA_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulfp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULFP24X2RA : AE_MULFP24X2RA_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulfp24x2ra AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULFP24X2RA_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulfp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULFP24X2RA_S2 : AE_MULFP24X2RA_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulfp24x2ra_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULFP32X16X2RAS_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulfp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULFP32X16X2RAS_H : AE_MULFP32X16X2RAS_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulfp32x16x2ras_h AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULFP32X16X2RAS_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulfp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULFP32X16X2RAS_H_S2 : AE_MULFP32X16X2RAS_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulfp32x16x2ras_h_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULFP32X16X2RAS_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulfp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULFP32X16X2RAS_L : AE_MULFP32X16X2RAS_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulfp32x16x2ras_l AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULFP32X16X2RAS_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulfp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULFP32X16X2RAS_L_S2 : AE_MULFP32X16X2RAS_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulfp32x16x2ras_l_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULFP32X16X2RS_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulfp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULFP32X16X2RS_H : AE_MULFP32X16X2RS_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulfp32x16x2rs_h AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULFP32X16X2RS_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulfp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULFP32X16X2RS_H_S2 : AE_MULFP32X16X2RS_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulfp32x16x2rs_h_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULFP32X16X2RS_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulfp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULFP32X16X2RS_L : AE_MULFP32X16X2RS_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulfp32x16x2rs_l AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULFP32X16X2RS_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulfp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULFP32X16X2RS_L_S2 : AE_MULFP32X16X2RS_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulfp32x16x2rs_l_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULFP32X2RAS_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulfp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULFP32X2RAS : AE_MULFP32X2RAS_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulfp32x2ras AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULFP32X2RS_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulfp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULFP32X2RS : AE_MULFP32X2RS_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulfp32x2rs AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULFQ32SP24S_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULFQ32SP24S_H_S2 : AE_MULFQ32SP24S_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulfq32sp24s_h_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULFQ32SP24S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULFQ32SP24S_L_S2 : AE_MULFQ32SP24S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulfq32sp24s_l_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULP24X2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulp24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULP24X2 : AE_MULP24X2_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulp24x2 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULP24X2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulp24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULP24X2_S2 : AE_MULP24X2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulp24x2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULP32X16X2_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulp32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULP32X16X2_H : AE_MULP32X16X2_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulp32x16x2_h AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULP32X16X2_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulp32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULP32X16X2_L : AE_MULP32X16X2_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulp32x16x2_l AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULP32X2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulp32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULP32X2 : AE_MULP32X2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulp32x2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULQ32SP16S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULQ32SP16S_L_S2 : AE_MULQ32SP16S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulq32sp16s_l_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULQ32SP16U_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULQ32SP16U_L_S2 : AE_MULQ32SP16U_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulq32sp16u_l_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULRFQ32SP24S_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulrfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULRFQ32SP24S_H_S2 : AE_MULRFQ32SP24S_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulrfq32sp24s_h_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULRFQ32SP24S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulrfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULRFQ32SP24S_L_S2 : AE_MULRFQ32SP24S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulrfq32sp24s_l_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS16X4_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q1_out, AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q1, AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d0), "ae_muls16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q1; +bits<4> ae_mul_q0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d0; +let Constraints = "$ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out, $ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{37} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +} + + + +def AE_MULS16X4 : AE_MULS16X4_AE_FORMAT2<[]>; + +class AE_MULS32_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32_HH : AE_MULS32_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32_hh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32_LH : AE_MULS32_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32_lh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32_LL : AE_MULS32_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32F48P16S_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32F48P16S_HH : AE_MULS32F48P16S_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_muls32f48p16s_hh AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32F48P16S_HH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32F48P16S_HH_S2 : AE_MULS32F48P16S_HH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_muls32f48p16s_hh_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32F48P16S_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32F48P16S_LH : AE_MULS32F48P16S_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_muls32f48p16s_lh AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32F48P16S_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32F48P16S_LH_S2 : AE_MULS32F48P16S_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_muls32f48p16s_lh_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32F48P16S_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32F48P16S_LL : AE_MULS32F48P16S_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_muls32f48p16s_ll AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32F48P16S_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32F48P16S_LL_S2 : AE_MULS32F48P16S_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_muls32f48p16s_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32U_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32U_LL : AE_MULS32U_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32u_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_H0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32X16_H0 : AE_MULS32X16_H0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32x16_h0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_H0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32X16_H0_S2 : AE_MULS32X16_H0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_muls32x16_h0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32X16_H1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32X16_H1 : AE_MULS32X16_H1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32x16_h1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_H1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32X16_H1_S2 : AE_MULS32X16_H1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_muls32x16_h1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32X16_H2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32X16_H2 : AE_MULS32X16_H2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32x16_h2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_H2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32X16_H2_S2 : AE_MULS32X16_H2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_muls32x16_h2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32X16_H3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32X16_H3 : AE_MULS32X16_H3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32x16_h3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_H3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32X16_H3_S2 : AE_MULS32X16_H3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_muls32x16_h3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32X16_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32X16_L0 : AE_MULS32X16_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32x16_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32X16_L0_S2 : AE_MULS32X16_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_muls32x16_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32X16_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32X16_L1 : AE_MULS32X16_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32x16_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32X16_L1_S2 : AE_MULS32X16_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_muls32x16_l1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32X16_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32X16_L2 : AE_MULS32X16_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32x16_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32X16_L2_S2 : AE_MULS32X16_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_muls32x16_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULS32X16_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_muls32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULS32X16_L3 : AE_MULS32X16_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_muls32x16_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULS32X16_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_muls32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULS32X16_L3_S2 : AE_MULS32X16_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_muls32x16_l3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSAD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSAD24_HH_LL : AE_MULSAD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsad24_hh_ll AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSAD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSAD24_HH_LL_S2 : AE_MULSAD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsad24_hh_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSAD32X16_H1_L0_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsad32x16.h1.l0 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSAD32X16_H1_L0 : AE_MULSAD32X16_H1_L0_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsad32x16_h1_l0 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSAD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSAD32X16_H1_L0_S2 : AE_MULSAD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsad32x16_h1_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSAD32X16_H3_L2_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsad32x16.h3.l2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{39} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSAD32X16_H3_L2 : AE_MULSAD32X16_H3_L2_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsad32x16_h3_l2 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSAD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSAD32X16_H3_L2_S2 : AE_MULSAD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsad32x16_h3_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSAFD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSAFD24_HH_LL : AE_MULSAFD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsafd24_hh_ll AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSAFD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSAFD24_HH_LL_S2 : AE_MULSAFD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsafd24_hh_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSAFD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSAFD32X16_H1_L0 : AE_MULSAFD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsafd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSAFD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSAFD32X16_H1_L0_S2 : AE_MULSAFD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsafd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSAFD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSAFD32X16_H3_L2 : AE_MULSAFD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsafd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSAFD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSAFD32X16_H3_L2_S2 : AE_MULSAFD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsafd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF16SS_00_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF16SS_00 : AE_MULSF16SS_00_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf16ss_00 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF16SS_00_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF16SS_00_S2 : AE_MULSF16SS_00_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf16ss_00_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF16SS_10_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_10 : AE_MULSF16SS_10_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_10 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16SS_11_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +let Inst{39} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_11 : AE_MULSF16SS_11_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_11 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16SS_20_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_20 : AE_MULSF16SS_20_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_20 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16SS_21_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{39} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_21 : AE_MULSF16SS_21_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_21 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16SS_22_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{36} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_22 : AE_MULSF16SS_22_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_22 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16SS_30_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{36} = 1; +let Inst{39} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_30 : AE_MULSF16SS_30_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_30 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16SS_31_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{21} = 1; +let Inst{36} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_31 : AE_MULSF16SS_31_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_31 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16SS_32_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{21} = 1; +let Inst{36} = 1; +let Inst{39} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_32 : AE_MULSF16SS_32_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_32 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16SS_33_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{36} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSF16SS_33 : AE_MULSF16SS_33_AE_FORMAT2<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsf16ss_33 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSF16X4SS_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q1_out, AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q1, AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d1, AE_DR:$ae_mul_d0), "ae_mulsf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q1; +bits<4> ae_mul_q0; +bits<4> ae_mul_d1; +bits<4> ae_mul_d0; +let Constraints = "$ae_mul_q1 = $ae_mul_q1_out,@earlyclobber $ae_mul_q1_out, $ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{37} = 1; +let Inst{39} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{20} = ae_mul_q1{0}; +let Inst{21} = ae_mul_q1{1}; +let Inst{22} = ae_mul_q1{2}; +let Inst{23} = ae_mul_q1{3}; +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +} + + + +def AE_MULSF16X4SS : AE_MULSF16X4SS_AE_FORMAT2<[]>; + +class AE_MULSF32R_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32R_HH : AE_MULSF32R_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32r_hh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32R_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32R_LH : AE_MULSF32R_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32r_lh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32R_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32R_LL : AE_MULSF32R_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32r_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32R_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32R_LL_S2 : AE_MULSF32R_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32r_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF32S_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32S_HH : AE_MULSF32S_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32s_hh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32S_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32S_LH : AE_MULSF32S_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32s_lh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32S_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32S_LL : AE_MULSF32S_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32s_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_H0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32X16_H0 : AE_MULSF32X16_H0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32x16_h0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_H0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32X16_H0_S2 : AE_MULSF32X16_H0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32x16_h0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF32X16_H1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32X16_H1 : AE_MULSF32X16_H1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32x16_h1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_H1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32X16_H1_S2 : AE_MULSF32X16_H1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32x16_h1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF32X16_H2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32X16_H2 : AE_MULSF32X16_H2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32x16_h2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_H2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32X16_H2_S2 : AE_MULSF32X16_H2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32x16_h2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF32X16_H3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32X16_H3 : AE_MULSF32X16_H3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32x16_h3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_H3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32X16_H3_S2 : AE_MULSF32X16_H3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32x16_h3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF32X16_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32X16_L0 : AE_MULSF32X16_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32x16_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32X16_L0_S2 : AE_MULSF32X16_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32x16_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF32X16_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32X16_L1 : AE_MULSF32X16_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32x16_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32X16_L1_S2 : AE_MULSF32X16_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32x16_l1_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF32X16_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32X16_L2 : AE_MULSF32X16_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32x16_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32X16_L2_S2 : AE_MULSF32X16_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32x16_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF32X16_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF32X16_L3 : AE_MULSF32X16_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf32x16_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF32X16_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF32X16_L3_S2 : AE_MULSF32X16_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf32x16_l3_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF48Q32SP16S_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF48Q32SP16S_L : AE_MULSF48Q32SP16S_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf48q32sp16s_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF48Q32SP16S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF48Q32SP16S_L_S2 : AE_MULSF48Q32SP16S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf48q32sp16s_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSF48Q32SP16U_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSF48Q32SP16U_L : AE_MULSF48Q32SP16U_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsf48q32sp16u_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSF48Q32SP16U_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSF48Q32SP16U_L_S2 : AE_MULSF48Q32SP16U_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsf48q32sp16u_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSFP24X2R_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsfp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSFP24X2R : AE_MULSFP24X2R_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsfp24x2r AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSFP24X2R_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsfp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSFP24X2R_S2 : AE_MULSFP24X2R_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsfp24x2r_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSFP24X2RA_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsfp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSFP24X2RA : AE_MULSFP24X2RA_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsfp24x2ra AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSFP24X2RA_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsfp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSFP24X2RA_S2 : AE_MULSFP24X2RA_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsfp24x2ra_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSFP32X16X2RAS_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsfp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSFP32X16X2RAS_H : AE_MULSFP32X16X2RAS_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsfp32x16x2ras_h AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSFP32X16X2RAS_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsfp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSFP32X16X2RAS_H_S2 : AE_MULSFP32X16X2RAS_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsfp32x16x2ras_h_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSFP32X16X2RAS_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsfp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSFP32X16X2RAS_L : AE_MULSFP32X16X2RAS_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsfp32x16x2ras_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSFP32X16X2RAS_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsfp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSFP32X16X2RAS_L_S2 : AE_MULSFP32X16X2RAS_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsfp32x16x2ras_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSFP32X16X2RS_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsfp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSFP32X16X2RS_H : AE_MULSFP32X16X2RS_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsfp32x16x2rs_h AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSFP32X16X2RS_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsfp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSFP32X16X2RS_H_S2 : AE_MULSFP32X16X2RS_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsfp32x16x2rs_h_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSFP32X16X2RS_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsfp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSFP32X16X2RS_L : AE_MULSFP32X16X2RS_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsfp32x16x2rs_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSFP32X16X2RS_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsfp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSFP32X16X2RS_L_S2 : AE_MULSFP32X16X2RS_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsfp32x16x2rs_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSFP32X2RAS_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsfp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSFP32X2RAS : AE_MULSFP32X2RAS_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsfp32x2ras AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSFP32X2RS_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsfp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSFP32X2RS : AE_MULSFP32X2RS_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsfp32x2rs AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSFQ32SP24S_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSFQ32SP24S_H_S2 : AE_MULSFQ32SP24S_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsfq32sp24s_h_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSFQ32SP24S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSFQ32SP24S_L_S2 : AE_MULSFQ32SP24S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsfq32sp24s_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSP24X2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulsp24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{53} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSP24X2 : AE_MULSP24X2_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulsp24x2 AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSP24X2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsp24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSP24X2_S2 : AE_MULSP24X2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsp24x2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSP32X16X2_H_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsp32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSP32X16X2_H : AE_MULSP32X16X2_H_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsp32x16x2_h AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSP32X16X2_L_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsp32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSP32X16X2_L : AE_MULSP32X16X2_L_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsp32x16x2_l AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSP32X2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulsp32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSP32X2 : AE_MULSP32X2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulsp32x2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSQ32SP16S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSQ32SP16S_L_S2 : AE_MULSQ32SP16S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsq32sp16s_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSQ32SP16U_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSQ32SP16U_L_S2 : AE_MULSQ32SP16U_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsq32sp16u_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSRFQ32SP24S_H_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsrfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSRFQ32SP24S_H_S2 : AE_MULSRFQ32SP24S_H_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsrfq32sp24s_h_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSRFQ32SP24S_L_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulsrfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSRFQ32SP24S_L_S2 : AE_MULSRFQ32SP24S_L_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulsrfq32sp24s_l_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSS32F48P16S_HH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulss32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSS32F48P16S_HH : AE_MULSS32F48P16S_HH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulss32f48p16s_hh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSS32F48P16S_HH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulss32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSS32F48P16S_HH_S2 : AE_MULSS32F48P16S_HH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulss32f48p16s_hh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSS32F48P16S_LH_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulss32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSS32F48P16S_LH : AE_MULSS32F48P16S_LH_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulss32f48p16s_lh AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSS32F48P16S_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulss32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSS32F48P16S_LH_S2 : AE_MULSS32F48P16S_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulss32f48p16s_lh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSS32F48P16S_LL_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulss32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSS32F48P16S_LL : AE_MULSS32F48P16S_LL_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulss32f48p16s_ll AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSS32F48P16S_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulss32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSS32F48P16S_LL_S2 : AE_MULSS32F48P16S_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulss32f48p16s_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulssd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSSD24_HH_LL : AE_MULSSD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulssd24_hh_ll AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSSD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSD24_HH_LL_S2 : AE_MULSSD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssd24_hh_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulssd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{50} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSSD24_HL_LH : AE_MULSSD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulssd24_hl_lh AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSSD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSD24_HL_LH_S2 : AE_MULSSD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssd24_hl_lh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulssd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSSD32X16_H1_L0 : AE_MULSSD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulssd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSSD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSD32X16_H1_L0_S2 : AE_MULSSD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulssd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSSD32X16_H3_L2 : AE_MULSSD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulssd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSSD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSD32X16_H3_L2_S2 : AE_MULSSD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSFD16SS_11_00_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulssfd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSSFD16SS_11_00 : AE_MULSSFD16SS_11_00_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulssfd16ss_11_00 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSSFD16SS_11_00_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssfd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSFD16SS_11_00_S2 : AE_MULSSFD16SS_11_00_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssfd16ss_11_00_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSFD16SS_13_02_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulssfd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSSFD16SS_13_02 : AE_MULSSFD16SS_13_02_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulssfd16ss_13_02 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSSFD16SS_13_02_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssfd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSFD16SS_13_02_S2 : AE_MULSSFD16SS_13_02_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssfd16ss_13_02_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSFD16SS_33_22_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulssfd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSSFD16SS_33_22 : AE_MULSSFD16SS_33_22_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulssfd16ss_33_22 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSSFD16SS_33_22_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssfd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSFD16SS_33_22_S2 : AE_MULSSFD16SS_33_22_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssfd16ss_33_22_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSFD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulssfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSSFD24_HH_LL : AE_MULSSFD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulssfd24_hh_ll AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSSFD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSFD24_HH_LL_S2 : AE_MULSSFD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssfd24_hh_ll_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSFD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0_out), (ins AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulssfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; +let Constraints = "$ae_mul_q0 = $ae_mul_q0_out,@earlyclobber $ae_mul_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULSSFD24_HL_LH : AE_MULSSFD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0_out, (int_xtensa_ae_mulssfd24_hl_lh AE_DR:$ae_mul_q0, AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULSSFD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSFD24_HL_LH_S2 : AE_MULSSFD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssfd24_hl_lh_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSFD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulssfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSSFD32X16_H1_L0 : AE_MULSSFD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulssfd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSSFD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSFD32X16_H1_L0_S2 : AE_MULSSFD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssfd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULSSFD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulssfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; +let Constraints = "$opnd_ae_sem_mul_x2_S1_q0 = $opnd_ae_sem_mul_x2_S1_q0_out,@earlyclobber $opnd_ae_sem_mul_x2_S1_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULSSFD32X16_H3_L2 : AE_MULSSFD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0_out, (int_xtensa_ae_mulssfd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_q0, AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULSSFD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0_out), (ins AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulssfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; +let Constraints = "$ae_mul_S2_q0 = $ae_mul_S2_q0_out,@earlyclobber $ae_mul_S2_q0_out"; + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULSSFD32X16_H3_L2_S2 : AE_MULSSFD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0_out, (int_xtensa_ae_mulssfd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_q0, AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzaad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZAAD24_HH_LL : AE_MULZAAD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzaad24_hh_ll AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZAAD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAD24_HH_LL_S2 : AE_MULZAAD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaad24_hh_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzaad24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZAAD24_HL_LH : AE_MULZAAD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzaad24_hl_lh AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZAAD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaad24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAD24_HL_LH_S2 : AE_MULZAAD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaad24_hl_lh_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAD32X16_H0_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaad32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAD32X16_H0_L1 : AE_MULZAAD32X16_H0_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaad32x16_h0_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAD32X16_H0_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaad32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAD32X16_H0_L1_S2 : AE_MULZAAD32X16_H0_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaad32x16_h0_l1_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaad32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAD32X16_H1_L0 : AE_MULZAAD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaad32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAD32X16_H1_L0_S2 : AE_MULZAAD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaad32x16_h1_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAD32X16_H2_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaad32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAD32X16_H2_L3 : AE_MULZAAD32X16_H2_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaad32x16_h2_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAD32X16_H2_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaad32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAD32X16_H2_L3_S2 : AE_MULZAAD32X16_H2_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaad32x16_h2_l3_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaad32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAD32X16_H3_L2 : AE_MULZAAD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaad32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAD32X16_H3_L2_S2 : AE_MULZAAD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaad32x16_h3_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD16SS_11_00_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaafd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAFD16SS_11_00 : AE_MULZAAFD16SS_11_00_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaafd16ss_11_00 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAFD16SS_11_00_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD16SS_11_00_S2 : AE_MULZAAFD16SS_11_00_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd16ss_11_00_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD16SS_13_02_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaafd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAFD16SS_13_02 : AE_MULZAAFD16SS_13_02_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaafd16ss_13_02 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAFD16SS_13_02_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD16SS_13_02_S2 : AE_MULZAAFD16SS_13_02_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd16ss_13_02_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD16SS_33_22_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaafd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAFD16SS_33_22 : AE_MULZAAFD16SS_33_22_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaafd16ss_33_22 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAFD16SS_33_22_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD16SS_33_22_S2 : AE_MULZAAFD16SS_33_22_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd16ss_33_22_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzaafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZAAFD24_HH_LL : AE_MULZAAFD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzaafd24_hh_ll AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZAAFD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD24_HH_LL_S2 : AE_MULZAAFD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd24_hh_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzaafd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{51} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZAAFD24_HL_LH : AE_MULZAAFD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzaafd24_hl_lh AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZAAFD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD24_HL_LH_S2 : AE_MULZAAFD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd24_hl_lh_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD32X16_H0_L1_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaafd32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAFD32X16_H0_L1 : AE_MULZAAFD32X16_H0_L1_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaafd32x16_h0_l1 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAFD32X16_H0_L1_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD32X16_H0_L1_S2 : AE_MULZAAFD32X16_H0_L1_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd32x16_h0_l1_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAFD32X16_H1_L0 : AE_MULZAAFD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaafd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAFD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD32X16_H1_L0_S2 : AE_MULZAAFD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD32X16_H2_L3_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaafd32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAFD32X16_H2_L3 : AE_MULZAAFD32X16_H2_L3_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaafd32x16_h2_l3 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAFD32X16_H2_L3_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD32X16_H2_L3_S2 : AE_MULZAAFD32X16_H2_L3_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd32x16_h2_l3_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZAAFD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzaafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZAAFD32X16_H3_L2 : AE_MULZAAFD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzaafd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZAAFD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzaafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZAAFD32X16_H3_L2_S2 : AE_MULZAAFD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzaafd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZASD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzasd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZASD24_HH_LL : AE_MULZASD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzasd24_hh_ll AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZASD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzasd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZASD24_HH_LL_S2 : AE_MULZASD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzasd24_hh_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZASD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzasd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZASD24_HL_LH : AE_MULZASD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzasd24_hl_lh AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZASD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzasd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZASD24_HL_LH_S2 : AE_MULZASD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzasd24_hl_lh_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZASD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzasd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZASD32X16_H1_L0 : AE_MULZASD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzasd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZASD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzasd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZASD32X16_H1_L0_S2 : AE_MULZASD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzasd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZASD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzasd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{43} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZASD32X16_H3_L2 : AE_MULZASD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzasd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZASD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzasd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZASD32X16_H3_L2_S2 : AE_MULZASD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzasd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZASFD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzasfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZASFD24_HH_LL : AE_MULZASFD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzasfd24_hh_ll AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZASFD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzasfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZASFD24_HH_LL_S2 : AE_MULZASFD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzasfd24_hh_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZASFD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzasfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZASFD24_HL_LH : AE_MULZASFD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzasfd24_hl_lh AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZASFD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzasfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZASFD24_HL_LH_S2 : AE_MULZASFD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzasfd24_hl_lh_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZASFD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzasfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZASFD32X16_H1_L0 : AE_MULZASFD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzasfd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZASFD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzasfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZASFD32X16_H1_L0_S2 : AE_MULZASFD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzasfd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZASFD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzasfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZASFD32X16_H3_L2 : AE_MULZASFD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzasfd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZASFD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzasfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZASFD32X16_H3_L2_S2 : AE_MULZASFD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzasfd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSAD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzsad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{50} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZSAD24_HH_LL : AE_MULZSAD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzsad24_hh_ll AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZSAD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzsad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSAD24_HH_LL_S2 : AE_MULZSAD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzsad24_hh_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSAD32X16_H1_L0_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzsad32x16.h1.l0 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{36} = 1; +let Inst{37} = 1; +let Inst{39} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZSAD32X16_H1_L0 : AE_MULZSAD32X16_H1_L0_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzsad32x16_h1_l0 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZSAD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzsad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSAD32X16_H1_L0_S2 : AE_MULZSAD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzsad32x16_h1_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSAD32X16_H3_L2_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzsad32x16.h3.l2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{23} = 1; +let Inst{36} = 1; +let Inst{37} = 1; +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZSAD32X16_H3_L2 : AE_MULZSAD32X16_H3_L2_AE_FORMAT2<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzsad32x16_h3_l2 AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZSAD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzsad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSAD32X16_H3_L2_S2 : AE_MULZSAD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzsad32x16_h3_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSAFD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzsafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZSAFD24_HH_LL : AE_MULZSAFD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzsafd24_hh_ll AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZSAFD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzsafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSAFD24_HH_LL_S2 : AE_MULZSAFD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzsafd24_hh_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSAFD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzsafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSAFD32X16_H1_L0 : AE_MULZSAFD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzsafd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSAFD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzsafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSAFD32X16_H1_L0_S2 : AE_MULZSAFD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzsafd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSAFD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzsafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSAFD32X16_H3_L2 : AE_MULZSAFD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzsafd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSAFD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzsafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSAFD32X16_H3_L2_S2 : AE_MULZSAFD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzsafd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzssd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZSSD24_HH_LL : AE_MULZSSD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzssd24_hh_ll AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZSSD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSD24_HH_LL_S2 : AE_MULZSSD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssd24_hh_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzssd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZSSD24_HL_LH : AE_MULZSSD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzssd24_hl_lh AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZSSD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSD24_HL_LH_S2 : AE_MULZSSD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssd24_hl_lh_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzssd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSSD32X16_H1_L0 : AE_MULZSSD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzssd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSSD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSD32X16_H1_L0_S2 : AE_MULZSSD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzssd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSSD32X16_H3_L2 : AE_MULZSSD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzssd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSSD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSD32X16_H3_L2_S2 : AE_MULZSSD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSFD16SS_11_00_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzssfd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSSFD16SS_11_00 : AE_MULZSSFD16SS_11_00_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzssfd16ss_11_00 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSSFD16SS_11_00_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssfd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSFD16SS_11_00_S2 : AE_MULZSSFD16SS_11_00_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssfd16ss_11_00_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSFD16SS_13_02_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzssfd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{40} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSSFD16SS_13_02 : AE_MULZSSFD16SS_13_02_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzssfd16ss_13_02 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSSFD16SS_13_02_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssfd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSFD16SS_13_02_S2 : AE_MULZSSFD16SS_13_02_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssfd16ss_13_02_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSFD16SS_33_22_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzssfd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSSFD16SS_33_22 : AE_MULZSSFD16SS_33_22_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzssfd16ss_33_22 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSSFD16SS_33_22_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssfd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSFD16SS_33_22_S2 : AE_MULZSSFD16SS_33_22_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssfd16ss_33_22_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSFD24_HH_LL_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzssfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZSSFD24_HH_LL : AE_MULZSSFD24_HH_LL_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzssfd24_hh_ll AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZSSFD24_HH_LL_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSFD24_HH_LL_S2 : AE_MULZSSFD24_HH_LL_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssfd24_hh_ll_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSFD24_HL_LH_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_q0), (ins AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1), "ae_mulzssfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_q0; +bits<4> ae_mul_d0; +bits<4> ae_mul_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_mul_q0{0}; +let Inst{17} = ae_mul_q0{1}; +let Inst{18} = ae_mul_q0{2}; +let Inst{19} = ae_mul_q0{3}; +let Inst{24} = ae_mul_d0{0}; +let Inst{25} = ae_mul_d0{1}; +let Inst{26} = ae_mul_d0{2}; +let Inst{27} = ae_mul_d0{3}; +let Inst{32} = ae_mul_d1{0}; +let Inst{33} = ae_mul_d1{1}; +let Inst{34} = ae_mul_d1{2}; +let Inst{35} = ae_mul_d1{3}; +} + + + +def AE_MULZSSFD24_HL_LH : AE_MULZSSFD24_HL_LH_AE_FORMAT<[(set AE_DR:$ae_mul_q0, (int_xtensa_ae_mulzssfd24_hl_lh AE_DR:$ae_mul_d0, AE_DR:$ae_mul_d1))]>; + +class AE_MULZSSFD24_HL_LH_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSFD24_HL_LH_S2 : AE_MULZSSFD24_HL_LH_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssfd24_hl_lh_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSFD32X16_H1_L0_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzssfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{39} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSSFD32X16_H1_L0 : AE_MULZSSFD32X16_H1_L0_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzssfd32x16_h1_l0 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSSFD32X16_H1_L0_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSFD32X16_H1_L0_S2 : AE_MULZSSFD32X16_H1_L0_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssfd32x16_h1_l0_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_MULZSSFD32X16_H3_L2_AE_FORMAT48_3 pattern> + : XtensaInst48<(outs AE_DR:$opnd_ae_sem_mul_x2_S1_q0), (ins AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1), "ae_mulzssfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> opnd_ae_sem_mul_x2_S1_q0; +bits<4> opnd_ae_sem_mul_x2_S1_d0; +bits<4> opnd_ae_sem_mul_x2_S1_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{42} = 1; +let Inst{44} = 1; +let Inst{45} = 1; +let Inst{46} = 1; +//operands +let Inst{16} = opnd_ae_sem_mul_x2_S1_q0{0}; +let Inst{17} = opnd_ae_sem_mul_x2_S1_q0{1}; +let Inst{18} = opnd_ae_sem_mul_x2_S1_q0{2}; +let Inst{19} = opnd_ae_sem_mul_x2_S1_q0{3}; +let Inst{20} = opnd_ae_sem_mul_x2_S1_d0{0}; +let Inst{21} = opnd_ae_sem_mul_x2_S1_d0{1}; +let Inst{22} = opnd_ae_sem_mul_x2_S1_d0{2}; +let Inst{23} = opnd_ae_sem_mul_x2_S1_d0{3}; +let Inst{24} = opnd_ae_sem_mul_x2_S1_d1{0}; +let Inst{25} = opnd_ae_sem_mul_x2_S1_d1{1}; +let Inst{26} = opnd_ae_sem_mul_x2_S1_d1{2}; +let Inst{27} = opnd_ae_sem_mul_x2_S1_d1{3}; +} + + + +def AE_MULZSSFD32X16_H3_L2 : AE_MULZSSFD32X16_H3_L2_AE_FORMAT48_3<[(set AE_DR:$opnd_ae_sem_mul_x2_S1_q0, (int_xtensa_ae_mulzssfd32x16_h3_l2 AE_DR:$opnd_ae_sem_mul_x2_S1_d0, AE_DR:$opnd_ae_sem_mul_x2_S1_d1))]>; + +class AE_MULZSSFD32X16_H3_L2_S2_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_mul_S2_q0), (ins AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1), "ae_mulzssfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_mul_S2_q0; +bits<4> ae_mul_S2_d0; +bits<4> ae_mul_S2_d1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_mul_S2_q0{0}; +let Inst{21} = ae_mul_S2_q0{1}; +let Inst{22} = ae_mul_S2_q0{2}; +let Inst{23} = ae_mul_S2_q0{3}; +let Inst{36} = ae_mul_S2_d0{0}; +let Inst{37} = ae_mul_S2_d0{1}; +let Inst{38} = ae_mul_S2_d0{2}; +let Inst{39} = ae_mul_S2_d0{3}; +let Inst{28} = ae_mul_S2_d1{0}; +let Inst{29} = ae_mul_S2_d1{1}; +let Inst{30} = ae_mul_S2_d1{2}; +let Inst{31} = ae_mul_S2_d1{3}; +} + + + +def AE_MULZSSFD32X16_H3_L2_S2 : AE_MULZSSFD32X16_H3_L2_S2_AE_FORMAT<[(set AE_DR:$ae_mul_S2_q0, (int_xtensa_ae_mulzssfd32x16_h3_l2_s2 AE_DR:$ae_mul_S2_d0, AE_DR:$ae_mul_S2_d1))]>; + +class AE_NAND_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1), "ae_nand $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; +bits<4> ae_dr_to_dr_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_dr_to_dr_v{0}; +let Inst{21} = ae_dr_to_dr_v{1}; +let Inst{22} = ae_dr_to_dr_v{2}; +let Inst{23} = ae_dr_to_dr_v{3}; +let Inst{36} = ae_dr_to_dr_v0{0}; +let Inst{37} = ae_dr_to_dr_v0{1}; +let Inst{38} = ae_dr_to_dr_v0{2}; +let Inst{39} = ae_dr_to_dr_v0{3}; +let Inst{28} = ae_dr_to_dr_v1{0}; +let Inst{29} = ae_dr_to_dr_v1{1}; +let Inst{30} = ae_dr_to_dr_v1{2}; +let Inst{31} = ae_dr_to_dr_v1{3}; +} + + + +def AE_NAND : AE_NAND_AE_FORMAT1<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_nand AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1))]>; + +class AE_NEG16S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_neg16s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_NEG16S : AE_NEG16S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_neg16s AE_DR:$ae_arth_v1))]>; + +class AE_NEG24S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_neg24s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{27} = 1; +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_NEG24S : AE_NEG24S_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_neg24s AE_DR:$ae_arth_v1))]>; + +class AE_NEG32_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_neg32 $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{24} = 1; +let Inst{27} = 1; +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_NEG32 : AE_NEG32_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_neg32 AE_DR:$ae_arth_v1))]>; + +class AE_NEG32S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_neg32s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_NEG32S : AE_NEG32S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_neg32s AE_DR:$ae_arth_v1))]>; + +class AE_NEG64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_neg64 $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{10} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_NEG64 : AE_NEG64_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_neg64 AE_DR:$ae_arth_v1))]>; + +class AE_NEG64S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_neg64s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{26} = 1; +let Inst{27} = 1; +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{51} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_NEG64S : AE_NEG64S_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_neg64s AE_DR:$ae_arth_v1))]>; + +class AE_NSA64_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_nsa64 $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_NSA64 : AE_NSA64_X24<[(set AR:$arr, (int_xtensa_ae_nsa64 AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_NSAZ16_0_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_nsaz16.0 $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_NSAZ16_0 : AE_NSAZ16_0_X24<[(set AR:$arr, (int_xtensa_ae_nsaz16_0 AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_NSAZ32_L_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AE_DR:$ae_dr_to_ar_v0), "ae_nsaz32.l $arr, $ae_dr_to_ar_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ae_dr_to_ar_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ae_dr_to_ar_v0{0}; +let Inst{9} = ae_dr_to_ar_v0{1}; +let Inst{10} = ae_dr_to_ar_v0{2}; +let Inst{11} = ae_dr_to_ar_v0{3}; +} + + + +def AE_NSAZ32_L : AE_NSAZ32_L_X24<[(set AR:$arr, (int_xtensa_ae_nsaz32_l AE_DR:$ae_dr_to_ar_v0))]>; + +class AE_OR_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1), "ae_or $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; +bits<4> ae_dr_to_dr_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +//operands +let Inst{12} = ae_dr_to_dr_v{0}; +let Inst{13} = ae_dr_to_dr_v{1}; +let Inst{14} = ae_dr_to_dr_v{2}; +let Inst{15} = ae_dr_to_dr_v{3}; +let Inst{8} = ae_dr_to_dr_v0{0}; +let Inst{9} = ae_dr_to_dr_v0{1}; +let Inst{10} = ae_dr_to_dr_v0{2}; +let Inst{11} = ae_dr_to_dr_v0{3}; +let Inst{4} = ae_dr_to_dr_v1{0}; +let Inst{5} = ae_dr_to_dr_v1{1}; +let Inst{6} = ae_dr_to_dr_v1{2}; +let Inst{7} = ae_dr_to_dr_v1{3}; +} + + + +def AE_OR : AE_OR_X24<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_or AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1))]>; + +class AE_PKSR24_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_pks_d_out), (ins AE_DR:$ae_pks_d, AE_DR:$ae_pks_s, uimm2:$ae_imm2), "ae_pksr24 $ae_pks_d, $ae_pks_s, $ae_imm2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_pks_d; +bits<4> ae_pks_s; +bits<2> ae_imm2; +let Constraints = "$ae_pks_d = $ae_pks_d_out,@earlyclobber $ae_pks_d_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_pks_d{0}; +let Inst{13} = ae_pks_d{1}; +let Inst{14} = ae_pks_d{2}; +let Inst{15} = ae_pks_d{3}; +let Inst{4} = ae_pks_s{0}; +let Inst{5} = ae_pks_s{1}; +let Inst{6} = ae_pks_s{2}; +let Inst{7} = ae_pks_s{3}; +let Inst{10} = ae_imm2{0}; +let Inst{11} = ae_imm2{1}; +} + + + +def AE_PKSR24 : AE_PKSR24_X24<[(set AE_DR:$ae_pks_d_out, (int_xtensa_ae_pksr24 AE_DR:$ae_pks_d, AE_DR:$ae_pks_s, timm:$ae_imm2))]>; + +class AE_PKSR32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_pks_d_out), (ins AE_DR:$ae_pks_d, AE_DR:$ae_pks_s, uimm2:$ae_imm2), "ae_pksr32 $ae_pks_d, $ae_pks_s, $ae_imm2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_pks_d; +bits<4> ae_pks_s; +bits<2> ae_imm2; +let Constraints = "$ae_pks_d = $ae_pks_d_out,@earlyclobber $ae_pks_d_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_pks_d{0}; +let Inst{13} = ae_pks_d{1}; +let Inst{14} = ae_pks_d{2}; +let Inst{15} = ae_pks_d{3}; +let Inst{4} = ae_pks_s{0}; +let Inst{5} = ae_pks_s{1}; +let Inst{6} = ae_pks_s{2}; +let Inst{7} = ae_pks_s{3}; +let Inst{10} = ae_imm2{0}; +let Inst{11} = ae_imm2{1}; +} + + + +def AE_PKSR32 : AE_PKSR32_X24<[(set AE_DR:$ae_pks_d_out, (int_xtensa_ae_pksr32 AE_DR:$ae_pks_d, AE_DR:$ae_pks_s, timm:$ae_imm2))]>; + +class AE_ROUND16X4F32SASYM_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1, AE_DR:$ae_arth_v0), "ae_round16x4f32sasym $ae_arth_v, $ae_arth_v1, $ae_arth_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; +bits<4> ae_arth_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +} + + + +def AE_ROUND16X4F32SASYM : AE_ROUND16X4F32SASYM_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_round16x4f32sasym AE_DR:$ae_arth_v1, AE_DR:$ae_arth_v0))]>; + +class AE_ROUND16X4F32SSYM_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1, AE_DR:$ae_arth_v0), "ae_round16x4f32ssym $ae_arth_v, $ae_arth_v1, $ae_arth_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; +bits<4> ae_arth_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +let Inst{28} = ae_arth_v0{0}; +let Inst{29} = ae_arth_v0{1}; +let Inst{30} = ae_arth_v0{2}; +let Inst{31} = ae_arth_v0{3}; +} + + + +def AE_ROUND16X4F32SSYM : AE_ROUND16X4F32SSYM_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_round16x4f32ssym AE_DR:$ae_arth_v1, AE_DR:$ae_arth_v0))]>; + +class AE_ROUND24X2F48SASYM_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_round24x2f48sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ROUND24X2F48SASYM : AE_ROUND24X2F48SASYM_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_round24x2f48sasym AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ROUND24X2F48SSYM_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_round24x2f48ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ROUND24X2F48SSYM : AE_ROUND24X2F48SSYM_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_round24x2f48ssym AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ROUND32X2F48SASYM_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_round32x2f48sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{59} = 1; +let Inst{60} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{28} = ae_arth_v0{0}; +let Inst{29} = ae_arth_v0{1}; +let Inst{30} = ae_arth_v0{2}; +let Inst{31} = ae_arth_v0{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +} + + + +def AE_ROUND32X2F48SASYM : AE_ROUND32X2F48SASYM_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_round32x2f48sasym AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ROUND32X2F48SSYM_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_round32x2f48ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{61} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{28} = ae_arth_v0{0}; +let Inst{29} = ae_arth_v0{1}; +let Inst{30} = ae_arth_v0{2}; +let Inst{31} = ae_arth_v0{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +} + + + +def AE_ROUND32X2F48SSYM : AE_ROUND32X2F48SSYM_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_round32x2f48ssym AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ROUND32X2F64SASYM_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_round32x2f64sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ROUND32X2F64SASYM : AE_ROUND32X2F64SASYM_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_round32x2f64sasym AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ROUND32X2F64SSYM_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_round32x2f64ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{57} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{28} = ae_arth_v0{0}; +let Inst{29} = ae_arth_v0{1}; +let Inst{30} = ae_arth_v0{2}; +let Inst{31} = ae_arth_v0{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +} + + + +def AE_ROUND32X2F64SSYM : AE_ROUND32X2F64SSYM_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_round32x2f64ssym AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ROUNDSP16F24ASYM_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0), "ae_roundsp16f24asym $ae_arth_v, $ae_arth_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{28} = ae_arth_v0{0}; +let Inst{29} = ae_arth_v0{1}; +let Inst{30} = ae_arth_v0{2}; +let Inst{31} = ae_arth_v0{3}; +} + + + +def AE_ROUNDSP16F24ASYM : AE_ROUNDSP16F24ASYM_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_roundsp16f24asym AE_DR:$ae_arth_v0))]>; + +class AE_ROUNDSP16F24SYM_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0), "ae_roundsp16f24sym $ae_arth_v, $ae_arth_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{36} = 1; +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{28} = ae_arth_v0{0}; +let Inst{29} = ae_arth_v0{1}; +let Inst{30} = ae_arth_v0{2}; +let Inst{31} = ae_arth_v0{3}; +} + + + +def AE_ROUNDSP16F24SYM : AE_ROUNDSP16F24SYM_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_roundsp16f24sym AE_DR:$ae_arth_v0))]>; + +class AE_ROUNDSP16Q48X2ASYM_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_roundsp16q48x2asym $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ROUNDSP16Q48X2ASYM : AE_ROUNDSP16Q48X2ASYM_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_roundsp16q48x2asym AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ROUNDSP16Q48X2SYM_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_roundsp16q48x2sym $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{58} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{28} = ae_arth_v0{0}; +let Inst{29} = ae_arth_v0{1}; +let Inst{30} = ae_arth_v0{2}; +let Inst{31} = ae_arth_v0{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +} + + + +def AE_ROUNDSP16Q48X2SYM : AE_ROUNDSP16Q48X2SYM_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_roundsp16q48x2sym AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_ROUNDSQ32F48ASYM_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_roundsq32f48asym $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ROUNDSQ32F48ASYM : AE_ROUNDSQ32F48ASYM_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_roundsq32f48asym AE_DR:$ae_arth_v1))]>; + +class AE_ROUNDSQ32F48SYM_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_roundsq32f48sym $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_ROUNDSQ32F48SYM : AE_ROUNDSQ32F48SYM_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_roundsq32f48sym AE_DR:$ae_arth_v1))]>; + +class AE_S16_0_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm16n_14:$ae_immls16), "ae_s16.0.i $ae_ls_v, $ars, $ae_immls16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls16; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls16{0}; +let Inst{5} = ae_immls16{1}; +let Inst{6} = ae_immls16{2}; +let Inst{7} = ae_immls16{3}; +} + + + +def AE_S16_0_I : AE_S16_0_I_X24<[(int_xtensa_ae_s16_0_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls16)]>; + +class AE_S16_0_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm16n_14:$ae_immls16), "ae_s16.0.ip $ae_ls_v, $ars, $ae_immls16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls16; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls16{0}; +let Inst{5} = ae_immls16{1}; +let Inst{6} = ae_immls16{2}; +let Inst{7} = ae_immls16{3}; +} + + + +def AE_S16_0_IP : AE_S16_0_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s16_0_ip AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls16))]>; + +class AE_S16_0_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16.0.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16_0_X : AE_S16_0_X_AE_FORMAT48<[(int_xtensa_ae_s16_0_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S16_0_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16.0.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16_0_XC : AE_S16_0_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s16_0_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S16_0_XP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16.0.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16_0_XP : AE_S16_0_XP_X24<[(set AR:$ars_out, (int_xtensa_ae_s16_0_xp AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S16M_L_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm16n_14:$ae_immls16), "ae_s16m.l.i $ae_ls_v, $ars, $ae_immls16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls16; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls16{0}; +let Inst{5} = ae_immls16{1}; +let Inst{6} = ae_immls16{2}; +let Inst{7} = ae_immls16{3}; +} + + + +def AE_S16M_L_I : AE_S16M_L_I_X24<[(int_xtensa_ae_s16m_l_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls16)]>; + +class AE_S16M_L_IU_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm16n_14:$ae_immls16), "ae_s16m.l.iu $ae_ls_v, $ars, $ae_immls16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls16; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls16{0}; +let Inst{5} = ae_immls16{1}; +let Inst{6} = ae_immls16{2}; +let Inst{7} = ae_immls16{3}; +} + + + +def AE_S16M_L_IU : AE_S16M_L_IU_X24<[(set AR:$ars_out, (int_xtensa_ae_s16m_l_iu AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls16))]>; + +class AE_S16M_L_X_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16m.l.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16M_L_X : AE_S16M_L_X_X24<[(int_xtensa_ae_s16m_l_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S16M_L_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16m.l.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16M_L_XC : AE_S16M_L_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s16m_l_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S16M_L_XU_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16m.l.xu $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16M_L_XU : AE_S16M_L_XU_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s16m_l_xu AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S16X2M_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm32n_28:$ae_immls32), "ae_s16x2m.i $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S16X2M_I : AE_S16X2M_I_X24<[(int_xtensa_ae_s16x2m_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls32)]>; + +class AE_S16X2M_IU_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm32n_28:$ae_immls32), "ae_s16x2m.iu $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S16X2M_IU : AE_S16X2M_IU_X24<[(set AR:$ars_out, (int_xtensa_ae_s16x2m_iu AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls32))]>; + +class AE_S16X2M_X_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16x2m.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16X2M_X : AE_S16X2M_X_X24<[(int_xtensa_ae_s16x2m_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S16X2M_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16x2m.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16X2M_XC : AE_S16X2M_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s16x2m_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S16X2M_XU_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16x2m.xu $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16X2M_XU : AE_S16X2M_XU_X24<[(set AR:$ars_out, (int_xtensa_ae_s16x2m_xu AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S16X4_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm64n_56:$ae_immls64), "ae_s16x4.i $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_S16X4_I : AE_S16X4_I_X24<[(int_xtensa_ae_s16x4_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls64)]>; + +class AE_S16X4_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm0_56:$ae_immls64pos), "ae_s16x4.ip $ae_ls_v, $ars, $ae_immls64pos", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<3> ae_immls64pos; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64pos{0}; +let Inst{5} = ae_immls64pos{1}; +let Inst{6} = ae_immls64pos{2}; +} + + + +def AE_S16X4_IP : AE_S16X4_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s16x4_ip AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls64pos))]>; + +class AE_S16X4_RIC_AE_FORMAT pattern> + : XtensaInst64<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars), "ae_s16x4.ric $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{4} = 1; +let Inst{6} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_S16X4_RIC : AE_S16X4_RIC_AE_FORMAT<[(set AR:$ars_out, (int_xtensa_ae_s16x4_ric AE_DR:$ae_ls_v, AR:$ars))]>; + +class AE_S16X4_RIP_AE_FORMAT pattern> + : XtensaInst64<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars), "ae_s16x4.rip $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_S16X4_RIP : AE_S16X4_RIP_AE_FORMAT<[(set AR:$ars_out, (int_xtensa_ae_s16x4_rip AE_DR:$ae_ls_v, AR:$ars))]>; + +class AE_S16X4_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16x4.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{35} = 1; +let Inst{36} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16X4_X : AE_S16X4_X_AE_FORMAT48<[(int_xtensa_ae_s16x4_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S16X4_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16x4.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16X4_XC : AE_S16X4_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s16x4_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S16X4_XP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s16x4.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S16X4_XP : AE_S16X4_XP_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s16x4_xp AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S24RA64S_I_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_DR:$ae_ls_v1, AR:$ars, imm32n_28:$ae_immls32), "ae_s24ra64s.i $ae_ls_v1, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> ae_immls32; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S24RA64S_I : AE_S24RA64S_I_AE_FORMAT48<[(int_xtensa_ae_s24ra64s_i AE_DR:$ae_ls_v1, AR:$ars, timm:$ae_immls32)]>; + +class AE_S24RA64S_IP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v1, AR:$ars, imm32n_28:$ae_immls32), "ae_s24ra64s.ip $ae_ls_v1, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S24RA64S_IP : AE_S24RA64S_IP_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s24ra64s_ip AE_DR:$ae_ls_v1, AR:$ars, timm:$ae_immls32))]>; + +class AE_S24RA64S_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_DR:$ae_ls_v1, AR:$ars, AR:$art), "ae_s24ra64s.x $ae_ls_v1, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S24RA64S_X : AE_S24RA64S_X_AE_FORMAT48<[(int_xtensa_ae_s24ra64s_x AE_DR:$ae_ls_v1, AR:$ars, AR:$art)]>; + +class AE_S24RA64S_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v1, AR:$ars, AR:$art), "ae_s24ra64s.xc $ae_ls_v1, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S24RA64S_XC : AE_S24RA64S_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s24ra64s_xc AE_DR:$ae_ls_v1, AR:$ars, AR:$art))]>; + +class AE_S24RA64S_XP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v1, AR:$ars, AR:$art), "ae_s24ra64s.xp $ae_ls_v1, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S24RA64S_XP : AE_S24RA64S_XP_X24<[(set AR:$ars_out, (int_xtensa_ae_s24ra64s_xp AE_DR:$ae_ls_v1, AR:$ars, AR:$art))]>; + +class AE_S24X2RA64S_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v2, AE_DR:$ae_ls_v1, AR:$ars), "ae_s24x2ra64s.ip $ae_ls_v2, $ae_ls_v1, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v2; +bits<4> ae_ls_v1; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +//operands +let Inst{4} = ae_ls_v2{0}; +let Inst{5} = ae_ls_v2{1}; +let Inst{6} = ae_ls_v2{2}; +let Inst{7} = ae_ls_v2{3}; +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_S24X2RA64S_IP : AE_S24X2RA64S_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s24x2ra64s_ip AE_DR:$ae_ls_v2, AE_DR:$ae_ls_v1, AR:$ars))]>; + +class AE_S32_L_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm32n_28:$ae_immls32), "ae_s32.l.i $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S32_L_I : AE_S32_L_I_X24<[(int_xtensa_ae_s32_l_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls32)]>; + +class AE_S32_L_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm32n_28:$ae_immls32), "ae_s32.l.ip $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S32_L_IP : AE_S32_L_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32_l_ip AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls32))]>; + +class AE_S32_L_X_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32.l.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32_L_X : AE_S32_L_X_X24<[(int_xtensa_ae_s32_l_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S32_L_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32.l.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32_L_XC : AE_S32_L_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32_l_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32_L_XP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32.l.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32_L_XP : AE_S32_L_XP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32_l_xp AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32F24_L_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm32n_28:$ae_immls32), "ae_s32f24.l.i $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S32F24_L_I : AE_S32F24_L_I_X24<[(int_xtensa_ae_s32f24_l_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls32)]>; + +class AE_S32F24_L_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm32n_28:$ae_immls32), "ae_s32f24.l.ip $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S32F24_L_IP : AE_S32F24_L_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32f24_l_ip AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls32))]>; + +class AE_S32F24_L_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32f24.l.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{31} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32F24_L_X : AE_S32F24_L_X_AE_FORMAT48<[(int_xtensa_ae_s32f24_l_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S32F24_L_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32f24.l.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{31} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32F24_L_XC : AE_S32F24_L_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32f24_l_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32F24_L_XP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32f24.l.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32F24_L_XP : AE_S32F24_L_XP_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32f24_l_xp AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32M_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm32n_28:$ae_immls32), "ae_s32m.i $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S32M_I : AE_S32M_I_X24<[(int_xtensa_ae_s32m_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls32)]>; + +class AE_S32M_IU_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm32n_28:$ae_immls32), "ae_s32m.iu $ae_ls_v, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S32M_IU : AE_S32M_IU_X24<[(set AR:$ars_out, (int_xtensa_ae_s32m_iu AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls32))]>; + +class AE_S32M_X_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32m.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32M_X : AE_S32M_X_X24<[(int_xtensa_ae_s32m_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S32M_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32m.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32M_XC : AE_S32M_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32m_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32M_XU_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32m.xu $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32M_XU : AE_S32M_XU_X24<[(set AR:$ars_out, (int_xtensa_ae_s32m_xu AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32RA64S_I_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_DR:$ae_ls_v1, AR:$ars, imm32n_28:$ae_immls32), "ae_s32ra64s.i $ae_ls_v1, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> ae_immls32; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S32RA64S_I : AE_S32RA64S_I_AE_FORMAT48<[(int_xtensa_ae_s32ra64s_i AE_DR:$ae_ls_v1, AR:$ars, timm:$ae_immls32)]>; + +class AE_S32RA64S_IP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v1, AR:$ars, imm32n_28:$ae_immls32), "ae_s32ra64s.ip $ae_ls_v1, $ars, $ae_immls32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> ae_immls32; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{33} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls32{0}; +let Inst{5} = ae_immls32{1}; +let Inst{6} = ae_immls32{2}; +let Inst{7} = ae_immls32{3}; +} + + + +def AE_S32RA64S_IP : AE_S32RA64S_IP_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32ra64s_ip AE_DR:$ae_ls_v1, AR:$ars, timm:$ae_immls32))]>; + +class AE_S32RA64S_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_DR:$ae_ls_v1, AR:$ars, AR:$art), "ae_s32ra64s.x $ae_ls_v1, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32RA64S_X : AE_S32RA64S_X_AE_FORMAT48<[(int_xtensa_ae_s32ra64s_x AE_DR:$ae_ls_v1, AR:$ars, AR:$art)]>; + +class AE_S32RA64S_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v1, AR:$ars, AR:$art), "ae_s32ra64s.xc $ae_ls_v1, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32RA64S_XC : AE_S32RA64S_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32ra64s_xc AE_DR:$ae_ls_v1, AR:$ars, AR:$art))]>; + +class AE_S32RA64S_XP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v1, AR:$ars, AR:$art), "ae_s32ra64s.xp $ae_ls_v1, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v1; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +//operands +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32RA64S_XP : AE_S32RA64S_XP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32ra64s_xp AE_DR:$ae_ls_v1, AR:$ars, AR:$art))]>; + +class AE_S32X2_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm64n_56:$ae_immls64), "ae_s32x2.i $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_S32X2_I : AE_S32X2_I_X24<[(int_xtensa_ae_s32x2_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls64)]>; + +class AE_S32X2_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm0_56:$ae_immls64pos), "ae_s32x2.ip $ae_ls_v, $ars, $ae_immls64pos", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<3> ae_immls64pos; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64pos{0}; +let Inst{5} = ae_immls64pos{1}; +let Inst{6} = ae_immls64pos{2}; +} + + + +def AE_S32X2_IP : AE_S32X2_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32x2_ip AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls64pos))]>; + +class AE_S32X2_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars), "ae_s32x2.ric $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_S32X2_RIC : AE_S32X2_RIC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32x2_ric AE_DR:$ae_ls_v, AR:$ars))]>; + +class AE_S32X2_RIP_AE_FORMAT pattern> + : XtensaInst64<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars), "ae_s32x2.rip $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_S32X2_RIP : AE_S32X2_RIP_AE_FORMAT<[(set AR:$ars_out, (int_xtensa_ae_s32x2_rip AE_DR:$ae_ls_v, AR:$ars))]>; + +class AE_S32X2_X_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32x2.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32X2_X : AE_S32X2_X_X24<[(int_xtensa_ae_s32x2_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S32X2_XC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32x2.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32X2_XC : AE_S32X2_XC_X24<[(set AR:$ars_out, (int_xtensa_ae_s32x2_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32X2_XP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32x2.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32X2_XP : AE_S32X2_XP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32x2_xp AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32X2F24_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm64n_56:$ae_immls64), "ae_s32x2f24.i $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_S32X2F24_I : AE_S32X2F24_I_X24<[(int_xtensa_ae_s32x2f24_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls64)]>; + +class AE_S32X2F24_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm0_56:$ae_immls64pos), "ae_s32x2f24.ip $ae_ls_v, $ars, $ae_immls64pos", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<3> ae_immls64pos; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64pos{0}; +let Inst{5} = ae_immls64pos{1}; +let Inst{6} = ae_immls64pos{2}; +} + + + +def AE_S32X2F24_IP : AE_S32X2F24_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32x2f24_ip AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls64pos))]>; + +class AE_S32X2F24_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars), "ae_s32x2f24.ric $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{6} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_S32X2F24_RIC : AE_S32X2F24_RIC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32x2f24_ric AE_DR:$ae_ls_v, AR:$ars))]>; + +class AE_S32X2F24_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars), "ae_s32x2f24.rip $ae_ls_v, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{7} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_S32X2F24_RIP : AE_S32X2F24_RIP_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s32x2f24_rip AE_DR:$ae_ls_v, AR:$ars))]>; + +class AE_S32X2F24_X_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32x2f24.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32X2F24_X : AE_S32X2F24_X_X24<[(int_xtensa_ae_s32x2f24_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S32X2F24_XC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32x2f24.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32X2F24_XC : AE_S32X2F24_XC_X24<[(set AR:$ars_out, (int_xtensa_ae_s32x2f24_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32X2F24_XP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s32x2f24.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S32X2F24_XP : AE_S32X2F24_XP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32x2f24_xp AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S32X2RA64S_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v2, AE_DR:$ae_ls_v1, AR:$ars), "ae_s32x2ra64s.ip $ae_ls_v2, $ae_ls_v1, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v2; +bits<4> ae_ls_v1; +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +//operands +let Inst{4} = ae_ls_v2{0}; +let Inst{5} = ae_ls_v2{1}; +let Inst{6} = ae_ls_v2{2}; +let Inst{7} = ae_ls_v2{3}; +let Inst{12} = ae_ls_v1{0}; +let Inst{13} = ae_ls_v1{1}; +let Inst{14} = ae_ls_v1{2}; +let Inst{15} = ae_ls_v1{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_S32X2RA64S_IP : AE_S32X2RA64S_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s32x2ra64s_ip AE_DR:$ae_ls_v2, AE_DR:$ae_ls_v1, AR:$ars))]>; + +class AE_S64_I_X24 pattern> + : XtensaAEInst24<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, imm64n_56:$ae_immls64), "ae_s64.i $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_S64_I : AE_S64_I_X24<[(int_xtensa_ae_s64_i AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls64)]>; + +class AE_S64_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, imm64n_56:$ae_immls64), "ae_s64.ip $ae_ls_v, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> ae_immls64; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{6} = ae_immls64{2}; +let Inst{7} = ae_immls64{3}; +} + + + +def AE_S64_IP : AE_S64_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_s64_ip AE_DR:$ae_ls_v, AR:$ars, timm:$ae_immls64))]>; + +class AE_S64_X_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s64.x $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S64_X : AE_S64_X_AE_FORMAT48<[(int_xtensa_ae_s64_x AE_DR:$ae_ls_v, AR:$ars, AR:$art)]>; + +class AE_S64_XC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s64.xc $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S64_XC : AE_S64_XC_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s64_xc AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_S64_XP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AR:$ars_out), (ins AE_DR:$ae_ls_v, AR:$ars, AR:$art), "ae_s64.xp $ae_ls_v, $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_S64_XP : AE_S64_XP_AE_FORMAT48<[(set AR:$ars_out, (int_xtensa_ae_s64_xp AE_DR:$ae_ls_v, AR:$ars, AR:$art))]>; + +class AE_SA16X4_IC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa16x4.ic $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA16X4_IC : AE_SA16X4_IC_AE_FORMAT48<[]>; + +class AE_SA16X4_IP_X24 pattern> + : XtensaAEInst24<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa16x4.ip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{4} = ae_ls_su{0}; +let Inst{5} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA16X4_IP : AE_SA16X4_IP_X24<[]>; + +class AE_SA16X4_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa16x4.ric $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA16X4_RIC : AE_SA16X4_RIC_AE_FORMAT48<[]>; + +class AE_SA16X4_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa16x4.rip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA16X4_RIP : AE_SA16X4_RIP_AE_FORMAT48<[]>; + +class AE_SA24_L_IC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa24.l.ic $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA24_L_IC : AE_SA24_L_IC_AE_FORMAT48<[]>; + +class AE_SA24_L_IP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa24.l.ip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA24_L_IP : AE_SA24_L_IP_AE_FORMAT48<[]>; + +class AE_SA24_L_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa24.l.ric $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA24_L_RIC : AE_SA24_L_RIC_AE_FORMAT48<[]>; + +class AE_SA24_L_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa24.l.rip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA24_L_RIP : AE_SA24_L_RIP_AE_FORMAT48<[]>; + +class AE_SA24X2_IC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa24x2.ic $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA24X2_IC : AE_SA24X2_IC_AE_FORMAT48<[]>; + +class AE_SA24X2_IP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa24x2.ip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA24X2_IP : AE_SA24X2_IP_AE_FORMAT48<[]>; + +class AE_SA24X2_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa24x2.ric $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA24X2_RIC : AE_SA24X2_RIC_AE_FORMAT48<[]>; + +class AE_SA24X2_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa24x2.rip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA24X2_RIP : AE_SA24X2_RIP_AE_FORMAT48<[]>; + +class AE_SA32X2_IC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa32x2.ic $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{28} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA32X2_IC : AE_SA32X2_IC_AE_FORMAT48<[]>; + +class AE_SA32X2_IP_X24 pattern> + : XtensaAEInst24<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa32x2.ip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{4} = ae_ls_su{0}; +let Inst{5} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA32X2_IP : AE_SA32X2_IP_X24<[]>; + +class AE_SA32X2_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa32x2.ric $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA32X2_RIC : AE_SA32X2_RIC_AE_FORMAT48<[]>; + +class AE_SA32X2_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa32x2.rip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{30} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA32X2_RIP : AE_SA32X2_RIP_AE_FORMAT48<[]>; + +class AE_SA32X2F24_IC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa32x2f24.ic $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA32X2F24_IC : AE_SA32X2F24_IC_AE_FORMAT48<[]>; + +class AE_SA32X2F24_IP_X24 pattern> + : XtensaAEInst24<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa32x2f24.ip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{4} = ae_ls_su{0}; +let Inst{5} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA32X2F24_IP : AE_SA32X2F24_IP_X24<[]>; + +class AE_SA32X2F24_RIC_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa32x2f24.ric $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{28} = 1; +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA32X2F24_RIC : AE_SA32X2F24_RIC_AE_FORMAT48<[]>; + +class AE_SA32X2F24_RIP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out, AR:$ars_out), (ins AE_DR:$ae_ls_v, AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa32x2f24.rip $ae_ls_v, $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_ls_v; +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out, $ars = $ars_out,@earlyclobber $ars_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{4} = 1; +let Inst{32} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{12} = ae_ls_v{0}; +let Inst{13} = ae_ls_v{1}; +let Inst{14} = ae_ls_v{2}; +let Inst{15} = ae_ls_v{3}; +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA32X2F24_RIP : AE_SA32X2F24_RIP_AE_FORMAT48<[]>; + +class AE_SA64NEG_FP_AE_FORMAT48 pattern> + : XtensaInst48<(outs AE_VALIGN:$ae_ls_su_out), (ins AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa64neg.fp $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{5} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{15} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA64NEG_FP : AE_SA64NEG_FP_AE_FORMAT48<[(set AE_VALIGN:$ae_ls_su_out, (int_xtensa_ae_sa64neg_fp AE_VALIGN:$ae_ls_su, AR:$ars))]>; + +class AE_SA64POS_FP_X24 pattern> + : XtensaAEInst24<(outs AE_VALIGN:$ae_ls_su_out), (ins AE_VALIGN:$ae_ls_su, AR:$ars), "ae_sa64pos.fp $ae_ls_su, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_su; +bits<4> ars; +let Constraints = "$ae_ls_su = $ae_ls_su_out,@earlyclobber $ae_ls_su_out"; + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = ae_ls_su{0}; +let Inst{5} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SA64POS_FP : AE_SA64POS_FP_X24<[(set AE_VALIGN:$ae_ls_su_out, (int_xtensa_ae_sa64pos_fp AE_VALIGN:$ae_ls_su, AR:$ars))]>; + +class AE_SALIGN64_I_AE_FORMAT48 pattern> + : XtensaInst48<(outs ), (ins AE_VALIGN:$ae_ls_su, AR:$ars, imm64n_56:$ae_immls64), "ae_salign64.i $ae_ls_su, $ars, $ae_immls64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_ls_su; +bits<4> ars; +bits<4> ae_immls64; + + +let mayStore = 1;let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//opcode +let Inst{14} = 1; +let Inst{30} = 1; +let Inst{33} = 1; +let Inst{34} = 1; +let Inst{37} = 1; +//operands +let Inst{6} = ae_ls_su{0}; +let Inst{7} = ae_ls_su{1}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = ae_immls64{0}; +let Inst{5} = ae_immls64{1}; +let Inst{28} = ae_immls64{2}; +let Inst{29} = ae_immls64{3}; +} + + + +def AE_SALIGN64_I : AE_SALIGN64_I_AE_FORMAT48<[(int_xtensa_ae_salign64_i AE_VALIGN:$ae_ls_su, AR:$ars, timm:$ae_immls64)]>; + +class AE_SAT16X4_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_sat16x4 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{56} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{28} = ae_arth_v0{0}; +let Inst{29} = ae_arth_v0{1}; +let Inst{30} = ae_arth_v0{2}; +let Inst{31} = ae_arth_v0{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +} + + + +def AE_SAT16X4 : AE_SAT16X4_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sat16x4 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SAT24S_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_sat24s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{29} = 1; +let Inst{30} = 1; +let Inst{31} = 1; +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +} + + + +def AE_SAT24S : AE_SAT24S_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sat24s AE_DR:$ae_arth_v1))]>; + +class AE_SAT48S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_sat48s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_SAT48S : AE_SAT48S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sat48s AE_DR:$ae_arth_v1))]>; + +class AE_SATQ56S_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v1), "ae_satq56s $ae_arth_v, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_arth_v{0}; +let Inst{21} = ae_arth_v{1}; +let Inst{22} = ae_arth_v{2}; +let Inst{23} = ae_arth_v{3}; +let Inst{36} = ae_arth_v1{0}; +let Inst{37} = ae_arth_v1{1}; +let Inst{38} = ae_arth_v1{2}; +let Inst{39} = ae_arth_v1{3}; +} + + + +def AE_SATQ56S : AE_SATQ56S_AE_FORMAT1<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_satq56s AE_DR:$ae_arth_v1))]>; + +class AE_SB_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art), "ae_sb $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{13} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_SB : AE_SB_X24<[(set AR:$ars_out, (int_xtensa_ae_sb AR:$ars, AR:$art))]>; + +class AE_SB_IC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art), "ae_sb.ic $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_SB_IC : AE_SB_IC_X24<[(set AR:$ars_out, (int_xtensa_ae_sb_ic AR:$ars, AR:$art))]>; + +class AE_SB_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art), "ae_sb.ip $ars, $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_SB_IP : AE_SB_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_sb_ip AR:$ars, AR:$art))]>; + +class AE_SBF_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_sbf $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SBF : AE_SBF_X24<[(set AR:$ars_out, (int_xtensa_ae_sbf AR:$ars))]>; + +class AE_SBF_IC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_sbf.ic $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SBF_IC : AE_SBF_IC_X24<[(set AR:$ars_out, (int_xtensa_ae_sbf_ic AR:$ars))]>; + +class AE_SBF_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_sbf.ip $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{6} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SBF_IP : AE_SBF_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_sbf_ip AR:$ars))]>; + +class AE_SBI_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art, imm1_16:$ae_ohba2), "ae_sbi $ars, $art, $ae_ohba2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +bits<4> ae_ohba2; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +let Inst{12} = ae_ohba2{0}; +let Inst{13} = ae_ohba2{1}; +let Inst{14} = ae_ohba2{2}; +let Inst{15} = ae_ohba2{3}; +} + + + +def AE_SBI : AE_SBI_X24<[(set AR:$ars_out, (int_xtensa_ae_sbi AR:$ars, AR:$art, timm:$ae_ohba2))]>; + +class AE_SBI_IC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art, imm1_16:$ae_ohba2), "ae_sbi.ic $ars, $art, $ae_ohba2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +bits<4> ae_ohba2; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +let Inst{12} = ae_ohba2{0}; +let Inst{13} = ae_ohba2{1}; +let Inst{14} = ae_ohba2{2}; +let Inst{15} = ae_ohba2{3}; +} + + + +def AE_SBI_IC : AE_SBI_IC_X24<[(set AR:$ars_out, (int_xtensa_ae_sbi_ic AR:$ars, AR:$art, timm:$ae_ohba2))]>; + +class AE_SBI_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars, AR:$art, imm1_16:$ae_ohba2), "ae_sbi.ip $ars, $art, $ae_ohba2", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +bits<4> art; +bits<4> ae_ohba2; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +let Inst{12} = ae_ohba2{0}; +let Inst{13} = ae_ohba2{1}; +let Inst{14} = ae_ohba2{2}; +let Inst{15} = ae_ohba2{3}; +} + + + +def AE_SBI_IP : AE_SBI_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_sbi_ip AR:$ars, AR:$art, timm:$ae_ohba2))]>; + +class AE_SEL16I_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1, uimm4:$ae_selimm), "ae_sel16i $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1, $ae_selimm", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; +bits<4> ae_dr_to_dr_v1; +bits<4> ae_selimm; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{21} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_dr_to_dr_v{0}; +let Inst{13} = ae_dr_to_dr_v{1}; +let Inst{14} = ae_dr_to_dr_v{2}; +let Inst{15} = ae_dr_to_dr_v{3}; +let Inst{8} = ae_dr_to_dr_v0{0}; +let Inst{9} = ae_dr_to_dr_v0{1}; +let Inst{10} = ae_dr_to_dr_v0{2}; +let Inst{11} = ae_dr_to_dr_v0{3}; +let Inst{4} = ae_dr_to_dr_v1{0}; +let Inst{5} = ae_dr_to_dr_v1{1}; +let Inst{6} = ae_dr_to_dr_v1{2}; +let Inst{7} = ae_dr_to_dr_v1{3}; +let Inst{16} = ae_selimm{0}; +let Inst{17} = ae_selimm{1}; +let Inst{18} = ae_selimm{2}; +let Inst{19} = ae_selimm{3}; +} + + + +def AE_SEL16I : AE_SEL16I_X24<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_sel16i AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1, timm:$ae_selimm))]>; + +class AE_SEL16I_N_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1, uimm2:$ae_selimm_N), "ae_sel16i.n $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1, $ae_selimm_N", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; +bits<4> ae_dr_to_dr_v1; +bits<2> ae_selimm_N; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode + +//operands +let Inst{16} = ae_dr_to_dr_v{0}; +let Inst{17} = ae_dr_to_dr_v{1}; +let Inst{18} = ae_dr_to_dr_v{2}; +let Inst{19} = ae_dr_to_dr_v{3}; +let Inst{24} = ae_dr_to_dr_v0{0}; +let Inst{25} = ae_dr_to_dr_v0{1}; +let Inst{26} = ae_dr_to_dr_v0{2}; +let Inst{27} = ae_dr_to_dr_v0{3}; +let Inst{32} = ae_dr_to_dr_v1{0}; +let Inst{33} = ae_dr_to_dr_v1{1}; +let Inst{34} = ae_dr_to_dr_v1{2}; +let Inst{35} = ae_dr_to_dr_v1{3}; +let Inst{48} = ae_selimm_N{0}; +let Inst{49} = ae_selimm_N{1}; +} + + + +def AE_SEL16I_N : AE_SEL16I_N_AE_FORMAT<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_sel16i_n AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1, timm:$ae_selimm_N))]>; + +class AE_SEXT32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0, imm7_22:$ae_opnd_tp7), "ae_sext32 $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_opnd_tp7", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; +bits<4> ae_opnd_tp7; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +//operands +let Inst{12} = ae_dr_to_dr_v{0}; +let Inst{13} = ae_dr_to_dr_v{1}; +let Inst{14} = ae_dr_to_dr_v{2}; +let Inst{15} = ae_dr_to_dr_v{3}; +let Inst{8} = ae_dr_to_dr_v0{0}; +let Inst{9} = ae_dr_to_dr_v0{1}; +let Inst{10} = ae_dr_to_dr_v0{2}; +let Inst{11} = ae_dr_to_dr_v0{3}; +let Inst{4} = ae_opnd_tp7{0}; +let Inst{5} = ae_opnd_tp7{1}; +let Inst{6} = ae_opnd_tp7{2}; +let Inst{7} = ae_opnd_tp7{3}; +} + + + +def AE_SEXT32 : AE_SEXT32_X24<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_sext32 AE_DR:$ae_dr_to_dr_v0, timm:$ae_opnd_tp7))]>; + +class AE_SEXT32X2D16_10_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_to_dr_v), (ins AE_DR:$ae_to_dr_v0), "ae_sext32x2d16.10 $ae_to_dr_v, $ae_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_to_dr_v; +bits<4> ae_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{7} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{46} = 1; +let Inst{47} = 1; +//operands +let Inst{12} = ae_to_dr_v{0}; +let Inst{13} = ae_to_dr_v{1}; +let Inst{14} = ae_to_dr_v{2}; +let Inst{15} = ae_to_dr_v{3}; +let Inst{8} = ae_to_dr_v0{0}; +let Inst{9} = ae_to_dr_v0{1}; +let Inst{10} = ae_to_dr_v0{2}; +let Inst{11} = ae_to_dr_v0{3}; +} + + + +def AE_SEXT32X2D16_10 : AE_SEXT32X2D16_10_AE_FORMAT<[(set AE_DR:$ae_to_dr_v, (int_xtensa_ae_sext32x2d16_10 AE_DR:$ae_to_dr_v0))]>; + +class AE_SEXT32X2D16_32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_to_dr_v), (ins AE_DR:$ae_to_dr_v0), "ae_sext32x2d16.32 $ae_to_dr_v, $ae_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_to_dr_v; +bits<4> ae_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +//operands +let Inst{12} = ae_to_dr_v{0}; +let Inst{13} = ae_to_dr_v{1}; +let Inst{14} = ae_to_dr_v{2}; +let Inst{15} = ae_to_dr_v{3}; +let Inst{8} = ae_to_dr_v0{0}; +let Inst{9} = ae_to_dr_v0{1}; +let Inst{10} = ae_to_dr_v0{2}; +let Inst{11} = ae_to_dr_v0{3}; +} + + + +def AE_SEXT32X2D16_32 : AE_SEXT32X2D16_32_X24<[(set AE_DR:$ae_to_dr_v, (int_xtensa_ae_sext32x2d16_32 AE_DR:$ae_to_dr_v0))]>; + +class AE_SHA32_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins AR:$ars), "ae_sha32 $arr, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SHA32 : AE_SHA32_X24<[(set AR:$arr, (int_xtensa_ae_sha32 AR:$ars))]>; + +class AE_SHORTSWAP_AE_FORMAT1 pattern> + : XtensaInst64<(outs AE_DR:$ae_to_dr_v), (ins AE_DR:$ae_to_dr_v0), "ae_shortswap $ae_to_dr_v, $ae_to_dr_v0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_to_dr_v; +bits<4> ae_to_dr_v0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +let Inst{63} = 1; +//opcode +let Inst{36} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{56} = 1; +let Inst{59} = 1; +let Inst{62} = 1; +//operands +let Inst{20} = ae_to_dr_v{0}; +let Inst{21} = ae_to_dr_v{1}; +let Inst{22} = ae_to_dr_v{2}; +let Inst{23} = ae_to_dr_v{3}; +let Inst{28} = ae_to_dr_v0{0}; +let Inst{29} = ae_to_dr_v0{1}; +let Inst{30} = ae_to_dr_v0{2}; +let Inst{31} = ae_to_dr_v0{3}; +} + + + +def AE_SHORTSWAP : AE_SHORTSWAP_AE_FORMAT1<[(set AE_DR:$ae_to_dr_v, (int_xtensa_ae_shortswap AE_DR:$ae_to_dr_v0))]>; + +class AE_SLAA16S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_slaa16s $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SLAA16S : AE_SLAA16S_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slaa16s AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SLAA32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_slaa32 $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SLAA32 : AE_SLAA32_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slaa32 AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SLAA32S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_slaa32s $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SLAA32S : AE_SLAA32S_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slaa32s AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SLAA64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_slaa64 $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SLAA64 : AE_SLAA64_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slaa64 AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SLAA64S_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_slaa64s $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{12} = 1; +let Inst{15} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SLAA64S : AE_SLAA64S_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slaa64s AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SLAAQ56_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_slaaq56 $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SLAAQ56 : AE_SLAAQ56_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slaaq56 AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SLAI16S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm4:$ae_osa16), "ae_slai16s $ae_shift_d, $ae_shift_d0, $ae_osa16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ae_osa16; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +let Inst{36} = ae_osa16{0}; +let Inst{37} = ae_osa16{1}; +let Inst{38} = ae_osa16{2}; +let Inst{39} = ae_osa16{3}; +} + + + +def AE_SLAI16S : AE_SLAI16S_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slai16s AE_DR:$ae_shift_d0, timm:$ae_osa16))]>; + +class AE_SLAI24_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_slai24 $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa32{0}; +let Inst{9} = ae_osa32{1}; +let Inst{10} = ae_osa32{2}; +let Inst{11} = ae_osa32{3}; +let Inst{16} = ae_osa32{4}; +} + + + +def AE_SLAI24 : AE_SLAI24_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slai24 AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SLAI24S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_slai24s $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa32{0}; +let Inst{9} = ae_osa32{1}; +let Inst{10} = ae_osa32{2}; +let Inst{11} = ae_osa32{3}; +let Inst{16} = ae_osa32{4}; +} + + + +def AE_SLAI24S : AE_SLAI24S_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slai24s AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SLAI32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_slai32 $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa32{0}; +let Inst{9} = ae_osa32{1}; +let Inst{10} = ae_osa32{2}; +let Inst{11} = ae_osa32{3}; +let Inst{16} = ae_osa32{4}; +} + + + +def AE_SLAI32 : AE_SLAI32_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slai32 AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SLAI32S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_slai32s $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa32{0}; +let Inst{9} = ae_osa32{1}; +let Inst{10} = ae_osa32{2}; +let Inst{11} = ae_osa32{3}; +let Inst{16} = ae_osa32{4}; +} + + + +def AE_SLAI32S : AE_SLAI32S_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slai32s AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SLAI64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm6:$ae_osa64), "ae_slai64 $ae_shift_d, $ae_shift_d0, $ae_osa64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<6> ae_osa64; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{19} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa64{0}; +let Inst{9} = ae_osa64{1}; +let Inst{10} = ae_osa64{2}; +let Inst{11} = ae_osa64{3}; +let Inst{16} = ae_osa64{4}; +let Inst{17} = ae_osa64{5}; +} + + + +def AE_SLAI64 : AE_SLAI64_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slai64 AE_DR:$ae_shift_d0, timm:$ae_osa64))]>; + +class AE_SLAI64S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm6:$ae_osa64), "ae_slai64s $ae_shift_d, $ae_shift_d0, $ae_osa64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<6> ae_osa64; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{58} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +let Inst{36} = ae_osa64{0}; +let Inst{37} = ae_osa64{1}; +let Inst{38} = ae_osa64{2}; +let Inst{39} = ae_osa64{3}; +let Inst{56} = ae_osa64{4}; +let Inst{57} = ae_osa64{5}; +} + + + +def AE_SLAI64S : AE_SLAI64S_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slai64s AE_DR:$ae_shift_d0, timm:$ae_osa64))]>; + +class AE_SLAISQ56S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm6:$ae_osa64), "ae_slaisq56s $ae_shift_d, $ae_shift_d0, $ae_osa64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<6> ae_osa64; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa64{0}; +let Inst{9} = ae_osa64{1}; +let Inst{10} = ae_osa64{2}; +let Inst{11} = ae_osa64{3}; +let Inst{16} = ae_osa64{4}; +let Inst{17} = ae_osa64{5}; +} + + + +def AE_SLAISQ56S : AE_SLAISQ56S_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slaisq56s AE_DR:$ae_shift_d0, timm:$ae_osa64))]>; + +class AE_SLAS24_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_slas24 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{11} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +} + + + +def AE_SLAS24 : AE_SLAS24_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slas24 AE_DR:$ae_shift_d0))]>; + +class AE_SLAS24S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_slas24s $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SLAS24S : AE_SLAS24S_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slas24s AE_DR:$ae_shift_d0))]>; + +class AE_SLAS32_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_slas32 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{37} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SLAS32 : AE_SLAS32_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slas32 AE_DR:$ae_shift_d0))]>; + +class AE_SLAS32S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_slas32s $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{37} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SLAS32S : AE_SLAS32S_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slas32s AE_DR:$ae_shift_d0))]>; + +class AE_SLAS64_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_slas64 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{38} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SLAS64 : AE_SLAS64_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slas64 AE_DR:$ae_shift_d0))]>; + +class AE_SLAS64S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_slas64s $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +} + + + +def AE_SLAS64S : AE_SLAS64S_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slas64s AE_DR:$ae_shift_d0))]>; + +class AE_SLASQ56_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_slasq56 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +} + + + +def AE_SLASQ56 : AE_SLASQ56_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slasq56 AE_DR:$ae_shift_d0))]>; + +class AE_SLASSQ56S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_slassq56s $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SLASSQ56S : AE_SLASSQ56S_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_slassq56s AE_DR:$ae_shift_d0))]>; + +class AE_SRA64_32_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_sra64_32 $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{42} = 1; +let Inst{43} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRA64_32 : AE_SRA64_32_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sra64_32 AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRAA16RS_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_sraa16rs $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRAA16RS : AE_SRAA16RS_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sraa16rs AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRAA16S_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_sraa16s $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{14} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRAA16S : AE_SRAA16S_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sraa16s AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRAA32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_sraa32 $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRAA32 : AE_SRAA32_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sraa32 AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRAA32RS_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_sraa32rs $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRAA32RS : AE_SRAA32RS_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sraa32rs AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRAA32S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_sraa32s $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRAA32S : AE_SRAA32S_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sraa32s AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRAA64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_sraa64 $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRAA64 : AE_SRAA64_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sraa64 AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRAI16_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm4:$ae_osa16), "ae_srai16 $ae_shift_d, $ae_shift_d0, $ae_osa16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ae_osa16; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{56} = 1; +let Inst{57} = 1; +let Inst{58} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +let Inst{36} = ae_osa16{0}; +let Inst{37} = ae_osa16{1}; +let Inst{38} = ae_osa16{2}; +let Inst{39} = ae_osa16{3}; +} + + + +def AE_SRAI16 : AE_SRAI16_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srai16 AE_DR:$ae_shift_d0, timm:$ae_osa16))]>; + +class AE_SRAI16R_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm4:$ae_osa16), "ae_srai16r $ae_shift_d, $ae_shift_d0, $ae_osa16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ae_osa16; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +let Inst{36} = ae_osa16{0}; +let Inst{37} = ae_osa16{1}; +let Inst{38} = ae_osa16{2}; +let Inst{39} = ae_osa16{3}; +} + + + +def AE_SRAI16R : AE_SRAI16R_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srai16r AE_DR:$ae_shift_d0, timm:$ae_osa16))]>; + +class AE_SRAI24_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_srai24 $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa32{0}; +let Inst{9} = ae_osa32{1}; +let Inst{10} = ae_osa32{2}; +let Inst{11} = ae_osa32{3}; +let Inst{16} = ae_osa32{4}; +} + + + +def AE_SRAI24 : AE_SRAI24_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srai24 AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SRAI32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_srai32 $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa32{0}; +let Inst{9} = ae_osa32{1}; +let Inst{10} = ae_osa32{2}; +let Inst{11} = ae_osa32{3}; +let Inst{16} = ae_osa32{4}; +} + + + +def AE_SRAI32 : AE_SRAI32_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srai32 AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SRAI32R_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_srai32r $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{61} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +let Inst{36} = ae_osa32{0}; +let Inst{37} = ae_osa32{1}; +let Inst{38} = ae_osa32{2}; +let Inst{39} = ae_osa32{3}; +let Inst{56} = ae_osa32{4}; +} + + + +def AE_SRAI32R : AE_SRAI32R_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srai32r AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SRAI64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm6:$ae_osa64), "ae_srai64 $ae_shift_d, $ae_shift_d0, $ae_osa64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<6> ae_osa64; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa64{0}; +let Inst{9} = ae_osa64{1}; +let Inst{10} = ae_osa64{2}; +let Inst{11} = ae_osa64{3}; +let Inst{16} = ae_osa64{4}; +let Inst{17} = ae_osa64{5}; +} + + + +def AE_SRAI64 : AE_SRAI64_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srai64 AE_DR:$ae_shift_d0, timm:$ae_osa64))]>; + +class AE_SRAS24_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_sras24 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +} + + + +def AE_SRAS24 : AE_SRAS24_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sras24 AE_DR:$ae_shift_d0))]>; + +class AE_SRAS32_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_sras32 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{39} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SRAS32 : AE_SRAS32_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sras32 AE_DR:$ae_shift_d0))]>; + +class AE_SRAS64_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_sras64 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{37} = 1; +let Inst{39} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SRAS64 : AE_SRAS64_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_sras64 AE_DR:$ae_shift_d0))]>; + +class AE_SRLA32_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_srla32 $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRLA32 : AE_SRLA32_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srla32 AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRLA64_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AR:$ars), "ae_srla64 $ae_shift_d, $ae_shift_d0, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{12} = 1; +let Inst{40} = 1; +let Inst{43} = 1; +let Inst{44} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_SRLA64 : AE_SRLA64_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srla64 AE_DR:$ae_shift_d0, AR:$ars))]>; + +class AE_SRLI24_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_srli24 $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{57} = 1; +let Inst{61} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +let Inst{36} = ae_osa32{0}; +let Inst{37} = ae_osa32{1}; +let Inst{38} = ae_osa32{2}; +let Inst{39} = ae_osa32{3}; +let Inst{56} = ae_osa32{4}; +} + + + +def AE_SRLI24 : AE_SRLI24_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srli24 AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SRLI32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm5:$ae_osa32), "ae_srli32 $ae_shift_d, $ae_shift_d0, $ae_osa32", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<5> ae_osa32; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{8} = ae_osa32{0}; +let Inst{9} = ae_osa32{1}; +let Inst{10} = ae_osa32{2}; +let Inst{11} = ae_osa32{3}; +let Inst{16} = ae_osa32{4}; +} + + + +def AE_SRLI32 : AE_SRLI32_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srli32 AE_DR:$ae_shift_d0, timm:$ae_osa32))]>; + +class AE_SRLI64_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, uimm6:$ae_osa64), "ae_srli64 $ae_shift_d, $ae_shift_d0, $ae_osa64", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<6> ae_osa64; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{60} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +let Inst{36} = ae_osa64{0}; +let Inst{37} = ae_osa64{1}; +let Inst{38} = ae_osa64{2}; +let Inst{39} = ae_osa64{3}; +let Inst{56} = ae_osa64{4}; +let Inst{57} = ae_osa64{5}; +} + + + +def AE_SRLI64 : AE_SRLI64_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srli64 AE_DR:$ae_shift_d0, timm:$ae_osa64))]>; + +class AE_SRLS24_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_srls24 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SRLS24 : AE_SRLS24_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srls24 AE_DR:$ae_shift_d0))]>; + +class AE_SRLS32_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_srls32 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{36} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SRLS32 : AE_SRLS32_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srls32 AE_DR:$ae_shift_d0))]>; + +class AE_SRLS64_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0), "ae_srls64 $ae_shift_d, $ae_shift_d0", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{37} = 1; +let Inst{38} = 1; +let Inst{39} = 1; +let Inst{57} = 1; +let Inst{59} = 1; +let Inst{61} = 1; +let Inst{62} = 1; +let Inst{63} = 1; +//operands +let Inst{20} = ae_shift_d{0}; +let Inst{21} = ae_shift_d{1}; +let Inst{22} = ae_shift_d{2}; +let Inst{23} = ae_shift_d{3}; +let Inst{28} = ae_shift_d0{0}; +let Inst{29} = ae_shift_d0{1}; +let Inst{30} = ae_shift_d0{2}; +let Inst{31} = ae_shift_d0{3}; +} + + + +def AE_SRLS64 : AE_SRLS64_AE_FORMAT<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_srls64 AE_DR:$ae_shift_d0))]>; + +class AE_SUB16_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_sub16 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{51} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_SUB16 : AE_SUB16_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sub16 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SUB16S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_sub16s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_SUB16S : AE_SUB16S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sub16s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SUB24S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_sub24s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_SUB24S : AE_SUB24S_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sub24s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SUB32_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_sub32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_SUB32 : AE_SUB32_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sub32 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SUB32S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_sub32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_SUB32S : AE_SUB32S_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sub32s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SUB64_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_sub64 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{22} = 1; +//operands +let Inst{12} = ae_arth_v{0}; +let Inst{13} = ae_arth_v{1}; +let Inst{14} = ae_arth_v{2}; +let Inst{15} = ae_arth_v{3}; +let Inst{8} = ae_arth_v0{0}; +let Inst{9} = ae_arth_v0{1}; +let Inst{10} = ae_arth_v0{2}; +let Inst{11} = ae_arth_v0{3}; +let Inst{4} = ae_arth_v1{0}; +let Inst{5} = ae_arth_v1{1}; +let Inst{6} = ae_arth_v1{2}; +let Inst{7} = ae_arth_v1{3}; +} + + + +def AE_SUB64 : AE_SUB64_X24<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sub64 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SUB64S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_sub64s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{50} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_SUB64S : AE_SUB64S_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_sub64s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SUBADD32_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_subadd32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_SUBADD32 : AE_SUBADD32_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_subadd32 AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_SUBADD32S_AE_FORMAT pattern> + : XtensaInst64<(outs AE_DR:$ae_arth_v), (ins AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1), "ae_subadd32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_arth_v; +bits<4> ae_arth_v0; +bits<4> ae_arth_v1; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{0} = 1; +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{48} = 1; +let Inst{49} = 1; +let Inst{50} = 1; +let Inst{52} = 1; +let Inst{53} = 1; +let Inst{54} = 1; +let Inst{55} = 1; +//operands +let Inst{16} = ae_arth_v{0}; +let Inst{17} = ae_arth_v{1}; +let Inst{18} = ae_arth_v{2}; +let Inst{19} = ae_arth_v{3}; +let Inst{24} = ae_arth_v0{0}; +let Inst{25} = ae_arth_v0{1}; +let Inst{26} = ae_arth_v0{2}; +let Inst{27} = ae_arth_v0{3}; +let Inst{32} = ae_arth_v1{0}; +let Inst{33} = ae_arth_v1{1}; +let Inst{34} = ae_arth_v1{2}; +let Inst{35} = ae_arth_v1{3}; +} + + + +def AE_SUBADD32S : AE_SUBADD32S_AE_FORMAT<[(set AE_DR:$ae_arth_v, (int_xtensa_ae_subadd32s AE_DR:$ae_arth_v0, AE_DR:$ae_arth_v1))]>; + +class AE_TRUNCA32F64S_L_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AE_DR:$ae_shift_sd, AR:$ars), "ae_trunca32f64s.l $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ae_shift_sd; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{41} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{12} = ae_shift_sd{0}; +let Inst{13} = ae_shift_sd{1}; +let Inst{14} = ae_shift_sd{2}; +let Inst{15} = ae_shift_sd{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_TRUNCA32F64S_L : AE_TRUNCA32F64S_L_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_trunca32f64s_l AE_DR:$ae_shift_d0, AE_DR:$ae_shift_sd, AR:$ars))]>; + +class AE_TRUNCA32X2F64S_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AE_DR:$ae_shift_sd, AR:$ars), "ae_trunca32x2f64s $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ae_shift_sd; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = ae_shift_d{0}; +let Inst{13} = ae_shift_d{1}; +let Inst{14} = ae_shift_d{2}; +let Inst{15} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{16} = ae_shift_sd{0}; +let Inst{17} = ae_shift_sd{1}; +let Inst{18} = ae_shift_sd{2}; +let Inst{19} = ae_shift_sd{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_TRUNCA32X2F64S : AE_TRUNCA32X2F64S_X24<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_trunca32x2f64s AE_DR:$ae_shift_d0, AE_DR:$ae_shift_sd, AR:$ars))]>; + +class AE_TRUNCI32F64S_L_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AE_DR:$ae_shift_sd, uimm4:$ae_osa16), "ae_trunci32f64s.l $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ae_osa16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ae_shift_sd; +bits<4> ae_osa16; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{40} = 1; +let Inst{41} = 1; +let Inst{42} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{12} = ae_shift_sd{0}; +let Inst{13} = ae_shift_sd{1}; +let Inst{14} = ae_shift_sd{2}; +let Inst{15} = ae_shift_sd{3}; +let Inst{8} = ae_osa16{0}; +let Inst{9} = ae_osa16{1}; +let Inst{10} = ae_osa16{2}; +let Inst{11} = ae_osa16{3}; +} + + + +def AE_TRUNCI32F64S_L : AE_TRUNCI32F64S_L_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_trunci32f64s_l AE_DR:$ae_shift_d0, AE_DR:$ae_shift_sd, timm:$ae_osa16))]>; + +class AE_TRUNCI32X2F64S_AE_FORMAT2 pattern> + : XtensaInst64<(outs AE_DR:$ae_shift_d), (ins AE_DR:$ae_shift_d0, AE_DR:$ae_shift_sd, uimm4:$ae_osa16), "ae_trunci32x2f64s $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ae_osa16", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_shift_d; +bits<4> ae_shift_d0; +bits<4> ae_shift_sd; +bits<4> ae_osa16; + + +let DecoderNamespace = "HIFI3"; + +//format +let Inst{1} = 1; +let Inst{2} = 1; +let Inst{3} = 1; +//opcode +let Inst{43} = 1; +let Inst{55} = 1; +//operands +let Inst{28} = ae_shift_d{0}; +let Inst{29} = ae_shift_d{1}; +let Inst{30} = ae_shift_d{2}; +let Inst{31} = ae_shift_d{3}; +let Inst{4} = ae_shift_d0{0}; +let Inst{5} = ae_shift_d0{1}; +let Inst{6} = ae_shift_d0{2}; +let Inst{7} = ae_shift_d0{3}; +let Inst{12} = ae_shift_sd{0}; +let Inst{13} = ae_shift_sd{1}; +let Inst{14} = ae_shift_sd{2}; +let Inst{15} = ae_shift_sd{3}; +let Inst{8} = ae_osa16{0}; +let Inst{9} = ae_osa16{1}; +let Inst{10} = ae_osa16{2}; +let Inst{11} = ae_osa16{3}; +} + + + +def AE_TRUNCI32X2F64S : AE_TRUNCI32X2F64S_AE_FORMAT2<[(set AE_DR:$ae_shift_d, (int_xtensa_ae_trunci32x2f64s AE_DR:$ae_shift_d0, AE_DR:$ae_shift_sd, timm:$ae_osa16))]>; + +class AE_VLDL16C_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_vldl16c $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLDL16C : AE_VLDL16C_X24<[(set AR:$ars_out, (int_xtensa_ae_vldl16c AR:$ars))]>; + +class AE_VLDL16C_IC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_vldl16c.ic $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLDL16C_IC : AE_VLDL16C_IC_X24<[(set AR:$ars_out, (int_xtensa_ae_vldl16c_ic AR:$ars))]>; + +class AE_VLDL16C_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_vldl16c.ip $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{7} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLDL16C_IP : AE_VLDL16C_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_vldl16c_ip AR:$ars))]>; + +class AE_VLDL16T_X24 pattern> + : XtensaAEInst24<(outs BR:$br, AR:$art), (ins AR:$ars), "ae_vldl16t $br, $art, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> br; +bits<4> art; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = br{0}; +let Inst{13} = br{1}; +let Inst{14} = br{2}; +let Inst{15} = br{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLDL16T : AE_VLDL16T_X24<[]>; + +class AE_VLDL32T_X24 pattern> + : XtensaAEInst24<(outs BR:$br, AR:$art), (ins AR:$ars), "ae_vldl32t $br, $art, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> br; +bits<4> art; +bits<4> ars; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +//operands +let Inst{12} = br{0}; +let Inst{13} = br{1}; +let Inst{14} = br{2}; +let Inst{15} = br{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLDL32T : AE_VLDL32T_X24<[]>; + +class AE_VLDSHT_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "ae_vldsht $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{12} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def AE_VLDSHT : AE_VLDSHT_X24<[(int_xtensa_ae_vldsht AR:$art)]>; + +class AE_VLEL16T_X24 pattern> + : XtensaAEInst24<(outs BR:$br, AR:$art_out), (ins AR:$art, AR:$ars), "ae_vlel16t $br, $art, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> br; +bits<4> art; +bits<4> ars; +let Constraints = "$art = $art_out,@earlyclobber $art_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{16} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = br{0}; +let Inst{13} = br{1}; +let Inst{14} = br{2}; +let Inst{15} = br{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLEL16T : AE_VLEL16T_X24<[]>; + +class AE_VLEL32T_X24 pattern> + : XtensaAEInst24<(outs BR:$br, AR:$art_out), (ins AR:$art, AR:$ars), "ae_vlel32t $br, $art, $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> br; +bits<4> art; +bits<4> ars; +let Constraints = "$art = $art_out,@earlyclobber $art_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{20} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = br{0}; +let Inst{13} = br{1}; +let Inst{14} = br{2}; +let Inst{15} = br{3}; +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLEL32T : AE_VLEL32T_X24<[]>; + +class AE_VLES16C_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_vles16c $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLES16C : AE_VLES16C_X24<[(set AR:$ars_out, (int_xtensa_ae_vles16c AR:$ars))]>; + +class AE_VLES16C_IC_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_vles16c.ic $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{5} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLES16C_IC : AE_VLES16C_IC_X24<[(set AR:$ars_out, (int_xtensa_ae_vles16c_ic AR:$ars))]>; + +class AE_VLES16C_IP_X24 pattern> + : XtensaAEInst24<(outs AR:$ars_out), (ins AR:$ars), "ae_vles16c.ip $ars", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ars; +let Constraints = "$ars = $ars_out,@earlyclobber $ars_out"; + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{6} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{8} = ars{0}; +let Inst{9} = ars{1}; +let Inst{10} = ars{2}; +let Inst{11} = ars{3}; +} + + + +def AE_VLES16C_IP : AE_VLES16C_IP_X24<[(set AR:$ars_out, (int_xtensa_ae_vles16c_ip AR:$ars))]>; + +class AE_XOR_X24 pattern> + : XtensaAEInst24<(outs AE_DR:$ae_dr_to_dr_v), (ins AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1), "ae_xor $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> ae_dr_to_dr_v; +bits<4> ae_dr_to_dr_v0; +bits<4> ae_dr_to_dr_v1; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{19} = 1; +let Inst{20} = 1; +//operands +let Inst{12} = ae_dr_to_dr_v{0}; +let Inst{13} = ae_dr_to_dr_v{1}; +let Inst{14} = ae_dr_to_dr_v{2}; +let Inst{15} = ae_dr_to_dr_v{3}; +let Inst{8} = ae_dr_to_dr_v0{0}; +let Inst{9} = ae_dr_to_dr_v0{1}; +let Inst{10} = ae_dr_to_dr_v0{2}; +let Inst{11} = ae_dr_to_dr_v0{3}; +let Inst{4} = ae_dr_to_dr_v1{0}; +let Inst{5} = ae_dr_to_dr_v1{1}; +let Inst{6} = ae_dr_to_dr_v1{2}; +let Inst{7} = ae_dr_to_dr_v1{3}; +} + + + +def AE_XOR : AE_XOR_X24<[(set AE_DR:$ae_dr_to_dr_v, (int_xtensa_ae_xor AE_DR:$ae_dr_to_dr_v0, AE_DR:$ae_dr_to_dr_v1))]>; + +class AE_ZALIGN64_X24 pattern> + : XtensaAEInst24<(outs AE_VALIGN:$ae_uu_uu), (ins ), "ae_zalign64 $ae_uu_uu", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<2> ae_uu_uu; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{12} = 1; +let Inst{19} = 1; +let Inst{21} = 1; +//operands +let Inst{6} = ae_uu_uu{0}; +let Inst{7} = ae_uu_uu{1}; +} + + + +def AE_ZALIGN64 : AE_ZALIGN64_X24<[(set AE_VALIGN:$ae_uu_uu, (int_xtensa_ae_zalign64 ))]>; + +class RUR_AE_BITHEAD_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins ), "rur.ae_bithead $arr", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{4} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +} + + + +def RUR_AE_BITHEAD : RUR_AE_BITHEAD_X24<[(set AR:$arr, (int_xtensa_rur_ae_bithead ))]>; + +class RUR_AE_BITPTR_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_bitptr $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_BITPTR : RUR_AE_BITPTR_X24<[(set AR:$art, (int_xtensa_rur_ae_bitptr ))]>; + +class RUR_AE_BITSUSED_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_bitsused $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_BITSUSED : RUR_AE_BITSUSED_X24<[(set AR:$art, (int_xtensa_rur_ae_bitsused ))]>; + +class RUR_AE_CBEGIN0_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins ), "rur.ae_cbegin0 $arr", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +} + + + +def RUR_AE_CBEGIN0 : RUR_AE_CBEGIN0_X24<[(set AR:$arr, (int_xtensa_rur_ae_cbegin0 ))]>; + +class RUR_AE_CEND0_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins ), "rur.ae_cend0 $arr", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{6} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +} + + + +def RUR_AE_CEND0 : RUR_AE_CEND0_X24<[(set AR:$arr, (int_xtensa_rur_ae_cend0 ))]>; + +class RUR_AE_CW_SD_NO_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins ), "rur.ae_cw_sd_no $arr", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{4} = 1; +let Inst{5} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +} + + + +def RUR_AE_CW_SD_NO : RUR_AE_CW_SD_NO_X24<[(set AR:$arr, (int_xtensa_rur_ae_cw_sd_no ))]>; + +class RUR_AE_CWRAP_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_cwrap $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{11} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_CWRAP : RUR_AE_CWRAP_X24<[(set AR:$art, (int_xtensa_rur_ae_cwrap ))]>; + +class RUR_AE_FIRST_TS_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_first_ts $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{10} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_FIRST_TS : RUR_AE_FIRST_TS_X24<[(set AR:$art, (int_xtensa_rur_ae_first_ts ))]>; + +class RUR_AE_NEXTOFFSET_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_nextoffset $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_NEXTOFFSET : RUR_AE_NEXTOFFSET_X24<[(set AR:$art, (int_xtensa_rur_ae_nextoffset ))]>; + +class RUR_AE_OVERFLOW_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_overflow $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{11} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_OVERFLOW : RUR_AE_OVERFLOW_X24<[(set AR:$art, (int_xtensa_rur_ae_overflow ))]>; + +class RUR_AE_OVF_SAR_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins ), "rur.ae_ovf_sar $arr", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +} + + + +def RUR_AE_OVF_SAR : RUR_AE_OVF_SAR_X24<[(set AR:$arr, (int_xtensa_rur_ae_ovf_sar ))]>; + +class RUR_AE_SAR_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_sar $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_SAR : RUR_AE_SAR_X24<[(set AR:$art, (int_xtensa_rur_ae_sar ))]>; + +class RUR_AE_SEARCHDONE_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_searchdone $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{11} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_SEARCHDONE : RUR_AE_SEARCHDONE_X24<[(set AR:$art, (int_xtensa_rur_ae_searchdone ))]>; + +class RUR_AE_TABLESIZE_X24 pattern> + : XtensaAEInst24<(outs AR:$art), (ins ), "rur.ae_tablesize $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{9} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def RUR_AE_TABLESIZE : RUR_AE_TABLESIZE_X24<[(set AR:$art, (int_xtensa_rur_ae_tablesize ))]>; + +class RUR_AE_TS_FTS_BU_BP_X24 pattern> + : XtensaAEInst24<(outs AR:$arr), (ins ), "rur.ae_ts_fts_bu_bp $arr", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> arr; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{5} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{12} = arr{0}; +let Inst{13} = arr{1}; +let Inst{14} = arr{2}; +let Inst{15} = arr{3}; +} + + + +def RUR_AE_TS_FTS_BU_BP : RUR_AE_TS_FTS_BU_BP_X24<[(set AR:$arr, (int_xtensa_rur_ae_ts_fts_bu_bp ))]>; + +class WUR_AE_BITHEAD_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_bithead $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{8} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_BITHEAD : WUR_AE_BITHEAD_X24<[(int_xtensa_wur_ae_bithead AR:$art)]>; + +class WUR_AE_BITPTR_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_bitptr $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_BITPTR : WUR_AE_BITPTR_X24<[(int_xtensa_wur_ae_bitptr AR:$art)]>; + +class WUR_AE_BITSUSED_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_bitsused $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_BITSUSED : WUR_AE_BITSUSED_X24<[(int_xtensa_wur_ae_bitsused AR:$art)]>; + +class WUR_AE_CBEGIN0_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_cbegin0 $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_CBEGIN0 : WUR_AE_CBEGIN0_X24<[(int_xtensa_wur_ae_cbegin0 AR:$art)]>; + +class WUR_AE_CEND0_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_cend0 $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_CEND0 : WUR_AE_CEND0_X24<[(int_xtensa_wur_ae_cend0 AR:$art)]>; + +class WUR_AE_CW_SD_NO_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_cw_sd_no $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_CW_SD_NO : WUR_AE_CW_SD_NO_X24<[(int_xtensa_wur_ae_cw_sd_no AR:$art)]>; + +class WUR_AE_CWRAP_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_cwrap $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{11} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_CWRAP : WUR_AE_CWRAP_X24<[(int_xtensa_wur_ae_cwrap AR:$art)]>; + +class WUR_AE_FIRST_TS_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_first_ts $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{10} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_FIRST_TS : WUR_AE_FIRST_TS_X24<[(int_xtensa_wur_ae_first_ts AR:$art)]>; + +class WUR_AE_NEXTOFFSET_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_nextoffset $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{10} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_NEXTOFFSET : WUR_AE_NEXTOFFSET_X24<[(int_xtensa_wur_ae_nextoffset AR:$art)]>; + +class WUR_AE_OVERFLOW_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_overflow $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{11} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_OVERFLOW : WUR_AE_OVERFLOW_X24<[(int_xtensa_wur_ae_overflow AR:$art)]>; + +class WUR_AE_OVF_SAR_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_ovf_sar $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_OVF_SAR : WUR_AE_OVF_SAR_X24<[(int_xtensa_wur_ae_ovf_sar AR:$art)]>; + +class WUR_AE_SAR_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_sar $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{10} = 1; +let Inst{11} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_SAR : WUR_AE_SAR_X24<[(int_xtensa_wur_ae_sar AR:$art)]>; + +class WUR_AE_SEARCHDONE_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_searchdone $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{11} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_SEARCHDONE : WUR_AE_SEARCHDONE_X24<[(int_xtensa_wur_ae_searchdone AR:$art)]>; + +class WUR_AE_TABLESIZE_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_tablesize $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{2} = 1; +let Inst{8} = 1; +let Inst{9} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{18} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_TABLESIZE : WUR_AE_TABLESIZE_X24<[(int_xtensa_wur_ae_tablesize AR:$art)]>; + +class WUR_AE_TS_FTS_BU_BP_X24 pattern> + : XtensaAEInst24<(outs ), (ins AR:$art), "wur.ae_ts_fts_bu_bp $art", pattern>, + Requires<[HasHIFI3]> +{ +//operand decl +bits<4> art; + + +let DecoderNamespace = "HIFI3"; + +//format + +//opcode +let Inst{9} = 1; +let Inst{12} = 1; +let Inst{13} = 1; +let Inst{14} = 1; +let Inst{15} = 1; +let Inst{16} = 1; +let Inst{17} = 1; +let Inst{20} = 1; +let Inst{21} = 1; +let Inst{22} = 1; +let Inst{23} = 1; +//operands +let Inst{4} = art{0}; +let Inst{5} = art{1}; +let Inst{6} = art{2}; +let Inst{7} = art{3}; +} + + + +def WUR_AE_TS_FTS_BU_BP : WUR_AE_TS_FTS_BU_BP_X24<[(int_xtensa_wur_ae_ts_fts_bu_bp AR:$art)]>; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 935ea605e3eb48..f37a65abaf1814 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -2007,3 +2007,8 @@ let Predicates = [HasSingleFloat] in { //===----------------------------------------------------------------------===// include "XtensaDSPInstrInfo.td" +//===----------------------------------------------------------------------===// +// HiFi3 Instructions +//===----------------------------------------------------------------------===// +include "XtensaHIFIInstrFormats.td" +include "XtensaHIFIInstrInfo.td" diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index ad22bac40ea764..3d10410a775996 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -21,6 +21,26 @@ class Immediate let ParserMatchClass = !cast(asmop); } +class ImmediateRanged : + Immediate= " # Low # " && Imm <= " # High # " && (Imm % " # Step # " ) == 0;", + asmop> { + let PrintMethod = "printImmOperand<" # Low #"," # High # "," # Step # ">"; + } + +class ImmRangedAsmOperand : + ImmAsmOperand { + let PredicateMethod = "isImmInRange<" # Low #"," # High # "," # Step # ">"; +} + +multiclass ImmRangeDecl { + + def _AsmOperand : ImmRangedAsmOperand; + def NAME : ImmediateRanged; + +} + + // imm8 predicate - Immediate in the range [-128,127] def Imm8_AsmOperand : ImmAsmOperand<"Imm8">; def imm8 : Immediate= -128 && Imm <= 127; }], "Imm8_AsmOperand"> { @@ -107,6 +127,14 @@ def shimm1_31 : Immediate= 1 && Imm <= 31; }], "Shimm1_31_A let DecoderMethod = "decodeShimm1_31Operand"; } +defm imm32n_28: ImmRangeDecl<-32, 28, 4>; +defm imm64n_56: ImmRangeDecl<-64, 56, 8>; +defm imm0_56: ImmRangeDecl<0, 56, 8>; +defm imm16n_14: ImmRangeDecl<-16, 14, 2>; +defm imm16n_47: ImmRangeDecl<-16, 47, 1>; +defm uimm2: ImmRangeDecl<0, 3, 1>; +defm uimm6: ImmRangeDecl<0, 63, 1>; + // Memory offset 0..255 for 8-bit memory accesses def Offset8m8_AsmOperand : ImmAsmOperand<"Offset8m8">; def offset8m8 : Immediate Date: Thu, 29 Jun 2023 13:10:20 +0000 Subject: [PATCH 212/261] [Xtensa] Add support for boolean vectors Xtensa architecture uses v2i1 (BR2 reg class) and v4i1 (BR4 reg class) boolean vectors as arguments for HIFI instructions: - vector compare, e.g.: AE_EQ16X4 - vector conditional move, e.g: AE_MOVT16X4 --- llvm/lib/Target/Xtensa/XtensaCallingConv.td | 2 + llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 148 ++++++++++++++++-- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 3 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 41 ++++- llvm/lib/Target/Xtensa/XtensaOperators.td | 3 + .../CodeGen/Xtensa/xtensa-xtbool-spill.ll | 4 +- 6 files changed, 184 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaCallingConv.td b/llvm/lib/Target/Xtensa/XtensaCallingConv.td index 6c4feff9c108b7..f06f0995d4581e 100644 --- a/llvm/lib/Target/Xtensa/XtensaCallingConv.td +++ b/llvm/lib/Target/Xtensa/XtensaCallingConv.td @@ -23,6 +23,8 @@ class CCIfFeature: def RetCC_Xtensa : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfFeature<"Boolean",CCIfType<[v1i1], CCAssignToReg<[B0]>>>, + CCIfFeature<"Boolean",CCIfType<[v2i1], CCAssignToReg<[B0_B1]>>>, + CCIfFeature<"Boolean",CCIfType<[v4i1], CCAssignToReg<[B0_B1_B2_B3]>>>, CCIfType<[f32], CCBitConvertToType>, //First two return values go in a2, a3, a4, a5 diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 304ad799703ba3..c4e34d12aa9b10 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -66,14 +66,21 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, if (Subtarget.hasBoolean()) { addRegisterClass(MVT::v1i1, &Xtensa::BRRegClass); + addRegisterClass(MVT::v2i1, &Xtensa::BR2RegClass); + addRegisterClass(MVT::v4i1, &Xtensa::BR4RegClass); + setOperationAction(ISD::Constant, MVT::v2i1, Expand); setOperationAction(ISD::Constant, MVT::v1i1, Expand); - for (MVT VT : MVT::integer_valuetypes()) { - setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v1i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v1i1, Promote); - setLoadExtAction(ISD::EXTLOAD, VT, MVT::v1i1, Promote); - } - } + setTargetDAGCombine(ISD::STORE); + setTargetDAGCombine(ISD::BITCAST); + setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); + setOperationAction(ISD::STORE, MVT::v1i1, Legal); + setOperationAction(ISD::STORE, MVT::v2i1, Legal); + setOperationAction(ISD::STORE, MVT::v4i1, Legal); + setOperationAction(ISD::LOAD, MVT::v1i1, Legal); + setOperationAction(ISD::LOAD, MVT::v2i1, Legal); + setOperationAction(ISD::LOAD, MVT::v4i1, Legal); + } // Set up special registers. setStackPointerRegisterToSaveRestore(Xtensa::SP); @@ -105,7 +112,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, // Used by legalize types to correctly generate the setcc result. // AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); - setOperationPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); + if (!Subtarget.hasBoolean()) + setOperationPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); setOperationPromotedToType(ISD::BR_CC, MVT::i1, MVT::i32); setOperationAction(ISD::BR_CC, MVT::i32, Legal); @@ -753,6 +761,91 @@ static SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG, LHS, RHS, Dest); } +static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const XtensaSubtarget &Subtarget) { + // (vNi1 (bitcast (iN (trunc i32)))) -> (vNi1 (xtensa_bitcast i32)) + SDLoc DL(N); + SDValue Op = N->getOperand(0); + + if (N->getOpcode() != ISD::BITCAST || Op.getOpcode() != ISD::TRUNCATE) + return SDValue(); + + SDValue Int = Op.getOperand(0); + llvm::EVT BoolVT = N->getValueType(0); + + if (!BoolVT.isVector() || BoolVT.getVectorElementType() != MVT::i1 || + Int.getValueType() != MVT::i32) + return SDValue(); + + SDValue Trunc = DAG.getNode(XtensaISD::TRUNC, DL, BoolVT, Int); + + return Trunc; +} + +static SDValue +PerformExtractSubvectorCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const XtensaSubtarget &Subtarget) { + // (vNi1 (extract_subvector (v8i1 (load x))) -> (vNi1 (load x)) + SDLoc DL(N); + SDValue Load = N->getOperand(0); + + if (N->getOpcode() != ISD::EXTRACT_SUBVECTOR) + return SDValue(); + + EVT LoadVT = Load.getValueType(); + EVT BoolVT = N->getValueType(0); + + if (!BoolVT.isVector() || BoolVT.getVectorElementType() != MVT::i1) + return SDValue(); + + if (Load.getOpcode() != ISD::LOAD) + return SDValue(); + + LoadSDNode *LdNode = cast(Load.getNode()); + + if (!LoadVT.isVector() || LoadVT.getVectorElementType() != MVT::i1) + return SDValue(); + + SDValue NewLoad = + DAG.getLoad(BoolVT, DL, LdNode->getChain(), LdNode->getBasePtr(), + LdNode->getPointerInfo(), LdNode->getOriginalAlign(), + LdNode->getMemOperand()->getFlags()); + + return NewLoad; +} +static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const XtensaSubtarget &Subtarget) { + // (store (v8i1 (concat_vector (vNi1 elt) undef )) addr off) + // -> (store (vNi1 elt) addr off) + SDLoc DL(N); + + if (N->getOpcode() != ISD::STORE) + return SDValue(); + + StoreSDNode *StNode = cast(N); + + SDValue Concat = N->getOperand(1); + EVT BoolVT = Concat.getValueType(); + + if ((Concat.getOpcode() != ISD::CONCAT_VECTORS) || !BoolVT.isVector() || + (BoolVT.getVectorElementType() != MVT::i1)) + return SDValue(); + + SDValue Val = Concat.getNode()->getOperand(0); + EVT ValVT = Val.getValueType(); + + if (!ValVT.isVector() || ValVT.getVectorElementType() != MVT::i1 || + ValVT.getSizeInBits() > 8) { + return SDValue(); + } + + return DAG.getStore(StNode->getChain(), DL, Val, StNode->getBasePtr(), + StNode->getMemOperand()); +} + SDValue XtensaTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; @@ -769,6 +862,12 @@ SDValue XtensaTargetLowering::PerformDAGCombine(SDNode *N, return PerformHWLoopCombine(N, DAG, DCI, Subtarget); case ISD::BRCOND: return PerformBRCONDCombine(N, DAG, DCI, Subtarget); + case ISD::BITCAST: + return PerformBITCASTCombine(N, DAG, DCI, Subtarget); + case ISD::EXTRACT_SUBVECTOR: + return PerformExtractSubvectorCombine(N, DAG, DCI, Subtarget); + case ISD::STORE: + return PerformSTORECombine(N, DAG, DCI, Subtarget); } return SDValue(); @@ -791,6 +890,12 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, Xtensa::B8, Xtensa::B9, Xtensa::B10, Xtensa::B11, Xtensa::B12, Xtensa::B13, Xtensa::B14, Xtensa::B15}; + ArrayRef BR2Regs(Xtensa::BR2RegClass.begin(), + Xtensa::BR2RegClass.end()); + + ArrayRef BR4Regs(Xtensa::BR4RegClass.begin(), + Xtensa::BR4RegClass.end()); + if (ArgFlags.isByVal()) { Align ByValAlign = ArgFlags.getNonZeroByValAlign(); unsigned ByValSize = ArgFlags.getByValSize(); @@ -848,6 +953,11 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, LocVT = MVT::i32; } else if (ValVT == MVT::v1i1) { Reg = State.AllocateReg(BoolRegs); + } else if (ValVT == MVT::v2i1) { + Reg = State.AllocateReg(BR2Regs); + LocVT = ValVT; + } else if (ValVT == MVT::v4i1) { + Reg = State.AllocateReg(BR4Regs); LocVT = ValVT; } else llvm_unreachable("Cannot handle this ValVT."); @@ -945,6 +1055,10 @@ SDValue XtensaTargetLowering::LowerFormalArguments( RC = &Xtensa::ARRegClass; } else if (RegVT == MVT::v1i1) { RC = &Xtensa::BRRegClass; + } else if (RegVT == MVT::v2i1) { + RC = &Xtensa::BR2RegClass; + } else if (RegVT == MVT::v4i1) { + RC = &Xtensa::BR4RegClass; } else llvm_unreachable("RegVT not supported by FormalArguments Lowering"); @@ -3432,7 +3546,8 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( } return MBB; } - case Xtensa::MOVBA_P: { + case Xtensa::MOVBA_P: + case Xtensa::MOVBA2_P: { const TargetRegisterClass *AR = getRegClassFor(MVT::i32); Register Dst1 = MRI.createVirtualRegister(AR); @@ -3443,8 +3558,21 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( /* MOVBA_P2 Breg, Dst1, Dest2, Src */ - - BuildMI(*MBB, MI, DL, TII.get(Xtensa::MOVBA_P2), Breg.getReg()) + unsigned TargetOpcode; + switch (MI.getOpcode()) { + case Xtensa::MOVBA_P: + TargetOpcode = Xtensa::MOVBA_P2; + break; + case Xtensa::MOVBA2_P: + TargetOpcode = Xtensa::MOVBA2_P2; + break; + case Xtensa::MOVBA4_P: + TargetOpcode = Xtensa::MOVBA4_P2; + break; + default: + llvm_unreachable("Unknown opcode"); + } + BuildMI(*MBB, MI, DL, TII.get(TargetOpcode), Breg.getReg()) .addReg(Dst1, RegState::Define | RegState::EarlyClobber) .addReg(Dst2, RegState::Define | RegState::EarlyClobber) .addReg(Src.getReg()); diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 3ca6fad904b802..c10a4d93dcac9c 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -91,7 +91,8 @@ enum { SRL, SRC, SSL, - SSR + SSR, + TRUNC }; } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index f37a65abaf1814..6ffb6f917faa33 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1003,22 +1003,57 @@ let Predicates = [HasBoolean] in { "!movba $r, $s", []> { let usesCustomInserter = 1; let Defs = [BREG]; - //let Uses = [BREG]; } + def MOVBA2_P2: Pseudo<(outs BR2:$r, AR:$x, AR:$y), (ins AR:$s), + "!movba $r, $x, $y, $s", []> { + let Defs = [BREG]; + } + + def MOVBA2_P: Pseudo<(outs BR2:$r), (ins AR:$s), + "!movba2 $r, $s", []> { + let usesCustomInserter = 1; + let Defs = [BREG]; + } + + def MOVBA4_P2: Pseudo<(outs BR4:$r, AR:$x, AR:$y), (ins AR:$s), + "!movba4 $r, $x, $y, $s", []> { + let Defs = [BREG]; + } + + def MOVBA4_P: Pseudo<(outs BR4:$r), (ins AR:$s), + "!movba4 $r, $s", []> { + let usesCustomInserter = 1; + let Defs = [BREG]; + } + def EXTUI_BR_P: Pseudo<(outs AR:$r), (ins AR:$s, BR:$b), "!extui_br $r, $s, $b", []>; + def EXTUI_BR2_P: Pseudo<(outs AR:$r), (ins AR:$s, BR2:$b), + "!extui_br2 $r, $s, $b", []>; + def EXTUI_BR4_P: Pseudo<(outs AR:$r), (ins AR:$s, BR4:$b), + "!extui_br4 $r, $s, $b", []>; def SLLI_BR_P: Pseudo<(outs AR:$r), (ins AR:$s, BR:$b), "!slli_br $r, $s, $b", []>; def : Pat<(v1i1 (build_vector AR:$a)), (MOVBA_P AR:$a)>; - + def : Pat<(v1i1 (scalar_to_vector AR:$a)), (MOVBA_P AR:$a)>; + + def : Pat<(v2i1 (build_vector AR:$a, AR:$b)), + (MOVBA2_P (OR AR:$a, (SLLI AR:$b, (i32 1))))>; + + def : Pat<(v2i1 (Xtensa_trunc AR:$s)), (MOVBA2_P AR:$s)>; + def : Pat<(v4i1 (Xtensa_trunc AR:$s)), (MOVBA4_P AR:$s)>; + def : Pat<(i32 (vector_extract (v1i1 BR:$b), (i32 0))), (EXTUI_BR_P (RSR BREG), BR:$b)>; - def : Pat<(v1i1 (load addr_ish1:$addr)), (MOVBA_P (L8UI mem8:$addr))>; + def : Pat<(v2i1 (load addr_ish1:$addr)), (MOVBA2_P (L8UI mem8:$addr))>; + def : Pat<(v4i1 (load addr_ish1:$addr)), (MOVBA4_P (L8UI mem8:$addr))>; def : Pat<(store BR:$b, addr_ish1:$addr), (S8I (EXTUI_BR_P (RSR BREG), BR:$b), mem32:$addr)>; + def : Pat<(store BR2:$b, addr_ish1:$addr), (S8I (EXTUI_BR2_P (RSR BREG), BR2:$b), mem32:$addr)>; + def : Pat<(store BR4:$b, addr_ish1:$addr), (S8I (EXTUI_BR4_P (RSR BREG), BR4:$b), mem32:$addr)>; def SPILL_BOOL: Pseudo<(outs), (ins BR:$b, mem8:$mem), "!spill_bool $b, $mem",[]> { diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index 684ae7b894f239..dadd52ed9c54cf 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -47,6 +47,8 @@ def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCis def SDT_XtensaLoopEnd : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; def SDT_XtensaLoopDec : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>; def SDT_XtensaLoopBr : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisVT<1, OtherVT>]>; +def SDT_XtensaTRUNC : SDTypeProfile<1, 1, [SDTCisVT<1, i32>, SDTCisVec<0>]>; + //===----------------------------------------------------------------------===// // Node definitions @@ -118,3 +120,4 @@ def Xtensa_loopdec: SDNode<"XtensaISD::LOOPDEC", SDT_XtensaLoopDec, [SDNPHasChain, SDNPInGlue]>; def Xtensa_loopbr: SDNode<"XtensaISD::LOOPBR", SDT_XtensaLoopBr, [SDNPHasChain, SDNPInGlue]>; +def Xtensa_trunc: SDNode<"XtensaISD::TRUNC", SDT_XtensaTRUNC>; diff --git a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll index 321e955be6cd96..c1fb9f20870416 100644 --- a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll +++ b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll @@ -21,11 +21,9 @@ declare <1 x i1> @get_xtbool() define <1 x i1> @test_xtbool_load(i32 %addr) { ; CHECK-LABEL: test_xtbool_load ; CHECK: l8ui {{a[0-9]+}} - ; CHECK: movi.n [[C:a[0-9]+]], 1 - ; CHECK: and [[SRC:a[0-9]+]], {{a[0-9]+}}, [[C]] ; CHECK: rsr [[BREG:a[0-9]+]], br ; CHECK: and [[AND:a[0-9]+]], {{a[0-9]+}}, [[BREG]] - ; CHECK: or [[OR:a[0-9]+]], [[AND]], [[SRC]] + ; CHECK: or [[OR:a[0-9]+]], [[AND]], {{a[0-9]+}} ; CHECK: wsr [[OR]], br %ptr = inttoptr i32 %addr to ptr %load_bits = load <8 x i1>, ptr %ptr, align 1 From 94e8aee68ce8e14cd28320062e32705b8e396b6a Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Mar 2024 16:22:22 +0300 Subject: [PATCH 213/261] [Xtensa] Add HIFI3 instruction lowering --- llvm/lib/Target/Xtensa/XtensaCallingConv.td | 10 +- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 116 +++++++++++++++++- llvm/lib/Target/Xtensa/XtensaISelLowering.h | 9 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 19 ++- llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 40 ++++++ 5 files changed, 189 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaCallingConv.td b/llvm/lib/Target/Xtensa/XtensaCallingConv.td index f06f0995d4581e..56c2fb1aa1d2b2 100644 --- a/llvm/lib/Target/Xtensa/XtensaCallingConv.td +++ b/llvm/lib/Target/Xtensa/XtensaCallingConv.td @@ -30,7 +30,10 @@ def RetCC_Xtensa : CallingConv<[ //First two return values go in a2, a3, a4, a5 CCIfType<[i32], CCAssignToReg<[A2, A3, A4, A5]>>, CCIfType<[f32], CCAssignToReg<[A2, A3, A4, A5]>>, - CCIfType<[i64], CCAssignToRegWithShadow<[A2, A4], [A3, A5]>> + CCIfType<[i64], CCAssignToRegWithShadow<[A2, A4], [A3, A5]>>, + CCIfFeature<"HIFI3", + CCIfType<[v4i16, v2i32, v1i64, v1i32], + CCAssignToReg<[AED0, AED1, AED2, AED3]>>> ]>; //===----------------------------------------------------------------------===// @@ -51,5 +54,8 @@ def RetCCW_Xtensa : CallingConv<[ //First two return values go in a10, a11, a12, a13 CCIfType<[i32], CCAssignToReg<[A10, A11, A12, A13]>>, CCIfType<[f32], CCAssignToReg<[A10, A11, A12, A13]>>, - CCIfType<[i64], CCAssignToRegWithShadow<[A10, A12], [A11, A13]>> + CCIfType<[i64], CCAssignToRegWithShadow<[A10, A12], [A11, A13]>>, + CCIfFeature<"HIFI3", + CCIfType<[v4i16, v2i32, v1i64, v1i32], + CCAssignToReg<[AED0, AED1, AED2, AED3]>>> ]>; diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index c4e34d12aa9b10..d70b9aac533a2c 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -36,6 +36,25 @@ using namespace llvm; static const MCPhysReg XtensaArgRegs[6] = {Xtensa::A2, Xtensa::A3, Xtensa::A4, Xtensa::A5, Xtensa::A6, Xtensa::A7}; +static const MCPhysReg VecRegs[] = {Xtensa::AED0, Xtensa::AED1, Xtensa::AED2, + Xtensa::AED3}; + +static const MVT VectorIntTypes[] = { + MVT::v2i32, + MVT::v1i32, + MVT::v4i16, + MVT::v1i64, +}; + +template static bool isVecVT(VT ValVT) { + for (const auto &V : VectorIntTypes) { + auto VV = VT(V); + if (VV == ValVT) + return true; + } + return false; +} + // Return true if we must use long (in fact, indirect) function call. // It's simplified version, production implimentation must // resolve a functions in ROM (usually glibc functions) @@ -81,6 +100,27 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setOperationAction(ISD::LOAD, MVT::v2i1, Legal); setOperationAction(ISD::LOAD, MVT::v4i1, Legal); } + + if (Subtarget.hasHIFI3()) { + for (MVT VT : VectorIntTypes) { + addRegisterClass(VT, &Xtensa::AE_DRRegClass); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); + // handle bicast v8i8 to VEC_VT + setOperationAction(ISD::BITCAST, VT, Custom); + } + addRegisterClass(MVT::v8i8, &Xtensa::AE_VALIGNRegClass); + // handle bicast VEC_VT to v8i8 + setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); + + setOperationAction(ISD::SIGN_EXTEND, MVT::v1i32, Expand); + setOperationAction(ISD::ZERO_EXTEND, MVT::v1i32, Expand); + setOperationAction(ISD::ANY_EXTEND, MVT::v1i32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Legal); + + setTargetDAGCombine(ISD::BUILD_VECTOR); + setOperationAction(ISD::MUL, MVT::v1i64, Expand); + } + // Set up special registers. setStackPointerRegisterToSaveRestore(Xtensa::SP); @@ -393,6 +433,34 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm, setMaxAtomicSizeInBitsSupported(0); } + for (MVT VT : MVT::fixedlen_vector_valuetypes()) { + if (isTypeLegal(VT)) { + setOperationAction(ISD::CTPOP, VT, Expand); + setOperationAction(ISD::SRL, VT, Expand); + setOperationAction(ISD::SRA, VT, Expand); + setOperationAction(ISD::SHL, VT, Expand); + + // Expand all divisions and remainders for vectors + setOperationAction(ISD::SDIV, VT, Expand); + setOperationAction(ISD::UDIV, VT, Expand); + setOperationAction(ISD::SREM, VT, Expand); + setOperationAction(ISD::UREM, VT, Expand); + } + setOperationAction(ISD::SDIVREM, VT, Expand); + setOperationAction(ISD::UDIVREM, VT, Expand); + + setOperationAction(ISD::SELECT_CC, VT, Custom); + setOperationAction(ISD::SETCC, VT, Custom); + + // Disable all narrowing stores and extending loads for vectors + for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { + setTruncStoreAction(VT, InnerVT, Expand); + setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); + setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); + setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); + } + } + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); } @@ -761,6 +829,22 @@ static SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG, LHS, RHS, Dest); } +static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const XtensaSubtarget &Subtarget) { + SDLoc DL(N); + EVT VT = N->getValueType(0); + SDValue Op0 = N->getOperand(0); + ConstantSDNode *Const = dyn_cast(Op0); + if (VT == MVT::v1i64 && Const) { + int64_t Val = Const->getSExtValue(); + if (Val <= std::numeric_limits::max()) + return DAG.getNode(XtensaISD::BUILD_VEC, DL, MVT::v1i64, + DAG.getConstant(Val, DL, MVT::i32)); + } + return SDValue(); +} + static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const XtensaSubtarget &Subtarget) { @@ -862,6 +946,8 @@ SDValue XtensaTargetLowering::PerformDAGCombine(SDNode *N, return PerformHWLoopCombine(N, DAG, DCI, Subtarget); case ISD::BRCOND: return PerformBRCONDCombine(N, DAG, DCI, Subtarget); + case ISD::BUILD_VECTOR: + return PerformBUILD_VECTORCombine(N, DAG, DCI, Subtarget); case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, DCI, Subtarget); case ISD::EXTRACT_SUBVECTOR: @@ -959,6 +1045,9 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, } else if (ValVT == MVT::v4i1) { Reg = State.AllocateReg(BR4Regs); LocVT = ValVT; + } else if (isVecVT(ValVT)) { + Reg = State.AllocateReg(VecRegs); + LocVT = ValVT; } else llvm_unreachable("Cannot handle this ValVT."); @@ -1059,6 +1148,8 @@ SDValue XtensaTargetLowering::LowerFormalArguments( RC = &Xtensa::BR2RegClass; } else if (RegVT == MVT::v4i1) { RC = &Xtensa::BR4RegClass; + } else if (isVecVT(RegVT)) { + RC = &Xtensa::AE_DRRegClass; } else llvm_unreachable("RegVT not supported by FormalArguments Lowering"); @@ -1497,6 +1588,8 @@ SDValue XtensaTargetLowering::LowerSELECT_CC(SDValue Op, else if (TrueV.getValueType() == MVT::f32) return DAG.getNode(XtensaISD::SELECT_CC_FP, DL, TrueV.getValueType(), LHS, RHS, TrueV, FalseV, TargetCC); + else if (TrueV.getValueType().isVector()) + return Op; else return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueV, FalseV, TargetCC); @@ -1526,7 +1619,7 @@ SDValue XtensaTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { // SETCC has BRCOND predecessor, return original operation if (Val) - return Op; + return SDValue(); // Expand to target SELECT_CC SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType()); @@ -1538,6 +1631,8 @@ SDValue XtensaTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { else if (TrueV.getValueType() == MVT::f32) return DAG.getNode(XtensaISD::SELECT_CC_FP, DL, TrueV.getValueType(), LHS, RHS, TrueV, FalseV, TargetCC); + else if (TrueV.getValueType().isVector()) + return SDValue(); else return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueV, FalseV, TargetCC); @@ -2027,6 +2122,14 @@ SDValue XtensaTargetLowering::LowerATOMIC_FENCE(SDValue Op, return DAG.getNode(XtensaISD::MEMW, DL, MVT::Other, Chain); } +SDValue XtensaTargetLowering::LowerBitVecLOAD(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT VT = Op.getValueType(); + assert(VT.isVector() && VT.getSizeInBits() <= 8); + return SDValue(); // Expand +} + SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -2077,6 +2180,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, case ISD::FSHL: case ISD::FSHR: return LowerFunnelShift(Op, DAG); + case ISD::BITCAST: + return LowerBITCAST(Op, DAG); default: llvm_unreachable("Unexpected node to lower"); } @@ -2121,6 +2226,7 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(SRC); OPCODE(SSL); OPCODE(SSR); + OPCODE(BUILD_VEC); } return NULL; #undef OPCODE @@ -3586,3 +3692,11 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter( // llvm_unreachable("Unexpected instr type to insert"); } } + +SDValue XtensaTargetLowering::LowerBITCAST(SDValue Op, + SelectionDAG &DAG) const { + assert(Op.getValueType().isVector()); + if (Op.getOperand(0).getValueType() == MVT::v8i8) + return SDValue(); // Expand + return Op; // Legal +} diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index c10a4d93dcac9c..faeb18d0c0b0c6 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -92,7 +92,9 @@ enum { SRC, SSL, SSR, - TRUNC + + BUILD_VEC, + TRUNC, }; } @@ -179,6 +181,8 @@ class XtensaTargetLowering : public TargetLowering { const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override; + SDValue LowerVectorShift(SDValue Op, SelectionDAG &DAG) const; + bool shouldInsertFencesForAtomic(const Instruction *I) const override { return true; } @@ -228,6 +232,9 @@ class XtensaTargetLowering : public TargetLowering { SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerBitVecLOAD(SDValue Op, SelectionDAG &DAG) const; + SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 09ee11a9666ac9..a84aba944d686f 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -111,7 +111,18 @@ void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(KillSrc)) .addReg(SrcReg, getKillRegState(KillSrc)); return; - } else + } else if (STI.hasHIFI3() && Xtensa::AE_DRRegClass.contains(DestReg, SrcReg)) + Opcode = Xtensa::AE_MOV; + else if (STI.hasHIFI3() && Xtensa::AE_DRRegClass.contains(DestReg) && + Xtensa::ARRegClass.contains(SrcReg)) + Opcode = Xtensa::AE_MOVDA32; + else if (STI.hasHIFI3() && Xtensa::AE_DRRegClass.contains(SrcReg) && + Xtensa::ARRegClass.contains(DestReg)) + Opcode = Xtensa::AE_MOVAD32_L; + else if (STI.hasHIFI3() && + Xtensa::AE_VALIGNRegClass.contains(DestReg, SrcReg)) + Opcode = Xtensa::AE_MOVALIGN; + else llvm_unreachable("Impossible reg-to-reg copy"); BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) @@ -157,6 +168,12 @@ void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, } else if (RC == &Xtensa::BRRegClass) { LoadOpcode = Xtensa::RESTORE_BOOL; StoreOpcode = Xtensa::SPILL_BOOL; + } else if (RC == &Xtensa::AE_DRRegClass) { + LoadOpcode = Xtensa::AE_L64_I; + StoreOpcode = Xtensa::AE_S64_I; + } else if (RC == &Xtensa::AE_VALIGNRegClass) { + LoadOpcode = Xtensa::AE_LALIGN64_I; + StoreOpcode = Xtensa::AE_SALIGN64_I; } else llvm_unreachable("Unsupported regclass to load or store"); } diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index 351f02a4c0fbf0..cea04749849f62 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -143,6 +143,46 @@ bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II, case Xtensa::LEA_ADD: Valid = (Offset >= -128 && Offset <= 127); break; + case Xtensa::AE_L64_I: + case Xtensa::AE_S64_I: + case Xtensa::AE_S32X2_I: + case Xtensa::AE_L32X2_I: + case Xtensa::AE_S16X4_I: + case Xtensa::AE_L16X4_I: + case Xtensa::AE_LALIGN64_I: + case Xtensa::AE_SALIGN64_I: + Valid = (Offset >= -64 && Offset <= 56); + break; + case Xtensa::AE_S64_IP: + case Xtensa::AE_L64_IP: + case Xtensa::AE_S32X2_IP: + case Xtensa::AE_L32X2_IP: + case Xtensa::AE_S16X4_IP: + case Xtensa::AE_L16X4_IP: + Valid = (Offset >= 0 && Offset <= 56); + break; + case Xtensa::AE_L16X2M_I: + case Xtensa::AE_L16X2M_IU: + case Xtensa::AE_L32F24_I: + case Xtensa::AE_L32F24_IP: + case Xtensa::AE_L32M_I: + case Xtensa::AE_L32M_IU: + case Xtensa::AE_L32_I: + case Xtensa::AE_L32_IP: + case Xtensa::AE_S16X2M_I: + case Xtensa::AE_S16X2M_IU: + case Xtensa::AE_S24RA64S_I: + case Xtensa::AE_S24RA64S_IP: + case Xtensa::AE_S32F24_L_I: + case Xtensa::AE_S32F24_L_IP: + case Xtensa::AE_S32M_I: + case Xtensa::AE_S32M_IU: + case Xtensa::AE_S32RA64S_I: + case Xtensa::AE_S32RA64S_IP: + case Xtensa::AE_S32_L_I: + case Xtensa::AE_S32_L_IP: + Valid = (Offset >= -32 && Offset <= 28); + break; default: // assume that MI is 32-bit load/store operation Valid = (Offset >= 0 && Offset <= 1020) && ((Offset & 0x3) == 0); From a4a76235a1ca15d6e15b763e1b851be6d3416cc5 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Fri, 30 Jun 2023 13:35:25 +0000 Subject: [PATCH 214/261] [Xtensa] Fix alignment in LowerVACOPY() --- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index d70b9aac533a2c..6b0964c375f97a 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -2012,7 +2012,7 @@ SDValue XtensaTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { unsigned VAListSize = 12; return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2), DAG.getConstant(VAListSize, SDLoc(Op), MVT::i32), - Align(8), false, true, false, MachinePointerInfo(), + Align(4), false, true, false, MachinePointerInfo(), MachinePointerInfo()); } From ed47c293f5853fda358bf57a331d9191a1fffa82 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:27:40 +0000 Subject: [PATCH 215/261] [Xtensa] Add HIFI3 instruction selection patterns --- .../Target/Xtensa/XtensaHIFIInstrPatterns.td | 189 ++++++++++++++++++ llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 38 ++++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 1 + llvm/lib/Target/Xtensa/XtensaOperators.td | 4 +- 4 files changed, 231 insertions(+), 1 deletion(-) create mode 100644 llvm/lib/Target/Xtensa/XtensaHIFIInstrPatterns.td diff --git a/llvm/lib/Target/Xtensa/XtensaHIFIInstrPatterns.td b/llvm/lib/Target/Xtensa/XtensaHIFIInstrPatterns.td new file mode 100644 index 00000000000000..fc60c8b7c10e79 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaHIFIInstrPatterns.td @@ -0,0 +1,189 @@ +//===- XtensaHIFIInstrPatterns.td - Tablegen patterns for Xtensa HIFI -*- tablegen -*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains Tablegen code generation patterns for Xtensa HIFI extension +// +//===----------------------------------------------------------------------===// + +def addr64n_56: ComplexPattern", [frameindex]>; + +def addr32n_28: ComplexPattern", [frameindex]>; + +let Predicates = [HasHIFI3] in { + +def : Pat<(v2i32 (load (addr64n_56 AR:$a, imm64n_56:$imm))), + (AE_L32X2_I AR:$a, imm64n_56:$imm)>; + +def : Pat<(store v2i32:$v, (addr64n_56 AR:$a, imm64n_56:$imm)), + (AE_S32X2_I v2i32:$v, AR:$a, imm64n_56:$imm)>; + +def : Pat<(v1i64 (load (addr64n_56 AR:$a, imm64n_56:$imm))), + (AE_L64_I AR:$a, imm64n_56:$imm)>; + +def : Pat<(store v1i64:$v, (addr64n_56 AR:$a, imm64n_56:$imm)), + (AE_S64_I v1i64:$v, AR:$a, imm64n_56:$imm)>; + +def : Pat<(v4i16 (load (addr64n_56 AR:$a, imm64n_56:$imm))), + (AE_L16X4_I AR:$a, imm64n_56:$imm)>; + +def : Pat<(store v4i16:$v, (addr64n_56 AR:$a, imm64n_56:$imm)), + (AE_S16X4_I v4i16:$v, AR:$a, imm64n_56:$imm)>; + +def : Pat<(v1i32 (load (addr32n_28 AR:$a, imm32n_28:$imm))), + (AE_L32_I AR:$a, imm32n_28:$imm)>; + +def : Pat<(store v1i32:$v, (addr32n_28 AR:$a, imm32n_28:$imm)), + (AE_S32_L_I v1i32:$v, AR:$a, imm32n_28:$imm)>; + + +def : Pat<(v8i8 (load (addr64n_56 AR:$a, imm64n_56:$imm))), + (AE_LALIGN64_I AR:$a, imm64n_56:$imm)>; + +def : Pat<(store AE_VALIGN:$v, (addr64n_56 AR:$a, imm64n_56:$imm)), + (AE_SALIGN64_I AE_VALIGN:$v, AR:$a, imm64n_56:$imm)>; + + +def : Pat<(v2i32 (build_vector AR:$v1, AR:$v2)), + (AE_MOVDA32X2 AR:$v2, AR:$v1)>; + +def : Pat<(v2i32 (build_vector AR:$a, AR:$a)), + (AE_MOVDA32 AR:$a)>; + +/* Build const i64 vector when const fit in [-16,47]*/ +def : Pat<(v1i64 (Xtensa_build_vec imm16n_47:$a)), + (AE_SRLI64 (AE_MOVI imm16n_47:$a), (i32 32))>; + +/* Build const i64 vector with 32-bit const */ +def : Pat<(v1i64 (Xtensa_build_vec AR:$a)), + (AE_SRLI64 (AE_MOVDA32 AR:$a), (i32 32))>; + + +def : Pat<(v1i32 (build_vector AR:$a)), + (AE_MOVDA32 AR:$a)>; + +def : Pat<(v4i16 (build_vector AR:$a, AR:$a, AR:$a, AR:$a)), + (AE_MOVDA16 AR:$a)>; + +def : Pat<(v4i16 (build_vector AR:$v1, AR:$v2, AR:$v1, AR:$v2)), + (AE_MOVDA16X2 AR:$v1, AR:$v2)>; + +def : Pat<(v4i16 (build_vector AR:$v1, AR:$v2, AR:$v3, AR:$v4)), + (AE_OR + (AE_SLAI64 (AE_MOVDA16X2 AR:$v1, AR:$v2), 32), + (AE_MOVDA16X2 AR:$v3, AR:$v4) + )>; + +def : Pat<(i32 (extractelt v2i32:$v1, (i32 0))), + (AE_MOVAD32_L AE_DR:$v1)>; + +def : Pat<(i32 (extractelt v2i32:$v1, (i32 1))), + (AE_MOVAD32_H AE_DR:$v1)>; + +def : Pat<(i32 (extractelt v1i32:$v1, (i32 0))), + (AE_MOVAD32_L AE_DR:$v1)>; + +def : Pat<(i32 (vector_extract v4i16:$v1, (i32 0))), + (AE_MOVAD16_0 AE_DR:$v1)>; + +def : Pat<(i32 (vector_extract v4i16:$v1, (i32 1))), + (AE_MOVAD16_1 AE_DR:$v1)>; + +def : Pat<(i32 (vector_extract v4i16:$v1, (i32 2))), + (AE_MOVAD16_2 AE_DR:$v1)>; + +def : Pat<(i32 (vector_extract v4i16:$v1, (i32 3))), + (AE_MOVAD16_3 AE_DR:$v1)>; + +def : Pat<(v1i32 (extract_subvector v2i32:$v1, (i32 0))), + (AE_MOVDA32 (AE_MOVAD32_L AE_DR:$v1))>; +} + +class CAST_PAT + : Pat<(dst_vt (bitconvert src_vt:$v)), + (COPY_TO_REGCLASS AE_DR:$v, AE_DR)>; + +def : CAST_PAT; +def : CAST_PAT; +def : CAST_PAT; +def : CAST_PAT; +def : CAST_PAT; +def : CAST_PAT; + +def : Pat<(v1i64 (anyext v1i32:$src)), + (AE_SRLI64 v1i32:$src, (i32 32))>; + +def : Pat<(v1i64 (zext v1i32:$src)), + (AE_SRLI64 v1i32:$src, (i32 32))>; + +def : Pat<(v1i64 (sext v1i32:$src)), + (AE_SRAI64 v1i32:$src, (i32 32))>; + +/* +class BIN_PAT + : Pat<(node src_vt:$f1, src_vt:$f2), + (inst dst_vt:$f1, dst_vt:$f2)>; +*/ +foreach VT = AE_DR.RegTypes in { + def : BIN_PAT; + def : BIN_PAT; + def : BIN_PAT; +} + +def : BIN_PAT; +def : BIN_PAT; +def : BIN_PAT; +def : BIN_PAT; + +def : BIN_PAT; +def : BIN_PAT; +def : BIN_PAT; +def : BIN_PAT; + +def : BIN_PAT; +def : BIN_PAT; +def : BIN_PAT; + +/* SELECT and SETCC patterns */ +foreach VT = AE_DR.RegTypes in { + def : Pat<(VT (select v1i1:$cc, AE_DR:$t, AE_DR:$f)), + (AE_MOVT64 AE_DR:$t, AE_DR:$f, v1i1:$cc)>; +} +def : Pat<(f32 (int_xtensa_xt_movt_s FPR:$t, FPR:$f, v1i1:$cc)), + (MOVT_S FPR:$t, FPR:$f, v1i1:$cc)>,Requires<[HasSingleFloat]>; + +def : Pat<(f32 (select v1i1:$cc, FPR:$t, FPR:$f)), + (MOVT_S FPR:$t, FPR:$f, v1i1:$cc)>,Requires<[HasSingleFloat]>; + +class SELECTCC_VEC_INT + : Pat<(vt (selectcc i32:$lhs, i32:$rhs, AE_DR:$t, AE_DR:$f, cond)), + (mov AE_DR:$t, AE_DR:$f, (cmp (AE_MOVDA32 AR:$lhs), + (AE_MOVDA32 AR:$rhs)))>; + +foreach vt = [v2i32,v1i32,v1i64,v4i16] in { + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; + def : SELECTCC_VEC_INT; +} diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 0e5dd349c2fcfb..2f5f516779ed6d 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -120,6 +120,44 @@ class XtensaDAGToDAGISel : public SelectionDAGISel { return selectMemRegAddr(Addr, Base, Offset, 4); } + template + bool selectMemRegImm(SDValue Addr, SDValue &Base, SDValue &Offset) { + EVT ValTy = Addr.getValueType(); + // if Address is FI, get the TargetFrameIndex. + if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy); + + return true; + } + if (TM.isPositionIndependent()) + report_fatal_error("PIC relocations is not supported"); + + if ((Addr.getOpcode() == ISD::TargetExternalSymbol || + Addr.getOpcode() == ISD::TargetGlobalAddress)) + return false; + + if (CurDAG->isBaseWithConstantOffset(Addr)) { + ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); + int64_t OffsetVal = CN->getSExtValue(); + if (((OffsetVal % std::abs(Scale)) == 0) && (OffsetVal >= Low) && + (OffsetVal <= High)) { + if (FrameIndexSDNode *FIN = + dyn_cast(Addr.getOperand(0))) + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); + else + Base = Addr.getOperand(0); + Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(Addr), + Addr.getValueType()); + return true; + } + } + // Last case + Base = Addr; + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType()); + return true; + } + // Include the pieces autogenerated from the target description. #include "XtensaGenDAGISel.inc" }; // namespace diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 6ffb6f917faa33..a89a0a55f07f6f 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -2047,3 +2047,4 @@ include "XtensaDSPInstrInfo.td" //===----------------------------------------------------------------------===// include "XtensaHIFIInstrFormats.td" include "XtensaHIFIInstrInfo.td" +include "XtensaHIFIInstrPatterns.td" diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td index dadd52ed9c54cf..37a92331fec3b9 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperators.td +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -47,8 +47,9 @@ def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCis def SDT_XtensaLoopEnd : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; def SDT_XtensaLoopDec : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>; def SDT_XtensaLoopBr : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisVT<1, OtherVT>]>; -def SDT_XtensaTRUNC : SDTypeProfile<1, 1, [SDTCisVT<1, i32>, SDTCisVec<0>]>; +def SDT_XtensaBuildVec : SDTypeProfile<1, 1, [SDTCisVT<0, v1i64>, SDTCisVT<1, i32>]>; +def SDT_XtensaTRUNC : SDTypeProfile<1, 1, [SDTCisVT<1, i32>, SDTCisVec<0>]>; //===----------------------------------------------------------------------===// // Node definitions @@ -104,6 +105,7 @@ def Xtensa_srl: SDNode<"XtensaISD::SRL", SDT_XtensaSRL, [SDNPInGlue]>; def Xtensa_src: SDNode<"XtensaISD::SRC", SDT_XtensaSRC, [SDNPInGlue]>; def Xtensa_ssl: SDNode<"XtensaISD::SSL", SDT_XtensaSSL, [SDNPOutGlue]>; def Xtensa_ssr: SDNode<"XtensaISD::SSR", SDT_XtensaSSR, [SDNPOutGlue]>; +def Xtensa_build_vec: SDNode<"XtensaISD::BUILD_VEC", SDT_XtensaBuildVec, [SDNPInGlue]>; def Xtensa_brjt: SDNode<"XtensaISD::BR_JT", SDT_XtensaBrJT, [SDNPHasChain]>; def Xtensa_callw: SDNode<"XtensaISD::CALLW", SDT_XtensaCall, From a062cb0ef04f7d480a8dda57b1039e316df76bd2 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:28:39 +0000 Subject: [PATCH 216/261] [Xtensa] Add codegen tests for vector operators --- llvm/test/CodeGen/Xtensa/xtensa-gen-ops.ll | 91 +++++ llvm/test/CodeGen/Xtensa/xtensa-vector-ops.ll | 329 ++++++++++++++++++ 2 files changed, 420 insertions(+) create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-gen-ops.ll create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-vector-ops.ll diff --git a/llvm/test/CodeGen/Xtensa/xtensa-gen-ops.ll b/llvm/test/CodeGen/Xtensa/xtensa-gen-ops.ll new file mode 100644 index 00000000000000..fd1fa8dcf06d1e --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-gen-ops.ll @@ -0,0 +1,91 @@ +# RUN: python3 %s > %t && ( llc -mtriple=xtensa -mcpu=cnl %t -o - | FileCheck %t ) + + +FIXTURES = [ + ('add','ae_add64','<1 x i64>'), + ('add','ae_add32','<1 x i32>'), + ('add','ae_add32','<2 x i32>'), + ('add','ae_add16','<4 x i16>'), + + ('sub','ae_sub64','<1 x i64>'), + ('sub','ae_sub32','<1 x i32>'), + ('sub','ae_sub32','<2 x i32>'), + ('sub','ae_sub16','<4 x i16>'), + + ('mul','ae_mulp32x2','<2 x i32>'), + ('mul','ae_mulp32x2','<1 x i32>'), + ('mul','ae_mul16x4','<4 x i16>'), +] + +REG_TYPES = ['<1 x i64>', '<2 x i32>', '<1 x i32>', '<4 x i16>'] + +BITWISE_OPS = [ + ('and', 'ae_and'), + ('or', 'ae_or'), + ('xor', 'ae_xor') +] + +from dataclasses import dataclass + +@dataclass +class F: + op: str + instr: str + type : str + +template = """ +define {type} @test_{fun}({type} %a, {type} %b) {{ + ; CHECK-LABEL: test_{fun} + ; CHECK: {instr} aed0, {{{{aed[01]}}}}, {{{{aed[01]}}}} + %r = {op} {type} %a, %b + ret {type} %r +}} +""" + +def v2s(typ): + return typ.strip('<>').replace(' ','') + +for f in FIXTURES: + f = F(*f) + f.fun = f.op + v2s(f.type) + print(template.format(**f.__dict__)) + +for f in BITWISE_OPS: + op, instr = f + for typ in REG_TYPES: + fun = op + v2s(typ) + print(template.format(op=op, instr=instr,fun=fun,type=typ)) + +cmp_template = """ +define {vtype} @test_sel_{fun}({ctype} %a, {ctype} %b, {vtype} %t, {vtype} %f) {{ + ; CHECK-LABEL: test_sel_{fun} + ; CHECK-DAG: ae_movda32 {{{{aed[0-9]+}}}}, {{{{a[0-9]+}}}} + ; CHECK-DAG: ae_movda32 {{{{aed[0-9]+}}}}, {{{{a[0-9]+}}}} + ; CHECK: {cmp_inst} {{{{b[0-9]+}}}}, {{{{aed[0-9]+}}}}, {{{{aed[0-9]+}}}} + ; CHECK: {mov_inst} {{{{aed[0-9]+}}}}, {{{{aed[0-9]+}}}}, {{{{b[0-9]+}}}} + %cmp = icmp {cmp_bc} {ctype} %a, %b + %cond = select i1 %cmp, {vtype} %f, {vtype} %t + ret {vtype} %cond +}} +""" + +CMP_FIXTURES = [ + ('eq','ae_eq64', 'ae_movt64'), + ('ne','ae_eq64', 'ae_movf64'), + ('ugt','ae_le64', 'ae_movf64'), + ('uge','ae_lt64', 'ae_movf64'), + ('ult','ae_lt64', 'ae_movt64'), + ('ule','ae_le64', 'ae_movt64'), + ('sgt','ae_le64', 'ae_movf64'), + ('sge','ae_lt64', 'ae_movf64'), + ('slt','ae_lt64', 'ae_movt64'), + ('sle','ae_le64', 'ae_movt64'), +] + +SCALARS = "i32 i16 i8".split() + +for cmp_bc, cmp_inst, mov_inst in CMP_FIXTURES: + for ctype in SCALARS: + for vtype in REG_TYPES: + fun = '_'.join((cmp_bc, ctype, v2s(vtype))) + print(cmp_template.format(**locals())) diff --git a/llvm/test/CodeGen/Xtensa/xtensa-vector-ops.ll b/llvm/test/CodeGen/Xtensa/xtensa-vector-ops.ll new file mode 100644 index 00000000000000..1e4df95919905e --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-vector-ops.ll @@ -0,0 +1,329 @@ +; RUN: llc -mtriple=xtensa -mcpu=cnl %s -o - | FileCheck %s + +define i32 @test_2xi32toi32(<2 x i32> %a) { + ; CHECK-LABEL: test_2xi32toi32 + ; CHECK: ae_movad32.l a2, aed0 + %r = extractelement <2 x i32> %a, i32 0 + ret i32 %r +} + +define <2 x i32> @test_i32to2xi32(i32 %a) { + ; CHECK-LABEL: test_i32to2xi32 + ; CHECK: ae_movda32x2 aed0, a2, a2 + %vecinit = insertelement <2 x i32> undef, i32 %a, i64 0 + %vecinit1 = shufflevector <2 x i32> %vecinit, <2 x i32> poison, <2 x i32> zeroinitializer + ret <2 x i32> %vecinit1 +} + +define void @test_store_2xi32(i32 %a, <2 x i32> %v) { + ; CHECK-LABEL: test_store_2xi32 + ; CHECK: ae_s32x2.i aed0, a2, 0 + %p = inttoptr i32 %a to ptr + store <2 x i32> %v, ptr %p, align 8 + ret void +} + +define void @test_store_1xi64(i32 %a, <1 x i64> %v) { + ; CHECK-LABEL: test_store_1xi64 + %p = inttoptr i32 %a to ptr + ; CHECK: ae_s64.i aed0, a2, 0 + store <1 x i64> %v, ptr %p, align 8 + ret void +} + +define <1 x i64> @test_build_1xi64(i64 %v) { + ; CHECK-LABEL: test_build_1xi64 + ; CHECK: ae_movda32x2 aed0, a3, a2 + %vec = insertelement <1 x i64> undef, i64 %v, i64 0 + ret <1 x i64> %vec +} + +define void @test_store_4xi16(i32 %a, <4 x i16> %v) { + ; CHECK-LABEL: test_store_4xi16 + ; CHECK: ae_s16x4.i aed0, a2, 0 + %p = inttoptr i32 %a to ptr + store <4 x i16> %v, ptr %p, align 8 + ret void +} + +define <2 x i32> @test_load_2xi32(i32 %a) { + ; CHECK-LABEL: test_load_2xi32 + ; CHECK: ae_l32x2.i aed0, a2, 0 + %p = inttoptr i32 %a to ptr + %v = load <2 x i32>, ptr %p, align 8 + ret <2 x i32> %v +} + +define <1 x i64> @test_load_1xi64(i32 %a) { + ; CHECK-LABEL: test_load_1xi64 + ; CHECK: ae_l64.i aed0, a2, 0 + %p = inttoptr i32 %a to ptr + %v = load <1 x i64>, ptr %p, align 8 + ret <1 x i64> %v +} + +define <4 x i16> @test_load_4xi16(i32 %a) { + ; CHECK-LABEL: test_load_4xi16 + ; CHECK: ae_l16x4.i aed0, a2, 0 + %p = inttoptr i32 %a to ptr + %v = load <4 x i16>, ptr %p, align 8 + ret <4 x i16> %v +} + +define void @test_build_store_1xi32(i32 %a, i32 %v) { + ; CHECK-LABEL: test_build_store_1xi32 + ; CHECK: ae_movda32 [[A:aed[0-9]+]], a3 + %vec = insertelement <1 x i32> undef, i32 %v, i64 0 + %p = inttoptr i32 %a to ptr + ; CHECK: ae_s32.l.i [[A]], a2, 0 + store <1 x i32> %vec, ptr %p, align 8 + ret void +} + +define i32 @test_load_extract_1xi32(i32 %a) { + ; CHECK-LABEL: test_load_extract_1xi32 + %p = inttoptr i32 %a to ptr + ; CHECK: ae_l32.i [[A:aed[0-9]+]], a2, 0 + %vec = load <1 x i32>, ptr %p, align 8 + ; CHECK: ae_movad32.l a2, [[A]] + %r = extractelement <1 x i32> %vec, i32 0 + ret i32 %r +} + +define <4 x i16> @test_build_4xi16_2(i16 %a, i16 %b) { + ; CHECK-LABEL: test_build_4xi16_2 + ; CHECK: ae_movda16x2 aed0, a2, a3 + %vecinit = insertelement <4 x i16> undef, i16 %a, i64 0 + %vecinit1 = insertelement <4 x i16> %vecinit, i16 %b, i64 1 + %vecinit2 = insertelement <4 x i16> %vecinit1, i16 %a, i64 2 + %vecinit3 = insertelement <4 x i16> %vecinit2, i16 %b, i64 3 + ret <4 x i16> %vecinit3 +} + +define <4 x i16> @test_build_4xi16_1(i16 %a) { + ; CHECK-LABEL: test_build_4xi16_1 + ; CHECK: ae_movda16 aed0, a2 + %vecinit = insertelement <4 x i16> undef, i16 %a, i64 0 + %vecinit1 = shufflevector <4 x i16> %vecinit, <4 x i16> poison, <4 x i32> zeroinitializer + ret <4 x i16> %vecinit1 +} + +define i32 @test_extract(<2 x i32> %v2i, <1 x i32> %v1i, <4 x i16> %v4s, <1 x i64> %v1l) { + ; CHECK-LABEL: test_extract + ; CHECK-DAG: ae_movad32.h {{a[0-9]+}}, aed0 + %v2i0 = extractelement <2 x i32> %v2i, i64 0 + ; CHECK-DAG: ae_movad32.l {{a[0-9]+}}, aed0 + %v2i1 = extractelement <2 x i32> %v2i, i64 1 + %sum1 = add i32 %v2i0, %v2i1 + ; CHECK-DAG: ae_movad32.l {{a[0-9]+}}, aed1 + %v1i0 = extractelement <1 x i32> %v1i, i64 0 + %sum2 = add i32 %sum1, %v1i0 + ; CHECK-DAG: ae_movad16.0 {{a[0-9]+}}, aed2 + %v4s0 = extractelement <4 x i16> %v4s, i64 0 + %v4s0i = zext i16 %v4s0 to i32 + %sum3 = add i32 %v4s0i, %sum2 + ; CHECK-DAG: ae_movad16.1 {{a[0-9]+}}, aed2 + %v4s1 = extractelement <4 x i16> %v4s, i64 1 + %v4s1i = zext i16 %v4s1 to i32 + %sum4 = add i32 %v4s1i, %sum3 + ; CHECK-DAG: ae_movad16.2 {{a[0-9]+}}, aed2 + %v4s2 = extractelement <4 x i16> %v4s, i64 2 + %v4s2i = zext i16 %v4s2 to i32 + %sum5 = add i32 %v4s2i, %sum4 + ; CHECK-DAG: ae_movad16.3 {{a[0-9]+}}, aed2 + %v4s3 = extractelement <4 x i16> %v4s, i64 3 + %v4s3i = zext i16 %v4s3 to i32 + %sum6 = add i32 %v4s3i, %sum5 + ; CHECK-DAG: ae_movad32.l {{a[0-9]+}}, aed3 + %v1l0 = extractelement <1 x i64> %v1l, i64 0 + %v1l0l = trunc i64 %v1l0 to i32 + %sum7 = add i32 %v1l0l, %sum6 + + ret i32 %sum7 +} + +define <1 x i32> @test_extract_subvec_1x32(<2 x i32> %v) { + ; CHECK-LABEL: test_extract_subvec_1x32 + ; CHECK: ae_movad32.l {{a[0-9]+}}, aed0 + ; CHECK: ae_movda32 aed0, {{a[0-9]+}} + %shuffle = shufflevector <2 x i32> %v, <2 x i32> poison, <1 x i32> zeroinitializer + ret <1 x i32> %shuffle +} + + +define <4 x i16> @rlshift4(<4 x i16> %a, i16 signext %b) { + ; CHECK-LABEL: rlshift4: + ; CHECK: ssr {{a[0-9]+}} + %v = insertelement <4 x i16> undef, i16 %b, i64 0 + %sh_prom = shufflevector <4 x i16> %v, <4 x i16> poison, <4 x i32> zeroinitializer + %shr = lshr <4 x i16> %a, %sh_prom + ret <4 x i16> %shr +} + + +define <4 x i16> @rlshift4_imm(<4 x i16> %a) { + ; CHECK-LABEL: rlshift4_imm: + ; CHECK: srli {{a[0-9]+}}, {{a[0-9]+}}, 1 + %shr = lshr <4 x i16> %a, + ret <4 x i16> %shr +} + + +define <2 x i32> @rlshift2(<2 x i32> %a, i32 %b) { + ; CHECK-LABEL: rlshift2: + ; CHECK: ssr {{a[0-9]+}} + %splat.splatinsert = insertelement <2 x i32> poison, i32 %b, i64 0 + %splat.splat = shufflevector <2 x i32> %splat.splatinsert, <2 x i32> poison, <2 x i32> zeroinitializer + %shr = lshr <2 x i32> %a, %splat.splat + ret <2 x i32> %shr +} + + +define <2 x i32> @rlshift2_imm(<2 x i32> %a) { + ; CHECK-LABEL: rlshift2_imm: + ; CHECK: srli {{a[0-9]+}}, {{a[0-9]+}}, 1 + %shr = lshr <2 x i32> %a, + ret <2 x i32> %shr +} + +define <1 x i64> @rlshift1(<1 x i64> %a, i32 %b) { + ; CHECK-LABEL: rlshift1: + ; CHECK: ssr {{a[0-9]+}} + ; CHECK: src {{a[0-9]+}} + ; CHECK: srl {{a[0-9]+}} + %splat.splatinsert = insertelement <1 x i32> poison, i32 %b, i64 0 + %sh_prom = zext <1 x i32> %splat.splatinsert to <1 x i64> + %shr = lshr <1 x i64> %a, %sh_prom + ret <1 x i64> %shr +} + +define <1 x i64> @rlshift1_imm(<1 x i64> %a) { + ; CHECK-LABEL: rlshift1_imm: + ; CHECK: ssr {{a[0-9]+}} + ; CHECK: src {{a[0-9]+}} + ; CHECK: srl {{a[0-9]+}} + %shr = lshr <1 x i64> %a, + ret <1 x i64> %shr +} + +define <4 x i16> @rashift4(<4 x i16> %a, i16 signext %b) { + ; CHECK-LABEL: rashift4: + ; CHECK: ssr {{a[0-9]+}} + ; CHECK: sra {{a[0-9]+}} + %v = insertelement <4 x i16> undef, i16 %b, i64 0 + %sh_prom = shufflevector <4 x i16> %v, <4 x i16> poison, <4 x i32> zeroinitializer + %shr = ashr <4 x i16> %a, %sh_prom + ret <4 x i16> %shr +} + +define <4 x i16> @rashift4_imm(<4 x i16> %a) { + ; CHECK-LABEL: rashift4_imm: + ; CHECK: srai {{a[0-9]+}}, {{a[0-9]+}}, 1 + %shr = ashr <4 x i16> %a, + ret <4 x i16> %shr +} + +define <2 x i32> @rashift2(<2 x i32> %a, i32 %b) { + ; CHECK-LABEL: rashift2: + ; CHECK: ssr {{a[0-9]+}} + ; CHECK: sra {{a[0-9]+}} + %splat.splatinsert = insertelement <2 x i32> poison, i32 %b, i64 0 + %splat.splat = shufflevector <2 x i32> %splat.splatinsert, <2 x i32> poison, <2 x i32> zeroinitializer + %shr = ashr <2 x i32> %a, %splat.splat + ret <2 x i32> %shr +} + + +define <2 x i32> @rashift2_imm(<2 x i32> %a) { + ; CHECK-LABEL: rashift2_imm: + ; CHECK: srai {{a[0-9]+}}, {{a[0-9]+}}, 1 + %shr = ashr <2 x i32> %a, + ret <2 x i32> %shr +} + + +define <1 x i64> @rashift1(<1 x i64> %a, i64 %b) { + ; CHECK-LABEL: rashift1: + ; CHECK: ssr {{a[0-9]+}} + ; CHECK: sra {{a[0-9]+}} + %splat.splatinsert = insertelement <1 x i64> poison, i64 %b, i64 0 + %shr = ashr <1 x i64> %a, %splat.splatinsert + ret <1 x i64> %shr +} + + +define <1 x i64> @rashift1_imm(<1 x i64> %a) { + ; CHECK-LABEL: rashift1_imm: + ; CHECK: ssr {{a[0-9]+}} + ; CHECK: sra {{a[0-9]+}} + %shr = ashr <1 x i64> %a, + ret <1 x i64> %shr +} + + +define <4 x i16> @lshift4(<4 x i16> %a, i16 signext %b) { + ; CHECK-LABEL: lshift4: + ; CHECK: ssl {{a[0-9]+}} + ; CHECK: sll {{a[0-9]+}} + %v = insertelement <4 x i16> undef, i16 %b, i64 0 + %sh_prom = shufflevector <4 x i16> %v, <4 x i16> poison, <4 x i32> zeroinitializer + %shl = shl <4 x i16> %a, %sh_prom + ret <4 x i16> %shl +} + + +define <4 x i16> @lshift4_imm(<4 x i16> %a) { + ; CHECK-LABEL: lshift4_imm: + ; CHECK: slli {{a[0-9]+}}, {{a[0-9]+}}, 1 + %shl = shl <4 x i16> %a, + ret <4 x i16> %shl +} + + +define <2 x i32> @lshift2(<2 x i32> %a, i32 %b) { + ; CHECK-LABEL: lshift2: + ; CHECK: ssl {{a[0-9]+}} + ; CHECK: sll {{a[0-9]+}} + %splat.splatinsert = insertelement <2 x i32> poison, i32 %b, i64 0 + %splat.splat = shufflevector <2 x i32> %splat.splatinsert, <2 x i32> poison, <2 x i32> zeroinitializer + %shl = shl <2 x i32> %a, %splat.splat + ret <2 x i32> %shl +} + + +define <2 x i32> @lshift2_imm(<2 x i32> %a) { + ; CHECK-LABEL: lshift2_imm: + ; CHECK: slli {{a[0-9]+}}, {{a[0-9]+}}, 1 + %shl = shl <2 x i32> %a, + ret <2 x i32> %shl +} + + +define <1 x i64> @lshift1(<1 x i64> %a, i64 %b) { + ; CHECK-LABEL: lshift1: + ; CHECK: ssl {{a[0-9]+}} + ; CHECK: sll {{a[0-9]+}} + %splat.splatinsert = insertelement <1 x i64> poison, i64 %b, i64 0 + %shl = shl <1 x i64> %a, %splat.splatinsert + ret <1 x i64> %shl +} + + +define <1 x i64> @lshift1_imm(<1 x i64> %a) { + ; CHECK-LABEL: lshift1_imm: + ; CHECK: ssl {{a[0-9]+}} + ; CHECK: sll {{a[0-9]+}} + %shl = shl <1 x i64> %a, + ret <1 x i64> %shl +} + +define void @test_valign_load_store(i32 %p1, i32 %p2) { + ; CHECK-LABEL: test_valign_load_store: + %ptr1 = inttoptr i32 %p1 to ptr + %ptr2 = inttoptr i32 %p2 to ptr + ; CHECK: ae_lalign64.i [[V:u[0-3]]], {{a[0-9]+}}, 0 + %v = load <8 x i8>, ptr %ptr1, align 8 + ; CHECK: ae_salign64.i [[V]], {{a[0-9]+}}, 0 + store <8 x i8> %v, ptr %ptr2, align 8 + ret void +} From f0130156a85f335d160af2c843bf8e40854f14e2 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:49:44 +0000 Subject: [PATCH 217/261] [Xtensa] Add codegen support for HIFI3 intrinsics --- .../Target/Xtensa/XtensaHIFIIntrinsics.inc | 227 + llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 53 +- .../CodeGen/Xtensa/xtensa-hifi-intrinsics.ll | 12298 ++++++++++++++++ 3 files changed, 12564 insertions(+), 14 deletions(-) create mode 100644 llvm/lib/Target/Xtensa/XtensaHIFIIntrinsics.inc create mode 100644 llvm/test/CodeGen/Xtensa/xtensa-hifi-intrinsics.ll diff --git a/llvm/lib/Target/Xtensa/XtensaHIFIIntrinsics.inc b/llvm/lib/Target/Xtensa/XtensaHIFIIntrinsics.inc new file mode 100644 index 00000000000000..f1cfbd35716277 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaHIFIIntrinsics.inc @@ -0,0 +1,227 @@ +//===- XtensaHIFIIntrinsics.td - Xtensa HIFI intrinsics database for LLVM ISEL +//-*- tablegen -*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains Tablegen instruction formats for Xtensa HIFI extension +// +//===----------------------------------------------------------------------===// + +case Intrinsic::xtensa_ae_l16_ip: +return Xtensa::AE_L16_IP; +case Intrinsic::xtensa_ae_l16_xc: +return Xtensa::AE_L16_XC; +case Intrinsic::xtensa_ae_l16_xp: +return Xtensa::AE_L16_XP; +case Intrinsic::xtensa_ae_l16m_iu: +return Xtensa::AE_L16M_IU; +case Intrinsic::xtensa_ae_l16m_xc: +return Xtensa::AE_L16M_XC; +case Intrinsic::xtensa_ae_l16m_xu: +return Xtensa::AE_L16M_XU; +case Intrinsic::xtensa_ae_l16x2m_iu: +return Xtensa::AE_L16X2M_IU; +case Intrinsic::xtensa_ae_l16x2m_xc: +return Xtensa::AE_L16X2M_XC; +case Intrinsic::xtensa_ae_l16x2m_xu: +return Xtensa::AE_L16X2M_XU; +case Intrinsic::xtensa_ae_l16x4_ip: +return Xtensa::AE_L16X4_IP; +case Intrinsic::xtensa_ae_l16x4_ric: +return Xtensa::AE_L16X4_RIC; +case Intrinsic::xtensa_ae_l16x4_rip: +return Xtensa::AE_L16X4_RIP; +case Intrinsic::xtensa_ae_l16x4_xc: +return Xtensa::AE_L16X4_XC; +case Intrinsic::xtensa_ae_l16x4_xp: +return Xtensa::AE_L16X4_XP; +case Intrinsic::xtensa_ae_l32_ip: +return Xtensa::AE_L32_IP; +case Intrinsic::xtensa_ae_l32_xc: +return Xtensa::AE_L32_XC; +case Intrinsic::xtensa_ae_l32_xp: +return Xtensa::AE_L32_XP; +case Intrinsic::xtensa_ae_l32f24_ip: +return Xtensa::AE_L32F24_IP; +case Intrinsic::xtensa_ae_l32f24_xc: +return Xtensa::AE_L32F24_XC; +case Intrinsic::xtensa_ae_l32f24_xp: +return Xtensa::AE_L32F24_XP; +case Intrinsic::xtensa_ae_l32m_iu: +return Xtensa::AE_L32M_IU; +case Intrinsic::xtensa_ae_l32m_xc: +return Xtensa::AE_L32M_XC; +case Intrinsic::xtensa_ae_l32m_xu: +return Xtensa::AE_L32M_XU; +case Intrinsic::xtensa_ae_l32x2_ip: +return Xtensa::AE_L32X2_IP; +case Intrinsic::xtensa_ae_l32x2_ric: +return Xtensa::AE_L32X2_RIC; +case Intrinsic::xtensa_ae_l32x2_rip: +return Xtensa::AE_L32X2_RIP; +case Intrinsic::xtensa_ae_l32x2_xc: +return Xtensa::AE_L32X2_XC; +case Intrinsic::xtensa_ae_l32x2_xp: +return Xtensa::AE_L32X2_XP; +case Intrinsic::xtensa_ae_l32x2f24_ip: +return Xtensa::AE_L32X2F24_IP; +case Intrinsic::xtensa_ae_l32x2f24_ric: +return Xtensa::AE_L32X2F24_RIC; +case Intrinsic::xtensa_ae_l32x2f24_rip: +return Xtensa::AE_L32X2F24_RIP; +case Intrinsic::xtensa_ae_l32x2f24_xc: +return Xtensa::AE_L32X2F24_XC; +case Intrinsic::xtensa_ae_l32x2f24_xp: +return Xtensa::AE_L32X2F24_XP; +case Intrinsic::xtensa_ae_l64_ip: +return Xtensa::AE_L64_IP; +case Intrinsic::xtensa_ae_l64_xc: +return Xtensa::AE_L64_XC; +case Intrinsic::xtensa_ae_l64_xp: +return Xtensa::AE_L64_XP; +case Intrinsic::xtensa_ae_la16x4_ic: +return Xtensa::AE_LA16X4_IC; +case Intrinsic::xtensa_ae_la16x4_ip: +return Xtensa::AE_LA16X4_IP; +case Intrinsic::xtensa_ae_la16x4_ric: +return Xtensa::AE_LA16X4_RIC; +case Intrinsic::xtensa_ae_la16x4_rip: +return Xtensa::AE_LA16X4_RIP; +case Intrinsic::xtensa_ae_la16x4neg_pc: +return Xtensa::AE_LA16X4NEG_PC; +case Intrinsic::xtensa_ae_la16x4pos_pc: +return Xtensa::AE_LA16X4POS_PC; +case Intrinsic::xtensa_ae_la24_ic: +return Xtensa::AE_LA24_IC; +case Intrinsic::xtensa_ae_la24_ip: +return Xtensa::AE_LA24_IP; +case Intrinsic::xtensa_ae_la24_ric: +return Xtensa::AE_LA24_RIC; +case Intrinsic::xtensa_ae_la24_rip: +return Xtensa::AE_LA24_RIP; +case Intrinsic::xtensa_ae_la24neg_pc: +return Xtensa::AE_LA24NEG_PC; +case Intrinsic::xtensa_ae_la24pos_pc: +return Xtensa::AE_LA24POS_PC; +case Intrinsic::xtensa_ae_la24x2_ic: +return Xtensa::AE_LA24X2_IC; +case Intrinsic::xtensa_ae_la24x2_ip: +return Xtensa::AE_LA24X2_IP; +case Intrinsic::xtensa_ae_la24x2_ric: +return Xtensa::AE_LA24X2_RIC; +case Intrinsic::xtensa_ae_la24x2_rip: +return Xtensa::AE_LA24X2_RIP; +case Intrinsic::xtensa_ae_la24x2neg_pc: +return Xtensa::AE_LA24X2NEG_PC; +case Intrinsic::xtensa_ae_la24x2pos_pc: +return Xtensa::AE_LA24X2POS_PC; +case Intrinsic::xtensa_ae_la32x2_ic: +return Xtensa::AE_LA32X2_IC; +case Intrinsic::xtensa_ae_la32x2_ip: +return Xtensa::AE_LA32X2_IP; +case Intrinsic::xtensa_ae_la32x2_ric: +return Xtensa::AE_LA32X2_RIC; +case Intrinsic::xtensa_ae_la32x2_rip: +return Xtensa::AE_LA32X2_RIP; +case Intrinsic::xtensa_ae_la32x2f24_ic: +return Xtensa::AE_LA32X2F24_IC; +case Intrinsic::xtensa_ae_la32x2f24_ip: +return Xtensa::AE_LA32X2F24_IP; +case Intrinsic::xtensa_ae_la32x2f24_ric: +return Xtensa::AE_LA32X2F24_RIC; +case Intrinsic::xtensa_ae_la32x2f24_rip: +return Xtensa::AE_LA32X2F24_RIP; +case Intrinsic::xtensa_ae_la32x2neg_pc: +return Xtensa::AE_LA32X2NEG_PC; +case Intrinsic::xtensa_ae_la32x2pos_pc: +return Xtensa::AE_LA32X2POS_PC; +case Intrinsic::xtensa_ae_mul16x4: +return Xtensa::AE_MUL16X4; +case Intrinsic::xtensa_ae_mula16x4: +return Xtensa::AE_MULA16X4; +case Intrinsic::xtensa_ae_mulaf16x4ss: +return Xtensa::AE_MULAF16X4SS; +case Intrinsic::xtensa_ae_mulafd24x2_fir_h: +return Xtensa::AE_MULAFD24X2_FIR_H; +case Intrinsic::xtensa_ae_mulafd24x2_fir_l: +return Xtensa::AE_MULAFD24X2_FIR_L; +case Intrinsic::xtensa_ae_mulafd32x16x2_fir_hh: +return Xtensa::AE_MULAFD32X16X2_FIR_HH; +case Intrinsic::xtensa_ae_mulafd32x16x2_fir_hl: +return Xtensa::AE_MULAFD32X16X2_FIR_HL; +case Intrinsic::xtensa_ae_mulafd32x16x2_fir_lh: +return Xtensa::AE_MULAFD32X16X2_FIR_LH; +case Intrinsic::xtensa_ae_mulafd32x16x2_fir_ll: +return Xtensa::AE_MULAFD32X16X2_FIR_LL; +case Intrinsic::xtensa_ae_mulf16x4ss: +return Xtensa::AE_MULF16X4SS; +case Intrinsic::xtensa_ae_mulfd24x2_fir_h: +return Xtensa::AE_MULFD24X2_FIR_H; +case Intrinsic::xtensa_ae_mulfd24x2_fir_l: +return Xtensa::AE_MULFD24X2_FIR_L; +case Intrinsic::xtensa_ae_mulfd32x16x2_fir_hh: +return Xtensa::AE_MULFD32X16X2_FIR_HH; +case Intrinsic::xtensa_ae_mulfd32x16x2_fir_hl: +return Xtensa::AE_MULFD32X16X2_FIR_HL; +case Intrinsic::xtensa_ae_mulfd32x16x2_fir_lh: +return Xtensa::AE_MULFD32X16X2_FIR_LH; +case Intrinsic::xtensa_ae_mulfd32x16x2_fir_ll: +return Xtensa::AE_MULFD32X16X2_FIR_LL; +case Intrinsic::xtensa_ae_muls16x4: +return Xtensa::AE_MULS16X4; +case Intrinsic::xtensa_ae_mulsf16x4ss: +return Xtensa::AE_MULSF16X4SS; +case Intrinsic::xtensa_ae_sa16x4_ic: +return Xtensa::AE_SA16X4_IC; +case Intrinsic::xtensa_ae_sa16x4_ip: +return Xtensa::AE_SA16X4_IP; +case Intrinsic::xtensa_ae_sa16x4_ric: +return Xtensa::AE_SA16X4_RIC; +case Intrinsic::xtensa_ae_sa16x4_rip: +return Xtensa::AE_SA16X4_RIP; +case Intrinsic::xtensa_ae_sa24_l_ic: +return Xtensa::AE_SA24_L_IC; +case Intrinsic::xtensa_ae_sa24_l_ip: +return Xtensa::AE_SA24_L_IP; +case Intrinsic::xtensa_ae_sa24_l_ric: +return Xtensa::AE_SA24_L_RIC; +case Intrinsic::xtensa_ae_sa24_l_rip: +return Xtensa::AE_SA24_L_RIP; +case Intrinsic::xtensa_ae_sa24x2_ic: +return Xtensa::AE_SA24X2_IC; +case Intrinsic::xtensa_ae_sa24x2_ip: +return Xtensa::AE_SA24X2_IP; +case Intrinsic::xtensa_ae_sa24x2_ric: +return Xtensa::AE_SA24X2_RIC; +case Intrinsic::xtensa_ae_sa24x2_rip: +return Xtensa::AE_SA24X2_RIP; +case Intrinsic::xtensa_ae_sa32x2_ic: +return Xtensa::AE_SA32X2_IC; +case Intrinsic::xtensa_ae_sa32x2_ip: +return Xtensa::AE_SA32X2_IP; +case Intrinsic::xtensa_ae_sa32x2_ric: +return Xtensa::AE_SA32X2_RIC; +case Intrinsic::xtensa_ae_sa32x2_rip: +return Xtensa::AE_SA32X2_RIP; +case Intrinsic::xtensa_ae_sa32x2f24_ic: +return Xtensa::AE_SA32X2F24_IC; +case Intrinsic::xtensa_ae_sa32x2f24_ip: +return Xtensa::AE_SA32X2F24_IP; +case Intrinsic::xtensa_ae_sa32x2f24_ric: +return Xtensa::AE_SA32X2F24_RIC; +case Intrinsic::xtensa_ae_sa32x2f24_rip: +return Xtensa::AE_SA32X2F24_RIP; +case Intrinsic::xtensa_ae_vldl16t: +return Xtensa::AE_VLDL16T; +case Intrinsic::xtensa_ae_vldl32t: +return Xtensa::AE_VLDL32T; +case Intrinsic::xtensa_ae_vlel16t: +return Xtensa::AE_VLEL16T; +case Intrinsic::xtensa_ae_vlel32t: +return Xtensa::AE_VLEL32T; diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 2f5f516779ed6d..da4e4958173369 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; @@ -170,6 +171,20 @@ FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM, return new XtensaDAGToDAGISel(TM, OptLevel); } +static std::optional GetXtensaIntrinsic(unsigned IntNo) { + switch (IntNo) { +#include "XtensaHIFIIntrinsics.inc" + case Intrinsic::xtensa_xt_lsxp: + return Xtensa::LSXP; + break; + case Intrinsic::xtensa_xt_lsip: + return Xtensa::LSIP; + break; + default: + return std::nullopt; + } +} + void XtensaDAGToDAGISel::Select(SDNode *Node) { unsigned Opcode = Node->getOpcode(); SDLoc DL(Node); @@ -421,28 +436,38 @@ void XtensaDAGToDAGISel::Select(SDNode *Node) { } break; } + case ISD::INTRINSIC_WO_CHAIN: { + unsigned IntNo = cast(Node->getOperand(0))->getZExtValue(); + auto OpCodeRes = GetXtensaIntrinsic(IntNo); + unsigned OpCode; + if (OpCodeRes) { + OpCode = *OpCodeRes; + } else { + break; + } + + auto ResTys = Node->getVTList(); + + SmallVector Ops; + for (unsigned i = 1; i < Node->getNumOperands(); i++) + Ops.push_back(Node->getOperand(i)); + SDNode *NewNode = CurDAG->getMachineNode(OpCode, DL, ResTys, Ops); + + ReplaceNode(Node, NewNode); + return; + } case ISD::INTRINSIC_W_CHAIN: { unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); unsigned OpCode = 0; - bool Skip = false; - - switch (IntNo) { - default: - Skip = true; - break; - case Intrinsic::xtensa_xt_lsxp: - OpCode = Xtensa::LSXP; - break; - case Intrinsic::xtensa_xt_lsip: - OpCode = Xtensa::LSIP; + auto OpCodeRes = GetXtensaIntrinsic(IntNo); + if (OpCodeRes) { + OpCode = *OpCodeRes; + } else { break; } - if (Skip) - break; SDValue Chain = Node->getOperand(0); - auto ResTys = Node->getVTList(); SmallVector Ops; diff --git a/llvm/test/CodeGen/Xtensa/xtensa-hifi-intrinsics.ll b/llvm/test/CodeGen/Xtensa/xtensa-hifi-intrinsics.ll new file mode 100644 index 00000000000000..14925a5e1d472a --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/xtensa-hifi-intrinsics.ll @@ -0,0 +1,12298 @@ +; RUN: split-file %s %t +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_abs16s.ll -o - | FileCheck %t/ae_abs16s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_abs24s.ll -o - | FileCheck %t/ae_abs24s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_abs32.ll -o - | FileCheck %t/ae_abs32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_abs32s.ll -o - | FileCheck %t/ae_abs32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_abs64.ll -o - | FileCheck %t/ae_abs64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_abs64s.ll -o - | FileCheck %t/ae_abs64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_add16.ll -o - | FileCheck %t/ae_add16.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_add16s.ll -o - | FileCheck %t/ae_add16s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_add24s.ll -o - | FileCheck %t/ae_add24s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_add32.ll -o - | FileCheck %t/ae_add32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_add32_hl_lh.ll -o - | FileCheck %t/ae_add32_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_add32s.ll -o - | FileCheck %t/ae_add32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_add64.ll -o - | FileCheck %t/ae_add64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_add64s.ll -o - | FileCheck %t/ae_add64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_addbrba32.ll -o - | FileCheck %t/ae_addbrba32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_addsub32.ll -o - | FileCheck %t/ae_addsub32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_addsub32s.ll -o - | FileCheck %t/ae_addsub32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_and.ll -o - | FileCheck %t/ae_and.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvt32x2f16_10.ll -o - | FileCheck %t/ae_cvt32x2f16_10.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvt32x2f16_32.ll -o - | FileCheck %t/ae_cvt32x2f16_32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvt48a32.ll -o - | FileCheck %t/ae_cvt48a32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvt64a32.ll -o - | FileCheck %t/ae_cvt64a32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvt64f32_h.ll -o - | FileCheck %t/ae_cvt64f32_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvta32f24s_h.ll -o - | FileCheck %t/ae_cvta32f24s_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvta32f24s_l.ll -o - | FileCheck %t/ae_cvta32f24s_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvtq56a32s.ll -o - | FileCheck %t/ae_cvtq56a32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvtq56p32s_h.ll -o - | FileCheck %t/ae_cvtq56p32s_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_cvtq56p32s_l.ll -o - | FileCheck %t/ae_cvtq56p32s_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_db.ll -o - | FileCheck %t/ae_db.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_db_ic.ll -o - | FileCheck %t/ae_db_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_db_ip.ll -o - | FileCheck %t/ae_db_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_dbi.ll -o - | FileCheck %t/ae_dbi.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_dbi_ic.ll -o - | FileCheck %t/ae_dbi_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_dbi_ip.ll -o - | FileCheck %t/ae_dbi_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_div64d32_h.ll -o - | FileCheck %t/ae_div64d32_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_div64d32_l.ll -o - | FileCheck %t/ae_div64d32_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_eq64.ll -o - | FileCheck %t/ae_eq64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16_i.ll -o - | FileCheck %t/ae_l16_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16_ip.ll -o - | FileCheck %t/ae_l16_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16_x.ll -o - | FileCheck %t/ae_l16_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16_xc.ll -o - | FileCheck %t/ae_l16_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16_xp.ll -o - | FileCheck %t/ae_l16_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16m_i.ll -o - | FileCheck %t/ae_l16m_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16m_iu.ll -o - | FileCheck %t/ae_l16m_iu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16m_x.ll -o - | FileCheck %t/ae_l16m_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16m_xc.ll -o - | FileCheck %t/ae_l16m_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16m_xu.ll -o - | FileCheck %t/ae_l16m_xu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x2m_i.ll -o - | FileCheck %t/ae_l16x2m_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x2m_iu.ll -o - | FileCheck %t/ae_l16x2m_iu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x2m_x.ll -o - | FileCheck %t/ae_l16x2m_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x2m_xc.ll -o - | FileCheck %t/ae_l16x2m_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x2m_xu.ll -o - | FileCheck %t/ae_l16x2m_xu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x4_i.ll -o - | FileCheck %t/ae_l16x4_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x4_ip.ll -o - | FileCheck %t/ae_l16x4_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x4_ric.ll -o - | FileCheck %t/ae_l16x4_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x4_rip.ll -o - | FileCheck %t/ae_l16x4_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x4_x.ll -o - | FileCheck %t/ae_l16x4_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x4_xc.ll -o - | FileCheck %t/ae_l16x4_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l16x4_xp.ll -o - | FileCheck %t/ae_l16x4_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32_i.ll -o - | FileCheck %t/ae_l32_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32_ip.ll -o - | FileCheck %t/ae_l32_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32_x.ll -o - | FileCheck %t/ae_l32_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32_xc.ll -o - | FileCheck %t/ae_l32_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32_xp.ll -o - | FileCheck %t/ae_l32_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32f24_i.ll -o - | FileCheck %t/ae_l32f24_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32f24_ip.ll -o - | FileCheck %t/ae_l32f24_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32f24_x.ll -o - | FileCheck %t/ae_l32f24_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32f24_xc.ll -o - | FileCheck %t/ae_l32f24_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32f24_xp.ll -o - | FileCheck %t/ae_l32f24_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32m_i.ll -o - | FileCheck %t/ae_l32m_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32m_iu.ll -o - | FileCheck %t/ae_l32m_iu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32m_x.ll -o - | FileCheck %t/ae_l32m_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32m_xc.ll -o - | FileCheck %t/ae_l32m_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32m_xu.ll -o - | FileCheck %t/ae_l32m_xu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2_i.ll -o - | FileCheck %t/ae_l32x2_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2_ip.ll -o - | FileCheck %t/ae_l32x2_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2_ric.ll -o - | FileCheck %t/ae_l32x2_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2_rip.ll -o - | FileCheck %t/ae_l32x2_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2_x.ll -o - | FileCheck %t/ae_l32x2_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2_xc.ll -o - | FileCheck %t/ae_l32x2_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2_xp.ll -o - | FileCheck %t/ae_l32x2_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2f24_i.ll -o - | FileCheck %t/ae_l32x2f24_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2f24_ip.ll -o - | FileCheck %t/ae_l32x2f24_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2f24_ric.ll -o - | FileCheck %t/ae_l32x2f24_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2f24_rip.ll -o - | FileCheck %t/ae_l32x2f24_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2f24_x.ll -o - | FileCheck %t/ae_l32x2f24_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2f24_xc.ll -o - | FileCheck %t/ae_l32x2f24_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l32x2f24_xp.ll -o - | FileCheck %t/ae_l32x2f24_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l64_i.ll -o - | FileCheck %t/ae_l64_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l64_ip.ll -o - | FileCheck %t/ae_l64_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l64_x.ll -o - | FileCheck %t/ae_l64_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l64_xc.ll -o - | FileCheck %t/ae_l64_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_l64_xp.ll -o - | FileCheck %t/ae_l64_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la16x4_ic.ll -o - | FileCheck %t/ae_la16x4_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la16x4_ip.ll -o - | FileCheck %t/ae_la16x4_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la16x4_ric.ll -o - | FileCheck %t/ae_la16x4_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la16x4_rip.ll -o - | FileCheck %t/ae_la16x4_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la16x4neg_pc.ll -o - | FileCheck %t/ae_la16x4neg_pc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la16x4pos_pc.ll -o - | FileCheck %t/ae_la16x4pos_pc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24_ic.ll -o - | FileCheck %t/ae_la24_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24_ip.ll -o - | FileCheck %t/ae_la24_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24_ric.ll -o - | FileCheck %t/ae_la24_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24_rip.ll -o - | FileCheck %t/ae_la24_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24neg_pc.ll -o - | FileCheck %t/ae_la24neg_pc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24pos_pc.ll -o - | FileCheck %t/ae_la24pos_pc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24x2_ic.ll -o - | FileCheck %t/ae_la24x2_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24x2_ip.ll -o - | FileCheck %t/ae_la24x2_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24x2_ric.ll -o - | FileCheck %t/ae_la24x2_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24x2_rip.ll -o - | FileCheck %t/ae_la24x2_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24x2neg_pc.ll -o - | FileCheck %t/ae_la24x2neg_pc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la24x2pos_pc.ll -o - | FileCheck %t/ae_la24x2pos_pc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2_ic.ll -o - | FileCheck %t/ae_la32x2_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2_ip.ll -o - | FileCheck %t/ae_la32x2_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2_ric.ll -o - | FileCheck %t/ae_la32x2_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2_rip.ll -o - | FileCheck %t/ae_la32x2_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2f24_ic.ll -o - | FileCheck %t/ae_la32x2f24_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2f24_ip.ll -o - | FileCheck %t/ae_la32x2f24_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2f24_ric.ll -o - | FileCheck %t/ae_la32x2f24_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2f24_rip.ll -o - | FileCheck %t/ae_la32x2f24_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2neg_pc.ll -o - | FileCheck %t/ae_la32x2neg_pc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la32x2pos_pc.ll -o - | FileCheck %t/ae_la32x2pos_pc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_la64_pp.ll -o - | FileCheck %t/ae_la64_pp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_lalign64_i.ll -o - | FileCheck %t/ae_lalign64_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_lb.ll -o - | FileCheck %t/ae_lb.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_lbi.ll -o - | FileCheck %t/ae_lbi.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_lbk.ll -o - | FileCheck %t/ae_lbk.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_lbki.ll -o - | FileCheck %t/ae_lbki.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_lbs.ll -o - | FileCheck %t/ae_lbs.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_lbsi.ll -o - | FileCheck %t/ae_lbsi.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_le64.ll -o - | FileCheck %t/ae_le64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_lt64.ll -o - | FileCheck %t/ae_lt64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_max32.ll -o - | FileCheck %t/ae_max32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_max64.ll -o - | FileCheck %t/ae_max64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_maxabs32s.ll -o - | FileCheck %t/ae_maxabs32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_maxabs64s.ll -o - | FileCheck %t/ae_maxabs64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_min32.ll -o - | FileCheck %t/ae_min32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_min64.ll -o - | FileCheck %t/ae_min64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_minabs32s.ll -o - | FileCheck %t/ae_minabs32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_minabs64s.ll -o - | FileCheck %t/ae_minabs64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mov.ll -o - | FileCheck %t/ae_mov.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movad16_0.ll -o - | FileCheck %t/ae_movad16_0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movad16_1.ll -o - | FileCheck %t/ae_movad16_1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movad16_2.ll -o - | FileCheck %t/ae_movad16_2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movad16_3.ll -o - | FileCheck %t/ae_movad16_3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movad32_h.ll -o - | FileCheck %t/ae_movad32_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movad32_l.ll -o - | FileCheck %t/ae_movad32_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movalign.ll -o - | FileCheck %t/ae_movalign.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movda16.ll -o - | FileCheck %t/ae_movda16.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movda16x2.ll -o - | FileCheck %t/ae_movda16x2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movda32.ll -o - | FileCheck %t/ae_movda32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movda32x2.ll -o - | FileCheck %t/ae_movda32x2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movf64.ll -o - | FileCheck %t/ae_movf64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movi.ll -o - | FileCheck %t/ae_movi.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_movt64.ll -o - | FileCheck %t/ae_movt64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul16x4.ll -o - | FileCheck %t/ae_mul16x4.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32_hh.ll -o - | FileCheck %t/ae_mul32_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32_lh.ll -o - | FileCheck %t/ae_mul32_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32_ll.ll -o - | FileCheck %t/ae_mul32_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32_ll_s2.ll -o - | FileCheck %t/ae_mul32_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32u_ll.ll -o - | FileCheck %t/ae_mul32u_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_h0.ll -o - | FileCheck %t/ae_mul32x16_h0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_h0_s2.ll -o - | FileCheck %t/ae_mul32x16_h0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_h1.ll -o - | FileCheck %t/ae_mul32x16_h1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_h1_s2.ll -o - | FileCheck %t/ae_mul32x16_h1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_h2.ll -o - | FileCheck %t/ae_mul32x16_h2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_h2_s2.ll -o - | FileCheck %t/ae_mul32x16_h2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_h3.ll -o - | FileCheck %t/ae_mul32x16_h3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_h3_s2.ll -o - | FileCheck %t/ae_mul32x16_h3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_l0.ll -o - | FileCheck %t/ae_mul32x16_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_l0_s2.ll -o - | FileCheck %t/ae_mul32x16_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_l1.ll -o - | FileCheck %t/ae_mul32x16_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_l1_s2.ll -o - | FileCheck %t/ae_mul32x16_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_l2.ll -o - | FileCheck %t/ae_mul32x16_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_l2_s2.ll -o - | FileCheck %t/ae_mul32x16_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_l3.ll -o - | FileCheck %t/ae_mul32x16_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mul32x16_l3_s2.ll -o - | FileCheck %t/ae_mul32x16_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula16x4.ll -o - | FileCheck %t/ae_mula16x4.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32_hh.ll -o - | FileCheck %t/ae_mula32_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32_lh.ll -o - | FileCheck %t/ae_mula32_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32_ll.ll -o - | FileCheck %t/ae_mula32_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32_ll_s2.ll -o - | FileCheck %t/ae_mula32_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32u_ll.ll -o - | FileCheck %t/ae_mula32u_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_h0.ll -o - | FileCheck %t/ae_mula32x16_h0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_h0_s2.ll -o - | FileCheck %t/ae_mula32x16_h0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_h1.ll -o - | FileCheck %t/ae_mula32x16_h1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_h1_s2.ll -o - | FileCheck %t/ae_mula32x16_h1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_h2.ll -o - | FileCheck %t/ae_mula32x16_h2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_h2_s2.ll -o - | FileCheck %t/ae_mula32x16_h2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_h3.ll -o - | FileCheck %t/ae_mula32x16_h3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_h3_s2.ll -o - | FileCheck %t/ae_mula32x16_h3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_l0.ll -o - | FileCheck %t/ae_mula32x16_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_l0_s2.ll -o - | FileCheck %t/ae_mula32x16_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_l1.ll -o - | FileCheck %t/ae_mula32x16_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_l1_s2.ll -o - | FileCheck %t/ae_mula32x16_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_l2.ll -o - | FileCheck %t/ae_mula32x16_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_l2_s2.ll -o - | FileCheck %t/ae_mula32x16_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_l3.ll -o - | FileCheck %t/ae_mula32x16_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mula32x16_l3_s2.ll -o - | FileCheck %t/ae_mula32x16_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad24_hh_ll.ll -o - | FileCheck %t/ae_mulaad24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulaad24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad24_hl_lh.ll -o - | FileCheck %t/ae_mulaad24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulaad24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad32x16_h0_l1.ll -o - | FileCheck %t/ae_mulaad32x16_h0_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad32x16_h0_l1_s2.ll -o - | FileCheck %t/ae_mulaad32x16_h0_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad32x16_h1_l0.ll -o - | FileCheck %t/ae_mulaad32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulaad32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad32x16_h2_l3.ll -o - | FileCheck %t/ae_mulaad32x16_h2_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad32x16_h2_l3_s2.ll -o - | FileCheck %t/ae_mulaad32x16_h2_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad32x16_h3_l2.ll -o - | FileCheck %t/ae_mulaad32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaad32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulaad32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd16ss_11_00.ll -o - | FileCheck %t/ae_mulaafd16ss_11_00.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd16ss_11_00_s2.ll -o - | FileCheck %t/ae_mulaafd16ss_11_00_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd16ss_13_02.ll -o - | FileCheck %t/ae_mulaafd16ss_13_02.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd16ss_13_02_s2.ll -o - | FileCheck %t/ae_mulaafd16ss_13_02_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd16ss_33_22.ll -o - | FileCheck %t/ae_mulaafd16ss_33_22.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd16ss_33_22_s2.ll -o - | FileCheck %t/ae_mulaafd16ss_33_22_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd24_hh_ll.ll -o - | FileCheck %t/ae_mulaafd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulaafd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd24_hl_lh.ll -o - | FileCheck %t/ae_mulaafd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulaafd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd32x16_h0_l1.ll -o - | FileCheck %t/ae_mulaafd32x16_h0_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd32x16_h0_l1_s2.ll -o - | FileCheck %t/ae_mulaafd32x16_h0_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulaafd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulaafd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd32x16_h2_l3.ll -o - | FileCheck %t/ae_mulaafd32x16_h2_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd32x16_h2_l3_s2.ll -o - | FileCheck %t/ae_mulaafd32x16_h2_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulaafd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaafd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulaafd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulac24.ll -o - | FileCheck %t/ae_mulac24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulac32x16_h.ll -o - | FileCheck %t/ae_mulac32x16_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulac32x16_l.ll -o - | FileCheck %t/ae_mulac32x16_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_00.ll -o - | FileCheck %t/ae_mulaf16ss_00.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_00_s2.ll -o - | FileCheck %t/ae_mulaf16ss_00_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_10.ll -o - | FileCheck %t/ae_mulaf16ss_10.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_11.ll -o - | FileCheck %t/ae_mulaf16ss_11.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_20.ll -o - | FileCheck %t/ae_mulaf16ss_20.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_21.ll -o - | FileCheck %t/ae_mulaf16ss_21.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_22.ll -o - | FileCheck %t/ae_mulaf16ss_22.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_30.ll -o - | FileCheck %t/ae_mulaf16ss_30.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_31.ll -o - | FileCheck %t/ae_mulaf16ss_31.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_32.ll -o - | FileCheck %t/ae_mulaf16ss_32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16ss_33.ll -o - | FileCheck %t/ae_mulaf16ss_33.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf16x4ss.ll -o - | FileCheck %t/ae_mulaf16x4ss.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32r_hh.ll -o - | FileCheck %t/ae_mulaf32r_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32r_lh.ll -o - | FileCheck %t/ae_mulaf32r_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32r_ll.ll -o - | FileCheck %t/ae_mulaf32r_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32r_ll_s2.ll -o - | FileCheck %t/ae_mulaf32r_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32s_hh.ll -o - | FileCheck %t/ae_mulaf32s_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32s_lh.ll -o - | FileCheck %t/ae_mulaf32s_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32s_ll.ll -o - | FileCheck %t/ae_mulaf32s_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32s_ll_s2.ll -o - | FileCheck %t/ae_mulaf32s_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_h0.ll -o - | FileCheck %t/ae_mulaf32x16_h0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_h0_s2.ll -o - | FileCheck %t/ae_mulaf32x16_h0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_h1.ll -o - | FileCheck %t/ae_mulaf32x16_h1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_h1_s2.ll -o - | FileCheck %t/ae_mulaf32x16_h1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_h2.ll -o - | FileCheck %t/ae_mulaf32x16_h2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_h2_s2.ll -o - | FileCheck %t/ae_mulaf32x16_h2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_h3.ll -o - | FileCheck %t/ae_mulaf32x16_h3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_h3_s2.ll -o - | FileCheck %t/ae_mulaf32x16_h3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_l0.ll -o - | FileCheck %t/ae_mulaf32x16_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_l0_s2.ll -o - | FileCheck %t/ae_mulaf32x16_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_l1.ll -o - | FileCheck %t/ae_mulaf32x16_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_l1_s2.ll -o - | FileCheck %t/ae_mulaf32x16_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_l2.ll -o - | FileCheck %t/ae_mulaf32x16_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_l2_s2.ll -o - | FileCheck %t/ae_mulaf32x16_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_l3.ll -o - | FileCheck %t/ae_mulaf32x16_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf32x16_l3_s2.ll -o - | FileCheck %t/ae_mulaf32x16_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf48q32sp16s_l.ll -o - | FileCheck %t/ae_mulaf48q32sp16s_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf48q32sp16s_l_s2.ll -o - | FileCheck %t/ae_mulaf48q32sp16s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf48q32sp16u_l.ll -o - | FileCheck %t/ae_mulaf48q32sp16u_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaf48q32sp16u_l_s2.ll -o - | FileCheck %t/ae_mulaf48q32sp16u_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafc24ra.ll -o - | FileCheck %t/ae_mulafc24ra.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafc32x16ras_h.ll -o - | FileCheck %t/ae_mulafc32x16ras_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafc32x16ras_l.ll -o - | FileCheck %t/ae_mulafc32x16ras_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafd24x2_fir_h.ll -o - | FileCheck %t/ae_mulafd24x2_fir_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafd24x2_fir_l.ll -o - | FileCheck %t/ae_mulafd24x2_fir_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafd32x16x2_fir_hh.ll -o - | FileCheck %t/ae_mulafd32x16x2_fir_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafd32x16x2_fir_hl.ll -o - | FileCheck %t/ae_mulafd32x16x2_fir_hl.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafd32x16x2_fir_lh.ll -o - | FileCheck %t/ae_mulafd32x16x2_fir_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafd32x16x2_fir_ll.ll -o - | FileCheck %t/ae_mulafd32x16x2_fir_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp24x2r.ll -o - | FileCheck %t/ae_mulafp24x2r.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp24x2r_s2.ll -o - | FileCheck %t/ae_mulafp24x2r_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp24x2ra.ll -o - | FileCheck %t/ae_mulafp24x2ra.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp24x2ra_s2.ll -o - | FileCheck %t/ae_mulafp24x2ra_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x16x2ras_h.ll -o - | FileCheck %t/ae_mulafp32x16x2ras_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x16x2ras_h_s2.ll -o - | FileCheck %t/ae_mulafp32x16x2ras_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x16x2ras_l.ll -o - | FileCheck %t/ae_mulafp32x16x2ras_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x16x2ras_l_s2.ll -o - | FileCheck %t/ae_mulafp32x16x2ras_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x16x2rs_h.ll -o - | FileCheck %t/ae_mulafp32x16x2rs_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x16x2rs_h_s2.ll -o - | FileCheck %t/ae_mulafp32x16x2rs_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x16x2rs_l.ll -o - | FileCheck %t/ae_mulafp32x16x2rs_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x16x2rs_l_s2.ll -o - | FileCheck %t/ae_mulafp32x16x2rs_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x2ras.ll -o - | FileCheck %t/ae_mulafp32x2ras.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafp32x2rs.ll -o - | FileCheck %t/ae_mulafp32x2rs.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafq32sp24s_h_s2.ll -o - | FileCheck %t/ae_mulafq32sp24s_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulafq32sp24s_l_s2.ll -o - | FileCheck %t/ae_mulafq32sp24s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulap24x2.ll -o - | FileCheck %t/ae_mulap24x2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulap24x2_s2.ll -o - | FileCheck %t/ae_mulap24x2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulap32x16x2_h.ll -o - | FileCheck %t/ae_mulap32x16x2_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulap32x16x2_l.ll -o - | FileCheck %t/ae_mulap32x16x2_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulap32x2.ll -o - | FileCheck %t/ae_mulap32x2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaq32sp16s_l_s2.ll -o - | FileCheck %t/ae_mulaq32sp16s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulaq32sp16u_l_s2.ll -o - | FileCheck %t/ae_mulaq32sp16u_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mularfq32sp24s_h_s2.ll -o - | FileCheck %t/ae_mularfq32sp24s_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mularfq32sp24s_l_s2.ll -o - | FileCheck %t/ae_mularfq32sp24s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulas32f48p16s_hh.ll -o - | FileCheck %t/ae_mulas32f48p16s_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulas32f48p16s_hh_s2.ll -o - | FileCheck %t/ae_mulas32f48p16s_hh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulas32f48p16s_lh.ll -o - | FileCheck %t/ae_mulas32f48p16s_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulas32f48p16s_lh_s2.ll -o - | FileCheck %t/ae_mulas32f48p16s_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulas32f48p16s_ll.ll -o - | FileCheck %t/ae_mulas32f48p16s_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulas32f48p16s_ll_s2.ll -o - | FileCheck %t/ae_mulas32f48p16s_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasd24_hh_ll.ll -o - | FileCheck %t/ae_mulasd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulasd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasd24_hl_lh.ll -o - | FileCheck %t/ae_mulasd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulasd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulasd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulasd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulasd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulasd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasfd24_hh_ll.ll -o - | FileCheck %t/ae_mulasfd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasfd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulasfd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasfd24_hl_lh.ll -o - | FileCheck %t/ae_mulasfd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasfd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulasfd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasfd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulasfd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasfd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulasfd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasfd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulasfd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulasfd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulasfd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulc24.ll -o - | FileCheck %t/ae_mulc24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulc32x16_h.ll -o - | FileCheck %t/ae_mulc32x16_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulc32x16_l.ll -o - | FileCheck %t/ae_mulc32x16_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_00.ll -o - | FileCheck %t/ae_mulf16ss_00.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_00_s2.ll -o - | FileCheck %t/ae_mulf16ss_00_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_10.ll -o - | FileCheck %t/ae_mulf16ss_10.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_11.ll -o - | FileCheck %t/ae_mulf16ss_11.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_20.ll -o - | FileCheck %t/ae_mulf16ss_20.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_21.ll -o - | FileCheck %t/ae_mulf16ss_21.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_22.ll -o - | FileCheck %t/ae_mulf16ss_22.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_30.ll -o - | FileCheck %t/ae_mulf16ss_30.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_31.ll -o - | FileCheck %t/ae_mulf16ss_31.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_32.ll -o - | FileCheck %t/ae_mulf16ss_32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16ss_33.ll -o - | FileCheck %t/ae_mulf16ss_33.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf16x4ss.ll -o - | FileCheck %t/ae_mulf16x4ss.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32r_hh.ll -o - | FileCheck %t/ae_mulf32r_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32r_lh.ll -o - | FileCheck %t/ae_mulf32r_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32r_ll.ll -o - | FileCheck %t/ae_mulf32r_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32r_ll_s2.ll -o - | FileCheck %t/ae_mulf32r_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32s_hh.ll -o - | FileCheck %t/ae_mulf32s_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32s_lh.ll -o - | FileCheck %t/ae_mulf32s_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32s_ll.ll -o - | FileCheck %t/ae_mulf32s_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32s_ll_s2.ll -o - | FileCheck %t/ae_mulf32s_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_h0.ll -o - | FileCheck %t/ae_mulf32x16_h0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_h0_s2.ll -o - | FileCheck %t/ae_mulf32x16_h0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_h1.ll -o - | FileCheck %t/ae_mulf32x16_h1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_h1_s2.ll -o - | FileCheck %t/ae_mulf32x16_h1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_h2.ll -o - | FileCheck %t/ae_mulf32x16_h2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_h2_s2.ll -o - | FileCheck %t/ae_mulf32x16_h2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_h3.ll -o - | FileCheck %t/ae_mulf32x16_h3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_h3_s2.ll -o - | FileCheck %t/ae_mulf32x16_h3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_l0.ll -o - | FileCheck %t/ae_mulf32x16_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_l0_s2.ll -o - | FileCheck %t/ae_mulf32x16_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_l1.ll -o - | FileCheck %t/ae_mulf32x16_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_l1_s2.ll -o - | FileCheck %t/ae_mulf32x16_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_l2.ll -o - | FileCheck %t/ae_mulf32x16_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_l2_s2.ll -o - | FileCheck %t/ae_mulf32x16_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_l3.ll -o - | FileCheck %t/ae_mulf32x16_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf32x16_l3_s2.ll -o - | FileCheck %t/ae_mulf32x16_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf48q32sp16s_l.ll -o - | FileCheck %t/ae_mulf48q32sp16s_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf48q32sp16s_l_s2.ll -o - | FileCheck %t/ae_mulf48q32sp16s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf48q32sp16u_l.ll -o - | FileCheck %t/ae_mulf48q32sp16u_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulf48q32sp16u_l_s2.ll -o - | FileCheck %t/ae_mulf48q32sp16u_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfc24ra.ll -o - | FileCheck %t/ae_mulfc24ra.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfc32x16ras_h.ll -o - | FileCheck %t/ae_mulfc32x16ras_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfc32x16ras_l.ll -o - | FileCheck %t/ae_mulfc32x16ras_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfd24x2_fir_h.ll -o - | FileCheck %t/ae_mulfd24x2_fir_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfd24x2_fir_l.ll -o - | FileCheck %t/ae_mulfd24x2_fir_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfd32x16x2_fir_hh.ll -o - | FileCheck %t/ae_mulfd32x16x2_fir_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfd32x16x2_fir_hl.ll -o - | FileCheck %t/ae_mulfd32x16x2_fir_hl.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfd32x16x2_fir_lh.ll -o - | FileCheck %t/ae_mulfd32x16x2_fir_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfd32x16x2_fir_ll.ll -o - | FileCheck %t/ae_mulfd32x16x2_fir_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp16x4ras.ll -o - | FileCheck %t/ae_mulfp16x4ras.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp16x4s.ll -o - | FileCheck %t/ae_mulfp16x4s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp24x2r.ll -o - | FileCheck %t/ae_mulfp24x2r.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp24x2r_s2.ll -o - | FileCheck %t/ae_mulfp24x2r_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp24x2ra.ll -o - | FileCheck %t/ae_mulfp24x2ra.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp24x2ra_s2.ll -o - | FileCheck %t/ae_mulfp24x2ra_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x16x2ras_h.ll -o - | FileCheck %t/ae_mulfp32x16x2ras_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x16x2ras_h_s2.ll -o - | FileCheck %t/ae_mulfp32x16x2ras_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x16x2ras_l.ll -o - | FileCheck %t/ae_mulfp32x16x2ras_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x16x2ras_l_s2.ll -o - | FileCheck %t/ae_mulfp32x16x2ras_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x16x2rs_h.ll -o - | FileCheck %t/ae_mulfp32x16x2rs_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x16x2rs_h_s2.ll -o - | FileCheck %t/ae_mulfp32x16x2rs_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x16x2rs_l.ll -o - | FileCheck %t/ae_mulfp32x16x2rs_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x16x2rs_l_s2.ll -o - | FileCheck %t/ae_mulfp32x16x2rs_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x2ras.ll -o - | FileCheck %t/ae_mulfp32x2ras.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfp32x2rs.ll -o - | FileCheck %t/ae_mulfp32x2rs.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfq32sp24s_h_s2.ll -o - | FileCheck %t/ae_mulfq32sp24s_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulfq32sp24s_l_s2.ll -o - | FileCheck %t/ae_mulfq32sp24s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulp24x2.ll -o - | FileCheck %t/ae_mulp24x2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulp24x2_s2.ll -o - | FileCheck %t/ae_mulp24x2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulp32x16x2_h.ll -o - | FileCheck %t/ae_mulp32x16x2_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulp32x16x2_l.ll -o - | FileCheck %t/ae_mulp32x16x2_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulp32x2.ll -o - | FileCheck %t/ae_mulp32x2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulq32sp16s_l_s2.ll -o - | FileCheck %t/ae_mulq32sp16s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulq32sp16u_l_s2.ll -o - | FileCheck %t/ae_mulq32sp16u_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulrfq32sp24s_h_s2.ll -o - | FileCheck %t/ae_mulrfq32sp24s_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulrfq32sp24s_l_s2.ll -o - | FileCheck %t/ae_mulrfq32sp24s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls16x4.ll -o - | FileCheck %t/ae_muls16x4.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32_hh.ll -o - | FileCheck %t/ae_muls32_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32_lh.ll -o - | FileCheck %t/ae_muls32_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32_ll.ll -o - | FileCheck %t/ae_muls32_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32f48p16s_hh.ll -o - | FileCheck %t/ae_muls32f48p16s_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32f48p16s_hh_s2.ll -o - | FileCheck %t/ae_muls32f48p16s_hh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32f48p16s_lh.ll -o - | FileCheck %t/ae_muls32f48p16s_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32f48p16s_lh_s2.ll -o - | FileCheck %t/ae_muls32f48p16s_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32f48p16s_ll.ll -o - | FileCheck %t/ae_muls32f48p16s_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32f48p16s_ll_s2.ll -o - | FileCheck %t/ae_muls32f48p16s_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32u_ll.ll -o - | FileCheck %t/ae_muls32u_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_h0.ll -o - | FileCheck %t/ae_muls32x16_h0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_h0_s2.ll -o - | FileCheck %t/ae_muls32x16_h0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_h1.ll -o - | FileCheck %t/ae_muls32x16_h1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_h1_s2.ll -o - | FileCheck %t/ae_muls32x16_h1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_h2.ll -o - | FileCheck %t/ae_muls32x16_h2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_h2_s2.ll -o - | FileCheck %t/ae_muls32x16_h2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_h3.ll -o - | FileCheck %t/ae_muls32x16_h3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_h3_s2.ll -o - | FileCheck %t/ae_muls32x16_h3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_l0.ll -o - | FileCheck %t/ae_muls32x16_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_l0_s2.ll -o - | FileCheck %t/ae_muls32x16_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_l1.ll -o - | FileCheck %t/ae_muls32x16_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_l1_s2.ll -o - | FileCheck %t/ae_muls32x16_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_l2.ll -o - | FileCheck %t/ae_muls32x16_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_l2_s2.ll -o - | FileCheck %t/ae_muls32x16_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_l3.ll -o - | FileCheck %t/ae_muls32x16_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_muls32x16_l3_s2.ll -o - | FileCheck %t/ae_muls32x16_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsad24_hh_ll.ll -o - | FileCheck %t/ae_mulsad24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsad24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulsad24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsad32x16_h1_l0.ll -o - | FileCheck %t/ae_mulsad32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsad32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulsad32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsad32x16_h3_l2.ll -o - | FileCheck %t/ae_mulsad32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsad32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulsad32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsafd24_hh_ll.ll -o - | FileCheck %t/ae_mulsafd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsafd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulsafd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsafd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulsafd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsafd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulsafd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsafd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulsafd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsafd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulsafd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_00.ll -o - | FileCheck %t/ae_mulsf16ss_00.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_00_s2.ll -o - | FileCheck %t/ae_mulsf16ss_00_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_10.ll -o - | FileCheck %t/ae_mulsf16ss_10.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_11.ll -o - | FileCheck %t/ae_mulsf16ss_11.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_20.ll -o - | FileCheck %t/ae_mulsf16ss_20.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_21.ll -o - | FileCheck %t/ae_mulsf16ss_21.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_22.ll -o - | FileCheck %t/ae_mulsf16ss_22.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_30.ll -o - | FileCheck %t/ae_mulsf16ss_30.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_31.ll -o - | FileCheck %t/ae_mulsf16ss_31.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_32.ll -o - | FileCheck %t/ae_mulsf16ss_32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16ss_33.ll -o - | FileCheck %t/ae_mulsf16ss_33.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf16x4ss.ll -o - | FileCheck %t/ae_mulsf16x4ss.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32r_hh.ll -o - | FileCheck %t/ae_mulsf32r_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32r_lh.ll -o - | FileCheck %t/ae_mulsf32r_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32r_ll.ll -o - | FileCheck %t/ae_mulsf32r_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32r_ll_s2.ll -o - | FileCheck %t/ae_mulsf32r_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32s_hh.ll -o - | FileCheck %t/ae_mulsf32s_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32s_lh.ll -o - | FileCheck %t/ae_mulsf32s_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32s_ll.ll -o - | FileCheck %t/ae_mulsf32s_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_h0.ll -o - | FileCheck %t/ae_mulsf32x16_h0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_h0_s2.ll -o - | FileCheck %t/ae_mulsf32x16_h0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_h1.ll -o - | FileCheck %t/ae_mulsf32x16_h1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_h1_s2.ll -o - | FileCheck %t/ae_mulsf32x16_h1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_h2.ll -o - | FileCheck %t/ae_mulsf32x16_h2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_h2_s2.ll -o - | FileCheck %t/ae_mulsf32x16_h2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_h3.ll -o - | FileCheck %t/ae_mulsf32x16_h3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_h3_s2.ll -o - | FileCheck %t/ae_mulsf32x16_h3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_l0.ll -o - | FileCheck %t/ae_mulsf32x16_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_l0_s2.ll -o - | FileCheck %t/ae_mulsf32x16_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_l1.ll -o - | FileCheck %t/ae_mulsf32x16_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_l1_s2.ll -o - | FileCheck %t/ae_mulsf32x16_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_l2.ll -o - | FileCheck %t/ae_mulsf32x16_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_l2_s2.ll -o - | FileCheck %t/ae_mulsf32x16_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_l3.ll -o - | FileCheck %t/ae_mulsf32x16_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf32x16_l3_s2.ll -o - | FileCheck %t/ae_mulsf32x16_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf48q32sp16s_l.ll -o - | FileCheck %t/ae_mulsf48q32sp16s_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf48q32sp16s_l_s2.ll -o - | FileCheck %t/ae_mulsf48q32sp16s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf48q32sp16u_l.ll -o - | FileCheck %t/ae_mulsf48q32sp16u_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsf48q32sp16u_l_s2.ll -o - | FileCheck %t/ae_mulsf48q32sp16u_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp24x2r.ll -o - | FileCheck %t/ae_mulsfp24x2r.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp24x2r_s2.ll -o - | FileCheck %t/ae_mulsfp24x2r_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp24x2ra.ll -o - | FileCheck %t/ae_mulsfp24x2ra.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp24x2ra_s2.ll -o - | FileCheck %t/ae_mulsfp24x2ra_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x16x2ras_h.ll -o - | FileCheck %t/ae_mulsfp32x16x2ras_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x16x2ras_h_s2.ll -o - | FileCheck %t/ae_mulsfp32x16x2ras_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x16x2ras_l.ll -o - | FileCheck %t/ae_mulsfp32x16x2ras_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x16x2ras_l_s2.ll -o - | FileCheck %t/ae_mulsfp32x16x2ras_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x16x2rs_h.ll -o - | FileCheck %t/ae_mulsfp32x16x2rs_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x16x2rs_h_s2.ll -o - | FileCheck %t/ae_mulsfp32x16x2rs_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x16x2rs_l.ll -o - | FileCheck %t/ae_mulsfp32x16x2rs_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x16x2rs_l_s2.ll -o - | FileCheck %t/ae_mulsfp32x16x2rs_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x2ras.ll -o - | FileCheck %t/ae_mulsfp32x2ras.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfp32x2rs.ll -o - | FileCheck %t/ae_mulsfp32x2rs.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfq32sp24s_h_s2.ll -o - | FileCheck %t/ae_mulsfq32sp24s_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsfq32sp24s_l_s2.ll -o - | FileCheck %t/ae_mulsfq32sp24s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsp24x2.ll -o - | FileCheck %t/ae_mulsp24x2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsp24x2_s2.ll -o - | FileCheck %t/ae_mulsp24x2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsp32x16x2_h.ll -o - | FileCheck %t/ae_mulsp32x16x2_h.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsp32x16x2_l.ll -o - | FileCheck %t/ae_mulsp32x16x2_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsp32x2.ll -o - | FileCheck %t/ae_mulsp32x2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsq32sp16s_l_s2.ll -o - | FileCheck %t/ae_mulsq32sp16s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsq32sp16u_l_s2.ll -o - | FileCheck %t/ae_mulsq32sp16u_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsrfq32sp24s_h_s2.ll -o - | FileCheck %t/ae_mulsrfq32sp24s_h_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulsrfq32sp24s_l_s2.ll -o - | FileCheck %t/ae_mulsrfq32sp24s_l_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulss32f48p16s_hh.ll -o - | FileCheck %t/ae_mulss32f48p16s_hh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulss32f48p16s_hh_s2.ll -o - | FileCheck %t/ae_mulss32f48p16s_hh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulss32f48p16s_lh.ll -o - | FileCheck %t/ae_mulss32f48p16s_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulss32f48p16s_lh_s2.ll -o - | FileCheck %t/ae_mulss32f48p16s_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulss32f48p16s_ll.ll -o - | FileCheck %t/ae_mulss32f48p16s_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulss32f48p16s_ll_s2.ll -o - | FileCheck %t/ae_mulss32f48p16s_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssd24_hh_ll.ll -o - | FileCheck %t/ae_mulssd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulssd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssd24_hl_lh.ll -o - | FileCheck %t/ae_mulssd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulssd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulssd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulssd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulssd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulssd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd16ss_11_00.ll -o - | FileCheck %t/ae_mulssfd16ss_11_00.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd16ss_11_00_s2.ll -o - | FileCheck %t/ae_mulssfd16ss_11_00_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd16ss_13_02.ll -o - | FileCheck %t/ae_mulssfd16ss_13_02.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd16ss_13_02_s2.ll -o - | FileCheck %t/ae_mulssfd16ss_13_02_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd16ss_33_22.ll -o - | FileCheck %t/ae_mulssfd16ss_33_22.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd16ss_33_22_s2.ll -o - | FileCheck %t/ae_mulssfd16ss_33_22_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd24_hh_ll.ll -o - | FileCheck %t/ae_mulssfd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulssfd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd24_hl_lh.ll -o - | FileCheck %t/ae_mulssfd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulssfd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulssfd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulssfd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulssfd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulssfd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulssfd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad24_hh_ll.ll -o - | FileCheck %t/ae_mulzaad24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulzaad24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad24_hl_lh.ll -o - | FileCheck %t/ae_mulzaad24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulzaad24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad32x16_h0_l1.ll -o - | FileCheck %t/ae_mulzaad32x16_h0_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad32x16_h0_l1_s2.ll -o - | FileCheck %t/ae_mulzaad32x16_h0_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad32x16_h1_l0.ll -o - | FileCheck %t/ae_mulzaad32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulzaad32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad32x16_h2_l3.ll -o - | FileCheck %t/ae_mulzaad32x16_h2_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad32x16_h2_l3_s2.ll -o - | FileCheck %t/ae_mulzaad32x16_h2_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad32x16_h3_l2.ll -o - | FileCheck %t/ae_mulzaad32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaad32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulzaad32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd16ss_11_00.ll -o - | FileCheck %t/ae_mulzaafd16ss_11_00.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd16ss_11_00_s2.ll -o - | FileCheck %t/ae_mulzaafd16ss_11_00_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd16ss_13_02.ll -o - | FileCheck %t/ae_mulzaafd16ss_13_02.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd16ss_13_02_s2.ll -o - | FileCheck %t/ae_mulzaafd16ss_13_02_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd16ss_33_22.ll -o - | FileCheck %t/ae_mulzaafd16ss_33_22.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd16ss_33_22_s2.ll -o - | FileCheck %t/ae_mulzaafd16ss_33_22_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd24_hh_ll.ll -o - | FileCheck %t/ae_mulzaafd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulzaafd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd24_hl_lh.ll -o - | FileCheck %t/ae_mulzaafd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulzaafd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd32x16_h0_l1.ll -o - | FileCheck %t/ae_mulzaafd32x16_h0_l1.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd32x16_h0_l1_s2.ll -o - | FileCheck %t/ae_mulzaafd32x16_h0_l1_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulzaafd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulzaafd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd32x16_h2_l3.ll -o - | FileCheck %t/ae_mulzaafd32x16_h2_l3.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd32x16_h2_l3_s2.ll -o - | FileCheck %t/ae_mulzaafd32x16_h2_l3_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulzaafd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzaafd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulzaafd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasd24_hh_ll.ll -o - | FileCheck %t/ae_mulzasd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulzasd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasd24_hl_lh.ll -o - | FileCheck %t/ae_mulzasd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulzasd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulzasd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulzasd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulzasd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulzasd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasfd24_hh_ll.ll -o - | FileCheck %t/ae_mulzasfd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasfd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulzasfd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasfd24_hl_lh.ll -o - | FileCheck %t/ae_mulzasfd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasfd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulzasfd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasfd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulzasfd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasfd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulzasfd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasfd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulzasfd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzasfd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulzasfd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsad24_hh_ll.ll -o - | FileCheck %t/ae_mulzsad24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsad24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulzsad24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsad32x16_h1_l0.ll -o - | FileCheck %t/ae_mulzsad32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsad32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulzsad32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsad32x16_h3_l2.ll -o - | FileCheck %t/ae_mulzsad32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsad32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulzsad32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsafd24_hh_ll.ll -o - | FileCheck %t/ae_mulzsafd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsafd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulzsafd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsafd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulzsafd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsafd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulzsafd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsafd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulzsafd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzsafd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulzsafd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssd24_hh_ll.ll -o - | FileCheck %t/ae_mulzssd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulzssd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssd24_hl_lh.ll -o - | FileCheck %t/ae_mulzssd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulzssd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulzssd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulzssd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulzssd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulzssd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd16ss_11_00.ll -o - | FileCheck %t/ae_mulzssfd16ss_11_00.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd16ss_11_00_s2.ll -o - | FileCheck %t/ae_mulzssfd16ss_11_00_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd16ss_13_02.ll -o - | FileCheck %t/ae_mulzssfd16ss_13_02.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd16ss_13_02_s2.ll -o - | FileCheck %t/ae_mulzssfd16ss_13_02_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd16ss_33_22.ll -o - | FileCheck %t/ae_mulzssfd16ss_33_22.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd16ss_33_22_s2.ll -o - | FileCheck %t/ae_mulzssfd16ss_33_22_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd24_hh_ll.ll -o - | FileCheck %t/ae_mulzssfd24_hh_ll.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd24_hh_ll_s2.ll -o - | FileCheck %t/ae_mulzssfd24_hh_ll_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd24_hl_lh.ll -o - | FileCheck %t/ae_mulzssfd24_hl_lh.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd24_hl_lh_s2.ll -o - | FileCheck %t/ae_mulzssfd24_hl_lh_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd32x16_h1_l0.ll -o - | FileCheck %t/ae_mulzssfd32x16_h1_l0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd32x16_h1_l0_s2.ll -o - | FileCheck %t/ae_mulzssfd32x16_h1_l0_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd32x16_h3_l2.ll -o - | FileCheck %t/ae_mulzssfd32x16_h3_l2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_mulzssfd32x16_h3_l2_s2.ll -o - | FileCheck %t/ae_mulzssfd32x16_h3_l2_s2.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_nand.ll -o - | FileCheck %t/ae_nand.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_neg16s.ll -o - | FileCheck %t/ae_neg16s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_neg24s.ll -o - | FileCheck %t/ae_neg24s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_neg32.ll -o - | FileCheck %t/ae_neg32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_neg32s.ll -o - | FileCheck %t/ae_neg32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_neg64.ll -o - | FileCheck %t/ae_neg64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_neg64s.ll -o - | FileCheck %t/ae_neg64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_nsa64.ll -o - | FileCheck %t/ae_nsa64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_nsaz16_0.ll -o - | FileCheck %t/ae_nsaz16_0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_nsaz32_l.ll -o - | FileCheck %t/ae_nsaz32_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_or.ll -o - | FileCheck %t/ae_or.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_pksr24.ll -o - | FileCheck %t/ae_pksr24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_pksr32.ll -o - | FileCheck %t/ae_pksr32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_round16x4f32sasym.ll -o - | FileCheck %t/ae_round16x4f32sasym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_round16x4f32ssym.ll -o - | FileCheck %t/ae_round16x4f32ssym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_round24x2f48sasym.ll -o - | FileCheck %t/ae_round24x2f48sasym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_round24x2f48ssym.ll -o - | FileCheck %t/ae_round24x2f48ssym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_round32x2f48sasym.ll -o - | FileCheck %t/ae_round32x2f48sasym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_round32x2f48ssym.ll -o - | FileCheck %t/ae_round32x2f48ssym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_round32x2f64sasym.ll -o - | FileCheck %t/ae_round32x2f64sasym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_round32x2f64ssym.ll -o - | FileCheck %t/ae_round32x2f64ssym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_roundsp16f24asym.ll -o - | FileCheck %t/ae_roundsp16f24asym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_roundsp16f24sym.ll -o - | FileCheck %t/ae_roundsp16f24sym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_roundsp16q48x2asym.ll -o - | FileCheck %t/ae_roundsp16q48x2asym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_roundsp16q48x2sym.ll -o - | FileCheck %t/ae_roundsp16q48x2sym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_roundsq32f48asym.ll -o - | FileCheck %t/ae_roundsq32f48asym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_roundsq32f48sym.ll -o - | FileCheck %t/ae_roundsq32f48sym.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16_0_i.ll -o - | FileCheck %t/ae_s16_0_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16_0_ip.ll -o - | FileCheck %t/ae_s16_0_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16_0_x.ll -o - | FileCheck %t/ae_s16_0_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16_0_xc.ll -o - | FileCheck %t/ae_s16_0_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16_0_xp.ll -o - | FileCheck %t/ae_s16_0_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16m_l_i.ll -o - | FileCheck %t/ae_s16m_l_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16m_l_iu.ll -o - | FileCheck %t/ae_s16m_l_iu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16m_l_x.ll -o - | FileCheck %t/ae_s16m_l_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16m_l_xc.ll -o - | FileCheck %t/ae_s16m_l_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16m_l_xu.ll -o - | FileCheck %t/ae_s16m_l_xu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x2m_i.ll -o - | FileCheck %t/ae_s16x2m_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x2m_iu.ll -o - | FileCheck %t/ae_s16x2m_iu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x2m_x.ll -o - | FileCheck %t/ae_s16x2m_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x2m_xc.ll -o - | FileCheck %t/ae_s16x2m_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x2m_xu.ll -o - | FileCheck %t/ae_s16x2m_xu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x4_i.ll -o - | FileCheck %t/ae_s16x4_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x4_ip.ll -o - | FileCheck %t/ae_s16x4_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x4_ric.ll -o - | FileCheck %t/ae_s16x4_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x4_rip.ll -o - | FileCheck %t/ae_s16x4_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x4_x.ll -o - | FileCheck %t/ae_s16x4_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x4_xc.ll -o - | FileCheck %t/ae_s16x4_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s16x4_xp.ll -o - | FileCheck %t/ae_s16x4_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s24ra64s_i.ll -o - | FileCheck %t/ae_s24ra64s_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s24ra64s_ip.ll -o - | FileCheck %t/ae_s24ra64s_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s24ra64s_x.ll -o - | FileCheck %t/ae_s24ra64s_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s24ra64s_xc.ll -o - | FileCheck %t/ae_s24ra64s_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s24ra64s_xp.ll -o - | FileCheck %t/ae_s24ra64s_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s24x2ra64s_ip.ll -o - | FileCheck %t/ae_s24x2ra64s_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32_l_i.ll -o - | FileCheck %t/ae_s32_l_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32_l_ip.ll -o - | FileCheck %t/ae_s32_l_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32_l_x.ll -o - | FileCheck %t/ae_s32_l_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32_l_xc.ll -o - | FileCheck %t/ae_s32_l_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32_l_xp.ll -o - | FileCheck %t/ae_s32_l_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32f24_l_i.ll -o - | FileCheck %t/ae_s32f24_l_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32f24_l_ip.ll -o - | FileCheck %t/ae_s32f24_l_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32f24_l_x.ll -o - | FileCheck %t/ae_s32f24_l_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32f24_l_xc.ll -o - | FileCheck %t/ae_s32f24_l_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32f24_l_xp.ll -o - | FileCheck %t/ae_s32f24_l_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32m_i.ll -o - | FileCheck %t/ae_s32m_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32m_iu.ll -o - | FileCheck %t/ae_s32m_iu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32m_x.ll -o - | FileCheck %t/ae_s32m_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32m_xc.ll -o - | FileCheck %t/ae_s32m_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32m_xu.ll -o - | FileCheck %t/ae_s32m_xu.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32ra64s_i.ll -o - | FileCheck %t/ae_s32ra64s_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32ra64s_ip.ll -o - | FileCheck %t/ae_s32ra64s_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32ra64s_x.ll -o - | FileCheck %t/ae_s32ra64s_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32ra64s_xc.ll -o - | FileCheck %t/ae_s32ra64s_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32ra64s_xp.ll -o - | FileCheck %t/ae_s32ra64s_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2_i.ll -o - | FileCheck %t/ae_s32x2_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2_ip.ll -o - | FileCheck %t/ae_s32x2_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2_ric.ll -o - | FileCheck %t/ae_s32x2_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2_rip.ll -o - | FileCheck %t/ae_s32x2_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2_x.ll -o - | FileCheck %t/ae_s32x2_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2_xc.ll -o - | FileCheck %t/ae_s32x2_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2_xp.ll -o - | FileCheck %t/ae_s32x2_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2f24_i.ll -o - | FileCheck %t/ae_s32x2f24_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2f24_ip.ll -o - | FileCheck %t/ae_s32x2f24_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2f24_ric.ll -o - | FileCheck %t/ae_s32x2f24_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2f24_rip.ll -o - | FileCheck %t/ae_s32x2f24_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2f24_x.ll -o - | FileCheck %t/ae_s32x2f24_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2f24_xc.ll -o - | FileCheck %t/ae_s32x2f24_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2f24_xp.ll -o - | FileCheck %t/ae_s32x2f24_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s32x2ra64s_ip.ll -o - | FileCheck %t/ae_s32x2ra64s_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s64_i.ll -o - | FileCheck %t/ae_s64_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s64_ip.ll -o - | FileCheck %t/ae_s64_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s64_x.ll -o - | FileCheck %t/ae_s64_x.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s64_xc.ll -o - | FileCheck %t/ae_s64_xc.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_s64_xp.ll -o - | FileCheck %t/ae_s64_xp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa16x4_ic.ll -o - | FileCheck %t/ae_sa16x4_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa16x4_ip.ll -o - | FileCheck %t/ae_sa16x4_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa16x4_ric.ll -o - | FileCheck %t/ae_sa16x4_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa16x4_rip.ll -o - | FileCheck %t/ae_sa16x4_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa24_l_ic.ll -o - | FileCheck %t/ae_sa24_l_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa24_l_ip.ll -o - | FileCheck %t/ae_sa24_l_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa24_l_ric.ll -o - | FileCheck %t/ae_sa24_l_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa24_l_rip.ll -o - | FileCheck %t/ae_sa24_l_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa24x2_ic.ll -o - | FileCheck %t/ae_sa24x2_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa24x2_ip.ll -o - | FileCheck %t/ae_sa24x2_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa24x2_ric.ll -o - | FileCheck %t/ae_sa24x2_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa24x2_rip.ll -o - | FileCheck %t/ae_sa24x2_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa32x2_ic.ll -o - | FileCheck %t/ae_sa32x2_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa32x2_ip.ll -o - | FileCheck %t/ae_sa32x2_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa32x2_ric.ll -o - | FileCheck %t/ae_sa32x2_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa32x2_rip.ll -o - | FileCheck %t/ae_sa32x2_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa32x2f24_ic.ll -o - | FileCheck %t/ae_sa32x2f24_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa32x2f24_ip.ll -o - | FileCheck %t/ae_sa32x2f24_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa32x2f24_ric.ll -o - | FileCheck %t/ae_sa32x2f24_ric.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa32x2f24_rip.ll -o - | FileCheck %t/ae_sa32x2f24_rip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa64neg_fp.ll -o - | FileCheck %t/ae_sa64neg_fp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sa64pos_fp.ll -o - | FileCheck %t/ae_sa64pos_fp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_salign64_i.ll -o - | FileCheck %t/ae_salign64_i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sat16x4.ll -o - | FileCheck %t/ae_sat16x4.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sat24s.ll -o - | FileCheck %t/ae_sat24s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sat48s.ll -o - | FileCheck %t/ae_sat48s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_satq56s.ll -o - | FileCheck %t/ae_satq56s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sb.ll -o - | FileCheck %t/ae_sb.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sb_ic.ll -o - | FileCheck %t/ae_sb_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sb_ip.ll -o - | FileCheck %t/ae_sb_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sbf.ll -o - | FileCheck %t/ae_sbf.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sbf_ic.ll -o - | FileCheck %t/ae_sbf_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sbf_ip.ll -o - | FileCheck %t/ae_sbf_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sbi.ll -o - | FileCheck %t/ae_sbi.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sbi_ic.ll -o - | FileCheck %t/ae_sbi_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sbi_ip.ll -o - | FileCheck %t/ae_sbi_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sel16i.ll -o - | FileCheck %t/ae_sel16i.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sel16i_n.ll -o - | FileCheck %t/ae_sel16i_n.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sext32.ll -o - | FileCheck %t/ae_sext32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sext32x2d16_10.ll -o - | FileCheck %t/ae_sext32x2d16_10.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sext32x2d16_32.ll -o - | FileCheck %t/ae_sext32x2d16_32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sha32.ll -o - | FileCheck %t/ae_sha32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_shortswap.ll -o - | FileCheck %t/ae_shortswap.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slaa16s.ll -o - | FileCheck %t/ae_slaa16s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slaa32.ll -o - | FileCheck %t/ae_slaa32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slaa32s.ll -o - | FileCheck %t/ae_slaa32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slaa64.ll -o - | FileCheck %t/ae_slaa64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slaa64s.ll -o - | FileCheck %t/ae_slaa64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slaaq56.ll -o - | FileCheck %t/ae_slaaq56.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slai16s.ll -o - | FileCheck %t/ae_slai16s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slai24.ll -o - | FileCheck %t/ae_slai24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slai24s.ll -o - | FileCheck %t/ae_slai24s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slai32.ll -o - | FileCheck %t/ae_slai32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slai32s.ll -o - | FileCheck %t/ae_slai32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slai64.ll -o - | FileCheck %t/ae_slai64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slai64s.ll -o - | FileCheck %t/ae_slai64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slaisq56s.ll -o - | FileCheck %t/ae_slaisq56s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slas24.ll -o - | FileCheck %t/ae_slas24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slas24s.ll -o - | FileCheck %t/ae_slas24s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slas32.ll -o - | FileCheck %t/ae_slas32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slas32s.ll -o - | FileCheck %t/ae_slas32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slas64.ll -o - | FileCheck %t/ae_slas64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slas64s.ll -o - | FileCheck %t/ae_slas64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slasq56.ll -o - | FileCheck %t/ae_slasq56.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_slassq56s.ll -o - | FileCheck %t/ae_slassq56s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sra64_32.ll -o - | FileCheck %t/ae_sra64_32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sraa16rs.ll -o - | FileCheck %t/ae_sraa16rs.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sraa16s.ll -o - | FileCheck %t/ae_sraa16s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sraa32.ll -o - | FileCheck %t/ae_sraa32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sraa32rs.ll -o - | FileCheck %t/ae_sraa32rs.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sraa32s.ll -o - | FileCheck %t/ae_sraa32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sraa64.ll -o - | FileCheck %t/ae_sraa64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srai16.ll -o - | FileCheck %t/ae_srai16.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srai16r.ll -o - | FileCheck %t/ae_srai16r.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srai24.ll -o - | FileCheck %t/ae_srai24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srai32.ll -o - | FileCheck %t/ae_srai32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srai32r.ll -o - | FileCheck %t/ae_srai32r.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srai64.ll -o - | FileCheck %t/ae_srai64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sras24.ll -o - | FileCheck %t/ae_sras24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sras32.ll -o - | FileCheck %t/ae_sras32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sras64.ll -o - | FileCheck %t/ae_sras64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srla32.ll -o - | FileCheck %t/ae_srla32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srla64.ll -o - | FileCheck %t/ae_srla64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srli24.ll -o - | FileCheck %t/ae_srli24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srli32.ll -o - | FileCheck %t/ae_srli32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srli64.ll -o - | FileCheck %t/ae_srli64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srls24.ll -o - | FileCheck %t/ae_srls24.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srls32.ll -o - | FileCheck %t/ae_srls32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_srls64.ll -o - | FileCheck %t/ae_srls64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sub16.ll -o - | FileCheck %t/ae_sub16.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sub16s.ll -o - | FileCheck %t/ae_sub16s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sub24s.ll -o - | FileCheck %t/ae_sub24s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sub32.ll -o - | FileCheck %t/ae_sub32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sub32s.ll -o - | FileCheck %t/ae_sub32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sub64.ll -o - | FileCheck %t/ae_sub64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_sub64s.ll -o - | FileCheck %t/ae_sub64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_subadd32.ll -o - | FileCheck %t/ae_subadd32.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_subadd32s.ll -o - | FileCheck %t/ae_subadd32s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_trunca32f64s_l.ll -o - | FileCheck %t/ae_trunca32f64s_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_trunca32x2f64s.ll -o - | FileCheck %t/ae_trunca32x2f64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_trunci32f64s_l.ll -o - | FileCheck %t/ae_trunci32f64s_l.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_trunci32x2f64s.ll -o - | FileCheck %t/ae_trunci32x2f64s.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vldl16c.ll -o - | FileCheck %t/ae_vldl16c.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vldl16c_ic.ll -o - | FileCheck %t/ae_vldl16c_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vldl16c_ip.ll -o - | FileCheck %t/ae_vldl16c_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vldl16t.ll -o - | FileCheck %t/ae_vldl16t.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vldl32t.ll -o - | FileCheck %t/ae_vldl32t.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vldsht.ll -o - | FileCheck %t/ae_vldsht.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vlel16t.ll -o - | FileCheck %t/ae_vlel16t.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vlel32t.ll -o - | FileCheck %t/ae_vlel32t.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vles16c.ll -o - | FileCheck %t/ae_vles16c.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vles16c_ic.ll -o - | FileCheck %t/ae_vles16c_ic.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_vles16c_ip.ll -o - | FileCheck %t/ae_vles16c_ip.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_xor.ll -o - | FileCheck %t/ae_xor.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/ae_zalign64.ll -o - | FileCheck %t/ae_zalign64.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_bithead.ll -o - | FileCheck %t/rur_ae_bithead.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_bitptr.ll -o - | FileCheck %t/rur_ae_bitptr.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_bitsused.ll -o - | FileCheck %t/rur_ae_bitsused.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_cbegin0.ll -o - | FileCheck %t/rur_ae_cbegin0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_cend0.ll -o - | FileCheck %t/rur_ae_cend0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_cw_sd_no.ll -o - | FileCheck %t/rur_ae_cw_sd_no.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_cwrap.ll -o - | FileCheck %t/rur_ae_cwrap.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_first_ts.ll -o - | FileCheck %t/rur_ae_first_ts.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_nextoffset.ll -o - | FileCheck %t/rur_ae_nextoffset.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_overflow.ll -o - | FileCheck %t/rur_ae_overflow.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_ovf_sar.ll -o - | FileCheck %t/rur_ae_ovf_sar.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_sar.ll -o - | FileCheck %t/rur_ae_sar.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_searchdone.ll -o - | FileCheck %t/rur_ae_searchdone.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_tablesize.ll -o - | FileCheck %t/rur_ae_tablesize.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/rur_ae_ts_fts_bu_bp.ll -o - | FileCheck %t/rur_ae_ts_fts_bu_bp.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_bithead.ll -o - | FileCheck %t/wur_ae_bithead.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_bitptr.ll -o - | FileCheck %t/wur_ae_bitptr.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_bitsused.ll -o - | FileCheck %t/wur_ae_bitsused.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_cbegin0.ll -o - | FileCheck %t/wur_ae_cbegin0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_cend0.ll -o - | FileCheck %t/wur_ae_cend0.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_cw_sd_no.ll -o - | FileCheck %t/wur_ae_cw_sd_no.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_cwrap.ll -o - | FileCheck %t/wur_ae_cwrap.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_first_ts.ll -o - | FileCheck %t/wur_ae_first_ts.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_nextoffset.ll -o - | FileCheck %t/wur_ae_nextoffset.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_overflow.ll -o - | FileCheck %t/wur_ae_overflow.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_ovf_sar.ll -o - | FileCheck %t/wur_ae_ovf_sar.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_sar.ll -o - | FileCheck %t/wur_ae_sar.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_searchdone.ll -o - | FileCheck %t/wur_ae_searchdone.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_tablesize.ll -o - | FileCheck %t/wur_ae_tablesize.ll +; RUN: llc -mtriple=xtensa -mcpu=cnl %t/wur_ae_ts_fts_bu_bp.ll -o - | FileCheck %t/wur_ae_ts_fts_bu_bp.ll +;--- ae_abs16s.ll +declare <4 x i16> @llvm.xtensa.ae.abs16s(<4 x i16>) +define <4 x i16> @test_xtensa_ae_abs16s(<4 x i16> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_abs16s: + +%ret = call <4 x i16> @llvm.xtensa.ae.abs16s(<4 x i16> %ae_arth_v1) +; CHECK: ae_abs16s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_abs24s.ll +declare <2 x i32> @llvm.xtensa.ae.abs24s(<2 x i32>) +define <2 x i32> @test_xtensa_ae_abs24s(<2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_abs24s: + +%ret = call <2 x i32> @llvm.xtensa.ae.abs24s(<2 x i32> %ae_arth_v1) +; CHECK: ae_abs24s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_abs32.ll +declare <2 x i32> @llvm.xtensa.ae.abs32(<2 x i32>) +define <2 x i32> @test_xtensa_ae_abs32(<2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_abs32: + +%ret = call <2 x i32> @llvm.xtensa.ae.abs32(<2 x i32> %ae_arth_v1) +; CHECK: ae_abs32 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_abs32s.ll +declare <2 x i32> @llvm.xtensa.ae.abs32s(<2 x i32>) +define <2 x i32> @test_xtensa_ae_abs32s(<2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_abs32s: + +%ret = call <2 x i32> @llvm.xtensa.ae.abs32s(<2 x i32> %ae_arth_v1) +; CHECK: ae_abs32s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_abs64.ll +declare <1 x i64> @llvm.xtensa.ae.abs64(<1 x i64>) +define <1 x i64> @test_xtensa_ae_abs64(<1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_abs64: + +%ret = call <1 x i64> @llvm.xtensa.ae.abs64(<1 x i64> %ae_arth_v1) +; CHECK: ae_abs64 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_abs64s.ll +declare <1 x i64> @llvm.xtensa.ae.abs64s(<1 x i64>) +define <1 x i64> @test_xtensa_ae_abs64s(<1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_abs64s: + +%ret = call <1 x i64> @llvm.xtensa.ae.abs64s(<1 x i64> %ae_arth_v1) +; CHECK: ae_abs64s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_add16.ll +declare <4 x i16> @llvm.xtensa.ae.add16(<4 x i16>, <4 x i16>) +define <4 x i16> @test_xtensa_ae_add16(<4 x i16> %ae_arth_v0, <4 x i16> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_add16: + + +%ret = call <4 x i16> @llvm.xtensa.ae.add16(<4 x i16> %ae_arth_v0, <4 x i16> %ae_arth_v1) +; CHECK: ae_add16 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_add16s.ll +declare <4 x i16> @llvm.xtensa.ae.add16s(<4 x i16>, <4 x i16>) +define <4 x i16> @test_xtensa_ae_add16s(<4 x i16> %ae_arth_v0, <4 x i16> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_add16s: + + +%ret = call <4 x i16> @llvm.xtensa.ae.add16s(<4 x i16> %ae_arth_v0, <4 x i16> %ae_arth_v1) +; CHECK: ae_add16s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_add24s.ll +declare <2 x i32> @llvm.xtensa.ae.add24s(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_add24s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_add24s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.add24s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_add24s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_add32.ll +declare <2 x i32> @llvm.xtensa.ae.add32(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_add32(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_add32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.add32(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_add32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_add32_hl_lh.ll +declare <2 x i32> @llvm.xtensa.ae.add32.hl.lh(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_add32_hl_lh(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_add32_hl_lh: + + +%ret = call <2 x i32> @llvm.xtensa.ae.add32.hl.lh(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_add32_hl_lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_add32s.ll +declare <2 x i32> @llvm.xtensa.ae.add32s(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_add32s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_add32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.add32s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_add32s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_add64.ll +declare <1 x i64> @llvm.xtensa.ae.add64(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_add64(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_add64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.add64(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_add64 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_add64s.ll +declare <1 x i64> @llvm.xtensa.ae.add64s(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_add64s(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_add64s: + + +%ret = call <1 x i64> @llvm.xtensa.ae.add64s(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_add64s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_addbrba32.ll +declare i32 @llvm.xtensa.ae.addbrba32(i32, i32) +define i32 @test_xtensa_ae_addbrba32(i32 %art, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_addbrba32: + + +%ret = call i32 @llvm.xtensa.ae.addbrba32(i32 %art, i32 %ars) +; CHECK: ae_addbrba32 a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_addsub32.ll +declare <2 x i32> @llvm.xtensa.ae.addsub32(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_addsub32(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_addsub32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.addsub32(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_addsub32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_addsub32s.ll +declare <2 x i32> @llvm.xtensa.ae.addsub32s(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_addsub32s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_addsub32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.addsub32s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_addsub32s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_and.ll +declare <1 x i64> @llvm.xtensa.ae.and(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_and(<1 x i64> %ae_dr_to_dr_v0, <1 x i64> %ae_dr_to_dr_v1) { +; CHECK-LABEL: test_xtensa_ae_and: + + +%ret = call <1 x i64> @llvm.xtensa.ae.and(<1 x i64> %ae_dr_to_dr_v0, <1 x i64> %ae_dr_to_dr_v1) +; CHECK: ae_and aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_cvt32x2f16_10.ll +declare <2 x i32> @llvm.xtensa.ae.cvt32x2f16.10(<4 x i16>) +define <2 x i32> @test_xtensa_ae_cvt32x2f16_10(<4 x i16> %ae_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_cvt32x2f16_10: + +%ret = call <2 x i32> @llvm.xtensa.ae.cvt32x2f16.10(<4 x i16> %ae_to_dr_v0) +; CHECK: ae_cvt32x2f16.10 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_cvt32x2f16_32.ll +declare <2 x i32> @llvm.xtensa.ae.cvt32x2f16.32(<4 x i16>) +define <2 x i32> @test_xtensa_ae_cvt32x2f16_32(<4 x i16> %ae_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_cvt32x2f16_32: + +%ret = call <2 x i32> @llvm.xtensa.ae.cvt32x2f16.32(<4 x i16> %ae_to_dr_v0) +; CHECK: ae_cvt32x2f16.32 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_cvt48a32.ll +declare <1 x i64> @llvm.xtensa.ae.cvt48a32(i32) +define <1 x i64> @test_xtensa_ae_cvt48a32(i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_cvt48a32: + +%ret = call <1 x i64> @llvm.xtensa.ae.cvt48a32(i32 %ars) +; CHECK: ae_cvt48a32 aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_cvt64a32.ll +declare <1 x i64> @llvm.xtensa.ae.cvt64a32(i32) +define <1 x i64> @test_xtensa_ae_cvt64a32(i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_cvt64a32: + +%ret = call <1 x i64> @llvm.xtensa.ae.cvt64a32(i32 %ars) +; CHECK: ae_cvt64a32 aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_cvt64f32_h.ll +declare <1 x i64> @llvm.xtensa.ae.cvt64f32.h(<2 x i32>) +define <1 x i64> @test_xtensa_ae_cvt64f32_h(<2 x i32> %ae_dr_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_cvt64f32_h: + +%ret = call <1 x i64> @llvm.xtensa.ae.cvt64f32.h(<2 x i32> %ae_dr_to_dr_v0) +; CHECK: ae_cvt64f32.h aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_cvta32f24s_h.ll +declare i32 @llvm.xtensa.ae.cvta32f24s.h(<2 x i32>) +define i32 @test_xtensa_ae_cvta32f24s_h(<2 x i32> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_cvta32f24s_h: + +%ret = call i32 @llvm.xtensa.ae.cvta32f24s.h(<2 x i32> %ae_dr_to_ar_v0) +; CHECK: ae_cvta32f24s.h a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_cvta32f24s_l.ll +declare i32 @llvm.xtensa.ae.cvta32f24s.l(<2 x i32>) +define i32 @test_xtensa_ae_cvta32f24s_l(<2 x i32> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_cvta32f24s_l: + +%ret = call i32 @llvm.xtensa.ae.cvta32f24s.l(<2 x i32> %ae_dr_to_ar_v0) +; CHECK: ae_cvta32f24s.l a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_cvtq56a32s.ll +declare <1 x i64> @llvm.xtensa.ae.cvtq56a32s(i32) +define <1 x i64> @test_xtensa_ae_cvtq56a32s(i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_cvtq56a32s: + +%ret = call <1 x i64> @llvm.xtensa.ae.cvtq56a32s(i32 %ars) +; CHECK: ae_cvtq56a32s aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_cvtq56p32s_h.ll +declare <1 x i64> @llvm.xtensa.ae.cvtq56p32s.h(<2 x i32>) +define <1 x i64> @test_xtensa_ae_cvtq56p32s_h(<2 x i32> %ae_dr_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_cvtq56p32s_h: + +%ret = call <1 x i64> @llvm.xtensa.ae.cvtq56p32s.h(<2 x i32> %ae_dr_to_dr_v0) +; CHECK: ae_cvtq56p32s.h aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_cvtq56p32s_l.ll +declare <1 x i64> @llvm.xtensa.ae.cvtq56p32s.l(<2 x i32>) +define <1 x i64> @test_xtensa_ae_cvtq56p32s_l(<2 x i32> %ae_dr_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_cvtq56p32s_l: + +%ret = call <1 x i64> @llvm.xtensa.ae.cvtq56p32s.l(<2 x i32> %ae_dr_to_dr_v0) +; CHECK: ae_cvtq56p32s.l aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_db.ll +declare ptr @llvm.xtensa.ae.db(ptr, i32) +define ptr @test_xtensa_ae_db(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_db: + + +%ret = call ptr @llvm.xtensa.ae.db(ptr %ars, i32 %art) +; CHECK: ae_db a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_db_ic.ll +declare ptr @llvm.xtensa.ae.db.ic(ptr, i32) +define ptr @test_xtensa_ae_db_ic(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_db_ic: + + +%ret = call ptr @llvm.xtensa.ae.db.ic(ptr %ars, i32 %art) +; CHECK: ae_db.ic a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_db_ip.ll +declare ptr @llvm.xtensa.ae.db.ip(ptr, i32) +define ptr @test_xtensa_ae_db_ip(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_db_ip: + + +%ret = call ptr @llvm.xtensa.ae.db.ip(ptr %ars, i32 %art) +; CHECK: ae_db.ip a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_dbi.ll +declare ptr @llvm.xtensa.ae.dbi(ptr, i32) +define ptr @test_xtensa_ae_dbi(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_dbi: + + +%ret = call ptr @llvm.xtensa.ae.dbi(ptr %ars, i32 1) +; CHECK: ae_dbi a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_dbi_ic.ll +declare ptr @llvm.xtensa.ae.dbi.ic(ptr, i32) +define ptr @test_xtensa_ae_dbi_ic(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_dbi_ic: + + +%ret = call ptr @llvm.xtensa.ae.dbi.ic(ptr %ars, i32 1) +; CHECK: ae_dbi.ic a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_dbi_ip.ll +declare ptr @llvm.xtensa.ae.dbi.ip(ptr, i32) +define ptr @test_xtensa_ae_dbi_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_dbi_ip: + + +%ret = call ptr @llvm.xtensa.ae.dbi.ip(ptr %ars, i32 1) +; CHECK: ae_dbi.ip a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_div64d32_h.ll +declare <1 x i64> @llvm.xtensa.ae.div64d32.h(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_div64d32_h(<1 x i64> %ae_arth_v, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_div64d32_h: + + +%ret = call <1 x i64> @llvm.xtensa.ae.div64d32.h(<1 x i64> %ae_arth_v, <2 x i32> %ae_arth_v1) +; CHECK: ae_div64d32.h aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_div64d32_l.ll +declare <1 x i64> @llvm.xtensa.ae.div64d32.l(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_div64d32_l(<1 x i64> %ae_arth_v, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_div64d32_l: + + +%ret = call <1 x i64> @llvm.xtensa.ae.div64d32.l(<1 x i64> %ae_arth_v, <2 x i32> %ae_arth_v1) +; CHECK: ae_div64d32.l aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_eq64.ll +declare <1 x i1> @llvm.xtensa.ae.eq64(<1 x i64>, <1 x i64>) +define <1 x i1> @test_xtensa_ae_eq64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_eq64: + + +%ret = call <1 x i1> @llvm.xtensa.ae.eq64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) +; CHECK: ae_eq64 b{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i1> %ret +} + + +;--- ae_l16_i.ll +declare <4 x i16> @llvm.xtensa.ae.l16.i(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16_i: + + +%ret = call <4 x i16> @llvm.xtensa.ae.l16.i(ptr %ars, i32 -16) +; CHECK: ae_l16.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_l16_ip.ll +declare { <4 x i16>, ptr } @llvm.xtensa.ae.l16.ip(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16_ip: + + +%ret = call { <4 x i16>, ptr } @llvm.xtensa.ae.l16.ip(ptr %ars, i32 -16) +; CHECK: ae_l16.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <4 x i16>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_l16_x.ll +declare <4 x i16> @llvm.xtensa.ae.l16.x(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16_x: + + +%ret = call <4 x i16> @llvm.xtensa.ae.l16.x(ptr %ars, i32 %art) +; CHECK: ae_l16.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_l16_xc.ll +declare { <4 x i16>, ptr } @llvm.xtensa.ae.l16.xc(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16_xc: + + +%ret = call { <4 x i16>, ptr } @llvm.xtensa.ae.l16.xc(ptr %ars, i32 %art) +; CHECK: ae_l16.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_l16_xp.ll +declare { <4 x i16>, ptr } @llvm.xtensa.ae.l16.xp(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16_xp(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16_xp: + + +%ret = call { <4 x i16>, ptr } @llvm.xtensa.ae.l16.xp(ptr %ars, i32 %art) +; CHECK: ae_l16.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_l16m_i.ll +declare <2 x i32> @llvm.xtensa.ae.l16m.i(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16m_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16m_i: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l16m.i(ptr %ars, i32 -16) +; CHECK: ae_l16m.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l16m_iu.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.iu(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16m_iu(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16m_iu: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.iu(ptr %ars, i32 -16) +; CHECK: ae_l16m.iu aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l16m_x.ll +declare <2 x i32> @llvm.xtensa.ae.l16m.x(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16m_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16m_x: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l16m.x(ptr %ars, i32 %art) +; CHECK: ae_l16m.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l16m_xc.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.xc(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16m_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16m_xc: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.xc(ptr %ars, i32 %art) +; CHECK: ae_l16m.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l16m_xu.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.xu(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16m_xu(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16m_xu: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.xu(ptr %ars, i32 %art) +; CHECK: ae_l16m.xu aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l16x2m_i.ll +declare <2 x i32> @llvm.xtensa.ae.l16x2m.i(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16x2m_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16x2m_i: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l16x2m.i(ptr %ars, i32 -32) +; CHECK: ae_l16x2m.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l16x2m_iu.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.iu(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16x2m_iu(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16x2m_iu: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.iu(ptr %ars, i32 -32) +; CHECK: ae_l16x2m.iu aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l16x2m_x.ll +declare <2 x i32> @llvm.xtensa.ae.l16x2m.x(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16x2m_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16x2m_x: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l16x2m.x(ptr %ars, i32 %art) +; CHECK: ae_l16x2m.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l16x2m_xc.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.xc(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16x2m_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16x2m_xc: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.xc(ptr %ars, i32 %art) +; CHECK: ae_l16x2m.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l16x2m_xu.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.xu(ptr, i32) +define <2 x i32> @test_xtensa_ae_l16x2m_xu(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16x2m_xu: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.xu(ptr %ars, i32 %art) +; CHECK: ae_l16x2m.xu aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l16x4_i.ll +declare <4 x i16> @llvm.xtensa.ae.l16x4.i(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16x4_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16x4_i: + + +%ret = call <4 x i16> @llvm.xtensa.ae.l16x4.i(ptr %ars, i32 -64) +; CHECK: ae_l16x4.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_l16x4_ip.ll +declare { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.ip(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16x4_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16x4_ip: + + +%ret = call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.ip(ptr %ars, i32 0) +; CHECK: ae_l16x4.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <4 x i16>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_l16x4_ric.ll +declare { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.ric(ptr) +define <4 x i16> @test_xtensa_ae_l16x4_ric(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16x4_ric: + +%ret = call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.ric(ptr %ars) +; CHECK: ae_l16x4.ric aed{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_l16x4_rip.ll +declare { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.rip(ptr) +define <4 x i16> @test_xtensa_ae_l16x4_rip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l16x4_rip: + +%ret = call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.rip(ptr %ars) +; CHECK: ae_l16x4.rip aed{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_l16x4_x.ll +declare <4 x i16> @llvm.xtensa.ae.l16x4.x(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16x4_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16x4_x: + + +%ret = call <4 x i16> @llvm.xtensa.ae.l16x4.x(ptr %ars, i32 %art) +; CHECK: ae_l16x4.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_l16x4_xc.ll +declare { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.xc(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16x4_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16x4_xc: + + +%ret = call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.xc(ptr %ars, i32 %art) +; CHECK: ae_l16x4.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_l16x4_xp.ll +declare { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.xp(ptr, i32) +define <4 x i16> @test_xtensa_ae_l16x4_xp(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l16x4_xp: + + +%ret = call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.xp(ptr %ars, i32 %art) +; CHECK: ae_l16x4.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_l32_i.ll +declare <2 x i32> @llvm.xtensa.ae.l32.i(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32_i: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l32.i(ptr %ars, i32 -32) +; CHECK: ae_l32.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l32_ip.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32.ip(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32_ip: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32.ip(ptr %ars, i32 -32) +; CHECK: ae_l32.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32_x.ll +declare <2 x i32> @llvm.xtensa.ae.l32.x(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32_x: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l32.x(ptr %ars, i32 %art) +; CHECK: ae_l32.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l32_xc.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32.xc(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32_xc: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32.xc(ptr %ars, i32 %art) +; CHECK: ae_l32.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32_xp.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32.xp(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32_xp(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32_xp: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32.xp(ptr %ars, i32 %art) +; CHECK: ae_l32.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32f24_i.ll +declare <2 x i32> @llvm.xtensa.ae.l32f24.i(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32f24_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32f24_i: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l32f24.i(ptr %ars, i32 -32) +; CHECK: ae_l32f24.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l32f24_ip.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.ip(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32f24_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32f24_ip: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.ip(ptr %ars, i32 -32) +; CHECK: ae_l32f24.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32f24_x.ll +declare <2 x i32> @llvm.xtensa.ae.l32f24.x(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32f24_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32f24_x: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l32f24.x(ptr %ars, i32 %art) +; CHECK: ae_l32f24.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l32f24_xc.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.xc(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32f24_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32f24_xc: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.xc(ptr %ars, i32 %art) +; CHECK: ae_l32f24.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32f24_xp.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.xp(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32f24_xp(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32f24_xp: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.xp(ptr %ars, i32 %art) +; CHECK: ae_l32f24.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32m_i.ll +declare <1 x i64> @llvm.xtensa.ae.l32m.i(ptr, i32) +define <1 x i64> @test_xtensa_ae_l32m_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32m_i: + + +%ret = call <1 x i64> @llvm.xtensa.ae.l32m.i(ptr %ars, i32 -32) +; CHECK: ae_l32m.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_l32m_iu.ll +declare { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.iu(ptr, i32) +define <1 x i64> @test_xtensa_ae_l32m_iu(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32m_iu: + + +%ret = call { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.iu(ptr %ars, i32 -32) +; CHECK: ae_l32m.iu aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <1 x i64>, ptr } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_l32m_x.ll +declare <1 x i64> @llvm.xtensa.ae.l32m.x(ptr, i32) +define <1 x i64> @test_xtensa_ae_l32m_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32m_x: + + +%ret = call <1 x i64> @llvm.xtensa.ae.l32m.x(ptr %ars, i32 %art) +; CHECK: ae_l32m.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_l32m_xc.ll +declare { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.xc(ptr, i32) +define <1 x i64> @test_xtensa_ae_l32m_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32m_xc: + + +%ret = call { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.xc(ptr %ars, i32 %art) +; CHECK: ae_l32m.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <1 x i64>, ptr } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_l32m_xu.ll +declare { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.xu(ptr, i32) +define <1 x i64> @test_xtensa_ae_l32m_xu(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32m_xu: + + +%ret = call { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.xu(ptr %ars, i32 %art) +; CHECK: ae_l32m.xu aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <1 x i64>, ptr } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_l32x2_i.ll +declare <2 x i32> @llvm.xtensa.ae.l32x2.i(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32x2_i: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l32x2.i(ptr %ars, i32 -64) +; CHECK: ae_l32x2.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l32x2_ip.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.ip(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32x2_ip: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.ip(ptr %ars, i32 0) +; CHECK: ae_l32x2.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2_ric.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.ric(ptr) +define <2 x i32> @test_xtensa_ae_l32x2_ric(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32x2_ric: + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.ric(ptr %ars) +; CHECK: ae_l32x2.ric aed{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2_rip.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.rip(ptr) +define <2 x i32> @test_xtensa_ae_l32x2_rip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32x2_rip: + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.rip(ptr %ars) +; CHECK: ae_l32x2.rip aed{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2_x.ll +declare <2 x i32> @llvm.xtensa.ae.l32x2.x(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32x2_x: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l32x2.x(ptr %ars, i32 %art) +; CHECK: ae_l32x2.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l32x2_xc.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.xc(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32x2_xc: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.xc(ptr %ars, i32 %art) +; CHECK: ae_l32x2.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2_xp.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.xp(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2_xp(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32x2_xp: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.xp(ptr %ars, i32 %art) +; CHECK: ae_l32x2.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2f24_i.ll +declare <2 x i32> @llvm.xtensa.ae.l32x2f24.i(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2f24_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32x2f24_i: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l32x2f24.i(ptr %ars, i32 -64) +; CHECK: ae_l32x2f24.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l32x2f24_ip.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.ip(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2f24_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32x2f24_ip: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.ip(ptr %ars, i32 0) +; CHECK: ae_l32x2f24.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2f24_ric.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.ric(ptr) +define <2 x i32> @test_xtensa_ae_l32x2f24_ric(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32x2f24_ric: + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.ric(ptr %ars) +; CHECK: ae_l32x2f24.ric aed{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2f24_rip.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.rip(ptr) +define <2 x i32> @test_xtensa_ae_l32x2f24_rip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l32x2f24_rip: + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.rip(ptr %ars) +; CHECK: ae_l32x2f24.rip aed{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2f24_x.ll +declare <2 x i32> @llvm.xtensa.ae.l32x2f24.x(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2f24_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32x2f24_x: + + +%ret = call <2 x i32> @llvm.xtensa.ae.l32x2f24.x(ptr %ars, i32 %art) +; CHECK: ae_l32x2f24.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_l32x2f24_xc.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.xc(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2f24_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32x2f24_xc: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.xc(ptr %ars, i32 %art) +; CHECK: ae_l32x2f24.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l32x2f24_xp.ll +declare { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.xp(ptr, i32) +define <2 x i32> @test_xtensa_ae_l32x2f24_xp(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l32x2f24_xp: + + +%ret = call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.xp(ptr %ars, i32 %art) +; CHECK: ae_l32x2f24.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_l64_i.ll +declare <1 x i64> @llvm.xtensa.ae.l64.i(ptr, i32) +define <1 x i64> @test_xtensa_ae_l64_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l64_i: + + +%ret = call <1 x i64> @llvm.xtensa.ae.l64.i(ptr %ars, i32 -64) +; CHECK: ae_l64.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_l64_ip.ll +declare { <1 x i64>, ptr } @llvm.xtensa.ae.l64.ip(ptr, i32) +define <1 x i64> @test_xtensa_ae_l64_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_l64_ip: + + +%ret = call { <1 x i64>, ptr } @llvm.xtensa.ae.l64.ip(ptr %ars, i32 -64) +; CHECK: ae_l64.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} +%ev = extractvalue { <1 x i64>, ptr } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_l64_x.ll +declare <1 x i64> @llvm.xtensa.ae.l64.x(ptr, i32) +define <1 x i64> @test_xtensa_ae_l64_x(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l64_x: + + +%ret = call <1 x i64> @llvm.xtensa.ae.l64.x(ptr %ars, i32 %art) +; CHECK: ae_l64.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_l64_xc.ll +declare { <1 x i64>, ptr } @llvm.xtensa.ae.l64.xc(ptr, i32) +define <1 x i64> @test_xtensa_ae_l64_xc(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l64_xc: + + +%ret = call { <1 x i64>, ptr } @llvm.xtensa.ae.l64.xc(ptr %ars, i32 %art) +; CHECK: ae_l64.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <1 x i64>, ptr } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_l64_xp.ll +declare { <1 x i64>, ptr } @llvm.xtensa.ae.l64.xp(ptr, i32) +define <1 x i64> @test_xtensa_ae_l64_xp(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_l64_xp: + + +%ret = call { <1 x i64>, ptr } @llvm.xtensa.ae.l64.xp(ptr %ars, i32 %art) +; CHECK: ae_l64.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <1 x i64>, ptr } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_la16x4_ic.ll +declare { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ic(<8 x i8>, ptr) +define <4 x i16> @test_xtensa_ae_la16x4_ic(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la16x4_ic: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ic(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la16x4.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, <8 x i8>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_la16x4_ip.ll +declare { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ip(<8 x i8>, ptr) +define <4 x i16> @test_xtensa_ae_la16x4_ip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la16x4_ip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la16x4.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, <8 x i8>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_la16x4_ric.ll +declare { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ric(<8 x i8>, ptr) +define <4 x i16> @test_xtensa_ae_la16x4_ric(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la16x4_ric: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ric(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la16x4.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, <8 x i8>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_la16x4_rip.ll +declare { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.rip(<8 x i8>, ptr) +define <4 x i16> @test_xtensa_ae_la16x4_rip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la16x4_rip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.rip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la16x4.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <4 x i16>, <8 x i8>, ptr } %ret, 0 +ret <4 x i16> %ev +} + + +;--- ae_la16x4neg_pc.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.la16x4neg.pc(ptr) +define <1 x i64> @test_xtensa_ae_la16x4neg_pc(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la16x4neg_pc: + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.la16x4neg.pc(ptr %ars) +; CHECK: ae_la16x4neg.pc u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_la16x4pos_pc.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.la16x4pos.pc(ptr) +define <1 x i64> @test_xtensa_ae_la16x4pos_pc(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la16x4pos_pc: + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.la16x4pos.pc(ptr %ars) +; CHECK: ae_la16x4pos.pc u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_la24_ic.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ic(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la24_ic(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24_ic: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ic(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la24.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la24_ip.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ip(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la24_ip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24_ip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la24.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la24_ric.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ric(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la24_ric(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24_ric: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ric(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la24.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la24_rip.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.rip(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la24_rip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24_rip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.rip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la24.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la24neg_pc.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.la24neg.pc(ptr) +define <1 x i64> @test_xtensa_ae_la24neg_pc(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24neg_pc: + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.la24neg.pc(ptr %ars) +; CHECK: ae_la24neg.pc u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_la24pos_pc.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.la24pos.pc(ptr) +define <1 x i64> @test_xtensa_ae_la24pos_pc(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24pos_pc: + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.la24pos.pc(ptr %ars) +; CHECK: ae_la24pos.pc u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_la24x2_ic.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ic(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la24x2_ic(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24x2_ic: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ic(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la24x2.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la24x2_ip.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ip(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la24x2_ip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24x2_ip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la24x2.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la24x2_ric.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ric(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la24x2_ric(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24x2_ric: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ric(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la24x2.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la24x2_rip.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.rip(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la24x2_rip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24x2_rip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.rip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la24x2.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la24x2neg_pc.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.la24x2neg.pc(ptr) +define <1 x i64> @test_xtensa_ae_la24x2neg_pc(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24x2neg_pc: + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.la24x2neg.pc(ptr %ars) +; CHECK: ae_la24x2neg.pc u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_la24x2pos_pc.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.la24x2pos.pc(ptr) +define <1 x i64> @test_xtensa_ae_la24x2pos_pc(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la24x2pos_pc: + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.la24x2pos.pc(ptr %ars) +; CHECK: ae_la24x2pos.pc u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_la32x2_ic.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ic(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la32x2_ic(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2_ic: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ic(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la32x2.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la32x2_ip.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ip(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la32x2_ip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2_ip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la32x2.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la32x2_ric.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ric(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la32x2_ric(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2_ric: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ric(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la32x2.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la32x2_rip.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.rip(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la32x2_rip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2_rip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.rip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la32x2.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la32x2f24_ic.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ic(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la32x2f24_ic(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2f24_ic: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ic(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la32x2f24.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la32x2f24_ip.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ip(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la32x2f24_ip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2f24_ip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la32x2f24.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la32x2f24_ric.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ric(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la32x2f24_ric(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2f24_ric: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ric(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la32x2f24.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la32x2f24_rip.ll +declare { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.rip(<8 x i8>, ptr) +define <2 x i32> @test_xtensa_ae_la32x2f24_rip(<1 x i64> %ae_ls_uu, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2f24_rip: +%wrap0 = bitcast <1 x i64> %ae_ls_uu to <8 x i8> + +%ret = call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.rip(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_la32x2f24.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <8 x i8>, ptr } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_la32x2neg_pc.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.la32x2neg.pc(ptr) +define <1 x i64> @test_xtensa_ae_la32x2neg_pc(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2neg_pc: + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.la32x2neg.pc(ptr %ars) +; CHECK: ae_la32x2neg.pc u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_la32x2pos_pc.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.la32x2pos.pc(ptr) +define <1 x i64> @test_xtensa_ae_la32x2pos_pc(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la32x2pos_pc: + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.la32x2pos.pc(ptr %ars) +; CHECK: ae_la32x2pos.pc u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_la64_pp.ll +declare <8 x i8> @llvm.xtensa.ae.la64.pp(ptr) +define <8 x i8> @test_xtensa_ae_la64_pp(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_la64_pp: + +%ret = call <8 x i8> @llvm.xtensa.ae.la64.pp(ptr %ars) +; CHECK: ae_la64.pp u{{[0-9]+}}, a{{[0-9]+}} + +ret <8 x i8> %ret +} + + +;--- ae_lalign64_i.ll +declare <8 x i8> @llvm.xtensa.ae.lalign64.i(ptr, i32) +define <8 x i8> @test_xtensa_ae_lalign64_i(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_lalign64_i: + + +%ret = call <8 x i8> @llvm.xtensa.ae.lalign64.i(ptr %ars, i32 -64) +; CHECK: ae_lalign64.i u{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret <8 x i8> %ret +} + + +;--- ae_lb.ll +declare i32 @llvm.xtensa.ae.lb(i32) +define i32 @test_xtensa_ae_lb(i32 %art) { +; CHECK-LABEL: test_xtensa_ae_lb: + +%ret = call i32 @llvm.xtensa.ae.lb(i32 %art) +; CHECK: ae_lb a{{[0-9]+}}, a{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_lbi.ll +declare i32 @llvm.xtensa.ae.lbi(i32) +define i32 @test_xtensa_ae_lbi() { +; CHECK-LABEL: test_xtensa_ae_lbi: + +%ret = call i32 @llvm.xtensa.ae.lbi(i32 1) +; CHECK: ae_lbi a{{[0-9]+}}, {{-?[0-9]+}} + +ret i32 %ret +} + + +;--- ae_lbk.ll +declare i32 @llvm.xtensa.ae.lbk(i32, i32) +define i32 @test_xtensa_ae_lbk(i32 %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_lbk: + + +%ret = call i32 @llvm.xtensa.ae.lbk(i32 %ars, i32 %art) +; CHECK: ae_lbk a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_lbki.ll +declare i32 @llvm.xtensa.ae.lbki(i32, i32) +define i32 @test_xtensa_ae_lbki(i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_lbki: + + +%ret = call i32 @llvm.xtensa.ae.lbki(i32 %ars, i32 1) +; CHECK: ae_lbki a{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret i32 %ret +} + + +;--- ae_lbs.ll +declare i32 @llvm.xtensa.ae.lbs(i32) +define i32 @test_xtensa_ae_lbs(i32 %art) { +; CHECK-LABEL: test_xtensa_ae_lbs: + +%ret = call i32 @llvm.xtensa.ae.lbs(i32 %art) +; CHECK: ae_lbs a{{[0-9]+}}, a{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_lbsi.ll +declare i32 @llvm.xtensa.ae.lbsi(i32) +define i32 @test_xtensa_ae_lbsi() { +; CHECK-LABEL: test_xtensa_ae_lbsi: + +%ret = call i32 @llvm.xtensa.ae.lbsi(i32 1) +; CHECK: ae_lbsi a{{[0-9]+}}, {{-?[0-9]+}} + +ret i32 %ret +} + + +;--- ae_le64.ll +declare <1 x i1> @llvm.xtensa.ae.le64(<1 x i64>, <1 x i64>) +define <1 x i1> @test_xtensa_ae_le64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_le64: + + +%ret = call <1 x i1> @llvm.xtensa.ae.le64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) +; CHECK: ae_le64 b{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i1> %ret +} + + +;--- ae_lt64.ll +declare <1 x i1> @llvm.xtensa.ae.lt64(<1 x i64>, <1 x i64>) +define <1 x i1> @test_xtensa_ae_lt64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_lt64: + + +%ret = call <1 x i1> @llvm.xtensa.ae.lt64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) +; CHECK: ae_lt64 b{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i1> %ret +} + + +;--- ae_max32.ll +declare <2 x i32> @llvm.xtensa.ae.max32(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_max32(<2 x i32> %ae_cmpp_v0, <2 x i32> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_max32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.max32(<2 x i32> %ae_cmpp_v0, <2 x i32> %ae_cmpp_v1) +; CHECK: ae_max32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_max64.ll +declare <1 x i64> @llvm.xtensa.ae.max64(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_max64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_max64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.max64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) +; CHECK: ae_max64 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_maxabs32s.ll +declare <2 x i32> @llvm.xtensa.ae.maxabs32s(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_maxabs32s(<2 x i32> %ae_cmpp_v0, <2 x i32> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_maxabs32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.maxabs32s(<2 x i32> %ae_cmpp_v0, <2 x i32> %ae_cmpp_v1) +; CHECK: ae_maxabs32s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_maxabs64s.ll +declare <1 x i64> @llvm.xtensa.ae.maxabs64s(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_maxabs64s(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_maxabs64s: + + +%ret = call <1 x i64> @llvm.xtensa.ae.maxabs64s(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) +; CHECK: ae_maxabs64s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_min32.ll +declare <2 x i32> @llvm.xtensa.ae.min32(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_min32(<2 x i32> %ae_cmpp_v0, <2 x i32> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_min32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.min32(<2 x i32> %ae_cmpp_v0, <2 x i32> %ae_cmpp_v1) +; CHECK: ae_min32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_min64.ll +declare <1 x i64> @llvm.xtensa.ae.min64(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_min64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_min64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.min64(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) +; CHECK: ae_min64 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_minabs32s.ll +declare <2 x i32> @llvm.xtensa.ae.minabs32s(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_minabs32s(<2 x i32> %ae_cmpp_v0, <2 x i32> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_minabs32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.minabs32s(<2 x i32> %ae_cmpp_v0, <2 x i32> %ae_cmpp_v1) +; CHECK: ae_minabs32s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_minabs64s.ll +declare <1 x i64> @llvm.xtensa.ae.minabs64s(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_minabs64s(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) { +; CHECK-LABEL: test_xtensa_ae_minabs64s: + + +%ret = call <1 x i64> @llvm.xtensa.ae.minabs64s(<1 x i64> %ae_cmpp_v0, <1 x i64> %ae_cmpp_v1) +; CHECK: ae_minabs64s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mov.ll +declare <1 x i64> @llvm.xtensa.ae.mov(<1 x i64>) +define <1 x i64> @test_xtensa_ae_mov(<1 x i64> %ae_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_mov: + +%ret = call <1 x i64> @llvm.xtensa.ae.mov(<1 x i64> %ae_to_dr_v0) +; CHECK: ae_mov aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_movad16_0.ll +declare i32 @llvm.xtensa.ae.movad16.0(<4 x i16>) +define i32 @test_xtensa_ae_movad16_0(<4 x i16> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_movad16_0: + +%ret = call i32 @llvm.xtensa.ae.movad16.0(<4 x i16> %ae_dr_to_ar_v0) +; CHECK: ae_movad16.0 a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_movad16_1.ll +declare i32 @llvm.xtensa.ae.movad16.1(<4 x i16>) +define i32 @test_xtensa_ae_movad16_1(<4 x i16> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_movad16_1: + +%ret = call i32 @llvm.xtensa.ae.movad16.1(<4 x i16> %ae_dr_to_ar_v0) +; CHECK: ae_movad16.1 a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_movad16_2.ll +declare i32 @llvm.xtensa.ae.movad16.2(<4 x i16>) +define i32 @test_xtensa_ae_movad16_2(<4 x i16> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_movad16_2: + +%ret = call i32 @llvm.xtensa.ae.movad16.2(<4 x i16> %ae_dr_to_ar_v0) +; CHECK: ae_movad16.2 a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_movad16_3.ll +declare i32 @llvm.xtensa.ae.movad16.3(<4 x i16>) +define i32 @test_xtensa_ae_movad16_3(<4 x i16> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_movad16_3: + +%ret = call i32 @llvm.xtensa.ae.movad16.3(<4 x i16> %ae_dr_to_ar_v0) +; CHECK: ae_movad16.3 a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_movad32_h.ll +declare i32 @llvm.xtensa.ae.movad32.h(<2 x i32>) +define i32 @test_xtensa_ae_movad32_h(<2 x i32> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_movad32_h: + +%ret = call i32 @llvm.xtensa.ae.movad32.h(<2 x i32> %ae_dr_to_ar_v0) +; CHECK: ae_movad32.h a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_movad32_l.ll +declare i32 @llvm.xtensa.ae.movad32.l(<2 x i32>) +define i32 @test_xtensa_ae_movad32_l(<2 x i32> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_movad32_l: + +%ret = call i32 @llvm.xtensa.ae.movad32.l(<2 x i32> %ae_dr_to_ar_v0) +; CHECK: ae_movad32.l a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_movalign.ll +declare <8 x i8> @llvm.xtensa.ae.movalign(<8 x i8>) +define <8 x i8> @test_xtensa_ae_movalign(<1 x i64> %ae_uu_v) { +; CHECK-LABEL: test_xtensa_ae_movalign: +%wrap0 = bitcast <1 x i64> %ae_uu_v to <8 x i8> +%ret = call <8 x i8> @llvm.xtensa.ae.movalign(<8 x i8> %wrap0) +; CHECK: ae_movalign u{{[0-9]+}}, u{{[0-9]+}} + +ret <8 x i8> %ret +} + + +;--- ae_movda16.ll +declare <4 x i16> @llvm.xtensa.ae.movda16(i32) +define <4 x i16> @test_xtensa_ae_movda16(i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_movda16: + +%ret = call <4 x i16> @llvm.xtensa.ae.movda16(i32 %ars) +; CHECK: ae_movda16 aed{{[0-9]+}}, a{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_movda16x2.ll +declare <4 x i16> @llvm.xtensa.ae.movda16x2(i32, i32) +define <4 x i16> @test_xtensa_ae_movda16x2(i32 %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_movda16x2: + + +%ret = call <4 x i16> @llvm.xtensa.ae.movda16x2(i32 %ars, i32 %art) +; CHECK: ae_movda16x2 aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_movda32.ll +declare <1 x i32> @llvm.xtensa.ae.movda32(i32) +define <1 x i32> @test_xtensa_ae_movda32(i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_movda32: + +%ret = call <1 x i32> @llvm.xtensa.ae.movda32(i32 %ars) +; CHECK: ae_movda32 aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i32> %ret +} + + +;--- ae_movda32x2.ll +declare <2 x i32> @llvm.xtensa.ae.movda32x2(i32, i32) +define <2 x i32> @test_xtensa_ae_movda32x2(i32 %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_movda32x2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.movda32x2(i32 %ars, i32 %art) +; CHECK: ae_movda32x2 aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_movf64.ll +declare <1 x i64> @llvm.xtensa.ae.movf64(<1 x i64>, <1 x i64>, <1 x i1>) +define <1 x i64> @test_xtensa_ae_movf64(<1 x i64> %ae_cmov_v, <1 x i64> %ae_cmov_v0, <1 x i1> %bt) { +; CHECK-LABEL: test_xtensa_ae_movf64: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.movf64(<1 x i64> %ae_cmov_v, <1 x i64> %ae_cmov_v0, <1 x i1> %bt) +; CHECK: ae_movf64 aed{{[0-9]+}}, aed{{[0-9]+}}, b{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_movi.ll +declare <2 x i32> @llvm.xtensa.ae.movi(i32) +define <2 x i32> @test_xtensa_ae_movi() { +; CHECK-LABEL: test_xtensa_ae_movi: + +%ret = call <2 x i32> @llvm.xtensa.ae.movi(i32 -16) +; CHECK: ae_movi aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_movt64.ll +declare <1 x i64> @llvm.xtensa.ae.movt64(<1 x i64>, <1 x i64>, <1 x i1>) +define <1 x i64> @test_xtensa_ae_movt64(<1 x i64> %ae_cmov_v, <1 x i64> %ae_cmov_v0, <1 x i1> %bt) { +; CHECK-LABEL: test_xtensa_ae_movt64: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.movt64(<1 x i64> %ae_cmov_v, <1 x i64> %ae_cmov_v0, <1 x i1> %bt) +; CHECK: ae_movt64 aed{{[0-9]+}}, aed{{[0-9]+}}, b{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul16x4.ll +declare { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mul16x4(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mul16x4(<4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) { +; CHECK-LABEL: test_xtensa_ae_mul16x4: + + +%ret = call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mul16x4(<4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) +; CHECK: ae_mul16x4 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <2 x i32> } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_mul32_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mul32.hh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mul32_hh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32_hh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32.hh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mul32.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mul32_lh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32.lh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mul32.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mul32_ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32.ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mul32_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mul32.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32u_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mul32u.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mul32u_ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32u_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32u.ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32u.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_h0.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.h0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_h0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_h0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.h0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32x16.h0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_h0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.h0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_h0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_h0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.h0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mul32x16.h0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_h1.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.h1(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_h1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_h1: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.h1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32x16.h1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_h1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.h1.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_h1_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_h1_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.h1.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mul32x16.h1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_h2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.h2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_h2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_h2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.h2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32x16.h2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_h2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.h2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_h2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_h2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.h2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mul32x16.h2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_h3.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.h3(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_h3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_h3: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.h3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32x16.h3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_h3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.h3.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_h3_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_h3_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.h3.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mul32x16.h3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32x16.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mul32x16.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.l1(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_l1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_l1: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.l1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32x16.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.l1.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_l1_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_l1_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.l1.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mul32x16.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32x16.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mul32x16.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.l3(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_l3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_l3: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.l3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mul32x16.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mul32x16_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mul32x16.l3.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mul32x16_l3_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mul32x16_l3_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mul32x16.l3.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mul32x16.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula16x4.ll +declare { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mula16x4(<2 x i32>, <2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mula16x4(<2 x i32> %ae_mul_q1, <2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) { +; CHECK-LABEL: test_xtensa_ae_mula16x4: + + + + +%ret = call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mula16x4(<2 x i32> %ae_mul_q1, <2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) +; CHECK: ae_mula16x4 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <2 x i32> } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_mula32_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mula32.hh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mula32_hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32_hh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32.hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mula32.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mula32_lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32.lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mula32.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mula32_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mula32_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mula32.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32u_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mula32u.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mula32u_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32u_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32u.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32u.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_h0.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.h0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_h0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_h0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.h0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32x16.h0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_h0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.h0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_h0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_h0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.h0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mula32x16.h0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_h1.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.h1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_h1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_h1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.h1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32x16.h1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_h1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.h1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_h1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_h1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.h1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mula32x16.h1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_h2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.h2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_h2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_h2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.h2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32x16.h2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_h2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.h2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_h2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_h2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.h2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mula32x16.h2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_h3.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.h3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_h3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_h3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.h3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32x16.h3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_h3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.h3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_h3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_h3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.h3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mula32x16.h3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32x16.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mula32x16.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.l1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_l1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32x16.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.l1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_l1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_l1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.l1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mula32x16.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32x16.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mula32x16.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.l3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_l3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mula32x16.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mula32x16_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mula32x16.l3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mula32x16_l3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mula32x16_l3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mula32x16.l3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mula32x16.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad24.hh.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaad24_hh_ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad24_hh_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad24.hh.ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulaad24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad24.hh.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaad24_hh_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad24_hh_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad24.hh.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaad24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad24.hl.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaad24_hl_lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad24_hl_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad24.hl.lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulaad24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad24.hl.lh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaad24_hl_lh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad24_hl_lh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad24.hl.lh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaad24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad32x16_h0_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad32x16.h0.l1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaad32x16_h0_l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad32x16_h0_l1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h0.l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaad32x16.h0.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad32x16_h0_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad32x16.h0.l1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaad32x16_h0_l1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad32x16_h0_l1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h0.l1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaad32x16.h0.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad32x16.h1.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaad32x16_h1_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad32x16_h1_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h1.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaad32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad32x16.h1.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaad32x16_h1_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad32x16_h1_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h1.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaad32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad32x16_h2_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad32x16.h2.l3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaad32x16_h2_l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad32x16_h2_l3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h2.l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaad32x16.h2.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad32x16_h2_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad32x16.h2.l3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaad32x16_h2_l3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad32x16_h2_l3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h2.l3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaad32x16.h2.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad32x16.h3.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaad32x16_h3_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad32x16_h3_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h3.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaad32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaad32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaad32x16.h3.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaad32x16_h3_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaad32x16_h3_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h3.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaad32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd16ss_11_00.ll +declare <2 x i32> @llvm.xtensa.ae.mulaafd16ss.11.00(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaafd16ss_11_00(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd16ss_11_00: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.11.00(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaafd16ss.11_00 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaafd16ss_11_00_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulaafd16ss.11.00.s2(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaafd16ss_11_00_s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd16ss_11_00_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.11.00.s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaafd16ss.11_00_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaafd16ss_13_02.ll +declare <2 x i32> @llvm.xtensa.ae.mulaafd16ss.13.02(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaafd16ss_13_02(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd16ss_13_02: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.13.02(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaafd16ss.13_02 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaafd16ss_13_02_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulaafd16ss.13.02.s2(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaafd16ss_13_02_s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd16ss_13_02_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.13.02.s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaafd16ss.13_02_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaafd16ss_33_22.ll +declare <2 x i32> @llvm.xtensa.ae.mulaafd16ss.33.22(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaafd16ss_33_22(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd16ss_33_22: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.33.22(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaafd16ss.33_22 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaafd16ss_33_22_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulaafd16ss.33.22.s2(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaafd16ss_33_22_s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd16ss_33_22_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.33.22.s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaafd16ss.33_22_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaafd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd24.hh.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaafd24_hh_ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd24_hh_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd24.hh.ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulaafd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd24.hh.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaafd24_hh_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd24_hh_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd24.hh.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaafd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd24.hl.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaafd24_hl_lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd24_hl_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd24.hl.lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulaafd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd24.hl.lh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaafd24_hl_lh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd24_hl_lh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd24.hl.lh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaafd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd32x16_h0_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h0.l1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaafd32x16_h0_l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd32x16_h0_l1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h0.l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaafd32x16.h0.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd32x16_h0_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h0.l1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaafd32x16_h0_l1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd32x16_h0_l1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h0.l1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaafd32x16.h0.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h1.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaafd32x16_h1_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd32x16_h1_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h1.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaafd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h1.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaafd32x16_h1_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd32x16_h1_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h1.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaafd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd32x16_h2_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h2.l3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaafd32x16_h2_l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd32x16_h2_l3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h2.l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaafd32x16.h2.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd32x16_h2_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h2.l3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaafd32x16_h2_l3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd32x16_h2_l3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h2.l3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaafd32x16.h2.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h3.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaafd32x16_h3_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd32x16_h3_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h3.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaafd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaafd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h3.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaafd32x16_h3_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaafd32x16_h3_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h3.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaafd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulac24.ll +declare <2 x i32> @llvm.xtensa.ae.mulac24(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulac24(<2 x i32> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulac24: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulac24(<2 x i32> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulac24 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulac32x16_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulac32x16.h(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulac32x16_h(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulac32x16_h: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulac32x16.h(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulac32x16.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulac32x16_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulac32x16.l(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulac32x16_l(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulac32x16_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulac32x16.l(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulac32x16.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_00.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.00(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_00(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_00: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.00(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf16ss.00 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_00_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.00.s2(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_00_s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_00_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.00.s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf16ss.00_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_10.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.10(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_10(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_10: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.10(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.10 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_11.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.11(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_11(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_11: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.11(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.11 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_20.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.20(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_20(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_20: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.20(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.20 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_21.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.21(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_21(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_21: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.21(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.21 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_22.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.22(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_22(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_22: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.22(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.22 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_30.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.30(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_30(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_30: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.30(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.30 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_31.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.31(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_31(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_31: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.31(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.31 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_32.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.32(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_32(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_32: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.32(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16ss_33.ll +declare <2 x i32> @llvm.xtensa.ae.mulaf16ss.33(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16ss_33(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf16ss_33: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulaf16ss.33(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulaf16ss.33 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaf16x4ss.ll +declare { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulaf16x4ss(<2 x i32>, <2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulaf16x4ss(<2 x i32> %ae_mul_q1, <2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) { +; CHECK-LABEL: test_xtensa_ae_mulaf16x4ss: + + + + +%ret = call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulaf16x4ss(<2 x i32> %ae_mul_q1, <2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) +; CHECK: ae_mulaf16x4ss aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <2 x i32> } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_mulaf32r_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32r.hh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf32r_hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32r_hh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32r.hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32r.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32r_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32r.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf32r_lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32r_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32r.lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32r.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32r_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32r.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf32r_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32r_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32r.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32r.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32r_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32r.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf32r_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32r_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32r.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaf32r.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32s_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32s.hh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf32s_hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32s_hh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32s.hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32s.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32s_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32s.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf32s_lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32s_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32s.lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32s.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32s_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32s.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf32s_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32s_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32s.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32s.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32s_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32s.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf32s_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32s_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32s.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaf32s.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_h0.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.h0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_h0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_h0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32x16.h0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_h0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.h0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_h0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_h0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf32x16.h0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_h1.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.h1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_h1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_h1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32x16.h1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_h1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.h1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_h1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_h1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf32x16.h1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_h2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.h2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_h2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_h2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32x16.h2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_h2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.h2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_h2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_h2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf32x16.h2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_h3.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.h3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_h3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_h3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32x16.h3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_h3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.h3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_h3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_h3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf32x16.h3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32x16.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf32x16.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.l1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_l1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32x16.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.l1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_l1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_l1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf32x16.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32x16.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf32x16.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.l3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_l3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf32x16.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf32x16_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf32x16.l3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulaf32x16_l3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf32x16_l3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulaf32x16.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf48q32sp16s_l.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16s.l(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf48q32sp16s_l(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf48q32sp16s_l: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16s.l(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf48q32sp16s.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf48q32sp16s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16s.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf48q32sp16s_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf48q32sp16s_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16s.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaf48q32sp16s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf48q32sp16u_l.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16u.l(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf48q32sp16u_l(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf48q32sp16u_l: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16u.l(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulaf48q32sp16u.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaf48q32sp16u_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16u.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaf48q32sp16u_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaf48q32sp16u_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16u.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaf48q32sp16u.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulafc24ra.ll +declare <2 x i32> @llvm.xtensa.ae.mulafc24ra(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulafc24ra(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <2 x i32> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafc24ra: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafc24ra(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <2 x i32> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulafc24ra aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafc32x16ras_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulafc32x16ras.h(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafc32x16ras_h(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafc32x16ras_h: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafc32x16ras.h(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulafc32x16ras.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafc32x16ras_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulafc32x16ras.l(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafc32x16ras_l(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafc32x16ras_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafc32x16ras.l(<2 x i32> %opnd_ae_sem_mul_x4_q0, <2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulafc32x16ras.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafd24x2_fir_h.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd24x2.fir.h(<1 x i64>, <1 x i64>, <2 x i32>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulafd24x2_fir_h(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <2 x i32> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulafd24x2_fir_h: + + + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd24x2.fir.h(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <2 x i32> %ae_mul_d2) +; CHECK: ae_mulafd24x2.fir.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulafd24x2_fir_l.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd24x2.fir.l(<1 x i64>, <1 x i64>, <2 x i32>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulafd24x2_fir_l(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <2 x i32> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulafd24x2_fir_l: + + + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd24x2.fir.l(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <2 x i32> %ae_mul_d2) +; CHECK: ae_mulafd24x2.fir.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulafd32x16x2_fir_hh.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.hh(<1 x i64>, <1 x i64>, <2 x i32>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulafd32x16x2_fir_hh(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulafd32x16x2_fir_hh: + + + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.hh(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) +; CHECK: ae_mulafd32x16x2.fir.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulafd32x16x2_fir_hl.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.hl(<1 x i64>, <1 x i64>, <2 x i32>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulafd32x16x2_fir_hl(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulafd32x16x2_fir_hl: + + + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.hl(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) +; CHECK: ae_mulafd32x16x2.fir.hl aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulafd32x16x2_fir_lh.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.lh(<1 x i64>, <1 x i64>, <2 x i32>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulafd32x16x2_fir_lh(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulafd32x16x2_fir_lh: + + + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.lh(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) +; CHECK: ae_mulafd32x16x2.fir.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulafd32x16x2_fir_ll.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.ll(<1 x i64>, <1 x i64>, <2 x i32>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulafd32x16x2_fir_ll(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulafd32x16x2_fir_ll: + + + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.ll(<1 x i64> %ae_mul_q0, <1 x i64> %ae_mul_q1, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) +; CHECK: ae_mulafd32x16x2.fir.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulafp24x2r.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp24x2r(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulafp24x2r(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp24x2r: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp24x2r(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulafp24x2r aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp24x2r_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp24x2r.s2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulafp24x2r_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp24x2r_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp24x2r.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulafp24x2r_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp24x2ra.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp24x2ra(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulafp24x2ra(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp24x2ra: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp24x2ra(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulafp24x2ra aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp24x2ra_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp24x2ra.s2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulafp24x2ra_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp24x2ra_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp24x2ra.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulafp24x2ra_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x16x2ras_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.h(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafp32x16x2ras_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x16x2ras_h: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulafp32x16x2ras.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x16x2ras_h_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.h.s2(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafp32x16x2ras_h_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x16x2ras_h_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.h.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulafp32x16x2ras.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x16x2ras_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.l(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafp32x16x2ras_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x16x2ras_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulafp32x16x2ras.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x16x2ras_l_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.l.s2(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafp32x16x2ras_l_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x16x2ras_l_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.l.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulafp32x16x2ras.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x16x2rs_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.h(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafp32x16x2rs_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x16x2rs_h: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulafp32x16x2rs.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x16x2rs_h_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.h.s2(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafp32x16x2rs_h_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x16x2rs_h_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.h.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulafp32x16x2rs.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x16x2rs_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.l(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafp32x16x2rs_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x16x2rs_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulafp32x16x2rs.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x16x2rs_l_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.l.s2(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulafp32x16x2rs_l_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x16x2rs_l_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.l.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulafp32x16x2rs.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x2ras.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x2ras(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulafp32x2ras(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x2ras: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x2ras(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulafp32x2ras aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafp32x2rs.ll +declare <2 x i32> @llvm.xtensa.ae.mulafp32x2rs(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulafp32x2rs(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafp32x2rs: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulafp32x2rs(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulafp32x2rs aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulafq32sp24s_h_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulafq32sp24s.h.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulafq32sp24s_h_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafq32sp24s_h_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulafq32sp24s.h.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulafq32sp24s.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulafq32sp24s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulafq32sp24s.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulafq32sp24s_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulafq32sp24s_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulafq32sp24s.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulafq32sp24s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulap24x2.ll +declare <2 x i32> @llvm.xtensa.ae.mulap24x2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulap24x2(<2 x i32> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulap24x2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulap24x2(<2 x i32> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulap24x2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulap24x2_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulap24x2.s2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulap24x2_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulap24x2_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulap24x2.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulap24x2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulap32x16x2_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulap32x16x2.h(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulap32x16x2_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulap32x16x2_h: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulap32x16x2.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulap32x16x2.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulap32x16x2_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulap32x16x2.l(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulap32x16x2_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulap32x16x2_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulap32x16x2.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulap32x16x2.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulap32x2.ll +declare <2 x i32> @llvm.xtensa.ae.mulap32x2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulap32x2(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulap32x2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulap32x2(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulap32x2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulaq32sp16s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaq32sp16s.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaq32sp16s_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaq32sp16s_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaq32sp16s.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaq32sp16s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulaq32sp16u_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulaq32sp16u.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulaq32sp16u_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulaq32sp16u_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulaq32sp16u.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulaq32sp16u.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mularfq32sp24s_h_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mularfq32sp24s.h.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mularfq32sp24s_h_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mularfq32sp24s_h_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mularfq32sp24s.h.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mularfq32sp24s.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mularfq32sp24s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mularfq32sp24s.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mularfq32sp24s_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mularfq32sp24s_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mularfq32sp24s.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mularfq32sp24s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulas32f48p16s_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.hh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulas32f48p16s_hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulas32f48p16s_hh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulas32f48p16s.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulas32f48p16s_hh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.hh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulas32f48p16s_hh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulas32f48p16s_hh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.hh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulas32f48p16s.hh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulas32f48p16s_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulas32f48p16s_lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulas32f48p16s_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulas32f48p16s.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulas32f48p16s_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.lh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulas32f48p16s_lh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulas32f48p16s_lh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.lh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulas32f48p16s.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulas32f48p16s_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulas32f48p16s_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulas32f48p16s_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulas32f48p16s.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulas32f48p16s_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulas32f48p16s_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulas32f48p16s_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulas32f48p16s.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulasd24.hh.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulasd24_hh_ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasd24_hh_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasd24.hh.ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulasd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasd24.hh.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulasd24_hh_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasd24_hh_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasd24.hh.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulasd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulasd24.hl.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulasd24_hl_lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasd24_hl_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasd24.hl.lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulasd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasd24.hl.lh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulasd24_hl_lh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasd24_hl_lh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasd24.hl.lh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulasd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulasd32x16.h1.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulasd32x16_h1_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasd32x16_h1_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasd32x16.h1.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulasd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasd32x16.h1.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulasd32x16_h1_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasd32x16_h1_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasd32x16.h1.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulasd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasd32x16.h3.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulasd32x16_h3_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasd32x16_h3_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasd32x16.h3.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulasd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasd32x16.h3.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulasd32x16_h3_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasd32x16_h3_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasd32x16.h3.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulasd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasfd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulasfd24.hh.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulasfd24_hh_ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasfd24_hh_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasfd24.hh.ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulasfd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasfd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasfd24.hh.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulasfd24_hh_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasfd24_hh_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasfd24.hh.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulasfd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasfd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulasfd24.hl.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulasfd24_hl_lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasfd24_hl_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasfd24.hl.lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulasfd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasfd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasfd24.hl.lh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulasfd24_hl_lh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasfd24_hl_lh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasfd24.hl.lh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulasfd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasfd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h1.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulasfd32x16_h1_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasfd32x16_h1_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h1.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulasfd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasfd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h1.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulasfd32x16_h1_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasfd32x16_h1_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h1.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulasfd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasfd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h3.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulasfd32x16_h3_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasfd32x16_h3_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h3.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulasfd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulasfd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h3.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulasfd32x16_h3_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulasfd32x16_h3_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h3.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulasfd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulc24.ll +declare <2 x i32> @llvm.xtensa.ae.mulc24(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulc24(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulc24: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulc24(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulc24 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulc32x16_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulc32x16.h(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulc32x16_h(<2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulc32x16_h: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulc32x16.h(<2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulc32x16.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulc32x16_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulc32x16.l(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulc32x16_l(<2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulc32x16_l: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulc32x16.l(<2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulc32x16.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_00.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.00(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_00(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_00: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.00(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf16ss.00 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_00_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.00.s2(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_00_s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_00_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.00.s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf16ss.00_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_10.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.10(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_10(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_10: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.10(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.10 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_11.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.11(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_11(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_11: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.11(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.11 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_20.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.20(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_20(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_20: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.20(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.20 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_21.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.21(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_21(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_21: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.21(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.21 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_22.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.22(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_22(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_22: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.22(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.22 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_30.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.30(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_30(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_30: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.30(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.30 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_31.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.31(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_31(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_31: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.31(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.31 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_32.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.32(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_32(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.32(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16ss_33.ll +declare <2 x i32> @llvm.xtensa.ae.mulf16ss.33(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16ss_33(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf16ss_33: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulf16ss.33(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulf16ss.33 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulf16x4ss.ll +declare { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulf16x4ss(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulf16x4ss(<4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) { +; CHECK-LABEL: test_xtensa_ae_mulf16x4ss: + + +%ret = call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulf16x4ss(<4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) +; CHECK: ae_mulf16x4ss aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <2 x i32> } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_mulf32r_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32r.hh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf32r_hh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32r_hh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32r.hh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32r.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32r_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32r.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf32r_lh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32r_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32r.lh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32r.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32r_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32r.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf32r_ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32r_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32r.ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32r.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32r_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32r.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf32r_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32r_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32r.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulf32r.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32s_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32s.hh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf32s_hh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32s_hh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32s.hh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32s.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32s_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32s.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf32s_lh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32s_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32s.lh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32s.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32s_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32s.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf32s_ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32s_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32s.ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32s.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32s_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32s.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf32s_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32s_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32s.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulf32s.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_h0.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.h0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_h0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_h0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.h0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32x16.h0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_h0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.h0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_h0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_h0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.h0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf32x16.h0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_h1.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.h1(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_h1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_h1: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.h1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32x16.h1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_h1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.h1.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_h1_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_h1_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.h1.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf32x16.h1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_h2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.h2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_h2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_h2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.h2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32x16.h2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_h2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.h2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_h2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_h2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.h2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf32x16.h2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_h3.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.h3(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_h3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_h3: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.h3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32x16.h3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_h3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.h3.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_h3_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_h3_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.h3.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf32x16.h3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32x16.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf32x16.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.l1(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_l1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_l1: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.l1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32x16.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.l1.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_l1_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_l1_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.l1.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf32x16.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32x16.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf32x16.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.l3(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_l3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_l3: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.l3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf32x16.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf32x16_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf32x16.l3.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulf32x16_l3_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf32x16_l3_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf32x16.l3.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulf32x16.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf48q32sp16s_l.ll +declare <1 x i64> @llvm.xtensa.ae.mulf48q32sp16s.l(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf48q32sp16s_l(<1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf48q32sp16s_l: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf48q32sp16s.l(<1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf48q32sp16s.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf48q32sp16s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf48q32sp16s.l.s2(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf48q32sp16s_l_s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf48q32sp16s_l_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf48q32sp16s.l.s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulf48q32sp16s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf48q32sp16u_l.ll +declare <1 x i64> @llvm.xtensa.ae.mulf48q32sp16u.l(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf48q32sp16u_l(<1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf48q32sp16u_l: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf48q32sp16u.l(<1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulf48q32sp16u.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulf48q32sp16u_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulf48q32sp16u.l.s2(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulf48q32sp16u_l_s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulf48q32sp16u_l_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulf48q32sp16u.l.s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulf48q32sp16u.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulfc24ra.ll +declare <2 x i32> @llvm.xtensa.ae.mulfc24ra(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulfc24ra(<2 x i32> %opnd_ae_sem_mul_x4_d0, <2 x i32> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfc24ra: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfc24ra(<2 x i32> %opnd_ae_sem_mul_x4_d0, <2 x i32> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulfc24ra aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfc32x16ras_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulfc32x16ras.h(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfc32x16ras_h(<2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfc32x16ras_h: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfc32x16ras.h(<2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulfc32x16ras.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfc32x16ras_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulfc32x16ras.l(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfc32x16ras_l(<2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfc32x16ras_l: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfc32x16ras.l(<2 x i32> %opnd_ae_sem_mul_x4_d0, <4 x i16> %opnd_ae_sem_mul_x4_d1) +; CHECK: ae_mulfc32x16ras.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfd24x2_fir_h.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd24x2.fir.h(<2 x i32>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulfd24x2_fir_h(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <2 x i32> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulfd24x2_fir_h: + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd24x2.fir.h(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <2 x i32> %ae_mul_d2) +; CHECK: ae_mulfd24x2.fir.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulfd24x2_fir_l.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd24x2.fir.l(<2 x i32>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulfd24x2_fir_l(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <2 x i32> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulfd24x2_fir_l: + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd24x2.fir.l(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <2 x i32> %ae_mul_d2) +; CHECK: ae_mulfd24x2.fir.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulfd32x16x2_fir_hh.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.hh(<2 x i32>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulfd32x16x2_fir_hh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulfd32x16x2_fir_hh: + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.hh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) +; CHECK: ae_mulfd32x16x2.fir.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulfd32x16x2_fir_hl.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.hl(<2 x i32>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulfd32x16x2_fir_hl(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulfd32x16x2_fir_hl: + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.hl(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) +; CHECK: ae_mulfd32x16x2.fir.hl aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulfd32x16x2_fir_lh.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.lh(<2 x i32>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulfd32x16x2_fir_lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulfd32x16x2_fir_lh: + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) +; CHECK: ae_mulfd32x16x2.fir.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulfd32x16x2_fir_ll.ll +declare { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.ll(<2 x i32>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulfd32x16x2_fir_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) { +; CHECK-LABEL: test_xtensa_ae_mulfd32x16x2_fir_ll: + + + +%ret = call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1, <4 x i16> %ae_mul_d2) +; CHECK: ae_mulfd32x16x2.fir.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <1 x i64>, <1 x i64> } %ret, 0 +ret <1 x i64> %ev +} + + +;--- ae_mulfp16x4ras.ll +declare <4 x i16> @llvm.xtensa.ae.mulfp16x4ras(<4 x i16>, <4 x i16>) +define <4 x i16> @test_xtensa_ae_mulfp16x4ras(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp16x4ras: + + +%ret = call <4 x i16> @llvm.xtensa.ae.mulfp16x4ras(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulfp16x4ras aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_mulfp16x4s.ll +declare <4 x i16> @llvm.xtensa.ae.mulfp16x4s(<4 x i16>, <4 x i16>) +define <4 x i16> @test_xtensa_ae_mulfp16x4s(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp16x4s: + + +%ret = call <4 x i16> @llvm.xtensa.ae.mulfp16x4s(<4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulfp16x4s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_mulfp24x2r.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp24x2r(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulfp24x2r(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp24x2r: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp24x2r(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulfp24x2r aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp24x2r_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp24x2r.s2(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulfp24x2r_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp24x2r_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp24x2r.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulfp24x2r_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp24x2ra.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp24x2ra(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulfp24x2ra(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp24x2ra: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp24x2ra(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulfp24x2ra aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp24x2ra_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp24x2ra.s2(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulfp24x2ra_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp24x2ra_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp24x2ra.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulfp24x2ra_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x16x2ras_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.h(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfp32x16x2ras_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x16x2ras_h: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulfp32x16x2ras.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x16x2ras_h_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.h.s2(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfp32x16x2ras_h_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x16x2ras_h_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.h.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulfp32x16x2ras.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x16x2ras_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.l(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfp32x16x2ras_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x16x2ras_l: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulfp32x16x2ras.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x16x2ras_l_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.l.s2(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfp32x16x2ras_l_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x16x2ras_l_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.l.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulfp32x16x2ras.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x16x2rs_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.h(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfp32x16x2rs_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x16x2rs_h: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulfp32x16x2rs.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x16x2rs_h_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.h.s2(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfp32x16x2rs_h_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x16x2rs_h_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.h.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulfp32x16x2rs.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x16x2rs_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.l(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfp32x16x2rs_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x16x2rs_l: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulfp32x16x2rs.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x16x2rs_l_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.l.s2(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulfp32x16x2rs_l_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x16x2rs_l_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.l.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulfp32x16x2rs.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x2ras.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x2ras(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulfp32x2ras(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x2ras: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x2ras(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulfp32x2ras aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfp32x2rs.ll +declare <2 x i32> @llvm.xtensa.ae.mulfp32x2rs(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulfp32x2rs(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfp32x2rs: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulfp32x2rs(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulfp32x2rs aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulfq32sp24s_h_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulfq32sp24s.h.s2(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulfq32sp24s_h_s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfq32sp24s_h_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulfq32sp24s.h.s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulfq32sp24s.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulfq32sp24s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulfq32sp24s.l.s2(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulfq32sp24s_l_s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulfq32sp24s_l_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulfq32sp24s.l.s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulfq32sp24s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulp24x2.ll +declare <2 x i32> @llvm.xtensa.ae.mulp24x2(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulp24x2(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulp24x2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulp24x2(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulp24x2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulp24x2_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulp24x2.s2(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulp24x2_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulp24x2_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulp24x2.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulp24x2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulp32x16x2_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulp32x16x2.h(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulp32x16x2_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulp32x16x2_h: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulp32x16x2.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulp32x16x2.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulp32x16x2_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulp32x16x2.l(<2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulp32x16x2_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulp32x16x2_l: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulp32x16x2.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulp32x16x2.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulp32x2.ll +declare <2 x i32> @llvm.xtensa.ae.mulp32x2(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulp32x2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulp32x2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulp32x2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulp32x2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulq32sp16s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulq32sp16s.l.s2(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulq32sp16s_l_s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulq32sp16s_l_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulq32sp16s.l.s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulq32sp16s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulq32sp16u_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulq32sp16u.l.s2(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulq32sp16u_l_s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulq32sp16u_l_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulq32sp16u.l.s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulq32sp16u.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulrfq32sp24s_h_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulrfq32sp24s.h.s2(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulrfq32sp24s_h_s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulrfq32sp24s_h_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulrfq32sp24s.h.s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulrfq32sp24s.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulrfq32sp24s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulrfq32sp24s.l.s2(<1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulrfq32sp24s_l_s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulrfq32sp24s_l_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulrfq32sp24s.l.s2(<1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulrfq32sp24s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls16x4.ll +declare { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.muls16x4(<2 x i32>, <2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_muls16x4(<2 x i32> %ae_mul_q1, <2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) { +; CHECK-LABEL: test_xtensa_ae_muls16x4: + + + + +%ret = call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.muls16x4(<2 x i32> %ae_mul_q1, <2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) +; CHECK: ae_muls16x4 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <2 x i32> } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_muls32_hh.ll +declare <1 x i64> @llvm.xtensa.ae.muls32.hh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32_hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32_hh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32.hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32_lh.ll +declare <1 x i64> @llvm.xtensa.ae.muls32.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32_lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32.lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32_ll.ll +declare <1 x i64> @llvm.xtensa.ae.muls32.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32f48p16s_hh.ll +declare <1 x i64> @llvm.xtensa.ae.muls32f48p16s.hh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32f48p16s_hh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32f48p16s_hh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.hh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32f48p16s.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32f48p16s_hh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32f48p16s.hh.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32f48p16s_hh_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32f48p16s_hh_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.hh.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_muls32f48p16s.hh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32f48p16s_lh.ll +declare <1 x i64> @llvm.xtensa.ae.muls32f48p16s.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32f48p16s_lh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32f48p16s_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.lh(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32f48p16s.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32f48p16s_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32f48p16s.lh.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32f48p16s_lh_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32f48p16s_lh_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.lh.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_muls32f48p16s.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32f48p16s_ll.ll +declare <1 x i64> @llvm.xtensa.ae.muls32f48p16s.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32f48p16s_ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32f48p16s_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.ll(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32f48p16s.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32f48p16s_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32f48p16s.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32f48p16s_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32f48p16s_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_muls32f48p16s.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32u_ll.ll +declare <1 x i64> @llvm.xtensa.ae.muls32u.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_muls32u_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32u_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32u.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32u.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_h0.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.h0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_h0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_h0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.h0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32x16.h0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_h0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.h0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_h0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_h0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.h0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_muls32x16.h0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_h1.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.h1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_h1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_h1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.h1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32x16.h1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_h1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.h1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_h1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_h1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.h1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_muls32x16.h1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_h2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.h2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_h2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_h2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.h2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32x16.h2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_h2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.h2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_h2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_h2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.h2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_muls32x16.h2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_h3.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.h3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_h3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_h3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.h3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32x16.h3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_h3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.h3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_h3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_h3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.h3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_muls32x16.h3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_l0.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32x16.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_muls32x16.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_l1.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.l1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_l1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32x16.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.l1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_l1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_l1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.l1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_muls32x16.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_l2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32x16.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_muls32x16.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_l3.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.l3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_l3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_muls32x16.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_muls32x16_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.muls32x16.l3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_muls32x16_l3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_muls32x16_l3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.muls32x16.l3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_muls32x16.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsad24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulsad24.hh.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsad24_hh_ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsad24_hh_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsad24.hh.ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulsad24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsad24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsad24.hh.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsad24_hh_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsad24_hh_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsad24.hh.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsad24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsad32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulsad32x16.h1.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsad32x16_h1_l0(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsad32x16_h1_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsad32x16.h1.l0(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsad32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsad32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsad32x16.h1.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsad32x16_h1_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsad32x16_h1_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsad32x16.h1.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsad32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsad32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsad32x16.h3.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsad32x16_h3_l2(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsad32x16_h3_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsad32x16.h3.l2(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsad32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsad32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsad32x16.h3.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsad32x16_h3_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsad32x16_h3_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsad32x16.h3.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsad32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsafd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulsafd24.hh.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsafd24_hh_ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsafd24_hh_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsafd24.hh.ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulsafd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsafd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsafd24.hh.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsafd24_hh_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsafd24_hh_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsafd24.hh.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsafd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsafd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h1.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsafd32x16_h1_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsafd32x16_h1_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h1.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsafd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsafd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h1.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsafd32x16_h1_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsafd32x16_h1_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h1.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsafd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsafd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h3.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsafd32x16_h3_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsafd32x16_h3_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h3.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsafd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsafd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h3.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsafd32x16_h3_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsafd32x16_h3_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h3.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsafd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf16ss_00.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.00(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_00(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_00: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.00(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf16ss.00 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_00_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.00.s2(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_00_s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_00_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.00.s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf16ss.00_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_10.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.10(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_10(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_10: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.10(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.10 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_11.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.11(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_11(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_11: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.11(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.11 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_20.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.20(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_20(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_20: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.20(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.20 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_21.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.21(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_21(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_21: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.21(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.21 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_22.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.22(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_22(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_22: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.22(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.22 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_30.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.30(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_30(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_30: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.30(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.30 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_31.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.31(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_31(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_31: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.31(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.31 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_32.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.32(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_32(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_32: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.32(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16ss_33.ll +declare <2 x i32> @llvm.xtensa.ae.mulsf16ss.33(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16ss_33(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf16ss_33: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsf16ss.33(<2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulsf16ss.33 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsf16x4ss.ll +declare { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulsf16x4ss(<2 x i32>, <2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsf16x4ss(<2 x i32> %ae_mul_q1, <2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) { +; CHECK-LABEL: test_xtensa_ae_mulsf16x4ss: + + + + +%ret = call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulsf16x4ss(<2 x i32> %ae_mul_q1, <2 x i32> %ae_mul_q0, <4 x i16> %ae_mul_d1, <4 x i16> %ae_mul_d0) +; CHECK: ae_mulsf16x4ss aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} +%ev = extractvalue { <2 x i32>, <2 x i32> } %ret, 0 +ret <2 x i32> %ev +} + + +;--- ae_mulsf32r_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32r.hh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf32r_hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32r_hh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32r.hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32r.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32r_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32r.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf32r_lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32r_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32r.lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32r.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32r_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32r.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf32r_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32r_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32r.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32r.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32r_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32r.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf32r_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32r_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32r.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsf32r.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32s_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32s.hh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf32s_hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32s_hh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32s.hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32s.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32s_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32s.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf32s_lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32s_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32s.lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32s.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32s_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32s.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf32s_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32s_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32s.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32s.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_h0.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.h0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_h0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_h0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32x16.h0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_h0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.h0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_h0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_h0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf32x16.h0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_h1.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.h1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_h1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_h1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32x16.h1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_h1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.h1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_h1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_h1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf32x16.h1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_h2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.h2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_h2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_h2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32x16.h2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_h2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.h2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_h2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_h2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf32x16.h2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_h3.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.h3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_h3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_h3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32x16.h3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_h3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.h3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_h3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_h3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf32x16.h3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32x16.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf32x16.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.l1(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_l1: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l1(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32x16.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.l1.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_l1_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_l1_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l1.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf32x16.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32x16.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf32x16.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.l3(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_l3: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l3(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf32x16.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf32x16_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf32x16.l3.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulsf32x16_l3_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf32x16_l3_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l3.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsf32x16.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf48q32sp16s_l.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16s.l(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf48q32sp16s_l(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf48q32sp16s_l: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16s.l(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf48q32sp16s.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf48q32sp16s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16s.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf48q32sp16s_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf48q32sp16s_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16s.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsf48q32sp16s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf48q32sp16u_l.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16u.l(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf48q32sp16u_l(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf48q32sp16u_l: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16u.l(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <1 x i64> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsf48q32sp16u.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsf48q32sp16u_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16u.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsf48q32sp16u_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsf48q32sp16u_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16u.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsf48q32sp16u.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsfp24x2r.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp24x2r(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsfp24x2r(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp24x2r: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp24x2r(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsfp24x2r aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp24x2r_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp24x2r.s2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsfp24x2r_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp24x2r_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp24x2r.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsfp24x2r_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp24x2ra.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp24x2ra(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsfp24x2ra(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp24x2ra: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp24x2ra(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsfp24x2ra aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp24x2ra_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp24x2ra.s2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsfp24x2ra_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp24x2ra_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp24x2ra.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsfp24x2ra_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x16x2ras_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.h(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsfp32x16x2ras_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x16x2ras_h: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsfp32x16x2ras.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x16x2ras_h_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.h.s2(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsfp32x16x2ras_h_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x16x2ras_h_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.h.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsfp32x16x2ras.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x16x2ras_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.l(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsfp32x16x2ras_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x16x2ras_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsfp32x16x2ras.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x16x2ras_l_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.l.s2(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsfp32x16x2ras_l_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x16x2ras_l_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.l.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsfp32x16x2ras.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x16x2rs_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.h(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsfp32x16x2rs_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x16x2rs_h: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsfp32x16x2rs.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x16x2rs_h_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.h.s2(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsfp32x16x2rs_h_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x16x2rs_h_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.h.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsfp32x16x2rs.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x16x2rs_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.l(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsfp32x16x2rs_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x16x2rs_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsfp32x16x2rs.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x16x2rs_l_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.l.s2(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsfp32x16x2rs_l_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x16x2rs_l_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.l.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulsfp32x16x2rs.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x2ras.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x2ras(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsfp32x2ras(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x2ras: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x2ras(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsfp32x2ras aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfp32x2rs.ll +declare <2 x i32> @llvm.xtensa.ae.mulsfp32x2rs(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsfp32x2rs(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfp32x2rs: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsfp32x2rs(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsfp32x2rs aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsfq32sp24s_h_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsfq32sp24s.h.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsfq32sp24s_h_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfq32sp24s_h_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsfq32sp24s.h.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsfq32sp24s.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsfq32sp24s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsfq32sp24s.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsfq32sp24s_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsfq32sp24s_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsfq32sp24s.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsfq32sp24s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsp24x2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsp24x2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsp24x2(<2 x i32> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsp24x2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsp24x2(<2 x i32> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulsp24x2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsp24x2_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsp24x2.s2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsp24x2_s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsp24x2_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsp24x2.s2(<2 x i32> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsp24x2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsp32x16x2_h.ll +declare <2 x i32> @llvm.xtensa.ae.mulsp32x16x2.h(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsp32x16x2_h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsp32x16x2_h: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsp32x16x2.h(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsp32x16x2.h aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsp32x16x2_l.ll +declare <2 x i32> @llvm.xtensa.ae.mulsp32x16x2.l(<2 x i32>, <2 x i32>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulsp32x16x2_l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsp32x16x2_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsp32x16x2.l(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsp32x16x2.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsp32x2.ll +declare <2 x i32> @llvm.xtensa.ae.mulsp32x2(<2 x i32>, <2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_mulsp32x2(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsp32x2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulsp32x2(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulsp32x2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulsq32sp16s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsq32sp16s.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsq32sp16s_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsq32sp16s_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsq32sp16s.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsq32sp16s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsq32sp16u_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsq32sp16u.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsq32sp16u_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsq32sp16u_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsq32sp16u.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsq32sp16u.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsrfq32sp24s_h_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsrfq32sp24s.h.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsrfq32sp24s_h_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsrfq32sp24s_h_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsrfq32sp24s.h.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsrfq32sp24s.h_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulsrfq32sp24s_l_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulsrfq32sp24s.l.s2(<1 x i64>, <1 x i64>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulsrfq32sp24s_l_s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulsrfq32sp24s_l_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulsrfq32sp24s.l.s2(<1 x i64> %ae_mul_S2_q0, <1 x i64> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulsrfq32sp24s.l_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulss32f48p16s_hh.ll +declare <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.hh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulss32f48p16s_hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulss32f48p16s_hh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.hh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulss32f48p16s.hh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulss32f48p16s_hh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.hh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulss32f48p16s_hh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulss32f48p16s_hh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.hh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulss32f48p16s.hh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulss32f48p16s_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulss32f48p16s_lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulss32f48p16s_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.lh(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulss32f48p16s.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulss32f48p16s_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.lh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulss32f48p16s_lh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulss32f48p16s_lh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.lh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulss32f48p16s.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulss32f48p16s_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulss32f48p16s_ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulss32f48p16s_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.ll(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulss32f48p16s.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulss32f48p16s_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulss32f48p16s_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulss32f48p16s_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulss32f48p16s.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulssd24.hh.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulssd24_hh_ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssd24_hh_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssd24.hh.ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulssd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssd24.hh.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulssd24_hh_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssd24_hh_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssd24.hh.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulssd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulssd24.hl.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulssd24_hl_lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssd24_hl_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssd24.hl.lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulssd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssd24.hl.lh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulssd24_hl_lh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssd24_hl_lh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssd24.hl.lh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulssd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulssd32x16.h1.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulssd32x16_h1_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssd32x16_h1_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssd32x16.h1.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulssd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssd32x16.h1.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulssd32x16_h1_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssd32x16_h1_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssd32x16.h1.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulssd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssd32x16.h3.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulssd32x16_h3_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssd32x16_h3_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssd32x16.h3.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulssd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssd32x16.h3.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulssd32x16_h3_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssd32x16_h3_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssd32x16.h3.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulssd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssfd16ss_11_00.ll +declare <2 x i32> @llvm.xtensa.ae.mulssfd16ss.11.00(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulssfd16ss_11_00(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd16ss_11_00: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.11.00(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulssfd16ss.11_00 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulssfd16ss_11_00_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulssfd16ss.11.00.s2(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulssfd16ss_11_00_s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd16ss_11_00_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.11.00.s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulssfd16ss.11_00_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulssfd16ss_13_02.ll +declare <2 x i32> @llvm.xtensa.ae.mulssfd16ss.13.02(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulssfd16ss_13_02(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd16ss_13_02: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.13.02(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulssfd16ss.13_02 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulssfd16ss_13_02_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulssfd16ss.13.02.s2(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulssfd16ss_13_02_s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd16ss_13_02_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.13.02.s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulssfd16ss.13_02_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulssfd16ss_33_22.ll +declare <2 x i32> @llvm.xtensa.ae.mulssfd16ss.33.22(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulssfd16ss_33_22(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd16ss_33_22: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.33.22(<2 x i32> %opnd_ae_sem_mul_x2_S1_q0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulssfd16ss.33_22 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulssfd16ss_33_22_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulssfd16ss.33.22.s2(<2 x i32>, <4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulssfd16ss_33_22_s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd16ss_33_22_s2: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.33.22.s2(<2 x i32> %ae_mul_S2_q0, <4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulssfd16ss.33_22_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulssfd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulssfd24.hh.ll(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulssfd24_hh_ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd24_hh_ll: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssfd24.hh.ll(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulssfd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssfd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssfd24.hh.ll.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulssfd24_hh_ll_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd24_hh_ll_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssfd24.hh.ll.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulssfd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssfd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulssfd24.hl.lh(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulssfd24_hl_lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd24_hl_lh: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssfd24.hl.lh(<1 x i64> %ae_mul_q0, <2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulssfd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssfd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssfd24.hl.lh.s2(<1 x i64>, <2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulssfd24_hl_lh_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd24_hl_lh_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssfd24.hl.lh.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulssfd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssfd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h1.l0(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulssfd32x16_h1_l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd32x16_h1_l0: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h1.l0(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulssfd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssfd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h1.l0.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulssfd32x16_h1_l0_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd32x16_h1_l0_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h1.l0.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulssfd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssfd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h3.l2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulssfd32x16_h3_l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd32x16_h3_l2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h3.l2(<1 x i64> %opnd_ae_sem_mul_x2_S1_q0, <2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulssfd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulssfd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h3.l2.s2(<1 x i64>, <2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulssfd32x16_h3_l2_s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulssfd32x16_h3_l2_s2: + + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h3.l2.s2(<1 x i64> %ae_mul_S2_q0, <2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulssfd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad24.hh.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzaad24_hh_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad24_hh_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad24.hh.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzaad24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad24.hh.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzaad24_hh_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad24_hh_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad24.hh.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzaad24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad24.hl.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzaad24_hl_lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad24_hl_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad24.hl.lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzaad24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad24.hl.lh.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzaad24_hl_lh_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad24_hl_lh_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad24.hl.lh.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzaad24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad32x16_h0_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h0.l1(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaad32x16_h0_l1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad32x16_h0_l1: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h0.l1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaad32x16.h0.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad32x16_h0_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h0.l1.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaad32x16_h0_l1_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad32x16_h0_l1_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h0.l1.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaad32x16.h0.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h1.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaad32x16_h1_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad32x16_h1_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h1.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaad32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h1.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaad32x16_h1_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad32x16_h1_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h1.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaad32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad32x16_h2_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h2.l3(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaad32x16_h2_l3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad32x16_h2_l3: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h2.l3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaad32x16.h2.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad32x16_h2_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h2.l3.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaad32x16_h2_l3_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad32x16_h2_l3_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h2.l3.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaad32x16.h2.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h3.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaad32x16_h3_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad32x16_h3_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h3.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaad32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaad32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h3.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaad32x16_h3_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaad32x16_h3_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h3.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaad32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd16ss_11_00.ll +declare <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.11.00(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzaafd16ss_11_00(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd16ss_11_00: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.11.00(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaafd16ss.11_00 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzaafd16ss_11_00_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.11.00.s2(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzaafd16ss_11_00_s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd16ss_11_00_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.11.00.s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd16ss.11_00_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzaafd16ss_13_02.ll +declare <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.13.02(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzaafd16ss_13_02(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd16ss_13_02: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.13.02(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaafd16ss.13_02 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzaafd16ss_13_02_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.13.02.s2(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzaafd16ss_13_02_s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd16ss_13_02_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.13.02.s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd16ss.13_02_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzaafd16ss_33_22.ll +declare <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.33.22(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzaafd16ss_33_22(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd16ss_33_22: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.33.22(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaafd16ss.33_22 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzaafd16ss_33_22_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.33.22.s2(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzaafd16ss_33_22_s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd16ss_33_22_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.33.22.s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd16ss.33_22_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzaafd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd24.hh.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzaafd24_hh_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd24_hh_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd24.hh.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzaafd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd24.hh.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzaafd24_hh_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd24_hh_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd24.hh.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd24.hl.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzaafd24_hl_lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd24_hl_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd24.hl.lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzaafd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd24.hl.lh.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzaafd24_hl_lh_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd24_hl_lh_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd24.hl.lh.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd32x16_h0_l1.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h0.l1(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaafd32x16_h0_l1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd32x16_h0_l1: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h0.l1(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaafd32x16.h0.l1 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd32x16_h0_l1_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h0.l1.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaafd32x16_h0_l1_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd32x16_h0_l1_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h0.l1.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd32x16.h0.l1_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h1.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaafd32x16_h1_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd32x16_h1_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h1.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaafd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h1.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaafd32x16_h1_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd32x16_h1_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h1.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd32x16_h2_l3.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h2.l3(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaafd32x16_h2_l3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd32x16_h2_l3: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h2.l3(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaafd32x16.h2.l3 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd32x16_h2_l3_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h2.l3.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaafd32x16_h2_l3_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd32x16_h2_l3_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h2.l3.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd32x16.h2.l3_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h3.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaafd32x16_h3_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd32x16_h3_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h3.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzaafd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzaafd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h3.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzaafd32x16_h3_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzaafd32x16_h3_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h3.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzaafd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasd24.hh.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzasd24_hh_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasd24_hh_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasd24.hh.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzasd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasd24.hh.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzasd24_hh_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasd24_hh_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasd24.hh.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzasd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasd24.hl.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzasd24_hl_lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasd24_hl_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasd24.hl.lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzasd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasd24.hl.lh.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzasd24_hl_lh_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasd24_hl_lh_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasd24.hl.lh.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzasd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h1.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzasd32x16_h1_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasd32x16_h1_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h1.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzasd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h1.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzasd32x16_h1_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasd32x16_h1_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h1.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzasd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h3.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzasd32x16_h3_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasd32x16_h3_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h3.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzasd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h3.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzasd32x16_h3_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasd32x16_h3_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h3.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzasd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasfd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasfd24.hh.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzasfd24_hh_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasfd24_hh_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasfd24.hh.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzasfd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasfd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasfd24.hh.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzasfd24_hh_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasfd24_hh_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasfd24.hh.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzasfd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasfd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasfd24.hl.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzasfd24_hl_lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasfd24_hl_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasfd24.hl.lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzasfd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasfd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasfd24.hl.lh.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzasfd24_hl_lh_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasfd24_hl_lh_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasfd24.hl.lh.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzasfd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasfd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h1.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzasfd32x16_h1_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasfd32x16_h1_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h1.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzasfd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasfd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h1.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzasfd32x16_h1_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasfd32x16_h1_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h1.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzasfd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasfd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h3.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzasfd32x16_h3_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasfd32x16_h3_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h3.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzasfd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzasfd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h3.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzasfd32x16_h3_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzasfd32x16_h3_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h3.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzasfd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsad24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsad24.hh.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzsad24_hh_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsad24_hh_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsad24.hh.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzsad24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsad24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsad24.hh.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzsad24_hh_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsad24_hh_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsad24.hh.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzsad24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsad32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h1.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzsad32x16_h1_l0(<2 x i32> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsad32x16_h1_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h1.l0(<2 x i32> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulzsad32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsad32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h1.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzsad32x16_h1_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsad32x16_h1_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h1.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzsad32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsad32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h3.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzsad32x16_h3_l2(<2 x i32> %ae_mul_d0, <4 x i16> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsad32x16_h3_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h3.l2(<2 x i32> %ae_mul_d0, <4 x i16> %ae_mul_d1) +; CHECK: ae_mulzsad32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsad32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h3.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzsad32x16_h3_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsad32x16_h3_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h3.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzsad32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsafd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsafd24.hh.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzsafd24_hh_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsafd24_hh_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsafd24.hh.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzsafd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsafd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsafd24.hh.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzsafd24_hh_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsafd24_hh_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsafd24.hh.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzsafd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsafd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h1.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzsafd32x16_h1_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsafd32x16_h1_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h1.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzsafd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsafd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h1.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzsafd32x16_h1_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsafd32x16_h1_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h1.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzsafd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsafd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h3.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzsafd32x16_h3_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsafd32x16_h3_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h3.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzsafd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzsafd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h3.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzsafd32x16_h3_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzsafd32x16_h3_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h3.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzsafd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssd24.hh.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzssd24_hh_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssd24_hh_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssd24.hh.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzssd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssd24.hh.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzssd24_hh_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssd24_hh_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssd24.hh.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzssd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssd24.hl.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzssd24_hl_lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssd24_hl_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssd24.hl.lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzssd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssd24.hl.lh.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzssd24_hl_lh_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssd24_hl_lh_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssd24.hl.lh.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzssd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h1.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzssd32x16_h1_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssd32x16_h1_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h1.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzssd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h1.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzssd32x16_h1_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssd32x16_h1_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h1.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzssd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h3.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzssd32x16_h3_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssd32x16_h3_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h3.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzssd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h3.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzssd32x16_h3_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssd32x16_h3_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h3.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzssd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssfd16ss_11_00.ll +declare <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.11.00(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzssfd16ss_11_00(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd16ss_11_00: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.11.00(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzssfd16ss.11_00 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzssfd16ss_11_00_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.11.00.s2(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzssfd16ss_11_00_s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd16ss_11_00_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.11.00.s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzssfd16ss.11_00_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzssfd16ss_13_02.ll +declare <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.13.02(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzssfd16ss_13_02(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd16ss_13_02: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.13.02(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzssfd16ss.13_02 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzssfd16ss_13_02_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.13.02.s2(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzssfd16ss_13_02_s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd16ss_13_02_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.13.02.s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzssfd16ss.13_02_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzssfd16ss_33_22.ll +declare <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.33.22(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzssfd16ss_33_22(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd16ss_33_22: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.33.22(<4 x i16> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzssfd16ss.33_22 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzssfd16ss_33_22_s2.ll +declare <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.33.22.s2(<4 x i16>, <4 x i16>) +define <2 x i32> @test_xtensa_ae_mulzssfd16ss_33_22_s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd16ss_33_22_s2: + + +%ret = call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.33.22.s2(<4 x i16> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzssfd16ss.33_22_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_mulzssfd24_hh_ll.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssfd24.hh.ll(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzssfd24_hh_ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd24_hh_ll: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssfd24.hh.ll(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzssfd24.hh.ll aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssfd24_hh_ll_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssfd24.hh.ll.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzssfd24_hh_ll_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd24_hh_ll_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssfd24.hh.ll.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzssfd24.hh.ll_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssfd24_hl_lh.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssfd24.hl.lh(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzssfd24_hl_lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd24_hl_lh: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssfd24.hl.lh(<2 x i32> %ae_mul_d0, <2 x i32> %ae_mul_d1) +; CHECK: ae_mulzssfd24.hl.lh aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssfd24_hl_lh_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssfd24.hl.lh.s2(<2 x i32>, <2 x i32>) +define <1 x i64> @test_xtensa_ae_mulzssfd24_hl_lh_s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd24_hl_lh_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssfd24.hl.lh.s2(<2 x i32> %ae_mul_S2_d0, <2 x i32> %ae_mul_S2_d1) +; CHECK: ae_mulzssfd24.hl.lh_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssfd32x16_h1_l0.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h1.l0(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzssfd32x16_h1_l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd32x16_h1_l0: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h1.l0(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzssfd32x16.h1.l0 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssfd32x16_h1_l0_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h1.l0.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzssfd32x16_h1_l0_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd32x16_h1_l0_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h1.l0.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzssfd32x16.h1.l0_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssfd32x16_h3_l2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h3.l2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzssfd32x16_h3_l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd32x16_h3_l2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h3.l2(<2 x i32> %opnd_ae_sem_mul_x2_S1_d0, <4 x i16> %opnd_ae_sem_mul_x2_S1_d1) +; CHECK: ae_mulzssfd32x16.h3.l2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_mulzssfd32x16_h3_l2_s2.ll +declare <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h3.l2.s2(<2 x i32>, <4 x i16>) +define <1 x i64> @test_xtensa_ae_mulzssfd32x16_h3_l2_s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) { +; CHECK-LABEL: test_xtensa_ae_mulzssfd32x16_h3_l2_s2: + + +%ret = call <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h3.l2.s2(<2 x i32> %ae_mul_S2_d0, <4 x i16> %ae_mul_S2_d1) +; CHECK: ae_mulzssfd32x16.h3.l2_s2 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_nand.ll +declare <1 x i64> @llvm.xtensa.ae.nand(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_nand(<1 x i64> %ae_dr_to_dr_v0, <1 x i64> %ae_dr_to_dr_v1) { +; CHECK-LABEL: test_xtensa_ae_nand: + + +%ret = call <1 x i64> @llvm.xtensa.ae.nand(<1 x i64> %ae_dr_to_dr_v0, <1 x i64> %ae_dr_to_dr_v1) +; CHECK: ae_nand aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_neg16s.ll +declare <4 x i16> @llvm.xtensa.ae.neg16s(<4 x i16>) +define <4 x i16> @test_xtensa_ae_neg16s(<4 x i16> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_neg16s: + +%ret = call <4 x i16> @llvm.xtensa.ae.neg16s(<4 x i16> %ae_arth_v1) +; CHECK: ae_neg16s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_neg24s.ll +declare <2 x i32> @llvm.xtensa.ae.neg24s(<2 x i32>) +define <2 x i32> @test_xtensa_ae_neg24s(<2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_neg24s: + +%ret = call <2 x i32> @llvm.xtensa.ae.neg24s(<2 x i32> %ae_arth_v1) +; CHECK: ae_neg24s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_neg32.ll +declare <2 x i32> @llvm.xtensa.ae.neg32(<2 x i32>) +define <2 x i32> @test_xtensa_ae_neg32(<2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_neg32: + +%ret = call <2 x i32> @llvm.xtensa.ae.neg32(<2 x i32> %ae_arth_v1) +; CHECK: ae_neg32 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_neg32s.ll +declare <2 x i32> @llvm.xtensa.ae.neg32s(<2 x i32>) +define <2 x i32> @test_xtensa_ae_neg32s(<2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_neg32s: + +%ret = call <2 x i32> @llvm.xtensa.ae.neg32s(<2 x i32> %ae_arth_v1) +; CHECK: ae_neg32s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_neg64.ll +declare <1 x i64> @llvm.xtensa.ae.neg64(<1 x i64>) +define <1 x i64> @test_xtensa_ae_neg64(<1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_neg64: + +%ret = call <1 x i64> @llvm.xtensa.ae.neg64(<1 x i64> %ae_arth_v1) +; CHECK: ae_neg64 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_neg64s.ll +declare <1 x i64> @llvm.xtensa.ae.neg64s(<1 x i64>) +define <1 x i64> @test_xtensa_ae_neg64s(<1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_neg64s: + +%ret = call <1 x i64> @llvm.xtensa.ae.neg64s(<1 x i64> %ae_arth_v1) +; CHECK: ae_neg64s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_nsa64.ll +declare i32 @llvm.xtensa.ae.nsa64(<1 x i64>) +define i32 @test_xtensa_ae_nsa64(<1 x i64> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_nsa64: + +%ret = call i32 @llvm.xtensa.ae.nsa64(<1 x i64> %ae_dr_to_ar_v0) +; CHECK: ae_nsa64 a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_nsaz16_0.ll +declare i32 @llvm.xtensa.ae.nsaz16.0(<4 x i16>) +define i32 @test_xtensa_ae_nsaz16_0(<4 x i16> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_nsaz16_0: + +%ret = call i32 @llvm.xtensa.ae.nsaz16.0(<4 x i16> %ae_dr_to_ar_v0) +; CHECK: ae_nsaz16.0 a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_nsaz32_l.ll +declare i32 @llvm.xtensa.ae.nsaz32.l(<2 x i32>) +define i32 @test_xtensa_ae_nsaz32_l(<2 x i32> %ae_dr_to_ar_v0) { +; CHECK-LABEL: test_xtensa_ae_nsaz32_l: + +%ret = call i32 @llvm.xtensa.ae.nsaz32.l(<2 x i32> %ae_dr_to_ar_v0) +; CHECK: ae_nsaz32.l a{{[0-9]+}}, aed{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_or.ll +declare <1 x i64> @llvm.xtensa.ae.or(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_or(<1 x i64> %ae_dr_to_dr_v0, <1 x i64> %ae_dr_to_dr_v1) { +; CHECK-LABEL: test_xtensa_ae_or: + + +%ret = call <1 x i64> @llvm.xtensa.ae.or(<1 x i64> %ae_dr_to_dr_v0, <1 x i64> %ae_dr_to_dr_v1) +; CHECK: ae_or aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_pksr24.ll +declare <2 x i32> @llvm.xtensa.ae.pksr24(<2 x i32>, <1 x i64>, i32) +define <2 x i32> @test_xtensa_ae_pksr24(<2 x i32> %ae_pks_d, <1 x i64> %ae_pks_s) { +; CHECK-LABEL: test_xtensa_ae_pksr24: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.pksr24(<2 x i32> %ae_pks_d, <1 x i64> %ae_pks_s, i32 0) +; CHECK: ae_pksr24 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_pksr32.ll +declare <2 x i32> @llvm.xtensa.ae.pksr32(<2 x i32>, <1 x i64>, i32) +define <2 x i32> @test_xtensa_ae_pksr32(<2 x i32> %ae_pks_d, <1 x i64> %ae_pks_s) { +; CHECK-LABEL: test_xtensa_ae_pksr32: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.pksr32(<2 x i32> %ae_pks_d, <1 x i64> %ae_pks_s, i32 0) +; CHECK: ae_pksr32 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_round16x4f32sasym.ll +declare <4 x i16> @llvm.xtensa.ae.round16x4f32sasym(<2 x i32>, <2 x i32>) +define <4 x i16> @test_xtensa_ae_round16x4f32sasym(<2 x i32> %ae_arth_v1, <2 x i32> %ae_arth_v0) { +; CHECK-LABEL: test_xtensa_ae_round16x4f32sasym: + + +%ret = call <4 x i16> @llvm.xtensa.ae.round16x4f32sasym(<2 x i32> %ae_arth_v1, <2 x i32> %ae_arth_v0) +; CHECK: ae_round16x4f32sasym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_round16x4f32ssym.ll +declare <4 x i16> @llvm.xtensa.ae.round16x4f32ssym(<2 x i32>, <2 x i32>) +define <4 x i16> @test_xtensa_ae_round16x4f32ssym(<2 x i32> %ae_arth_v1, <2 x i32> %ae_arth_v0) { +; CHECK-LABEL: test_xtensa_ae_round16x4f32ssym: + + +%ret = call <4 x i16> @llvm.xtensa.ae.round16x4f32ssym(<2 x i32> %ae_arth_v1, <2 x i32> %ae_arth_v0) +; CHECK: ae_round16x4f32ssym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_round24x2f48sasym.ll +declare <2 x i32> @llvm.xtensa.ae.round24x2f48sasym(<1 x i64>, <1 x i64>) +define <2 x i32> @test_xtensa_ae_round24x2f48sasym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_round24x2f48sasym: + + +%ret = call <2 x i32> @llvm.xtensa.ae.round24x2f48sasym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_round24x2f48sasym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_round24x2f48ssym.ll +declare <2 x i32> @llvm.xtensa.ae.round24x2f48ssym(<1 x i64>, <1 x i64>) +define <2 x i32> @test_xtensa_ae_round24x2f48ssym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_round24x2f48ssym: + + +%ret = call <2 x i32> @llvm.xtensa.ae.round24x2f48ssym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_round24x2f48ssym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_round32x2f48sasym.ll +declare <2 x i32> @llvm.xtensa.ae.round32x2f48sasym(<1 x i64>, <1 x i64>) +define <2 x i32> @test_xtensa_ae_round32x2f48sasym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_round32x2f48sasym: + + +%ret = call <2 x i32> @llvm.xtensa.ae.round32x2f48sasym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_round32x2f48sasym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_round32x2f48ssym.ll +declare <2 x i32> @llvm.xtensa.ae.round32x2f48ssym(<1 x i64>, <1 x i64>) +define <2 x i32> @test_xtensa_ae_round32x2f48ssym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_round32x2f48ssym: + + +%ret = call <2 x i32> @llvm.xtensa.ae.round32x2f48ssym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_round32x2f48ssym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_round32x2f64sasym.ll +declare <2 x i32> @llvm.xtensa.ae.round32x2f64sasym(<1 x i64>, <1 x i64>) +define <2 x i32> @test_xtensa_ae_round32x2f64sasym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_round32x2f64sasym: + + +%ret = call <2 x i32> @llvm.xtensa.ae.round32x2f64sasym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_round32x2f64sasym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_round32x2f64ssym.ll +declare <2 x i32> @llvm.xtensa.ae.round32x2f64ssym(<1 x i64>, <1 x i64>) +define <2 x i32> @test_xtensa_ae_round32x2f64ssym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_round32x2f64ssym: + + +%ret = call <2 x i32> @llvm.xtensa.ae.round32x2f64ssym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_round32x2f64ssym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_roundsp16f24asym.ll +declare <2 x i32> @llvm.xtensa.ae.roundsp16f24asym(<2 x i32>) +define <2 x i32> @test_xtensa_ae_roundsp16f24asym(<2 x i32> %ae_arth_v0) { +; CHECK-LABEL: test_xtensa_ae_roundsp16f24asym: + +%ret = call <2 x i32> @llvm.xtensa.ae.roundsp16f24asym(<2 x i32> %ae_arth_v0) +; CHECK: ae_roundsp16f24asym aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_roundsp16f24sym.ll +declare <2 x i32> @llvm.xtensa.ae.roundsp16f24sym(<2 x i32>) +define <2 x i32> @test_xtensa_ae_roundsp16f24sym(<2 x i32> %ae_arth_v0) { +; CHECK-LABEL: test_xtensa_ae_roundsp16f24sym: + +%ret = call <2 x i32> @llvm.xtensa.ae.roundsp16f24sym(<2 x i32> %ae_arth_v0) +; CHECK: ae_roundsp16f24sym aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_roundsp16q48x2asym.ll +declare <2 x i32> @llvm.xtensa.ae.roundsp16q48x2asym(<1 x i64>, <1 x i64>) +define <2 x i32> @test_xtensa_ae_roundsp16q48x2asym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_roundsp16q48x2asym: + + +%ret = call <2 x i32> @llvm.xtensa.ae.roundsp16q48x2asym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_roundsp16q48x2asym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_roundsp16q48x2sym.ll +declare <2 x i32> @llvm.xtensa.ae.roundsp16q48x2sym(<1 x i64>, <1 x i64>) +define <2 x i32> @test_xtensa_ae_roundsp16q48x2sym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_roundsp16q48x2sym: + + +%ret = call <2 x i32> @llvm.xtensa.ae.roundsp16q48x2sym(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_roundsp16q48x2sym aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_roundsq32f48asym.ll +declare <1 x i64> @llvm.xtensa.ae.roundsq32f48asym(<1 x i64>) +define <1 x i64> @test_xtensa_ae_roundsq32f48asym(<1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_roundsq32f48asym: + +%ret = call <1 x i64> @llvm.xtensa.ae.roundsq32f48asym(<1 x i64> %ae_arth_v1) +; CHECK: ae_roundsq32f48asym aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_roundsq32f48sym.ll +declare <1 x i64> @llvm.xtensa.ae.roundsq32f48sym(<1 x i64>) +define <1 x i64> @test_xtensa_ae_roundsq32f48sym(<1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_roundsq32f48sym: + +%ret = call <1 x i64> @llvm.xtensa.ae.roundsq32f48sym(<1 x i64> %ae_arth_v1) +; CHECK: ae_roundsq32f48sym aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_s16_0_i.ll +declare void @llvm.xtensa.ae.s16.0.i(<4 x i16>, ptr, i32) +define void @test_xtensa_ae_s16_0_i(<4 x i16> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16_0_i: + + + + call void @llvm.xtensa.ae.s16.0.i(<4 x i16> %ae_ls_v, ptr %ars, i32 -16) +; CHECK: ae_s16.0.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s16_0_ip.ll +declare ptr @llvm.xtensa.ae.s16.0.ip(<4 x i16>, ptr, i32) +define ptr @test_xtensa_ae_s16_0_ip(<4 x i16> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16_0_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s16.0.ip(<4 x i16> %ae_ls_v, ptr %ars, i32 -16) +; CHECK: ae_s16.0.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16_0_x.ll +declare void @llvm.xtensa.ae.s16.0.x(<4 x i16>, ptr, i32) +define void @test_xtensa_ae_s16_0_x(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16_0_x: + + + + call void @llvm.xtensa.ae.s16.0.x(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16.0.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s16_0_xc.ll +declare ptr @llvm.xtensa.ae.s16.0.xc(<4 x i16>, ptr, i32) +define ptr @test_xtensa_ae_s16_0_xc(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16_0_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s16.0.xc(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16.0.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16_0_xp.ll +declare ptr @llvm.xtensa.ae.s16.0.xp(<4 x i16>, ptr, i32) +define ptr @test_xtensa_ae_s16_0_xp(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16_0_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s16.0.xp(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16.0.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16m_l_i.ll +declare void @llvm.xtensa.ae.s16m.l.i(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s16m_l_i(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16m_l_i: + + + + call void @llvm.xtensa.ae.s16m.l.i(<2 x i32> %ae_ls_v, ptr %ars, i32 -16) +; CHECK: ae_s16m.l.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s16m_l_iu.ll +declare ptr @llvm.xtensa.ae.s16m.l.iu(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s16m_l_iu(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16m_l_iu: + + + +%ret = call ptr @llvm.xtensa.ae.s16m.l.iu(<2 x i32> %ae_ls_v, ptr %ars, i32 -16) +; CHECK: ae_s16m.l.iu aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16m_l_x.ll +declare void @llvm.xtensa.ae.s16m.l.x(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s16m_l_x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16m_l_x: + + + + call void @llvm.xtensa.ae.s16m.l.x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16m.l.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s16m_l_xc.ll +declare ptr @llvm.xtensa.ae.s16m.l.xc(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s16m_l_xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16m_l_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s16m.l.xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16m.l.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16m_l_xu.ll +declare ptr @llvm.xtensa.ae.s16m.l.xu(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s16m_l_xu(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16m_l_xu: + + + +%ret = call ptr @llvm.xtensa.ae.s16m.l.xu(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16m.l.xu aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16x2m_i.ll +declare void @llvm.xtensa.ae.s16x2m.i(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s16x2m_i(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16x2m_i: + + + + call void @llvm.xtensa.ae.s16x2m.i(<2 x i32> %ae_ls_v, ptr %ars, i32 -32) +; CHECK: ae_s16x2m.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s16x2m_iu.ll +declare ptr @llvm.xtensa.ae.s16x2m.iu(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s16x2m_iu(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16x2m_iu: + + + +%ret = call ptr @llvm.xtensa.ae.s16x2m.iu(<2 x i32> %ae_ls_v, ptr %ars, i32 -32) +; CHECK: ae_s16x2m.iu aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16x2m_x.ll +declare void @llvm.xtensa.ae.s16x2m.x(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s16x2m_x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16x2m_x: + + + + call void @llvm.xtensa.ae.s16x2m.x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16x2m.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s16x2m_xc.ll +declare ptr @llvm.xtensa.ae.s16x2m.xc(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s16x2m_xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16x2m_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s16x2m.xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16x2m.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16x2m_xu.ll +declare ptr @llvm.xtensa.ae.s16x2m.xu(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s16x2m_xu(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16x2m_xu: + + + +%ret = call ptr @llvm.xtensa.ae.s16x2m.xu(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16x2m.xu aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16x4_i.ll +declare void @llvm.xtensa.ae.s16x4.i(<4 x i16>, ptr, i32) +define void @test_xtensa_ae_s16x4_i(<4 x i16> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16x4_i: + + + + call void @llvm.xtensa.ae.s16x4.i(<4 x i16> %ae_ls_v, ptr %ars, i32 -64) +; CHECK: ae_s16x4.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s16x4_ip.ll +declare ptr @llvm.xtensa.ae.s16x4.ip(<4 x i16>, ptr, i32) +define ptr @test_xtensa_ae_s16x4_ip(<4 x i16> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16x4_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s16x4.ip(<4 x i16> %ae_ls_v, ptr %ars, i32 0) +; CHECK: ae_s16x4.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16x4_ric.ll +declare ptr @llvm.xtensa.ae.s16x4.ric(<4 x i16>, ptr) +define ptr @test_xtensa_ae_s16x4_ric(<4 x i16> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16x4_ric: + + +%ret = call ptr @llvm.xtensa.ae.s16x4.ric(<4 x i16> %ae_ls_v, ptr %ars) +; CHECK: ae_s16x4.ric aed{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16x4_rip.ll +declare ptr @llvm.xtensa.ae.s16x4.rip(<4 x i16>, ptr) +define ptr @test_xtensa_ae_s16x4_rip(<4 x i16> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s16x4_rip: + + +%ret = call ptr @llvm.xtensa.ae.s16x4.rip(<4 x i16> %ae_ls_v, ptr %ars) +; CHECK: ae_s16x4.rip aed{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16x4_x.ll +declare void @llvm.xtensa.ae.s16x4.x(<4 x i16>, ptr, i32) +define void @test_xtensa_ae_s16x4_x(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16x4_x: + + + + call void @llvm.xtensa.ae.s16x4.x(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16x4.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s16x4_xc.ll +declare ptr @llvm.xtensa.ae.s16x4.xc(<4 x i16>, ptr, i32) +define ptr @test_xtensa_ae_s16x4_xc(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16x4_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s16x4.xc(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16x4.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s16x4_xp.ll +declare ptr @llvm.xtensa.ae.s16x4.xp(<4 x i16>, ptr, i32) +define ptr @test_xtensa_ae_s16x4_xp(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s16x4_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s16x4.xp(<4 x i16> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s16x4.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s24ra64s_i.ll +declare void @llvm.xtensa.ae.s24ra64s.i(<1 x i64>, ptr, i32) +define void @test_xtensa_ae_s24ra64s_i(<1 x i64> %ae_ls_v1, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s24ra64s_i: + + + + call void @llvm.xtensa.ae.s24ra64s.i(<1 x i64> %ae_ls_v1, ptr %ars, i32 -32) +; CHECK: ae_s24ra64s.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s24ra64s_ip.ll +declare ptr @llvm.xtensa.ae.s24ra64s.ip(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s24ra64s_ip(<1 x i64> %ae_ls_v1, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s24ra64s_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s24ra64s.ip(<1 x i64> %ae_ls_v1, ptr %ars, i32 -32) +; CHECK: ae_s24ra64s.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s24ra64s_x.ll +declare void @llvm.xtensa.ae.s24ra64s.x(<1 x i64>, ptr, i32) +define void @test_xtensa_ae_s24ra64s_x(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s24ra64s_x: + + + + call void @llvm.xtensa.ae.s24ra64s.x(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) +; CHECK: ae_s24ra64s.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s24ra64s_xc.ll +declare ptr @llvm.xtensa.ae.s24ra64s.xc(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s24ra64s_xc(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s24ra64s_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s24ra64s.xc(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) +; CHECK: ae_s24ra64s.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s24ra64s_xp.ll +declare ptr @llvm.xtensa.ae.s24ra64s.xp(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s24ra64s_xp(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s24ra64s_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s24ra64s.xp(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) +; CHECK: ae_s24ra64s.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s24x2ra64s_ip.ll +declare ptr @llvm.xtensa.ae.s24x2ra64s.ip(<1 x i64>, <1 x i64>, ptr) +define ptr @test_xtensa_ae_s24x2ra64s_ip(<1 x i64> %ae_ls_v2, <1 x i64> %ae_ls_v1, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s24x2ra64s_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s24x2ra64s.ip(<1 x i64> %ae_ls_v2, <1 x i64> %ae_ls_v1, ptr %ars) +; CHECK: ae_s24x2ra64s.ip aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32_l_i.ll +declare void @llvm.xtensa.ae.s32.l.i(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s32_l_i(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32_l_i: + + + + call void @llvm.xtensa.ae.s32.l.i(<2 x i32> %ae_ls_v, ptr %ars, i32 -32) +; CHECK: ae_s32.l.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s32_l_ip.ll +declare ptr @llvm.xtensa.ae.s32.l.ip(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32_l_ip(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32_l_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s32.l.ip(<2 x i32> %ae_ls_v, ptr %ars, i32 -32) +; CHECK: ae_s32.l.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32_l_x.ll +declare void @llvm.xtensa.ae.s32.l.x(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s32_l_x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32_l_x: + + + + call void @llvm.xtensa.ae.s32.l.x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32.l.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s32_l_xc.ll +declare ptr @llvm.xtensa.ae.s32.l.xc(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32_l_xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32_l_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s32.l.xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32.l.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32_l_xp.ll +declare ptr @llvm.xtensa.ae.s32.l.xp(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32_l_xp(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32_l_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s32.l.xp(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32.l.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32f24_l_i.ll +declare void @llvm.xtensa.ae.s32f24.l.i(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s32f24_l_i(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32f24_l_i: + + + + call void @llvm.xtensa.ae.s32f24.l.i(<2 x i32> %ae_ls_v, ptr %ars, i32 -32) +; CHECK: ae_s32f24.l.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s32f24_l_ip.ll +declare ptr @llvm.xtensa.ae.s32f24.l.ip(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32f24_l_ip(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32f24_l_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s32f24.l.ip(<2 x i32> %ae_ls_v, ptr %ars, i32 -32) +; CHECK: ae_s32f24.l.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32f24_l_x.ll +declare void @llvm.xtensa.ae.s32f24.l.x(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s32f24_l_x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32f24_l_x: + + + + call void @llvm.xtensa.ae.s32f24.l.x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32f24.l.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s32f24_l_xc.ll +declare ptr @llvm.xtensa.ae.s32f24.l.xc(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32f24_l_xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32f24_l_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s32f24.l.xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32f24.l.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32f24_l_xp.ll +declare ptr @llvm.xtensa.ae.s32f24.l.xp(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32f24_l_xp(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32f24_l_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s32f24.l.xp(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32f24.l.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32m_i.ll +declare void @llvm.xtensa.ae.s32m.i(<1 x i64>, ptr, i32) +define void @test_xtensa_ae_s32m_i(<1 x i64> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32m_i: + + + + call void @llvm.xtensa.ae.s32m.i(<1 x i64> %ae_ls_v, ptr %ars, i32 -32) +; CHECK: ae_s32m.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s32m_iu.ll +declare ptr @llvm.xtensa.ae.s32m.iu(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s32m_iu(<1 x i64> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32m_iu: + + + +%ret = call ptr @llvm.xtensa.ae.s32m.iu(<1 x i64> %ae_ls_v, ptr %ars, i32 -32) +; CHECK: ae_s32m.iu aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32m_x.ll +declare void @llvm.xtensa.ae.s32m.x(<1 x i64>, ptr, i32) +define void @test_xtensa_ae_s32m_x(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32m_x: + + + + call void @llvm.xtensa.ae.s32m.x(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32m.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s32m_xc.ll +declare ptr @llvm.xtensa.ae.s32m.xc(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s32m_xc(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32m_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s32m.xc(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32m.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32m_xu.ll +declare ptr @llvm.xtensa.ae.s32m.xu(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s32m_xu(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32m_xu: + + + +%ret = call ptr @llvm.xtensa.ae.s32m.xu(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32m.xu aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32ra64s_i.ll +declare void @llvm.xtensa.ae.s32ra64s.i(<1 x i64>, ptr, i32) +define void @test_xtensa_ae_s32ra64s_i(<1 x i64> %ae_ls_v1, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32ra64s_i: + + + + call void @llvm.xtensa.ae.s32ra64s.i(<1 x i64> %ae_ls_v1, ptr %ars, i32 -32) +; CHECK: ae_s32ra64s.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s32ra64s_ip.ll +declare ptr @llvm.xtensa.ae.s32ra64s.ip(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s32ra64s_ip(<1 x i64> %ae_ls_v1, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32ra64s_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s32ra64s.ip(<1 x i64> %ae_ls_v1, ptr %ars, i32 -32) +; CHECK: ae_s32ra64s.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32ra64s_x.ll +declare void @llvm.xtensa.ae.s32ra64s.x(<1 x i64>, ptr, i32) +define void @test_xtensa_ae_s32ra64s_x(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32ra64s_x: + + + + call void @llvm.xtensa.ae.s32ra64s.x(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) +; CHECK: ae_s32ra64s.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s32ra64s_xc.ll +declare ptr @llvm.xtensa.ae.s32ra64s.xc(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s32ra64s_xc(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32ra64s_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s32ra64s.xc(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) +; CHECK: ae_s32ra64s.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32ra64s_xp.ll +declare ptr @llvm.xtensa.ae.s32ra64s.xp(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s32ra64s_xp(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32ra64s_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s32ra64s.xp(<1 x i64> %ae_ls_v1, ptr %ars, i32 %art) +; CHECK: ae_s32ra64s.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2_i.ll +declare void @llvm.xtensa.ae.s32x2.i(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s32x2_i(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2_i: + + + + call void @llvm.xtensa.ae.s32x2.i(<2 x i32> %ae_ls_v, ptr %ars, i32 -64) +; CHECK: ae_s32x2.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s32x2_ip.ll +declare ptr @llvm.xtensa.ae.s32x2.ip(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32x2_ip(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s32x2.ip(<2 x i32> %ae_ls_v, ptr %ars, i32 0) +; CHECK: ae_s32x2.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2_ric.ll +declare ptr @llvm.xtensa.ae.s32x2.ric(<2 x i32>, ptr) +define ptr @test_xtensa_ae_s32x2_ric(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2_ric: + + +%ret = call ptr @llvm.xtensa.ae.s32x2.ric(<2 x i32> %ae_ls_v, ptr %ars) +; CHECK: ae_s32x2.ric aed{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2_rip.ll +declare ptr @llvm.xtensa.ae.s32x2.rip(<2 x i32>, ptr) +define ptr @test_xtensa_ae_s32x2_rip(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2_rip: + + +%ret = call ptr @llvm.xtensa.ae.s32x2.rip(<2 x i32> %ae_ls_v, ptr %ars) +; CHECK: ae_s32x2.rip aed{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2_x.ll +declare void @llvm.xtensa.ae.s32x2.x(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s32x2_x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32x2_x: + + + + call void @llvm.xtensa.ae.s32x2.x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32x2.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s32x2_xc.ll +declare ptr @llvm.xtensa.ae.s32x2.xc(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32x2_xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32x2_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s32x2.xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32x2.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2_xp.ll +declare ptr @llvm.xtensa.ae.s32x2.xp(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32x2_xp(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32x2_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s32x2.xp(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32x2.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2f24_i.ll +declare void @llvm.xtensa.ae.s32x2f24.i(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s32x2f24_i(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2f24_i: + + + + call void @llvm.xtensa.ae.s32x2f24.i(<2 x i32> %ae_ls_v, ptr %ars, i32 -64) +; CHECK: ae_s32x2f24.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s32x2f24_ip.ll +declare ptr @llvm.xtensa.ae.s32x2f24.ip(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32x2f24_ip(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2f24_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s32x2f24.ip(<2 x i32> %ae_ls_v, ptr %ars, i32 0) +; CHECK: ae_s32x2f24.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2f24_ric.ll +declare ptr @llvm.xtensa.ae.s32x2f24.ric(<2 x i32>, ptr) +define ptr @test_xtensa_ae_s32x2f24_ric(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2f24_ric: + + +%ret = call ptr @llvm.xtensa.ae.s32x2f24.ric(<2 x i32> %ae_ls_v, ptr %ars) +; CHECK: ae_s32x2f24.ric aed{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2f24_rip.ll +declare ptr @llvm.xtensa.ae.s32x2f24.rip(<2 x i32>, ptr) +define ptr @test_xtensa_ae_s32x2f24_rip(<2 x i32> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2f24_rip: + + +%ret = call ptr @llvm.xtensa.ae.s32x2f24.rip(<2 x i32> %ae_ls_v, ptr %ars) +; CHECK: ae_s32x2f24.rip aed{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2f24_x.ll +declare void @llvm.xtensa.ae.s32x2f24.x(<2 x i32>, ptr, i32) +define void @test_xtensa_ae_s32x2f24_x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32x2f24_x: + + + + call void @llvm.xtensa.ae.s32x2f24.x(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32x2f24.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s32x2f24_xc.ll +declare ptr @llvm.xtensa.ae.s32x2f24.xc(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32x2f24_xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32x2f24_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s32x2f24.xc(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32x2f24.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2f24_xp.ll +declare ptr @llvm.xtensa.ae.s32x2f24.xp(<2 x i32>, ptr, i32) +define ptr @test_xtensa_ae_s32x2f24_xp(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s32x2f24_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s32x2f24.xp(<2 x i32> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s32x2f24.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s32x2ra64s_ip.ll +declare ptr @llvm.xtensa.ae.s32x2ra64s.ip(<1 x i64>, <1 x i64>, ptr) +define ptr @test_xtensa_ae_s32x2ra64s_ip(<1 x i64> %ae_ls_v2, <1 x i64> %ae_ls_v1, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s32x2ra64s_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s32x2ra64s.ip(<1 x i64> %ae_ls_v2, <1 x i64> %ae_ls_v1, ptr %ars) +; CHECK: ae_s32x2ra64s.ip aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s64_i.ll +declare void @llvm.xtensa.ae.s64.i(<1 x i64>, ptr, i32) +define void @test_xtensa_ae_s64_i(<1 x i64> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s64_i: + + + + call void @llvm.xtensa.ae.s64.i(<1 x i64> %ae_ls_v, ptr %ars, i32 -64) +; CHECK: ae_s64.i aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_s64_ip.ll +declare ptr @llvm.xtensa.ae.s64.ip(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s64_ip(<1 x i64> %ae_ls_v, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_s64_ip: + + + +%ret = call ptr @llvm.xtensa.ae.s64.ip(<1 x i64> %ae_ls_v, ptr %ars, i32 -64) +; CHECK: ae_s64.ip aed{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s64_x.ll +declare void @llvm.xtensa.ae.s64.x(<1 x i64>, ptr, i32) +define void @test_xtensa_ae_s64_x(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s64_x: + + + + call void @llvm.xtensa.ae.s64.x(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s64.x aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret void +} + + +;--- ae_s64_xc.ll +declare ptr @llvm.xtensa.ae.s64.xc(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s64_xc(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s64_xc: + + + +%ret = call ptr @llvm.xtensa.ae.s64.xc(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s64.xc aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_s64_xp.ll +declare ptr @llvm.xtensa.ae.s64.xp(<1 x i64>, ptr, i32) +define ptr @test_xtensa_ae_s64_xp(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_s64_xp: + + + +%ret = call ptr @llvm.xtensa.ae.s64.xp(<1 x i64> %ae_ls_v, ptr %ars, i32 %art) +; CHECK: ae_s64.xp aed{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sa16x4_ic.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ic(<4 x i16>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa16x4_ic(<4 x i16> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa16x4_ic: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ic(<4 x i16> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa16x4.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa16x4_ip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ip(<4 x i16>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa16x4_ip(<4 x i16> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa16x4_ip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ip(<4 x i16> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa16x4.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa16x4_ric.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ric(<4 x i16>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa16x4_ric(<4 x i16> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa16x4_ric: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ric(<4 x i16> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa16x4.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa16x4_rip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.rip(<4 x i16>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa16x4_rip(<4 x i16> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa16x4_rip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.rip(<4 x i16> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa16x4.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa24_l_ic.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ic(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa24_l_ic(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa24_l_ic: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ic(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa24.l.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa24_l_ip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ip(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa24_l_ip(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa24_l_ip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ip(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa24.l.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa24_l_ric.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ric(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa24_l_ric(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa24_l_ric: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ric(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa24.l.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa24_l_rip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.rip(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa24_l_rip(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa24_l_rip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.rip(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa24.l.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa24x2_ic.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ic(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa24x2_ic(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa24x2_ic: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ic(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa24x2.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa24x2_ip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ip(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa24x2_ip(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa24x2_ip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ip(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa24x2.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa24x2_ric.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ric(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa24x2_ric(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa24x2_ric: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ric(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa24x2.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa24x2_rip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.rip(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa24x2_rip(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa24x2_rip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.rip(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa24x2.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa32x2_ic.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ic(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa32x2_ic(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa32x2_ic: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ic(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa32x2.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa32x2_ip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ip(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa32x2_ip(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa32x2_ip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ip(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa32x2.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa32x2_ric.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ric(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa32x2_ric(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa32x2_ric: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ric(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa32x2.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa32x2_rip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.rip(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa32x2_rip(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa32x2_rip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.rip(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa32x2.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa32x2f24_ic.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ic(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa32x2f24_ic(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa32x2f24_ic: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ic(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa32x2f24.ic aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa32x2f24_ip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ip(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa32x2f24_ip(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa32x2f24_ip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ip(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa32x2f24.ip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa32x2f24_ric.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ric(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa32x2f24_ric(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa32x2f24_ric: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ric(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa32x2f24.ric aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa32x2f24_rip.ll +declare { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.rip(<2 x i32>, <8 x i8>, ptr) +define <1 x i64> @test_xtensa_ae_sa32x2f24_rip(<2 x i32> %ae_ls_v, <1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa32x2f24_rip: + +%wrap1 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.rip(<2 x i32> %ae_ls_v, <8 x i8> %wrap1, ptr %ars) +; CHECK: ae_sa32x2f24.rip aed{{[0-9]+}}, u{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <8 x i8>, ptr } %ret, 0 +%unwrap = bitcast <8 x i8> %ev to <1 x i64> +ret <1 x i64> %unwrap +} + + +;--- ae_sa64neg_fp.ll +declare <8 x i8> @llvm.xtensa.ae.sa64neg.fp(<8 x i8>, ptr) +define <8 x i8> @test_xtensa_ae_sa64neg_fp(<1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa64neg_fp: +%wrap0 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call <8 x i8> @llvm.xtensa.ae.sa64neg.fp(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_sa64neg.fp u{{[0-9]+}}, a{{[0-9]+}} + +ret <8 x i8> %ret +} + + +;--- ae_sa64pos_fp.ll +declare <8 x i8> @llvm.xtensa.ae.sa64pos.fp(<8 x i8>, ptr) +define <8 x i8> @test_xtensa_ae_sa64pos_fp(<1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sa64pos_fp: +%wrap0 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + +%ret = call <8 x i8> @llvm.xtensa.ae.sa64pos.fp(<8 x i8> %wrap0, ptr %ars) +; CHECK: ae_sa64pos.fp u{{[0-9]+}}, a{{[0-9]+}} + +ret <8 x i8> %ret +} + + +;--- ae_salign64_i.ll +declare void @llvm.xtensa.ae.salign64.i(<8 x i8>, ptr, i32) +define void @test_xtensa_ae_salign64_i(<1 x i64> %ae_ls_su, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_salign64_i: +%wrap0 = bitcast <1 x i64> %ae_ls_su to <8 x i8> + + + call void @llvm.xtensa.ae.salign64.i(<8 x i8> %wrap0, ptr %ars, i32 -64) +; CHECK: ae_salign64.i u{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret void +} + + +;--- ae_sat16x4.ll +declare <4 x i16> @llvm.xtensa.ae.sat16x4(<2 x i32>, <2 x i32>) +define <4 x i16> @test_xtensa_ae_sat16x4(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sat16x4: + + +%ret = call <4 x i16> @llvm.xtensa.ae.sat16x4(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_sat16x4 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_sat24s.ll +declare <2 x i32> @llvm.xtensa.ae.sat24s(<2 x i32>) +define <2 x i32> @test_xtensa_ae_sat24s(<2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sat24s: + +%ret = call <2 x i32> @llvm.xtensa.ae.sat24s(<2 x i32> %ae_arth_v1) +; CHECK: ae_sat24s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sat48s.ll +declare <1 x i64> @llvm.xtensa.ae.sat48s(<1 x i64>) +define <1 x i64> @test_xtensa_ae_sat48s(<1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sat48s: + +%ret = call <1 x i64> @llvm.xtensa.ae.sat48s(<1 x i64> %ae_arth_v1) +; CHECK: ae_sat48s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_satq56s.ll +declare <1 x i64> @llvm.xtensa.ae.satq56s(<1 x i64>) +define <1 x i64> @test_xtensa_ae_satq56s(<1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_satq56s: + +%ret = call <1 x i64> @llvm.xtensa.ae.satq56s(<1 x i64> %ae_arth_v1) +; CHECK: ae_satq56s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_sb.ll +declare ptr @llvm.xtensa.ae.sb(ptr, i32) +define ptr @test_xtensa_ae_sb(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_sb: + + +%ret = call ptr @llvm.xtensa.ae.sb(ptr %ars, i32 %art) +; CHECK: ae_sb a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sb_ic.ll +declare ptr @llvm.xtensa.ae.sb.ic(ptr, i32) +define ptr @test_xtensa_ae_sb_ic(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_sb_ic: + + +%ret = call ptr @llvm.xtensa.ae.sb.ic(ptr %ars, i32 %art) +; CHECK: ae_sb.ic a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sb_ip.ll +declare ptr @llvm.xtensa.ae.sb.ip(ptr, i32) +define ptr @test_xtensa_ae_sb_ip(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_sb_ip: + + +%ret = call ptr @llvm.xtensa.ae.sb.ip(ptr %ars, i32 %art) +; CHECK: ae_sb.ip a{{[0-9]+}}, a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sbf.ll +declare ptr @llvm.xtensa.ae.sbf(ptr) +define ptr @test_xtensa_ae_sbf(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sbf: + +%ret = call ptr @llvm.xtensa.ae.sbf(ptr %ars) +; CHECK: ae_sbf a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sbf_ic.ll +declare ptr @llvm.xtensa.ae.sbf.ic(ptr) +define ptr @test_xtensa_ae_sbf_ic(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sbf_ic: + +%ret = call ptr @llvm.xtensa.ae.sbf.ic(ptr %ars) +; CHECK: ae_sbf.ic a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sbf_ip.ll +declare ptr @llvm.xtensa.ae.sbf.ip(ptr) +define ptr @test_xtensa_ae_sbf_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_sbf_ip: + +%ret = call ptr @llvm.xtensa.ae.sbf.ip(ptr %ars) +; CHECK: ae_sbf.ip a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sbi.ll +declare ptr @llvm.xtensa.ae.sbi(ptr, i32, i32) +define ptr @test_xtensa_ae_sbi(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_sbi: + + + +%ret = call ptr @llvm.xtensa.ae.sbi(ptr %ars, i32 %art, i32 1) +; CHECK: ae_sbi a{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sbi_ic.ll +declare ptr @llvm.xtensa.ae.sbi.ic(ptr, i32, i32) +define ptr @test_xtensa_ae_sbi_ic(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_sbi_ic: + + + +%ret = call ptr @llvm.xtensa.ae.sbi.ic(ptr %ars, i32 %art, i32 1) +; CHECK: ae_sbi.ic a{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sbi_ip.ll +declare ptr @llvm.xtensa.ae.sbi.ip(ptr, i32, i32) +define ptr @test_xtensa_ae_sbi_ip(ptr %ars, i32 %art) { +; CHECK-LABEL: test_xtensa_ae_sbi_ip: + + + +%ret = call ptr @llvm.xtensa.ae.sbi.ip(ptr %ars, i32 %art, i32 1) +; CHECK: ae_sbi.ip a{{[0-9]+}}, a{{[0-9]+}}, {{-?[0-9]+}} + +ret ptr %ret +} + + +;--- ae_sel16i.ll +declare <4 x i16> @llvm.xtensa.ae.sel16i(<4 x i16>, <4 x i16>, i32) +define <4 x i16> @test_xtensa_ae_sel16i(<4 x i16> %ae_dr_to_dr_v0, <4 x i16> %ae_dr_to_dr_v1) { +; CHECK-LABEL: test_xtensa_ae_sel16i: + + + +%ret = call <4 x i16> @llvm.xtensa.ae.sel16i(<4 x i16> %ae_dr_to_dr_v0, <4 x i16> %ae_dr_to_dr_v1, i32 0) +; CHECK: ae_sel16i aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_sel16i_n.ll +declare <4 x i16> @llvm.xtensa.ae.sel16i.n(<4 x i16>, <4 x i16>, i32) +define <4 x i16> @test_xtensa_ae_sel16i_n(<4 x i16> %ae_dr_to_dr_v0, <4 x i16> %ae_dr_to_dr_v1) { +; CHECK-LABEL: test_xtensa_ae_sel16i_n: + + + +%ret = call <4 x i16> @llvm.xtensa.ae.sel16i.n(<4 x i16> %ae_dr_to_dr_v0, <4 x i16> %ae_dr_to_dr_v1, i32 0) +; CHECK: ae_sel16i.n aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_sext32.ll +declare <2 x i32> @llvm.xtensa.ae.sext32(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_sext32(<2 x i32> %ae_dr_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_sext32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.sext32(<2 x i32> %ae_dr_to_dr_v0, i32 7) +; CHECK: ae_sext32 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sext32x2d16_10.ll +declare <2 x i32> @llvm.xtensa.ae.sext32x2d16.10(<4 x i16>) +define <2 x i32> @test_xtensa_ae_sext32x2d16_10(<4 x i16> %ae_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_sext32x2d16_10: + +%ret = call <2 x i32> @llvm.xtensa.ae.sext32x2d16.10(<4 x i16> %ae_to_dr_v0) +; CHECK: ae_sext32x2d16.10 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sext32x2d16_32.ll +declare <2 x i32> @llvm.xtensa.ae.sext32x2d16.32(<4 x i16>) +define <2 x i32> @test_xtensa_ae_sext32x2d16_32(<4 x i16> %ae_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_sext32x2d16_32: + +%ret = call <2 x i32> @llvm.xtensa.ae.sext32x2d16.32(<4 x i16> %ae_to_dr_v0) +; CHECK: ae_sext32x2d16.32 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sha32.ll +declare i32 @llvm.xtensa.ae.sha32(i32) +define i32 @test_xtensa_ae_sha32(i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_sha32: + +%ret = call i32 @llvm.xtensa.ae.sha32(i32 %ars) +; CHECK: ae_sha32 a{{[0-9]+}}, a{{[0-9]+}} + +ret i32 %ret +} + + +;--- ae_shortswap.ll +declare <4 x i16> @llvm.xtensa.ae.shortswap(<4 x i16>) +define <4 x i16> @test_xtensa_ae_shortswap(<4 x i16> %ae_to_dr_v0) { +; CHECK-LABEL: test_xtensa_ae_shortswap: + +%ret = call <4 x i16> @llvm.xtensa.ae.shortswap(<4 x i16> %ae_to_dr_v0) +; CHECK: ae_shortswap aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_slaa16s.ll +declare <4 x i16> @llvm.xtensa.ae.slaa16s(<4 x i16>, i32) +define <4 x i16> @test_xtensa_ae_slaa16s(<4 x i16> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_slaa16s: + + +%ret = call <4 x i16> @llvm.xtensa.ae.slaa16s(<4 x i16> %ae_shift_d0, i32 %ars) +; CHECK: ae_slaa16s aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_slaa32.ll +declare <2 x i32> @llvm.xtensa.ae.slaa32(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_slaa32(<2 x i32> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_slaa32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.slaa32(<2 x i32> %ae_shift_d0, i32 %ars) +; CHECK: ae_slaa32 aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slaa32s.ll +declare <2 x i32> @llvm.xtensa.ae.slaa32s(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_slaa32s(<2 x i32> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_slaa32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.slaa32s(<2 x i32> %ae_shift_d0, i32 %ars) +; CHECK: ae_slaa32s aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slaa64.ll +declare <1 x i64> @llvm.xtensa.ae.slaa64(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_slaa64(<1 x i64> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_slaa64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.slaa64(<1 x i64> %ae_shift_d0, i32 %ars) +; CHECK: ae_slaa64 aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slaa64s.ll +declare <1 x i64> @llvm.xtensa.ae.slaa64s(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_slaa64s(<1 x i64> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_slaa64s: + + +%ret = call <1 x i64> @llvm.xtensa.ae.slaa64s(<1 x i64> %ae_shift_d0, i32 %ars) +; CHECK: ae_slaa64s aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slaaq56.ll +declare <1 x i64> @llvm.xtensa.ae.slaaq56(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_slaaq56(<1 x i64> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_slaaq56: + + +%ret = call <1 x i64> @llvm.xtensa.ae.slaaq56(<1 x i64> %ae_shift_d0, i32 %ars) +; CHECK: ae_slaaq56 aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slai16s.ll +declare <4 x i16> @llvm.xtensa.ae.slai16s(<4 x i16>, i32) +define <4 x i16> @test_xtensa_ae_slai16s(<4 x i16> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slai16s: + + +%ret = call <4 x i16> @llvm.xtensa.ae.slai16s(<4 x i16> %ae_shift_d0, i32 0) +; CHECK: ae_slai16s aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_slai24.ll +declare <2 x i32> @llvm.xtensa.ae.slai24(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_slai24(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slai24: + + +%ret = call <2 x i32> @llvm.xtensa.ae.slai24(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_slai24 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slai24s.ll +declare <2 x i32> @llvm.xtensa.ae.slai24s(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_slai24s(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slai24s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.slai24s(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_slai24s aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slai32.ll +declare <2 x i32> @llvm.xtensa.ae.slai32(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_slai32(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slai32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.slai32(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_slai32 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slai32s.ll +declare <2 x i32> @llvm.xtensa.ae.slai32s(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_slai32s(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slai32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.slai32s(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_slai32s aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slai64.ll +declare <1 x i64> @llvm.xtensa.ae.slai64(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_slai64(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slai64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.slai64(<1 x i64> %ae_shift_d0, i32 0) +; CHECK: ae_slai64 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slai64s.ll +declare <1 x i64> @llvm.xtensa.ae.slai64s(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_slai64s(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slai64s: + + +%ret = call <1 x i64> @llvm.xtensa.ae.slai64s(<1 x i64> %ae_shift_d0, i32 0) +; CHECK: ae_slai64s aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slaisq56s.ll +declare <1 x i64> @llvm.xtensa.ae.slaisq56s(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_slaisq56s(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slaisq56s: + + +%ret = call <1 x i64> @llvm.xtensa.ae.slaisq56s(<1 x i64> %ae_shift_d0, i32 0) +; CHECK: ae_slaisq56s aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slas24.ll +declare <2 x i32> @llvm.xtensa.ae.slas24(<2 x i32>) +define <2 x i32> @test_xtensa_ae_slas24(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slas24: + +%ret = call <2 x i32> @llvm.xtensa.ae.slas24(<2 x i32> %ae_shift_d0) +; CHECK: ae_slas24 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slas24s.ll +declare <2 x i32> @llvm.xtensa.ae.slas24s(<2 x i32>) +define <2 x i32> @test_xtensa_ae_slas24s(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slas24s: + +%ret = call <2 x i32> @llvm.xtensa.ae.slas24s(<2 x i32> %ae_shift_d0) +; CHECK: ae_slas24s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slas32.ll +declare <2 x i32> @llvm.xtensa.ae.slas32(<2 x i32>) +define <2 x i32> @test_xtensa_ae_slas32(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slas32: + +%ret = call <2 x i32> @llvm.xtensa.ae.slas32(<2 x i32> %ae_shift_d0) +; CHECK: ae_slas32 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slas32s.ll +declare <2 x i32> @llvm.xtensa.ae.slas32s(<2 x i32>) +define <2 x i32> @test_xtensa_ae_slas32s(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slas32s: + +%ret = call <2 x i32> @llvm.xtensa.ae.slas32s(<2 x i32> %ae_shift_d0) +; CHECK: ae_slas32s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_slas64.ll +declare <1 x i64> @llvm.xtensa.ae.slas64(<1 x i64>) +define <1 x i64> @test_xtensa_ae_slas64(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slas64: + +%ret = call <1 x i64> @llvm.xtensa.ae.slas64(<1 x i64> %ae_shift_d0) +; CHECK: ae_slas64 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slas64s.ll +declare <1 x i64> @llvm.xtensa.ae.slas64s(<1 x i64>) +define <1 x i64> @test_xtensa_ae_slas64s(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slas64s: + +%ret = call <1 x i64> @llvm.xtensa.ae.slas64s(<1 x i64> %ae_shift_d0) +; CHECK: ae_slas64s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slasq56.ll +declare <1 x i64> @llvm.xtensa.ae.slasq56(<1 x i64>) +define <1 x i64> @test_xtensa_ae_slasq56(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slasq56: + +%ret = call <1 x i64> @llvm.xtensa.ae.slasq56(<1 x i64> %ae_shift_d0) +; CHECK: ae_slasq56 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_slassq56s.ll +declare <1 x i64> @llvm.xtensa.ae.slassq56s(<1 x i64>) +define <1 x i64> @test_xtensa_ae_slassq56s(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_slassq56s: + +%ret = call <1 x i64> @llvm.xtensa.ae.slassq56s(<1 x i64> %ae_shift_d0) +; CHECK: ae_slassq56s aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_sra64_32.ll +declare <1 x i64> @llvm.xtensa.ae.sra64.32(<2 x i32>, i32) +define <1 x i64> @test_xtensa_ae_sra64_32(<2 x i32> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_sra64_32: + + +%ret = call <1 x i64> @llvm.xtensa.ae.sra64.32(<2 x i32> %ae_shift_d0, i32 %ars) +; CHECK: ae_sra64_32 aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_sraa16rs.ll +declare <4 x i16> @llvm.xtensa.ae.sraa16rs(<4 x i16>, i32) +define <4 x i16> @test_xtensa_ae_sraa16rs(<4 x i16> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_sraa16rs: + + +%ret = call <4 x i16> @llvm.xtensa.ae.sraa16rs(<4 x i16> %ae_shift_d0, i32 %ars) +; CHECK: ae_sraa16rs aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_sraa16s.ll +declare <4 x i16> @llvm.xtensa.ae.sraa16s(<4 x i16>, i32) +define <4 x i16> @test_xtensa_ae_sraa16s(<4 x i16> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_sraa16s: + + +%ret = call <4 x i16> @llvm.xtensa.ae.sraa16s(<4 x i16> %ae_shift_d0, i32 %ars) +; CHECK: ae_sraa16s aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_sraa32.ll +declare <2 x i32> @llvm.xtensa.ae.sraa32(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_sraa32(<2 x i32> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_sraa32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.sraa32(<2 x i32> %ae_shift_d0, i32 %ars) +; CHECK: ae_sraa32 aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sraa32rs.ll +declare <2 x i32> @llvm.xtensa.ae.sraa32rs(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_sraa32rs(<2 x i32> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_sraa32rs: + + +%ret = call <2 x i32> @llvm.xtensa.ae.sraa32rs(<2 x i32> %ae_shift_d0, i32 %ars) +; CHECK: ae_sraa32rs aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sraa32s.ll +declare <2 x i32> @llvm.xtensa.ae.sraa32s(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_sraa32s(<2 x i32> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_sraa32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.sraa32s(<2 x i32> %ae_shift_d0, i32 %ars) +; CHECK: ae_sraa32s aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sraa64.ll +declare <1 x i64> @llvm.xtensa.ae.sraa64(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_sraa64(<1 x i64> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_sraa64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.sraa64(<1 x i64> %ae_shift_d0, i32 %ars) +; CHECK: ae_sraa64 aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_srai16.ll +declare <4 x i16> @llvm.xtensa.ae.srai16(<4 x i16>, i32) +define <4 x i16> @test_xtensa_ae_srai16(<4 x i16> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srai16: + + +%ret = call <4 x i16> @llvm.xtensa.ae.srai16(<4 x i16> %ae_shift_d0, i32 0) +; CHECK: ae_srai16 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_srai16r.ll +declare <4 x i16> @llvm.xtensa.ae.srai16r(<4 x i16>, i32) +define <4 x i16> @test_xtensa_ae_srai16r(<4 x i16> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srai16r: + + +%ret = call <4 x i16> @llvm.xtensa.ae.srai16r(<4 x i16> %ae_shift_d0, i32 0) +; CHECK: ae_srai16r aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_srai24.ll +declare <2 x i32> @llvm.xtensa.ae.srai24(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_srai24(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srai24: + + +%ret = call <2 x i32> @llvm.xtensa.ae.srai24(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_srai24 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_srai32.ll +declare <2 x i32> @llvm.xtensa.ae.srai32(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_srai32(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srai32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.srai32(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_srai32 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_srai32r.ll +declare <2 x i32> @llvm.xtensa.ae.srai32r(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_srai32r(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srai32r: + + +%ret = call <2 x i32> @llvm.xtensa.ae.srai32r(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_srai32r aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_srai64.ll +declare <1 x i64> @llvm.xtensa.ae.srai64(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_srai64(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srai64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.srai64(<1 x i64> %ae_shift_d0, i32 0) +; CHECK: ae_srai64 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_sras24.ll +declare <2 x i32> @llvm.xtensa.ae.sras24(<2 x i32>) +define <2 x i32> @test_xtensa_ae_sras24(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_sras24: + +%ret = call <2 x i32> @llvm.xtensa.ae.sras24(<2 x i32> %ae_shift_d0) +; CHECK: ae_sras24 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sras32.ll +declare <2 x i32> @llvm.xtensa.ae.sras32(<2 x i32>) +define <2 x i32> @test_xtensa_ae_sras32(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_sras32: + +%ret = call <2 x i32> @llvm.xtensa.ae.sras32(<2 x i32> %ae_shift_d0) +; CHECK: ae_sras32 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sras64.ll +declare <1 x i64> @llvm.xtensa.ae.sras64(<1 x i64>) +define <1 x i64> @test_xtensa_ae_sras64(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_sras64: + +%ret = call <1 x i64> @llvm.xtensa.ae.sras64(<1 x i64> %ae_shift_d0) +; CHECK: ae_sras64 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_srla32.ll +declare <2 x i32> @llvm.xtensa.ae.srla32(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_srla32(<2 x i32> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_srla32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.srla32(<2 x i32> %ae_shift_d0, i32 %ars) +; CHECK: ae_srla32 aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_srla64.ll +declare <1 x i64> @llvm.xtensa.ae.srla64(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_srla64(<1 x i64> %ae_shift_d0, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_srla64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.srla64(<1 x i64> %ae_shift_d0, i32 %ars) +; CHECK: ae_srla64 aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_srli24.ll +declare <2 x i32> @llvm.xtensa.ae.srli24(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_srli24(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srli24: + + +%ret = call <2 x i32> @llvm.xtensa.ae.srli24(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_srli24 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_srli32.ll +declare <2 x i32> @llvm.xtensa.ae.srli32(<2 x i32>, i32) +define <2 x i32> @test_xtensa_ae_srli32(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srli32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.srli32(<2 x i32> %ae_shift_d0, i32 0) +; CHECK: ae_srli32 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_srli64.ll +declare <1 x i64> @llvm.xtensa.ae.srli64(<1 x i64>, i32) +define <1 x i64> @test_xtensa_ae_srli64(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srli64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.srli64(<1 x i64> %ae_shift_d0, i32 0) +; CHECK: ae_srli64 aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_srls24.ll +declare <2 x i32> @llvm.xtensa.ae.srls24(<2 x i32>) +define <2 x i32> @test_xtensa_ae_srls24(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srls24: + +%ret = call <2 x i32> @llvm.xtensa.ae.srls24(<2 x i32> %ae_shift_d0) +; CHECK: ae_srls24 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_srls32.ll +declare <2 x i32> @llvm.xtensa.ae.srls32(<2 x i32>) +define <2 x i32> @test_xtensa_ae_srls32(<2 x i32> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srls32: + +%ret = call <2 x i32> @llvm.xtensa.ae.srls32(<2 x i32> %ae_shift_d0) +; CHECK: ae_srls32 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_srls64.ll +declare <1 x i64> @llvm.xtensa.ae.srls64(<1 x i64>) +define <1 x i64> @test_xtensa_ae_srls64(<1 x i64> %ae_shift_d0) { +; CHECK-LABEL: test_xtensa_ae_srls64: + +%ret = call <1 x i64> @llvm.xtensa.ae.srls64(<1 x i64> %ae_shift_d0) +; CHECK: ae_srls64 aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_sub16.ll +declare <4 x i16> @llvm.xtensa.ae.sub16(<4 x i16>, <4 x i16>) +define <4 x i16> @test_xtensa_ae_sub16(<4 x i16> %ae_arth_v0, <4 x i16> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sub16: + + +%ret = call <4 x i16> @llvm.xtensa.ae.sub16(<4 x i16> %ae_arth_v0, <4 x i16> %ae_arth_v1) +; CHECK: ae_sub16 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_sub16s.ll +declare <4 x i16> @llvm.xtensa.ae.sub16s(<4 x i16>, <4 x i16>) +define <4 x i16> @test_xtensa_ae_sub16s(<4 x i16> %ae_arth_v0, <4 x i16> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sub16s: + + +%ret = call <4 x i16> @llvm.xtensa.ae.sub16s(<4 x i16> %ae_arth_v0, <4 x i16> %ae_arth_v1) +; CHECK: ae_sub16s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <4 x i16> %ret +} + + +;--- ae_sub24s.ll +declare <2 x i32> @llvm.xtensa.ae.sub24s(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_sub24s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sub24s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.sub24s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_sub24s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sub32.ll +declare <2 x i32> @llvm.xtensa.ae.sub32(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_sub32(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sub32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.sub32(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_sub32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sub32s.ll +declare <2 x i32> @llvm.xtensa.ae.sub32s(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_sub32s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sub32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.sub32s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_sub32s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_sub64.ll +declare <1 x i64> @llvm.xtensa.ae.sub64(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_sub64(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sub64: + + +%ret = call <1 x i64> @llvm.xtensa.ae.sub64(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_sub64 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_sub64s.ll +declare <1 x i64> @llvm.xtensa.ae.sub64s(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_sub64s(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_sub64s: + + +%ret = call <1 x i64> @llvm.xtensa.ae.sub64s(<1 x i64> %ae_arth_v0, <1 x i64> %ae_arth_v1) +; CHECK: ae_sub64s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_subadd32.ll +declare <2 x i32> @llvm.xtensa.ae.subadd32(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_subadd32(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_subadd32: + + +%ret = call <2 x i32> @llvm.xtensa.ae.subadd32(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_subadd32 aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_subadd32s.ll +declare <2 x i32> @llvm.xtensa.ae.subadd32s(<2 x i32>, <2 x i32>) +define <2 x i32> @test_xtensa_ae_subadd32s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) { +; CHECK-LABEL: test_xtensa_ae_subadd32s: + + +%ret = call <2 x i32> @llvm.xtensa.ae.subadd32s(<2 x i32> %ae_arth_v0, <2 x i32> %ae_arth_v1) +; CHECK: ae_subadd32s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_trunca32f64s_l.ll +declare <2 x i32> @llvm.xtensa.ae.trunca32f64s.l(<2 x i32>, <1 x i64>, i32) +define <2 x i32> @test_xtensa_ae_trunca32f64s_l(<2 x i32> %ae_shift_d0, <1 x i64> %ae_shift_sd, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_trunca32f64s_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.trunca32f64s.l(<2 x i32> %ae_shift_d0, <1 x i64> %ae_shift_sd, i32 %ars) +; CHECK: ae_trunca32f64s.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_trunca32x2f64s.ll +declare <2 x i32> @llvm.xtensa.ae.trunca32x2f64s(<1 x i64>, <1 x i64>, i32) +define <2 x i32> @test_xtensa_ae_trunca32x2f64s(<1 x i64> %ae_shift_d0, <1 x i64> %ae_shift_sd, i32 %ars) { +; CHECK-LABEL: test_xtensa_ae_trunca32x2f64s: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.trunca32x2f64s(<1 x i64> %ae_shift_d0, <1 x i64> %ae_shift_sd, i32 %ars) +; CHECK: ae_trunca32x2f64s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, a{{[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_trunci32f64s_l.ll +declare <2 x i32> @llvm.xtensa.ae.trunci32f64s.l(<2 x i32>, <1 x i64>, i32) +define <2 x i32> @test_xtensa_ae_trunci32f64s_l(<2 x i32> %ae_shift_d0, <1 x i64> %ae_shift_sd) { +; CHECK-LABEL: test_xtensa_ae_trunci32f64s_l: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.trunci32f64s.l(<2 x i32> %ae_shift_d0, <1 x i64> %ae_shift_sd, i32 0) +; CHECK: ae_trunci32f64s.l aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_trunci32x2f64s.ll +declare <2 x i32> @llvm.xtensa.ae.trunci32x2f64s(<1 x i64>, <1 x i64>, i32) +define <2 x i32> @test_xtensa_ae_trunci32x2f64s(<1 x i64> %ae_shift_d0, <1 x i64> %ae_shift_sd) { +; CHECK-LABEL: test_xtensa_ae_trunci32x2f64s: + + + +%ret = call <2 x i32> @llvm.xtensa.ae.trunci32x2f64s(<1 x i64> %ae_shift_d0, <1 x i64> %ae_shift_sd, i32 0) +; CHECK: ae_trunci32x2f64s aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}}, {{-?[0-9]+}} + +ret <2 x i32> %ret +} + + +;--- ae_vldl16c.ll +declare ptr @llvm.xtensa.ae.vldl16c(ptr) +define ptr @test_xtensa_ae_vldl16c(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vldl16c: + +%ret = call ptr @llvm.xtensa.ae.vldl16c(ptr %ars) +; CHECK: ae_vldl16c a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_vldl16c_ic.ll +declare ptr @llvm.xtensa.ae.vldl16c.ic(ptr) +define ptr @test_xtensa_ae_vldl16c_ic(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vldl16c_ic: + +%ret = call ptr @llvm.xtensa.ae.vldl16c.ic(ptr %ars) +; CHECK: ae_vldl16c.ic a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_vldl16c_ip.ll +declare ptr @llvm.xtensa.ae.vldl16c.ip(ptr) +define ptr @test_xtensa_ae_vldl16c_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vldl16c_ip: + +%ret = call ptr @llvm.xtensa.ae.vldl16c.ip(ptr %ars) +; CHECK: ae_vldl16c.ip a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_vldl16t.ll +declare { <1 x i1>, i32 } @llvm.xtensa.ae.vldl16t(ptr) +define <1 x i1> @test_xtensa_ae_vldl16t(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vldl16t: + +%ret = call { <1 x i1>, i32 } @llvm.xtensa.ae.vldl16t(ptr %ars) +; CHECK: ae_vldl16t b{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <1 x i1>, i32 } %ret, 0 +ret <1 x i1> %ev +} + + +;--- ae_vldl32t.ll +declare { <1 x i1>, i32 } @llvm.xtensa.ae.vldl32t(ptr) +define <1 x i1> @test_xtensa_ae_vldl32t(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vldl32t: + +%ret = call { <1 x i1>, i32 } @llvm.xtensa.ae.vldl32t(ptr %ars) +; CHECK: ae_vldl32t b{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <1 x i1>, i32 } %ret, 0 +ret <1 x i1> %ev +} + + +;--- ae_vldsht.ll +declare void @llvm.xtensa.ae.vldsht(i32) +define void @test_xtensa_ae_vldsht(i32 %art) { +; CHECK-LABEL: test_xtensa_ae_vldsht: + + call void @llvm.xtensa.ae.vldsht(i32 %art) +; CHECK: ae_vldsht a{{[0-9]+}} + +ret void +} + + +;--- ae_vlel16t.ll +declare { <1 x i1>, i32 } @llvm.xtensa.ae.vlel16t(i32, ptr) +define <1 x i1> @test_xtensa_ae_vlel16t(i32 %art, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vlel16t: + + +%ret = call { <1 x i1>, i32 } @llvm.xtensa.ae.vlel16t(i32 %art, ptr %ars) +; CHECK: ae_vlel16t b{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <1 x i1>, i32 } %ret, 0 +ret <1 x i1> %ev +} + + +;--- ae_vlel32t.ll +declare { <1 x i1>, i32 } @llvm.xtensa.ae.vlel32t(i32, ptr) +define <1 x i1> @test_xtensa_ae_vlel32t(i32 %art, ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vlel32t: + + +%ret = call { <1 x i1>, i32 } @llvm.xtensa.ae.vlel32t(i32 %art, ptr %ars) +; CHECK: ae_vlel32t b{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}} +%ev = extractvalue { <1 x i1>, i32 } %ret, 0 +ret <1 x i1> %ev +} + + +;--- ae_vles16c.ll +declare ptr @llvm.xtensa.ae.vles16c(ptr) +define ptr @test_xtensa_ae_vles16c(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vles16c: + +%ret = call ptr @llvm.xtensa.ae.vles16c(ptr %ars) +; CHECK: ae_vles16c a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_vles16c_ic.ll +declare ptr @llvm.xtensa.ae.vles16c.ic(ptr) +define ptr @test_xtensa_ae_vles16c_ic(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vles16c_ic: + +%ret = call ptr @llvm.xtensa.ae.vles16c.ic(ptr %ars) +; CHECK: ae_vles16c.ic a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_vles16c_ip.ll +declare ptr @llvm.xtensa.ae.vles16c.ip(ptr) +define ptr @test_xtensa_ae_vles16c_ip(ptr %ars) { +; CHECK-LABEL: test_xtensa_ae_vles16c_ip: + +%ret = call ptr @llvm.xtensa.ae.vles16c.ip(ptr %ars) +; CHECK: ae_vles16c.ip a{{[0-9]+}} + +ret ptr %ret +} + + +;--- ae_xor.ll +declare <1 x i64> @llvm.xtensa.ae.xor(<1 x i64>, <1 x i64>) +define <1 x i64> @test_xtensa_ae_xor(<1 x i64> %ae_dr_to_dr_v0, <1 x i64> %ae_dr_to_dr_v1) { +; CHECK-LABEL: test_xtensa_ae_xor: + + +%ret = call <1 x i64> @llvm.xtensa.ae.xor(<1 x i64> %ae_dr_to_dr_v0, <1 x i64> %ae_dr_to_dr_v1) +; CHECK: ae_xor aed{{[0-9]+}}, aed{{[0-9]+}}, aed{{[0-9]+}} + +ret <1 x i64> %ret +} + + +;--- ae_zalign64.ll +declare <8 x i8> @llvm.xtensa.ae.zalign64() +define <8 x i8> @test_xtensa_ae_zalign64() { +; CHECK-LABEL: test_xtensa_ae_zalign64: + +%ret = call <8 x i8> @llvm.xtensa.ae.zalign64() +; CHECK: ae_zalign64 u{{[0-9]+}} + +ret <8 x i8> %ret +} + + +;--- rur_ae_bithead.ll +declare i32 @llvm.xtensa.rur.ae.bithead() +define i32 @test_xtensa_rur_ae_bithead() { +; CHECK-LABEL: test_xtensa_rur_ae_bithead: + +%ret = call i32 @llvm.xtensa.rur.ae.bithead() +; CHECK: rur.ae_bithead a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_bitptr.ll +declare i32 @llvm.xtensa.rur.ae.bitptr() +define i32 @test_xtensa_rur_ae_bitptr() { +; CHECK-LABEL: test_xtensa_rur_ae_bitptr: + +%ret = call i32 @llvm.xtensa.rur.ae.bitptr() +; CHECK: rur.ae_bitptr a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_bitsused.ll +declare i32 @llvm.xtensa.rur.ae.bitsused() +define i32 @test_xtensa_rur_ae_bitsused() { +; CHECK-LABEL: test_xtensa_rur_ae_bitsused: + +%ret = call i32 @llvm.xtensa.rur.ae.bitsused() +; CHECK: rur.ae_bitsused a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_cbegin0.ll +declare i32 @llvm.xtensa.rur.ae.cbegin0() +define i32 @test_xtensa_rur_ae_cbegin0() { +; CHECK-LABEL: test_xtensa_rur_ae_cbegin0: + +%ret = call i32 @llvm.xtensa.rur.ae.cbegin0() +; CHECK: rur.ae_cbegin0 a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_cend0.ll +declare i32 @llvm.xtensa.rur.ae.cend0() +define i32 @test_xtensa_rur_ae_cend0() { +; CHECK-LABEL: test_xtensa_rur_ae_cend0: + +%ret = call i32 @llvm.xtensa.rur.ae.cend0() +; CHECK: rur.ae_cend0 a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_cw_sd_no.ll +declare i32 @llvm.xtensa.rur.ae.cw.sd.no() +define i32 @test_xtensa_rur_ae_cw_sd_no() { +; CHECK-LABEL: test_xtensa_rur_ae_cw_sd_no: + +%ret = call i32 @llvm.xtensa.rur.ae.cw.sd.no() +; CHECK: rur.ae_cw_sd_no a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_cwrap.ll +declare i32 @llvm.xtensa.rur.ae.cwrap() +define i32 @test_xtensa_rur_ae_cwrap() { +; CHECK-LABEL: test_xtensa_rur_ae_cwrap: + +%ret = call i32 @llvm.xtensa.rur.ae.cwrap() +; CHECK: rur.ae_cwrap a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_first_ts.ll +declare i32 @llvm.xtensa.rur.ae.first.ts() +define i32 @test_xtensa_rur_ae_first_ts() { +; CHECK-LABEL: test_xtensa_rur_ae_first_ts: + +%ret = call i32 @llvm.xtensa.rur.ae.first.ts() +; CHECK: rur.ae_first_ts a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_nextoffset.ll +declare i32 @llvm.xtensa.rur.ae.nextoffset() +define i32 @test_xtensa_rur_ae_nextoffset() { +; CHECK-LABEL: test_xtensa_rur_ae_nextoffset: + +%ret = call i32 @llvm.xtensa.rur.ae.nextoffset() +; CHECK: rur.ae_nextoffset a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_overflow.ll +declare i32 @llvm.xtensa.rur.ae.overflow() +define i32 @test_xtensa_rur_ae_overflow() { +; CHECK-LABEL: test_xtensa_rur_ae_overflow: + +%ret = call i32 @llvm.xtensa.rur.ae.overflow() +; CHECK: rur.ae_overflow a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_ovf_sar.ll +declare i32 @llvm.xtensa.rur.ae.ovf.sar() +define i32 @test_xtensa_rur_ae_ovf_sar() { +; CHECK-LABEL: test_xtensa_rur_ae_ovf_sar: + +%ret = call i32 @llvm.xtensa.rur.ae.ovf.sar() +; CHECK: rur.ae_ovf_sar a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_sar.ll +declare i32 @llvm.xtensa.rur.ae.sar() +define i32 @test_xtensa_rur_ae_sar() { +; CHECK-LABEL: test_xtensa_rur_ae_sar: + +%ret = call i32 @llvm.xtensa.rur.ae.sar() +; CHECK: rur.ae_sar a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_searchdone.ll +declare i32 @llvm.xtensa.rur.ae.searchdone() +define i32 @test_xtensa_rur_ae_searchdone() { +; CHECK-LABEL: test_xtensa_rur_ae_searchdone: + +%ret = call i32 @llvm.xtensa.rur.ae.searchdone() +; CHECK: rur.ae_searchdone a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_tablesize.ll +declare i32 @llvm.xtensa.rur.ae.tablesize() +define i32 @test_xtensa_rur_ae_tablesize() { +; CHECK-LABEL: test_xtensa_rur_ae_tablesize: + +%ret = call i32 @llvm.xtensa.rur.ae.tablesize() +; CHECK: rur.ae_tablesize a{{[0-9]+}} + +ret i32 %ret +} + + +;--- rur_ae_ts_fts_bu_bp.ll +declare i32 @llvm.xtensa.rur.ae.ts.fts.bu.bp() +define i32 @test_xtensa_rur_ae_ts_fts_bu_bp() { +; CHECK-LABEL: test_xtensa_rur_ae_ts_fts_bu_bp: + +%ret = call i32 @llvm.xtensa.rur.ae.ts.fts.bu.bp() +; CHECK: rur.ae_ts_fts_bu_bp a{{[0-9]+}} + +ret i32 %ret +} + + +;--- wur_ae_bithead.ll +declare void @llvm.xtensa.wur.ae.bithead(i32) +define void @test_xtensa_wur_ae_bithead(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_bithead: + + call void @llvm.xtensa.wur.ae.bithead(i32 %art) +; CHECK: wur.ae_bithead a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_bitptr.ll +declare void @llvm.xtensa.wur.ae.bitptr(i32) +define void @test_xtensa_wur_ae_bitptr(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_bitptr: + + call void @llvm.xtensa.wur.ae.bitptr(i32 %art) +; CHECK: wur.ae_bitptr a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_bitsused.ll +declare void @llvm.xtensa.wur.ae.bitsused(i32) +define void @test_xtensa_wur_ae_bitsused(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_bitsused: + + call void @llvm.xtensa.wur.ae.bitsused(i32 %art) +; CHECK: wur.ae_bitsused a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_cbegin0.ll +declare void @llvm.xtensa.wur.ae.cbegin0(i32) +define void @test_xtensa_wur_ae_cbegin0(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_cbegin0: + + call void @llvm.xtensa.wur.ae.cbegin0(i32 %art) +; CHECK: wur.ae_cbegin0 a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_cend0.ll +declare void @llvm.xtensa.wur.ae.cend0(i32) +define void @test_xtensa_wur_ae_cend0(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_cend0: + + call void @llvm.xtensa.wur.ae.cend0(i32 %art) +; CHECK: wur.ae_cend0 a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_cw_sd_no.ll +declare void @llvm.xtensa.wur.ae.cw.sd.no(i32) +define void @test_xtensa_wur_ae_cw_sd_no(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_cw_sd_no: + + call void @llvm.xtensa.wur.ae.cw.sd.no(i32 %art) +; CHECK: wur.ae_cw_sd_no a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_cwrap.ll +declare void @llvm.xtensa.wur.ae.cwrap(i32) +define void @test_xtensa_wur_ae_cwrap(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_cwrap: + + call void @llvm.xtensa.wur.ae.cwrap(i32 %art) +; CHECK: wur.ae_cwrap a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_first_ts.ll +declare void @llvm.xtensa.wur.ae.first.ts(i32) +define void @test_xtensa_wur_ae_first_ts(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_first_ts: + + call void @llvm.xtensa.wur.ae.first.ts(i32 %art) +; CHECK: wur.ae_first_ts a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_nextoffset.ll +declare void @llvm.xtensa.wur.ae.nextoffset(i32) +define void @test_xtensa_wur_ae_nextoffset(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_nextoffset: + + call void @llvm.xtensa.wur.ae.nextoffset(i32 %art) +; CHECK: wur.ae_nextoffset a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_overflow.ll +declare void @llvm.xtensa.wur.ae.overflow(i32) +define void @test_xtensa_wur_ae_overflow(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_overflow: + + call void @llvm.xtensa.wur.ae.overflow(i32 %art) +; CHECK: wur.ae_overflow a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_ovf_sar.ll +declare void @llvm.xtensa.wur.ae.ovf.sar(i32) +define void @test_xtensa_wur_ae_ovf_sar(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_ovf_sar: + + call void @llvm.xtensa.wur.ae.ovf.sar(i32 %art) +; CHECK: wur.ae_ovf_sar a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_sar.ll +declare void @llvm.xtensa.wur.ae.sar(i32) +define void @test_xtensa_wur_ae_sar(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_sar: + + call void @llvm.xtensa.wur.ae.sar(i32 %art) +; CHECK: wur.ae_sar a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_searchdone.ll +declare void @llvm.xtensa.wur.ae.searchdone(i32) +define void @test_xtensa_wur_ae_searchdone(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_searchdone: + + call void @llvm.xtensa.wur.ae.searchdone(i32 %art) +; CHECK: wur.ae_searchdone a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_tablesize.ll +declare void @llvm.xtensa.wur.ae.tablesize(i32) +define void @test_xtensa_wur_ae_tablesize(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_tablesize: + + call void @llvm.xtensa.wur.ae.tablesize(i32 %art) +; CHECK: wur.ae_tablesize a{{[0-9]+}} + +ret void +} + + +;--- wur_ae_ts_fts_bu_bp.ll +declare void @llvm.xtensa.wur.ae.ts.fts.bu.bp(i32) +define void @test_xtensa_wur_ae_ts_fts_bu_bp(i32 %art) { +; CHECK-LABEL: test_xtensa_wur_ae_ts_fts_bu_bp: + + call void @llvm.xtensa.wur.ae.ts.fts.bu.bp(i32 %art) +; CHECK: wur.ae_ts_fts_bu_bp a{{[0-9]+}} + +ret void +} + + From 81e701d3bd35b0e4a0a2b53d9fc377f819c4f1a3 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:51:02 +0000 Subject: [PATCH 218/261] [Xtensa] Support bit vectors in BRegFixupPass --- .../lib/Target/Xtensa/XtensaBRegFixupPass.cpp | 49 +++++++++++++++++-- 1 file changed, 45 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaBRegFixupPass.cpp b/llvm/lib/Target/Xtensa/XtensaBRegFixupPass.cpp index 87077c96fd81d6..0fcdebc1b88584 100644 --- a/llvm/lib/Target/Xtensa/XtensaBRegFixupPass.cpp +++ b/llvm/lib/Target/Xtensa/XtensaBRegFixupPass.cpp @@ -92,10 +92,26 @@ bool XtensaBRegFixup::VisitInstruction( const XtensaInstrInfo &TII = *static_cast(MF->getSubtarget().getInstrInfo()); unsigned Opcode = MI->getOpcode(); - unsigned RegBase = Xtensa::B0; switch (Opcode) { + case Xtensa::MOVBA2_P2: case Xtensa::MOVBA_P2: { + + unsigned RegBase; + unsigned Arity; + + switch (Opcode) { + case Xtensa::MOVBA_P2: + RegBase = Xtensa::B0; + Arity = 1; + break; + case Xtensa::MOVBA2_P2: + RegBase = Xtensa::B0_B1; + Arity = 2; + break; + default: + llvm_unreachable("Unknown MOVBA opcode"); + } /* MOVBA_P2 Breg, Dst1, Dst2, Src | @@ -107,13 +123,16 @@ bool XtensaBRegFixup::VisitInstruction( OR Dst2, Dst2, Dst1 WSR BREG, Dst2 */ + // TODO: Mask SRC, e.g. by EXTUI MachineOperand Breg = MI->getOperand(0); MachineOperand Dst1 = MI->getOperand(1); MachineOperand Dst2 = MI->getOperand(2); MachineOperand Src = MI->getOperand(3); DebugLoc DL = MI->getDebugLoc(); unsigned RegNo = Breg.getReg().id() - RegBase; - int64_t Mask = 0xffff & (~(1 << RegNo)); + + int64_t BaseMask = (1 << Arity) - 1; + int64_t Mask = 0xffff & (~(BaseMask << (RegNo * Arity))); MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Xtensa::RSR)).add(Dst1).addReg(Xtensa::BREG); @@ -139,6 +158,27 @@ bool XtensaBRegFixup::VisitInstruction( return true; } break; case Xtensa::EXTUI_BR_P: { + case Xtensa::EXTUI_BR2_P: + case Xtensa::EXTUI_BR4_P: + unsigned RegBase; + unsigned Arity; + + switch (Opcode) { + case Xtensa::EXTUI_BR_P: + RegBase = Xtensa::B0; + Arity = 1; + break; + case Xtensa::EXTUI_BR2_P: + RegBase = Xtensa::B0_B1; + Arity = 2; + break; + case Xtensa::EXTUI_BR4_P: + RegBase = Xtensa::B0_B1_B2_B3; + Arity = 4; + break; + default: + llvm_unreachable("Unknown EXTUI opcode"); + } MachineOperand Breg = MI->getOperand(2); DebugLoc dl = MI->getDebugLoc(); @@ -149,8 +189,8 @@ bool XtensaBRegFixup::VisitInstruction( MIB.add(MI->getOperand(0)); MIB.add(MI->getOperand(1)); unsigned RegNo = Breg.getReg().id() - RegBase; - MIB.addImm(RegNo); - MIB.addImm(1); + MIB.addImm(RegNo * Arity); + MIB.addImm(Arity); LLVM_DEBUG(dbgs() << " Fixed EXTUI: " << *MIB); MBB.erase_instr(MI); @@ -160,6 +200,7 @@ bool XtensaBRegFixup::VisitInstruction( case Xtensa::SLLI_BR_P: { + unsigned RegBase = Xtensa::B0; MachineOperand Breg = MI->getOperand(2); unsigned RegNo = Breg.getReg().id() - RegBase; if (RegNo != 0) { From 607935aa47efe9dd4fab88496f2111fbc32f9b22 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:29:23 +0000 Subject: [PATCH 219/261] [Xtensa] Add codegen tests for bit vectors --- .../CodeGen/Xtensa/xtensa-xtbool-convert.ll | 16 +++++++++++ .../CodeGen/Xtensa/xtensa-xtbool-spill.ll | 27 +++++++++++++++++-- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-convert.ll b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-convert.ll index c2428cead69d7e..17eb2b5fefee54 100644 --- a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-convert.ll +++ b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-convert.ll @@ -19,3 +19,19 @@ define i32 @test_xtbool_zext(<1 x i1> %b) { %int = zext i1 %bit to i32 ret i32 %int } + + +define <2 x i1> @test_xtbool2_build(i32 %a, i32 %b) { + ; CHECK-LABEL: test_xtbool2_build: + ; CHECK: slli {{a[0-9]+}}, {{a[0-9]+}}, 1 + ; CHECK: or {{a[0-9]+}}, {{a[0-9]+}}, {{a[0-9]+}} + ; CHECK: rsr [[BREG:a[0-9]+]], br + ; CHECK: and [[AND:a[0-9]+]], {{a[0-9]+}}, {{a[0-9]+}} + ; CHECK: or [[OR:a[0-9]+]], [[AND]], {{a[0-9]+}} + ; CHECK: wsr [[OR]], br + %tobool = icmp ne i32 %a, 0 + %vecinit = insertelement <2 x i1> undef, i1 %tobool, i64 0 + %tobool1 = icmp ne i32 %b, 0 + %vecinit2 = insertelement <2 x i1> %vecinit, i1 %tobool1, i64 1 + ret <2 x i1> %vecinit2 +} diff --git a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll index c1fb9f20870416..3381657d294b90 100644 --- a/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll +++ b/llvm/test/CodeGen/Xtensa/xtensa-xtbool-spill.ll @@ -32,8 +32,7 @@ define <1 x i1> @test_xtbool_load(i32 %addr) { } define void @test_xtbool_store(i32 %addr, <1 x i1> %b) { -entry: - ; CHECK-LABEL: test_xtbool_store + ; CHECK-LABEL: test_xtbool_store: ; CHECK: rsr [[BREG:a[0-9]+]], br ; CHECK: extui [[DST:a[0-9]+]], [[BREG]], 0, 1 ; CHECK: s8i [[DST]], {{a[0-9]+}}, {{[0-9]+}} @@ -42,3 +41,27 @@ entry: store <8 x i1> %insertvec, ptr %ptr, align 1 ret void } +define <2 x i1> @test_xtbool2_load(i32 %addr) { + ; CHECK-LABEL: test_xtbool2_load: + ; CHECK: l8ui {{a[0-9]+}} + ; CHECK: rsr [[BREG:a[0-9]+]], br + ; CHECK: and [[AND:a[0-9]+]], {{a[0-9]+}}, [[BREG]] + ; CHECK: or [[OR:a[0-9]+]], [[AND]], {{a[0-9]+}} + ; CHECK: wsr [[OR]], br + %ptr = inttoptr i32 %addr to ptr + %load_bits = load <8 x i1>, ptr %ptr, align 1 + %extractvec = shufflevector <8 x i1> %load_bits, <8 x i1> poison,<2 x i32> + ret <2 x i1> %extractvec +} + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn writeonly +define void @test_xtbool2_store(i32 %p, <2 x i1> %v) { + ; CHECK-LABEL: test_xtbool2_store: + ; CHECK: rsr [[BREG:a[0-9]+]], br + ; CHECK: extui [[DST:a[0-9]+]], [[BREG]], 0, 2 + ; CHECK: s8i [[DST]], {{a[0-9]+}}, {{[0-9]+}} + %ptr = inttoptr i32 %p to ptr + %insertvec = shufflevector <2 x i1> %v, <2 x i1> poison, <8 x i32> + store <8 x i1> %insertvec, ptr %ptr, align 1 + ret void +} From 0f41383056b365432929c78cf0db9680e8c0d0ae Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:52:19 +0000 Subject: [PATCH 220/261] [Xtensa] Remove unsspported intrinsic xt_conjc_s --- llvm/include/llvm/IR/IntrinsicsXtensa.td | 3 --- 1 file changed, 3 deletions(-) diff --git a/llvm/include/llvm/IR/IntrinsicsXtensa.td b/llvm/include/llvm/IR/IntrinsicsXtensa.td index e805a02f624554..3ac44dba439fb0 100644 --- a/llvm/include/llvm/IR/IntrinsicsXtensa.td +++ b/llvm/include/llvm/IR/IntrinsicsXtensa.td @@ -312,9 +312,6 @@ def int_xtensa_xt_addexpm_s: ClangBuiltin<"__builtin_xtensa_xt_addexpm_s">, def int_xtensa_xt_ceil_s: ClangBuiltin<"__builtin_xtensa_xt_ceil_s">, Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty], [ImmArg>, IntrNoMem]>; -def int_xtensa_xt_conjc_s: ClangBuiltin<"__builtin_xtensa_xt_conjc_s">, - Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty], [IntrNoMem]>; - def int_xtensa_xt_div0_s: ClangBuiltin<"__builtin_xtensa_xt_div0_s">, Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; From cbd147e7a48cf82300598dedbcf5633263948578 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:55:47 +0000 Subject: [PATCH 221/261] [Xtensa] Add HIFI3 intrinsic definitions to clang --- clang/include/clang/Basic/BuiltinsXtensa.def | 1 - .../clang/Basic/BuiltinsXtensaHIFI.def | 2617 +++++++++++++++++ clang/include/clang/Basic/TargetBuiltins.h | 10 +- clang/lib/Basic/Targets/Xtensa.cpp | 2 + 4 files changed, 2625 insertions(+), 5 deletions(-) create mode 100644 clang/include/clang/Basic/BuiltinsXtensaHIFI.def diff --git a/clang/include/clang/Basic/BuiltinsXtensa.def b/clang/include/clang/Basic/BuiltinsXtensa.def index b03e31412ffe61..b87098d79c4557 100644 --- a/clang/include/clang/Basic/BuiltinsXtensa.def +++ b/clang/include/clang/Basic/BuiltinsXtensa.def @@ -286,4 +286,3 @@ BUILTIN(__builtin_xtensa_xt_wur_fsr, "vi", "n") // generated code #include "clang/Basic/BuiltinsXtensaESP32S3.def" -#undef BUILTIN \ No newline at end of file diff --git a/clang/include/clang/Basic/BuiltinsXtensaHIFI.def b/clang/include/clang/Basic/BuiltinsXtensaHIFI.def new file mode 100644 index 00000000000000..d0ac10aeab39b0 --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsXtensaHIFI.def @@ -0,0 +1,2617 @@ +//===-- BuiltinsXtensaHIFI.def - Xtensa HIFI Builtin function database ----*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the builtin function database for Xtensa HIFI extension. Users of +// this file must define the BUILTIN macro to make use of this information. +// +//===----------------------------------------------------------------------===// + +// The format of this database matches clang/Basic/Builtins.def.// ae_int16x4 __builtin_xtensa_ae_abs16s(ae_int16x4 ae_arth_v1) + +// ae_int16x4 __builtin_xtensa_ae_abs16s(ae_int16x4 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_abs16s, "V4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_abs24s(ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_abs24s, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_abs32(ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_abs32, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_abs32s(ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_abs32s, "V2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_abs64(ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_abs64, "V1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_abs64s(ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_abs64s, "V1LLiV1LLi", "n") + +// ae_int16x4 __builtin_xtensa_ae_add16(ae_int16x4 ae_arth_v0,ae_int16x4 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_add16, "V4sV4sV4s", "n") + +// ae_int16x4 __builtin_xtensa_ae_add16s(ae_int16x4 ae_arth_v0,ae_int16x4 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_add16s, "V4sV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_add24s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_add24s, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_add32(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_add32, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_add32_hl_lh(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_add32_hl_lh, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_add32s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_add32s, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_add64(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_add64, "V1LLiV1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_add64s(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_add64s, "V1LLiV1LLiV1LLi", "n") + +// int __builtin_xtensa_ae_addbrba32(int art,int ars) +BUILTIN(__builtin_xtensa_ae_addbrba32, "iii", "n") + +// ae_int32x2 __builtin_xtensa_ae_addsub32(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_addsub32, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_addsub32s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_addsub32s, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_and(ae_int64 ae_dr_to_dr_v0,ae_int64 ae_dr_to_dr_v1) +BUILTIN(__builtin_xtensa_ae_and, "V1LLiV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_cvt32x2f16_10(ae_int16x4 ae_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_cvt32x2f16_10, "V2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_cvt32x2f16_32(ae_int16x4 ae_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_cvt32x2f16_32, "V2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_cvt48a32(int ars) +BUILTIN(__builtin_xtensa_ae_cvt48a32, "V1LLii", "n") + +// ae_int64 __builtin_xtensa_ae_cvt64a32(int ars) +BUILTIN(__builtin_xtensa_ae_cvt64a32, "V1LLii", "n") + +// ae_int64 __builtin_xtensa_ae_cvt64f32_h(ae_int32x2 ae_dr_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_cvt64f32_h, "V1LLiV2i", "n") + +// int __builtin_xtensa_ae_cvta32f24s_h(ae_int32x2 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_cvta32f24s_h, "iV2i", "n") + +// int __builtin_xtensa_ae_cvta32f24s_l(ae_int32x2 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_cvta32f24s_l, "iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_cvtq56a32s(int ars) +BUILTIN(__builtin_xtensa_ae_cvtq56a32s, "V1LLii", "n") + +// ae_int64 __builtin_xtensa_ae_cvtq56p32s_h(ae_int32x2 ae_dr_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_cvtq56p32s_h, "V1LLiV2i", "n") + +// ae_int64 __builtin_xtensa_ae_cvtq56p32s_l(ae_int32x2 ae_dr_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_cvtq56p32s_l, "V1LLiV2i", "n") + +// void __builtin_xtensa_ae_db(const short** ars,int art) +BUILTIN(__builtin_xtensa_ae_db, "vsC**i", "n") + +// void __builtin_xtensa_ae_db_ic(const short** ars,int art) +BUILTIN(__builtin_xtensa_ae_db_ic, "vsC**i", "n") + +// void __builtin_xtensa_ae_db_ip(const short** ars,int art) +BUILTIN(__builtin_xtensa_ae_db_ip, "vsC**i", "n") + +// void __builtin_xtensa_ae_dbi(const short** ars,immediate ae_ohba) +BUILTIN(__builtin_xtensa_ae_dbi, "vsC**i", "n") + +// void __builtin_xtensa_ae_dbi_ic(const short** ars,immediate ae_ohba) +BUILTIN(__builtin_xtensa_ae_dbi_ic, "vsC**i", "n") + +// void __builtin_xtensa_ae_dbi_ip(const short** ars,immediate ae_ohba) +BUILTIN(__builtin_xtensa_ae_dbi_ip, "vsC**i", "n") + +// void __builtin_xtensa_ae_div64d32_h(ae_int64* ae_arth_v,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_div64d32_h, "vV1LLi*V2i", "n") + +// void __builtin_xtensa_ae_div64d32_l(ae_int64* ae_arth_v,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_div64d32_l, "vV1LLi*V2i", "n") + +// xtbool4 __builtin_xtensa_ae_eq16(ae_int16x4 ae_cmpp_v0,ae_int16x4 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_eq16, "V4bV4sV4s", "n") + +// xtbool2 __builtin_xtensa_ae_eq32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_eq32, "V2bV2iV2i", "n") + +// xtbool __builtin_xtensa_ae_eq64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_eq64, "V1bV1LLiV1LLi", "n") + +// ae_int16x4 __builtin_xtensa_ae_l16_i(const ae_int16* ars,immediate ae_immls16) +BUILTIN(__builtin_xtensa_ae_l16_i, "V4sV1sC*i", "n") + +// void __builtin_xtensa_ae_l16_ip(ae_int16x4* ae_ls_v,const ae_int16** ars,immediate ae_immls16) +BUILTIN(__builtin_xtensa_ae_l16_ip, "vV4s*V1sC**i", "n") + +// ae_int16x4 __builtin_xtensa_ae_l16_x(const ae_int16* ars,int art) +BUILTIN(__builtin_xtensa_ae_l16_x, "V4sV1sC*i", "n") + +// void __builtin_xtensa_ae_l16_xc(ae_int16x4* ae_ls_v,const ae_int16** ars,int art) +BUILTIN(__builtin_xtensa_ae_l16_xc, "vV4s*V1sC**i", "n") + +// void __builtin_xtensa_ae_l16_xp(ae_int16x4* ae_ls_v,const ae_int16** ars,int art) +BUILTIN(__builtin_xtensa_ae_l16_xp, "vV4s*V1sC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l16m_i(const ae_int16* ars,immediate ae_immls16) +BUILTIN(__builtin_xtensa_ae_l16m_i, "V2iV1sC*i", "n") + +// void __builtin_xtensa_ae_l16m_iu(ae_int32x2* ae_ls_v,const ae_int16** ars,immediate ae_immls16) +BUILTIN(__builtin_xtensa_ae_l16m_iu, "vV2i*V1sC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l16m_x(const ae_int16* ars,int art) +BUILTIN(__builtin_xtensa_ae_l16m_x, "V2iV1sC*i", "n") + +// void __builtin_xtensa_ae_l16m_xc(ae_int32x2* ae_ls_v,const ae_int16** ars,int art) +BUILTIN(__builtin_xtensa_ae_l16m_xc, "vV2i*V1sC**i", "n") + +// void __builtin_xtensa_ae_l16m_xu(ae_int32x2* ae_ls_v,const ae_int16** ars,int art) +BUILTIN(__builtin_xtensa_ae_l16m_xu, "vV2i*V1sC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l16x2m_i(const ae_int16x2* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_l16x2m_i, "V2iV2sC*i", "n") + +// void __builtin_xtensa_ae_l16x2m_iu(ae_int32x2* ae_ls_v,const ae_int16x2** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_l16x2m_iu, "vV2i*V2sC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l16x2m_x(const ae_int16x2* ars,int art) +BUILTIN(__builtin_xtensa_ae_l16x2m_x, "V2iV2sC*i", "n") + +// void __builtin_xtensa_ae_l16x2m_xc(ae_int32x2* ae_ls_v,const ae_int16x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_l16x2m_xc, "vV2i*V2sC**i", "n") + +// void __builtin_xtensa_ae_l16x2m_xu(ae_int32x2* ae_ls_v,const ae_int16x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_l16x2m_xu, "vV2i*V2sC**i", "n") + +// ae_int16x4 __builtin_xtensa_ae_l16x4_i(const ae_int16x4* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_l16x4_i, "V4sV4sC*i", "n") + +// void __builtin_xtensa_ae_l16x4_ip(ae_int16x4* ae_ls_v,const ae_int16x4** ars,immediate ae_immls64pos) +BUILTIN(__builtin_xtensa_ae_l16x4_ip, "vV4s*V4sC**i", "n") + +// void __builtin_xtensa_ae_l16x4_ric(ae_int16x4* ae_ls_v,const ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_l16x4_ric, "vV4s*V4sC**", "n") + +// void __builtin_xtensa_ae_l16x4_rip(ae_int16x4* ae_ls_v,const ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_l16x4_rip, "vV4s*V4sC**", "n") + +// ae_int16x4 __builtin_xtensa_ae_l16x4_x(const ae_int16x4* ars,int art) +BUILTIN(__builtin_xtensa_ae_l16x4_x, "V4sV4sC*i", "n") + +// void __builtin_xtensa_ae_l16x4_xc(ae_int16x4* ae_ls_v,const ae_int16x4** ars,int art) +BUILTIN(__builtin_xtensa_ae_l16x4_xc, "vV4s*V4sC**i", "n") + +// void __builtin_xtensa_ae_l16x4_xp(ae_int16x4* ae_ls_v,const ae_int16x4** ars,int art) +BUILTIN(__builtin_xtensa_ae_l16x4_xp, "vV4s*V4sC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l32_i(const ae_int32* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_l32_i, "V2iV1iC*i", "n") + +// void __builtin_xtensa_ae_l32_ip(ae_int32x2* ae_ls_v,const ae_int32** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_l32_ip, "vV2i*V1iC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l32_x(const ae_int32* ars,int art) +BUILTIN(__builtin_xtensa_ae_l32_x, "V2iV1iC*i", "n") + +// void __builtin_xtensa_ae_l32_xc(ae_int32x2* ae_ls_v,const ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32_xc, "vV2i*V1iC**i", "n") + +// void __builtin_xtensa_ae_l32_xp(ae_int32x2* ae_ls_v,const ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32_xp, "vV2i*V1iC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l32f24_i(const ae_int32* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_l32f24_i, "V2iV1iC*i", "n") + +// void __builtin_xtensa_ae_l32f24_ip(ae_int32x2* ae_ls_v,const ae_int32** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_l32f24_ip, "vV2i*V1iC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l32f24_x(const ae_int32* ars,int art) +BUILTIN(__builtin_xtensa_ae_l32f24_x, "V2iV1iC*i", "n") + +// void __builtin_xtensa_ae_l32f24_xc(ae_int32x2* ae_ls_v,const ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32f24_xc, "vV2i*V1iC**i", "n") + +// void __builtin_xtensa_ae_l32f24_xp(ae_int32x2* ae_ls_v,const ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32f24_xp, "vV2i*V1iC**i", "n") + +// ae_int64 __builtin_xtensa_ae_l32m_i(const ae_int32* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_l32m_i, "V1LLiV1iC*i", "n") + +// void __builtin_xtensa_ae_l32m_iu(ae_int64* ae_ls_v,const ae_int32** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_l32m_iu, "vV1LLi*V1iC**i", "n") + +// ae_int64 __builtin_xtensa_ae_l32m_x(const ae_int32* ars,int art) +BUILTIN(__builtin_xtensa_ae_l32m_x, "V1LLiV1iC*i", "n") + +// void __builtin_xtensa_ae_l32m_xc(ae_int64* ae_ls_v,const ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32m_xc, "vV1LLi*V1iC**i", "n") + +// void __builtin_xtensa_ae_l32m_xu(ae_int64* ae_ls_v,const ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32m_xu, "vV1LLi*V1iC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l32x2_i(const ae_int32x2* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_l32x2_i, "V2iV2iC*i", "n") + +// void __builtin_xtensa_ae_l32x2_ip(ae_int32x2* ae_ls_v,const ae_int32x2** ars,immediate ae_immls64pos) +BUILTIN(__builtin_xtensa_ae_l32x2_ip, "vV2i*V2iC**i", "n") + +// void __builtin_xtensa_ae_l32x2_ric(ae_int32x2* ae_ls_v,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_l32x2_ric, "vV2i*V2iC**", "n") + +// void __builtin_xtensa_ae_l32x2_rip(ae_int32x2* ae_ls_v,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_l32x2_rip, "vV2i*V2iC**", "n") + +// ae_int32x2 __builtin_xtensa_ae_l32x2_x(const ae_int32x2* ars,int art) +BUILTIN(__builtin_xtensa_ae_l32x2_x, "V2iV2iC*i", "n") + +// void __builtin_xtensa_ae_l32x2_xc(ae_int32x2* ae_ls_v,const ae_int32x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32x2_xc, "vV2i*V2iC**i", "n") + +// void __builtin_xtensa_ae_l32x2_xp(ae_int32x2* ae_ls_v,const ae_int32x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32x2_xp, "vV2i*V2iC**i", "n") + +// ae_int32x2 __builtin_xtensa_ae_l32x2f24_i(const ae_int32x2* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_l32x2f24_i, "V2iV2iC*i", "n") + +// void __builtin_xtensa_ae_l32x2f24_ip(ae_int32x2* ae_ls_v,const ae_int32x2** ars,immediate ae_immls64pos) +BUILTIN(__builtin_xtensa_ae_l32x2f24_ip, "vV2i*V2iC**i", "n") + +// void __builtin_xtensa_ae_l32x2f24_ric(ae_int32x2* ae_ls_v,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_l32x2f24_ric, "vV2i*V2iC**", "n") + +// void __builtin_xtensa_ae_l32x2f24_rip(ae_int32x2* ae_ls_v,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_l32x2f24_rip, "vV2i*V2iC**", "n") + +// ae_int32x2 __builtin_xtensa_ae_l32x2f24_x(const ae_int32x2* ars,int art) +BUILTIN(__builtin_xtensa_ae_l32x2f24_x, "V2iV2iC*i", "n") + +// void __builtin_xtensa_ae_l32x2f24_xc(ae_int32x2* ae_ls_v,const ae_int32x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32x2f24_xc, "vV2i*V2iC**i", "n") + +// void __builtin_xtensa_ae_l32x2f24_xp(ae_int32x2* ae_ls_v,const ae_int32x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_l32x2f24_xp, "vV2i*V2iC**i", "n") + +// ae_int64 __builtin_xtensa_ae_l64_i(const ae_int64* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_l64_i, "V1LLiV1LLiC*i", "n") + +// void __builtin_xtensa_ae_l64_ip(ae_int64* ae_ls_v,const ae_int64** ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_l64_ip, "vV1LLi*V1LLiC**i", "n") + +// ae_int64 __builtin_xtensa_ae_l64_x(const ae_int64* ars,int art) +BUILTIN(__builtin_xtensa_ae_l64_x, "V1LLiV1LLiC*i", "n") + +// void __builtin_xtensa_ae_l64_xc(ae_int64* ae_ls_v,const ae_int64** ars,int art) +BUILTIN(__builtin_xtensa_ae_l64_xc, "vV1LLi*V1LLiC**i", "n") + +// void __builtin_xtensa_ae_l64_xp(ae_int64* ae_ls_v,const ae_int64** ars,int art) +BUILTIN(__builtin_xtensa_ae_l64_xp, "vV1LLi*V1LLiC**i", "n") + +// void __builtin_xtensa_ae_la16x4_ic(ae_int16x4* ae_ls_av,ae_valign* ae_ls_uu,const ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_la16x4_ic, "vV4s*V8Uc*V4sC**", "n") + +// void __builtin_xtensa_ae_la16x4_ip(ae_int16x4* ae_ls_av,ae_valign* ae_ls_uu,const ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_la16x4_ip, "vV4s*V8Uc*V4sC**", "n") + +// void __builtin_xtensa_ae_la16x4_ric(ae_int16x4* ae_ls_av,ae_valign* ae_ls_uu,const ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_la16x4_ric, "vV4s*V8Uc*V4sC**", "n") + +// void __builtin_xtensa_ae_la16x4_rip(ae_int16x4* ae_ls_av,ae_valign* ae_ls_uu,const ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_la16x4_rip, "vV4s*V8Uc*V4sC**", "n") + +// void __builtin_xtensa_ae_la16x4neg_pc(ae_valign* ae_ls_uu,const ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_la16x4neg_pc, "vV8Uc*V4sC**", "n") + +// void __builtin_xtensa_ae_la16x4pos_pc(ae_valign* ae_ls_uu,const ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_la16x4pos_pc, "vV8Uc*V4sC**", "n") + +// void __builtin_xtensa_ae_la24_ic(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24_ic, "vV2i*V8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24_ip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24_ip, "vV2i*V8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24_ric(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24_ric, "vV2i*V8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24_rip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24_rip, "vV2i*V8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24neg_pc(ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24neg_pc, "vV8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24pos_pc(ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24pos_pc, "vV8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24x2_ic(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24x2_ic, "vV2i*V8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24x2_ip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24x2_ip, "vV2i*V8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24x2_ric(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24x2_ric, "vV2i*V8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24x2_rip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24x2_rip, "vV2i*V8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24x2neg_pc(ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24x2neg_pc, "vV8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la24x2pos_pc(ae_valign* ae_ls_uu,const void** ars) +BUILTIN(__builtin_xtensa_ae_la24x2pos_pc, "vV8Uc*vC**", "n") + +// void __builtin_xtensa_ae_la32x2_ic(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2_ic, "vV2i*V8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2_ip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2_ip, "vV2i*V8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2_ric(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2_ric, "vV2i*V8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2_rip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2_rip, "vV2i*V8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2f24_ic(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2f24_ic, "vV2i*V8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2f24_ip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2f24_ip, "vV2i*V8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2f24_ric(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2f24_ric, "vV2i*V8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2f24_rip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2f24_rip, "vV2i*V8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2neg_pc(ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2neg_pc, "vV8Uc*V2iC**", "n") + +// void __builtin_xtensa_ae_la32x2pos_pc(ae_valign* ae_ls_uu,const ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_la32x2pos_pc, "vV8Uc*V2iC**", "n") + +// ae_valign __builtin_xtensa_ae_la64_pp(const void* ars) +BUILTIN(__builtin_xtensa_ae_la64_pp, "V8UcvC*", "n") + +// ae_valign __builtin_xtensa_ae_lalign64_i(const ae_valign* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_lalign64_i, "V8UcV8UcC*i", "n") + +// int __builtin_xtensa_ae_lb(int art) +BUILTIN(__builtin_xtensa_ae_lb, "ii", "n") + +// int __builtin_xtensa_ae_lbi(immediate ae_ohba) +BUILTIN(__builtin_xtensa_ae_lbi, "ii", "n") + +// int __builtin_xtensa_ae_lbk(int ars,int art) +BUILTIN(__builtin_xtensa_ae_lbk, "iii", "n") + +// int __builtin_xtensa_ae_lbki(int ars,immediate ae_ohba) +BUILTIN(__builtin_xtensa_ae_lbki, "iii", "n") + +// int __builtin_xtensa_ae_lbs(int art) +BUILTIN(__builtin_xtensa_ae_lbs, "ii", "n") + +// int __builtin_xtensa_ae_lbsi(immediate ae_ohba) +BUILTIN(__builtin_xtensa_ae_lbsi, "ii", "n") + +// xtbool4 __builtin_xtensa_ae_le16(ae_int16x4 ae_cmpp_v0,ae_int16x4 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_le16, "V4bV4sV4s", "n") + +// xtbool2 __builtin_xtensa_ae_le32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_le32, "V2bV2iV2i", "n") + +// xtbool __builtin_xtensa_ae_le64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_le64, "V1bV1LLiV1LLi", "n") + +// xtbool4 __builtin_xtensa_ae_lt16(ae_int16x4 ae_cmpp_v0,ae_int16x4 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_lt16, "V4bV4sV4s", "n") + +// xtbool2 __builtin_xtensa_ae_lt32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_lt32, "V2bV2iV2i", "n") + +// xtbool __builtin_xtensa_ae_lt64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_lt64, "V1bV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_max32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_max32, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_max64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_max64, "V1LLiV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_maxabs32s(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_maxabs32s, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_maxabs64s(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_maxabs64s, "V1LLiV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_min32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_min32, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_min64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_min64, "V1LLiV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_minabs32s(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_minabs32s, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_minabs64s(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) +BUILTIN(__builtin_xtensa_ae_minabs64s, "V1LLiV1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_mov(ae_int64 ae_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_mov, "V1LLiV1LLi", "n") + +// int __builtin_xtensa_ae_movad16_0(ae_int16x4 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_movad16_0, "iV4s", "n") + +// int __builtin_xtensa_ae_movad16_1(ae_int16x4 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_movad16_1, "iV4s", "n") + +// int __builtin_xtensa_ae_movad16_2(ae_int16x4 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_movad16_2, "iV4s", "n") + +// int __builtin_xtensa_ae_movad16_3(ae_int16x4 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_movad16_3, "iV4s", "n") + +// int __builtin_xtensa_ae_movad32_h(ae_int32x2 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_movad32_h, "iV2i", "n") + +// int __builtin_xtensa_ae_movad32_l(ae_int32x2 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_movad32_l, "iV2i", "n") + +// ae_valign __builtin_xtensa_ae_movalign(ae_valign ae_uu_v) +BUILTIN(__builtin_xtensa_ae_movalign, "V8UcV8Uc", "n") + +// ae_int16x4 __builtin_xtensa_ae_movda16(int ars) +BUILTIN(__builtin_xtensa_ae_movda16, "V4si", "n") + +// ae_int16x4 __builtin_xtensa_ae_movda16x2(int ars,int art) +BUILTIN(__builtin_xtensa_ae_movda16x2, "V4sii", "n") + +// ae_int32 __builtin_xtensa_ae_movda32(int ars) +BUILTIN(__builtin_xtensa_ae_movda32, "V1ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_movda32x2(int ars,int art) +BUILTIN(__builtin_xtensa_ae_movda32x2, "V2iii", "n") + +// void __builtin_xtensa_ae_movf16x4(ae_int16x4* ae_cmov_v,ae_int16x4 ae_cmov_v0,xtbool4 bt4) +BUILTIN(__builtin_xtensa_ae_movf16x4, "vV4s*V4sV4b", "n") + +// void __builtin_xtensa_ae_movf32x2(ae_int32x2* ae_cmov_v,ae_int32x2 ae_cmov_v0,xtbool2 bt2) +BUILTIN(__builtin_xtensa_ae_movf32x2, "vV2i*V2iV2b", "n") + +// void __builtin_xtensa_ae_movf64(ae_int64* ae_cmov_v,ae_int64 ae_cmov_v0,xtbool bt) +BUILTIN(__builtin_xtensa_ae_movf64, "vV1LLi*V1LLiV1b", "n") + +// ae_int32x2 __builtin_xtensa_ae_movi(immediate movi_imm) +BUILTIN(__builtin_xtensa_ae_movi, "V2ii", "n") + +// void __builtin_xtensa_ae_movt16x4(ae_int16x4* ae_cmov_v,ae_int16x4 ae_cmov_v0,xtbool4 bt4) +BUILTIN(__builtin_xtensa_ae_movt16x4, "vV4s*V4sV4b", "n") + +// void __builtin_xtensa_ae_movt32x2(ae_int32x2* ae_cmov_v,ae_int32x2 ae_cmov_v0,xtbool2 bt2) +BUILTIN(__builtin_xtensa_ae_movt32x2, "vV2i*V2iV2b", "n") + +// void __builtin_xtensa_ae_movt64(ae_int64* ae_cmov_v,ae_int64 ae_cmov_v0,xtbool bt) +BUILTIN(__builtin_xtensa_ae_movt64, "vV1LLi*V1LLiV1b", "n") + +// void __builtin_xtensa_ae_mul16x4(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) +BUILTIN(__builtin_xtensa_ae_mul16x4, "vV2i*V2i*V4sV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32_hh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32_hh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mul32_lh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mul32_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mul32_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mul32u_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32u_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_h0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_h0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_h0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_h0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_h1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_h1, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_h1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_h1_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_h2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_h2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_h2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_h2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_h3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_h3, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_h3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_h3_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_l1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_l1, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_l1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_l1_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_l3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_l3, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mul32x16_l3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mul32x16_l3_s2, "V1LLiV2iV4s", "n") + +// void __builtin_xtensa_ae_mula16x4(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) +BUILTIN(__builtin_xtensa_ae_mula16x4, "vV2i*V2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mula32_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32_hh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mula32_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mula32_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mula32_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mula32u_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32u_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mula32x16_h0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_h0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_h0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_h0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_h1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_h1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_h1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_h1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_h2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_h2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_h2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_h2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_h3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_h3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_h3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_h3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_l1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_l1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_l3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mula32x16_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mula32x16_l3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaad24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaad24_hh_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaad24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaad24_hh_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaad24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaad24_hl_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaad24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaad24_hl_lh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaad32x16_h0_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaad32x16_h0_l1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaad32x16_h0_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaad32x16_h0_l1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaad32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaad32x16_h1_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaad32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaad32x16_h1_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaad32x16_h2_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaad32x16_h2_l3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaad32x16_h2_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaad32x16_h2_l3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaad32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaad32x16_h3_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaad32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaad32x16_h3_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaafd16ss_11_00(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd16ss_11_00, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaafd16ss_11_00_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd16ss_11_00_s2, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaafd16ss_13_02(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd16ss_13_02, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaafd16ss_13_02_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd16ss_13_02_s2, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaafd16ss_33_22(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd16ss_33_22, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaafd16ss_33_22_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd16ss_33_22_s2, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaafd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd24_hh_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaafd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd24_hh_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaafd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd24_hl_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaafd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd24_hl_lh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaafd32x16_h0_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd32x16_h0_l1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaafd32x16_h0_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd32x16_h0_l1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaafd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd32x16_h1_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaafd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd32x16_h1_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaafd32x16_h2_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd32x16_h2_l3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaafd32x16_h2_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd32x16_h2_l3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaafd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd32x16_h3_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaafd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaafd32x16_h3_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulac24(ae_int32x2* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulac24, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulac32x16_h(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulac32x16_h, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulac32x16_l(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulac32x16_l, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_00(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_00, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_00_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_00_s2, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_10(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_10, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_11(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_11, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_20(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_20, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_21(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_21, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_22(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_22, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_30(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_30, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_31(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_31, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_32(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_32, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16ss_33(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulaf16ss_33, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf16x4ss(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) +BUILTIN(__builtin_xtensa_ae_mulaf16x4ss, "vV2i*V2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulaf32r_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32r_hh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaf32r_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32r_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaf32r_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32r_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaf32r_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32r_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaf32s_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32s_hh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaf32s_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32s_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaf32s_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32s_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaf32s_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32s_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaf32x16_h0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_h0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_h0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_h0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_h1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_h1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_h1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_h1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_h2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_h2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_h2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_h2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_h3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_h3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_h3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_h3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_l1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_l1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_l3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf32x16_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf32x16_l3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulaf48q32sp16s_l(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf48q32sp16s_l, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulaf48q32sp16s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf48q32sp16s_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulaf48q32sp16u_l(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulaf48q32sp16u_l, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulaf48q32sp16u_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaf48q32sp16u_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulafc24ra(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int32x2 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulafc24ra, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulafc32x16ras_h(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulafc32x16ras_h, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafc32x16ras_l(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulafc32x16ras_l, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafd24x2_fir_h(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int32x2 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulafd24x2_fir_h, "vV1LLi*V1LLi*V2iV2iV2i", "n") + +// void __builtin_xtensa_ae_mulafd24x2_fir_l(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int32x2 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulafd24x2_fir_l, "vV1LLi*V1LLi*V2iV2iV2i", "n") + +// void __builtin_xtensa_ae_mulafd32x16x2_fir_hh(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulafd32x16x2_fir_hh, "vV1LLi*V1LLi*V2iV2iV4s", "n") + +// void __builtin_xtensa_ae_mulafd32x16x2_fir_hl(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulafd32x16x2_fir_hl, "vV1LLi*V1LLi*V2iV2iV4s", "n") + +// void __builtin_xtensa_ae_mulafd32x16x2_fir_lh(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulafd32x16x2_fir_lh, "vV1LLi*V1LLi*V2iV2iV4s", "n") + +// void __builtin_xtensa_ae_mulafd32x16x2_fir_ll(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulafd32x16x2_fir_ll, "vV1LLi*V1LLi*V2iV2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp24x2r(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulafp24x2r, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulafp24x2r_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulafp24x2r_s2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulafp24x2ra(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulafp24x2ra, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulafp24x2ra_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulafp24x2ra_s2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulafp32x16x2ras_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x16x2ras_h, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp32x16x2ras_h_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x16x2ras_h_s2, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp32x16x2ras_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x16x2ras_l, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp32x16x2ras_l_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x16x2ras_l_s2, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp32x16x2rs_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x16x2rs_h, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp32x16x2rs_h_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x16x2rs_h_s2, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp32x16x2rs_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x16x2rs_l, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp32x16x2rs_l_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x16x2rs_l_s2, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulafp32x2ras(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x2ras, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulafp32x2rs(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulafp32x2rs, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulafq32sp24s_h_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulafq32sp24s_h_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulafq32sp24s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulafq32sp24s_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulap24x2(ae_int32x2* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulap24x2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulap24x2_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulap24x2_s2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulap32x16x2_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulap32x16x2_h, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulap32x16x2_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulap32x16x2_l, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulap32x2(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulap32x2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulaq32sp16s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaq32sp16s_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulaq32sp16u_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulaq32sp16u_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mularfq32sp24s_h_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mularfq32sp24s_h_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mularfq32sp24s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mularfq32sp24s_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulas32f48p16s_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulas32f48p16s_hh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulas32f48p16s_hh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulas32f48p16s_hh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulas32f48p16s_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulas32f48p16s_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulas32f48p16s_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulas32f48p16s_lh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulas32f48p16s_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulas32f48p16s_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulas32f48p16s_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulas32f48p16s_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulasd24_hh_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulasd24_hh_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulasd24_hl_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulasd24_hl_lh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulasd32x16_h1_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulasd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulasd32x16_h1_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulasd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulasd32x16_h3_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulasd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulasd32x16_h3_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulasfd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulasfd24_hh_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasfd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulasfd24_hh_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasfd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulasfd24_hl_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasfd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulasfd24_hl_lh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulasfd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulasfd32x16_h1_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulasfd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulasfd32x16_h1_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulasfd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulasfd32x16_h3_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulasfd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulasfd32x16_h3_l2_s2, "vV1LLi*V2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulc24(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulc24, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulc32x16_h(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulc32x16_h, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulc32x16_l(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulc32x16_l, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_00(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_00, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_00_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_00_s2, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_10(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_10, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_11(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_11, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_20(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_20, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_21(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_21, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_22(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_22, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_30(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_30, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_31(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_31, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_32(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_32, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulf16ss_33(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulf16ss_33, "V2iV4sV4s", "n") + +// void __builtin_xtensa_ae_mulf16x4ss(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) +BUILTIN(__builtin_xtensa_ae_mulf16x4ss, "vV2i*V2i*V4sV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32r_hh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32r_hh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32r_lh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32r_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32r_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32r_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32r_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32r_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32s_hh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32s_hh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32s_lh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32s_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32s_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32s_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32s_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32s_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_h0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_h0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_h0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_h0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_h1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_h1, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_h1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_h1_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_h2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_h2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_h2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_h2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_h3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_h3, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_h3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_h3_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_l1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_l1, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_l1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_l1_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_l3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_l3, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf32x16_l3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf32x16_l3_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulf48q32sp16s_l(ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf48q32sp16s_l, "V1LLiV1LLiV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf48q32sp16s_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf48q32sp16s_l_s2, "V1LLiV1LLiV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf48q32sp16u_l(ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulf48q32sp16u_l, "V1LLiV1LLiV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulf48q32sp16u_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulf48q32sp16u_l_s2, "V1LLiV1LLiV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfc24ra(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int32x2 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulfc24ra, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfc32x16ras_h(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulfc32x16ras_h, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfc32x16ras_l(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) +BUILTIN(__builtin_xtensa_ae_mulfc32x16ras_l, "V2iV2iV4s", "n") + +// void __builtin_xtensa_ae_mulfd24x2_fir_h(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int32x2 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulfd24x2_fir_h, "vV1LLi*V1LLi*V2iV2iV2i", "n") + +// void __builtin_xtensa_ae_mulfd24x2_fir_l(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int32x2 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulfd24x2_fir_l, "vV1LLi*V1LLi*V2iV2iV2i", "n") + +// void __builtin_xtensa_ae_mulfd32x16x2_fir_hh(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulfd32x16x2_fir_hh, "vV1LLi*V1LLi*V2iV2iV4s", "n") + +// void __builtin_xtensa_ae_mulfd32x16x2_fir_hl(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulfd32x16x2_fir_hl, "vV1LLi*V1LLi*V2iV2iV4s", "n") + +// void __builtin_xtensa_ae_mulfd32x16x2_fir_lh(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulfd32x16x2_fir_lh, "vV1LLi*V1LLi*V2iV2iV4s", "n") + +// void __builtin_xtensa_ae_mulfd32x16x2_fir_ll(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) +BUILTIN(__builtin_xtensa_ae_mulfd32x16x2_fir_ll, "vV1LLi*V1LLi*V2iV2iV4s", "n") + +// ae_int16x4 __builtin_xtensa_ae_mulfp16x4ras(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulfp16x4ras, "V4sV4sV4s", "n") + +// ae_int16x4 __builtin_xtensa_ae_mulfp16x4s(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulfp16x4s, "V4sV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp24x2r(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulfp24x2r, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp24x2r_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulfp24x2r_s2, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp24x2ra(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulfp24x2ra, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp24x2ra_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulfp24x2ra_s2, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x16x2ras_h(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x16x2ras_h, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x16x2ras_h_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x16x2ras_h_s2, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x16x2ras_l(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x16x2ras_l, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x16x2ras_l_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x16x2ras_l_s2, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x16x2rs_h(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x16x2rs_h, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x16x2rs_h_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x16x2rs_h_s2, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x16x2rs_l(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x16x2rs_l, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x16x2rs_l_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x16x2rs_l_s2, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x2ras(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x2ras, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulfp32x2rs(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulfp32x2rs, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulfq32sp24s_h_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulfq32sp24s_h_s2, "V1LLiV1LLiV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulfq32sp24s_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulfq32sp24s_l_s2, "V1LLiV1LLiV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulp24x2(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulp24x2, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulp24x2_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulp24x2_s2, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulp32x16x2_h(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulp32x16x2_h, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulp32x16x2_l(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulp32x16x2_l, "V2iV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulp32x2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulp32x2, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulq32sp16s_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulq32sp16s_l_s2, "V1LLiV1LLiV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulq32sp16u_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulq32sp16u_l_s2, "V1LLiV1LLiV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulrfq32sp24s_h_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulrfq32sp24s_h_s2, "V1LLiV1LLiV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulrfq32sp24s_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulrfq32sp24s_l_s2, "V1LLiV1LLiV2i", "n") + +// void __builtin_xtensa_ae_muls16x4(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) +BUILTIN(__builtin_xtensa_ae_muls16x4, "vV2i*V2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_muls32_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32_hh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_muls32_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_muls32_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32_ll, "vV1LLi*V2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_muls32f48p16s_hh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32f48p16s_hh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_muls32f48p16s_hh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32f48p16s_hh_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_muls32f48p16s_lh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32f48p16s_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_muls32f48p16s_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32f48p16s_lh_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_muls32f48p16s_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32f48p16s_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_muls32f48p16s_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32f48p16s_ll_s2, "V1LLiV2iV2i", "n") + +// void __builtin_xtensa_ae_muls32u_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32u_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_muls32x16_h0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_h0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_h0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_h0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_h1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_h1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_h1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_h1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_h2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_h2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_h2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_h2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_h3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_h3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_h3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_h3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_l1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_l1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_l3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_muls32x16_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_muls32x16_l3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsad24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsad24_hh_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsad24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsad24_hh_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsad32x16_h1_l0(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsad32x16_h1_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsad32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsad32x16_h1_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsad32x16_h3_l2(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsad32x16_h3_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsad32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsad32x16_h3_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsafd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsafd24_hh_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsafd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsafd24_hh_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsafd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsafd32x16_h1_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsafd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsafd32x16_h1_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsafd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsafd32x16_h3_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsafd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsafd32x16_h3_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_00(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_00, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_00_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_00_s2, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_10(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_10, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_11(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_11, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_20(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_20, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_21(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_21, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_22(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_22, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_30(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_30, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_31(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_31, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_32(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_32, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16ss_33(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsf16ss_33, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf16x4ss(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) +BUILTIN(__builtin_xtensa_ae_mulsf16x4ss, "vV2i*V2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulsf32r_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32r_hh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsf32r_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32r_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsf32r_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32r_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsf32r_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32r_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsf32s_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32s_hh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsf32s_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32s_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsf32s_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32s_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsf32x16_h0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_h0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_h0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_h0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_h1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_h1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_h1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_h1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_h2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_h2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_h2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_h2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_h3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_h3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_h3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_h3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_l1, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_l1_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_l3, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf32x16_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf32x16_l3_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsf48q32sp16s_l(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf48q32sp16s_l, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsf48q32sp16s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf48q32sp16s_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsf48q32sp16u_l(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsf48q32sp16u_l, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsf48q32sp16u_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsf48q32sp16u_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsfp24x2r(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp24x2r, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsfp24x2r_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp24x2r_s2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsfp24x2ra(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp24x2ra, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsfp24x2ra_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp24x2ra_s2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsfp32x16x2ras_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x16x2ras_h, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsfp32x16x2ras_h_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x16x2ras_h_s2, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsfp32x16x2ras_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x16x2ras_l, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsfp32x16x2ras_l_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x16x2ras_l_s2, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsfp32x16x2rs_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x16x2rs_h, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsfp32x16x2rs_h_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x16x2rs_h_s2, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsfp32x16x2rs_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x16x2rs_l, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsfp32x16x2rs_l_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x16x2rs_l_s2, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsfp32x2ras(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x2ras, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsfp32x2rs(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsfp32x2rs, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsfq32sp24s_h_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsfq32sp24s_h_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsfq32sp24s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsfq32sp24s_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsp24x2(ae_int32x2* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulsp24x2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsp24x2_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsp24x2_s2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsp32x16x2_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsp32x16x2_h, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsp32x16x2_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsp32x16x2_l, "vV2i*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulsp32x2(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulsp32x2, "vV2i*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulsq32sp16s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsq32sp16s_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsq32sp16u_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsq32sp16u_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsrfq32sp24s_h_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsrfq32sp24s_h_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulsrfq32sp24s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulsrfq32sp24s_l_s2, "vV1LLi*V1LLiV2i", "n") + +// void __builtin_xtensa_ae_mulss32f48p16s_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulss32f48p16s_hh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulss32f48p16s_hh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulss32f48p16s_hh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulss32f48p16s_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulss32f48p16s_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulss32f48p16s_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulss32f48p16s_lh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulss32f48p16s_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulss32f48p16s_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulss32f48p16s_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulss32f48p16s_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulssd24_hh_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssd24_hh_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulssd24_hl_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssd24_hl_lh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulssd32x16_h1_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulssd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssd32x16_h1_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulssd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulssd32x16_h3_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulssd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssd32x16_h3_l2_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulssfd16ss_11_00(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd16ss_11_00, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulssfd16ss_11_00_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd16ss_11_00_s2, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulssfd16ss_13_02(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd16ss_13_02, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulssfd16ss_13_02_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd16ss_13_02_s2, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulssfd16ss_33_22(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd16ss_33_22, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulssfd16ss_33_22_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd16ss_33_22_s2, "vV2i*V4sV4s", "n") + +// void __builtin_xtensa_ae_mulssfd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd24_hh_ll, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssfd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd24_hh_ll_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssfd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd24_hl_lh, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssfd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd24_hl_lh_s2, "vV1LLi*V2iV2i", "n") + +// void __builtin_xtensa_ae_mulssfd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd32x16_h1_l0, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulssfd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd32x16_h1_l0_s2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulssfd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd32x16_h3_l2, "vV1LLi*V2iV4s", "n") + +// void __builtin_xtensa_ae_mulssfd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulssfd32x16_h3_l2_s2, "vV1LLi*V2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad24_hh_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad24_hh_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad24_hl_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad24_hl_lh_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad32x16_h0_l1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad32x16_h0_l1, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad32x16_h0_l1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad32x16_h0_l1_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad32x16_h1_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad32x16_h1_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad32x16_h2_l3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad32x16_h2_l3, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad32x16_h2_l3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad32x16_h2_l3_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad32x16_h3_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaad32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaad32x16_h3_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzaafd16ss_11_00(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd16ss_11_00, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzaafd16ss_11_00_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd16ss_11_00_s2, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzaafd16ss_13_02(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd16ss_13_02, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzaafd16ss_13_02_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd16ss_13_02_s2, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzaafd16ss_33_22(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd16ss_33_22, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzaafd16ss_33_22_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd16ss_33_22_s2, "V2iV4sV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd24_hh_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd24_hh_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd24_hl_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd24_hl_lh_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd32x16_h0_l1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd32x16_h0_l1, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd32x16_h0_l1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd32x16_h0_l1_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd32x16_h1_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd32x16_h1_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd32x16_h2_l3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd32x16_h2_l3, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd32x16_h2_l3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd32x16_h2_l3_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd32x16_h3_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzaafd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzaafd32x16_h3_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzasd24_hh_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzasd24_hh_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzasd24_hl_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzasd24_hl_lh_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzasd32x16_h1_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzasd32x16_h1_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzasd32x16_h3_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzasd32x16_h3_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasfd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzasfd24_hh_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasfd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzasfd24_hh_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasfd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzasfd24_hl_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasfd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzasfd24_hl_lh_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasfd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzasfd32x16_h1_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasfd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzasfd32x16_h1_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasfd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzasfd32x16_h3_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzasfd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzasfd32x16_h3_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsad24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzsad24_hh_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsad24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzsad24_hh_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsad32x16_h1_l0(ae_int32x2 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzsad32x16_h1_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsad32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzsad32x16_h1_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsad32x16_h3_l2(ae_int32x2 ae_mul_d0,ae_int16x4 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzsad32x16_h3_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsad32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzsad32x16_h3_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsafd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzsafd24_hh_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsafd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzsafd24_hh_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsafd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzsafd32x16_h1_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsafd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzsafd32x16_h1_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsafd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzsafd32x16_h3_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzsafd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzsafd32x16_h3_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzssd24_hh_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssd24_hh_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzssd24_hl_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssd24_hl_lh_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzssd32x16_h1_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssd32x16_h1_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzssd32x16_h3_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssd32x16_h3_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzssfd16ss_11_00(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd16ss_11_00, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzssfd16ss_11_00_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd16ss_11_00_s2, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzssfd16ss_13_02(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd16ss_13_02, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzssfd16ss_13_02_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd16ss_13_02_s2, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzssfd16ss_33_22(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd16ss_33_22, "V2iV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_mulzssfd16ss_33_22_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd16ss_33_22_s2, "V2iV4sV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssfd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd24_hh_ll, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssfd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd24_hh_ll_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssfd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd24_hl_lh, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssfd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd24_hl_lh_s2, "V1LLiV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssfd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd32x16_h1_l0, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssfd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd32x16_h1_l0_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssfd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd32x16_h3_l2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_mulzssfd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) +BUILTIN(__builtin_xtensa_ae_mulzssfd32x16_h3_l2_s2, "V1LLiV2iV4s", "n") + +// ae_int64 __builtin_xtensa_ae_nand(ae_int64 ae_dr_to_dr_v0,ae_int64 ae_dr_to_dr_v1) +BUILTIN(__builtin_xtensa_ae_nand, "V1LLiV1LLiV1LLi", "n") + +// ae_int16x4 __builtin_xtensa_ae_neg16s(ae_int16x4 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_neg16s, "V4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_neg24s(ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_neg24s, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_neg32(ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_neg32, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_neg32s(ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_neg32s, "V2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_neg64(ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_neg64, "V1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_neg64s(ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_neg64s, "V1LLiV1LLi", "n") + +// int __builtin_xtensa_ae_nsa64(ae_int64 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_nsa64, "iV1LLi", "n") + +// int __builtin_xtensa_ae_nsaz16_0(ae_int16x4 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_nsaz16_0, "iV4s", "n") + +// int __builtin_xtensa_ae_nsaz32_l(ae_int32x2 ae_dr_to_ar_v0) +BUILTIN(__builtin_xtensa_ae_nsaz32_l, "iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_or(ae_int64 ae_dr_to_dr_v0,ae_int64 ae_dr_to_dr_v1) +BUILTIN(__builtin_xtensa_ae_or, "V1LLiV1LLiV1LLi", "n") + +// void __builtin_xtensa_ae_pksr24(ae_int32x2* ae_pks_d,ae_int64 ae_pks_s,immediate ae_imm2) +BUILTIN(__builtin_xtensa_ae_pksr24, "vV2i*V1LLii", "n") + +// void __builtin_xtensa_ae_pksr32(ae_int32x2* ae_pks_d,ae_int64 ae_pks_s,immediate ae_imm2) +BUILTIN(__builtin_xtensa_ae_pksr32, "vV2i*V1LLii", "n") + +// ae_int16x4 __builtin_xtensa_ae_round16x4f32sasym(ae_int32x2 ae_arth_v1,ae_int32x2 ae_arth_v0) +BUILTIN(__builtin_xtensa_ae_round16x4f32sasym, "V4sV2iV2i", "n") + +// ae_int16x4 __builtin_xtensa_ae_round16x4f32ssym(ae_int32x2 ae_arth_v1,ae_int32x2 ae_arth_v0) +BUILTIN(__builtin_xtensa_ae_round16x4f32ssym, "V4sV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_round24x2f48sasym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_round24x2f48sasym, "V2iV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_round24x2f48ssym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_round24x2f48ssym, "V2iV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_round32x2f48sasym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_round32x2f48sasym, "V2iV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_round32x2f48ssym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_round32x2f48ssym, "V2iV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_round32x2f64sasym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_round32x2f64sasym, "V2iV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_round32x2f64ssym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_round32x2f64ssym, "V2iV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_roundsp16f24asym(ae_int32x2 ae_arth_v0) +BUILTIN(__builtin_xtensa_ae_roundsp16f24asym, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_roundsp16f24sym(ae_int32x2 ae_arth_v0) +BUILTIN(__builtin_xtensa_ae_roundsp16f24sym, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_roundsp16q48x2asym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_roundsp16q48x2asym, "V2iV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_roundsp16q48x2sym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_roundsp16q48x2sym, "V2iV1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_roundsq32f48asym(ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_roundsq32f48asym, "V1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_roundsq32f48sym(ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_roundsq32f48sym, "V1LLiV1LLi", "n") + +// void __builtin_xtensa_ae_s16_0_i(ae_int16x4 ae_ls_v,ae_int16* ars,immediate ae_immls16) +BUILTIN(__builtin_xtensa_ae_s16_0_i, "vV4sV1s*i", "n") + +// void __builtin_xtensa_ae_s16_0_ip(ae_int16x4 ae_ls_v,ae_int16** ars,immediate ae_immls16) +BUILTIN(__builtin_xtensa_ae_s16_0_ip, "vV4sV1s**i", "n") + +// void __builtin_xtensa_ae_s16_0_x(ae_int16x4 ae_ls_v,ae_int16* ars,int art) +BUILTIN(__builtin_xtensa_ae_s16_0_x, "vV4sV1s*i", "n") + +// void __builtin_xtensa_ae_s16_0_xc(ae_int16x4 ae_ls_v,ae_int16** ars,int art) +BUILTIN(__builtin_xtensa_ae_s16_0_xc, "vV4sV1s**i", "n") + +// void __builtin_xtensa_ae_s16_0_xp(ae_int16x4 ae_ls_v,ae_int16** ars,int art) +BUILTIN(__builtin_xtensa_ae_s16_0_xp, "vV4sV1s**i", "n") + +// void __builtin_xtensa_ae_s16m_l_i(ae_int32x2 ae_ls_v,ae_int16* ars,immediate ae_immls16) +BUILTIN(__builtin_xtensa_ae_s16m_l_i, "vV2iV1s*i", "n") + +// void __builtin_xtensa_ae_s16m_l_iu(ae_int32x2 ae_ls_v,ae_int16** ars,immediate ae_immls16) +BUILTIN(__builtin_xtensa_ae_s16m_l_iu, "vV2iV1s**i", "n") + +// void __builtin_xtensa_ae_s16m_l_x(ae_int32x2 ae_ls_v,ae_int16* ars,int art) +BUILTIN(__builtin_xtensa_ae_s16m_l_x, "vV2iV1s*i", "n") + +// void __builtin_xtensa_ae_s16m_l_xc(ae_int32x2 ae_ls_v,ae_int16** ars,int art) +BUILTIN(__builtin_xtensa_ae_s16m_l_xc, "vV2iV1s**i", "n") + +// void __builtin_xtensa_ae_s16m_l_xu(ae_int32x2 ae_ls_v,ae_int16** ars,int art) +BUILTIN(__builtin_xtensa_ae_s16m_l_xu, "vV2iV1s**i", "n") + +// void __builtin_xtensa_ae_s16x2m_i(ae_int32x2 ae_ls_v,ae_int16x2* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s16x2m_i, "vV2iV2s*i", "n") + +// void __builtin_xtensa_ae_s16x2m_iu(ae_int32x2 ae_ls_v,ae_int16x2** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s16x2m_iu, "vV2iV2s**i", "n") + +// void __builtin_xtensa_ae_s16x2m_x(ae_int32x2 ae_ls_v,ae_int16x2* ars,int art) +BUILTIN(__builtin_xtensa_ae_s16x2m_x, "vV2iV2s*i", "n") + +// void __builtin_xtensa_ae_s16x2m_xc(ae_int32x2 ae_ls_v,ae_int16x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_s16x2m_xc, "vV2iV2s**i", "n") + +// void __builtin_xtensa_ae_s16x2m_xu(ae_int32x2 ae_ls_v,ae_int16x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_s16x2m_xu, "vV2iV2s**i", "n") + +// void __builtin_xtensa_ae_s16x4_i(ae_int16x4 ae_ls_v,ae_int16x4* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_s16x4_i, "vV4sV4s*i", "n") + +// void __builtin_xtensa_ae_s16x4_ip(ae_int16x4 ae_ls_v,ae_int16x4** ars,immediate ae_immls64pos) +BUILTIN(__builtin_xtensa_ae_s16x4_ip, "vV4sV4s**i", "n") + +// void __builtin_xtensa_ae_s16x4_ric(ae_int16x4 ae_ls_v,ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_s16x4_ric, "vV4sV4s**", "n") + +// void __builtin_xtensa_ae_s16x4_rip(ae_int16x4 ae_ls_v,ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_s16x4_rip, "vV4sV4s**", "n") + +// void __builtin_xtensa_ae_s16x4_x(ae_int16x4 ae_ls_v,ae_int16x4* ars,int art) +BUILTIN(__builtin_xtensa_ae_s16x4_x, "vV4sV4s*i", "n") + +// void __builtin_xtensa_ae_s16x4_xc(ae_int16x4 ae_ls_v,ae_int16x4** ars,int art) +BUILTIN(__builtin_xtensa_ae_s16x4_xc, "vV4sV4s**i", "n") + +// void __builtin_xtensa_ae_s16x4_xp(ae_int16x4 ae_ls_v,ae_int16x4** ars,int art) +BUILTIN(__builtin_xtensa_ae_s16x4_xp, "vV4sV4s**i", "n") + +// void __builtin_xtensa_ae_s24ra64s_i(ae_int64 ae_ls_v1,ae_int32* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s24ra64s_i, "vV1LLiV1i*i", "n") + +// void __builtin_xtensa_ae_s24ra64s_ip(ae_int64 ae_ls_v1,ae_int32** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s24ra64s_ip, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s24ra64s_x(ae_int64 ae_ls_v1,ae_int32* ars,int art) +BUILTIN(__builtin_xtensa_ae_s24ra64s_x, "vV1LLiV1i*i", "n") + +// void __builtin_xtensa_ae_s24ra64s_xc(ae_int64 ae_ls_v1,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s24ra64s_xc, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s24ra64s_xp(ae_int64 ae_ls_v1,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s24ra64s_xp, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s24x2ra64s_ip(ae_int64 ae_ls_v2,ae_int64 ae_ls_v1,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_s24x2ra64s_ip, "vV1LLiV1LLiV2i**", "n") + +// void __builtin_xtensa_ae_s32_l_i(ae_int32x2 ae_ls_v,ae_int32* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s32_l_i, "vV2iV1i*i", "n") + +// void __builtin_xtensa_ae_s32_l_ip(ae_int32x2 ae_ls_v,ae_int32** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s32_l_ip, "vV2iV1i**i", "n") + +// void __builtin_xtensa_ae_s32_l_x(ae_int32x2 ae_ls_v,ae_int32* ars,int art) +BUILTIN(__builtin_xtensa_ae_s32_l_x, "vV2iV1i*i", "n") + +// void __builtin_xtensa_ae_s32_l_xc(ae_int32x2 ae_ls_v,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32_l_xc, "vV2iV1i**i", "n") + +// void __builtin_xtensa_ae_s32_l_xp(ae_int32x2 ae_ls_v,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32_l_xp, "vV2iV1i**i", "n") + +// void __builtin_xtensa_ae_s32f24_l_i(ae_int32x2 ae_ls_v,ae_int32* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s32f24_l_i, "vV2iV1i*i", "n") + +// void __builtin_xtensa_ae_s32f24_l_ip(ae_int32x2 ae_ls_v,ae_int32** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s32f24_l_ip, "vV2iV1i**i", "n") + +// void __builtin_xtensa_ae_s32f24_l_x(ae_int32x2 ae_ls_v,ae_int32* ars,int art) +BUILTIN(__builtin_xtensa_ae_s32f24_l_x, "vV2iV1i*i", "n") + +// void __builtin_xtensa_ae_s32f24_l_xc(ae_int32x2 ae_ls_v,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32f24_l_xc, "vV2iV1i**i", "n") + +// void __builtin_xtensa_ae_s32f24_l_xp(ae_int32x2 ae_ls_v,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32f24_l_xp, "vV2iV1i**i", "n") + +// void __builtin_xtensa_ae_s32m_i(ae_int64 ae_ls_v,ae_int32* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s32m_i, "vV1LLiV1i*i", "n") + +// void __builtin_xtensa_ae_s32m_iu(ae_int64 ae_ls_v,ae_int32** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s32m_iu, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s32m_x(ae_int64 ae_ls_v,ae_int32* ars,int art) +BUILTIN(__builtin_xtensa_ae_s32m_x, "vV1LLiV1i*i", "n") + +// void __builtin_xtensa_ae_s32m_xc(ae_int64 ae_ls_v,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32m_xc, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s32m_xu(ae_int64 ae_ls_v,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32m_xu, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s32ra64s_i(ae_int64 ae_ls_v1,ae_int32* ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s32ra64s_i, "vV1LLiV1i*i", "n") + +// void __builtin_xtensa_ae_s32ra64s_ip(ae_int64 ae_ls_v1,ae_int32** ars,immediate ae_immls32) +BUILTIN(__builtin_xtensa_ae_s32ra64s_ip, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s32ra64s_x(ae_int64 ae_ls_v1,ae_int32* ars,int art) +BUILTIN(__builtin_xtensa_ae_s32ra64s_x, "vV1LLiV1i*i", "n") + +// void __builtin_xtensa_ae_s32ra64s_xc(ae_int64 ae_ls_v1,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32ra64s_xc, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s32ra64s_xp(ae_int64 ae_ls_v1,ae_int32** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32ra64s_xp, "vV1LLiV1i**i", "n") + +// void __builtin_xtensa_ae_s32x2_i(ae_int32x2 ae_ls_v,ae_int32x2* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_s32x2_i, "vV2iV2i*i", "n") + +// void __builtin_xtensa_ae_s32x2_ip(ae_int32x2 ae_ls_v,ae_int32x2** ars,immediate ae_immls64pos) +BUILTIN(__builtin_xtensa_ae_s32x2_ip, "vV2iV2i**i", "n") + +// void __builtin_xtensa_ae_s32x2_ric(ae_int32x2 ae_ls_v,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_s32x2_ric, "vV2iV2i**", "n") + +// void __builtin_xtensa_ae_s32x2_rip(ae_int32x2 ae_ls_v,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_s32x2_rip, "vV2iV2i**", "n") + +// void __builtin_xtensa_ae_s32x2_x(ae_int32x2 ae_ls_v,ae_int32x2* ars,int art) +BUILTIN(__builtin_xtensa_ae_s32x2_x, "vV2iV2i*i", "n") + +// void __builtin_xtensa_ae_s32x2_xc(ae_int32x2 ae_ls_v,ae_int32x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32x2_xc, "vV2iV2i**i", "n") + +// void __builtin_xtensa_ae_s32x2_xp(ae_int32x2 ae_ls_v,ae_int32x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32x2_xp, "vV2iV2i**i", "n") + +// void __builtin_xtensa_ae_s32x2f24_i(ae_int32x2 ae_ls_v,ae_int32x2* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_s32x2f24_i, "vV2iV2i*i", "n") + +// void __builtin_xtensa_ae_s32x2f24_ip(ae_int32x2 ae_ls_v,ae_int32x2** ars,immediate ae_immls64pos) +BUILTIN(__builtin_xtensa_ae_s32x2f24_ip, "vV2iV2i**i", "n") + +// void __builtin_xtensa_ae_s32x2f24_ric(ae_int32x2 ae_ls_v,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_s32x2f24_ric, "vV2iV2i**", "n") + +// void __builtin_xtensa_ae_s32x2f24_rip(ae_int32x2 ae_ls_v,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_s32x2f24_rip, "vV2iV2i**", "n") + +// void __builtin_xtensa_ae_s32x2f24_x(ae_int32x2 ae_ls_v,ae_int32x2* ars,int art) +BUILTIN(__builtin_xtensa_ae_s32x2f24_x, "vV2iV2i*i", "n") + +// void __builtin_xtensa_ae_s32x2f24_xc(ae_int32x2 ae_ls_v,ae_int32x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32x2f24_xc, "vV2iV2i**i", "n") + +// void __builtin_xtensa_ae_s32x2f24_xp(ae_int32x2 ae_ls_v,ae_int32x2** ars,int art) +BUILTIN(__builtin_xtensa_ae_s32x2f24_xp, "vV2iV2i**i", "n") + +// void __builtin_xtensa_ae_s32x2ra64s_ip(ae_int64 ae_ls_v2,ae_int64 ae_ls_v1,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_s32x2ra64s_ip, "vV1LLiV1LLiV2i**", "n") + +// void __builtin_xtensa_ae_s64_i(ae_int64 ae_ls_v,ae_int64* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_s64_i, "vV1LLiV1LLi*i", "n") + +// void __builtin_xtensa_ae_s64_ip(ae_int64 ae_ls_v,ae_int64** ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_s64_ip, "vV1LLiV1LLi**i", "n") + +// void __builtin_xtensa_ae_s64_x(ae_int64 ae_ls_v,ae_int64* ars,int art) +BUILTIN(__builtin_xtensa_ae_s64_x, "vV1LLiV1LLi*i", "n") + +// void __builtin_xtensa_ae_s64_xc(ae_int64 ae_ls_v,ae_int64** ars,int art) +BUILTIN(__builtin_xtensa_ae_s64_xc, "vV1LLiV1LLi**i", "n") + +// void __builtin_xtensa_ae_s64_xp(ae_int64 ae_ls_v,ae_int64** ars,int art) +BUILTIN(__builtin_xtensa_ae_s64_xp, "vV1LLiV1LLi**i", "n") + +// void __builtin_xtensa_ae_sa16x4_ic(ae_int16x4 ae_ls_v,ae_valign* ae_ls_su,ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_sa16x4_ic, "vV4sV8Uc*V4s**", "n") + +// void __builtin_xtensa_ae_sa16x4_ip(ae_int16x4 ae_ls_v,ae_valign* ae_ls_su,ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_sa16x4_ip, "vV4sV8Uc*V4s**", "n") + +// void __builtin_xtensa_ae_sa16x4_ric(ae_int16x4 ae_ls_v,ae_valign* ae_ls_su,ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_sa16x4_ric, "vV4sV8Uc*V4s**", "n") + +// void __builtin_xtensa_ae_sa16x4_rip(ae_int16x4 ae_ls_v,ae_valign* ae_ls_su,ae_int16x4** ars) +BUILTIN(__builtin_xtensa_ae_sa16x4_rip, "vV4sV8Uc*V4s**", "n") + +// void __builtin_xtensa_ae_sa24_l_ic(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) +BUILTIN(__builtin_xtensa_ae_sa24_l_ic, "vV2iV8Uc*v**", "n") + +// void __builtin_xtensa_ae_sa24_l_ip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) +BUILTIN(__builtin_xtensa_ae_sa24_l_ip, "vV2iV8Uc*v**", "n") + +// void __builtin_xtensa_ae_sa24_l_ric(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) +BUILTIN(__builtin_xtensa_ae_sa24_l_ric, "vV2iV8Uc*v**", "n") + +// void __builtin_xtensa_ae_sa24_l_rip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) +BUILTIN(__builtin_xtensa_ae_sa24_l_rip, "vV2iV8Uc*v**", "n") + +// void __builtin_xtensa_ae_sa24x2_ic(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) +BUILTIN(__builtin_xtensa_ae_sa24x2_ic, "vV2iV8Uc*v**", "n") + +// void __builtin_xtensa_ae_sa24x2_ip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) +BUILTIN(__builtin_xtensa_ae_sa24x2_ip, "vV2iV8Uc*v**", "n") + +// void __builtin_xtensa_ae_sa24x2_ric(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) +BUILTIN(__builtin_xtensa_ae_sa24x2_ric, "vV2iV8Uc*v**", "n") + +// void __builtin_xtensa_ae_sa24x2_rip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) +BUILTIN(__builtin_xtensa_ae_sa24x2_rip, "vV2iV8Uc*v**", "n") + +// void __builtin_xtensa_ae_sa32x2_ic(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_sa32x2_ic, "vV2iV8Uc*V2i**", "n") + +// void __builtin_xtensa_ae_sa32x2_ip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_sa32x2_ip, "vV2iV8Uc*V2i**", "n") + +// void __builtin_xtensa_ae_sa32x2_ric(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_sa32x2_ric, "vV2iV8Uc*V2i**", "n") + +// void __builtin_xtensa_ae_sa32x2_rip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_sa32x2_rip, "vV2iV8Uc*V2i**", "n") + +// void __builtin_xtensa_ae_sa32x2f24_ic(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_sa32x2f24_ic, "vV2iV8Uc*V2i**", "n") + +// void __builtin_xtensa_ae_sa32x2f24_ip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_sa32x2f24_ip, "vV2iV8Uc*V2i**", "n") + +// void __builtin_xtensa_ae_sa32x2f24_ric(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_sa32x2f24_ric, "vV2iV8Uc*V2i**", "n") + +// void __builtin_xtensa_ae_sa32x2f24_rip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) +BUILTIN(__builtin_xtensa_ae_sa32x2f24_rip, "vV2iV8Uc*V2i**", "n") + +// void __builtin_xtensa_ae_sa64neg_fp(ae_valign* ae_ls_su,void* ars) +BUILTIN(__builtin_xtensa_ae_sa64neg_fp, "vV8Uc*v*", "n") + +// void __builtin_xtensa_ae_sa64pos_fp(ae_valign* ae_ls_su,void* ars) +BUILTIN(__builtin_xtensa_ae_sa64pos_fp, "vV8Uc*v*", "n") + +// void __builtin_xtensa_ae_salign64_i(ae_valign ae_ls_su,ae_valign* ars,immediate ae_immls64) +BUILTIN(__builtin_xtensa_ae_salign64_i, "vV8UcV8Uc*i", "n") + +// ae_int16x4 __builtin_xtensa_ae_sat16x4(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sat16x4, "V4sV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_sat24s(ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sat24s, "V2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_sat48s(ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sat48s, "V1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_satq56s(ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_satq56s, "V1LLiV1LLi", "n") + +// void __builtin_xtensa_ae_sb(short** ars,int art) +BUILTIN(__builtin_xtensa_ae_sb, "vs**i", "n") + +// void __builtin_xtensa_ae_sb_ic(short** ars,int art) +BUILTIN(__builtin_xtensa_ae_sb_ic, "vs**i", "n") + +// void __builtin_xtensa_ae_sb_ip(short** ars,int art) +BUILTIN(__builtin_xtensa_ae_sb_ip, "vs**i", "n") + +// void __builtin_xtensa_ae_sbf(short** ars) +BUILTIN(__builtin_xtensa_ae_sbf, "vs**", "n") + +// void __builtin_xtensa_ae_sbf_ic(short** ars) +BUILTIN(__builtin_xtensa_ae_sbf_ic, "vs**", "n") + +// void __builtin_xtensa_ae_sbf_ip(short** ars) +BUILTIN(__builtin_xtensa_ae_sbf_ip, "vs**", "n") + +// void __builtin_xtensa_ae_sbi(short** ars,int art,immediate ae_ohba2) +BUILTIN(__builtin_xtensa_ae_sbi, "vs**ii", "n") + +// void __builtin_xtensa_ae_sbi_ic(short** ars,int art,immediate ae_ohba2) +BUILTIN(__builtin_xtensa_ae_sbi_ic, "vs**ii", "n") + +// void __builtin_xtensa_ae_sbi_ip(short** ars,int art,immediate ae_ohba2) +BUILTIN(__builtin_xtensa_ae_sbi_ip, "vs**ii", "n") + +// ae_int16x4 __builtin_xtensa_ae_sel16i(ae_int16x4 ae_dr_to_dr_v0,ae_int16x4 ae_dr_to_dr_v1,immediate ae_selimm) +BUILTIN(__builtin_xtensa_ae_sel16i, "V4sV4sV4si", "n") + +// ae_int16x4 __builtin_xtensa_ae_sel16i_n(ae_int16x4 ae_dr_to_dr_v0,ae_int16x4 ae_dr_to_dr_v1,immediate ae_selimm_N) +BUILTIN(__builtin_xtensa_ae_sel16i_n, "V4sV4sV4si", "n") + +// ae_int32x2 __builtin_xtensa_ae_sext32(ae_int32x2 ae_dr_to_dr_v0,immediate ae_opnd_tp7) +BUILTIN(__builtin_xtensa_ae_sext32, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_sext32x2d16_10(ae_int16x4 ae_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_sext32x2d16_10, "V2iV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_sext32x2d16_32(ae_int16x4 ae_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_sext32x2d16_32, "V2iV4s", "n") + +// int __builtin_xtensa_ae_sha32(int ars) +BUILTIN(__builtin_xtensa_ae_sha32, "ii", "n") + +// ae_int16x4 __builtin_xtensa_ae_shortswap(ae_int16x4 ae_to_dr_v0) +BUILTIN(__builtin_xtensa_ae_shortswap, "V4sV4s", "n") + +// ae_int16x4 __builtin_xtensa_ae_slaa16s(ae_int16x4 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_slaa16s, "V4sV4si", "n") + +// ae_int32x2 __builtin_xtensa_ae_slaa32(ae_int32x2 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_slaa32, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_slaa32s(ae_int32x2 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_slaa32s, "V2iV2ii", "n") + +// ae_int64 __builtin_xtensa_ae_slaa64(ae_int64 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_slaa64, "V1LLiV1LLii", "n") + +// ae_int64 __builtin_xtensa_ae_slaa64s(ae_int64 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_slaa64s, "V1LLiV1LLii", "n") + +// ae_int64 __builtin_xtensa_ae_slaaq56(ae_int64 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_slaaq56, "V1LLiV1LLii", "n") + +// ae_int16x4 __builtin_xtensa_ae_slai16s(ae_int16x4 ae_shift_d0,immediate ae_osa16) +BUILTIN(__builtin_xtensa_ae_slai16s, "V4sV4si", "n") + +// ae_int32x2 __builtin_xtensa_ae_slai24(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_slai24, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_slai24s(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_slai24s, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_slai32(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_slai32, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_slai32s(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_slai32s, "V2iV2ii", "n") + +// ae_int64 __builtin_xtensa_ae_slai64(ae_int64 ae_shift_d0,immediate ae_osa64) +BUILTIN(__builtin_xtensa_ae_slai64, "V1LLiV1LLii", "n") + +// ae_int64 __builtin_xtensa_ae_slai64s(ae_int64 ae_shift_d0,immediate ae_osa64) +BUILTIN(__builtin_xtensa_ae_slai64s, "V1LLiV1LLii", "n") + +// ae_int64 __builtin_xtensa_ae_slaisq56s(ae_int64 ae_shift_d0,immediate ae_osa64) +BUILTIN(__builtin_xtensa_ae_slaisq56s, "V1LLiV1LLii", "n") + +// ae_int32x2 __builtin_xtensa_ae_slas24(ae_int32x2 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_slas24, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_slas24s(ae_int32x2 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_slas24s, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_slas32(ae_int32x2 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_slas32, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_slas32s(ae_int32x2 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_slas32s, "V2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_slas64(ae_int64 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_slas64, "V1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_slas64s(ae_int64 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_slas64s, "V1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_slasq56(ae_int64 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_slasq56, "V1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_slassq56s(ae_int64 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_slassq56s, "V1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_sra64_32(ae_int32x2 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_sra64_32, "V1LLiV2ii", "n") + +// ae_int16x4 __builtin_xtensa_ae_sraa16rs(ae_int16x4 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_sraa16rs, "V4sV4si", "n") + +// ae_int16x4 __builtin_xtensa_ae_sraa16s(ae_int16x4 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_sraa16s, "V4sV4si", "n") + +// ae_int32x2 __builtin_xtensa_ae_sraa32(ae_int32x2 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_sraa32, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_sraa32rs(ae_int32x2 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_sraa32rs, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_sraa32s(ae_int32x2 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_sraa32s, "V2iV2ii", "n") + +// ae_int64 __builtin_xtensa_ae_sraa64(ae_int64 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_sraa64, "V1LLiV1LLii", "n") + +// ae_int16x4 __builtin_xtensa_ae_srai16(ae_int16x4 ae_shift_d0,immediate ae_osa16) +BUILTIN(__builtin_xtensa_ae_srai16, "V4sV4si", "n") + +// ae_int16x4 __builtin_xtensa_ae_srai16r(ae_int16x4 ae_shift_d0,immediate ae_osa16) +BUILTIN(__builtin_xtensa_ae_srai16r, "V4sV4si", "n") + +// ae_int32x2 __builtin_xtensa_ae_srai24(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_srai24, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_srai32(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_srai32, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_srai32r(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_srai32r, "V2iV2ii", "n") + +// ae_int64 __builtin_xtensa_ae_srai64(ae_int64 ae_shift_d0,immediate ae_osa64) +BUILTIN(__builtin_xtensa_ae_srai64, "V1LLiV1LLii", "n") + +// ae_int32x2 __builtin_xtensa_ae_sras24(ae_int32x2 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_sras24, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_sras32(ae_int32x2 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_sras32, "V2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_sras64(ae_int64 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_sras64, "V1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_srla32(ae_int32x2 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_srla32, "V2iV2ii", "n") + +// ae_int64 __builtin_xtensa_ae_srla64(ae_int64 ae_shift_d0,int ars) +BUILTIN(__builtin_xtensa_ae_srla64, "V1LLiV1LLii", "n") + +// ae_int32x2 __builtin_xtensa_ae_srli24(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_srli24, "V2iV2ii", "n") + +// ae_int32x2 __builtin_xtensa_ae_srli32(ae_int32x2 ae_shift_d0,immediate ae_osa32) +BUILTIN(__builtin_xtensa_ae_srli32, "V2iV2ii", "n") + +// ae_int64 __builtin_xtensa_ae_srli64(ae_int64 ae_shift_d0,immediate ae_osa64) +BUILTIN(__builtin_xtensa_ae_srli64, "V1LLiV1LLii", "n") + +// ae_int32x2 __builtin_xtensa_ae_srls24(ae_int32x2 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_srls24, "V2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_srls32(ae_int32x2 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_srls32, "V2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_srls64(ae_int64 ae_shift_d0) +BUILTIN(__builtin_xtensa_ae_srls64, "V1LLiV1LLi", "n") + +// ae_int16x4 __builtin_xtensa_ae_sub16(ae_int16x4 ae_arth_v0,ae_int16x4 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sub16, "V4sV4sV4s", "n") + +// ae_int16x4 __builtin_xtensa_ae_sub16s(ae_int16x4 ae_arth_v0,ae_int16x4 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sub16s, "V4sV4sV4s", "n") + +// ae_int32x2 __builtin_xtensa_ae_sub24s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sub24s, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_sub32(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sub32, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_sub32s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sub32s, "V2iV2iV2i", "n") + +// ae_int64 __builtin_xtensa_ae_sub64(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sub64, "V1LLiV1LLiV1LLi", "n") + +// ae_int64 __builtin_xtensa_ae_sub64s(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_sub64s, "V1LLiV1LLiV1LLi", "n") + +// ae_int32x2 __builtin_xtensa_ae_subadd32(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_subadd32, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_subadd32s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) +BUILTIN(__builtin_xtensa_ae_subadd32s, "V2iV2iV2i", "n") + +// ae_int32x2 __builtin_xtensa_ae_trunca32f64s_l(ae_int32x2 ae_shift_d0,ae_int64 ae_shift_sd,int ars) +BUILTIN(__builtin_xtensa_ae_trunca32f64s_l, "V2iV2iV1LLii", "n") + +// ae_int32x2 __builtin_xtensa_ae_trunca32x2f64s(ae_int64 ae_shift_d0,ae_int64 ae_shift_sd,int ars) +BUILTIN(__builtin_xtensa_ae_trunca32x2f64s, "V2iV1LLiV1LLii", "n") + +// ae_int32x2 __builtin_xtensa_ae_trunci32f64s_l(ae_int32x2 ae_shift_d0,ae_int64 ae_shift_sd,immediate ae_osa16) +BUILTIN(__builtin_xtensa_ae_trunci32f64s_l, "V2iV2iV1LLii", "n") + +// ae_int32x2 __builtin_xtensa_ae_trunci32x2f64s(ae_int64 ae_shift_d0,ae_int64 ae_shift_sd,immediate ae_osa16) +BUILTIN(__builtin_xtensa_ae_trunci32x2f64s, "V2iV1LLiV1LLii", "n") + +// void __builtin_xtensa_ae_vldl16c(const short** ars) +BUILTIN(__builtin_xtensa_ae_vldl16c, "vsC**", "n") + +// void __builtin_xtensa_ae_vldl16c_ic(const short** ars) +BUILTIN(__builtin_xtensa_ae_vldl16c_ic, "vsC**", "n") + +// void __builtin_xtensa_ae_vldl16c_ip(const short** ars) +BUILTIN(__builtin_xtensa_ae_vldl16c_ip, "vsC**", "n") + +// void __builtin_xtensa_ae_vldl16t(xtbool* br,int* art,const short* ars) +BUILTIN(__builtin_xtensa_ae_vldl16t, "vV1b*i*sC*", "n") + +// void __builtin_xtensa_ae_vldl32t(xtbool* br,int* art,const int* ars) +BUILTIN(__builtin_xtensa_ae_vldl32t, "vV1b*i*iC*", "n") + +// void __builtin_xtensa_ae_vldsht(int art) +BUILTIN(__builtin_xtensa_ae_vldsht, "vi", "n") + +// void __builtin_xtensa_ae_vlel16t(xtbool* br,int* art,const short* ars) +BUILTIN(__builtin_xtensa_ae_vlel16t, "vV1b*i*sC*", "n") + +// void __builtin_xtensa_ae_vlel32t(xtbool* br,int* art,const int* ars) +BUILTIN(__builtin_xtensa_ae_vlel32t, "vV1b*i*iC*", "n") + +// void __builtin_xtensa_ae_vles16c(short** ars) +BUILTIN(__builtin_xtensa_ae_vles16c, "vs**", "n") + +// void __builtin_xtensa_ae_vles16c_ic(short** ars) +BUILTIN(__builtin_xtensa_ae_vles16c_ic, "vs**", "n") + +// void __builtin_xtensa_ae_vles16c_ip(short** ars) +BUILTIN(__builtin_xtensa_ae_vles16c_ip, "vs**", "n") + +// ae_int64 __builtin_xtensa_ae_xor(ae_int64 ae_dr_to_dr_v0,ae_int64 ae_dr_to_dr_v1) +BUILTIN(__builtin_xtensa_ae_xor, "V1LLiV1LLiV1LLi", "n") + +// ae_valign __builtin_xtensa_ae_zalign64() +BUILTIN(__builtin_xtensa_ae_zalign64, "V8Uc", "n") + +// int __builtin_xtensa_rur_ae_bithead() +BUILTIN(__builtin_xtensa_rur_ae_bithead, "i", "n") + +// int __builtin_xtensa_rur_ae_bitptr() +BUILTIN(__builtin_xtensa_rur_ae_bitptr, "i", "n") + +// int __builtin_xtensa_rur_ae_bitsused() +BUILTIN(__builtin_xtensa_rur_ae_bitsused, "i", "n") + +// int __builtin_xtensa_rur_ae_cbegin0() +BUILTIN(__builtin_xtensa_rur_ae_cbegin0, "i", "n") + +// int __builtin_xtensa_rur_ae_cend0() +BUILTIN(__builtin_xtensa_rur_ae_cend0, "i", "n") + +// int __builtin_xtensa_rur_ae_cw_sd_no() +BUILTIN(__builtin_xtensa_rur_ae_cw_sd_no, "i", "n") + +// int __builtin_xtensa_rur_ae_cwrap() +BUILTIN(__builtin_xtensa_rur_ae_cwrap, "i", "n") + +// int __builtin_xtensa_rur_ae_first_ts() +BUILTIN(__builtin_xtensa_rur_ae_first_ts, "i", "n") + +// int __builtin_xtensa_rur_ae_nextoffset() +BUILTIN(__builtin_xtensa_rur_ae_nextoffset, "i", "n") + +// int __builtin_xtensa_rur_ae_overflow() +BUILTIN(__builtin_xtensa_rur_ae_overflow, "i", "n") + +// int __builtin_xtensa_rur_ae_ovf_sar() +BUILTIN(__builtin_xtensa_rur_ae_ovf_sar, "i", "n") + +// int __builtin_xtensa_rur_ae_sar() +BUILTIN(__builtin_xtensa_rur_ae_sar, "i", "n") + +// int __builtin_xtensa_rur_ae_searchdone() +BUILTIN(__builtin_xtensa_rur_ae_searchdone, "i", "n") + +// int __builtin_xtensa_rur_ae_tablesize() +BUILTIN(__builtin_xtensa_rur_ae_tablesize, "i", "n") + +// int __builtin_xtensa_rur_ae_ts_fts_bu_bp() +BUILTIN(__builtin_xtensa_rur_ae_ts_fts_bu_bp, "i", "n") + +// void __builtin_xtensa_wur_ae_bithead(int art) +BUILTIN(__builtin_xtensa_wur_ae_bithead, "vi", "n") + +// void __builtin_xtensa_wur_ae_bitptr(int art) +BUILTIN(__builtin_xtensa_wur_ae_bitptr, "vi", "n") + +// void __builtin_xtensa_wur_ae_bitsused(int art) +BUILTIN(__builtin_xtensa_wur_ae_bitsused, "vi", "n") + +// void __builtin_xtensa_wur_ae_cbegin0(int art) +BUILTIN(__builtin_xtensa_wur_ae_cbegin0, "vi", "n") + +// void __builtin_xtensa_wur_ae_cend0(int art) +BUILTIN(__builtin_xtensa_wur_ae_cend0, "vi", "n") + +// void __builtin_xtensa_wur_ae_cw_sd_no(int art) +BUILTIN(__builtin_xtensa_wur_ae_cw_sd_no, "vi", "n") + +// void __builtin_xtensa_wur_ae_cwrap(int art) +BUILTIN(__builtin_xtensa_wur_ae_cwrap, "vi", "n") + +// void __builtin_xtensa_wur_ae_first_ts(int art) +BUILTIN(__builtin_xtensa_wur_ae_first_ts, "vi", "n") + +// void __builtin_xtensa_wur_ae_nextoffset(int art) +BUILTIN(__builtin_xtensa_wur_ae_nextoffset, "vi", "n") + +// void __builtin_xtensa_wur_ae_overflow(int art) +BUILTIN(__builtin_xtensa_wur_ae_overflow, "vi", "n") + +// void __builtin_xtensa_wur_ae_ovf_sar(int art) +BUILTIN(__builtin_xtensa_wur_ae_ovf_sar, "vi", "n") + +// void __builtin_xtensa_wur_ae_sar(int art) +BUILTIN(__builtin_xtensa_wur_ae_sar, "vi", "n") + +// void __builtin_xtensa_wur_ae_searchdone(int art) +BUILTIN(__builtin_xtensa_wur_ae_searchdone, "vi", "n") + +// void __builtin_xtensa_wur_ae_tablesize(int art) +BUILTIN(__builtin_xtensa_wur_ae_tablesize, "vi", "n") + +// void __builtin_xtensa_wur_ae_ts_fts_bu_bp(int art) +BUILTIN(__builtin_xtensa_wur_ae_ts_fts_bu_bp, "vi", "n") + +#undef BUILTIN diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index 50c4052a995571..25f6526fb022ca 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -368,12 +368,14 @@ namespace clang { /// Xtensa builtins namespace Xtensa { - enum { - LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1, + enum { + LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1, #define BUILTIN(ID, TYPE, ATTRS) BI##ID, #include "clang/Basic/BuiltinsXtensa.def" - LastTSBuiltin - }; +#include "clang/Basic/BuiltinsXtensaHIFI.def" +#undef BUILTIN + LastTSBuiltin + }; } // namespace Xtensa static constexpr uint64_t LargestBuiltinID = std::max( diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp index cded885966c896..7b5346062bccb0 100644 --- a/clang/lib/Basic/Targets/Xtensa.cpp +++ b/clang/lib/Basic/Targets/Xtensa.cpp @@ -24,6 +24,8 @@ static constexpr Builtin::Info BuiltinInfo[] = { #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, #include "clang/Basic/BuiltinsXtensa.def" +#include "clang/Basic/BuiltinsXtensaHIFI.def" +#undef BUILTIN }; ArrayRef XtensaTargetInfo::getTargetBuiltins() const { From f24eb6224e40806752a175a797262cdd90039cb5 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:57:23 +0000 Subject: [PATCH 222/261] [Xtensa] Add constant checks for HIFI3 intrinsics --- clang/include/clang/Basic/XtensaSemaCheck.inc | 215 ++++++++++++++++++ clang/lib/Sema/SemaChecking.cpp | 1 + 2 files changed, 216 insertions(+) create mode 100644 clang/include/clang/Basic/XtensaSemaCheck.inc diff --git a/clang/include/clang/Basic/XtensaSemaCheck.inc b/clang/include/clang/Basic/XtensaSemaCheck.inc new file mode 100644 index 00000000000000..58c267e103d46e --- /dev/null +++ b/clang/include/clang/Basic/XtensaSemaCheck.inc @@ -0,0 +1,215 @@ +//===-- XtensaSemaCheck.inc - Clang semantic checks for Xtensa arch ----*- C++ +//-*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +case Xtensa::BI__builtin_xtensa_ae_dbi: +return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_dbi_ic: +return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_dbi_ip: +return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_l16_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -16, 14) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 2); +case Xtensa::BI__builtin_xtensa_ae_l16_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -16, 14) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 2); +case Xtensa::BI__builtin_xtensa_ae_l16m_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -16, 14) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 2); +case Xtensa::BI__builtin_xtensa_ae_l16m_iu: +return SemaBuiltinConstantArgRange(TheCall, 2, -16, 14) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 2); +case Xtensa::BI__builtin_xtensa_ae_l16x2m_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 4); +case Xtensa::BI__builtin_xtensa_ae_l16x2m_iu: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_l16x4_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 8); +case Xtensa::BI__builtin_xtensa_ae_l16x4_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_l32_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 4); +case Xtensa::BI__builtin_xtensa_ae_l32_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_l32f24_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 4); +case Xtensa::BI__builtin_xtensa_ae_l32f24_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_l32m_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 4); +case Xtensa::BI__builtin_xtensa_ae_l32m_iu: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_l32x2_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 8); +case Xtensa::BI__builtin_xtensa_ae_l32x2_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 8); +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_l64_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 8); +case Xtensa::BI__builtin_xtensa_ae_l64_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_lalign64_i: +return SemaBuiltinConstantArgRange(TheCall, 1, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 1, 8); +case Xtensa::BI__builtin_xtensa_ae_lbi: +return SemaBuiltinConstantArgRange(TheCall, 0, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_lbki: +return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_lbsi: +return SemaBuiltinConstantArgRange(TheCall, 0, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_movi: +return SemaBuiltinConstantArgRange(TheCall, 0, -16, 47); +case Xtensa::BI__builtin_xtensa_ae_pksr24: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); +case Xtensa::BI__builtin_xtensa_ae_pksr32: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); +case Xtensa::BI__builtin_xtensa_ae_s16_0_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -16, 14) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 2); +case Xtensa::BI__builtin_xtensa_ae_s16_0_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -16, 14) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 2); +case Xtensa::BI__builtin_xtensa_ae_s16m_l_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -16, 14) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 2); +case Xtensa::BI__builtin_xtensa_ae_s16m_l_iu: +return SemaBuiltinConstantArgRange(TheCall, 2, -16, 14) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 2); +case Xtensa::BI__builtin_xtensa_ae_s16x2m_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s16x2m_iu: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s16x4_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_s16x4_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_s24ra64s_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s24ra64s_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32_l_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32_l_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32f24_l_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32f24_l_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32m_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32m_iu: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32ra64s_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32ra64s_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -32, 28) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 4); +case Xtensa::BI__builtin_xtensa_ae_s32x2_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_s32x2_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_s64_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_s64_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_salign64_i: +return SemaBuiltinConstantArgRange(TheCall, 2, -64, 56) || + SemaBuiltinConstantArgMultiple(TheCall, 2, 8); +case Xtensa::BI__builtin_xtensa_ae_sbi: +return SemaBuiltinConstantArgRange(TheCall, 2, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_sbi_ic: +return SemaBuiltinConstantArgRange(TheCall, 2, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_sbi_ip: +return SemaBuiltinConstantArgRange(TheCall, 2, 1, 16); +case Xtensa::BI__builtin_xtensa_ae_sel16i: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 15); +case Xtensa::BI__builtin_xtensa_ae_sel16i_n: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); +case Xtensa::BI__builtin_xtensa_ae_sext32: +return SemaBuiltinConstantArgRange(TheCall, 1, 7, 22); +case Xtensa::BI__builtin_xtensa_ae_slai16s: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); +case Xtensa::BI__builtin_xtensa_ae_slai24: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_slai24s: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_slai32: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_slai32s: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_slai64: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 63); +case Xtensa::BI__builtin_xtensa_ae_slai64s: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 63); +case Xtensa::BI__builtin_xtensa_ae_slaisq56s: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 63); +case Xtensa::BI__builtin_xtensa_ae_srai16: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); +case Xtensa::BI__builtin_xtensa_ae_srai16r: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); +case Xtensa::BI__builtin_xtensa_ae_srai24: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_srai32: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_srai32r: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_srai64: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 63); +case Xtensa::BI__builtin_xtensa_ae_srli24: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_srli32: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); +case Xtensa::BI__builtin_xtensa_ae_srli64: +return SemaBuiltinConstantArgRange(TheCall, 1, 0, 63); +case Xtensa::BI__builtin_xtensa_ae_trunci32f64s_l: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 15); +case Xtensa::BI__builtin_xtensa_ae_trunci32x2f64s: +return SemaBuiltinConstantArgRange(TheCall, 2, 0, 15); diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 72efbb6e507d85..565c99b787fe09 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -6216,6 +6216,7 @@ bool Sema::CheckXtensaBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { unsigned i = 0, l = 0, u = 0; switch (BuiltinID) { +#include "clang/Basic/XtensaSemaCheck.inc" default: return false; case Xtensa::BI__builtin_xtensa_mul_ad_ll: From 959b98273f7467157955d2413b5cdcc5d1825031 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 14:01:42 +0000 Subject: [PATCH 223/261] [Xtensa] Support HIFI3 vectors in LLVM calls --- clang/lib/CodeGen/Targets/Xtensa.cpp | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/clang/lib/CodeGen/Targets/Xtensa.cpp b/clang/lib/CodeGen/Targets/Xtensa.cpp index f53039e5e90a56..0a824924e4a2b5 100644 --- a/clang/lib/CodeGen/Targets/Xtensa.cpp +++ b/clang/lib/CodeGen/Targets/Xtensa.cpp @@ -104,7 +104,16 @@ ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty, llvm::FixedVectorType::get(llvm::Type::getInt1Ty(getVMContext()), 1); return ABIArgInfo::getDirect(ResType); } - + // Vector arguments + if (getTarget().hasFeature("hifi3") && Ty->isVectorType() && (Size <= 64)) { + const VectorType *VT = Ty->getAs(); + QualType EltTy = VT->getElementType(); + unsigned EltSize = getContext().getTypeSize(EltTy); + if (EltSize == 8) // VAlign + return ABIArgInfo::getDirect( + llvm::IntegerType::get(getVMContext(), Size)); + return ABIArgInfo::getDirectInReg(); + } // Aggregates which are <= 6*32 will be passed in registers if possible, // so coerce to integers. if ((Size <= (MaxNumArgGPRs * 32)) && (!MustUseStack)) { @@ -246,7 +255,6 @@ class XtensaTargetCodeGenInfo : public TargetCodeGenInfo { }; } // namespace - std::unique_ptr CodeGen::createXtensaTargetCodeGenInfo(CodeGenModule &CGM) { return std::make_unique(CGM.getTypes()); From 9e3290df5883f5682942983a1018603fea035f49 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 26 Mar 2024 16:47:48 +0300 Subject: [PATCH 224/261] [Xtensa] Add HIFI3 intrinsics to Clang codegen --- clang/include/clang/Basic/XtensaBuiltins.inc | 1743 ++ clang/lib/CodeGen/CGBuiltin.cpp | 216 +- clang/lib/CodeGen/CodeGenFunction.h | 2 + .../CodeGen/Xtensa/xtensa-hifi-intrinsics.c | 21408 ++++++++++++++++ 4 files changed, 23335 insertions(+), 34 deletions(-) create mode 100644 clang/include/clang/Basic/XtensaBuiltins.inc create mode 100644 clang/test/CodeGen/Xtensa/xtensa-hifi-intrinsics.c diff --git a/clang/include/clang/Basic/XtensaBuiltins.inc b/clang/include/clang/Basic/XtensaBuiltins.inc new file mode 100644 index 00000000000000..1231d992c36c4d --- /dev/null +++ b/clang/include/clang/Basic/XtensaBuiltins.inc @@ -0,0 +1,1743 @@ +//===-- XtensaBuiltins.inc - Clang intrinsic database for Xtensa arch ----*- C++ +//-*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +case Xtensa::BI__builtin_xtensa_ae_abs16s: +return {Intrinsic::xtensa_ae_abs16s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_abs24s: +return {Intrinsic::xtensa_ae_abs24s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_abs32: +return {Intrinsic::xtensa_ae_abs32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_abs32s: +return {Intrinsic::xtensa_ae_abs32s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_abs64: +return {Intrinsic::xtensa_ae_abs64, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_abs64s: +return {Intrinsic::xtensa_ae_abs64s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_add16: +return {Intrinsic::xtensa_ae_add16, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_add16s: +return {Intrinsic::xtensa_ae_add16s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_add24s: +return {Intrinsic::xtensa_ae_add24s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_add32: +return {Intrinsic::xtensa_ae_add32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_add32_hl_lh: +return {Intrinsic::xtensa_ae_add32_hl_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_add32s: +return {Intrinsic::xtensa_ae_add32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_add64: +return {Intrinsic::xtensa_ae_add64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_add64s: +return {Intrinsic::xtensa_ae_add64s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_addbrba32: +return {Intrinsic::xtensa_ae_addbrba32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_addsub32: +return {Intrinsic::xtensa_ae_addsub32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_addsub32s: +return {Intrinsic::xtensa_ae_addsub32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_and: +return {Intrinsic::xtensa_ae_and, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_cvt32x2f16_10: +return {Intrinsic::xtensa_ae_cvt32x2f16_10, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvt32x2f16_32: +return {Intrinsic::xtensa_ae_cvt32x2f16_32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvt48a32: +return {Intrinsic::xtensa_ae_cvt48a32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvt64a32: +return {Intrinsic::xtensa_ae_cvt64a32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvt64f32_h: +return {Intrinsic::xtensa_ae_cvt64f32_h, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvta32f24s_h: +return {Intrinsic::xtensa_ae_cvta32f24s_h, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvta32f24s_l: +return {Intrinsic::xtensa_ae_cvta32f24s_l, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvtq56a32s: +return {Intrinsic::xtensa_ae_cvtq56a32s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvtq56p32s_h: +return {Intrinsic::xtensa_ae_cvtq56p32s_h, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_cvtq56p32s_l: +return {Intrinsic::xtensa_ae_cvtq56p32s_l, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_db: +return {Intrinsic::xtensa_ae_db, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_db_ic: +return {Intrinsic::xtensa_ae_db_ic, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_db_ip: +return {Intrinsic::xtensa_ae_db_ip, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_dbi: +return {Intrinsic::xtensa_ae_dbi, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_dbi_ic: +return {Intrinsic::xtensa_ae_dbi_ic, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_dbi_ip: +return {Intrinsic::xtensa_ae_dbi_ip, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_div64d32_h: +return {Intrinsic::xtensa_ae_div64d32_h, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_div64d32_l: +return {Intrinsic::xtensa_ae_div64d32_l, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_eq16: +return {Intrinsic::xtensa_ae_eq16, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_eq32: +return {Intrinsic::xtensa_ae_eq32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_eq64: +return {Intrinsic::xtensa_ae_eq64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16_i: +return {Intrinsic::xtensa_ae_l16_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16_ip: +return {Intrinsic::xtensa_ae_l16_ip, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16_x: +return {Intrinsic::xtensa_ae_l16_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16_xc: +return {Intrinsic::xtensa_ae_l16_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16_xp: +return {Intrinsic::xtensa_ae_l16_xp, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16m_i: +return {Intrinsic::xtensa_ae_l16m_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16m_iu: +return {Intrinsic::xtensa_ae_l16m_iu, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16m_x: +return {Intrinsic::xtensa_ae_l16m_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16m_xc: +return {Intrinsic::xtensa_ae_l16m_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16m_xu: +return {Intrinsic::xtensa_ae_l16m_xu, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16x2m_i: +return {Intrinsic::xtensa_ae_l16x2m_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16x2m_iu: +return {Intrinsic::xtensa_ae_l16x2m_iu, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16x2m_x: +return {Intrinsic::xtensa_ae_l16x2m_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16x2m_xc: +return {Intrinsic::xtensa_ae_l16x2m_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16x2m_xu: +return {Intrinsic::xtensa_ae_l16x2m_xu, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16x4_i: +return {Intrinsic::xtensa_ae_l16x4_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16x4_ip: +return {Intrinsic::xtensa_ae_l16x4_ip, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16x4_ric: +return {Intrinsic::xtensa_ae_l16x4_ric, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_l16x4_rip: +return {Intrinsic::xtensa_ae_l16x4_rip, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_l16x4_x: +return {Intrinsic::xtensa_ae_l16x4_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l16x4_xc: +return {Intrinsic::xtensa_ae_l16x4_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l16x4_xp: +return {Intrinsic::xtensa_ae_l16x4_xp, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32_i: +return {Intrinsic::xtensa_ae_l32_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32_ip: +return {Intrinsic::xtensa_ae_l32_ip, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32_x: +return {Intrinsic::xtensa_ae_l32_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32_xc: +return {Intrinsic::xtensa_ae_l32_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32_xp: +return {Intrinsic::xtensa_ae_l32_xp, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32f24_i: +return {Intrinsic::xtensa_ae_l32f24_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32f24_ip: +return {Intrinsic::xtensa_ae_l32f24_ip, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32f24_x: +return {Intrinsic::xtensa_ae_l32f24_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32f24_xc: +return {Intrinsic::xtensa_ae_l32f24_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32f24_xp: +return {Intrinsic::xtensa_ae_l32f24_xp, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32m_i: +return {Intrinsic::xtensa_ae_l32m_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32m_iu: +return {Intrinsic::xtensa_ae_l32m_iu, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32m_x: +return {Intrinsic::xtensa_ae_l32m_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32m_xc: +return {Intrinsic::xtensa_ae_l32m_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32m_xu: +return {Intrinsic::xtensa_ae_l32m_xu, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2_i: +return {Intrinsic::xtensa_ae_l32x2_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32x2_ip: +return {Intrinsic::xtensa_ae_l32x2_ip, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2_ric: +return {Intrinsic::xtensa_ae_l32x2_ric, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2_rip: +return {Intrinsic::xtensa_ae_l32x2_rip, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2_x: +return {Intrinsic::xtensa_ae_l32x2_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32x2_xc: +return {Intrinsic::xtensa_ae_l32x2_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2_xp: +return {Intrinsic::xtensa_ae_l32x2_xp, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_i: +return {Intrinsic::xtensa_ae_l32x2f24_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_ip: +return {Intrinsic::xtensa_ae_l32x2f24_ip, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_ric: +return {Intrinsic::xtensa_ae_l32x2f24_ric, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_rip: +return {Intrinsic::xtensa_ae_l32x2f24_rip, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_x: +return {Intrinsic::xtensa_ae_l32x2f24_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_xc: +return {Intrinsic::xtensa_ae_l32x2f24_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l32x2f24_xp: +return {Intrinsic::xtensa_ae_l32x2f24_xp, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l64_i: +return {Intrinsic::xtensa_ae_l64_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l64_ip: +return {Intrinsic::xtensa_ae_l64_ip, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l64_x: +return {Intrinsic::xtensa_ae_l64_x, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_l64_xc: +return {Intrinsic::xtensa_ae_l64_xc, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_l64_xp: +return {Intrinsic::xtensa_ae_l64_xp, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_la16x4_ic: +return {Intrinsic::xtensa_ae_la16x4_ic, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la16x4_ip: +return {Intrinsic::xtensa_ae_la16x4_ip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la16x4_ric: +return {Intrinsic::xtensa_ae_la16x4_ric, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la16x4_rip: +return {Intrinsic::xtensa_ae_la16x4_rip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la16x4neg_pc: +return {Intrinsic::xtensa_ae_la16x4neg_pc, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_la16x4pos_pc: +return {Intrinsic::xtensa_ae_la16x4pos_pc, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_la24_ic: +return {Intrinsic::xtensa_ae_la24_ic, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la24_ip: +return {Intrinsic::xtensa_ae_la24_ip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la24_ric: +return {Intrinsic::xtensa_ae_la24_ric, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la24_rip: +return {Intrinsic::xtensa_ae_la24_rip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la24neg_pc: +return {Intrinsic::xtensa_ae_la24neg_pc, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_la24pos_pc: +return {Intrinsic::xtensa_ae_la24pos_pc, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_la24x2_ic: +return {Intrinsic::xtensa_ae_la24x2_ic, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la24x2_ip: +return {Intrinsic::xtensa_ae_la24x2_ip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la24x2_ric: +return {Intrinsic::xtensa_ae_la24x2_ric, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la24x2_rip: +return {Intrinsic::xtensa_ae_la24x2_rip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la24x2neg_pc: +return {Intrinsic::xtensa_ae_la24x2neg_pc, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_la24x2pos_pc: +return {Intrinsic::xtensa_ae_la24x2pos_pc, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_la32x2_ic: +return {Intrinsic::xtensa_ae_la32x2_ic, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la32x2_ip: +return {Intrinsic::xtensa_ae_la32x2_ip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la32x2_ric: +return {Intrinsic::xtensa_ae_la32x2_ric, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la32x2_rip: +return {Intrinsic::xtensa_ae_la32x2_rip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la32x2f24_ic: +return {Intrinsic::xtensa_ae_la32x2f24_ic, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la32x2f24_ip: +return {Intrinsic::xtensa_ae_la32x2f24_ip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la32x2f24_ric: +return {Intrinsic::xtensa_ae_la32x2f24_ric, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la32x2f24_rip: +return {Intrinsic::xtensa_ae_la32x2f24_rip, 0, 0x601}; +case Xtensa::BI__builtin_xtensa_ae_la32x2neg_pc: +return {Intrinsic::xtensa_ae_la32x2neg_pc, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_la32x2pos_pc: +return {Intrinsic::xtensa_ae_la32x2pos_pc, 0, 0x201}; +case Xtensa::BI__builtin_xtensa_ae_la64_pp: +return {Intrinsic::xtensa_ae_la64_pp, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_lalign64_i: +return {Intrinsic::xtensa_ae_lalign64_i, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_lb: +return {Intrinsic::xtensa_ae_lb, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_lbi: +return {Intrinsic::xtensa_ae_lbi, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_lbk: +return {Intrinsic::xtensa_ae_lbk, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_lbki: +return {Intrinsic::xtensa_ae_lbki, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_lbs: +return {Intrinsic::xtensa_ae_lbs, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_lbsi: +return {Intrinsic::xtensa_ae_lbsi, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_le16: +return {Intrinsic::xtensa_ae_le16, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_le32: +return {Intrinsic::xtensa_ae_le32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_le64: +return {Intrinsic::xtensa_ae_le64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_lt16: +return {Intrinsic::xtensa_ae_lt16, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_lt32: +return {Intrinsic::xtensa_ae_lt32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_lt64: +return {Intrinsic::xtensa_ae_lt64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_max32: +return {Intrinsic::xtensa_ae_max32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_max64: +return {Intrinsic::xtensa_ae_max64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_maxabs32s: +return {Intrinsic::xtensa_ae_maxabs32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_maxabs64s: +return {Intrinsic::xtensa_ae_maxabs64s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_min32: +return {Intrinsic::xtensa_ae_min32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_min64: +return {Intrinsic::xtensa_ae_min64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_minabs32s: +return {Intrinsic::xtensa_ae_minabs32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_minabs64s: +return {Intrinsic::xtensa_ae_minabs64s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mov: +return {Intrinsic::xtensa_ae_mov, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movad16_0: +return {Intrinsic::xtensa_ae_movad16_0, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movad16_1: +return {Intrinsic::xtensa_ae_movad16_1, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movad16_2: +return {Intrinsic::xtensa_ae_movad16_2, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movad16_3: +return {Intrinsic::xtensa_ae_movad16_3, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movad32_h: +return {Intrinsic::xtensa_ae_movad32_h, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movad32_l: +return {Intrinsic::xtensa_ae_movad32_l, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movalign: +return {Intrinsic::xtensa_ae_movalign, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movda16: +return {Intrinsic::xtensa_ae_movda16, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movda16x2: +return {Intrinsic::xtensa_ae_movda16x2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_movda32: +return {Intrinsic::xtensa_ae_movda32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movda32x2: +return {Intrinsic::xtensa_ae_movda32x2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_movf16x4: +return {Intrinsic::xtensa_ae_movf16x4, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_movf32x2: +return {Intrinsic::xtensa_ae_movf32x2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_movf64: +return {Intrinsic::xtensa_ae_movf64, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_movi: +return {Intrinsic::xtensa_ae_movi, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_movt16x4: +return {Intrinsic::xtensa_ae_movt16x4, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_movt32x2: +return {Intrinsic::xtensa_ae_movt32x2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_movt64: +return {Intrinsic::xtensa_ae_movt64, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mul16x4: +return {Intrinsic::xtensa_ae_mul16x4, 0, 0xc0003}; +case Xtensa::BI__builtin_xtensa_ae_mul32_hh: +return {Intrinsic::xtensa_ae_mul32_hh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32_lh: +return {Intrinsic::xtensa_ae_mul32_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32_ll: +return {Intrinsic::xtensa_ae_mul32_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32_ll_s2: +return {Intrinsic::xtensa_ae_mul32_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32u_ll: +return {Intrinsic::xtensa_ae_mul32u_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_h0: +return {Intrinsic::xtensa_ae_mul32x16_h0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_h0_s2: +return {Intrinsic::xtensa_ae_mul32x16_h0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_h1: +return {Intrinsic::xtensa_ae_mul32x16_h1, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_h1_s2: +return {Intrinsic::xtensa_ae_mul32x16_h1_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_h2: +return {Intrinsic::xtensa_ae_mul32x16_h2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_h2_s2: +return {Intrinsic::xtensa_ae_mul32x16_h2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_h3: +return {Intrinsic::xtensa_ae_mul32x16_h3, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_h3_s2: +return {Intrinsic::xtensa_ae_mul32x16_h3_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_l0: +return {Intrinsic::xtensa_ae_mul32x16_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_l0_s2: +return {Intrinsic::xtensa_ae_mul32x16_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_l1: +return {Intrinsic::xtensa_ae_mul32x16_l1, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_l1_s2: +return {Intrinsic::xtensa_ae_mul32x16_l1_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_l2: +return {Intrinsic::xtensa_ae_mul32x16_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_l2_s2: +return {Intrinsic::xtensa_ae_mul32x16_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_l3: +return {Intrinsic::xtensa_ae_mul32x16_l3, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mul32x16_l3_s2: +return {Intrinsic::xtensa_ae_mul32x16_l3_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mula16x4: +return {Intrinsic::xtensa_ae_mula16x4, 0, 0xc0300}; +case Xtensa::BI__builtin_xtensa_ae_mula32_hh: +return {Intrinsic::xtensa_ae_mula32_hh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32_lh: +return {Intrinsic::xtensa_ae_mula32_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32_ll: +return {Intrinsic::xtensa_ae_mula32_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32_ll_s2: +return {Intrinsic::xtensa_ae_mula32_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32u_ll: +return {Intrinsic::xtensa_ae_mula32u_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_h0: +return {Intrinsic::xtensa_ae_mula32x16_h0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_h0_s2: +return {Intrinsic::xtensa_ae_mula32x16_h0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_h1: +return {Intrinsic::xtensa_ae_mula32x16_h1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_h1_s2: +return {Intrinsic::xtensa_ae_mula32x16_h1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_h2: +return {Intrinsic::xtensa_ae_mula32x16_h2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_h2_s2: +return {Intrinsic::xtensa_ae_mula32x16_h2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_h3: +return {Intrinsic::xtensa_ae_mula32x16_h3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_h3_s2: +return {Intrinsic::xtensa_ae_mula32x16_h3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_l0: +return {Intrinsic::xtensa_ae_mula32x16_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_l0_s2: +return {Intrinsic::xtensa_ae_mula32x16_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_l1: +return {Intrinsic::xtensa_ae_mula32x16_l1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_l1_s2: +return {Intrinsic::xtensa_ae_mula32x16_l1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_l2: +return {Intrinsic::xtensa_ae_mula32x16_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_l2_s2: +return {Intrinsic::xtensa_ae_mula32x16_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_l3: +return {Intrinsic::xtensa_ae_mula32x16_l3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mula32x16_l3_s2: +return {Intrinsic::xtensa_ae_mula32x16_l3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad24_hh_ll: +return {Intrinsic::xtensa_ae_mulaad24_hh_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulaad24_hh_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad24_hl_lh: +return {Intrinsic::xtensa_ae_mulaad24_hl_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulaad24_hl_lh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad32x16_h0_l1: +return {Intrinsic::xtensa_ae_mulaad32x16_h0_l1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad32x16_h0_l1_s2: +return {Intrinsic::xtensa_ae_mulaad32x16_h0_l1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulaad32x16_h1_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulaad32x16_h1_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad32x16_h2_l3: +return {Intrinsic::xtensa_ae_mulaad32x16_h2_l3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad32x16_h2_l3_s2: +return {Intrinsic::xtensa_ae_mulaad32x16_h2_l3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulaad32x16_h3_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaad32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulaad32x16_h3_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd16ss_11_00: +return {Intrinsic::xtensa_ae_mulaafd16ss_11_00, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd16ss_11_00_s2: +return {Intrinsic::xtensa_ae_mulaafd16ss_11_00_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd16ss_13_02: +return {Intrinsic::xtensa_ae_mulaafd16ss_13_02, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd16ss_13_02_s2: +return {Intrinsic::xtensa_ae_mulaafd16ss_13_02_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd16ss_33_22: +return {Intrinsic::xtensa_ae_mulaafd16ss_33_22, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd16ss_33_22_s2: +return {Intrinsic::xtensa_ae_mulaafd16ss_33_22_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd24_hh_ll: +return {Intrinsic::xtensa_ae_mulaafd24_hh_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulaafd24_hh_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd24_hl_lh: +return {Intrinsic::xtensa_ae_mulaafd24_hl_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulaafd24_hl_lh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd32x16_h0_l1: +return {Intrinsic::xtensa_ae_mulaafd32x16_h0_l1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd32x16_h0_l1_s2: +return {Intrinsic::xtensa_ae_mulaafd32x16_h0_l1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulaafd32x16_h1_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulaafd32x16_h1_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd32x16_h2_l3: +return {Intrinsic::xtensa_ae_mulaafd32x16_h2_l3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd32x16_h2_l3_s2: +return {Intrinsic::xtensa_ae_mulaafd32x16_h2_l3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulaafd32x16_h3_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaafd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulaafd32x16_h3_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulac24: +return {Intrinsic::xtensa_ae_mulac24, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulac32x16_h: +return {Intrinsic::xtensa_ae_mulac32x16_h, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulac32x16_l: +return {Intrinsic::xtensa_ae_mulac32x16_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_00: +return {Intrinsic::xtensa_ae_mulaf16ss_00, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_00_s2: +return {Intrinsic::xtensa_ae_mulaf16ss_00_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_10: +return {Intrinsic::xtensa_ae_mulaf16ss_10, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_11: +return {Intrinsic::xtensa_ae_mulaf16ss_11, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_20: +return {Intrinsic::xtensa_ae_mulaf16ss_20, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_21: +return {Intrinsic::xtensa_ae_mulaf16ss_21, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_22: +return {Intrinsic::xtensa_ae_mulaf16ss_22, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_30: +return {Intrinsic::xtensa_ae_mulaf16ss_30, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_31: +return {Intrinsic::xtensa_ae_mulaf16ss_31, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_32: +return {Intrinsic::xtensa_ae_mulaf16ss_32, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16ss_33: +return {Intrinsic::xtensa_ae_mulaf16ss_33, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf16x4ss: +return {Intrinsic::xtensa_ae_mulaf16x4ss, 0, 0xc0300}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32r_hh: +return {Intrinsic::xtensa_ae_mulaf32r_hh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32r_lh: +return {Intrinsic::xtensa_ae_mulaf32r_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32r_ll: +return {Intrinsic::xtensa_ae_mulaf32r_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32r_ll_s2: +return {Intrinsic::xtensa_ae_mulaf32r_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32s_hh: +return {Intrinsic::xtensa_ae_mulaf32s_hh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32s_lh: +return {Intrinsic::xtensa_ae_mulaf32s_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32s_ll: +return {Intrinsic::xtensa_ae_mulaf32s_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32s_ll_s2: +return {Intrinsic::xtensa_ae_mulaf32s_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_h0: +return {Intrinsic::xtensa_ae_mulaf32x16_h0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_h0_s2: +return {Intrinsic::xtensa_ae_mulaf32x16_h0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_h1: +return {Intrinsic::xtensa_ae_mulaf32x16_h1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_h1_s2: +return {Intrinsic::xtensa_ae_mulaf32x16_h1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_h2: +return {Intrinsic::xtensa_ae_mulaf32x16_h2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_h2_s2: +return {Intrinsic::xtensa_ae_mulaf32x16_h2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_h3: +return {Intrinsic::xtensa_ae_mulaf32x16_h3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_h3_s2: +return {Intrinsic::xtensa_ae_mulaf32x16_h3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_l0: +return {Intrinsic::xtensa_ae_mulaf32x16_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_l0_s2: +return {Intrinsic::xtensa_ae_mulaf32x16_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_l1: +return {Intrinsic::xtensa_ae_mulaf32x16_l1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_l1_s2: +return {Intrinsic::xtensa_ae_mulaf32x16_l1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_l2: +return {Intrinsic::xtensa_ae_mulaf32x16_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_l2_s2: +return {Intrinsic::xtensa_ae_mulaf32x16_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_l3: +return {Intrinsic::xtensa_ae_mulaf32x16_l3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf32x16_l3_s2: +return {Intrinsic::xtensa_ae_mulaf32x16_l3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf48q32sp16s_l: +return {Intrinsic::xtensa_ae_mulaf48q32sp16s_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf48q32sp16s_l_s2: +return {Intrinsic::xtensa_ae_mulaf48q32sp16s_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf48q32sp16u_l: +return {Intrinsic::xtensa_ae_mulaf48q32sp16u_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaf48q32sp16u_l_s2: +return {Intrinsic::xtensa_ae_mulaf48q32sp16u_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafc24ra: +return {Intrinsic::xtensa_ae_mulafc24ra, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafc32x16ras_h: +return {Intrinsic::xtensa_ae_mulafc32x16ras_h, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafc32x16ras_l: +return {Intrinsic::xtensa_ae_mulafc32x16ras_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafd24x2_fir_h: +return {Intrinsic::xtensa_ae_mulafd24x2_fir_h, 0, 0x1c0300}; +case Xtensa::BI__builtin_xtensa_ae_mulafd24x2_fir_l: +return {Intrinsic::xtensa_ae_mulafd24x2_fir_l, 0, 0x1c0300}; +case Xtensa::BI__builtin_xtensa_ae_mulafd32x16x2_fir_hh: +return {Intrinsic::xtensa_ae_mulafd32x16x2_fir_hh, 0, 0x1c0300}; +case Xtensa::BI__builtin_xtensa_ae_mulafd32x16x2_fir_hl: +return {Intrinsic::xtensa_ae_mulafd32x16x2_fir_hl, 0, 0x1c0300}; +case Xtensa::BI__builtin_xtensa_ae_mulafd32x16x2_fir_lh: +return {Intrinsic::xtensa_ae_mulafd32x16x2_fir_lh, 0, 0x1c0300}; +case Xtensa::BI__builtin_xtensa_ae_mulafd32x16x2_fir_ll: +return {Intrinsic::xtensa_ae_mulafd32x16x2_fir_ll, 0, 0x1c0300}; +case Xtensa::BI__builtin_xtensa_ae_mulafp24x2r: +return {Intrinsic::xtensa_ae_mulafp24x2r, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp24x2r_s2: +return {Intrinsic::xtensa_ae_mulafp24x2r_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp24x2ra: +return {Intrinsic::xtensa_ae_mulafp24x2ra, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp24x2ra_s2: +return {Intrinsic::xtensa_ae_mulafp24x2ra_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x16x2ras_h: +return {Intrinsic::xtensa_ae_mulafp32x16x2ras_h, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x16x2ras_h_s2: +return {Intrinsic::xtensa_ae_mulafp32x16x2ras_h_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x16x2ras_l: +return {Intrinsic::xtensa_ae_mulafp32x16x2ras_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x16x2ras_l_s2: +return {Intrinsic::xtensa_ae_mulafp32x16x2ras_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x16x2rs_h: +return {Intrinsic::xtensa_ae_mulafp32x16x2rs_h, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x16x2rs_h_s2: +return {Intrinsic::xtensa_ae_mulafp32x16x2rs_h_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x16x2rs_l: +return {Intrinsic::xtensa_ae_mulafp32x16x2rs_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x16x2rs_l_s2: +return {Intrinsic::xtensa_ae_mulafp32x16x2rs_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x2ras: +return {Intrinsic::xtensa_ae_mulafp32x2ras, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafp32x2rs: +return {Intrinsic::xtensa_ae_mulafp32x2rs, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafq32sp24s_h_s2: +return {Intrinsic::xtensa_ae_mulafq32sp24s_h_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulafq32sp24s_l_s2: +return {Intrinsic::xtensa_ae_mulafq32sp24s_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulap24x2: +return {Intrinsic::xtensa_ae_mulap24x2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulap24x2_s2: +return {Intrinsic::xtensa_ae_mulap24x2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulap32x16x2_h: +return {Intrinsic::xtensa_ae_mulap32x16x2_h, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulap32x16x2_l: +return {Intrinsic::xtensa_ae_mulap32x16x2_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulap32x2: +return {Intrinsic::xtensa_ae_mulap32x2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaq32sp16s_l_s2: +return {Intrinsic::xtensa_ae_mulaq32sp16s_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulaq32sp16u_l_s2: +return {Intrinsic::xtensa_ae_mulaq32sp16u_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mularfq32sp24s_h_s2: +return {Intrinsic::xtensa_ae_mularfq32sp24s_h_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mularfq32sp24s_l_s2: +return {Intrinsic::xtensa_ae_mularfq32sp24s_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulas32f48p16s_hh: +return {Intrinsic::xtensa_ae_mulas32f48p16s_hh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulas32f48p16s_hh_s2: +return {Intrinsic::xtensa_ae_mulas32f48p16s_hh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulas32f48p16s_lh: +return {Intrinsic::xtensa_ae_mulas32f48p16s_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulas32f48p16s_lh_s2: +return {Intrinsic::xtensa_ae_mulas32f48p16s_lh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulas32f48p16s_ll: +return {Intrinsic::xtensa_ae_mulas32f48p16s_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulas32f48p16s_ll_s2: +return {Intrinsic::xtensa_ae_mulas32f48p16s_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasd24_hh_ll: +return {Intrinsic::xtensa_ae_mulasd24_hh_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulasd24_hh_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasd24_hl_lh: +return {Intrinsic::xtensa_ae_mulasd24_hl_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulasd24_hl_lh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulasd32x16_h1_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulasd32x16_h1_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulasd32x16_h3_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulasd32x16_h3_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasfd24_hh_ll: +return {Intrinsic::xtensa_ae_mulasfd24_hh_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasfd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulasfd24_hh_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasfd24_hl_lh: +return {Intrinsic::xtensa_ae_mulasfd24_hl_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasfd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulasfd24_hl_lh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasfd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulasfd32x16_h1_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasfd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulasfd32x16_h1_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasfd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulasfd32x16_h3_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulasfd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulasfd32x16_h3_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulc24: +return {Intrinsic::xtensa_ae_mulc24, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulc32x16_h: +return {Intrinsic::xtensa_ae_mulc32x16_h, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulc32x16_l: +return {Intrinsic::xtensa_ae_mulc32x16_l, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_00: +return {Intrinsic::xtensa_ae_mulf16ss_00, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_00_s2: +return {Intrinsic::xtensa_ae_mulf16ss_00_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_10: +return {Intrinsic::xtensa_ae_mulf16ss_10, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_11: +return {Intrinsic::xtensa_ae_mulf16ss_11, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_20: +return {Intrinsic::xtensa_ae_mulf16ss_20, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_21: +return {Intrinsic::xtensa_ae_mulf16ss_21, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_22: +return {Intrinsic::xtensa_ae_mulf16ss_22, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_30: +return {Intrinsic::xtensa_ae_mulf16ss_30, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_31: +return {Intrinsic::xtensa_ae_mulf16ss_31, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_32: +return {Intrinsic::xtensa_ae_mulf16ss_32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16ss_33: +return {Intrinsic::xtensa_ae_mulf16ss_33, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf16x4ss: +return {Intrinsic::xtensa_ae_mulf16x4ss, 0, 0xc0003}; +case Xtensa::BI__builtin_xtensa_ae_mulf32r_hh: +return {Intrinsic::xtensa_ae_mulf32r_hh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32r_lh: +return {Intrinsic::xtensa_ae_mulf32r_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32r_ll: +return {Intrinsic::xtensa_ae_mulf32r_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32r_ll_s2: +return {Intrinsic::xtensa_ae_mulf32r_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32s_hh: +return {Intrinsic::xtensa_ae_mulf32s_hh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32s_lh: +return {Intrinsic::xtensa_ae_mulf32s_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32s_ll: +return {Intrinsic::xtensa_ae_mulf32s_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32s_ll_s2: +return {Intrinsic::xtensa_ae_mulf32s_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_h0: +return {Intrinsic::xtensa_ae_mulf32x16_h0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_h0_s2: +return {Intrinsic::xtensa_ae_mulf32x16_h0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_h1: +return {Intrinsic::xtensa_ae_mulf32x16_h1, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_h1_s2: +return {Intrinsic::xtensa_ae_mulf32x16_h1_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_h2: +return {Intrinsic::xtensa_ae_mulf32x16_h2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_h2_s2: +return {Intrinsic::xtensa_ae_mulf32x16_h2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_h3: +return {Intrinsic::xtensa_ae_mulf32x16_h3, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_h3_s2: +return {Intrinsic::xtensa_ae_mulf32x16_h3_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_l0: +return {Intrinsic::xtensa_ae_mulf32x16_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_l0_s2: +return {Intrinsic::xtensa_ae_mulf32x16_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_l1: +return {Intrinsic::xtensa_ae_mulf32x16_l1, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_l1_s2: +return {Intrinsic::xtensa_ae_mulf32x16_l1_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_l2: +return {Intrinsic::xtensa_ae_mulf32x16_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_l2_s2: +return {Intrinsic::xtensa_ae_mulf32x16_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_l3: +return {Intrinsic::xtensa_ae_mulf32x16_l3, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf32x16_l3_s2: +return {Intrinsic::xtensa_ae_mulf32x16_l3_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf48q32sp16s_l: +return {Intrinsic::xtensa_ae_mulf48q32sp16s_l, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf48q32sp16s_l_s2: +return {Intrinsic::xtensa_ae_mulf48q32sp16s_l_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf48q32sp16u_l: +return {Intrinsic::xtensa_ae_mulf48q32sp16u_l, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulf48q32sp16u_l_s2: +return {Intrinsic::xtensa_ae_mulf48q32sp16u_l_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfc24ra: +return {Intrinsic::xtensa_ae_mulfc24ra, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfc32x16ras_h: +return {Intrinsic::xtensa_ae_mulfc32x16ras_h, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfc32x16ras_l: +return {Intrinsic::xtensa_ae_mulfc32x16ras_l, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfd24x2_fir_h: +return {Intrinsic::xtensa_ae_mulfd24x2_fir_h, 0, 0x1c0003}; +case Xtensa::BI__builtin_xtensa_ae_mulfd24x2_fir_l: +return {Intrinsic::xtensa_ae_mulfd24x2_fir_l, 0, 0x1c0003}; +case Xtensa::BI__builtin_xtensa_ae_mulfd32x16x2_fir_hh: +return {Intrinsic::xtensa_ae_mulfd32x16x2_fir_hh, 0, 0x1c0003}; +case Xtensa::BI__builtin_xtensa_ae_mulfd32x16x2_fir_hl: +return {Intrinsic::xtensa_ae_mulfd32x16x2_fir_hl, 0, 0x1c0003}; +case Xtensa::BI__builtin_xtensa_ae_mulfd32x16x2_fir_lh: +return {Intrinsic::xtensa_ae_mulfd32x16x2_fir_lh, 0, 0x1c0003}; +case Xtensa::BI__builtin_xtensa_ae_mulfd32x16x2_fir_ll: +return {Intrinsic::xtensa_ae_mulfd32x16x2_fir_ll, 0, 0x1c0003}; +case Xtensa::BI__builtin_xtensa_ae_mulfp16x4ras: +return {Intrinsic::xtensa_ae_mulfp16x4ras, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp16x4s: +return {Intrinsic::xtensa_ae_mulfp16x4s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp24x2r: +return {Intrinsic::xtensa_ae_mulfp24x2r, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp24x2r_s2: +return {Intrinsic::xtensa_ae_mulfp24x2r_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp24x2ra: +return {Intrinsic::xtensa_ae_mulfp24x2ra, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp24x2ra_s2: +return {Intrinsic::xtensa_ae_mulfp24x2ra_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x16x2ras_h: +return {Intrinsic::xtensa_ae_mulfp32x16x2ras_h, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x16x2ras_h_s2: +return {Intrinsic::xtensa_ae_mulfp32x16x2ras_h_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x16x2ras_l: +return {Intrinsic::xtensa_ae_mulfp32x16x2ras_l, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x16x2ras_l_s2: +return {Intrinsic::xtensa_ae_mulfp32x16x2ras_l_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x16x2rs_h: +return {Intrinsic::xtensa_ae_mulfp32x16x2rs_h, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x16x2rs_h_s2: +return {Intrinsic::xtensa_ae_mulfp32x16x2rs_h_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x16x2rs_l: +return {Intrinsic::xtensa_ae_mulfp32x16x2rs_l, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x16x2rs_l_s2: +return {Intrinsic::xtensa_ae_mulfp32x16x2rs_l_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x2ras: +return {Intrinsic::xtensa_ae_mulfp32x2ras, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfp32x2rs: +return {Intrinsic::xtensa_ae_mulfp32x2rs, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfq32sp24s_h_s2: +return {Intrinsic::xtensa_ae_mulfq32sp24s_h_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulfq32sp24s_l_s2: +return {Intrinsic::xtensa_ae_mulfq32sp24s_l_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulp24x2: +return {Intrinsic::xtensa_ae_mulp24x2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulp24x2_s2: +return {Intrinsic::xtensa_ae_mulp24x2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulp32x16x2_h: +return {Intrinsic::xtensa_ae_mulp32x16x2_h, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulp32x16x2_l: +return {Intrinsic::xtensa_ae_mulp32x16x2_l, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulp32x2: +return {Intrinsic::xtensa_ae_mulp32x2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulq32sp16s_l_s2: +return {Intrinsic::xtensa_ae_mulq32sp16s_l_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulq32sp16u_l_s2: +return {Intrinsic::xtensa_ae_mulq32sp16u_l_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulrfq32sp24s_h_s2: +return {Intrinsic::xtensa_ae_mulrfq32sp24s_h_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulrfq32sp24s_l_s2: +return {Intrinsic::xtensa_ae_mulrfq32sp24s_l_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_muls16x4: +return {Intrinsic::xtensa_ae_muls16x4, 0, 0xc0300}; +case Xtensa::BI__builtin_xtensa_ae_muls32_hh: +return {Intrinsic::xtensa_ae_muls32_hh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32_lh: +return {Intrinsic::xtensa_ae_muls32_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32_ll: +return {Intrinsic::xtensa_ae_muls32_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32f48p16s_hh: +return {Intrinsic::xtensa_ae_muls32f48p16s_hh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_muls32f48p16s_hh_s2: +return {Intrinsic::xtensa_ae_muls32f48p16s_hh_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_muls32f48p16s_lh: +return {Intrinsic::xtensa_ae_muls32f48p16s_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_muls32f48p16s_lh_s2: +return {Intrinsic::xtensa_ae_muls32f48p16s_lh_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_muls32f48p16s_ll: +return {Intrinsic::xtensa_ae_muls32f48p16s_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_muls32f48p16s_ll_s2: +return {Intrinsic::xtensa_ae_muls32f48p16s_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_muls32u_ll: +return {Intrinsic::xtensa_ae_muls32u_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_h0: +return {Intrinsic::xtensa_ae_muls32x16_h0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_h0_s2: +return {Intrinsic::xtensa_ae_muls32x16_h0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_h1: +return {Intrinsic::xtensa_ae_muls32x16_h1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_h1_s2: +return {Intrinsic::xtensa_ae_muls32x16_h1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_h2: +return {Intrinsic::xtensa_ae_muls32x16_h2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_h2_s2: +return {Intrinsic::xtensa_ae_muls32x16_h2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_h3: +return {Intrinsic::xtensa_ae_muls32x16_h3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_h3_s2: +return {Intrinsic::xtensa_ae_muls32x16_h3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_l0: +return {Intrinsic::xtensa_ae_muls32x16_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_l0_s2: +return {Intrinsic::xtensa_ae_muls32x16_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_l1: +return {Intrinsic::xtensa_ae_muls32x16_l1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_l1_s2: +return {Intrinsic::xtensa_ae_muls32x16_l1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_l2: +return {Intrinsic::xtensa_ae_muls32x16_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_l2_s2: +return {Intrinsic::xtensa_ae_muls32x16_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_l3: +return {Intrinsic::xtensa_ae_muls32x16_l3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_muls32x16_l3_s2: +return {Intrinsic::xtensa_ae_muls32x16_l3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsad24_hh_ll: +return {Intrinsic::xtensa_ae_mulsad24_hh_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsad24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulsad24_hh_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsad32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulsad32x16_h1_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsad32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulsad32x16_h1_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsad32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulsad32x16_h3_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsad32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulsad32x16_h3_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsafd24_hh_ll: +return {Intrinsic::xtensa_ae_mulsafd24_hh_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsafd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulsafd24_hh_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsafd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulsafd32x16_h1_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsafd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulsafd32x16_h1_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsafd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulsafd32x16_h3_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsafd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulsafd32x16_h3_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_00: +return {Intrinsic::xtensa_ae_mulsf16ss_00, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_00_s2: +return {Intrinsic::xtensa_ae_mulsf16ss_00_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_10: +return {Intrinsic::xtensa_ae_mulsf16ss_10, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_11: +return {Intrinsic::xtensa_ae_mulsf16ss_11, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_20: +return {Intrinsic::xtensa_ae_mulsf16ss_20, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_21: +return {Intrinsic::xtensa_ae_mulsf16ss_21, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_22: +return {Intrinsic::xtensa_ae_mulsf16ss_22, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_30: +return {Intrinsic::xtensa_ae_mulsf16ss_30, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_31: +return {Intrinsic::xtensa_ae_mulsf16ss_31, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_32: +return {Intrinsic::xtensa_ae_mulsf16ss_32, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16ss_33: +return {Intrinsic::xtensa_ae_mulsf16ss_33, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf16x4ss: +return {Intrinsic::xtensa_ae_mulsf16x4ss, 0, 0xc0300}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32r_hh: +return {Intrinsic::xtensa_ae_mulsf32r_hh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32r_lh: +return {Intrinsic::xtensa_ae_mulsf32r_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32r_ll: +return {Intrinsic::xtensa_ae_mulsf32r_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32r_ll_s2: +return {Intrinsic::xtensa_ae_mulsf32r_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32s_hh: +return {Intrinsic::xtensa_ae_mulsf32s_hh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32s_lh: +return {Intrinsic::xtensa_ae_mulsf32s_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32s_ll: +return {Intrinsic::xtensa_ae_mulsf32s_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_h0: +return {Intrinsic::xtensa_ae_mulsf32x16_h0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_h0_s2: +return {Intrinsic::xtensa_ae_mulsf32x16_h0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_h1: +return {Intrinsic::xtensa_ae_mulsf32x16_h1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_h1_s2: +return {Intrinsic::xtensa_ae_mulsf32x16_h1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_h2: +return {Intrinsic::xtensa_ae_mulsf32x16_h2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_h2_s2: +return {Intrinsic::xtensa_ae_mulsf32x16_h2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_h3: +return {Intrinsic::xtensa_ae_mulsf32x16_h3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_h3_s2: +return {Intrinsic::xtensa_ae_mulsf32x16_h3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_l0: +return {Intrinsic::xtensa_ae_mulsf32x16_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_l0_s2: +return {Intrinsic::xtensa_ae_mulsf32x16_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_l1: +return {Intrinsic::xtensa_ae_mulsf32x16_l1, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_l1_s2: +return {Intrinsic::xtensa_ae_mulsf32x16_l1_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_l2: +return {Intrinsic::xtensa_ae_mulsf32x16_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_l2_s2: +return {Intrinsic::xtensa_ae_mulsf32x16_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_l3: +return {Intrinsic::xtensa_ae_mulsf32x16_l3, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf32x16_l3_s2: +return {Intrinsic::xtensa_ae_mulsf32x16_l3_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf48q32sp16s_l: +return {Intrinsic::xtensa_ae_mulsf48q32sp16s_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf48q32sp16s_l_s2: +return {Intrinsic::xtensa_ae_mulsf48q32sp16s_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf48q32sp16u_l: +return {Intrinsic::xtensa_ae_mulsf48q32sp16u_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsf48q32sp16u_l_s2: +return {Intrinsic::xtensa_ae_mulsf48q32sp16u_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp24x2r: +return {Intrinsic::xtensa_ae_mulsfp24x2r, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp24x2r_s2: +return {Intrinsic::xtensa_ae_mulsfp24x2r_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp24x2ra: +return {Intrinsic::xtensa_ae_mulsfp24x2ra, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp24x2ra_s2: +return {Intrinsic::xtensa_ae_mulsfp24x2ra_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x16x2ras_h: +return {Intrinsic::xtensa_ae_mulsfp32x16x2ras_h, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x16x2ras_h_s2: +return {Intrinsic::xtensa_ae_mulsfp32x16x2ras_h_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x16x2ras_l: +return {Intrinsic::xtensa_ae_mulsfp32x16x2ras_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x16x2ras_l_s2: +return {Intrinsic::xtensa_ae_mulsfp32x16x2ras_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x16x2rs_h: +return {Intrinsic::xtensa_ae_mulsfp32x16x2rs_h, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x16x2rs_h_s2: +return {Intrinsic::xtensa_ae_mulsfp32x16x2rs_h_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x16x2rs_l: +return {Intrinsic::xtensa_ae_mulsfp32x16x2rs_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x16x2rs_l_s2: +return {Intrinsic::xtensa_ae_mulsfp32x16x2rs_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x2ras: +return {Intrinsic::xtensa_ae_mulsfp32x2ras, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfp32x2rs: +return {Intrinsic::xtensa_ae_mulsfp32x2rs, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfq32sp24s_h_s2: +return {Intrinsic::xtensa_ae_mulsfq32sp24s_h_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsfq32sp24s_l_s2: +return {Intrinsic::xtensa_ae_mulsfq32sp24s_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsp24x2: +return {Intrinsic::xtensa_ae_mulsp24x2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsp24x2_s2: +return {Intrinsic::xtensa_ae_mulsp24x2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsp32x16x2_h: +return {Intrinsic::xtensa_ae_mulsp32x16x2_h, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsp32x16x2_l: +return {Intrinsic::xtensa_ae_mulsp32x16x2_l, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsp32x2: +return {Intrinsic::xtensa_ae_mulsp32x2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsq32sp16s_l_s2: +return {Intrinsic::xtensa_ae_mulsq32sp16s_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsq32sp16u_l_s2: +return {Intrinsic::xtensa_ae_mulsq32sp16u_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsrfq32sp24s_h_s2: +return {Intrinsic::xtensa_ae_mulsrfq32sp24s_h_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulsrfq32sp24s_l_s2: +return {Intrinsic::xtensa_ae_mulsrfq32sp24s_l_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulss32f48p16s_hh: +return {Intrinsic::xtensa_ae_mulss32f48p16s_hh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulss32f48p16s_hh_s2: +return {Intrinsic::xtensa_ae_mulss32f48p16s_hh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulss32f48p16s_lh: +return {Intrinsic::xtensa_ae_mulss32f48p16s_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulss32f48p16s_lh_s2: +return {Intrinsic::xtensa_ae_mulss32f48p16s_lh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulss32f48p16s_ll: +return {Intrinsic::xtensa_ae_mulss32f48p16s_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulss32f48p16s_ll_s2: +return {Intrinsic::xtensa_ae_mulss32f48p16s_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssd24_hh_ll: +return {Intrinsic::xtensa_ae_mulssd24_hh_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulssd24_hh_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssd24_hl_lh: +return {Intrinsic::xtensa_ae_mulssd24_hl_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulssd24_hl_lh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulssd32x16_h1_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulssd32x16_h1_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulssd32x16_h3_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulssd32x16_h3_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd16ss_11_00: +return {Intrinsic::xtensa_ae_mulssfd16ss_11_00, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd16ss_11_00_s2: +return {Intrinsic::xtensa_ae_mulssfd16ss_11_00_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd16ss_13_02: +return {Intrinsic::xtensa_ae_mulssfd16ss_13_02, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd16ss_13_02_s2: +return {Intrinsic::xtensa_ae_mulssfd16ss_13_02_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd16ss_33_22: +return {Intrinsic::xtensa_ae_mulssfd16ss_33_22, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd16ss_33_22_s2: +return {Intrinsic::xtensa_ae_mulssfd16ss_33_22_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd24_hh_ll: +return {Intrinsic::xtensa_ae_mulssfd24_hh_ll, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulssfd24_hh_ll_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd24_hl_lh: +return {Intrinsic::xtensa_ae_mulssfd24_hl_lh, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulssfd24_hl_lh_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulssfd32x16_h1_l0, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulssfd32x16_h1_l0_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulssfd32x16_h3_l2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulssfd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulssfd32x16_h3_l2_s2, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad24_hh_ll: +return {Intrinsic::xtensa_ae_mulzaad24_hh_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulzaad24_hh_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad24_hl_lh: +return {Intrinsic::xtensa_ae_mulzaad24_hl_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulzaad24_hl_lh_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad32x16_h0_l1: +return {Intrinsic::xtensa_ae_mulzaad32x16_h0_l1, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad32x16_h0_l1_s2: +return {Intrinsic::xtensa_ae_mulzaad32x16_h0_l1_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulzaad32x16_h1_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulzaad32x16_h1_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad32x16_h2_l3: +return {Intrinsic::xtensa_ae_mulzaad32x16_h2_l3, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad32x16_h2_l3_s2: +return {Intrinsic::xtensa_ae_mulzaad32x16_h2_l3_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulzaad32x16_h3_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaad32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulzaad32x16_h3_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd16ss_11_00: +return {Intrinsic::xtensa_ae_mulzaafd16ss_11_00, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd16ss_11_00_s2: +return {Intrinsic::xtensa_ae_mulzaafd16ss_11_00_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd16ss_13_02: +return {Intrinsic::xtensa_ae_mulzaafd16ss_13_02, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd16ss_13_02_s2: +return {Intrinsic::xtensa_ae_mulzaafd16ss_13_02_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd16ss_33_22: +return {Intrinsic::xtensa_ae_mulzaafd16ss_33_22, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd16ss_33_22_s2: +return {Intrinsic::xtensa_ae_mulzaafd16ss_33_22_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd24_hh_ll: +return {Intrinsic::xtensa_ae_mulzaafd24_hh_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulzaafd24_hh_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd24_hl_lh: +return {Intrinsic::xtensa_ae_mulzaafd24_hl_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulzaafd24_hl_lh_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd32x16_h0_l1: +return {Intrinsic::xtensa_ae_mulzaafd32x16_h0_l1, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd32x16_h0_l1_s2: +return {Intrinsic::xtensa_ae_mulzaafd32x16_h0_l1_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulzaafd32x16_h1_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulzaafd32x16_h1_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd32x16_h2_l3: +return {Intrinsic::xtensa_ae_mulzaafd32x16_h2_l3, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd32x16_h2_l3_s2: +return {Intrinsic::xtensa_ae_mulzaafd32x16_h2_l3_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulzaafd32x16_h3_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzaafd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulzaafd32x16_h3_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasd24_hh_ll: +return {Intrinsic::xtensa_ae_mulzasd24_hh_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulzasd24_hh_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasd24_hl_lh: +return {Intrinsic::xtensa_ae_mulzasd24_hl_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulzasd24_hl_lh_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulzasd32x16_h1_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulzasd32x16_h1_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulzasd32x16_h3_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulzasd32x16_h3_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasfd24_hh_ll: +return {Intrinsic::xtensa_ae_mulzasfd24_hh_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasfd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulzasfd24_hh_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasfd24_hl_lh: +return {Intrinsic::xtensa_ae_mulzasfd24_hl_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasfd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulzasfd24_hl_lh_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasfd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulzasfd32x16_h1_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasfd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulzasfd32x16_h1_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasfd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulzasfd32x16_h3_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzasfd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulzasfd32x16_h3_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsad24_hh_ll: +return {Intrinsic::xtensa_ae_mulzsad24_hh_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsad24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulzsad24_hh_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsad32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulzsad32x16_h1_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsad32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulzsad32x16_h1_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsad32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulzsad32x16_h3_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsad32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulzsad32x16_h3_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsafd24_hh_ll: +return {Intrinsic::xtensa_ae_mulzsafd24_hh_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsafd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulzsafd24_hh_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsafd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulzsafd32x16_h1_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsafd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulzsafd32x16_h1_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsafd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulzsafd32x16_h3_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzsafd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulzsafd32x16_h3_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssd24_hh_ll: +return {Intrinsic::xtensa_ae_mulzssd24_hh_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulzssd24_hh_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssd24_hl_lh: +return {Intrinsic::xtensa_ae_mulzssd24_hl_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulzssd24_hl_lh_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulzssd32x16_h1_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulzssd32x16_h1_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulzssd32x16_h3_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulzssd32x16_h3_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd16ss_11_00: +return {Intrinsic::xtensa_ae_mulzssfd16ss_11_00, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd16ss_11_00_s2: +return {Intrinsic::xtensa_ae_mulzssfd16ss_11_00_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd16ss_13_02: +return {Intrinsic::xtensa_ae_mulzssfd16ss_13_02, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd16ss_13_02_s2: +return {Intrinsic::xtensa_ae_mulzssfd16ss_13_02_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd16ss_33_22: +return {Intrinsic::xtensa_ae_mulzssfd16ss_33_22, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd16ss_33_22_s2: +return {Intrinsic::xtensa_ae_mulzssfd16ss_33_22_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd24_hh_ll: +return {Intrinsic::xtensa_ae_mulzssfd24_hh_ll, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd24_hh_ll_s2: +return {Intrinsic::xtensa_ae_mulzssfd24_hh_ll_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd24_hl_lh: +return {Intrinsic::xtensa_ae_mulzssfd24_hl_lh, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd24_hl_lh_s2: +return {Intrinsic::xtensa_ae_mulzssfd24_hl_lh_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd32x16_h1_l0: +return {Intrinsic::xtensa_ae_mulzssfd32x16_h1_l0, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd32x16_h1_l0_s2: +return {Intrinsic::xtensa_ae_mulzssfd32x16_h1_l0_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd32x16_h3_l2: +return {Intrinsic::xtensa_ae_mulzssfd32x16_h3_l2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_mulzssfd32x16_h3_l2_s2: +return {Intrinsic::xtensa_ae_mulzssfd32x16_h3_l2_s2, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_nand: +return {Intrinsic::xtensa_ae_nand, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_neg16s: +return {Intrinsic::xtensa_ae_neg16s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_neg24s: +return {Intrinsic::xtensa_ae_neg24s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_neg32: +return {Intrinsic::xtensa_ae_neg32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_neg32s: +return {Intrinsic::xtensa_ae_neg32s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_neg64: +return {Intrinsic::xtensa_ae_neg64, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_neg64s: +return {Intrinsic::xtensa_ae_neg64s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_nsa64: +return {Intrinsic::xtensa_ae_nsa64, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_nsaz16_0: +return {Intrinsic::xtensa_ae_nsaz16_0, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_nsaz32_l: +return {Intrinsic::xtensa_ae_nsaz32_l, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_or: +return {Intrinsic::xtensa_ae_or, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_pksr24: +return {Intrinsic::xtensa_ae_pksr24, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_pksr32: +return {Intrinsic::xtensa_ae_pksr32, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_round16x4f32sasym: +return {Intrinsic::xtensa_ae_round16x4f32sasym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_round16x4f32ssym: +return {Intrinsic::xtensa_ae_round16x4f32ssym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_round24x2f48sasym: +return {Intrinsic::xtensa_ae_round24x2f48sasym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_round24x2f48ssym: +return {Intrinsic::xtensa_ae_round24x2f48ssym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_round32x2f48sasym: +return {Intrinsic::xtensa_ae_round32x2f48sasym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_round32x2f48ssym: +return {Intrinsic::xtensa_ae_round32x2f48ssym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_round32x2f64sasym: +return {Intrinsic::xtensa_ae_round32x2f64sasym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_round32x2f64ssym: +return {Intrinsic::xtensa_ae_round32x2f64ssym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_roundsp16f24asym: +return {Intrinsic::xtensa_ae_roundsp16f24asym, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_roundsp16f24sym: +return {Intrinsic::xtensa_ae_roundsp16f24sym, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_roundsp16q48x2asym: +return {Intrinsic::xtensa_ae_roundsp16q48x2asym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_roundsp16q48x2sym: +return {Intrinsic::xtensa_ae_roundsp16q48x2sym, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_roundsq32f48asym: +return {Intrinsic::xtensa_ae_roundsq32f48asym, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_roundsq32f48sym: +return {Intrinsic::xtensa_ae_roundsq32f48sym, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_s16_0_i: +return {Intrinsic::xtensa_ae_s16_0_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s16_0_ip: +return {Intrinsic::xtensa_ae_s16_0_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16_0_x: +return {Intrinsic::xtensa_ae_s16_0_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s16_0_xc: +return {Intrinsic::xtensa_ae_s16_0_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16_0_xp: +return {Intrinsic::xtensa_ae_s16_0_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16m_l_i: +return {Intrinsic::xtensa_ae_s16m_l_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s16m_l_iu: +return {Intrinsic::xtensa_ae_s16m_l_iu, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16m_l_x: +return {Intrinsic::xtensa_ae_s16m_l_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s16m_l_xc: +return {Intrinsic::xtensa_ae_s16m_l_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16m_l_xu: +return {Intrinsic::xtensa_ae_s16m_l_xu, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16x2m_i: +return {Intrinsic::xtensa_ae_s16x2m_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s16x2m_iu: +return {Intrinsic::xtensa_ae_s16x2m_iu, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16x2m_x: +return {Intrinsic::xtensa_ae_s16x2m_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s16x2m_xc: +return {Intrinsic::xtensa_ae_s16x2m_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16x2m_xu: +return {Intrinsic::xtensa_ae_s16x2m_xu, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16x4_i: +return {Intrinsic::xtensa_ae_s16x4_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s16x4_ip: +return {Intrinsic::xtensa_ae_s16x4_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16x4_ric: +return {Intrinsic::xtensa_ae_s16x4_ric, 0, 0x10200}; +case Xtensa::BI__builtin_xtensa_ae_s16x4_rip: +return {Intrinsic::xtensa_ae_s16x4_rip, 0, 0x10200}; +case Xtensa::BI__builtin_xtensa_ae_s16x4_x: +return {Intrinsic::xtensa_ae_s16x4_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s16x4_xc: +return {Intrinsic::xtensa_ae_s16x4_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s16x4_xp: +return {Intrinsic::xtensa_ae_s16x4_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s24ra64s_i: +return {Intrinsic::xtensa_ae_s24ra64s_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s24ra64s_ip: +return {Intrinsic::xtensa_ae_s24ra64s_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s24ra64s_x: +return {Intrinsic::xtensa_ae_s24ra64s_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s24ra64s_xc: +return {Intrinsic::xtensa_ae_s24ra64s_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s24ra64s_xp: +return {Intrinsic::xtensa_ae_s24ra64s_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s24x2ra64s_ip: +return {Intrinsic::xtensa_ae_s24x2ra64s_ip, 0, 0x30400}; +case Xtensa::BI__builtin_xtensa_ae_s32_l_i: +return {Intrinsic::xtensa_ae_s32_l_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32_l_ip: +return {Intrinsic::xtensa_ae_s32_l_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32_l_x: +return {Intrinsic::xtensa_ae_s32_l_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32_l_xc: +return {Intrinsic::xtensa_ae_s32_l_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32_l_xp: +return {Intrinsic::xtensa_ae_s32_l_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32f24_l_i: +return {Intrinsic::xtensa_ae_s32f24_l_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32f24_l_ip: +return {Intrinsic::xtensa_ae_s32f24_l_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32f24_l_x: +return {Intrinsic::xtensa_ae_s32f24_l_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32f24_l_xc: +return {Intrinsic::xtensa_ae_s32f24_l_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32f24_l_xp: +return {Intrinsic::xtensa_ae_s32f24_l_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32m_i: +return {Intrinsic::xtensa_ae_s32m_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32m_iu: +return {Intrinsic::xtensa_ae_s32m_iu, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32m_x: +return {Intrinsic::xtensa_ae_s32m_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32m_xc: +return {Intrinsic::xtensa_ae_s32m_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32m_xu: +return {Intrinsic::xtensa_ae_s32m_xu, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32ra64s_i: +return {Intrinsic::xtensa_ae_s32ra64s_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32ra64s_ip: +return {Intrinsic::xtensa_ae_s32ra64s_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32ra64s_x: +return {Intrinsic::xtensa_ae_s32ra64s_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32ra64s_xc: +return {Intrinsic::xtensa_ae_s32ra64s_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32ra64s_xp: +return {Intrinsic::xtensa_ae_s32ra64s_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2_i: +return {Intrinsic::xtensa_ae_s32x2_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32x2_ip: +return {Intrinsic::xtensa_ae_s32x2_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2_ric: +return {Intrinsic::xtensa_ae_s32x2_ric, 0, 0x10200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2_rip: +return {Intrinsic::xtensa_ae_s32x2_rip, 0, 0x10200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2_x: +return {Intrinsic::xtensa_ae_s32x2_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32x2_xc: +return {Intrinsic::xtensa_ae_s32x2_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2_xp: +return {Intrinsic::xtensa_ae_s32x2_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_i: +return {Intrinsic::xtensa_ae_s32x2f24_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_ip: +return {Intrinsic::xtensa_ae_s32x2f24_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_ric: +return {Intrinsic::xtensa_ae_s32x2f24_ric, 0, 0x10200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_rip: +return {Intrinsic::xtensa_ae_s32x2f24_rip, 0, 0x10200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_x: +return {Intrinsic::xtensa_ae_s32x2f24_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_xc: +return {Intrinsic::xtensa_ae_s32x2f24_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2f24_xp: +return {Intrinsic::xtensa_ae_s32x2f24_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s32x2ra64s_ip: +return {Intrinsic::xtensa_ae_s32x2ra64s_ip, 0, 0x30400}; +case Xtensa::BI__builtin_xtensa_ae_s64_i: +return {Intrinsic::xtensa_ae_s64_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s64_ip: +return {Intrinsic::xtensa_ae_s64_ip, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s64_x: +return {Intrinsic::xtensa_ae_s64_x, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_s64_xc: +return {Intrinsic::xtensa_ae_s64_xc, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_s64_xp: +return {Intrinsic::xtensa_ae_s64_xp, 0, 0x50200}; +case Xtensa::BI__builtin_xtensa_ae_sa16x4_ic: +return {Intrinsic::xtensa_ae_sa16x4_ic, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa16x4_ip: +return {Intrinsic::xtensa_ae_sa16x4_ip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa16x4_ric: +return {Intrinsic::xtensa_ae_sa16x4_ric, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa16x4_rip: +return {Intrinsic::xtensa_ae_sa16x4_rip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa24_l_ic: +return {Intrinsic::xtensa_ae_sa24_l_ic, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa24_l_ip: +return {Intrinsic::xtensa_ae_sa24_l_ip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa24_l_ric: +return {Intrinsic::xtensa_ae_sa24_l_ric, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa24_l_rip: +return {Intrinsic::xtensa_ae_sa24_l_rip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa24x2_ic: +return {Intrinsic::xtensa_ae_sa24x2_ic, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa24x2_ip: +return {Intrinsic::xtensa_ae_sa24x2_ip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa24x2_ric: +return {Intrinsic::xtensa_ae_sa24x2_ric, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa24x2_rip: +return {Intrinsic::xtensa_ae_sa24x2_rip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa32x2_ic: +return {Intrinsic::xtensa_ae_sa32x2_ic, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa32x2_ip: +return {Intrinsic::xtensa_ae_sa32x2_ip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa32x2_ric: +return {Intrinsic::xtensa_ae_sa32x2_ric, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa32x2_rip: +return {Intrinsic::xtensa_ae_sa32x2_rip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa32x2f24_ic: +return {Intrinsic::xtensa_ae_sa32x2f24_ic, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa32x2f24_ip: +return {Intrinsic::xtensa_ae_sa32x2f24_ip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa32x2f24_ric: +return {Intrinsic::xtensa_ae_sa32x2f24_ric, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa32x2f24_rip: +return {Intrinsic::xtensa_ae_sa32x2f24_rip, 0, 0x10600}; +case Xtensa::BI__builtin_xtensa_ae_sa64neg_fp: +return {Intrinsic::xtensa_ae_sa64neg_fp, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_sa64pos_fp: +return {Intrinsic::xtensa_ae_sa64pos_fp, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_salign64_i: +return {Intrinsic::xtensa_ae_salign64_i, 0, 0x70000}; +case Xtensa::BI__builtin_xtensa_ae_sat16x4: +return {Intrinsic::xtensa_ae_sat16x4, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sat24s: +return {Intrinsic::xtensa_ae_sat24s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_sat48s: +return {Intrinsic::xtensa_ae_sat48s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_satq56s: +return {Intrinsic::xtensa_ae_satq56s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_sb: +return {Intrinsic::xtensa_ae_sb, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_sb_ic: +return {Intrinsic::xtensa_ae_sb_ic, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_sb_ip: +return {Intrinsic::xtensa_ae_sb_ip, 0, 0x20100}; +case Xtensa::BI__builtin_xtensa_ae_sbf: +return {Intrinsic::xtensa_ae_sbf, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_sbf_ic: +return {Intrinsic::xtensa_ae_sbf_ic, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_sbf_ip: +return {Intrinsic::xtensa_ae_sbf_ip, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_sbi: +return {Intrinsic::xtensa_ae_sbi, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_sbi_ic: +return {Intrinsic::xtensa_ae_sbi_ic, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_sbi_ip: +return {Intrinsic::xtensa_ae_sbi_ip, 0, 0x60100}; +case Xtensa::BI__builtin_xtensa_ae_sel16i: +return {Intrinsic::xtensa_ae_sel16i, 1, 0xe0001}; +case Xtensa::BI__builtin_xtensa_ae_sel16i_n: +return {Intrinsic::xtensa_ae_sel16i_n, 1, 0xe0001}; +case Xtensa::BI__builtin_xtensa_ae_sext32: +return {Intrinsic::xtensa_ae_sext32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sext32x2d16_10: +return {Intrinsic::xtensa_ae_sext32x2d16_10, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_sext32x2d16_32: +return {Intrinsic::xtensa_ae_sext32x2d16_32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_sha32: +return {Intrinsic::xtensa_ae_sha32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_shortswap: +return {Intrinsic::xtensa_ae_shortswap, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_slaa16s: +return {Intrinsic::xtensa_ae_slaa16s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slaa32: +return {Intrinsic::xtensa_ae_slaa32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slaa32s: +return {Intrinsic::xtensa_ae_slaa32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slaa64: +return {Intrinsic::xtensa_ae_slaa64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slaa64s: +return {Intrinsic::xtensa_ae_slaa64s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slaaq56: +return {Intrinsic::xtensa_ae_slaaq56, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slai16s: +return {Intrinsic::xtensa_ae_slai16s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slai24: +return {Intrinsic::xtensa_ae_slai24, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slai24s: +return {Intrinsic::xtensa_ae_slai24s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slai32: +return {Intrinsic::xtensa_ae_slai32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slai32s: +return {Intrinsic::xtensa_ae_slai32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slai64: +return {Intrinsic::xtensa_ae_slai64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slai64s: +return {Intrinsic::xtensa_ae_slai64s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slaisq56s: +return {Intrinsic::xtensa_ae_slaisq56s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_slas24: +return {Intrinsic::xtensa_ae_slas24, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_slas24s: +return {Intrinsic::xtensa_ae_slas24s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_slas32: +return {Intrinsic::xtensa_ae_slas32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_slas32s: +return {Intrinsic::xtensa_ae_slas32s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_slas64: +return {Intrinsic::xtensa_ae_slas64, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_slas64s: +return {Intrinsic::xtensa_ae_slas64s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_slasq56: +return {Intrinsic::xtensa_ae_slasq56, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_slassq56s: +return {Intrinsic::xtensa_ae_slassq56s, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_sra64_32: +return {Intrinsic::xtensa_ae_sra64_32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sraa16rs: +return {Intrinsic::xtensa_ae_sraa16rs, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sraa16s: +return {Intrinsic::xtensa_ae_sraa16s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sraa32: +return {Intrinsic::xtensa_ae_sraa32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sraa32rs: +return {Intrinsic::xtensa_ae_sraa32rs, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sraa32s: +return {Intrinsic::xtensa_ae_sraa32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sraa64: +return {Intrinsic::xtensa_ae_sraa64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srai16: +return {Intrinsic::xtensa_ae_srai16, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srai16r: +return {Intrinsic::xtensa_ae_srai16r, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srai24: +return {Intrinsic::xtensa_ae_srai24, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srai32: +return {Intrinsic::xtensa_ae_srai32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srai32r: +return {Intrinsic::xtensa_ae_srai32r, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srai64: +return {Intrinsic::xtensa_ae_srai64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sras24: +return {Intrinsic::xtensa_ae_sras24, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_sras32: +return {Intrinsic::xtensa_ae_sras32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_sras64: +return {Intrinsic::xtensa_ae_sras64, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_srla32: +return {Intrinsic::xtensa_ae_srla32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srla64: +return {Intrinsic::xtensa_ae_srla64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srli24: +return {Intrinsic::xtensa_ae_srli24, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srli32: +return {Intrinsic::xtensa_ae_srli32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srli64: +return {Intrinsic::xtensa_ae_srli64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_srls24: +return {Intrinsic::xtensa_ae_srls24, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_srls32: +return {Intrinsic::xtensa_ae_srls32, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_srls64: +return {Intrinsic::xtensa_ae_srls64, 1, 0x20001}; +case Xtensa::BI__builtin_xtensa_ae_sub16: +return {Intrinsic::xtensa_ae_sub16, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sub16s: +return {Intrinsic::xtensa_ae_sub16s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sub24s: +return {Intrinsic::xtensa_ae_sub24s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sub32: +return {Intrinsic::xtensa_ae_sub32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sub32s: +return {Intrinsic::xtensa_ae_sub32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sub64: +return {Intrinsic::xtensa_ae_sub64, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_sub64s: +return {Intrinsic::xtensa_ae_sub64s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_subadd32: +return {Intrinsic::xtensa_ae_subadd32, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_subadd32s: +return {Intrinsic::xtensa_ae_subadd32s, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_trunca32f64s_l: +return {Intrinsic::xtensa_ae_trunca32f64s_l, 1, 0xe0001}; +case Xtensa::BI__builtin_xtensa_ae_trunca32x2f64s: +return {Intrinsic::xtensa_ae_trunca32x2f64s, 1, 0xe0001}; +case Xtensa::BI__builtin_xtensa_ae_trunci32f64s_l: +return {Intrinsic::xtensa_ae_trunci32f64s_l, 1, 0xe0001}; +case Xtensa::BI__builtin_xtensa_ae_trunci32x2f64s: +return {Intrinsic::xtensa_ae_trunci32x2f64s, 1, 0xe0001}; +case Xtensa::BI__builtin_xtensa_ae_vldl16c: +return {Intrinsic::xtensa_ae_vldl16c, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_vldl16c_ic: +return {Intrinsic::xtensa_ae_vldl16c_ic, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_vldl16c_ip: +return {Intrinsic::xtensa_ae_vldl16c_ip, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_vldl16t: +return {Intrinsic::xtensa_ae_vldl16t, 0, 0x40003}; +case Xtensa::BI__builtin_xtensa_ae_vldl32t: +return {Intrinsic::xtensa_ae_vldl32t, 0, 0x40003}; +case Xtensa::BI__builtin_xtensa_ae_vldsht: +return {Intrinsic::xtensa_ae_vldsht, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_ae_vlel16t: +return {Intrinsic::xtensa_ae_vlel16t, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_vlel32t: +return {Intrinsic::xtensa_ae_vlel32t, 0, 0x40201}; +case Xtensa::BI__builtin_xtensa_ae_vles16c: +return {Intrinsic::xtensa_ae_vles16c, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_vles16c_ic: +return {Intrinsic::xtensa_ae_vles16c_ic, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_vles16c_ip: +return {Intrinsic::xtensa_ae_vles16c_ip, 0, 0x100}; +case Xtensa::BI__builtin_xtensa_ae_xor: +return {Intrinsic::xtensa_ae_xor, 1, 0x60001}; +case Xtensa::BI__builtin_xtensa_ae_zalign64: +return {Intrinsic::xtensa_ae_zalign64, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_bithead: +return {Intrinsic::xtensa_rur_ae_bithead, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_bitptr: +return {Intrinsic::xtensa_rur_ae_bitptr, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_bitsused: +return {Intrinsic::xtensa_rur_ae_bitsused, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_cbegin0: +return {Intrinsic::xtensa_rur_ae_cbegin0, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_cend0: +return {Intrinsic::xtensa_rur_ae_cend0, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_cw_sd_no: +return {Intrinsic::xtensa_rur_ae_cw_sd_no, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_cwrap: +return {Intrinsic::xtensa_rur_ae_cwrap, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_first_ts: +return {Intrinsic::xtensa_rur_ae_first_ts, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_nextoffset: +return {Intrinsic::xtensa_rur_ae_nextoffset, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_overflow: +return {Intrinsic::xtensa_rur_ae_overflow, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_ovf_sar: +return {Intrinsic::xtensa_rur_ae_ovf_sar, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_sar: +return {Intrinsic::xtensa_rur_ae_sar, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_searchdone: +return {Intrinsic::xtensa_rur_ae_searchdone, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_tablesize: +return {Intrinsic::xtensa_rur_ae_tablesize, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_rur_ae_ts_fts_bu_bp: +return {Intrinsic::xtensa_rur_ae_ts_fts_bu_bp, 1, 0x1}; +case Xtensa::BI__builtin_xtensa_wur_ae_bithead: +return {Intrinsic::xtensa_wur_ae_bithead, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_bitptr: +return {Intrinsic::xtensa_wur_ae_bitptr, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_bitsused: +return {Intrinsic::xtensa_wur_ae_bitsused, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_cbegin0: +return {Intrinsic::xtensa_wur_ae_cbegin0, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_cend0: +return {Intrinsic::xtensa_wur_ae_cend0, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_cw_sd_no: +return {Intrinsic::xtensa_wur_ae_cw_sd_no, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_cwrap: +return {Intrinsic::xtensa_wur_ae_cwrap, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_first_ts: +return {Intrinsic::xtensa_wur_ae_first_ts, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_nextoffset: +return {Intrinsic::xtensa_wur_ae_nextoffset, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_overflow: +return {Intrinsic::xtensa_wur_ae_overflow, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_ovf_sar: +return {Intrinsic::xtensa_wur_ae_ovf_sar, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_sar: +return {Intrinsic::xtensa_wur_ae_sar, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_searchdone: +return {Intrinsic::xtensa_wur_ae_searchdone, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_tablesize: +return {Intrinsic::xtensa_wur_ae_tablesize, 0, 0x10000}; +case Xtensa::BI__builtin_xtensa_wur_ae_ts_fts_bu_bp: +return {Intrinsic::xtensa_wur_ae_ts_fts_bu_bp, 0, 0x10000}; diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index fb8798f82ace75..d1e2c8c273df72 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -21323,45 +21323,193 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, return Builder.CreateCall(F, Ops, ""); } -llvm::Value * -CodeGenFunction::EmitXtensaBuiltinExpr(unsigned BuiltinID, const CallExpr *E, - ReturnValueSlot ReturnValue, - llvm::Triple::ArchType Arch) { - +struct XtensaIntrinsicInfo { unsigned IntrinsicID; + unsigned Kind; + unsigned Arg; +}; + +static XtensaIntrinsicInfo GetXtensaIntrinsic(unsigned BuiltinID) { switch (BuiltinID) { - case Xtensa::BI__builtin_xtensa_xt_lsxp: - IntrinsicID = Intrinsic::xtensa_xt_lsxp; - break; case Xtensa::BI__builtin_xtensa_xt_lsip: - IntrinsicID = Intrinsic::xtensa_xt_lsip; - break; + return {Intrinsic::xtensa_xt_lsip, 2, 0x20100}; + case Xtensa::BI__builtin_xtensa_xt_lsxp: + return {Intrinsic::xtensa_xt_lsxp, 2, 0x20100}; +#include "clang/Basic/XtensaBuiltins.inc" default: llvm_unreachable("unexpected builtin ID"); } +} + +llvm::Value *CodeGenFunction::ConvertXtensaToC(Value *val, + llvm::Type *destType) { + Value *argCast; + llvm::Type *valType = val->getType(); + + if (valType != destType) { // i32 to C short or char + argCast = Builder.CreateTruncOrBitCast(val, destType, "cast"); + return argCast; + } else { + return val; + } +} + +llvm::Value *CodeGenFunction::ConvertXtensaToBc(const Expr *ArgExpr, + llvm::Type *destType) { + + Value *ArgVal = EmitScalarExpr(ArgExpr); + Value *ArgCast = ArgVal; + llvm::Type *ArgType = ArgVal->getType(); + bool sign = ArgExpr->getType()->isSignedIntegerType(); + + if (ArgType != destType) { // short,char + if (sign) + ArgCast = Builder.CreateSExtOrBitCast(ArgVal, destType, "cast"); + else + ArgCast = Builder.CreateZExtOrBitCast(ArgVal, destType, "cast"); + } + return ArgCast; +} + +llvm::Value * +CodeGenFunction::EmitXtensaBuiltinExpr(unsigned BuiltinID, const CallExpr *E, + ReturnValueSlot ReturnValue, + llvm::Triple::ArchType Arch) { - llvm::Function *F = CGM.getIntrinsic(IntrinsicID); - // 1st argument is passed by pointer - /* float lsip(float **a, int off) => float p = *a - ret, p' = @int.xtensa.lsip(p, off) - *a = p' - */ - auto InoutPtrTy = F->getArg(0)->getType()->getPointerTo(); - Address InoutPtrAddr = Builder.CreateElementBitCast( - EmitPointerWithAlignment(E->getArg(0)), InoutPtrTy); - - unsigned NumArgs = E->getNumArgs(); - Value *InoutVal = Builder.CreateLoad(InoutPtrAddr); - SmallVector Args; - - Args.push_back(InoutVal); - for (unsigned i = 1; i < NumArgs; i++) - Args.push_back(EmitScalarExpr(E->getArg(i))); - - Value *Val = Builder.CreateCall(F, Args, "retval"); - Value *Val0 = Builder.CreateExtractValue(Val, 0); - Value *Val1 = Builder.CreateExtractValue(Val, 1); - // ret store - Builder.CreateStore(Val1, InoutPtrAddr); - return Val0; + XtensaIntrinsicInfo Info = GetXtensaIntrinsic(BuiltinID); + unsigned Intrinsic = Info.IntrinsicID; + + llvm::Function *F = CGM.getIntrinsic(Intrinsic); + + switch (Info.Kind) { + case 0: { + // void case + // + // void builtin(t1 *out /*out*/,..,t2 *inout, ..., t3 in, ..,) => + // load t2 inout, ... + // {t1 out1, ..., t2 inout, ... ,} = func(t2 inout, ..., t3 in, ...) + // store (extractvalue 0) t1, .. + + SmallVector Out; + SmallVector Inout; + SmallVector In; + SmallVector OutAddr; + + unsigned Code = Info.Arg; + unsigned CodeOut = Code & 0xff; + unsigned CodeInout = (Code >> 8) & 0xff; + unsigned CodeIn = (Code >> 16) & 0xff; + + for (unsigned i = 0; i < 8; ++i) { + if (CodeOut & (1 << i)) + Out.push_back(i); + if (CodeInout & (1 << i)) + Inout.push_back(i); + if (CodeIn & (1 << i)) + In.push_back(i); + } + + size_t asize = Inout.size() + In.size(); + SmallVector Args(asize, nullptr); + assert(Args.size() == asize); + + for (uint8_t idx : In) { + unsigned funArg = idx - Out.size(); + llvm::Type *destType = F->getArg(funArg)->getType(); + Args[funArg] = ConvertXtensaToBc(E->getArg(idx), destType); + } + + for (unsigned i = 0; i < Out.size(); ++i) { + unsigned idx = Out[i]; + Address AIn = EmitPointerWithAlignment(E->getArg(idx)); + Address AOut = AIn; + OutAddr.push_back(AOut); + } + + for (uint8_t idx : Inout) { + uint8_t FIdx = idx - Out.size(); + Address AIn = EmitPointerWithAlignment(E->getArg(idx)); + Address AOut = AIn; + OutAddr.push_back(AOut); + Value *Ptr = Builder.CreateLoad(AOut); + Args[FIdx] = Ptr; + } + + for (auto a : Args) + assert(a != nullptr); + + Value *Val = Builder.CreateCall(F, Args); + Value *Val0 = nullptr; + // check if out is a struct + if ((OutAddr.size() > 1)) { + for (unsigned i = 0; i < OutAddr.size(); ++i) { + Value *Out = Builder.CreateExtractValue(Val, i); + if (!Val0) // return the first value + Val0 = Out; + Address Addr = OutAddr[i]; + llvm::Type *DestType = Addr.getElementType(); + Value *OutConv = ConvertXtensaToC(Out, DestType); + Builder.CreateStore(OutConv, Addr); + } + } else if (OutAddr.size() == 1) { + Builder.CreateStore(Val, OutAddr[0]); + Val0 = Val; + } + assert(Val0); + return Val0; + } + case 1: { + // t_out bultin(t1 in1, t2 in2, ...) => + // t_out out1 = BcToXt( func(XtToBc(t1), XtToBc(t2), ...) ) + unsigned Code = Info.Arg; + uint8_t CodeOut = Code & 0xff; + uint8_t CodeInout = (Code >> 8) & 0xff; + uint8_t CodeIn = (Code >> 16) & 0xff; + + SmallVector In; + + assert(CodeOut == 1 && CodeInout == 0 && "Invalid signature"); + for (unsigned i = 0; i < 8; ++i) { + if (CodeIn & (1 << i)) + In.push_back(i); + } + SmallVector Args(In.size(), nullptr); + for (uint8_t idx : In) { + uint8_t aIdx = idx - 1; + llvm::Type *destType = F->getArg(aIdx)->getType(); + Args[aIdx] = ConvertXtensaToBc(E->getArg(aIdx), destType); + } + Value *Val = Builder.CreateCall(F, Args, "retval"); + llvm::Type *ResultType = ConvertType(E->getType()); + Value *ValConv = ConvertXtensaToC(Val, ResultType); + return ValConv; + } + case 2: { + // 1st argument is passed by pointer + /* float lsip(float **a, int off) => float p = *a + ret, p' = @int.xtensa.lsip(p, off) + *a = p' + */ + auto InoutPtrTy = F->getArg(0)->getType()->getPointerTo(); + Address InoutPtrAddr = EmitPointerWithAlignment(E->getArg(0)) + .withElementType(InoutPtrTy); + + unsigned NumArgs = E->getNumArgs(); + Value *InoutVal = Builder.CreateLoad(InoutPtrAddr); + SmallVector Args; + + Args.push_back(InoutVal); + for (unsigned i = 1; i < NumArgs; i++) + Args.push_back(EmitScalarExpr(E->getArg(i))); + + Value *Val = Builder.CreateCall(F, Args, "retval"); + Value *Val0 = Builder.CreateExtractValue(Val, 0); + Value *Val1 = Builder.CreateExtractValue(Val, 1); + // ret store + Builder.CreateStore(Val1, InoutPtrAddr); + return Val0; + } + default: + llvm_unreachable("unknown intrinsic kind"); + } } diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 4c0ac975f03fff..c57f1a0d8ccaef 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -4503,6 +4503,8 @@ class CodeGenFunction : public CodeGenTypeCache { /// Emits a reference binding to the passed in expression. RValue EmitReferenceBindingToExpr(const Expr *E); + llvm::Value *ConvertXtensaToBc(const Expr *Arg, llvm::Type *destType); + llvm::Value *ConvertXtensaToC(llvm::Value *arg, llvm::Type *destType); llvm::Value *EmitXtensaBuiltinExpr(unsigned BuiltinID, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Triple::ArchType Arch); diff --git a/clang/test/CodeGen/Xtensa/xtensa-hifi-intrinsics.c b/clang/test/CodeGen/Xtensa/xtensa-hifi-intrinsics.c new file mode 100644 index 00000000000000..13b07f3a5cc746 --- /dev/null +++ b/clang/test/CodeGen/Xtensa/xtensa-hifi-intrinsics.c @@ -0,0 +1,21408 @@ +// RUN: split-file %s %t +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_abs16s.c | FileCheck %t/ae_abs16s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_abs24s.c | FileCheck %t/ae_abs24s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_abs32.c | FileCheck %t/ae_abs32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_abs32s.c | FileCheck %t/ae_abs32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_abs64.c | FileCheck %t/ae_abs64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_abs64s.c | FileCheck %t/ae_abs64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_add16.c | FileCheck %t/ae_add16.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_add16s.c | FileCheck %t/ae_add16s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_add24s.c | FileCheck %t/ae_add24s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_add32.c | FileCheck %t/ae_add32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_add32_hl_lh.c | FileCheck %t/ae_add32_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_add32s.c | FileCheck %t/ae_add32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_add64.c | FileCheck %t/ae_add64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_add64s.c | FileCheck %t/ae_add64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_addbrba32.c | FileCheck %t/ae_addbrba32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_addsub32.c | FileCheck %t/ae_addsub32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_addsub32s.c | FileCheck %t/ae_addsub32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_and.c | FileCheck %t/ae_and.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvt32x2f16_10.c | FileCheck %t/ae_cvt32x2f16_10.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvt32x2f16_32.c | FileCheck %t/ae_cvt32x2f16_32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvt48a32.c | FileCheck %t/ae_cvt48a32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvt64a32.c | FileCheck %t/ae_cvt64a32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvt64f32_h.c | FileCheck %t/ae_cvt64f32_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvta32f24s_h.c | FileCheck %t/ae_cvta32f24s_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvta32f24s_l.c | FileCheck %t/ae_cvta32f24s_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvtq56a32s.c | FileCheck %t/ae_cvtq56a32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvtq56p32s_h.c | FileCheck %t/ae_cvtq56p32s_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_cvtq56p32s_l.c | FileCheck %t/ae_cvtq56p32s_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_db.c | FileCheck %t/ae_db.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_db_ic.c | FileCheck %t/ae_db_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_db_ip.c | FileCheck %t/ae_db_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_dbi.c | FileCheck %t/ae_dbi.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_dbi_ic.c | FileCheck %t/ae_dbi_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_dbi_ip.c | FileCheck %t/ae_dbi_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_div64d32_h.c | FileCheck %t/ae_div64d32_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_div64d32_l.c | FileCheck %t/ae_div64d32_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_eq16.c | FileCheck %t/ae_eq16.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_eq32.c | FileCheck %t/ae_eq32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_eq64.c | FileCheck %t/ae_eq64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16_i.c | FileCheck %t/ae_l16_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16_ip.c | FileCheck %t/ae_l16_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16_x.c | FileCheck %t/ae_l16_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16_xc.c | FileCheck %t/ae_l16_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16_xp.c | FileCheck %t/ae_l16_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16m_i.c | FileCheck %t/ae_l16m_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16m_iu.c | FileCheck %t/ae_l16m_iu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16m_x.c | FileCheck %t/ae_l16m_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16m_xc.c | FileCheck %t/ae_l16m_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16m_xu.c | FileCheck %t/ae_l16m_xu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x2m_i.c | FileCheck %t/ae_l16x2m_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x2m_iu.c | FileCheck %t/ae_l16x2m_iu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x2m_x.c | FileCheck %t/ae_l16x2m_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x2m_xc.c | FileCheck %t/ae_l16x2m_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x2m_xu.c | FileCheck %t/ae_l16x2m_xu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x4_i.c | FileCheck %t/ae_l16x4_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x4_ip.c | FileCheck %t/ae_l16x4_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x4_ric.c | FileCheck %t/ae_l16x4_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x4_rip.c | FileCheck %t/ae_l16x4_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x4_x.c | FileCheck %t/ae_l16x4_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x4_xc.c | FileCheck %t/ae_l16x4_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l16x4_xp.c | FileCheck %t/ae_l16x4_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32_i.c | FileCheck %t/ae_l32_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32_ip.c | FileCheck %t/ae_l32_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32_x.c | FileCheck %t/ae_l32_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32_xc.c | FileCheck %t/ae_l32_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32_xp.c | FileCheck %t/ae_l32_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32f24_i.c | FileCheck %t/ae_l32f24_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32f24_ip.c | FileCheck %t/ae_l32f24_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32f24_x.c | FileCheck %t/ae_l32f24_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32f24_xc.c | FileCheck %t/ae_l32f24_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32f24_xp.c | FileCheck %t/ae_l32f24_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32m_i.c | FileCheck %t/ae_l32m_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32m_iu.c | FileCheck %t/ae_l32m_iu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32m_x.c | FileCheck %t/ae_l32m_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32m_xc.c | FileCheck %t/ae_l32m_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32m_xu.c | FileCheck %t/ae_l32m_xu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2_i.c | FileCheck %t/ae_l32x2_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2_ip.c | FileCheck %t/ae_l32x2_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2_ric.c | FileCheck %t/ae_l32x2_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2_rip.c | FileCheck %t/ae_l32x2_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2_x.c | FileCheck %t/ae_l32x2_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2_xc.c | FileCheck %t/ae_l32x2_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2_xp.c | FileCheck %t/ae_l32x2_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2f24_i.c | FileCheck %t/ae_l32x2f24_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2f24_ip.c | FileCheck %t/ae_l32x2f24_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2f24_ric.c | FileCheck %t/ae_l32x2f24_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2f24_rip.c | FileCheck %t/ae_l32x2f24_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2f24_x.c | FileCheck %t/ae_l32x2f24_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2f24_xc.c | FileCheck %t/ae_l32x2f24_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l32x2f24_xp.c | FileCheck %t/ae_l32x2f24_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l64_i.c | FileCheck %t/ae_l64_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l64_ip.c | FileCheck %t/ae_l64_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l64_x.c | FileCheck %t/ae_l64_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l64_xc.c | FileCheck %t/ae_l64_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_l64_xp.c | FileCheck %t/ae_l64_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la16x4_ic.c | FileCheck %t/ae_la16x4_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la16x4_ip.c | FileCheck %t/ae_la16x4_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la16x4_ric.c | FileCheck %t/ae_la16x4_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la16x4_rip.c | FileCheck %t/ae_la16x4_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la16x4neg_pc.c | FileCheck %t/ae_la16x4neg_pc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la16x4pos_pc.c | FileCheck %t/ae_la16x4pos_pc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24_ic.c | FileCheck %t/ae_la24_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24_ip.c | FileCheck %t/ae_la24_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24_ric.c | FileCheck %t/ae_la24_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24_rip.c | FileCheck %t/ae_la24_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24neg_pc.c | FileCheck %t/ae_la24neg_pc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24pos_pc.c | FileCheck %t/ae_la24pos_pc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24x2_ic.c | FileCheck %t/ae_la24x2_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24x2_ip.c | FileCheck %t/ae_la24x2_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24x2_ric.c | FileCheck %t/ae_la24x2_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24x2_rip.c | FileCheck %t/ae_la24x2_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24x2neg_pc.c | FileCheck %t/ae_la24x2neg_pc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la24x2pos_pc.c | FileCheck %t/ae_la24x2pos_pc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2_ic.c | FileCheck %t/ae_la32x2_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2_ip.c | FileCheck %t/ae_la32x2_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2_ric.c | FileCheck %t/ae_la32x2_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2_rip.c | FileCheck %t/ae_la32x2_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2f24_ic.c | FileCheck %t/ae_la32x2f24_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2f24_ip.c | FileCheck %t/ae_la32x2f24_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2f24_ric.c | FileCheck %t/ae_la32x2f24_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2f24_rip.c | FileCheck %t/ae_la32x2f24_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2neg_pc.c | FileCheck %t/ae_la32x2neg_pc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la32x2pos_pc.c | FileCheck %t/ae_la32x2pos_pc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_la64_pp.c | FileCheck %t/ae_la64_pp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lalign64_i.c | FileCheck %t/ae_lalign64_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lb.c | FileCheck %t/ae_lb.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lbi.c | FileCheck %t/ae_lbi.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lbk.c | FileCheck %t/ae_lbk.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lbki.c | FileCheck %t/ae_lbki.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lbs.c | FileCheck %t/ae_lbs.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lbsi.c | FileCheck %t/ae_lbsi.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_le16.c | FileCheck %t/ae_le16.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_le32.c | FileCheck %t/ae_le32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_le64.c | FileCheck %t/ae_le64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lt16.c | FileCheck %t/ae_lt16.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lt32.c | FileCheck %t/ae_lt32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_lt64.c | FileCheck %t/ae_lt64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_max32.c | FileCheck %t/ae_max32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_max64.c | FileCheck %t/ae_max64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_maxabs32s.c | FileCheck %t/ae_maxabs32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_maxabs64s.c | FileCheck %t/ae_maxabs64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_min32.c | FileCheck %t/ae_min32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_min64.c | FileCheck %t/ae_min64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_minabs32s.c | FileCheck %t/ae_minabs32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_minabs64s.c | FileCheck %t/ae_minabs64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mov.c | FileCheck %t/ae_mov.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movad16_0.c | FileCheck %t/ae_movad16_0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movad16_1.c | FileCheck %t/ae_movad16_1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movad16_2.c | FileCheck %t/ae_movad16_2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movad16_3.c | FileCheck %t/ae_movad16_3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movad32_h.c | FileCheck %t/ae_movad32_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movad32_l.c | FileCheck %t/ae_movad32_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movalign.c | FileCheck %t/ae_movalign.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movda16.c | FileCheck %t/ae_movda16.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movda16x2.c | FileCheck %t/ae_movda16x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movda32.c | FileCheck %t/ae_movda32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movda32x2.c | FileCheck %t/ae_movda32x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movf16x4.c | FileCheck %t/ae_movf16x4.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movf32x2.c | FileCheck %t/ae_movf32x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movf64.c | FileCheck %t/ae_movf64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movi.c | FileCheck %t/ae_movi.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movt16x4.c | FileCheck %t/ae_movt16x4.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movt32x2.c | FileCheck %t/ae_movt32x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_movt64.c | FileCheck %t/ae_movt64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul16x4.c | FileCheck %t/ae_mul16x4.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32_hh.c | FileCheck %t/ae_mul32_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32_lh.c | FileCheck %t/ae_mul32_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32_ll.c | FileCheck %t/ae_mul32_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32_ll_s2.c | FileCheck %t/ae_mul32_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32u_ll.c | FileCheck %t/ae_mul32u_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_h0.c | FileCheck %t/ae_mul32x16_h0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_h0_s2.c | FileCheck %t/ae_mul32x16_h0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_h1.c | FileCheck %t/ae_mul32x16_h1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_h1_s2.c | FileCheck %t/ae_mul32x16_h1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_h2.c | FileCheck %t/ae_mul32x16_h2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_h2_s2.c | FileCheck %t/ae_mul32x16_h2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_h3.c | FileCheck %t/ae_mul32x16_h3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_h3_s2.c | FileCheck %t/ae_mul32x16_h3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_l0.c | FileCheck %t/ae_mul32x16_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_l0_s2.c | FileCheck %t/ae_mul32x16_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_l1.c | FileCheck %t/ae_mul32x16_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_l1_s2.c | FileCheck %t/ae_mul32x16_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_l2.c | FileCheck %t/ae_mul32x16_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_l2_s2.c | FileCheck %t/ae_mul32x16_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_l3.c | FileCheck %t/ae_mul32x16_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mul32x16_l3_s2.c | FileCheck %t/ae_mul32x16_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula16x4.c | FileCheck %t/ae_mula16x4.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32_hh.c | FileCheck %t/ae_mula32_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32_lh.c | FileCheck %t/ae_mula32_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32_ll.c | FileCheck %t/ae_mula32_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32_ll_s2.c | FileCheck %t/ae_mula32_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32u_ll.c | FileCheck %t/ae_mula32u_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_h0.c | FileCheck %t/ae_mula32x16_h0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_h0_s2.c | FileCheck %t/ae_mula32x16_h0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_h1.c | FileCheck %t/ae_mula32x16_h1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_h1_s2.c | FileCheck %t/ae_mula32x16_h1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_h2.c | FileCheck %t/ae_mula32x16_h2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_h2_s2.c | FileCheck %t/ae_mula32x16_h2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_h3.c | FileCheck %t/ae_mula32x16_h3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_h3_s2.c | FileCheck %t/ae_mula32x16_h3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_l0.c | FileCheck %t/ae_mula32x16_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_l0_s2.c | FileCheck %t/ae_mula32x16_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_l1.c | FileCheck %t/ae_mula32x16_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_l1_s2.c | FileCheck %t/ae_mula32x16_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_l2.c | FileCheck %t/ae_mula32x16_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_l2_s2.c | FileCheck %t/ae_mula32x16_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_l3.c | FileCheck %t/ae_mula32x16_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mula32x16_l3_s2.c | FileCheck %t/ae_mula32x16_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad24_hh_ll.c | FileCheck %t/ae_mulaad24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad24_hh_ll_s2.c | FileCheck %t/ae_mulaad24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad24_hl_lh.c | FileCheck %t/ae_mulaad24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad24_hl_lh_s2.c | FileCheck %t/ae_mulaad24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad32x16_h0_l1.c | FileCheck %t/ae_mulaad32x16_h0_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad32x16_h0_l1_s2.c | FileCheck %t/ae_mulaad32x16_h0_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad32x16_h1_l0.c | FileCheck %t/ae_mulaad32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad32x16_h1_l0_s2.c | FileCheck %t/ae_mulaad32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad32x16_h2_l3.c | FileCheck %t/ae_mulaad32x16_h2_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad32x16_h2_l3_s2.c | FileCheck %t/ae_mulaad32x16_h2_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad32x16_h3_l2.c | FileCheck %t/ae_mulaad32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaad32x16_h3_l2_s2.c | FileCheck %t/ae_mulaad32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd16ss_11_00.c | FileCheck %t/ae_mulaafd16ss_11_00.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd16ss_11_00_s2.c | FileCheck %t/ae_mulaafd16ss_11_00_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd16ss_13_02.c | FileCheck %t/ae_mulaafd16ss_13_02.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd16ss_13_02_s2.c | FileCheck %t/ae_mulaafd16ss_13_02_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd16ss_33_22.c | FileCheck %t/ae_mulaafd16ss_33_22.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd16ss_33_22_s2.c | FileCheck %t/ae_mulaafd16ss_33_22_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd24_hh_ll.c | FileCheck %t/ae_mulaafd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd24_hh_ll_s2.c | FileCheck %t/ae_mulaafd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd24_hl_lh.c | FileCheck %t/ae_mulaafd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd24_hl_lh_s2.c | FileCheck %t/ae_mulaafd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd32x16_h0_l1.c | FileCheck %t/ae_mulaafd32x16_h0_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd32x16_h0_l1_s2.c | FileCheck %t/ae_mulaafd32x16_h0_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd32x16_h1_l0.c | FileCheck %t/ae_mulaafd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd32x16_h1_l0_s2.c | FileCheck %t/ae_mulaafd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd32x16_h2_l3.c | FileCheck %t/ae_mulaafd32x16_h2_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd32x16_h2_l3_s2.c | FileCheck %t/ae_mulaafd32x16_h2_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd32x16_h3_l2.c | FileCheck %t/ae_mulaafd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaafd32x16_h3_l2_s2.c | FileCheck %t/ae_mulaafd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulac24.c | FileCheck %t/ae_mulac24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulac32x16_h.c | FileCheck %t/ae_mulac32x16_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulac32x16_l.c | FileCheck %t/ae_mulac32x16_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_00.c | FileCheck %t/ae_mulaf16ss_00.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_00_s2.c | FileCheck %t/ae_mulaf16ss_00_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_10.c | FileCheck %t/ae_mulaf16ss_10.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_11.c | FileCheck %t/ae_mulaf16ss_11.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_20.c | FileCheck %t/ae_mulaf16ss_20.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_21.c | FileCheck %t/ae_mulaf16ss_21.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_22.c | FileCheck %t/ae_mulaf16ss_22.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_30.c | FileCheck %t/ae_mulaf16ss_30.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_31.c | FileCheck %t/ae_mulaf16ss_31.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_32.c | FileCheck %t/ae_mulaf16ss_32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16ss_33.c | FileCheck %t/ae_mulaf16ss_33.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf16x4ss.c | FileCheck %t/ae_mulaf16x4ss.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32r_hh.c | FileCheck %t/ae_mulaf32r_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32r_lh.c | FileCheck %t/ae_mulaf32r_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32r_ll.c | FileCheck %t/ae_mulaf32r_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32r_ll_s2.c | FileCheck %t/ae_mulaf32r_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32s_hh.c | FileCheck %t/ae_mulaf32s_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32s_lh.c | FileCheck %t/ae_mulaf32s_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32s_ll.c | FileCheck %t/ae_mulaf32s_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32s_ll_s2.c | FileCheck %t/ae_mulaf32s_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_h0.c | FileCheck %t/ae_mulaf32x16_h0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_h0_s2.c | FileCheck %t/ae_mulaf32x16_h0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_h1.c | FileCheck %t/ae_mulaf32x16_h1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_h1_s2.c | FileCheck %t/ae_mulaf32x16_h1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_h2.c | FileCheck %t/ae_mulaf32x16_h2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_h2_s2.c | FileCheck %t/ae_mulaf32x16_h2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_h3.c | FileCheck %t/ae_mulaf32x16_h3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_h3_s2.c | FileCheck %t/ae_mulaf32x16_h3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_l0.c | FileCheck %t/ae_mulaf32x16_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_l0_s2.c | FileCheck %t/ae_mulaf32x16_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_l1.c | FileCheck %t/ae_mulaf32x16_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_l1_s2.c | FileCheck %t/ae_mulaf32x16_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_l2.c | FileCheck %t/ae_mulaf32x16_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_l2_s2.c | FileCheck %t/ae_mulaf32x16_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_l3.c | FileCheck %t/ae_mulaf32x16_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf32x16_l3_s2.c | FileCheck %t/ae_mulaf32x16_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf48q32sp16s_l.c | FileCheck %t/ae_mulaf48q32sp16s_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf48q32sp16s_l_s2.c | FileCheck %t/ae_mulaf48q32sp16s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf48q32sp16u_l.c | FileCheck %t/ae_mulaf48q32sp16u_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaf48q32sp16u_l_s2.c | FileCheck %t/ae_mulaf48q32sp16u_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafc24ra.c | FileCheck %t/ae_mulafc24ra.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafc32x16ras_h.c | FileCheck %t/ae_mulafc32x16ras_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafc32x16ras_l.c | FileCheck %t/ae_mulafc32x16ras_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafd24x2_fir_h.c | FileCheck %t/ae_mulafd24x2_fir_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafd24x2_fir_l.c | FileCheck %t/ae_mulafd24x2_fir_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafd32x16x2_fir_hh.c | FileCheck %t/ae_mulafd32x16x2_fir_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafd32x16x2_fir_hl.c | FileCheck %t/ae_mulafd32x16x2_fir_hl.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafd32x16x2_fir_lh.c | FileCheck %t/ae_mulafd32x16x2_fir_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafd32x16x2_fir_ll.c | FileCheck %t/ae_mulafd32x16x2_fir_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp24x2r.c | FileCheck %t/ae_mulafp24x2r.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp24x2r_s2.c | FileCheck %t/ae_mulafp24x2r_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp24x2ra.c | FileCheck %t/ae_mulafp24x2ra.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp24x2ra_s2.c | FileCheck %t/ae_mulafp24x2ra_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x16x2ras_h.c | FileCheck %t/ae_mulafp32x16x2ras_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x16x2ras_h_s2.c | FileCheck %t/ae_mulafp32x16x2ras_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x16x2ras_l.c | FileCheck %t/ae_mulafp32x16x2ras_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x16x2ras_l_s2.c | FileCheck %t/ae_mulafp32x16x2ras_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x16x2rs_h.c | FileCheck %t/ae_mulafp32x16x2rs_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x16x2rs_h_s2.c | FileCheck %t/ae_mulafp32x16x2rs_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x16x2rs_l.c | FileCheck %t/ae_mulafp32x16x2rs_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x16x2rs_l_s2.c | FileCheck %t/ae_mulafp32x16x2rs_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x2ras.c | FileCheck %t/ae_mulafp32x2ras.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafp32x2rs.c | FileCheck %t/ae_mulafp32x2rs.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafq32sp24s_h_s2.c | FileCheck %t/ae_mulafq32sp24s_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulafq32sp24s_l_s2.c | FileCheck %t/ae_mulafq32sp24s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulap24x2.c | FileCheck %t/ae_mulap24x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulap24x2_s2.c | FileCheck %t/ae_mulap24x2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulap32x16x2_h.c | FileCheck %t/ae_mulap32x16x2_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulap32x16x2_l.c | FileCheck %t/ae_mulap32x16x2_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulap32x2.c | FileCheck %t/ae_mulap32x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaq32sp16s_l_s2.c | FileCheck %t/ae_mulaq32sp16s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulaq32sp16u_l_s2.c | FileCheck %t/ae_mulaq32sp16u_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mularfq32sp24s_h_s2.c | FileCheck %t/ae_mularfq32sp24s_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mularfq32sp24s_l_s2.c | FileCheck %t/ae_mularfq32sp24s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulas32f48p16s_hh.c | FileCheck %t/ae_mulas32f48p16s_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulas32f48p16s_hh_s2.c | FileCheck %t/ae_mulas32f48p16s_hh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulas32f48p16s_lh.c | FileCheck %t/ae_mulas32f48p16s_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulas32f48p16s_lh_s2.c | FileCheck %t/ae_mulas32f48p16s_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulas32f48p16s_ll.c | FileCheck %t/ae_mulas32f48p16s_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulas32f48p16s_ll_s2.c | FileCheck %t/ae_mulas32f48p16s_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasd24_hh_ll.c | FileCheck %t/ae_mulasd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasd24_hh_ll_s2.c | FileCheck %t/ae_mulasd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasd24_hl_lh.c | FileCheck %t/ae_mulasd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasd24_hl_lh_s2.c | FileCheck %t/ae_mulasd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasd32x16_h1_l0.c | FileCheck %t/ae_mulasd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasd32x16_h1_l0_s2.c | FileCheck %t/ae_mulasd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasd32x16_h3_l2.c | FileCheck %t/ae_mulasd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasd32x16_h3_l2_s2.c | FileCheck %t/ae_mulasd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasfd24_hh_ll.c | FileCheck %t/ae_mulasfd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasfd24_hh_ll_s2.c | FileCheck %t/ae_mulasfd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasfd24_hl_lh.c | FileCheck %t/ae_mulasfd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasfd24_hl_lh_s2.c | FileCheck %t/ae_mulasfd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasfd32x16_h1_l0.c | FileCheck %t/ae_mulasfd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasfd32x16_h1_l0_s2.c | FileCheck %t/ae_mulasfd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasfd32x16_h3_l2.c | FileCheck %t/ae_mulasfd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulasfd32x16_h3_l2_s2.c | FileCheck %t/ae_mulasfd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulc24.c | FileCheck %t/ae_mulc24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulc32x16_h.c | FileCheck %t/ae_mulc32x16_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulc32x16_l.c | FileCheck %t/ae_mulc32x16_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_00.c | FileCheck %t/ae_mulf16ss_00.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_00_s2.c | FileCheck %t/ae_mulf16ss_00_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_10.c | FileCheck %t/ae_mulf16ss_10.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_11.c | FileCheck %t/ae_mulf16ss_11.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_20.c | FileCheck %t/ae_mulf16ss_20.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_21.c | FileCheck %t/ae_mulf16ss_21.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_22.c | FileCheck %t/ae_mulf16ss_22.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_30.c | FileCheck %t/ae_mulf16ss_30.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_31.c | FileCheck %t/ae_mulf16ss_31.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_32.c | FileCheck %t/ae_mulf16ss_32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16ss_33.c | FileCheck %t/ae_mulf16ss_33.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf16x4ss.c | FileCheck %t/ae_mulf16x4ss.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32r_hh.c | FileCheck %t/ae_mulf32r_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32r_lh.c | FileCheck %t/ae_mulf32r_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32r_ll.c | FileCheck %t/ae_mulf32r_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32r_ll_s2.c | FileCheck %t/ae_mulf32r_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32s_hh.c | FileCheck %t/ae_mulf32s_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32s_lh.c | FileCheck %t/ae_mulf32s_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32s_ll.c | FileCheck %t/ae_mulf32s_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32s_ll_s2.c | FileCheck %t/ae_mulf32s_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_h0.c | FileCheck %t/ae_mulf32x16_h0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_h0_s2.c | FileCheck %t/ae_mulf32x16_h0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_h1.c | FileCheck %t/ae_mulf32x16_h1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_h1_s2.c | FileCheck %t/ae_mulf32x16_h1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_h2.c | FileCheck %t/ae_mulf32x16_h2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_h2_s2.c | FileCheck %t/ae_mulf32x16_h2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_h3.c | FileCheck %t/ae_mulf32x16_h3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_h3_s2.c | FileCheck %t/ae_mulf32x16_h3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_l0.c | FileCheck %t/ae_mulf32x16_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_l0_s2.c | FileCheck %t/ae_mulf32x16_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_l1.c | FileCheck %t/ae_mulf32x16_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_l1_s2.c | FileCheck %t/ae_mulf32x16_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_l2.c | FileCheck %t/ae_mulf32x16_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_l2_s2.c | FileCheck %t/ae_mulf32x16_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_l3.c | FileCheck %t/ae_mulf32x16_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf32x16_l3_s2.c | FileCheck %t/ae_mulf32x16_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf48q32sp16s_l.c | FileCheck %t/ae_mulf48q32sp16s_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf48q32sp16s_l_s2.c | FileCheck %t/ae_mulf48q32sp16s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf48q32sp16u_l.c | FileCheck %t/ae_mulf48q32sp16u_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulf48q32sp16u_l_s2.c | FileCheck %t/ae_mulf48q32sp16u_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfc24ra.c | FileCheck %t/ae_mulfc24ra.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfc32x16ras_h.c | FileCheck %t/ae_mulfc32x16ras_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfc32x16ras_l.c | FileCheck %t/ae_mulfc32x16ras_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfd24x2_fir_h.c | FileCheck %t/ae_mulfd24x2_fir_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfd24x2_fir_l.c | FileCheck %t/ae_mulfd24x2_fir_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfd32x16x2_fir_hh.c | FileCheck %t/ae_mulfd32x16x2_fir_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfd32x16x2_fir_hl.c | FileCheck %t/ae_mulfd32x16x2_fir_hl.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfd32x16x2_fir_lh.c | FileCheck %t/ae_mulfd32x16x2_fir_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfd32x16x2_fir_ll.c | FileCheck %t/ae_mulfd32x16x2_fir_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp16x4ras.c | FileCheck %t/ae_mulfp16x4ras.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp16x4s.c | FileCheck %t/ae_mulfp16x4s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp24x2r.c | FileCheck %t/ae_mulfp24x2r.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp24x2r_s2.c | FileCheck %t/ae_mulfp24x2r_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp24x2ra.c | FileCheck %t/ae_mulfp24x2ra.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp24x2ra_s2.c | FileCheck %t/ae_mulfp24x2ra_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x16x2ras_h.c | FileCheck %t/ae_mulfp32x16x2ras_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x16x2ras_h_s2.c | FileCheck %t/ae_mulfp32x16x2ras_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x16x2ras_l.c | FileCheck %t/ae_mulfp32x16x2ras_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x16x2ras_l_s2.c | FileCheck %t/ae_mulfp32x16x2ras_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x16x2rs_h.c | FileCheck %t/ae_mulfp32x16x2rs_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x16x2rs_h_s2.c | FileCheck %t/ae_mulfp32x16x2rs_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x16x2rs_l.c | FileCheck %t/ae_mulfp32x16x2rs_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x16x2rs_l_s2.c | FileCheck %t/ae_mulfp32x16x2rs_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x2ras.c | FileCheck %t/ae_mulfp32x2ras.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfp32x2rs.c | FileCheck %t/ae_mulfp32x2rs.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfq32sp24s_h_s2.c | FileCheck %t/ae_mulfq32sp24s_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulfq32sp24s_l_s2.c | FileCheck %t/ae_mulfq32sp24s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulp24x2.c | FileCheck %t/ae_mulp24x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulp24x2_s2.c | FileCheck %t/ae_mulp24x2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulp32x16x2_h.c | FileCheck %t/ae_mulp32x16x2_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulp32x16x2_l.c | FileCheck %t/ae_mulp32x16x2_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulp32x2.c | FileCheck %t/ae_mulp32x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulq32sp16s_l_s2.c | FileCheck %t/ae_mulq32sp16s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulq32sp16u_l_s2.c | FileCheck %t/ae_mulq32sp16u_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulrfq32sp24s_h_s2.c | FileCheck %t/ae_mulrfq32sp24s_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulrfq32sp24s_l_s2.c | FileCheck %t/ae_mulrfq32sp24s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls16x4.c | FileCheck %t/ae_muls16x4.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32_hh.c | FileCheck %t/ae_muls32_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32_lh.c | FileCheck %t/ae_muls32_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32_ll.c | FileCheck %t/ae_muls32_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32f48p16s_hh.c | FileCheck %t/ae_muls32f48p16s_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32f48p16s_hh_s2.c | FileCheck %t/ae_muls32f48p16s_hh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32f48p16s_lh.c | FileCheck %t/ae_muls32f48p16s_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32f48p16s_lh_s2.c | FileCheck %t/ae_muls32f48p16s_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32f48p16s_ll.c | FileCheck %t/ae_muls32f48p16s_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32f48p16s_ll_s2.c | FileCheck %t/ae_muls32f48p16s_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32u_ll.c | FileCheck %t/ae_muls32u_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_h0.c | FileCheck %t/ae_muls32x16_h0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_h0_s2.c | FileCheck %t/ae_muls32x16_h0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_h1.c | FileCheck %t/ae_muls32x16_h1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_h1_s2.c | FileCheck %t/ae_muls32x16_h1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_h2.c | FileCheck %t/ae_muls32x16_h2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_h2_s2.c | FileCheck %t/ae_muls32x16_h2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_h3.c | FileCheck %t/ae_muls32x16_h3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_h3_s2.c | FileCheck %t/ae_muls32x16_h3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_l0.c | FileCheck %t/ae_muls32x16_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_l0_s2.c | FileCheck %t/ae_muls32x16_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_l1.c | FileCheck %t/ae_muls32x16_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_l1_s2.c | FileCheck %t/ae_muls32x16_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_l2.c | FileCheck %t/ae_muls32x16_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_l2_s2.c | FileCheck %t/ae_muls32x16_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_l3.c | FileCheck %t/ae_muls32x16_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_muls32x16_l3_s2.c | FileCheck %t/ae_muls32x16_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsad24_hh_ll.c | FileCheck %t/ae_mulsad24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsad24_hh_ll_s2.c | FileCheck %t/ae_mulsad24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsad32x16_h1_l0.c | FileCheck %t/ae_mulsad32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsad32x16_h1_l0_s2.c | FileCheck %t/ae_mulsad32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsad32x16_h3_l2.c | FileCheck %t/ae_mulsad32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsad32x16_h3_l2_s2.c | FileCheck %t/ae_mulsad32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsafd24_hh_ll.c | FileCheck %t/ae_mulsafd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsafd24_hh_ll_s2.c | FileCheck %t/ae_mulsafd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsafd32x16_h1_l0.c | FileCheck %t/ae_mulsafd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsafd32x16_h1_l0_s2.c | FileCheck %t/ae_mulsafd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsafd32x16_h3_l2.c | FileCheck %t/ae_mulsafd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsafd32x16_h3_l2_s2.c | FileCheck %t/ae_mulsafd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_00.c | FileCheck %t/ae_mulsf16ss_00.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_00_s2.c | FileCheck %t/ae_mulsf16ss_00_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_10.c | FileCheck %t/ae_mulsf16ss_10.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_11.c | FileCheck %t/ae_mulsf16ss_11.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_20.c | FileCheck %t/ae_mulsf16ss_20.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_21.c | FileCheck %t/ae_mulsf16ss_21.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_22.c | FileCheck %t/ae_mulsf16ss_22.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_30.c | FileCheck %t/ae_mulsf16ss_30.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_31.c | FileCheck %t/ae_mulsf16ss_31.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_32.c | FileCheck %t/ae_mulsf16ss_32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16ss_33.c | FileCheck %t/ae_mulsf16ss_33.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf16x4ss.c | FileCheck %t/ae_mulsf16x4ss.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32r_hh.c | FileCheck %t/ae_mulsf32r_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32r_lh.c | FileCheck %t/ae_mulsf32r_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32r_ll.c | FileCheck %t/ae_mulsf32r_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32r_ll_s2.c | FileCheck %t/ae_mulsf32r_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32s_hh.c | FileCheck %t/ae_mulsf32s_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32s_lh.c | FileCheck %t/ae_mulsf32s_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32s_ll.c | FileCheck %t/ae_mulsf32s_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_h0.c | FileCheck %t/ae_mulsf32x16_h0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_h0_s2.c | FileCheck %t/ae_mulsf32x16_h0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_h1.c | FileCheck %t/ae_mulsf32x16_h1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_h1_s2.c | FileCheck %t/ae_mulsf32x16_h1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_h2.c | FileCheck %t/ae_mulsf32x16_h2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_h2_s2.c | FileCheck %t/ae_mulsf32x16_h2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_h3.c | FileCheck %t/ae_mulsf32x16_h3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_h3_s2.c | FileCheck %t/ae_mulsf32x16_h3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_l0.c | FileCheck %t/ae_mulsf32x16_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_l0_s2.c | FileCheck %t/ae_mulsf32x16_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_l1.c | FileCheck %t/ae_mulsf32x16_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_l1_s2.c | FileCheck %t/ae_mulsf32x16_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_l2.c | FileCheck %t/ae_mulsf32x16_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_l2_s2.c | FileCheck %t/ae_mulsf32x16_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_l3.c | FileCheck %t/ae_mulsf32x16_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf32x16_l3_s2.c | FileCheck %t/ae_mulsf32x16_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf48q32sp16s_l.c | FileCheck %t/ae_mulsf48q32sp16s_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf48q32sp16s_l_s2.c | FileCheck %t/ae_mulsf48q32sp16s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf48q32sp16u_l.c | FileCheck %t/ae_mulsf48q32sp16u_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsf48q32sp16u_l_s2.c | FileCheck %t/ae_mulsf48q32sp16u_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp24x2r.c | FileCheck %t/ae_mulsfp24x2r.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp24x2r_s2.c | FileCheck %t/ae_mulsfp24x2r_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp24x2ra.c | FileCheck %t/ae_mulsfp24x2ra.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp24x2ra_s2.c | FileCheck %t/ae_mulsfp24x2ra_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x16x2ras_h.c | FileCheck %t/ae_mulsfp32x16x2ras_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x16x2ras_h_s2.c | FileCheck %t/ae_mulsfp32x16x2ras_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x16x2ras_l.c | FileCheck %t/ae_mulsfp32x16x2ras_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x16x2ras_l_s2.c | FileCheck %t/ae_mulsfp32x16x2ras_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x16x2rs_h.c | FileCheck %t/ae_mulsfp32x16x2rs_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x16x2rs_h_s2.c | FileCheck %t/ae_mulsfp32x16x2rs_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x16x2rs_l.c | FileCheck %t/ae_mulsfp32x16x2rs_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x16x2rs_l_s2.c | FileCheck %t/ae_mulsfp32x16x2rs_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x2ras.c | FileCheck %t/ae_mulsfp32x2ras.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfp32x2rs.c | FileCheck %t/ae_mulsfp32x2rs.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfq32sp24s_h_s2.c | FileCheck %t/ae_mulsfq32sp24s_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsfq32sp24s_l_s2.c | FileCheck %t/ae_mulsfq32sp24s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsp24x2.c | FileCheck %t/ae_mulsp24x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsp24x2_s2.c | FileCheck %t/ae_mulsp24x2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsp32x16x2_h.c | FileCheck %t/ae_mulsp32x16x2_h.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsp32x16x2_l.c | FileCheck %t/ae_mulsp32x16x2_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsp32x2.c | FileCheck %t/ae_mulsp32x2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsq32sp16s_l_s2.c | FileCheck %t/ae_mulsq32sp16s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsq32sp16u_l_s2.c | FileCheck %t/ae_mulsq32sp16u_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsrfq32sp24s_h_s2.c | FileCheck %t/ae_mulsrfq32sp24s_h_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulsrfq32sp24s_l_s2.c | FileCheck %t/ae_mulsrfq32sp24s_l_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulss32f48p16s_hh.c | FileCheck %t/ae_mulss32f48p16s_hh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulss32f48p16s_hh_s2.c | FileCheck %t/ae_mulss32f48p16s_hh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulss32f48p16s_lh.c | FileCheck %t/ae_mulss32f48p16s_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulss32f48p16s_lh_s2.c | FileCheck %t/ae_mulss32f48p16s_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulss32f48p16s_ll.c | FileCheck %t/ae_mulss32f48p16s_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulss32f48p16s_ll_s2.c | FileCheck %t/ae_mulss32f48p16s_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssd24_hh_ll.c | FileCheck %t/ae_mulssd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssd24_hh_ll_s2.c | FileCheck %t/ae_mulssd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssd24_hl_lh.c | FileCheck %t/ae_mulssd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssd24_hl_lh_s2.c | FileCheck %t/ae_mulssd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssd32x16_h1_l0.c | FileCheck %t/ae_mulssd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssd32x16_h1_l0_s2.c | FileCheck %t/ae_mulssd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssd32x16_h3_l2.c | FileCheck %t/ae_mulssd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssd32x16_h3_l2_s2.c | FileCheck %t/ae_mulssd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd16ss_11_00.c | FileCheck %t/ae_mulssfd16ss_11_00.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd16ss_11_00_s2.c | FileCheck %t/ae_mulssfd16ss_11_00_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd16ss_13_02.c | FileCheck %t/ae_mulssfd16ss_13_02.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd16ss_13_02_s2.c | FileCheck %t/ae_mulssfd16ss_13_02_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd16ss_33_22.c | FileCheck %t/ae_mulssfd16ss_33_22.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd16ss_33_22_s2.c | FileCheck %t/ae_mulssfd16ss_33_22_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd24_hh_ll.c | FileCheck %t/ae_mulssfd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd24_hh_ll_s2.c | FileCheck %t/ae_mulssfd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd24_hl_lh.c | FileCheck %t/ae_mulssfd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd24_hl_lh_s2.c | FileCheck %t/ae_mulssfd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd32x16_h1_l0.c | FileCheck %t/ae_mulssfd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd32x16_h1_l0_s2.c | FileCheck %t/ae_mulssfd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd32x16_h3_l2.c | FileCheck %t/ae_mulssfd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulssfd32x16_h3_l2_s2.c | FileCheck %t/ae_mulssfd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad24_hh_ll.c | FileCheck %t/ae_mulzaad24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad24_hh_ll_s2.c | FileCheck %t/ae_mulzaad24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad24_hl_lh.c | FileCheck %t/ae_mulzaad24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad24_hl_lh_s2.c | FileCheck %t/ae_mulzaad24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad32x16_h0_l1.c | FileCheck %t/ae_mulzaad32x16_h0_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad32x16_h0_l1_s2.c | FileCheck %t/ae_mulzaad32x16_h0_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad32x16_h1_l0.c | FileCheck %t/ae_mulzaad32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad32x16_h1_l0_s2.c | FileCheck %t/ae_mulzaad32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad32x16_h2_l3.c | FileCheck %t/ae_mulzaad32x16_h2_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad32x16_h2_l3_s2.c | FileCheck %t/ae_mulzaad32x16_h2_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad32x16_h3_l2.c | FileCheck %t/ae_mulzaad32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaad32x16_h3_l2_s2.c | FileCheck %t/ae_mulzaad32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd16ss_11_00.c | FileCheck %t/ae_mulzaafd16ss_11_00.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd16ss_11_00_s2.c | FileCheck %t/ae_mulzaafd16ss_11_00_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd16ss_13_02.c | FileCheck %t/ae_mulzaafd16ss_13_02.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd16ss_13_02_s2.c | FileCheck %t/ae_mulzaafd16ss_13_02_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd16ss_33_22.c | FileCheck %t/ae_mulzaafd16ss_33_22.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd16ss_33_22_s2.c | FileCheck %t/ae_mulzaafd16ss_33_22_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd24_hh_ll.c | FileCheck %t/ae_mulzaafd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd24_hh_ll_s2.c | FileCheck %t/ae_mulzaafd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd24_hl_lh.c | FileCheck %t/ae_mulzaafd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd24_hl_lh_s2.c | FileCheck %t/ae_mulzaafd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd32x16_h0_l1.c | FileCheck %t/ae_mulzaafd32x16_h0_l1.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd32x16_h0_l1_s2.c | FileCheck %t/ae_mulzaafd32x16_h0_l1_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd32x16_h1_l0.c | FileCheck %t/ae_mulzaafd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd32x16_h1_l0_s2.c | FileCheck %t/ae_mulzaafd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd32x16_h2_l3.c | FileCheck %t/ae_mulzaafd32x16_h2_l3.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd32x16_h2_l3_s2.c | FileCheck %t/ae_mulzaafd32x16_h2_l3_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd32x16_h3_l2.c | FileCheck %t/ae_mulzaafd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzaafd32x16_h3_l2_s2.c | FileCheck %t/ae_mulzaafd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasd24_hh_ll.c | FileCheck %t/ae_mulzasd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasd24_hh_ll_s2.c | FileCheck %t/ae_mulzasd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasd24_hl_lh.c | FileCheck %t/ae_mulzasd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasd24_hl_lh_s2.c | FileCheck %t/ae_mulzasd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasd32x16_h1_l0.c | FileCheck %t/ae_mulzasd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasd32x16_h1_l0_s2.c | FileCheck %t/ae_mulzasd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasd32x16_h3_l2.c | FileCheck %t/ae_mulzasd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasd32x16_h3_l2_s2.c | FileCheck %t/ae_mulzasd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasfd24_hh_ll.c | FileCheck %t/ae_mulzasfd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasfd24_hh_ll_s2.c | FileCheck %t/ae_mulzasfd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasfd24_hl_lh.c | FileCheck %t/ae_mulzasfd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasfd24_hl_lh_s2.c | FileCheck %t/ae_mulzasfd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasfd32x16_h1_l0.c | FileCheck %t/ae_mulzasfd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasfd32x16_h1_l0_s2.c | FileCheck %t/ae_mulzasfd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasfd32x16_h3_l2.c | FileCheck %t/ae_mulzasfd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzasfd32x16_h3_l2_s2.c | FileCheck %t/ae_mulzasfd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsad24_hh_ll.c | FileCheck %t/ae_mulzsad24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsad24_hh_ll_s2.c | FileCheck %t/ae_mulzsad24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsad32x16_h1_l0.c | FileCheck %t/ae_mulzsad32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsad32x16_h1_l0_s2.c | FileCheck %t/ae_mulzsad32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsad32x16_h3_l2.c | FileCheck %t/ae_mulzsad32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsad32x16_h3_l2_s2.c | FileCheck %t/ae_mulzsad32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsafd24_hh_ll.c | FileCheck %t/ae_mulzsafd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsafd24_hh_ll_s2.c | FileCheck %t/ae_mulzsafd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsafd32x16_h1_l0.c | FileCheck %t/ae_mulzsafd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsafd32x16_h1_l0_s2.c | FileCheck %t/ae_mulzsafd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsafd32x16_h3_l2.c | FileCheck %t/ae_mulzsafd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzsafd32x16_h3_l2_s2.c | FileCheck %t/ae_mulzsafd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssd24_hh_ll.c | FileCheck %t/ae_mulzssd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssd24_hh_ll_s2.c | FileCheck %t/ae_mulzssd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssd24_hl_lh.c | FileCheck %t/ae_mulzssd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssd24_hl_lh_s2.c | FileCheck %t/ae_mulzssd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssd32x16_h1_l0.c | FileCheck %t/ae_mulzssd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssd32x16_h1_l0_s2.c | FileCheck %t/ae_mulzssd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssd32x16_h3_l2.c | FileCheck %t/ae_mulzssd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssd32x16_h3_l2_s2.c | FileCheck %t/ae_mulzssd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd16ss_11_00.c | FileCheck %t/ae_mulzssfd16ss_11_00.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd16ss_11_00_s2.c | FileCheck %t/ae_mulzssfd16ss_11_00_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd16ss_13_02.c | FileCheck %t/ae_mulzssfd16ss_13_02.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd16ss_13_02_s2.c | FileCheck %t/ae_mulzssfd16ss_13_02_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd16ss_33_22.c | FileCheck %t/ae_mulzssfd16ss_33_22.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd16ss_33_22_s2.c | FileCheck %t/ae_mulzssfd16ss_33_22_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd24_hh_ll.c | FileCheck %t/ae_mulzssfd24_hh_ll.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd24_hh_ll_s2.c | FileCheck %t/ae_mulzssfd24_hh_ll_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd24_hl_lh.c | FileCheck %t/ae_mulzssfd24_hl_lh.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd24_hl_lh_s2.c | FileCheck %t/ae_mulzssfd24_hl_lh_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd32x16_h1_l0.c | FileCheck %t/ae_mulzssfd32x16_h1_l0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd32x16_h1_l0_s2.c | FileCheck %t/ae_mulzssfd32x16_h1_l0_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd32x16_h3_l2.c | FileCheck %t/ae_mulzssfd32x16_h3_l2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_mulzssfd32x16_h3_l2_s2.c | FileCheck %t/ae_mulzssfd32x16_h3_l2_s2.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_nand.c | FileCheck %t/ae_nand.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_neg16s.c | FileCheck %t/ae_neg16s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_neg24s.c | FileCheck %t/ae_neg24s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_neg32.c | FileCheck %t/ae_neg32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_neg32s.c | FileCheck %t/ae_neg32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_neg64.c | FileCheck %t/ae_neg64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_neg64s.c | FileCheck %t/ae_neg64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_nsa64.c | FileCheck %t/ae_nsa64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_nsaz16_0.c | FileCheck %t/ae_nsaz16_0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_nsaz32_l.c | FileCheck %t/ae_nsaz32_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_or.c | FileCheck %t/ae_or.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_pksr24.c | FileCheck %t/ae_pksr24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_pksr32.c | FileCheck %t/ae_pksr32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_round16x4f32sasym.c | FileCheck %t/ae_round16x4f32sasym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_round16x4f32ssym.c | FileCheck %t/ae_round16x4f32ssym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_round24x2f48sasym.c | FileCheck %t/ae_round24x2f48sasym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_round24x2f48ssym.c | FileCheck %t/ae_round24x2f48ssym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_round32x2f48sasym.c | FileCheck %t/ae_round32x2f48sasym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_round32x2f48ssym.c | FileCheck %t/ae_round32x2f48ssym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_round32x2f64sasym.c | FileCheck %t/ae_round32x2f64sasym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_round32x2f64ssym.c | FileCheck %t/ae_round32x2f64ssym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_roundsp16f24asym.c | FileCheck %t/ae_roundsp16f24asym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_roundsp16f24sym.c | FileCheck %t/ae_roundsp16f24sym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_roundsp16q48x2asym.c | FileCheck %t/ae_roundsp16q48x2asym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_roundsp16q48x2sym.c | FileCheck %t/ae_roundsp16q48x2sym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_roundsq32f48asym.c | FileCheck %t/ae_roundsq32f48asym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_roundsq32f48sym.c | FileCheck %t/ae_roundsq32f48sym.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16_0_i.c | FileCheck %t/ae_s16_0_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16_0_ip.c | FileCheck %t/ae_s16_0_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16_0_x.c | FileCheck %t/ae_s16_0_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16_0_xc.c | FileCheck %t/ae_s16_0_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16_0_xp.c | FileCheck %t/ae_s16_0_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16m_l_i.c | FileCheck %t/ae_s16m_l_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16m_l_iu.c | FileCheck %t/ae_s16m_l_iu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16m_l_x.c | FileCheck %t/ae_s16m_l_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16m_l_xc.c | FileCheck %t/ae_s16m_l_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16m_l_xu.c | FileCheck %t/ae_s16m_l_xu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x2m_i.c | FileCheck %t/ae_s16x2m_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x2m_iu.c | FileCheck %t/ae_s16x2m_iu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x2m_x.c | FileCheck %t/ae_s16x2m_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x2m_xc.c | FileCheck %t/ae_s16x2m_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x2m_xu.c | FileCheck %t/ae_s16x2m_xu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x4_i.c | FileCheck %t/ae_s16x4_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x4_ip.c | FileCheck %t/ae_s16x4_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x4_ric.c | FileCheck %t/ae_s16x4_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x4_rip.c | FileCheck %t/ae_s16x4_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x4_x.c | FileCheck %t/ae_s16x4_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x4_xc.c | FileCheck %t/ae_s16x4_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s16x4_xp.c | FileCheck %t/ae_s16x4_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s24ra64s_i.c | FileCheck %t/ae_s24ra64s_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s24ra64s_ip.c | FileCheck %t/ae_s24ra64s_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s24ra64s_x.c | FileCheck %t/ae_s24ra64s_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s24ra64s_xc.c | FileCheck %t/ae_s24ra64s_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s24ra64s_xp.c | FileCheck %t/ae_s24ra64s_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s24x2ra64s_ip.c | FileCheck %t/ae_s24x2ra64s_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32_l_i.c | FileCheck %t/ae_s32_l_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32_l_ip.c | FileCheck %t/ae_s32_l_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32_l_x.c | FileCheck %t/ae_s32_l_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32_l_xc.c | FileCheck %t/ae_s32_l_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32_l_xp.c | FileCheck %t/ae_s32_l_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32f24_l_i.c | FileCheck %t/ae_s32f24_l_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32f24_l_ip.c | FileCheck %t/ae_s32f24_l_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32f24_l_x.c | FileCheck %t/ae_s32f24_l_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32f24_l_xc.c | FileCheck %t/ae_s32f24_l_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32f24_l_xp.c | FileCheck %t/ae_s32f24_l_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32m_i.c | FileCheck %t/ae_s32m_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32m_iu.c | FileCheck %t/ae_s32m_iu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32m_x.c | FileCheck %t/ae_s32m_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32m_xc.c | FileCheck %t/ae_s32m_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32m_xu.c | FileCheck %t/ae_s32m_xu.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32ra64s_i.c | FileCheck %t/ae_s32ra64s_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32ra64s_ip.c | FileCheck %t/ae_s32ra64s_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32ra64s_x.c | FileCheck %t/ae_s32ra64s_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32ra64s_xc.c | FileCheck %t/ae_s32ra64s_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32ra64s_xp.c | FileCheck %t/ae_s32ra64s_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2_i.c | FileCheck %t/ae_s32x2_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2_ip.c | FileCheck %t/ae_s32x2_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2_ric.c | FileCheck %t/ae_s32x2_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2_rip.c | FileCheck %t/ae_s32x2_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2_x.c | FileCheck %t/ae_s32x2_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2_xc.c | FileCheck %t/ae_s32x2_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2_xp.c | FileCheck %t/ae_s32x2_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2f24_i.c | FileCheck %t/ae_s32x2f24_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2f24_ip.c | FileCheck %t/ae_s32x2f24_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2f24_ric.c | FileCheck %t/ae_s32x2f24_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2f24_rip.c | FileCheck %t/ae_s32x2f24_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2f24_x.c | FileCheck %t/ae_s32x2f24_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2f24_xc.c | FileCheck %t/ae_s32x2f24_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2f24_xp.c | FileCheck %t/ae_s32x2f24_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s32x2ra64s_ip.c | FileCheck %t/ae_s32x2ra64s_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s64_i.c | FileCheck %t/ae_s64_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s64_ip.c | FileCheck %t/ae_s64_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s64_x.c | FileCheck %t/ae_s64_x.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s64_xc.c | FileCheck %t/ae_s64_xc.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_s64_xp.c | FileCheck %t/ae_s64_xp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa16x4_ic.c | FileCheck %t/ae_sa16x4_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa16x4_ip.c | FileCheck %t/ae_sa16x4_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa16x4_ric.c | FileCheck %t/ae_sa16x4_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa16x4_rip.c | FileCheck %t/ae_sa16x4_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa24_l_ic.c | FileCheck %t/ae_sa24_l_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa24_l_ip.c | FileCheck %t/ae_sa24_l_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa24_l_ric.c | FileCheck %t/ae_sa24_l_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa24_l_rip.c | FileCheck %t/ae_sa24_l_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa24x2_ic.c | FileCheck %t/ae_sa24x2_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa24x2_ip.c | FileCheck %t/ae_sa24x2_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa24x2_ric.c | FileCheck %t/ae_sa24x2_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa24x2_rip.c | FileCheck %t/ae_sa24x2_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa32x2_ic.c | FileCheck %t/ae_sa32x2_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa32x2_ip.c | FileCheck %t/ae_sa32x2_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa32x2_ric.c | FileCheck %t/ae_sa32x2_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa32x2_rip.c | FileCheck %t/ae_sa32x2_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa32x2f24_ic.c | FileCheck %t/ae_sa32x2f24_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa32x2f24_ip.c | FileCheck %t/ae_sa32x2f24_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa32x2f24_ric.c | FileCheck %t/ae_sa32x2f24_ric.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa32x2f24_rip.c | FileCheck %t/ae_sa32x2f24_rip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa64neg_fp.c | FileCheck %t/ae_sa64neg_fp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sa64pos_fp.c | FileCheck %t/ae_sa64pos_fp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_salign64_i.c | FileCheck %t/ae_salign64_i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sat16x4.c | FileCheck %t/ae_sat16x4.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sat24s.c | FileCheck %t/ae_sat24s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sat48s.c | FileCheck %t/ae_sat48s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_satq56s.c | FileCheck %t/ae_satq56s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sb.c | FileCheck %t/ae_sb.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sb_ic.c | FileCheck %t/ae_sb_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sb_ip.c | FileCheck %t/ae_sb_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sbf.c | FileCheck %t/ae_sbf.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sbf_ic.c | FileCheck %t/ae_sbf_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sbf_ip.c | FileCheck %t/ae_sbf_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sbi.c | FileCheck %t/ae_sbi.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sbi_ic.c | FileCheck %t/ae_sbi_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sbi_ip.c | FileCheck %t/ae_sbi_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sel16i.c | FileCheck %t/ae_sel16i.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sel16i_n.c | FileCheck %t/ae_sel16i_n.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sext32.c | FileCheck %t/ae_sext32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sext32x2d16_10.c | FileCheck %t/ae_sext32x2d16_10.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sext32x2d16_32.c | FileCheck %t/ae_sext32x2d16_32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sha32.c | FileCheck %t/ae_sha32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_shortswap.c | FileCheck %t/ae_shortswap.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slaa16s.c | FileCheck %t/ae_slaa16s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slaa32.c | FileCheck %t/ae_slaa32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slaa32s.c | FileCheck %t/ae_slaa32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slaa64.c | FileCheck %t/ae_slaa64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slaa64s.c | FileCheck %t/ae_slaa64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slaaq56.c | FileCheck %t/ae_slaaq56.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slai16s.c | FileCheck %t/ae_slai16s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slai24.c | FileCheck %t/ae_slai24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slai24s.c | FileCheck %t/ae_slai24s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slai32.c | FileCheck %t/ae_slai32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slai32s.c | FileCheck %t/ae_slai32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slai64.c | FileCheck %t/ae_slai64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slai64s.c | FileCheck %t/ae_slai64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slaisq56s.c | FileCheck %t/ae_slaisq56s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slas24.c | FileCheck %t/ae_slas24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slas24s.c | FileCheck %t/ae_slas24s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slas32.c | FileCheck %t/ae_slas32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slas32s.c | FileCheck %t/ae_slas32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slas64.c | FileCheck %t/ae_slas64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slas64s.c | FileCheck %t/ae_slas64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slasq56.c | FileCheck %t/ae_slasq56.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_slassq56s.c | FileCheck %t/ae_slassq56s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sra64_32.c | FileCheck %t/ae_sra64_32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sraa16rs.c | FileCheck %t/ae_sraa16rs.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sraa16s.c | FileCheck %t/ae_sraa16s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sraa32.c | FileCheck %t/ae_sraa32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sraa32rs.c | FileCheck %t/ae_sraa32rs.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sraa32s.c | FileCheck %t/ae_sraa32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sraa64.c | FileCheck %t/ae_sraa64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srai16.c | FileCheck %t/ae_srai16.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srai16r.c | FileCheck %t/ae_srai16r.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srai24.c | FileCheck %t/ae_srai24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srai32.c | FileCheck %t/ae_srai32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srai32r.c | FileCheck %t/ae_srai32r.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srai64.c | FileCheck %t/ae_srai64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sras24.c | FileCheck %t/ae_sras24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sras32.c | FileCheck %t/ae_sras32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sras64.c | FileCheck %t/ae_sras64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srla32.c | FileCheck %t/ae_srla32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srla64.c | FileCheck %t/ae_srla64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srli24.c | FileCheck %t/ae_srli24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srli32.c | FileCheck %t/ae_srli32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srli64.c | FileCheck %t/ae_srli64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srls24.c | FileCheck %t/ae_srls24.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srls32.c | FileCheck %t/ae_srls32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_srls64.c | FileCheck %t/ae_srls64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sub16.c | FileCheck %t/ae_sub16.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sub16s.c | FileCheck %t/ae_sub16s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sub24s.c | FileCheck %t/ae_sub24s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sub32.c | FileCheck %t/ae_sub32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sub32s.c | FileCheck %t/ae_sub32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sub64.c | FileCheck %t/ae_sub64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_sub64s.c | FileCheck %t/ae_sub64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_subadd32.c | FileCheck %t/ae_subadd32.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_subadd32s.c | FileCheck %t/ae_subadd32s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_trunca32f64s_l.c | FileCheck %t/ae_trunca32f64s_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_trunca32x2f64s.c | FileCheck %t/ae_trunca32x2f64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_trunci32f64s_l.c | FileCheck %t/ae_trunci32f64s_l.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_trunci32x2f64s.c | FileCheck %t/ae_trunci32x2f64s.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vldl16c.c | FileCheck %t/ae_vldl16c.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vldl16c_ic.c | FileCheck %t/ae_vldl16c_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vldl16c_ip.c | FileCheck %t/ae_vldl16c_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vldl16t.c | FileCheck %t/ae_vldl16t.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vldl32t.c | FileCheck %t/ae_vldl32t.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vldsht.c | FileCheck %t/ae_vldsht.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vlel16t.c | FileCheck %t/ae_vlel16t.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vlel32t.c | FileCheck %t/ae_vlel32t.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vles16c.c | FileCheck %t/ae_vles16c.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vles16c_ic.c | FileCheck %t/ae_vles16c_ic.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_vles16c_ip.c | FileCheck %t/ae_vles16c_ip.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_xor.c | FileCheck %t/ae_xor.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/ae_zalign64.c | FileCheck %t/ae_zalign64.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_bithead.c | FileCheck %t/rur_ae_bithead.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_bitptr.c | FileCheck %t/rur_ae_bitptr.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_bitsused.c | FileCheck %t/rur_ae_bitsused.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_cbegin0.c | FileCheck %t/rur_ae_cbegin0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_cend0.c | FileCheck %t/rur_ae_cend0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_cw_sd_no.c | FileCheck %t/rur_ae_cw_sd_no.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_cwrap.c | FileCheck %t/rur_ae_cwrap.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_first_ts.c | FileCheck %t/rur_ae_first_ts.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_nextoffset.c | FileCheck %t/rur_ae_nextoffset.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_overflow.c | FileCheck %t/rur_ae_overflow.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_ovf_sar.c | FileCheck %t/rur_ae_ovf_sar.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_sar.c | FileCheck %t/rur_ae_sar.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_searchdone.c | FileCheck %t/rur_ae_searchdone.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_tablesize.c | FileCheck %t/rur_ae_tablesize.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/rur_ae_ts_fts_bu_bp.c | FileCheck %t/rur_ae_ts_fts_bu_bp.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_bithead.c | FileCheck %t/wur_ae_bithead.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_bitptr.c | FileCheck %t/wur_ae_bitptr.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_bitsused.c | FileCheck %t/wur_ae_bitsused.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_cbegin0.c | FileCheck %t/wur_ae_cbegin0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_cend0.c | FileCheck %t/wur_ae_cend0.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_cw_sd_no.c | FileCheck %t/wur_ae_cw_sd_no.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_cwrap.c | FileCheck %t/wur_ae_cwrap.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_first_ts.c | FileCheck %t/wur_ae_first_ts.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_nextoffset.c | FileCheck %t/wur_ae_nextoffset.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_overflow.c | FileCheck %t/wur_ae_overflow.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_ovf_sar.c | FileCheck %t/wur_ae_ovf_sar.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_sar.c | FileCheck %t/wur_ae_sar.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_searchdone.c | FileCheck %t/wur_ae_searchdone.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_tablesize.c | FileCheck %t/wur_ae_tablesize.c +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/wur_ae_ts_fts_bu_bp.c | FileCheck %t/wur_ae_ts_fts_bu_bp.c +//--- ae_abs16s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_abs16s(ae_int16x4 ae_arth_v1) { +// CHECK-LABEL: test_ae_abs16s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.abs16s(<4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_abs16s(ae_arth_v1); +} + +//--- ae_abs24s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_abs24s(ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_abs24s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.abs24s(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_abs24s(ae_arth_v1); +} + +//--- ae_abs32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_abs32(ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_abs32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.abs32(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_abs32(ae_arth_v1); +} + +//--- ae_abs32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_abs32s(ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_abs32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.abs32s(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_abs32s(ae_arth_v1); +} + +//--- ae_abs64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_abs64(ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_abs64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.abs64(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_abs64(ae_arth_v1); +} + +//--- ae_abs64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_abs64s(ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_abs64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.abs64s(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_abs64s(ae_arth_v1); +} + +//--- ae_add16.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_add16(ae_int16x4 ae_arth_v0,ae_int16x4 ae_arth_v1) { +// CHECK-LABEL: test_ae_add16 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.add16(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_add16(ae_arth_v0, ae_arth_v1); +} + +//--- ae_add16s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_add16s(ae_int16x4 ae_arth_v0,ae_int16x4 ae_arth_v1) { +// CHECK-LABEL: test_ae_add16s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.add16s(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_add16s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_add24s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_add24s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_add24s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.add24s(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_add24s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_add32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_add32(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_add32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.add32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_add32(ae_arth_v0, ae_arth_v1); +} + +//--- ae_add32_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_add32_hl_lh(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_add32_hl_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.add32.hl.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_add32_hl_lh(ae_arth_v0, ae_arth_v1); +} + +//--- ae_add32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_add32s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_add32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.add32s(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_add32s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_add64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_add64(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_add64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.add64(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_add64(ae_arth_v0, ae_arth_v1); +} + +//--- ae_add64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_add64s(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_add64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.add64s(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_add64s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_addbrba32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_addbrba32(int art,int ars) { +// CHECK-LABEL: test_ae_addbrba32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.addbrba32(i32 {{.*}}, i32 {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_addbrba32(art, ars); +} + +//--- ae_addsub32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_addsub32(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_addsub32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.addsub32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_addsub32(ae_arth_v0, ae_arth_v1); +} + +//--- ae_addsub32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_addsub32s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_addsub32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.addsub32s(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_addsub32s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_and.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_and(ae_int64 ae_dr_to_dr_v0,ae_int64 ae_dr_to_dr_v1) { +// CHECK-LABEL: test_ae_and +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.and(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_and(ae_dr_to_dr_v0, ae_dr_to_dr_v1); +} + +//--- ae_cvt32x2f16_10.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_cvt32x2f16_10(ae_int16x4 ae_to_dr_v0) { +// CHECK-LABEL: test_ae_cvt32x2f16_10 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.cvt32x2f16.10(<4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_cvt32x2f16_10(ae_to_dr_v0); +} + +//--- ae_cvt32x2f16_32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_cvt32x2f16_32(ae_int16x4 ae_to_dr_v0) { +// CHECK-LABEL: test_ae_cvt32x2f16_32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.cvt32x2f16.32(<4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_cvt32x2f16_32(ae_to_dr_v0); +} + +//--- ae_cvt48a32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_cvt48a32(int ars) { +// CHECK-LABEL: test_ae_cvt48a32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.cvt48a32(i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_cvt48a32(ars); +} + +//--- ae_cvt64a32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_cvt64a32(int ars) { +// CHECK-LABEL: test_ae_cvt64a32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.cvt64a32(i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_cvt64a32(ars); +} + +//--- ae_cvt64f32_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_cvt64f32_h(ae_int32x2 ae_dr_to_dr_v0) { +// CHECK-LABEL: test_ae_cvt64f32_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.cvt64f32.h(<2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_cvt64f32_h(ae_dr_to_dr_v0); +} + +//--- ae_cvta32f24s_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_cvta32f24s_h(ae_int32x2 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_cvta32f24s_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.cvta32f24s.h(<2 x i32> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_cvta32f24s_h(ae_dr_to_ar_v0); +} + +//--- ae_cvta32f24s_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_cvta32f24s_l(ae_int32x2 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_cvta32f24s_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.cvta32f24s.l(<2 x i32> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_cvta32f24s_l(ae_dr_to_ar_v0); +} + +//--- ae_cvtq56a32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_cvtq56a32s(int ars) { +// CHECK-LABEL: test_ae_cvtq56a32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.cvtq56a32s(i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_cvtq56a32s(ars); +} + +//--- ae_cvtq56p32s_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_cvtq56p32s_h(ae_int32x2 ae_dr_to_dr_v0) { +// CHECK-LABEL: test_ae_cvtq56p32s_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.cvtq56p32s.h(<2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_cvtq56p32s_h(ae_dr_to_dr_v0); +} + +//--- ae_cvtq56p32s_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_cvtq56p32s_l(ae_int32x2 ae_dr_to_dr_v0) { +// CHECK-LABEL: test_ae_cvtq56p32s_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.cvtq56p32s.l(<2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_cvtq56p32s_l(ae_dr_to_dr_v0); +} + +//--- ae_db.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_db(const short** ars,int art) { +// CHECK-LABEL: test_ae_db +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.db(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_db(ars, art); +} + +//--- ae_db_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_db_ic(const short** ars,int art) { +// CHECK-LABEL: test_ae_db_ic +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.db.ic(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_db_ic(ars, art); +} + +//--- ae_db_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_db_ip(const short** ars,int art) { +// CHECK-LABEL: test_ae_db_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.db.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_db_ip(ars, art); +} + +//--- ae_dbi.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_dbi(const short** ars,immediate ae_ohba) { +// CHECK-LABEL: test_ae_dbi +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.dbi(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_dbi(ars, 1); +} + +//--- ae_dbi_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_dbi_ic(const short** ars,immediate ae_ohba) { +// CHECK-LABEL: test_ae_dbi_ic +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.dbi.ic(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_dbi_ic(ars, 1); +} + +//--- ae_dbi_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_dbi_ip(const short** ars,immediate ae_ohba) { +// CHECK-LABEL: test_ae_dbi_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.dbi.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_dbi_ip(ars, 1); +} + +//--- ae_div64d32_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_div64d32_h(ae_int64* ae_arth_v,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_div64d32_h +// CHECK: %[[LD_AE_ARTH_V:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.div64d32.h(<1 x i64> %[[LD_AE_ARTH_V]], <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_div64d32_h(ae_arth_v, ae_arth_v1); +} + +//--- ae_div64d32_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_div64d32_l(ae_int64* ae_arth_v,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_div64d32_l +// CHECK: %[[LD_AE_ARTH_V:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.div64d32.l(<1 x i64> %[[LD_AE_ARTH_V]], <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_div64d32_l(ae_arth_v, ae_arth_v1); +} + +//--- ae_eq16.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool4 test_ae_eq16(ae_int16x4 ae_cmpp_v0,ae_int16x4 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_eq16 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i1> @llvm.xtensa.ae.eq16(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i1> %[[RET]] +return __builtin_xtensa_ae_eq16(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_eq32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool2 test_ae_eq32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_eq32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i1> @llvm.xtensa.ae.eq32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i1> %[[RET]] +return __builtin_xtensa_ae_eq32(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_eq64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool test_ae_eq64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_eq64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i1> @llvm.xtensa.ae.eq64(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i1> %[[RET]] +return __builtin_xtensa_ae_eq64(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_l16_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_l16_i(const ae_int16* ars,immediate ae_immls16) { +// CHECK-LABEL: test_ae_l16_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.l16.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_l16_i(ars, -16); +} + +//--- ae_l16_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16_ip(ae_int16x4* ae_ls_v,const ae_int16** ars,immediate ae_immls16) { +// CHECK-LABEL: test_ae_l16_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, ptr } @llvm.xtensa.ae.l16.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16_ip(ae_ls_v, ars, -16); +} + +//--- ae_l16_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_l16_x(const ae_int16* ars,int art) { +// CHECK-LABEL: test_ae_l16_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.l16.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_l16_x(ars, art); +} + +//--- ae_l16_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16_xc(ae_int16x4* ae_ls_v,const ae_int16** ars,int art) { +// CHECK-LABEL: test_ae_l16_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, ptr } @llvm.xtensa.ae.l16.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16_xc(ae_ls_v, ars, art); +} + +//--- ae_l16_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16_xp(ae_int16x4* ae_ls_v,const ae_int16** ars,int art) { +// CHECK-LABEL: test_ae_l16_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, ptr } @llvm.xtensa.ae.l16.xp(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16_xp(ae_ls_v, ars, art); +} + +//--- ae_l16m_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l16m_i(const ae_int16* ars,immediate ae_immls16) { +// CHECK-LABEL: test_ae_l16m_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l16m.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l16m_i(ars, -16); +} + +//--- ae_l16m_iu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16m_iu(ae_int32x2* ae_ls_v,const ae_int16** ars,immediate ae_immls16) { +// CHECK-LABEL: test_ae_l16m_iu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.iu(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16m_iu(ae_ls_v, ars, -16); +} + +//--- ae_l16m_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l16m_x(const ae_int16* ars,int art) { +// CHECK-LABEL: test_ae_l16m_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l16m.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l16m_x(ars, art); +} + +//--- ae_l16m_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16m_xc(ae_int32x2* ae_ls_v,const ae_int16** ars,int art) { +// CHECK-LABEL: test_ae_l16m_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16m_xc(ae_ls_v, ars, art); +} + +//--- ae_l16m_xu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16m_xu(ae_int32x2* ae_ls_v,const ae_int16** ars,int art) { +// CHECK-LABEL: test_ae_l16m_xu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l16m.xu(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16m_xu(ae_ls_v, ars, art); +} + +//--- ae_l16x2m_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l16x2m_i(const ae_int16x2* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_l16x2m_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l16x2m.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l16x2m_i(ars, -32); +} + +//--- ae_l16x2m_iu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16x2m_iu(ae_int32x2* ae_ls_v,const ae_int16x2** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_l16x2m_iu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.iu(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16x2m_iu(ae_ls_v, ars, -32); +} + +//--- ae_l16x2m_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l16x2m_x(const ae_int16x2* ars,int art) { +// CHECK-LABEL: test_ae_l16x2m_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l16x2m.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l16x2m_x(ars, art); +} + +//--- ae_l16x2m_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16x2m_xc(ae_int32x2* ae_ls_v,const ae_int16x2** ars,int art) { +// CHECK-LABEL: test_ae_l16x2m_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16x2m_xc(ae_ls_v, ars, art); +} + +//--- ae_l16x2m_xu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16x2m_xu(ae_int32x2* ae_ls_v,const ae_int16x2** ars,int art) { +// CHECK-LABEL: test_ae_l16x2m_xu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l16x2m.xu(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16x2m_xu(ae_ls_v, ars, art); +} + +//--- ae_l16x4_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_l16x4_i(const ae_int16x4* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_l16x4_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.l16x4.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_l16x4_i(ars, -64); +} + +//--- ae_l16x4_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16x4_ip(ae_int16x4* ae_ls_v,const ae_int16x4** ars,immediate ae_immls64pos) { +// CHECK-LABEL: test_ae_l16x4_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16x4_ip(ae_ls_v, ars, 0); +} + +//--- ae_l16x4_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16x4_ric(ae_int16x4* ae_ls_v,const ae_int16x4** ars) { +// CHECK-LABEL: test_ae_l16x4_ric +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.ric(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16x4_ric(ae_ls_v, ars); +} + +//--- ae_l16x4_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16x4_rip(ae_int16x4* ae_ls_v,const ae_int16x4** ars) { +// CHECK-LABEL: test_ae_l16x4_rip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.rip(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16x4_rip(ae_ls_v, ars); +} + +//--- ae_l16x4_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_l16x4_x(const ae_int16x4* ars,int art) { +// CHECK-LABEL: test_ae_l16x4_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.l16x4.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_l16x4_x(ars, art); +} + +//--- ae_l16x4_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16x4_xc(ae_int16x4* ae_ls_v,const ae_int16x4** ars,int art) { +// CHECK-LABEL: test_ae_l16x4_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16x4_xc(ae_ls_v, ars, art); +} + +//--- ae_l16x4_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l16x4_xp(ae_int16x4* ae_ls_v,const ae_int16x4** ars,int art) { +// CHECK-LABEL: test_ae_l16x4_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, ptr } @llvm.xtensa.ae.l16x4.xp(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l16x4_xp(ae_ls_v, ars, art); +} + +//--- ae_l32_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l32_i(const ae_int32* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_l32_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l32.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l32_i(ars, -32); +} + +//--- ae_l32_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32_ip(ae_int32x2* ae_ls_v,const ae_int32** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_l32_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32_ip(ae_ls_v, ars, -32); +} + +//--- ae_l32_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l32_x(const ae_int32* ars,int art) { +// CHECK-LABEL: test_ae_l32_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l32.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l32_x(ars, art); +} + +//--- ae_l32_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32_xc(ae_int32x2* ae_ls_v,const ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_l32_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32_xc(ae_ls_v, ars, art); +} + +//--- ae_l32_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32_xp(ae_int32x2* ae_ls_v,const ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_l32_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32.xp(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32_xp(ae_ls_v, ars, art); +} + +//--- ae_l32f24_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l32f24_i(const ae_int32* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_l32f24_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l32f24.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l32f24_i(ars, -32); +} + +//--- ae_l32f24_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32f24_ip(ae_int32x2* ae_ls_v,const ae_int32** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_l32f24_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32f24_ip(ae_ls_v, ars, -32); +} + +//--- ae_l32f24_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l32f24_x(const ae_int32* ars,int art) { +// CHECK-LABEL: test_ae_l32f24_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l32f24.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l32f24_x(ars, art); +} + +//--- ae_l32f24_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32f24_xc(ae_int32x2* ae_ls_v,const ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_l32f24_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32f24_xc(ae_ls_v, ars, art); +} + +//--- ae_l32f24_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32f24_xp(ae_int32x2* ae_ls_v,const ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_l32f24_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32f24.xp(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32f24_xp(ae_ls_v, ars, art); +} + +//--- ae_l32m_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_l32m_i(const ae_int32* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_l32m_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.l32m.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_l32m_i(ars, -32); +} + +//--- ae_l32m_iu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32m_iu(ae_int64* ae_ls_v,const ae_int32** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_l32m_iu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.iu(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32m_iu(ae_ls_v, ars, -32); +} + +//--- ae_l32m_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_l32m_x(const ae_int32* ars,int art) { +// CHECK-LABEL: test_ae_l32m_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.l32m.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_l32m_x(ars, art); +} + +//--- ae_l32m_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32m_xc(ae_int64* ae_ls_v,const ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_l32m_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32m_xc(ae_ls_v, ars, art); +} + +//--- ae_l32m_xu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32m_xu(ae_int64* ae_ls_v,const ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_l32m_xu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, ptr } @llvm.xtensa.ae.l32m.xu(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32m_xu(ae_ls_v, ars, art); +} + +//--- ae_l32x2_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l32x2_i(const ae_int32x2* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_l32x2_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l32x2.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l32x2_i(ars, -64); +} + +//--- ae_l32x2_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2_ip(ae_int32x2* ae_ls_v,const ae_int32x2** ars,immediate ae_immls64pos) { +// CHECK-LABEL: test_ae_l32x2_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2_ip(ae_ls_v, ars, 0); +} + +//--- ae_l32x2_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2_ric(ae_int32x2* ae_ls_v,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_l32x2_ric +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.ric(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2_ric(ae_ls_v, ars); +} + +//--- ae_l32x2_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2_rip(ae_int32x2* ae_ls_v,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_l32x2_rip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.rip(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2_rip(ae_ls_v, ars); +} + +//--- ae_l32x2_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l32x2_x(const ae_int32x2* ars,int art) { +// CHECK-LABEL: test_ae_l32x2_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l32x2.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l32x2_x(ars, art); +} + +//--- ae_l32x2_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2_xc(ae_int32x2* ae_ls_v,const ae_int32x2** ars,int art) { +// CHECK-LABEL: test_ae_l32x2_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2_xc(ae_ls_v, ars, art); +} + +//--- ae_l32x2_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2_xp(ae_int32x2* ae_ls_v,const ae_int32x2** ars,int art) { +// CHECK-LABEL: test_ae_l32x2_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2.xp(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2_xp(ae_ls_v, ars, art); +} + +//--- ae_l32x2f24_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l32x2f24_i(const ae_int32x2* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_l32x2f24_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l32x2f24.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l32x2f24_i(ars, -64); +} + +//--- ae_l32x2f24_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2f24_ip(ae_int32x2* ae_ls_v,const ae_int32x2** ars,immediate ae_immls64pos) { +// CHECK-LABEL: test_ae_l32x2f24_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2f24_ip(ae_ls_v, ars, 0); +} + +//--- ae_l32x2f24_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2f24_ric(ae_int32x2* ae_ls_v,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_l32x2f24_ric +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.ric(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2f24_ric(ae_ls_v, ars); +} + +//--- ae_l32x2f24_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2f24_rip(ae_int32x2* ae_ls_v,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_l32x2f24_rip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.rip(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2f24_rip(ae_ls_v, ars); +} + +//--- ae_l32x2f24_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_l32x2f24_x(const ae_int32x2* ars,int art) { +// CHECK-LABEL: test_ae_l32x2f24_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.l32x2f24.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_l32x2f24_x(ars, art); +} + +//--- ae_l32x2f24_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2f24_xc(ae_int32x2* ae_ls_v,const ae_int32x2** ars,int art) { +// CHECK-LABEL: test_ae_l32x2f24_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2f24_xc(ae_ls_v, ars, art); +} + +//--- ae_l32x2f24_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l32x2f24_xp(ae_int32x2* ae_ls_v,const ae_int32x2** ars,int art) { +// CHECK-LABEL: test_ae_l32x2f24_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, ptr } @llvm.xtensa.ae.l32x2f24.xp(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l32x2f24_xp(ae_ls_v, ars, art); +} + +//--- ae_l64_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_l64_i(const ae_int64* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_l64_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.l64.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_l64_i(ars, -64); +} + +//--- ae_l64_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l64_ip(ae_int64* ae_ls_v,const ae_int64** ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_l64_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, ptr } @llvm.xtensa.ae.l64.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l64_ip(ae_ls_v, ars, -64); +} + +//--- ae_l64_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_l64_x(const ae_int64* ars,int art) { +// CHECK-LABEL: test_ae_l64_x +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.l64.x(ptr {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_l64_x(ars, art); +} + +//--- ae_l64_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l64_xc(ae_int64* ae_ls_v,const ae_int64** ars,int art) { +// CHECK-LABEL: test_ae_l64_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, ptr } @llvm.xtensa.ae.l64.xc(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l64_xc(ae_ls_v, ars, art); +} + +//--- ae_l64_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_l64_xp(ae_int64* ae_ls_v,const ae_int64** ars,int art) { +// CHECK-LABEL: test_ae_l64_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, ptr } @llvm.xtensa.ae.l64.xp(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_l64_xp(ae_ls_v, ars, art); +} + +//--- ae_la16x4_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la16x4_ic(ae_int16x4* ae_ls_av,ae_valign* ae_ls_uu,const ae_int16x4** ars) { +// CHECK-LABEL: test_ae_la16x4_ic +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ic(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la16x4_ic(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la16x4_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la16x4_ip(ae_int16x4* ae_ls_av,ae_valign* ae_ls_uu,const ae_int16x4** ars) { +// CHECK-LABEL: test_ae_la16x4_ip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la16x4_ip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la16x4_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la16x4_ric(ae_int16x4* ae_ls_av,ae_valign* ae_ls_uu,const ae_int16x4** ars) { +// CHECK-LABEL: test_ae_la16x4_ric +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.ric(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la16x4_ric(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la16x4_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la16x4_rip(ae_int16x4* ae_ls_av,ae_valign* ae_ls_uu,const ae_int16x4** ars) { +// CHECK-LABEL: test_ae_la16x4_rip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <4 x i16>, <8 x i8>, ptr } @llvm.xtensa.ae.la16x4.rip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <4 x i16>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la16x4_rip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la16x4neg_pc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la16x4neg_pc(ae_valign* ae_ls_uu,const ae_int16x4** ars) { +// CHECK-LABEL: test_ae_la16x4neg_pc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.la16x4neg.pc(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la16x4neg_pc(ae_ls_uu, ars); +} + +//--- ae_la16x4pos_pc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la16x4pos_pc(ae_valign* ae_ls_uu,const ae_int16x4** ars) { +// CHECK-LABEL: test_ae_la16x4pos_pc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.la16x4pos.pc(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la16x4pos_pc(ae_ls_uu, ars); +} + +//--- ae_la24_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24_ic(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24_ic +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ic(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24_ic(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la24_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24_ip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24_ip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24_ip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la24_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24_ric(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24_ric +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.ric(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24_ric(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la24_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24_rip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24_rip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24.rip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24_rip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la24neg_pc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24neg_pc(ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24neg_pc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.la24neg.pc(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24neg_pc(ae_ls_uu, ars); +} + +//--- ae_la24pos_pc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24pos_pc(ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24pos_pc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.la24pos.pc(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24pos_pc(ae_ls_uu, ars); +} + +//--- ae_la24x2_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24x2_ic(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24x2_ic +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ic(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24x2_ic(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la24x2_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24x2_ip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24x2_ip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24x2_ip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la24x2_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24x2_ric(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24x2_ric +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.ric(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24x2_ric(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la24x2_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24x2_rip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24x2_rip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la24x2.rip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24x2_rip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la24x2neg_pc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24x2neg_pc(ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24x2neg_pc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.la24x2neg.pc(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24x2neg_pc(ae_ls_uu, ars); +} + +//--- ae_la24x2pos_pc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la24x2pos_pc(ae_valign* ae_ls_uu,const void** ars) { +// CHECK-LABEL: test_ae_la24x2pos_pc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.la24x2pos.pc(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la24x2pos_pc(ae_ls_uu, ars); +} + +//--- ae_la32x2_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2_ic(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2_ic +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ic(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2_ic(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la32x2_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2_ip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2_ip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2_ip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la32x2_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2_ric(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2_ric +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.ric(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2_ric(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la32x2_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2_rip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2_rip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2.rip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2_rip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la32x2f24_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2f24_ic(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2f24_ic +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ic(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2f24_ic(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la32x2f24_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2f24_ip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2f24_ip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2f24_ip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la32x2f24_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2f24_ric(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2f24_ric +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.ric(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2f24_ric(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la32x2f24_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2f24_rip(ae_int32x2* ae_ls_av,ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2f24_rip +// CHECK: %[[LD_AE_LS_UU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <8 x i8>, ptr } @llvm.xtensa.ae.la32x2f24.rip(<8 x i8> %[[LD_AE_LS_UU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2f24_rip(ae_ls_av, ae_ls_uu, ars); +} + +//--- ae_la32x2neg_pc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2neg_pc(ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2neg_pc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.la32x2neg.pc(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2neg_pc(ae_ls_uu, ars); +} + +//--- ae_la32x2pos_pc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_la32x2pos_pc(ae_valign* ae_ls_uu,const ae_int32x2** ars) { +// CHECK-LABEL: test_ae_la32x2pos_pc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.la32x2pos.pc(ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_la32x2pos_pc(ae_ls_uu, ars); +} + +//--- ae_la64_pp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_valign test_ae_la64_pp(const void* ars) { +// CHECK-LABEL: test_ae_la64_pp +// CHECK: %[[RET:.*]] = {{(tail)?}} call <8 x i8> @llvm.xtensa.ae.la64.pp(ptr {{.*}}) +// CHECK: %[[CAST:.*]] = bitcast <8 x i8> %[[RET]] to i64 +// CHECK: ret i64 %[[CAST]] +return __builtin_xtensa_ae_la64_pp(ars); +} + +//--- ae_lalign64_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_valign test_ae_lalign64_i(const ae_valign* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_lalign64_i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <8 x i8> @llvm.xtensa.ae.lalign64.i(ptr {{.*}}, i32 {{.*}}) +// CHECK: %[[CAST:.*]] = bitcast <8 x i8> %[[RET]] to i64 +// CHECK: ret i64 %[[CAST]] +return __builtin_xtensa_ae_lalign64_i(ars, -64); +} + +//--- ae_lb.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_lb(int art) { +// CHECK-LABEL: test_ae_lb +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.lb(i32 {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_lb(art); +} + +//--- ae_lbi.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_lbi(immediate ae_ohba) { +// CHECK-LABEL: test_ae_lbi +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.lbi(i32 {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_lbi(1); +} + +//--- ae_lbk.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_lbk(int ars,int art) { +// CHECK-LABEL: test_ae_lbk +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.lbk(i32 {{.*}}, i32 {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_lbk(ars, art); +} + +//--- ae_lbki.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_lbki(int ars,immediate ae_ohba) { +// CHECK-LABEL: test_ae_lbki +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.lbki(i32 {{.*}}, i32 {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_lbki(ars, 1); +} + +//--- ae_lbs.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_lbs(int art) { +// CHECK-LABEL: test_ae_lbs +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.lbs(i32 {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_lbs(art); +} + +//--- ae_lbsi.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_lbsi(immediate ae_ohba) { +// CHECK-LABEL: test_ae_lbsi +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.lbsi(i32 {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_lbsi(1); +} + +//--- ae_le16.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool4 test_ae_le16(ae_int16x4 ae_cmpp_v0,ae_int16x4 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_le16 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i1> @llvm.xtensa.ae.le16(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i1> %[[RET]] +return __builtin_xtensa_ae_le16(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_le32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool2 test_ae_le32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_le32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i1> @llvm.xtensa.ae.le32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i1> %[[RET]] +return __builtin_xtensa_ae_le32(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_le64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool test_ae_le64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_le64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i1> @llvm.xtensa.ae.le64(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i1> %[[RET]] +return __builtin_xtensa_ae_le64(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_lt16.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool4 test_ae_lt16(ae_int16x4 ae_cmpp_v0,ae_int16x4 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_lt16 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i1> @llvm.xtensa.ae.lt16(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i1> %[[RET]] +return __builtin_xtensa_ae_lt16(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_lt32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool2 test_ae_lt32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_lt32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i1> @llvm.xtensa.ae.lt32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i1> %[[RET]] +return __builtin_xtensa_ae_lt32(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_lt64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +xtbool test_ae_lt64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_lt64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i1> @llvm.xtensa.ae.lt64(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i1> %[[RET]] +return __builtin_xtensa_ae_lt64(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_max32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_max32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_max32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.max32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_max32(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_max64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_max64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_max64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.max64(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_max64(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_maxabs32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_maxabs32s(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_maxabs32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.maxabs32s(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_maxabs32s(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_maxabs64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_maxabs64s(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_maxabs64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.maxabs64s(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_maxabs64s(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_min32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_min32(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_min32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.min32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_min32(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_min64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_min64(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_min64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.min64(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_min64(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_minabs32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_minabs32s(ae_int32x2 ae_cmpp_v0,ae_int32x2 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_minabs32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.minabs32s(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_minabs32s(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_minabs64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_minabs64s(ae_int64 ae_cmpp_v0,ae_int64 ae_cmpp_v1) { +// CHECK-LABEL: test_ae_minabs64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.minabs64s(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_minabs64s(ae_cmpp_v0, ae_cmpp_v1); +} + +//--- ae_mov.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mov(ae_int64 ae_to_dr_v0) { +// CHECK-LABEL: test_ae_mov +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mov(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mov(ae_to_dr_v0); +} + +//--- ae_movad16_0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_movad16_0(ae_int16x4 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_movad16_0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.movad16.0(<4 x i16> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_movad16_0(ae_dr_to_ar_v0); +} + +//--- ae_movad16_1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_movad16_1(ae_int16x4 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_movad16_1 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.movad16.1(<4 x i16> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_movad16_1(ae_dr_to_ar_v0); +} + +//--- ae_movad16_2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_movad16_2(ae_int16x4 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_movad16_2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.movad16.2(<4 x i16> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_movad16_2(ae_dr_to_ar_v0); +} + +//--- ae_movad16_3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_movad16_3(ae_int16x4 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_movad16_3 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.movad16.3(<4 x i16> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_movad16_3(ae_dr_to_ar_v0); +} + +//--- ae_movad32_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_movad32_h(ae_int32x2 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_movad32_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.movad32.h(<2 x i32> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_movad32_h(ae_dr_to_ar_v0); +} + +//--- ae_movad32_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_movad32_l(ae_int32x2 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_movad32_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.movad32.l(<2 x i32> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_movad32_l(ae_dr_to_ar_v0); +} + +//--- ae_movalign.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_valign test_ae_movalign(ae_valign ae_uu_v) { +// CHECK-LABEL: test_ae_movalign +// CHECK: %[[RET:.*]] = {{(tail)?}} call <8 x i8> @llvm.xtensa.ae.movalign(<8 x i8> {{.*}}) +// CHECK: %[[CAST:.*]] = bitcast <8 x i8> %[[RET]] to i64 +// CHECK: ret i64 %[[CAST]] +return __builtin_xtensa_ae_movalign(ae_uu_v); +} + +//--- ae_movda16.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_movda16(int ars) { +// CHECK-LABEL: test_ae_movda16 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.movda16(i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_movda16(ars); +} + +//--- ae_movda16x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_movda16x2(int ars,int art) { +// CHECK-LABEL: test_ae_movda16x2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.movda16x2(i32 {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_movda16x2(ars, art); +} + +//--- ae_movda32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32 test_ae_movda32(int ars) { +// CHECK-LABEL: test_ae_movda32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i32> @llvm.xtensa.ae.movda32(i32 {{.*}}) +// CHECK: ret <1 x i32> %[[RET]] +return __builtin_xtensa_ae_movda32(ars); +} + +//--- ae_movda32x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_movda32x2(int ars,int art) { +// CHECK-LABEL: test_ae_movda32x2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.movda32x2(i32 {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_movda32x2(ars, art); +} + +//--- ae_movf16x4.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_movf16x4(ae_int16x4* ae_cmov_v,ae_int16x4 ae_cmov_v0,xtbool4 bt4) { +// CHECK-LABEL: test_ae_movf16x4 +// CHECK: %[[LD_AE_CMOV_V:.*]] = load <4 x i16>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.movf16x4(<4 x i16> %[[LD_AE_CMOV_V]], <4 x i16> {{.*}}, <4 x i1> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_movf16x4(ae_cmov_v, ae_cmov_v0, bt4); +} + +//--- ae_movf32x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_movf32x2(ae_int32x2* ae_cmov_v,ae_int32x2 ae_cmov_v0,xtbool2 bt2) { +// CHECK-LABEL: test_ae_movf32x2 +// CHECK: %[[LD_AE_CMOV_V:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.movf32x2(<2 x i32> %[[LD_AE_CMOV_V]], <2 x i32> {{.*}}, <2 x i1> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_movf32x2(ae_cmov_v, ae_cmov_v0, bt2); +} + +//--- ae_movf64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_movf64(ae_int64* ae_cmov_v,ae_int64 ae_cmov_v0,xtbool bt) { +// CHECK-LABEL: test_ae_movf64 +// CHECK: %[[LD_AE_CMOV_V:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.movf64(<1 x i64> %[[LD_AE_CMOV_V]], <1 x i64> {{.*}}, <1 x i1> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_movf64(ae_cmov_v, ae_cmov_v0, bt); +} + +//--- ae_movi.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_movi(immediate movi_imm) { +// CHECK-LABEL: test_ae_movi +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.movi(i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_movi(-16); +} + +//--- ae_movt16x4.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_movt16x4(ae_int16x4* ae_cmov_v,ae_int16x4 ae_cmov_v0,xtbool4 bt4) { +// CHECK-LABEL: test_ae_movt16x4 +// CHECK: %[[LD_AE_CMOV_V:.*]] = load <4 x i16>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.movt16x4(<4 x i16> %[[LD_AE_CMOV_V]], <4 x i16> {{.*}}, <4 x i1> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_movt16x4(ae_cmov_v, ae_cmov_v0, bt4); +} + +//--- ae_movt32x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_movt32x2(ae_int32x2* ae_cmov_v,ae_int32x2 ae_cmov_v0,xtbool2 bt2) { +// CHECK-LABEL: test_ae_movt32x2 +// CHECK: %[[LD_AE_CMOV_V:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.movt32x2(<2 x i32> %[[LD_AE_CMOV_V]], <2 x i32> {{.*}}, <2 x i1> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_movt32x2(ae_cmov_v, ae_cmov_v0, bt2); +} + +//--- ae_movt64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_movt64(ae_int64* ae_cmov_v,ae_int64 ae_cmov_v0,xtbool bt) { +// CHECK-LABEL: test_ae_movt64 +// CHECK: %[[LD_AE_CMOV_V:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.movt64(<1 x i64> %[[LD_AE_CMOV_V]], <1 x i64> {{.*}}, <1 x i1> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_movt64(ae_cmov_v, ae_cmov_v0, bt); +} + +//--- ae_mul16x4.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mul16x4(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) { +// CHECK-LABEL: test_ae_mul16x4 +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mul16x4(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <2 x i32> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mul16x4(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0); +} + +//--- ae_mul32_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32_hh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32_hh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32.hh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32_hh(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32_lh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32_lh(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32_ll(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mul32u_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32u_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32u_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32u.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32u_ll(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_h0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_h0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32x16_h0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.h0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_h0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_h0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_h0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32x16_h0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.h0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_h0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mul32x16_h1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_h1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32x16_h1 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.h1(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_h1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_h1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_h1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32x16_h1_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.h1.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_h1_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mul32x16_h2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_h2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32x16_h2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.h2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_h2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_h2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_h2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32x16_h2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.h2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_h2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mul32x16_h3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_h3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32x16_h3 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.h3(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_h3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_h3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_h3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32x16_h3_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.h3.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_h3_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mul32x16_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32x16_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32x16_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mul32x16_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_l1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32x16_l1 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.l1(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_l1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_l1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32x16_l1_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.l1.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_l1_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mul32x16_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32x16_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32x16_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mul32x16_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_l3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mul32x16_l3 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.l3(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_l3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mul32x16_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mul32x16_l3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mul32x16_l3_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mul32x16.l3.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mul32x16_l3_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula16x4.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula16x4(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) { +// CHECK-LABEL: test_ae_mula16x4 +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mula16x4(<2 x i32> %[[LD_AE_MUL_Q1]], <2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <2 x i32> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mula16x4(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0); +} + +//--- ae_mula32_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32_hh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32.hh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32_hh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32_lh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32.lh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32_lh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula32u_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32u_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32u_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32u.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32u_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_h0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_h0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32x16_h0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.h0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_h0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_h0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_h0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32x16_h0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.h0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_h0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula32x16_h1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_h1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32x16_h1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.h1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_h1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_h1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_h1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32x16_h1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.h1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_h1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula32x16_h2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_h2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32x16_h2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.h2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_h2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_h2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_h2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32x16_h2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.h2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_h2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula32x16_h3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_h3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32x16_h3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.h3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_h3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_h3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_h3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32x16_h3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.h3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_h3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula32x16_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32x16_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32x16_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula32x16_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32x16_l1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.l1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_l1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32x16_l1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.l1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_l1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula32x16_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32x16_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32x16_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mula32x16_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mula32x16_l3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.l3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_l3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mula32x16_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mula32x16_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mula32x16_l3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mula32x16.l3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mula32x16_l3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaad24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaad24_hh_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad24.hh.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad24_hh_ll(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaad24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaad24_hh_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad24.hh.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad24_hh_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaad24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaad24_hl_lh +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad24.hl.lh(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad24_hl_lh(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaad24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaad24_hl_lh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad24.hl.lh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad24_hl_lh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaad32x16_h0_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad32x16_h0_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaad32x16_h0_l1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h0.l1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad32x16_h0_l1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaad32x16_h0_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad32x16_h0_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaad32x16_h0_l1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h0.l1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad32x16_h0_l1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaad32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaad32x16_h1_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h1.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad32x16_h1_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaad32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaad32x16_h1_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h1.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad32x16_h1_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaad32x16_h2_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad32x16_h2_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaad32x16_h2_l3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h2.l3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad32x16_h2_l3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaad32x16_h2_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad32x16_h2_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaad32x16_h2_l3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h2.l3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad32x16_h2_l3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaad32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaad32x16_h3_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h3.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad32x16_h3_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaad32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaad32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaad32x16_h3_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaad32x16.h3.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaad32x16_h3_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd16ss_11_00.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd16ss_11_00(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaafd16ss_11_00 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.11.00(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd16ss_11_00(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaafd16ss_11_00_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd16ss_11_00_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd16ss_11_00_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.11.00.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd16ss_11_00_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd16ss_13_02.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd16ss_13_02(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaafd16ss_13_02 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.13.02(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd16ss_13_02(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaafd16ss_13_02_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd16ss_13_02_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd16ss_13_02_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.13.02.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd16ss_13_02_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd16ss_33_22.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd16ss_33_22(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaafd16ss_33_22 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.33.22(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd16ss_33_22(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaafd16ss_33_22_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd16ss_33_22_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd16ss_33_22_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaafd16ss.33.22.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd16ss_33_22_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaafd24_hh_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd24.hh.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd24_hh_ll(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaafd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd24_hh_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd24.hh.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd24_hh_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaafd24_hl_lh +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd24.hl.lh(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd24_hl_lh(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaafd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd24_hl_lh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd24.hl.lh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd24_hl_lh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd32x16_h0_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd32x16_h0_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaafd32x16_h0_l1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h0.l1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd32x16_h0_l1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaafd32x16_h0_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd32x16_h0_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd32x16_h0_l1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h0.l1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd32x16_h0_l1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaafd32x16_h1_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h1.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaafd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd32x16_h1_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h1.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd32x16_h1_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd32x16_h2_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd32x16_h2_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaafd32x16_h2_l3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h2.l3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd32x16_h2_l3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaafd32x16_h2_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd32x16_h2_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd32x16_h2_l3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h2.l3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd32x16_h2_l3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaafd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaafd32x16_h3_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h3.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaafd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaafd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaafd32x16_h3_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaafd32x16.h3.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaafd32x16_h3_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulac24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulac24(ae_int32x2* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulac24 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulac24(<2 x i32> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulac24(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulac32x16_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulac32x16_h(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulac32x16_h +// CHECK: %[[LD_OPND_AE_SEM_MUL_X4_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulac32x16.h(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X4_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulac32x16_h(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulac32x16_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulac32x16_l(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulac32x16_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X4_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulac32x16.l(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X4_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulac32x16_l(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulaf16ss_00.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_00(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_00 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.00(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_00(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf16ss_00_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_00_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_00_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.00.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_00_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf16ss_10.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_10(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_10 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.10(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_10(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16ss_11.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_11(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_11 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.11(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_11(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16ss_20.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_20(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_20 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.20(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_20(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16ss_21.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_21(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_21 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.21(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_21(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16ss_22.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_22(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_22 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.22(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_22(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16ss_30.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_30(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_30 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.30(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_30(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16ss_31.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_31(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_31 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.31(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_31(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16ss_32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_32(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_32 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.32(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_32(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16ss_33.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16ss_33(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulaf16ss_33 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulaf16ss.33(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf16ss_33(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulaf16x4ss.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf16x4ss(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) { +// CHECK-LABEL: test_ae_mulaf16x4ss +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulaf16x4ss(<2 x i32> %[[LD_AE_MUL_Q1]], <2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <2 x i32> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulaf16x4ss(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0); +} + +//--- ae_mulaf32r_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32r_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32r_hh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32r.hh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32r_hh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32r_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32r_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32r_lh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32r.lh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32r_lh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32r_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32r_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32r_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32r.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32r_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32r_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32r_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32r_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32r.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32r_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32s_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32s_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32s_hh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32s.hh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32s_hh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32s_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32s_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32s_lh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32s.lh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32s_lh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32s_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32s_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32s_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32s.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32s_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32s_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32s_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32s_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32s.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32s_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32x16_h0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_h0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_h0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_h0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32x16_h0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_h0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_h0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_h0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32x16_h1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_h1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_h1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_h1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32x16_h1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_h1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_h1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_h1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32x16_h2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_h2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_h2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_h2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32x16_h2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_h2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_h2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_h2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32x16_h3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_h3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_h3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_h3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32x16_h3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_h3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_h3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.h3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_h3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32x16_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32x16_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32x16_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_l1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_l1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32x16_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_l1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_l1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32x16_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32x16_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf32x16_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_l3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_l3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf32x16_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf32x16_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf32x16_l3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf32x16.l3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf32x16_l3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf48q32sp16s_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf48q32sp16s_l(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf48q32sp16s_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16s.l(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf48q32sp16s_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf48q32sp16s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf48q32sp16s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf48q32sp16s_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16s.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf48q32sp16s_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaf48q32sp16u_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf48q32sp16u_l(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulaf48q32sp16u_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16u.l(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf48q32sp16u_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaf48q32sp16u_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaf48q32sp16u_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaf48q32sp16u_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaf48q32sp16u.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaf48q32sp16u_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulafc24ra.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafc24ra(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int32x2 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulafc24ra +// CHECK: %[[LD_OPND_AE_SEM_MUL_X4_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafc24ra(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X4_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafc24ra(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulafc32x16ras_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafc32x16ras_h(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulafc32x16ras_h +// CHECK: %[[LD_OPND_AE_SEM_MUL_X4_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafc32x16ras.h(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X4_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafc32x16ras_h(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulafc32x16ras_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafc32x16ras_l(ae_int32x2* opnd_ae_sem_mul_x4_q0,ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulafc32x16ras_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X4_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafc32x16ras.l(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X4_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafc32x16ras_l(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulafd24x2_fir_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafd24x2_fir_h(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int32x2 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulafd24x2_fir_h +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd24x2.fir.h(<1 x i64> %[[LD_AE_MUL_Q0]], <1 x i64> %[[LD_AE_MUL_Q1]], <2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulafd24x2_fir_h(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulafd24x2_fir_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafd24x2_fir_l(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int32x2 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulafd24x2_fir_l +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd24x2.fir.l(<1 x i64> %[[LD_AE_MUL_Q0]], <1 x i64> %[[LD_AE_MUL_Q1]], <2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulafd24x2_fir_l(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulafd32x16x2_fir_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafd32x16x2_fir_hh(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulafd32x16x2_fir_hh +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.hh(<1 x i64> %[[LD_AE_MUL_Q0]], <1 x i64> %[[LD_AE_MUL_Q1]], <2 x i32> {{.*}}, <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulafd32x16x2_fir_hh(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulafd32x16x2_fir_hl.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafd32x16x2_fir_hl(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulafd32x16x2_fir_hl +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.hl(<1 x i64> %[[LD_AE_MUL_Q0]], <1 x i64> %[[LD_AE_MUL_Q1]], <2 x i32> {{.*}}, <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulafd32x16x2_fir_hl(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulafd32x16x2_fir_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafd32x16x2_fir_lh(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulafd32x16x2_fir_lh +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.lh(<1 x i64> %[[LD_AE_MUL_Q0]], <1 x i64> %[[LD_AE_MUL_Q1]], <2 x i32> {{.*}}, <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulafd32x16x2_fir_lh(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulafd32x16x2_fir_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafd32x16x2_fir_ll(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulafd32x16x2_fir_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulafd32x16x2.fir.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <1 x i64> %[[LD_AE_MUL_Q1]], <2 x i32> {{.*}}, <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulafd32x16x2_fir_ll(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulafp24x2r.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp24x2r(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulafp24x2r +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp24x2r(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp24x2r(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulafp24x2r_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp24x2r_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulafp24x2r_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp24x2r.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp24x2r_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulafp24x2ra.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp24x2ra(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulafp24x2ra +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp24x2ra(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp24x2ra(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulafp24x2ra_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp24x2ra_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulafp24x2ra_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp24x2ra.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp24x2ra_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulafp32x16x2ras_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x16x2ras_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulafp32x16x2ras_h +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.h(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x16x2ras_h(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulafp32x16x2ras_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x16x2ras_h_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulafp32x16x2ras_h_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.h.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x16x2ras_h_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulafp32x16x2ras_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x16x2ras_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulafp32x16x2ras_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.l(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x16x2ras_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulafp32x16x2ras_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x16x2ras_l_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulafp32x16x2ras_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2ras.l.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x16x2ras_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulafp32x16x2rs_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x16x2rs_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulafp32x16x2rs_h +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.h(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x16x2rs_h(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulafp32x16x2rs_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x16x2rs_h_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulafp32x16x2rs_h_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.h.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x16x2rs_h_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulafp32x16x2rs_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x16x2rs_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulafp32x16x2rs_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.l(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x16x2rs_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulafp32x16x2rs_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x16x2rs_l_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulafp32x16x2rs_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x16x2rs.l.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x16x2rs_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulafp32x2ras.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x2ras(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulafp32x2ras +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x2ras(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x2ras(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulafp32x2rs.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafp32x2rs(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulafp32x2rs +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulafp32x2rs(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafp32x2rs(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulafq32sp24s_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafq32sp24s_h_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulafq32sp24s_h_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulafq32sp24s.h.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafq32sp24s_h_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulafq32sp24s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulafq32sp24s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulafq32sp24s_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulafq32sp24s.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulafq32sp24s_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulap24x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulap24x2(ae_int32x2* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulap24x2 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulap24x2(<2 x i32> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulap24x2(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulap24x2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulap24x2_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulap24x2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulap24x2.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulap24x2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulap32x16x2_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulap32x16x2_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulap32x16x2_h +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulap32x16x2.h(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulap32x16x2_h(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulap32x16x2_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulap32x16x2_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulap32x16x2_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulap32x16x2.l(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulap32x16x2_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulap32x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulap32x2(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulap32x2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulap32x2(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulap32x2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulaq32sp16s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaq32sp16s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaq32sp16s_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaq32sp16s.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaq32sp16s_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulaq32sp16u_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulaq32sp16u_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulaq32sp16u_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulaq32sp16u.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulaq32sp16u_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mularfq32sp24s_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mularfq32sp24s_h_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mularfq32sp24s_h_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mularfq32sp24s.h.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mularfq32sp24s_h_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mularfq32sp24s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mularfq32sp24s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mularfq32sp24s_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mularfq32sp24s.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mularfq32sp24s_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulas32f48p16s_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulas32f48p16s_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulas32f48p16s_hh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.hh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulas32f48p16s_hh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulas32f48p16s_hh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulas32f48p16s_hh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulas32f48p16s_hh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.hh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulas32f48p16s_hh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulas32f48p16s_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulas32f48p16s_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulas32f48p16s_lh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.lh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulas32f48p16s_lh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulas32f48p16s_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulas32f48p16s_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulas32f48p16s_lh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.lh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulas32f48p16s_lh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulas32f48p16s_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulas32f48p16s_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulas32f48p16s_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulas32f48p16s_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulas32f48p16s_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulas32f48p16s_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulas32f48p16s_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulas32f48p16s.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulas32f48p16s_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulasd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulasd24_hh_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasd24.hh.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasd24_hh_ll(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulasd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulasd24_hh_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasd24.hh.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasd24_hh_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulasd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulasd24_hl_lh +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasd24.hl.lh(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasd24_hl_lh(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulasd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulasd24_hl_lh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasd24.hl.lh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasd24_hl_lh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulasd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulasd32x16_h1_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasd32x16.h1.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulasd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulasd32x16_h1_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasd32x16.h1.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasd32x16_h1_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulasd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulasd32x16_h3_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasd32x16.h3.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulasd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulasd32x16_h3_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasd32x16.h3.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasd32x16_h3_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulasfd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasfd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulasfd24_hh_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasfd24.hh.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasfd24_hh_ll(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulasfd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasfd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulasfd24_hh_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasfd24.hh.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasfd24_hh_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulasfd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasfd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulasfd24_hl_lh +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasfd24.hl.lh(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasfd24_hl_lh(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulasfd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasfd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulasfd24_hl_lh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasfd24.hl.lh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasfd24_hl_lh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulasfd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasfd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulasfd32x16_h1_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h1.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasfd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulasfd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasfd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulasfd32x16_h1_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h1.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasfd32x16_h1_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulasfd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasfd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulasfd32x16_h3_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h3.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasfd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulasfd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulasfd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulasfd32x16_h3_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulasfd32x16.h3.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulasfd32x16_h3_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulc24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulc24(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulc24 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulc24(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulc24(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulc32x16_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulc32x16_h(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulc32x16_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulc32x16.h(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulc32x16_h(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulc32x16_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulc32x16_l(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulc32x16_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulc32x16.l(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulc32x16_l(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulf16ss_00.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_00(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf16ss_00 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.00(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_00(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf16ss_00_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_00_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf16ss_00_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.00.s2(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_00_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf16ss_10.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_10(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_10 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.10(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_10(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16ss_11.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_11(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_11 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.11(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_11(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16ss_20.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_20(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_20 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.20(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_20(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16ss_21.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_21(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_21 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.21(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_21(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16ss_22.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_22(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_22 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.22(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_22(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16ss_30.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_30(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_30 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.30(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_30(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16ss_31.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_31(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_31 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.31(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_31(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16ss_32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_32(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.32(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_32(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16ss_33.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulf16ss_33(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulf16ss_33 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulf16ss.33(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulf16ss_33(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulf16x4ss.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulf16x4ss(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) { +// CHECK-LABEL: test_ae_mulf16x4ss +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulf16x4ss(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <2 x i32> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulf16x4ss(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0); +} + +//--- ae_mulf32r_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32r_hh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32r_hh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32r.hh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32r_hh(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32r_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32r_lh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32r_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32r.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32r_lh(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32r_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32r_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32r_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32r.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32r_ll(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32r_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32r_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32r_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32r.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32r_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32s_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32s_hh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32s_hh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32s.hh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32s_hh(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32s_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32s_lh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32s_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32s.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32s_lh(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32s_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32s_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32s_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32s.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32s_ll(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32s_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32s_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32s_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32s.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32s_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32x16_h0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_h0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32x16_h0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.h0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_h0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32x16_h0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_h0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32x16_h0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.h0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_h0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32x16_h1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_h1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32x16_h1 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.h1(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_h1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32x16_h1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_h1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32x16_h1_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.h1.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_h1_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32x16_h2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_h2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32x16_h2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.h2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_h2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32x16_h2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_h2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32x16_h2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.h2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_h2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32x16_h3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_h3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32x16_h3 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.h3(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_h3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32x16_h3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_h3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32x16_h3_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.h3.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_h3_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32x16_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32x16_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32x16_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32x16_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32x16_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_l1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32x16_l1 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.l1(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_l1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32x16_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_l1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32x16_l1_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.l1.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_l1_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32x16_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32x16_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32x16_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32x16_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf32x16_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_l3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf32x16_l3 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.l3(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_l3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf32x16_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf32x16_l3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf32x16_l3_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf32x16.l3.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf32x16_l3_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf48q32sp16s_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf48q32sp16s_l(ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf48q32sp16s_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf48q32sp16s.l(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf48q32sp16s_l(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf48q32sp16s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf48q32sp16s_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf48q32sp16s_l_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf48q32sp16s.l.s2(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf48q32sp16s_l_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulf48q32sp16u_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf48q32sp16u_l(ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulf48q32sp16u_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf48q32sp16u.l(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf48q32sp16u_l(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulf48q32sp16u_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulf48q32sp16u_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulf48q32sp16u_l_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulf48q32sp16u.l.s2(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulf48q32sp16u_l_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulfc24ra.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfc24ra(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int32x2 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulfc24ra +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfc24ra(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfc24ra(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulfc32x16ras_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfc32x16ras_h(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulfc32x16ras_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfc32x16ras.h(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfc32x16ras_h(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulfc32x16ras_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfc32x16ras_l(ae_int32x2 opnd_ae_sem_mul_x4_d0,ae_int16x4 opnd_ae_sem_mul_x4_d1) { +// CHECK-LABEL: test_ae_mulfc32x16ras_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfc32x16ras.l(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfc32x16ras_l(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1); +} + +//--- ae_mulfd24x2_fir_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulfd24x2_fir_h(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int32x2 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulfd24x2_fir_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd24x2.fir.h(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulfd24x2_fir_h(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulfd24x2_fir_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulfd24x2_fir_l(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int32x2 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulfd24x2_fir_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd24x2.fir.l(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulfd24x2_fir_l(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulfd32x16x2_fir_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulfd32x16x2_fir_hh(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulfd32x16x2_fir_hh +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.hh(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulfd32x16x2_fir_hh(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulfd32x16x2_fir_hl.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulfd32x16x2_fir_hl(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulfd32x16x2_fir_hl +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.hl(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulfd32x16x2_fir_hl(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulfd32x16x2_fir_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulfd32x16x2_fir_lh(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulfd32x16x2_fir_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulfd32x16x2_fir_lh(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulfd32x16x2_fir_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulfd32x16x2_fir_ll(ae_int64* ae_mul_q0,ae_int64* ae_mul_q1,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1,ae_int16x4 ae_mul_d2) { +// CHECK-LABEL: test_ae_mulfd32x16x2_fir_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i64>, <1 x i64> } @llvm.xtensa.ae.mulfd32x16x2.fir.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i64>, <1 x i64> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulfd32x16x2_fir_ll(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, ae_mul_d2); +} + +//--- ae_mulfp16x4ras.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_mulfp16x4ras(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulfp16x4ras +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.mulfp16x4ras(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_mulfp16x4ras(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulfp16x4s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_mulfp16x4s(ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulfp16x4s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.mulfp16x4s(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_mulfp16x4s(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulfp24x2r.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp24x2r(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulfp24x2r +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp24x2r(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp24x2r(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulfp24x2r_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp24x2r_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulfp24x2r_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp24x2r.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp24x2r_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulfp24x2ra.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp24x2ra(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulfp24x2ra +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp24x2ra(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp24x2ra(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulfp24x2ra_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp24x2ra_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulfp24x2ra_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp24x2ra.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp24x2ra_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulfp32x16x2ras_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x16x2ras_h(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulfp32x16x2ras_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.h(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x16x2ras_h(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulfp32x16x2ras_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x16x2ras_h_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulfp32x16x2ras_h_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.h.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x16x2ras_h_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulfp32x16x2ras_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x16x2ras_l(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulfp32x16x2ras_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.l(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x16x2ras_l(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulfp32x16x2ras_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x16x2ras_l_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulfp32x16x2ras_l_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2ras.l.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x16x2ras_l_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulfp32x16x2rs_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x16x2rs_h(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulfp32x16x2rs_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.h(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x16x2rs_h(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulfp32x16x2rs_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x16x2rs_h_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulfp32x16x2rs_h_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.h.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x16x2rs_h_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulfp32x16x2rs_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x16x2rs_l(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulfp32x16x2rs_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.l(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x16x2rs_l(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulfp32x16x2rs_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x16x2rs_l_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulfp32x16x2rs_l_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x16x2rs.l.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x16x2rs_l_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulfp32x2ras.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x2ras(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulfp32x2ras +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x2ras(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x2ras(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulfp32x2rs.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulfp32x2rs(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulfp32x2rs +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulfp32x2rs(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulfp32x2rs(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulfq32sp24s_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulfq32sp24s_h_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulfq32sp24s_h_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulfq32sp24s.h.s2(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulfq32sp24s_h_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulfq32sp24s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulfq32sp24s_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulfq32sp24s_l_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulfq32sp24s.l.s2(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulfq32sp24s_l_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulp24x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulp24x2(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulp24x2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulp24x2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulp24x2(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulp24x2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulp24x2_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulp24x2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulp24x2.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulp24x2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulp32x16x2_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulp32x16x2_h(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulp32x16x2_h +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulp32x16x2.h(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulp32x16x2_h(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulp32x16x2_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulp32x16x2_l(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulp32x16x2_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulp32x16x2.l(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulp32x16x2_l(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulp32x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulp32x2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulp32x2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulp32x2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulp32x2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulq32sp16s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulq32sp16s_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulq32sp16s_l_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulq32sp16s.l.s2(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulq32sp16s_l_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulq32sp16u_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulq32sp16u_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulq32sp16u_l_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulq32sp16u.l.s2(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulq32sp16u_l_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulrfq32sp24s_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulrfq32sp24s_h_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulrfq32sp24s_h_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulrfq32sp24s.h.s2(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulrfq32sp24s_h_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulrfq32sp24s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulrfq32sp24s_l_s2(ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulrfq32sp24s_l_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulrfq32sp24s.l.s2(<1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulrfq32sp24s_l_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls16x4.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls16x4(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) { +// CHECK-LABEL: test_ae_muls16x4 +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.muls16x4(<2 x i32> %[[LD_AE_MUL_Q1]], <2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <2 x i32> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_muls16x4(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0); +} + +//--- ae_muls32_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32_hh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32.hh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32_hh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32_lh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32.lh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32_lh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32f48p16s_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_muls32f48p16s_hh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32f48p16s_hh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.hh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_muls32f48p16s_hh(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32f48p16s_hh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_muls32f48p16s_hh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32f48p16s_hh_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.hh.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_muls32f48p16s_hh_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32f48p16s_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_muls32f48p16s_lh(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32f48p16s_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_muls32f48p16s_lh(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32f48p16s_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_muls32f48p16s_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32f48p16s_lh_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.lh.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_muls32f48p16s_lh_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32f48p16s_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_muls32f48p16s_ll(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32f48p16s_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_muls32f48p16s_ll(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32f48p16s_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_muls32f48p16s_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32f48p16s_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32f48p16s.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_muls32f48p16s_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32u_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32u_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32u_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32u.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32u_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_h0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_h0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32x16_h0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.h0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_h0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_h0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_h0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32x16_h0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.h0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_h0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32x16_h1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_h1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32x16_h1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.h1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_h1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_h1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_h1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32x16_h1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.h1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_h1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32x16_h2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_h2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32x16_h2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.h2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_h2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_h2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_h2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32x16_h2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.h2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_h2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32x16_h3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_h3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32x16_h3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.h3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_h3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_h3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_h3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32x16_h3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.h3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_h3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32x16_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32x16_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32x16_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32x16_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32x16_l1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.l1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_l1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32x16_l1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.l1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_l1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32x16_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32x16_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32x16_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_muls32x16_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_muls32x16_l3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.l3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_l3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_muls32x16_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_muls32x16_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_muls32x16_l3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.muls32x16.l3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_muls32x16_l3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsad24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsad24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsad24_hh_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsad24.hh.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsad24_hh_ll(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsad24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsad24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsad24_hh_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsad24.hh.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsad24_hh_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsad32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsad32x16_h1_l0(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsad32x16_h1_l0 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsad32x16.h1.l0(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsad32x16_h1_l0(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsad32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsad32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsad32x16_h1_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsad32x16.h1.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsad32x16_h1_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsad32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsad32x16_h3_l2(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsad32x16_h3_l2 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsad32x16.h3.l2(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsad32x16_h3_l2(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsad32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsad32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsad32x16_h3_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsad32x16.h3.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsad32x16_h3_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsafd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsafd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsafd24_hh_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsafd24.hh.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsafd24_hh_ll(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsafd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsafd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsafd24_hh_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsafd24.hh.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsafd24_hh_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsafd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsafd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsafd32x16_h1_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h1.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsafd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsafd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsafd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsafd32x16_h1_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h1.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsafd32x16_h1_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsafd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsafd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsafd32x16_h3_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h3.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsafd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsafd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsafd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsafd32x16_h3_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsafd32x16.h3.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsafd32x16_h3_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf16ss_00.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_00(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_00 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.00(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_00(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf16ss_00_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_00_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_00_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.00.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_00_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf16ss_10.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_10(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_10 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.10(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_10(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16ss_11.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_11(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_11 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.11(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_11(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16ss_20.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_20(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_20 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.20(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_20(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16ss_21.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_21(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_21 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.21(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_21(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16ss_22.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_22(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_22 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.22(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_22(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16ss_30.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_30(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_30 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.30(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_30(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16ss_31.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_31(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_31 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.31(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_31(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16ss_32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_32(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_32 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.32(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_32(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16ss_33.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16ss_33(ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsf16ss_33 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsf16ss.33(<2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf16ss_33(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsf16x4ss.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf16x4ss(ae_int32x2* ae_mul_q1,ae_int32x2* ae_mul_q0,ae_int16x4 ae_mul_d1,ae_int16x4 ae_mul_d0) { +// CHECK-LABEL: test_ae_mulsf16x4ss +// CHECK: %[[LD_AE_MUL_Q1:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <2 x i32>, <2 x i32> } @llvm.xtensa.ae.mulsf16x4ss(<2 x i32> %[[LD_AE_MUL_Q1]], <2 x i32> %[[LD_AE_MUL_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <2 x i32>, <2 x i32> } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_mulsf16x4ss(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0); +} + +//--- ae_mulsf32r_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32r_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32r_hh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32r.hh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32r_hh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32r_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32r_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32r_lh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32r.lh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32r_lh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32r_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32r_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32r_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32r.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32r_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32r_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32r_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32r_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32r.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32r_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf32s_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32s_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32s_hh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32s.hh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32s_hh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32s_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32s_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32s_lh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32s.lh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32s_lh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32s_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32s_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32s_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32s.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32s_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_h0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_h0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_h0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_h0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_h0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_h0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_h0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_h0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf32x16_h1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_h1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_h1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_h1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_h1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_h1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_h1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_h1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf32x16_h2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_h2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_h2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_h2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_h2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_h2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_h2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_h2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf32x16_h3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_h3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_h3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_h3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_h3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_h3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_h3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.h3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_h3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf32x16_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf32x16_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_l1(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_l1 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l1(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_l1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_l1_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_l1_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l1.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_l1_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf32x16_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf32x16_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_l3(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_l3 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l3(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_l3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf32x16_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf32x16_l3_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf32x16_l3_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf32x16.l3.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf32x16_l3_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf48q32sp16s_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf48q32sp16s_l(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf48q32sp16s_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16s.l(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf48q32sp16s_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf48q32sp16s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf48q32sp16s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf48q32sp16s_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16s.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf48q32sp16s_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsf48q32sp16u_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf48q32sp16u_l(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int64 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsf48q32sp16u_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16u.l(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf48q32sp16u_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsf48q32sp16u_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsf48q32sp16u_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsf48q32sp16u_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsf48q32sp16u.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsf48q32sp16u_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsfp24x2r.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp24x2r(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsfp24x2r +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp24x2r(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp24x2r(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsfp24x2r_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp24x2r_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsfp24x2r_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp24x2r.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp24x2r_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsfp24x2ra.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp24x2ra(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsfp24x2ra +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp24x2ra(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp24x2ra(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsfp24x2ra_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp24x2ra_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsfp24x2ra_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp24x2ra.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp24x2ra_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsfp32x16x2ras_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x16x2ras_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsfp32x16x2ras_h +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.h(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x16x2ras_h(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsfp32x16x2ras_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x16x2ras_h_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsfp32x16x2ras_h_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.h.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x16x2ras_h_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsfp32x16x2ras_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x16x2ras_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsfp32x16x2ras_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.l(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x16x2ras_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsfp32x16x2ras_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x16x2ras_l_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsfp32x16x2ras_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2ras.l.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x16x2ras_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsfp32x16x2rs_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x16x2rs_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsfp32x16x2rs_h +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.h(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x16x2rs_h(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsfp32x16x2rs_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x16x2rs_h_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsfp32x16x2rs_h_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.h.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x16x2rs_h_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsfp32x16x2rs_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x16x2rs_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsfp32x16x2rs_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.l(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x16x2rs_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsfp32x16x2rs_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x16x2rs_l_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsfp32x16x2rs_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x16x2rs.l.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x16x2rs_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsfp32x2ras.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x2ras(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsfp32x2ras +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x2ras(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x2ras(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsfp32x2rs.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfp32x2rs(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsfp32x2rs +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsfp32x2rs(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfp32x2rs(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsfq32sp24s_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfq32sp24s_h_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsfq32sp24s_h_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsfq32sp24s.h.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfq32sp24s_h_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsfq32sp24s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsfq32sp24s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsfq32sp24s_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsfq32sp24s.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsfq32sp24s_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsp24x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsp24x2(ae_int32x2* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulsp24x2 +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsp24x2(<2 x i32> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsp24x2(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulsp24x2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsp24x2_s2(ae_int32x2* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsp24x2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsp24x2.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsp24x2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsp32x16x2_h.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsp32x16x2_h(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsp32x16x2_h +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsp32x16x2.h(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsp32x16x2_h(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsp32x16x2_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsp32x16x2_l(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsp32x16x2_l +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsp32x16x2.l(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsp32x16x2_l(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsp32x2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsp32x2(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulsp32x2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulsp32x2(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsp32x2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulsq32sp16s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsq32sp16s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsq32sp16s_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsq32sp16s.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsq32sp16s_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsq32sp16u_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsq32sp16u_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsq32sp16u_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsq32sp16u.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsq32sp16u_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsrfq32sp24s_h_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsrfq32sp24s_h_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsrfq32sp24s_h_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsrfq32sp24s.h.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsrfq32sp24s_h_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulsrfq32sp24s_l_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulsrfq32sp24s_l_s2(ae_int64* ae_mul_S2_q0,ae_int64 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulsrfq32sp24s_l_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulsrfq32sp24s.l.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <1 x i64> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulsrfq32sp24s_l_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulss32f48p16s_hh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulss32f48p16s_hh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulss32f48p16s_hh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.hh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulss32f48p16s_hh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulss32f48p16s_hh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulss32f48p16s_hh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulss32f48p16s_hh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.hh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulss32f48p16s_hh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulss32f48p16s_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulss32f48p16s_lh(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulss32f48p16s_lh +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.lh(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulss32f48p16s_lh(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulss32f48p16s_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulss32f48p16s_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulss32f48p16s_lh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.lh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulss32f48p16s_lh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulss32f48p16s_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulss32f48p16s_ll(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulss32f48p16s_ll +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.ll(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulss32f48p16s_ll(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulss32f48p16s_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulss32f48p16s_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulss32f48p16s_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulss32f48p16s.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulss32f48p16s_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulssd24_hh_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssd24.hh.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssd24_hh_ll(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulssd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssd24_hh_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssd24.hh.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssd24_hh_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulssd24_hl_lh +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssd24.hl.lh(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssd24_hl_lh(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulssd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssd24_hl_lh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssd24.hl.lh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssd24_hl_lh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulssd32x16_h1_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssd32x16.h1.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulssd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssd32x16_h1_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssd32x16.h1.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssd32x16_h1_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulssd32x16_h3_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssd32x16.h3.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulssd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssd32x16_h3_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssd32x16.h3.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssd32x16_h3_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssfd16ss_11_00.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd16ss_11_00(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulssfd16ss_11_00 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.11.00(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd16ss_11_00(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulssfd16ss_11_00_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd16ss_11_00_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssfd16ss_11_00_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.11.00.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd16ss_11_00_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssfd16ss_13_02.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd16ss_13_02(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulssfd16ss_13_02 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.13.02(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd16ss_13_02(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulssfd16ss_13_02_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd16ss_13_02_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssfd16ss_13_02_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.13.02.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd16ss_13_02_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssfd16ss_33_22.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd16ss_33_22(ae_int32x2* opnd_ae_sem_mul_x2_S1_q0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulssfd16ss_33_22 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.33.22(<2 x i32> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd16ss_33_22(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulssfd16ss_33_22_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd16ss_33_22_s2(ae_int32x2* ae_mul_S2_q0,ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssfd16ss_33_22_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulssfd16ss.33.22.s2(<2 x i32> %[[LD_AE_MUL_S2_Q0]], <4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd16ss_33_22_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssfd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd24_hh_ll(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulssfd24_hh_ll +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssfd24.hh.ll(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd24_hh_ll(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulssfd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd24_hh_ll_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssfd24_hh_ll_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssfd24.hh.ll.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd24_hh_ll_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssfd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd24_hl_lh(ae_int64* ae_mul_q0,ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulssfd24_hl_lh +// CHECK: %[[LD_AE_MUL_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssfd24.hl.lh(<1 x i64> %[[LD_AE_MUL_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd24_hl_lh(ae_mul_q0, ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulssfd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd24_hl_lh_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssfd24_hl_lh_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssfd24.hl.lh.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd24_hl_lh_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssfd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd32x16_h1_l0(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulssfd32x16_h1_l0 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h1.l0(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulssfd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd32x16_h1_l0_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssfd32x16_h1_l0_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h1.l0.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd32x16_h1_l0_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulssfd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd32x16_h3_l2(ae_int64* opnd_ae_sem_mul_x2_S1_q0,ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulssfd32x16_h3_l2 +// CHECK: %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h3.l2(<1 x i64> %[[LD_OPND_AE_SEM_MUL_X2_S1_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulssfd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_mulssfd32x16_h3_l2_s2(ae_int64* ae_mul_S2_q0,ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulssfd32x16_h3_l2_s2 +// CHECK: %[[LD_AE_MUL_S2_Q0:.*]] = load <1 x i64>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulssfd32x16.h3.l2.s2(<1 x i64> %[[LD_AE_MUL_S2_Q0]], <2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_mulssfd32x16_h3_l2_s2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaad24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzaad24_hh_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad24.hh.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad24_hh_ll(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzaad24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaad24_hh_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad24.hh.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad24_hh_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaad24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzaad24_hl_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad24.hl.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad24_hl_lh(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzaad24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaad24_hl_lh_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad24.hl.lh.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad24_hl_lh_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaad32x16_h0_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad32x16_h0_l1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaad32x16_h0_l1 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h0.l1(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad32x16_h0_l1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaad32x16_h0_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad32x16_h0_l1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaad32x16_h0_l1_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h0.l1.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad32x16_h0_l1_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaad32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaad32x16_h1_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h1.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad32x16_h1_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaad32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaad32x16_h1_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h1.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad32x16_h1_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaad32x16_h2_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad32x16_h2_l3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaad32x16_h2_l3 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h2.l3(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad32x16_h2_l3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaad32x16_h2_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad32x16_h2_l3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaad32x16_h2_l3_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h2.l3.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad32x16_h2_l3_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaad32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaad32x16_h3_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h3.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad32x16_h3_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaad32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaad32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaad32x16_h3_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaad32x16.h3.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaad32x16_h3_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd16ss_11_00.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzaafd16ss_11_00(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaafd16ss_11_00 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.11.00(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzaafd16ss_11_00(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaafd16ss_11_00_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzaafd16ss_11_00_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd16ss_11_00_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.11.00.s2(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzaafd16ss_11_00_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd16ss_13_02.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzaafd16ss_13_02(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaafd16ss_13_02 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.13.02(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzaafd16ss_13_02(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaafd16ss_13_02_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzaafd16ss_13_02_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd16ss_13_02_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.13.02.s2(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzaafd16ss_13_02_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd16ss_33_22.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzaafd16ss_33_22(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaafd16ss_33_22 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.33.22(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzaafd16ss_33_22(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaafd16ss_33_22_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzaafd16ss_33_22_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd16ss_33_22_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzaafd16ss.33.22.s2(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzaafd16ss_33_22_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzaafd24_hh_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd24.hh.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd24_hh_ll(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzaafd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd24_hh_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd24.hh.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd24_hh_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzaafd24_hl_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd24.hl.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd24_hl_lh(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzaafd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd24_hl_lh_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd24.hl.lh.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd24_hl_lh_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd32x16_h0_l1.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd32x16_h0_l1(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaafd32x16_h0_l1 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h0.l1(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd32x16_h0_l1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaafd32x16_h0_l1_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd32x16_h0_l1_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd32x16_h0_l1_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h0.l1.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd32x16_h0_l1_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaafd32x16_h1_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h1.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaafd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd32x16_h1_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h1.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd32x16_h1_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd32x16_h2_l3.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd32x16_h2_l3(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaafd32x16_h2_l3 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h2.l3(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd32x16_h2_l3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaafd32x16_h2_l3_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd32x16_h2_l3_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd32x16_h2_l3_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h2.l3.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd32x16_h2_l3_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzaafd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzaafd32x16_h3_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h3.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzaafd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzaafd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzaafd32x16_h3_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzaafd32x16.h3.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzaafd32x16_h3_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzasd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzasd24_hh_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasd24.hh.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasd24_hh_ll(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzasd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzasd24_hh_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasd24.hh.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasd24_hh_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzasd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzasd24_hl_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasd24.hl.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasd24_hl_lh(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzasd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzasd24_hl_lh_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasd24.hl.lh.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasd24_hl_lh_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzasd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzasd32x16_h1_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h1.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzasd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzasd32x16_h1_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h1.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasd32x16_h1_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzasd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzasd32x16_h3_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h3.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzasd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzasd32x16_h3_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasd32x16.h3.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasd32x16_h3_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzasfd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasfd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzasfd24_hh_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasfd24.hh.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasfd24_hh_ll(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzasfd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasfd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzasfd24_hh_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasfd24.hh.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasfd24_hh_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzasfd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasfd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzasfd24_hl_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasfd24.hl.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasfd24_hl_lh(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzasfd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasfd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzasfd24_hl_lh_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasfd24.hl.lh.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasfd24_hl_lh_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzasfd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasfd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzasfd32x16_h1_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h1.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasfd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzasfd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasfd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzasfd32x16_h1_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h1.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasfd32x16_h1_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzasfd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasfd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzasfd32x16_h3_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h3.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasfd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzasfd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzasfd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzasfd32x16_h3_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzasfd32x16.h3.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzasfd32x16_h3_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzsad24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsad24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzsad24_hh_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsad24.hh.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsad24_hh_ll(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzsad24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsad24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzsad24_hh_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsad24.hh.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsad24_hh_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzsad32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsad32x16_h1_l0(ae_int32x2 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzsad32x16_h1_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h1.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsad32x16_h1_l0(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzsad32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsad32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzsad32x16_h1_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h1.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsad32x16_h1_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzsad32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsad32x16_h3_l2(ae_int32x2 ae_mul_d0,ae_int16x4 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzsad32x16_h3_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h3.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsad32x16_h3_l2(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzsad32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsad32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzsad32x16_h3_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsad32x16.h3.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsad32x16_h3_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzsafd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsafd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzsafd24_hh_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsafd24.hh.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsafd24_hh_ll(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzsafd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsafd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzsafd24_hh_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsafd24.hh.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsafd24_hh_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzsafd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsafd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzsafd32x16_h1_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h1.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsafd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzsafd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsafd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzsafd32x16_h1_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h1.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsafd32x16_h1_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzsafd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsafd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzsafd32x16_h3_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h3.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsafd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzsafd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzsafd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzsafd32x16_h3_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzsafd32x16.h3.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzsafd32x16_h3_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzssd24_hh_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssd24.hh.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssd24_hh_ll(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzssd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssd24_hh_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssd24.hh.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssd24_hh_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzssd24_hl_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssd24.hl.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssd24_hl_lh(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzssd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssd24_hl_lh_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssd24.hl.lh.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssd24_hl_lh_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzssd32x16_h1_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h1.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzssd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssd32x16_h1_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h1.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssd32x16_h1_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzssd32x16_h3_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h3.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzssd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssd32x16_h3_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssd32x16.h3.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssd32x16_h3_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssfd16ss_11_00.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzssfd16ss_11_00(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzssfd16ss_11_00 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.11.00(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzssfd16ss_11_00(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzssfd16ss_11_00_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzssfd16ss_11_00_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssfd16ss_11_00_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.11.00.s2(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzssfd16ss_11_00_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssfd16ss_13_02.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzssfd16ss_13_02(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzssfd16ss_13_02 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.13.02(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzssfd16ss_13_02(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzssfd16ss_13_02_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzssfd16ss_13_02_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssfd16ss_13_02_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.13.02.s2(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzssfd16ss_13_02_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssfd16ss_33_22.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzssfd16ss_33_22(ae_int16x4 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzssfd16ss_33_22 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.33.22(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzssfd16ss_33_22(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzssfd16ss_33_22_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_mulzssfd16ss_33_22_s2(ae_int16x4 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssfd16ss_33_22_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.mulzssfd16ss.33.22.s2(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_mulzssfd16ss_33_22_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssfd24_hh_ll.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssfd24_hh_ll(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzssfd24_hh_ll +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssfd24.hh.ll(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssfd24_hh_ll(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzssfd24_hh_ll_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssfd24_hh_ll_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssfd24_hh_ll_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssfd24.hh.ll.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssfd24_hh_ll_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssfd24_hl_lh.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssfd24_hl_lh(ae_int32x2 ae_mul_d0,ae_int32x2 ae_mul_d1) { +// CHECK-LABEL: test_ae_mulzssfd24_hl_lh +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssfd24.hl.lh(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssfd24_hl_lh(ae_mul_d0, ae_mul_d1); +} + +//--- ae_mulzssfd24_hl_lh_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssfd24_hl_lh_s2(ae_int32x2 ae_mul_S2_d0,ae_int32x2 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssfd24_hl_lh_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssfd24.hl.lh.s2(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssfd24_hl_lh_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssfd32x16_h1_l0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssfd32x16_h1_l0(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzssfd32x16_h1_l0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h1.l0(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssfd32x16_h1_l0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzssfd32x16_h1_l0_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssfd32x16_h1_l0_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssfd32x16_h1_l0_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h1.l0.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssfd32x16_h1_l0_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_mulzssfd32x16_h3_l2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssfd32x16_h3_l2(ae_int32x2 opnd_ae_sem_mul_x2_S1_d0,ae_int16x4 opnd_ae_sem_mul_x2_S1_d1) { +// CHECK-LABEL: test_ae_mulzssfd32x16_h3_l2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h3.l2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssfd32x16_h3_l2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1); +} + +//--- ae_mulzssfd32x16_h3_l2_s2.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_mulzssfd32x16_h3_l2_s2(ae_int32x2 ae_mul_S2_d0,ae_int16x4 ae_mul_S2_d1) { +// CHECK-LABEL: test_ae_mulzssfd32x16_h3_l2_s2 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.mulzssfd32x16.h3.l2.s2(<2 x i32> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_mulzssfd32x16_h3_l2_s2(ae_mul_S2_d0, ae_mul_S2_d1); +} + +//--- ae_nand.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_nand(ae_int64 ae_dr_to_dr_v0,ae_int64 ae_dr_to_dr_v1) { +// CHECK-LABEL: test_ae_nand +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.nand(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_nand(ae_dr_to_dr_v0, ae_dr_to_dr_v1); +} + +//--- ae_neg16s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_neg16s(ae_int16x4 ae_arth_v1) { +// CHECK-LABEL: test_ae_neg16s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.neg16s(<4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_neg16s(ae_arth_v1); +} + +//--- ae_neg24s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_neg24s(ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_neg24s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.neg24s(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_neg24s(ae_arth_v1); +} + +//--- ae_neg32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_neg32(ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_neg32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.neg32(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_neg32(ae_arth_v1); +} + +//--- ae_neg32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_neg32s(ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_neg32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.neg32s(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_neg32s(ae_arth_v1); +} + +//--- ae_neg64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_neg64(ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_neg64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.neg64(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_neg64(ae_arth_v1); +} + +//--- ae_neg64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_neg64s(ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_neg64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.neg64s(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_neg64s(ae_arth_v1); +} + +//--- ae_nsa64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_nsa64(ae_int64 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_nsa64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.nsa64(<1 x i64> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_nsa64(ae_dr_to_ar_v0); +} + +//--- ae_nsaz16_0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_nsaz16_0(ae_int16x4 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_nsaz16_0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.nsaz16.0(<4 x i16> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_nsaz16_0(ae_dr_to_ar_v0); +} + +//--- ae_nsaz32_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_nsaz32_l(ae_int32x2 ae_dr_to_ar_v0) { +// CHECK-LABEL: test_ae_nsaz32_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.nsaz32.l(<2 x i32> {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_nsaz32_l(ae_dr_to_ar_v0); +} + +//--- ae_or.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_or(ae_int64 ae_dr_to_dr_v0,ae_int64 ae_dr_to_dr_v1) { +// CHECK-LABEL: test_ae_or +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.or(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_or(ae_dr_to_dr_v0, ae_dr_to_dr_v1); +} + +//--- ae_pksr24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_pksr24(ae_int32x2* ae_pks_d,ae_int64 ae_pks_s,immediate ae_imm2) { +// CHECK-LABEL: test_ae_pksr24 +// CHECK: %[[LD_AE_PKS_D:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.pksr24(<2 x i32> %[[LD_AE_PKS_D]], <1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_pksr24(ae_pks_d, ae_pks_s, 0); +} + +//--- ae_pksr32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_pksr32(ae_int32x2* ae_pks_d,ae_int64 ae_pks_s,immediate ae_imm2) { +// CHECK-LABEL: test_ae_pksr32 +// CHECK: %[[LD_AE_PKS_D:.*]] = load <2 x i32>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.pksr32(<2 x i32> %[[LD_AE_PKS_D]], <1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_pksr32(ae_pks_d, ae_pks_s, 0); +} + +//--- ae_round16x4f32sasym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_round16x4f32sasym(ae_int32x2 ae_arth_v1,ae_int32x2 ae_arth_v0) { +// CHECK-LABEL: test_ae_round16x4f32sasym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.round16x4f32sasym(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_round16x4f32sasym(ae_arth_v1, ae_arth_v0); +} + +//--- ae_round16x4f32ssym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_round16x4f32ssym(ae_int32x2 ae_arth_v1,ae_int32x2 ae_arth_v0) { +// CHECK-LABEL: test_ae_round16x4f32ssym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.round16x4f32ssym(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_round16x4f32ssym(ae_arth_v1, ae_arth_v0); +} + +//--- ae_round24x2f48sasym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_round24x2f48sasym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_round24x2f48sasym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.round24x2f48sasym(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_round24x2f48sasym(ae_arth_v0, ae_arth_v1); +} + +//--- ae_round24x2f48ssym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_round24x2f48ssym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_round24x2f48ssym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.round24x2f48ssym(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_round24x2f48ssym(ae_arth_v0, ae_arth_v1); +} + +//--- ae_round32x2f48sasym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_round32x2f48sasym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_round32x2f48sasym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.round32x2f48sasym(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_round32x2f48sasym(ae_arth_v0, ae_arth_v1); +} + +//--- ae_round32x2f48ssym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_round32x2f48ssym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_round32x2f48ssym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.round32x2f48ssym(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_round32x2f48ssym(ae_arth_v0, ae_arth_v1); +} + +//--- ae_round32x2f64sasym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_round32x2f64sasym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_round32x2f64sasym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.round32x2f64sasym(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_round32x2f64sasym(ae_arth_v0, ae_arth_v1); +} + +//--- ae_round32x2f64ssym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_round32x2f64ssym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_round32x2f64ssym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.round32x2f64ssym(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_round32x2f64ssym(ae_arth_v0, ae_arth_v1); +} + +//--- ae_roundsp16f24asym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_roundsp16f24asym(ae_int32x2 ae_arth_v0) { +// CHECK-LABEL: test_ae_roundsp16f24asym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.roundsp16f24asym(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_roundsp16f24asym(ae_arth_v0); +} + +//--- ae_roundsp16f24sym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_roundsp16f24sym(ae_int32x2 ae_arth_v0) { +// CHECK-LABEL: test_ae_roundsp16f24sym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.roundsp16f24sym(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_roundsp16f24sym(ae_arth_v0); +} + +//--- ae_roundsp16q48x2asym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_roundsp16q48x2asym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_roundsp16q48x2asym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.roundsp16q48x2asym(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_roundsp16q48x2asym(ae_arth_v0, ae_arth_v1); +} + +//--- ae_roundsp16q48x2sym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_roundsp16q48x2sym(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_roundsp16q48x2sym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.roundsp16q48x2sym(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_roundsp16q48x2sym(ae_arth_v0, ae_arth_v1); +} + +//--- ae_roundsq32f48asym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_roundsq32f48asym(ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_roundsq32f48asym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.roundsq32f48asym(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_roundsq32f48asym(ae_arth_v1); +} + +//--- ae_roundsq32f48sym.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_roundsq32f48sym(ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_roundsq32f48sym +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.roundsq32f48sym(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_roundsq32f48sym(ae_arth_v1); +} + +//--- ae_s16_0_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16_0_i(ae_int16x4 ae_ls_v,ae_int16* ars,immediate ae_immls16) { +// CHECK-LABEL: test_ae_s16_0_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s16.0.i(<4 x i16> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16_0_i(ae_ls_v, ars, -16); +} + +//--- ae_s16_0_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16_0_ip(ae_int16x4 ae_ls_v,ae_int16** ars,immediate ae_immls16) { +// CHECK-LABEL: test_ae_s16_0_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16.0.ip(<4 x i16> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16_0_ip(ae_ls_v, ars, -16); +} + +//--- ae_s16_0_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16_0_x(ae_int16x4 ae_ls_v,ae_int16* ars,int art) { +// CHECK-LABEL: test_ae_s16_0_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s16.0.x(<4 x i16> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16_0_x(ae_ls_v, ars, art); +} + +//--- ae_s16_0_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16_0_xc(ae_int16x4 ae_ls_v,ae_int16** ars,int art) { +// CHECK-LABEL: test_ae_s16_0_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16.0.xc(<4 x i16> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16_0_xc(ae_ls_v, ars, art); +} + +//--- ae_s16_0_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16_0_xp(ae_int16x4 ae_ls_v,ae_int16** ars,int art) { +// CHECK-LABEL: test_ae_s16_0_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16.0.xp(<4 x i16> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16_0_xp(ae_ls_v, ars, art); +} + +//--- ae_s16m_l_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16m_l_i(ae_int32x2 ae_ls_v,ae_int16* ars,immediate ae_immls16) { +// CHECK-LABEL: test_ae_s16m_l_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s16m.l.i(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16m_l_i(ae_ls_v, ars, -16); +} + +//--- ae_s16m_l_iu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16m_l_iu(ae_int32x2 ae_ls_v,ae_int16** ars,immediate ae_immls16) { +// CHECK-LABEL: test_ae_s16m_l_iu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16m.l.iu(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16m_l_iu(ae_ls_v, ars, -16); +} + +//--- ae_s16m_l_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16m_l_x(ae_int32x2 ae_ls_v,ae_int16* ars,int art) { +// CHECK-LABEL: test_ae_s16m_l_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s16m.l.x(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16m_l_x(ae_ls_v, ars, art); +} + +//--- ae_s16m_l_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16m_l_xc(ae_int32x2 ae_ls_v,ae_int16** ars,int art) { +// CHECK-LABEL: test_ae_s16m_l_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16m.l.xc(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16m_l_xc(ae_ls_v, ars, art); +} + +//--- ae_s16m_l_xu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16m_l_xu(ae_int32x2 ae_ls_v,ae_int16** ars,int art) { +// CHECK-LABEL: test_ae_s16m_l_xu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16m.l.xu(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16m_l_xu(ae_ls_v, ars, art); +} + +//--- ae_s16x2m_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x2m_i(ae_int32x2 ae_ls_v,ae_int16x2* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s16x2m_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s16x2m.i(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x2m_i(ae_ls_v, ars, -32); +} + +//--- ae_s16x2m_iu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x2m_iu(ae_int32x2 ae_ls_v,ae_int16x2** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s16x2m_iu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16x2m.iu(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x2m_iu(ae_ls_v, ars, -32); +} + +//--- ae_s16x2m_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x2m_x(ae_int32x2 ae_ls_v,ae_int16x2* ars,int art) { +// CHECK-LABEL: test_ae_s16x2m_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s16x2m.x(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x2m_x(ae_ls_v, ars, art); +} + +//--- ae_s16x2m_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x2m_xc(ae_int32x2 ae_ls_v,ae_int16x2** ars,int art) { +// CHECK-LABEL: test_ae_s16x2m_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16x2m.xc(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x2m_xc(ae_ls_v, ars, art); +} + +//--- ae_s16x2m_xu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x2m_xu(ae_int32x2 ae_ls_v,ae_int16x2** ars,int art) { +// CHECK-LABEL: test_ae_s16x2m_xu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16x2m.xu(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x2m_xu(ae_ls_v, ars, art); +} + +//--- ae_s16x4_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x4_i(ae_int16x4 ae_ls_v,ae_int16x4* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_s16x4_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s16x4.i(<4 x i16> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x4_i(ae_ls_v, ars, -64); +} + +//--- ae_s16x4_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x4_ip(ae_int16x4 ae_ls_v,ae_int16x4** ars,immediate ae_immls64pos) { +// CHECK-LABEL: test_ae_s16x4_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16x4.ip(<4 x i16> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x4_ip(ae_ls_v, ars, 0); +} + +//--- ae_s16x4_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x4_ric(ae_int16x4 ae_ls_v,ae_int16x4** ars) { +// CHECK-LABEL: test_ae_s16x4_ric +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16x4.ric(<4 x i16> {{.*}}, ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_s16x4_ric(ae_ls_v, ars); +} + +//--- ae_s16x4_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x4_rip(ae_int16x4 ae_ls_v,ae_int16x4** ars) { +// CHECK-LABEL: test_ae_s16x4_rip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16x4.rip(<4 x i16> {{.*}}, ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_s16x4_rip(ae_ls_v, ars); +} + +//--- ae_s16x4_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x4_x(ae_int16x4 ae_ls_v,ae_int16x4* ars,int art) { +// CHECK-LABEL: test_ae_s16x4_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s16x4.x(<4 x i16> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x4_x(ae_ls_v, ars, art); +} + +//--- ae_s16x4_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x4_xc(ae_int16x4 ae_ls_v,ae_int16x4** ars,int art) { +// CHECK-LABEL: test_ae_s16x4_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16x4.xc(<4 x i16> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x4_xc(ae_ls_v, ars, art); +} + +//--- ae_s16x4_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s16x4_xp(ae_int16x4 ae_ls_v,ae_int16x4** ars,int art) { +// CHECK-LABEL: test_ae_s16x4_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s16x4.xp(<4 x i16> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s16x4_xp(ae_ls_v, ars, art); +} + +//--- ae_s24ra64s_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s24ra64s_i(ae_int64 ae_ls_v1,ae_int32* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s24ra64s_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s24ra64s.i(<1 x i64> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s24ra64s_i(ae_ls_v1, ars, -32); +} + +//--- ae_s24ra64s_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s24ra64s_ip(ae_int64 ae_ls_v1,ae_int32** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s24ra64s_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s24ra64s.ip(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s24ra64s_ip(ae_ls_v1, ars, -32); +} + +//--- ae_s24ra64s_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s24ra64s_x(ae_int64 ae_ls_v1,ae_int32* ars,int art) { +// CHECK-LABEL: test_ae_s24ra64s_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s24ra64s.x(<1 x i64> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s24ra64s_x(ae_ls_v1, ars, art); +} + +//--- ae_s24ra64s_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s24ra64s_xc(ae_int64 ae_ls_v1,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s24ra64s_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s24ra64s.xc(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s24ra64s_xc(ae_ls_v1, ars, art); +} + +//--- ae_s24ra64s_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s24ra64s_xp(ae_int64 ae_ls_v1,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s24ra64s_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s24ra64s.xp(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s24ra64s_xp(ae_ls_v1, ars, art); +} + +//--- ae_s24x2ra64s_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s24x2ra64s_ip(ae_int64 ae_ls_v2,ae_int64 ae_ls_v1,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_s24x2ra64s_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s24x2ra64s.ip(<1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_s24x2ra64s_ip(ae_ls_v2, ae_ls_v1, ars); +} + +//--- ae_s32_l_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32_l_i(ae_int32x2 ae_ls_v,ae_int32* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s32_l_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32.l.i(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32_l_i(ae_ls_v, ars, -32); +} + +//--- ae_s32_l_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32_l_ip(ae_int32x2 ae_ls_v,ae_int32** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s32_l_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32.l.ip(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32_l_ip(ae_ls_v, ars, -32); +} + +//--- ae_s32_l_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32_l_x(ae_int32x2 ae_ls_v,ae_int32* ars,int art) { +// CHECK-LABEL: test_ae_s32_l_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32.l.x(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32_l_x(ae_ls_v, ars, art); +} + +//--- ae_s32_l_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32_l_xc(ae_int32x2 ae_ls_v,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s32_l_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32.l.xc(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32_l_xc(ae_ls_v, ars, art); +} + +//--- ae_s32_l_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32_l_xp(ae_int32x2 ae_ls_v,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s32_l_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32.l.xp(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32_l_xp(ae_ls_v, ars, art); +} + +//--- ae_s32f24_l_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32f24_l_i(ae_int32x2 ae_ls_v,ae_int32* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s32f24_l_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32f24.l.i(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32f24_l_i(ae_ls_v, ars, -32); +} + +//--- ae_s32f24_l_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32f24_l_ip(ae_int32x2 ae_ls_v,ae_int32** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s32f24_l_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32f24.l.ip(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32f24_l_ip(ae_ls_v, ars, -32); +} + +//--- ae_s32f24_l_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32f24_l_x(ae_int32x2 ae_ls_v,ae_int32* ars,int art) { +// CHECK-LABEL: test_ae_s32f24_l_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32f24.l.x(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32f24_l_x(ae_ls_v, ars, art); +} + +//--- ae_s32f24_l_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32f24_l_xc(ae_int32x2 ae_ls_v,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s32f24_l_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32f24.l.xc(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32f24_l_xc(ae_ls_v, ars, art); +} + +//--- ae_s32f24_l_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32f24_l_xp(ae_int32x2 ae_ls_v,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s32f24_l_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32f24.l.xp(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32f24_l_xp(ae_ls_v, ars, art); +} + +//--- ae_s32m_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32m_i(ae_int64 ae_ls_v,ae_int32* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s32m_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32m.i(<1 x i64> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32m_i(ae_ls_v, ars, -32); +} + +//--- ae_s32m_iu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32m_iu(ae_int64 ae_ls_v,ae_int32** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s32m_iu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32m.iu(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32m_iu(ae_ls_v, ars, -32); +} + +//--- ae_s32m_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32m_x(ae_int64 ae_ls_v,ae_int32* ars,int art) { +// CHECK-LABEL: test_ae_s32m_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32m.x(<1 x i64> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32m_x(ae_ls_v, ars, art); +} + +//--- ae_s32m_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32m_xc(ae_int64 ae_ls_v,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s32m_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32m.xc(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32m_xc(ae_ls_v, ars, art); +} + +//--- ae_s32m_xu.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32m_xu(ae_int64 ae_ls_v,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s32m_xu +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32m.xu(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32m_xu(ae_ls_v, ars, art); +} + +//--- ae_s32ra64s_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32ra64s_i(ae_int64 ae_ls_v1,ae_int32* ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s32ra64s_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32ra64s.i(<1 x i64> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32ra64s_i(ae_ls_v1, ars, -32); +} + +//--- ae_s32ra64s_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32ra64s_ip(ae_int64 ae_ls_v1,ae_int32** ars,immediate ae_immls32) { +// CHECK-LABEL: test_ae_s32ra64s_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32ra64s.ip(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32ra64s_ip(ae_ls_v1, ars, -32); +} + +//--- ae_s32ra64s_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32ra64s_x(ae_int64 ae_ls_v1,ae_int32* ars,int art) { +// CHECK-LABEL: test_ae_s32ra64s_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32ra64s.x(<1 x i64> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32ra64s_x(ae_ls_v1, ars, art); +} + +//--- ae_s32ra64s_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32ra64s_xc(ae_int64 ae_ls_v1,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s32ra64s_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32ra64s.xc(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32ra64s_xc(ae_ls_v1, ars, art); +} + +//--- ae_s32ra64s_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32ra64s_xp(ae_int64 ae_ls_v1,ae_int32** ars,int art) { +// CHECK-LABEL: test_ae_s32ra64s_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32ra64s.xp(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32ra64s_xp(ae_ls_v1, ars, art); +} + +//--- ae_s32x2_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2_i(ae_int32x2 ae_ls_v,ae_int32x2* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_s32x2_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32x2.i(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2_i(ae_ls_v, ars, -64); +} + +//--- ae_s32x2_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2_ip(ae_int32x2 ae_ls_v,ae_int32x2** ars,immediate ae_immls64pos) { +// CHECK-LABEL: test_ae_s32x2_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2.ip(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2_ip(ae_ls_v, ars, 0); +} + +//--- ae_s32x2_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2_ric(ae_int32x2 ae_ls_v,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_s32x2_ric +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2.ric(<2 x i32> {{.*}}, ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_s32x2_ric(ae_ls_v, ars); +} + +//--- ae_s32x2_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2_rip(ae_int32x2 ae_ls_v,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_s32x2_rip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2.rip(<2 x i32> {{.*}}, ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_s32x2_rip(ae_ls_v, ars); +} + +//--- ae_s32x2_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2_x(ae_int32x2 ae_ls_v,ae_int32x2* ars,int art) { +// CHECK-LABEL: test_ae_s32x2_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32x2.x(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2_x(ae_ls_v, ars, art); +} + +//--- ae_s32x2_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2_xc(ae_int32x2 ae_ls_v,ae_int32x2** ars,int art) { +// CHECK-LABEL: test_ae_s32x2_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2.xc(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2_xc(ae_ls_v, ars, art); +} + +//--- ae_s32x2_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2_xp(ae_int32x2 ae_ls_v,ae_int32x2** ars,int art) { +// CHECK-LABEL: test_ae_s32x2_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2.xp(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2_xp(ae_ls_v, ars, art); +} + +//--- ae_s32x2f24_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2f24_i(ae_int32x2 ae_ls_v,ae_int32x2* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_s32x2f24_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32x2f24.i(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2f24_i(ae_ls_v, ars, -64); +} + +//--- ae_s32x2f24_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2f24_ip(ae_int32x2 ae_ls_v,ae_int32x2** ars,immediate ae_immls64pos) { +// CHECK-LABEL: test_ae_s32x2f24_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2f24.ip(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2f24_ip(ae_ls_v, ars, 0); +} + +//--- ae_s32x2f24_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2f24_ric(ae_int32x2 ae_ls_v,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_s32x2f24_ric +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2f24.ric(<2 x i32> {{.*}}, ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_s32x2f24_ric(ae_ls_v, ars); +} + +//--- ae_s32x2f24_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2f24_rip(ae_int32x2 ae_ls_v,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_s32x2f24_rip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2f24.rip(<2 x i32> {{.*}}, ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_s32x2f24_rip(ae_ls_v, ars); +} + +//--- ae_s32x2f24_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2f24_x(ae_int32x2 ae_ls_v,ae_int32x2* ars,int art) { +// CHECK-LABEL: test_ae_s32x2f24_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s32x2f24.x(<2 x i32> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2f24_x(ae_ls_v, ars, art); +} + +//--- ae_s32x2f24_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2f24_xc(ae_int32x2 ae_ls_v,ae_int32x2** ars,int art) { +// CHECK-LABEL: test_ae_s32x2f24_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2f24.xc(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2f24_xc(ae_ls_v, ars, art); +} + +//--- ae_s32x2f24_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2f24_xp(ae_int32x2 ae_ls_v,ae_int32x2** ars,int art) { +// CHECK-LABEL: test_ae_s32x2f24_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2f24.xp(<2 x i32> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s32x2f24_xp(ae_ls_v, ars, art); +} + +//--- ae_s32x2ra64s_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s32x2ra64s_ip(ae_int64 ae_ls_v2,ae_int64 ae_ls_v1,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_s32x2ra64s_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s32x2ra64s.ip(<1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_s32x2ra64s_ip(ae_ls_v2, ae_ls_v1, ars); +} + +//--- ae_s64_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s64_i(ae_int64 ae_ls_v,ae_int64* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_s64_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s64.i(<1 x i64> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s64_i(ae_ls_v, ars, -64); +} + +//--- ae_s64_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s64_ip(ae_int64 ae_ls_v,ae_int64** ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_s64_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s64.ip(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s64_ip(ae_ls_v, ars, -64); +} + +//--- ae_s64_x.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s64_x(ae_int64 ae_ls_v,ae_int64* ars,int art) { +// CHECK-LABEL: test_ae_s64_x +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.s64.x(<1 x i64> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s64_x(ae_ls_v, ars, art); +} + +//--- ae_s64_xc.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s64_xc(ae_int64 ae_ls_v,ae_int64** ars,int art) { +// CHECK-LABEL: test_ae_s64_xc +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s64.xc(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s64_xc(ae_ls_v, ars, art); +} + +//--- ae_s64_xp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_s64_xp(ae_int64 ae_ls_v,ae_int64** ars,int art) { +// CHECK-LABEL: test_ae_s64_xp +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.s64.xp(<1 x i64> {{.*}}, ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_s64_xp(ae_ls_v, ars, art); +} + +//--- ae_sa16x4_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa16x4_ic(ae_int16x4 ae_ls_v,ae_valign* ae_ls_su,ae_int16x4** ars) { +// CHECK-LABEL: test_ae_sa16x4_ic +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ic(<4 x i16> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa16x4_ic(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa16x4_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa16x4_ip(ae_int16x4 ae_ls_v,ae_valign* ae_ls_su,ae_int16x4** ars) { +// CHECK-LABEL: test_ae_sa16x4_ip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ip(<4 x i16> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa16x4_ip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa16x4_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa16x4_ric(ae_int16x4 ae_ls_v,ae_valign* ae_ls_su,ae_int16x4** ars) { +// CHECK-LABEL: test_ae_sa16x4_ric +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.ric(<4 x i16> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa16x4_ric(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa16x4_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa16x4_rip(ae_int16x4 ae_ls_v,ae_valign* ae_ls_su,ae_int16x4** ars) { +// CHECK-LABEL: test_ae_sa16x4_rip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa16x4.rip(<4 x i16> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa16x4_rip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa24_l_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa24_l_ic(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) { +// CHECK-LABEL: test_ae_sa24_l_ic +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ic(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa24_l_ic(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa24_l_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa24_l_ip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) { +// CHECK-LABEL: test_ae_sa24_l_ip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ip(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa24_l_ip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa24_l_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa24_l_ric(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) { +// CHECK-LABEL: test_ae_sa24_l_ric +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.ric(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa24_l_ric(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa24_l_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa24_l_rip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) { +// CHECK-LABEL: test_ae_sa24_l_rip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24.l.rip(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa24_l_rip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa24x2_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa24x2_ic(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) { +// CHECK-LABEL: test_ae_sa24x2_ic +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ic(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa24x2_ic(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa24x2_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa24x2_ip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) { +// CHECK-LABEL: test_ae_sa24x2_ip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ip(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa24x2_ip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa24x2_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa24x2_ric(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) { +// CHECK-LABEL: test_ae_sa24x2_ric +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.ric(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa24x2_ric(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa24x2_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa24x2_rip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,void** ars) { +// CHECK-LABEL: test_ae_sa24x2_rip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa24x2.rip(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa24x2_rip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa32x2_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa32x2_ic(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_sa32x2_ic +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ic(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa32x2_ic(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa32x2_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa32x2_ip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_sa32x2_ip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ip(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa32x2_ip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa32x2_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa32x2_ric(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_sa32x2_ric +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.ric(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa32x2_ric(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa32x2_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa32x2_rip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_sa32x2_rip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2.rip(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa32x2_rip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa32x2f24_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa32x2f24_ic(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_sa32x2f24_ic +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ic(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa32x2f24_ic(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa32x2f24_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa32x2f24_ip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_sa32x2f24_ip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ip(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa32x2f24_ip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa32x2f24_ric.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa32x2f24_ric(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_sa32x2f24_ric +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.ric(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa32x2f24_ric(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa32x2f24_rip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa32x2f24_rip(ae_int32x2 ae_ls_v,ae_valign* ae_ls_su,ae_int32x2** ars) { +// CHECK-LABEL: test_ae_sa32x2f24_rip +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <8 x i8>, ptr } @llvm.xtensa.ae.sa32x2f24.rip(<2 x i32> {{.*}}, <8 x i8> %[[LD_AE_LS_SU]], ptr %[[LD_ARS]]) +// CHECK: %[[EV:.*]] = extractvalue { <8 x i8>, ptr } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_sa32x2f24_rip(ae_ls_v, ae_ls_su, ars); +} + +//--- ae_sa64neg_fp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa64neg_fp(ae_valign* ae_ls_su,void* ars) { +// CHECK-LABEL: test_ae_sa64neg_fp +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <8 x i8> @llvm.xtensa.ae.sa64neg.fp(<8 x i8> %[[LD_AE_LS_SU]], ptr {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_sa64neg_fp(ae_ls_su, ars); +} + +//--- ae_sa64pos_fp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sa64pos_fp(ae_valign* ae_ls_su,void* ars) { +// CHECK-LABEL: test_ae_sa64pos_fp +// CHECK: %[[LD_AE_LS_SU:.*]] = load <8 x i8>, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call <8 x i8> @llvm.xtensa.ae.sa64pos.fp(<8 x i8> %[[LD_AE_LS_SU]], ptr {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_sa64pos_fp(ae_ls_su, ars); +} + +//--- ae_salign64_i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_salign64_i(ae_valign ae_ls_su,ae_valign* ars,immediate ae_immls64) { +// CHECK-LABEL: test_ae_salign64_i +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.salign64.i(<8 x i8> {{.*}}, ptr {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_salign64_i(ae_ls_su, ars, -64); +} + +//--- ae_sat16x4.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_sat16x4(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_sat16x4 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.sat16x4(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_sat16x4(ae_arth_v0, ae_arth_v1); +} + +//--- ae_sat24s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sat24s(ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_sat24s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sat24s(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sat24s(ae_arth_v1); +} + +//--- ae_sat48s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_sat48s(ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_sat48s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.sat48s(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_sat48s(ae_arth_v1); +} + +//--- ae_satq56s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_satq56s(ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_satq56s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.satq56s(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_satq56s(ae_arth_v1); +} + +//--- ae_sb.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sb(short** ars,int art) { +// CHECK-LABEL: test_ae_sb +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sb(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_sb(ars, art); +} + +//--- ae_sb_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sb_ic(short** ars,int art) { +// CHECK-LABEL: test_ae_sb_ic +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sb.ic(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_sb_ic(ars, art); +} + +//--- ae_sb_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sb_ip(short** ars,int art) { +// CHECK-LABEL: test_ae_sb_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sb.ip(ptr %[[LD_ARS]], i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_sb_ip(ars, art); +} + +//--- ae_sbf.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sbf(short** ars) { +// CHECK-LABEL: test_ae_sbf +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sbf(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_sbf(ars); +} + +//--- ae_sbf_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sbf_ic(short** ars) { +// CHECK-LABEL: test_ae_sbf_ic +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sbf.ic(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_sbf_ic(ars); +} + +//--- ae_sbf_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sbf_ip(short** ars) { +// CHECK-LABEL: test_ae_sbf_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sbf.ip(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_sbf_ip(ars); +} + +//--- ae_sbi.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sbi(short** ars,int art,immediate ae_ohba2) { +// CHECK-LABEL: test_ae_sbi +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sbi(ptr %[[LD_ARS]], i32 {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_sbi(ars, art, 1); +} + +//--- ae_sbi_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sbi_ic(short** ars,int art,immediate ae_ohba2) { +// CHECK-LABEL: test_ae_sbi_ic +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sbi.ic(ptr %[[LD_ARS]], i32 {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_sbi_ic(ars, art, 1); +} + +//--- ae_sbi_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_sbi_ip(short** ars,int art,immediate ae_ohba2) { +// CHECK-LABEL: test_ae_sbi_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.sbi.ip(ptr %[[LD_ARS]], i32 {{.*}}, i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_sbi_ip(ars, art, 1); +} + +//--- ae_sel16i.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_sel16i(ae_int16x4 ae_dr_to_dr_v0,ae_int16x4 ae_dr_to_dr_v1,immediate ae_selimm) { +// CHECK-LABEL: test_ae_sel16i +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.sel16i(<4 x i16> {{.*}}, <4 x i16> {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_sel16i(ae_dr_to_dr_v0, ae_dr_to_dr_v1, 0); +} + +//--- ae_sel16i_n.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_sel16i_n(ae_int16x4 ae_dr_to_dr_v0,ae_int16x4 ae_dr_to_dr_v1,immediate ae_selimm_N) { +// CHECK-LABEL: test_ae_sel16i_n +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.sel16i.n(<4 x i16> {{.*}}, <4 x i16> {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_sel16i_n(ae_dr_to_dr_v0, ae_dr_to_dr_v1, 0); +} + +//--- ae_sext32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sext32(ae_int32x2 ae_dr_to_dr_v0,immediate ae_opnd_tp7) { +// CHECK-LABEL: test_ae_sext32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sext32(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sext32(ae_dr_to_dr_v0, 7); +} + +//--- ae_sext32x2d16_10.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sext32x2d16_10(ae_int16x4 ae_to_dr_v0) { +// CHECK-LABEL: test_ae_sext32x2d16_10 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sext32x2d16.10(<4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sext32x2d16_10(ae_to_dr_v0); +} + +//--- ae_sext32x2d16_32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sext32x2d16_32(ae_int16x4 ae_to_dr_v0) { +// CHECK-LABEL: test_ae_sext32x2d16_32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sext32x2d16.32(<4 x i16> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sext32x2d16_32(ae_to_dr_v0); +} + +//--- ae_sha32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_ae_sha32(int ars) { +// CHECK-LABEL: test_ae_sha32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.ae.sha32(i32 {{.*}}) +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_ae_sha32(ars); +} + +//--- ae_shortswap.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_shortswap(ae_int16x4 ae_to_dr_v0) { +// CHECK-LABEL: test_ae_shortswap +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.shortswap(<4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_shortswap(ae_to_dr_v0); +} + +//--- ae_slaa16s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_slaa16s(ae_int16x4 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_slaa16s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.slaa16s(<4 x i16> {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_slaa16s(ae_shift_d0, ars); +} + +//--- ae_slaa32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slaa32(ae_int32x2 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_slaa32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slaa32(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slaa32(ae_shift_d0, ars); +} + +//--- ae_slaa32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slaa32s(ae_int32x2 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_slaa32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slaa32s(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slaa32s(ae_shift_d0, ars); +} + +//--- ae_slaa64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slaa64(ae_int64 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_slaa64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slaa64(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slaa64(ae_shift_d0, ars); +} + +//--- ae_slaa64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slaa64s(ae_int64 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_slaa64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slaa64s(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slaa64s(ae_shift_d0, ars); +} + +//--- ae_slaaq56.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slaaq56(ae_int64 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_slaaq56 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slaaq56(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slaaq56(ae_shift_d0, ars); +} + +//--- ae_slai16s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_slai16s(ae_int16x4 ae_shift_d0,immediate ae_osa16) { +// CHECK-LABEL: test_ae_slai16s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.slai16s(<4 x i16> {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_slai16s(ae_shift_d0, 0); +} + +//--- ae_slai24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slai24(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_slai24 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slai24(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slai24(ae_shift_d0, 0); +} + +//--- ae_slai24s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slai24s(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_slai24s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slai24s(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slai24s(ae_shift_d0, 0); +} + +//--- ae_slai32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slai32(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_slai32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slai32(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slai32(ae_shift_d0, 0); +} + +//--- ae_slai32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slai32s(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_slai32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slai32s(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slai32s(ae_shift_d0, 0); +} + +//--- ae_slai64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slai64(ae_int64 ae_shift_d0,immediate ae_osa64) { +// CHECK-LABEL: test_ae_slai64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slai64(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slai64(ae_shift_d0, 0); +} + +//--- ae_slai64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slai64s(ae_int64 ae_shift_d0,immediate ae_osa64) { +// CHECK-LABEL: test_ae_slai64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slai64s(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slai64s(ae_shift_d0, 0); +} + +//--- ae_slaisq56s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slaisq56s(ae_int64 ae_shift_d0,immediate ae_osa64) { +// CHECK-LABEL: test_ae_slaisq56s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slaisq56s(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slaisq56s(ae_shift_d0, 0); +} + +//--- ae_slas24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slas24(ae_int32x2 ae_shift_d0) { +// CHECK-LABEL: test_ae_slas24 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slas24(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slas24(ae_shift_d0); +} + +//--- ae_slas24s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slas24s(ae_int32x2 ae_shift_d0) { +// CHECK-LABEL: test_ae_slas24s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slas24s(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slas24s(ae_shift_d0); +} + +//--- ae_slas32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slas32(ae_int32x2 ae_shift_d0) { +// CHECK-LABEL: test_ae_slas32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slas32(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slas32(ae_shift_d0); +} + +//--- ae_slas32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_slas32s(ae_int32x2 ae_shift_d0) { +// CHECK-LABEL: test_ae_slas32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.slas32s(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_slas32s(ae_shift_d0); +} + +//--- ae_slas64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slas64(ae_int64 ae_shift_d0) { +// CHECK-LABEL: test_ae_slas64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slas64(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slas64(ae_shift_d0); +} + +//--- ae_slas64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slas64s(ae_int64 ae_shift_d0) { +// CHECK-LABEL: test_ae_slas64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slas64s(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slas64s(ae_shift_d0); +} + +//--- ae_slasq56.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slasq56(ae_int64 ae_shift_d0) { +// CHECK-LABEL: test_ae_slasq56 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slasq56(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slasq56(ae_shift_d0); +} + +//--- ae_slassq56s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_slassq56s(ae_int64 ae_shift_d0) { +// CHECK-LABEL: test_ae_slassq56s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.slassq56s(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_slassq56s(ae_shift_d0); +} + +//--- ae_sra64_32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_sra64_32(ae_int32x2 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_sra64_32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.sra64.32(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_sra64_32(ae_shift_d0, ars); +} + +//--- ae_sraa16rs.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_sraa16rs(ae_int16x4 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_sraa16rs +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.sraa16rs(<4 x i16> {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_sraa16rs(ae_shift_d0, ars); +} + +//--- ae_sraa16s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_sraa16s(ae_int16x4 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_sraa16s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.sraa16s(<4 x i16> {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_sraa16s(ae_shift_d0, ars); +} + +//--- ae_sraa32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sraa32(ae_int32x2 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_sraa32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sraa32(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sraa32(ae_shift_d0, ars); +} + +//--- ae_sraa32rs.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sraa32rs(ae_int32x2 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_sraa32rs +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sraa32rs(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sraa32rs(ae_shift_d0, ars); +} + +//--- ae_sraa32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sraa32s(ae_int32x2 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_sraa32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sraa32s(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sraa32s(ae_shift_d0, ars); +} + +//--- ae_sraa64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_sraa64(ae_int64 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_sraa64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.sraa64(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_sraa64(ae_shift_d0, ars); +} + +//--- ae_srai16.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_srai16(ae_int16x4 ae_shift_d0,immediate ae_osa16) { +// CHECK-LABEL: test_ae_srai16 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.srai16(<4 x i16> {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_srai16(ae_shift_d0, 0); +} + +//--- ae_srai16r.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_srai16r(ae_int16x4 ae_shift_d0,immediate ae_osa16) { +// CHECK-LABEL: test_ae_srai16r +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.srai16r(<4 x i16> {{.*}}, i32 {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_srai16r(ae_shift_d0, 0); +} + +//--- ae_srai24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_srai24(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_srai24 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.srai24(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_srai24(ae_shift_d0, 0); +} + +//--- ae_srai32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_srai32(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_srai32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.srai32(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_srai32(ae_shift_d0, 0); +} + +//--- ae_srai32r.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_srai32r(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_srai32r +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.srai32r(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_srai32r(ae_shift_d0, 0); +} + +//--- ae_srai64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_srai64(ae_int64 ae_shift_d0,immediate ae_osa64) { +// CHECK-LABEL: test_ae_srai64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.srai64(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_srai64(ae_shift_d0, 0); +} + +//--- ae_sras24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sras24(ae_int32x2 ae_shift_d0) { +// CHECK-LABEL: test_ae_sras24 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sras24(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sras24(ae_shift_d0); +} + +//--- ae_sras32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sras32(ae_int32x2 ae_shift_d0) { +// CHECK-LABEL: test_ae_sras32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sras32(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sras32(ae_shift_d0); +} + +//--- ae_sras64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_sras64(ae_int64 ae_shift_d0) { +// CHECK-LABEL: test_ae_sras64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.sras64(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_sras64(ae_shift_d0); +} + +//--- ae_srla32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_srla32(ae_int32x2 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_srla32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.srla32(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_srla32(ae_shift_d0, ars); +} + +//--- ae_srla64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_srla64(ae_int64 ae_shift_d0,int ars) { +// CHECK-LABEL: test_ae_srla64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.srla64(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_srla64(ae_shift_d0, ars); +} + +//--- ae_srli24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_srli24(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_srli24 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.srli24(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_srli24(ae_shift_d0, 0); +} + +//--- ae_srli32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_srli32(ae_int32x2 ae_shift_d0,immediate ae_osa32) { +// CHECK-LABEL: test_ae_srli32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.srli32(<2 x i32> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_srli32(ae_shift_d0, 0); +} + +//--- ae_srli64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_srli64(ae_int64 ae_shift_d0,immediate ae_osa64) { +// CHECK-LABEL: test_ae_srli64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.srli64(<1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_srli64(ae_shift_d0, 0); +} + +//--- ae_srls24.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_srls24(ae_int32x2 ae_shift_d0) { +// CHECK-LABEL: test_ae_srls24 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.srls24(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_srls24(ae_shift_d0); +} + +//--- ae_srls32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_srls32(ae_int32x2 ae_shift_d0) { +// CHECK-LABEL: test_ae_srls32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.srls32(<2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_srls32(ae_shift_d0); +} + +//--- ae_srls64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_srls64(ae_int64 ae_shift_d0) { +// CHECK-LABEL: test_ae_srls64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.srls64(<1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_srls64(ae_shift_d0); +} + +//--- ae_sub16.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_sub16(ae_int16x4 ae_arth_v0,ae_int16x4 ae_arth_v1) { +// CHECK-LABEL: test_ae_sub16 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.sub16(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_sub16(ae_arth_v0, ae_arth_v1); +} + +//--- ae_sub16s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int16x4 test_ae_sub16s(ae_int16x4 ae_arth_v0,ae_int16x4 ae_arth_v1) { +// CHECK-LABEL: test_ae_sub16s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <4 x i16> @llvm.xtensa.ae.sub16s(<4 x i16> {{.*}}, <4 x i16> {{.*}}) +// CHECK: ret <4 x i16> %[[RET]] +return __builtin_xtensa_ae_sub16s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_sub24s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sub24s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_sub24s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sub24s(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sub24s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_sub32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sub32(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_sub32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sub32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sub32(ae_arth_v0, ae_arth_v1); +} + +//--- ae_sub32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_sub32s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_sub32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.sub32s(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_sub32s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_sub64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_sub64(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_sub64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.sub64(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_sub64(ae_arth_v0, ae_arth_v1); +} + +//--- ae_sub64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_sub64s(ae_int64 ae_arth_v0,ae_int64 ae_arth_v1) { +// CHECK-LABEL: test_ae_sub64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.sub64s(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_sub64s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_subadd32.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_subadd32(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_subadd32 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.subadd32(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_subadd32(ae_arth_v0, ae_arth_v1); +} + +//--- ae_subadd32s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_subadd32s(ae_int32x2 ae_arth_v0,ae_int32x2 ae_arth_v1) { +// CHECK-LABEL: test_ae_subadd32s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.subadd32s(<2 x i32> {{.*}}, <2 x i32> {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_subadd32s(ae_arth_v0, ae_arth_v1); +} + +//--- ae_trunca32f64s_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_trunca32f64s_l(ae_int32x2 ae_shift_d0,ae_int64 ae_shift_sd,int ars) { +// CHECK-LABEL: test_ae_trunca32f64s_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.trunca32f64s.l(<2 x i32> {{.*}}, <1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_trunca32f64s_l(ae_shift_d0, ae_shift_sd, ars); +} + +//--- ae_trunca32x2f64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_trunca32x2f64s(ae_int64 ae_shift_d0,ae_int64 ae_shift_sd,int ars) { +// CHECK-LABEL: test_ae_trunca32x2f64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.trunca32x2f64s(<1 x i64> {{.*}}, <1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_trunca32x2f64s(ae_shift_d0, ae_shift_sd, ars); +} + +//--- ae_trunci32f64s_l.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_trunci32f64s_l(ae_int32x2 ae_shift_d0,ae_int64 ae_shift_sd,immediate ae_osa16) { +// CHECK-LABEL: test_ae_trunci32f64s_l +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.trunci32f64s.l(<2 x i32> {{.*}}, <1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_trunci32f64s_l(ae_shift_d0, ae_shift_sd, 0); +} + +//--- ae_trunci32x2f64s.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int32x2 test_ae_trunci32x2f64s(ae_int64 ae_shift_d0,ae_int64 ae_shift_sd,immediate ae_osa16) { +// CHECK-LABEL: test_ae_trunci32x2f64s +// CHECK: %[[RET:.*]] = {{(tail)?}} call <2 x i32> @llvm.xtensa.ae.trunci32x2f64s(<1 x i64> {{.*}}, <1 x i64> {{.*}}, i32 {{.*}}) +// CHECK: ret <2 x i32> %[[RET]] +return __builtin_xtensa_ae_trunci32x2f64s(ae_shift_d0, ae_shift_sd, 0); +} + +//--- ae_vldl16c.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vldl16c(const short** ars) { +// CHECK-LABEL: test_ae_vldl16c +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.vldl16c(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_vldl16c(ars); +} + +//--- ae_vldl16c_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vldl16c_ic(const short** ars) { +// CHECK-LABEL: test_ae_vldl16c_ic +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.vldl16c.ic(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_vldl16c_ic(ars); +} + +//--- ae_vldl16c_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vldl16c_ip(const short** ars) { +// CHECK-LABEL: test_ae_vldl16c_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.vldl16c.ip(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_vldl16c_ip(ars); +} + +//--- ae_vldl16t.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vldl16t(xtbool* br,int* art,const short* ars) { +// CHECK-LABEL: test_ae_vldl16t +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i1>, i32 } @llvm.xtensa.ae.vldl16t(ptr {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i1>, i32 } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_vldl16t(br, art, ars); +} + +//--- ae_vldl32t.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vldl32t(xtbool* br,int* art,const int* ars) { +// CHECK-LABEL: test_ae_vldl32t +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i1>, i32 } @llvm.xtensa.ae.vldl32t(ptr {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i1>, i32 } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_vldl32t(br, art, ars); +} + +//--- ae_vldsht.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vldsht(int art) { +// CHECK-LABEL: test_ae_vldsht +// CHECK: {{(tail)?}} call void @llvm.xtensa.ae.vldsht(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_ae_vldsht(art); +} + +//--- ae_vlel16t.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vlel16t(xtbool* br,int* art,const short* ars) { +// CHECK-LABEL: test_ae_vlel16t +// CHECK: %[[LD_ART:.*]] = load i32, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i1>, i32 } @llvm.xtensa.ae.vlel16t(i32 %[[LD_ART]], ptr {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i1>, i32 } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_vlel16t(br, art, ars); +} + +//--- ae_vlel32t.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vlel32t(xtbool* br,int* art,const int* ars) { +// CHECK-LABEL: test_ae_vlel32t +// CHECK: %[[LD_ART:.*]] = load i32, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call { <1 x i1>, i32 } @llvm.xtensa.ae.vlel32t(i32 %[[LD_ART]], ptr {{.*}}) +// CHECK: %[[EV:.*]] = extractvalue { <1 x i1>, i32 } %[[RET]], 0 +// CHECK: ret void + __builtin_xtensa_ae_vlel32t(br, art, ars); +} + +//--- ae_vles16c.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vles16c(short** ars) { +// CHECK-LABEL: test_ae_vles16c +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.vles16c(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_vles16c(ars); +} + +//--- ae_vles16c_ic.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vles16c_ic(short** ars) { +// CHECK-LABEL: test_ae_vles16c_ic +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.vles16c.ic(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_vles16c_ic(ars); +} + +//--- ae_vles16c_ip.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_ae_vles16c_ip(short** ars) { +// CHECK-LABEL: test_ae_vles16c_ip +// CHECK: %[[LD_ARS:.*]] = load ptr, ptr {{.*}} +// CHECK: %[[RET:.*]] = {{(tail)?}} call ptr @llvm.xtensa.ae.vles16c.ip(ptr %[[LD_ARS]]) +// CHECK: ret void + __builtin_xtensa_ae_vles16c_ip(ars); +} + +//--- ae_xor.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_int64 test_ae_xor(ae_int64 ae_dr_to_dr_v0,ae_int64 ae_dr_to_dr_v1) { +// CHECK-LABEL: test_ae_xor +// CHECK: %[[RET:.*]] = {{(tail)?}} call <1 x i64> @llvm.xtensa.ae.xor(<1 x i64> {{.*}}, <1 x i64> {{.*}}) +// CHECK: ret <1 x i64> %[[RET]] +return __builtin_xtensa_ae_xor(ae_dr_to_dr_v0, ae_dr_to_dr_v1); +} + +//--- ae_zalign64.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +ae_valign test_ae_zalign64() { +// CHECK-LABEL: test_ae_zalign64 +// CHECK: %[[RET:.*]] = {{(tail)?}} call <8 x i8> @llvm.xtensa.ae.zalign64() +// CHECK: %[[CAST:.*]] = bitcast <8 x i8> %[[RET]] to i64 +// CHECK: ret i64 %[[CAST]] +return __builtin_xtensa_ae_zalign64(); +} + +//--- rur_ae_bithead.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_bithead() { +// CHECK-LABEL: test_rur_ae_bithead +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.bithead() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_bithead(); +} + +//--- rur_ae_bitptr.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_bitptr() { +// CHECK-LABEL: test_rur_ae_bitptr +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.bitptr() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_bitptr(); +} + +//--- rur_ae_bitsused.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_bitsused() { +// CHECK-LABEL: test_rur_ae_bitsused +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.bitsused() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_bitsused(); +} + +//--- rur_ae_cbegin0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_cbegin0() { +// CHECK-LABEL: test_rur_ae_cbegin0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.cbegin0() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_cbegin0(); +} + +//--- rur_ae_cend0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_cend0() { +// CHECK-LABEL: test_rur_ae_cend0 +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.cend0() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_cend0(); +} + +//--- rur_ae_cw_sd_no.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_cw_sd_no() { +// CHECK-LABEL: test_rur_ae_cw_sd_no +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.cw.sd.no() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_cw_sd_no(); +} + +//--- rur_ae_cwrap.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_cwrap() { +// CHECK-LABEL: test_rur_ae_cwrap +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.cwrap() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_cwrap(); +} + +//--- rur_ae_first_ts.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_first_ts() { +// CHECK-LABEL: test_rur_ae_first_ts +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.first.ts() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_first_ts(); +} + +//--- rur_ae_nextoffset.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_nextoffset() { +// CHECK-LABEL: test_rur_ae_nextoffset +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.nextoffset() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_nextoffset(); +} + +//--- rur_ae_overflow.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_overflow() { +// CHECK-LABEL: test_rur_ae_overflow +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.overflow() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_overflow(); +} + +//--- rur_ae_ovf_sar.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_ovf_sar() { +// CHECK-LABEL: test_rur_ae_ovf_sar +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.ovf.sar() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_ovf_sar(); +} + +//--- rur_ae_sar.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_sar() { +// CHECK-LABEL: test_rur_ae_sar +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.sar() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_sar(); +} + +//--- rur_ae_searchdone.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_searchdone() { +// CHECK-LABEL: test_rur_ae_searchdone +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.searchdone() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_searchdone(); +} + +//--- rur_ae_tablesize.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_tablesize() { +// CHECK-LABEL: test_rur_ae_tablesize +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.tablesize() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_tablesize(); +} + +//--- rur_ae_ts_fts_bu_bp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +int test_rur_ae_ts_fts_bu_bp() { +// CHECK-LABEL: test_rur_ae_ts_fts_bu_bp +// CHECK: %[[RET:.*]] = {{(tail)?}} call i32 @llvm.xtensa.rur.ae.ts.fts.bu.bp() +// CHECK: ret i32 %[[RET]] +return __builtin_xtensa_rur_ae_ts_fts_bu_bp(); +} + +//--- wur_ae_bithead.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_bithead(int art) { +// CHECK-LABEL: test_wur_ae_bithead +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.bithead(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_bithead(art); +} + +//--- wur_ae_bitptr.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_bitptr(int art) { +// CHECK-LABEL: test_wur_ae_bitptr +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.bitptr(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_bitptr(art); +} + +//--- wur_ae_bitsused.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_bitsused(int art) { +// CHECK-LABEL: test_wur_ae_bitsused +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.bitsused(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_bitsused(art); +} + +//--- wur_ae_cbegin0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_cbegin0(int art) { +// CHECK-LABEL: test_wur_ae_cbegin0 +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.cbegin0(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_cbegin0(art); +} + +//--- wur_ae_cend0.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_cend0(int art) { +// CHECK-LABEL: test_wur_ae_cend0 +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.cend0(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_cend0(art); +} + +//--- wur_ae_cw_sd_no.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_cw_sd_no(int art) { +// CHECK-LABEL: test_wur_ae_cw_sd_no +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.cw.sd.no(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_cw_sd_no(art); +} + +//--- wur_ae_cwrap.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_cwrap(int art) { +// CHECK-LABEL: test_wur_ae_cwrap +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.cwrap(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_cwrap(art); +} + +//--- wur_ae_first_ts.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_first_ts(int art) { +// CHECK-LABEL: test_wur_ae_first_ts +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.first.ts(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_first_ts(art); +} + +//--- wur_ae_nextoffset.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_nextoffset(int art) { +// CHECK-LABEL: test_wur_ae_nextoffset +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.nextoffset(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_nextoffset(art); +} + +//--- wur_ae_overflow.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_overflow(int art) { +// CHECK-LABEL: test_wur_ae_overflow +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.overflow(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_overflow(art); +} + +//--- wur_ae_ovf_sar.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_ovf_sar(int art) { +// CHECK-LABEL: test_wur_ae_ovf_sar +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.ovf.sar(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_ovf_sar(art); +} + +//--- wur_ae_sar.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_sar(int art) { +// CHECK-LABEL: test_wur_ae_sar +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.sar(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_sar(art); +} + +//--- wur_ae_searchdone.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_searchdone(int art) { +// CHECK-LABEL: test_wur_ae_searchdone +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.searchdone(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_searchdone(art); +} + +//--- wur_ae_tablesize.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_tablesize(int art) { +// CHECK-LABEL: test_wur_ae_tablesize +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.tablesize(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_tablesize(art); +} + +//--- wur_ae_ts_fts_bu_bp.c + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); +typedef short ae_int16 __attribute__(( vector_size(2))); +typedef short ae_int16x2 __attribute__(( vector_size(4))); +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef long long ae_int64 __attribute__(( vector_size(8))); +typedef unsigned char ae_valign __attribute__(( vector_size(8))); + +typedef int immediate; + +void test_wur_ae_ts_fts_bu_bp(int art) { +// CHECK-LABEL: test_wur_ae_ts_fts_bu_bp +// CHECK: {{(tail)?}} call void @llvm.xtensa.wur.ae.ts.fts.bu.bp(i32 {{.*}}) +// CHECK: ret void + __builtin_xtensa_wur_ae_ts_fts_bu_bp(art); +} + From 5b244704ba83cdb9ba03886ca0a7037f7a3edb7b Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 13:59:58 +0000 Subject: [PATCH 225/261] [Xtensa] Fix xt_lsxp builtin definition --- clang/include/clang/Basic/BuiltinsXtensa.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/BuiltinsXtensa.def b/clang/include/clang/Basic/BuiltinsXtensa.def index b87098d79c4557..01d26ffc6d7625 100644 --- a/clang/include/clang/Basic/BuiltinsXtensa.def +++ b/clang/include/clang/Basic/BuiltinsXtensa.def @@ -203,7 +203,7 @@ BUILTIN(__builtin_xtensa_xt_lsip, "ff**i", "n") // xtfloat __builtin_xtensa___builtin_xtensa_xt_lsx(const xtfloat*,int) BUILTIN(__builtin_xtensa_xt_lsx, "ff*i", "n") -BUILTIN(__builtin_xtensa_xt_lsxp, "ff*i", "n") +BUILTIN(__builtin_xtensa_xt_lsxp, "ff**i", "n") // xtfloat __builtin_xtensa___builtin_xtensa_xt_madd_s(xtfloat,xtfloat,xtfloat) BUILTIN(__builtin_xtensa_xt_madd_s, "ffff", "n") From f2308b0bf179e92df6dcc22759077488274b15bb Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 14:01:04 +0000 Subject: [PATCH 226/261] [Xtensa] Support bool vectors in LLVM calls --- clang/lib/CodeGen/Targets/Xtensa.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/clang/lib/CodeGen/Targets/Xtensa.cpp b/clang/lib/CodeGen/Targets/Xtensa.cpp index 0a824924e4a2b5..b615ce7913526f 100644 --- a/clang/lib/CodeGen/Targets/Xtensa.cpp +++ b/clang/lib/CodeGen/Targets/Xtensa.cpp @@ -11,6 +11,7 @@ using namespace clang; using namespace clang::CodeGen; + //===----------------------------------------------------------------------===// // Xtensa ABI Implementation //===----------------------------------------------------------------------===// @@ -99,9 +100,13 @@ ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty, } // xtbool - if (getTarget().hasFeature("bool") && Size == 1 && Ty->isVectorType()) { + if (getTarget().hasFeature("bool") && Size <= 8 && Ty->isVectorType()) { + // The type size is rounded up to the power of two and at least 8 bits, + // so we need to get the "true" size from num of vector elements + const VectorType *VT = Ty->getAs(); + unsigned NumBits = VT->getNumElements(); llvm::Type *ResType = - llvm::FixedVectorType::get(llvm::Type::getInt1Ty(getVMContext()), 1); + llvm::FixedVectorType::get(llvm::Type::getInt1Ty(getVMContext()), NumBits); return ABIArgInfo::getDirect(ResType); } // Vector arguments From 9245db23ac376a6e04a43691ec4a0b9bd2e19c9a Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 14:03:00 +0000 Subject: [PATCH 227/261] [Xtensa] Add --text-section-literals option This option is passed to GNU AS and makes Xtensa compiler driver compatible with GCC. --- clang/lib/Driver/ToolChains/Xtensa.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp index e7d01eefda6f64..b5f90b4593504a 100644 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ b/clang/lib/Driver/ToolChains/Xtensa.cpp @@ -250,6 +250,9 @@ void tools::xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, if (!A->getOption().matches(options::OPT_g0)) CmdArgs.push_back("-g"); + if (Args.getLastArg(options::OPT_mtext_section_literals)) + CmdArgs.push_back("--text-section-literals"); + if (Args.hasFlag(options::OPT_fverbose_asm, options::OPT_fno_verbose_asm, false)) CmdArgs.push_back("-fverbose-asm"); From 2ea3ef361197a3e057ff27bc3cde5bbd456c8fc2 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Mar 2024 02:38:46 +0300 Subject: [PATCH 228/261] [Xtensa] Add vector conversion builtins Intrinsics: __builtin_xtensa_ae_int32x2 and builtin_xtensa_int32 are convenience functions for easy integer-vector and vector-vector conversions that conform to Xtensa coding style. Xtensa C dialect allows for implicit conversion between wider and narrower vector (via shuffle) and between integer and any vector (via broadcast). Standard Clang vectors do not support this, so these functions provide a handicap for better portability. --- .../clang/Basic/BuiltinsXtensaHIFI.def | 4 +- clang/include/clang/Sema/Sema.h | 2 + clang/lib/CodeGen/CGBuiltin.cpp | 49 +++++++++++++++++++ clang/lib/CodeGen/CodeGenFunction.h | 3 ++ clang/lib/Sema/SemaChecking.cpp | 41 ++++++++++++++++ .../CodeGen/Xtensa/xtensa-hifi-conversions.c | 48 ++++++++++++++++++ 6 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 clang/test/CodeGen/Xtensa/xtensa-hifi-conversions.c diff --git a/clang/include/clang/Basic/BuiltinsXtensaHIFI.def b/clang/include/clang/Basic/BuiltinsXtensaHIFI.def index d0ac10aeab39b0..1ccfb0cdeda15e 100644 --- a/clang/include/clang/Basic/BuiltinsXtensaHIFI.def +++ b/clang/include/clang/Basic/BuiltinsXtensaHIFI.def @@ -2614,4 +2614,6 @@ BUILTIN(__builtin_xtensa_wur_ae_tablesize, "vi", "n") // void __builtin_xtensa_wur_ae_ts_fts_bu_bp(int art) BUILTIN(__builtin_xtensa_wur_ae_ts_fts_bu_bp, "vi", "n") -#undef BUILTIN +// Type conversion builtins +BUILTIN(__builtin_xtensa_ae_int32x2, "V2i.", "nct") +BUILTIN(__builtin_xtensa_ae_int32, "V1i.", "nct") diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 8ea0b9caa669af..04bde0871d3ed2 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -13934,6 +13934,8 @@ class Sema final { bool CheckXtensaBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall); + bool SemaBuiltinXtensaConversion(unsigned BuiltinID, CallExpr *TheCall); + bool SemaBuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall); bool SemaBuiltinVAStartARMMicrosoft(CallExpr *Call); bool SemaBuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID); diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index d1e2c8c273df72..c6cffe83f0e815 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -21370,12 +21370,61 @@ llvm::Value *CodeGenFunction::ConvertXtensaToBc(const Expr *ArgExpr, } return ArgCast; } +llvm::Value * +CodeGenFunction::EmitXtensaConversionExpr(unsigned BuiltinID, const CallExpr *E, + ReturnValueSlot ReturnValue, + llvm::Triple::ArchType Arch) { + unsigned MaxElems; + switch (BuiltinID) { + case Xtensa::BI__builtin_xtensa_ae_int32x2: + MaxElems = 2; + break; + case Xtensa::BI__builtin_xtensa_ae_int32: + MaxElems = 1; + break; + default: + llvm_unreachable("Unknown intrinsic ID"); + } + + Value *ArgVal = EmitScalarExpr(E->getArg(0)); + QualType QT = E->getArg(0)->getType(); + if (auto *VecTy = QT->getAs()) { + unsigned NumEl = VecTy->getNumElements(); + llvm::Type *ElType = ConvertType(VecTy->getElementType()); + if (ElType != Int32Ty || NumEl > MaxElems) { + CGM.Error(E->getExprLoc(), "Expected int32x1 or int32x2"); + return ArgVal; + } + if (NumEl == MaxElems) + return ArgVal; // no-op + int Mask[] = {0,0}; + Value *Result = + Builder.CreateShuffleVector(ArgVal, ArgVal, ArrayRef(Mask, MaxElems)); + return Result; + } else if (QT->isIntegerType()) { + Value *Int32Val = (QT->isSignedIntegerType()) + ? Builder.CreateSExtOrTrunc(ArgVal, Int32Ty, "cast") + : Builder.CreateZExtOrTrunc(ArgVal, Int32Ty, "cast"); + Value *VecOps[] = {Int32Val,Int32Val}; + Value *Result = BuildVector(ArrayRef(VecOps, MaxElems)); + return Result; + } + llvm_unreachable("Invalid Argument type"); +} llvm::Value * CodeGenFunction::EmitXtensaBuiltinExpr(unsigned BuiltinID, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Triple::ArchType Arch) { + switch (BuiltinID) { + case Xtensa::BI__builtin_xtensa_ae_int32x2: + case Xtensa::BI__builtin_xtensa_ae_int32: + return EmitXtensaConversionExpr(BuiltinID, E, ReturnValue, Arch); + default: + break; + }; + XtensaIntrinsicInfo Info = GetXtensaIntrinsic(BuiltinID); unsigned Intrinsic = Info.IntrinsicID; diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index c57f1a0d8ccaef..77e7ccde3604a4 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -4508,6 +4508,9 @@ class CodeGenFunction : public CodeGenTypeCache { llvm::Value *EmitXtensaBuiltinExpr(unsigned BuiltinID, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Triple::ArchType Arch); + llvm::Value *EmitXtensaConversionExpr(unsigned BuiltinID, const CallExpr *E, + ReturnValueSlot ReturnValue, + llvm::Triple::ArchType Arch); //===--------------------------------------------------------------------===// // Expression Emission //===--------------------------------------------------------------------===// diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 565c99b787fe09..193092cce3beef 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -6533,10 +6533,51 @@ bool Sema::CheckXtensaBuiltinFunctionCall(unsigned BuiltinID, SemaBuiltinConstantArgRange(TheCall, 3, 0, 7) && SemaBuiltinConstantArgRange(TheCall, 4, 0, 7) && SemaBuiltinConstantArgRange(TheCall, 5, 0, 7); + case Xtensa::BI__builtin_xtensa_ae_int32x2: + case Xtensa::BI__builtin_xtensa_ae_int32: + return SemaBuiltinXtensaConversion(BuiltinID, TheCall); } return SemaBuiltinConstantArgRange(TheCall, i, l, u); } +bool Sema::SemaBuiltinXtensaConversion(unsigned BuiltinID, CallExpr *TheCall) { + unsigned MaxElems; + switch (BuiltinID) { + case Xtensa::BI__builtin_xtensa_ae_int32x2: + MaxElems = 2; + break; + case Xtensa::BI__builtin_xtensa_ae_int32: + MaxElems = 1; + break; + default: + llvm_unreachable("Unknown intrinsic ID"); + } + if (checkArgCount(*this, TheCall, 1)) + return true; + Expr *Arg = TheCall->getArg(0); + QualType QT = Arg->getType(); + if (auto *VecTy = QT->getAs()) { + unsigned NumEl = VecTy->getNumElements(); + QualType ElType = VecTy->getElementType(); + unsigned ElWidth = Context.getIntWidth(ElType); + QualType VecType = Context.getVectorType(Context.IntTy, MaxElems, + VectorKind::Generic); + if (ElWidth != 32 || NumEl > MaxElems) + return Diag(TheCall->getBeginLoc(), + diag::err_typecheck_convert_incompatible) + << QT << VecType << 1 << 0 << 0; + return false; + } else { + if (!QT->isIntegerType()) + return Diag(TheCall->getBeginLoc(), + diag::err_typecheck_convert_incompatible) + << QT << Context.IntTy << 1 << 0 << 0; + + return false; + } + return false; +} + void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) { const TargetInfo &TI = Context.getTargetInfo(); diff --git a/clang/test/CodeGen/Xtensa/xtensa-hifi-conversions.c b/clang/test/CodeGen/Xtensa/xtensa-hifi-conversions.c new file mode 100644 index 00000000000000..506e785717e6db --- /dev/null +++ b/clang/test/CodeGen/Xtensa/xtensa-hifi-conversions.c @@ -0,0 +1,48 @@ +// RUN: split-file %s %t +// RUN: %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/correct.c | FileCheck %t/correct.c +// RUN: not %clang -target xtensa -mcpu=cnl -S -emit-llvm -O1 -o - %t/bad_vec.c 2>&1 | FileCheck %t/bad_vec.c + +//--- correct.c + +typedef int ae_int32 __attribute__(( vector_size(4))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); + +ae_int32x2 test_ae_int32x2_from_int(int a) { +// CHECK-LABEL: @test_ae_int32x2_from_int(i +// CHECK: %[[INS:.*]] = insertelement <2 x i32> poison, i32 %{{.*}}, i64 0 +// CHECK: %[[SHUF:.*]] = shufflevector <2 x i32> %[[INS]], <2 x i32> poison, <2 x i32> zeroinitializer +// CHECK: ret <2 x i32> %[[SHUF]] +return __builtin_xtensa_ae_int32x2(a); +} + +ae_int32x2 test_ae_int32x2_from_ae_int32(ae_int32 a) { +// CHECK-LABEL: @test_ae_int32x2_from_ae_int32( +// CHECK: %[[SHUF:.*]] = shufflevector <1 x i32> %{{.*}}, <1 x i32> poison, <2 x i32> zeroinitializer +// CHECK: ret <2 x i32> %[[SHUF]] +return __builtin_xtensa_ae_int32x2(a); +} + +ae_int32x2 test_ae_int32x2_from_ae_int32x2(ae_int32x2 a) { +// CHECK: {{.*}}<2 x i32> @test_ae_int32x2_from_ae_int32x2(<2 x i32>{{.*}} %[[A:.*]]) +// CHECK: ret <2 x i32> %[[A]] +return __builtin_xtensa_ae_int32x2(a); +} + +ae_int32x2 test_ae_int32x2_from_short(short a) { +// CHECK-LABEL: @test_ae_int32x2_from_short( +// CHECK: %[[SEXT:.*]] = sext i16 %{{.*}} to i32 +// CHECK: %[[INS:.*]] = insertelement <2 x i32> poison, i32 %[[SEXT]], i64 0 +// CHECK: %[[SHUF:.*]] = shufflevector <2 x i32> %[[INS]], <2 x i32> poison, <2 x i32> zeroinitializer +// CHECK: ret <2 x i32> %[[SHUF]] +return __builtin_xtensa_ae_int32x2(a); +} + +//--- bad_vec.c + +typedef short ae_int16x4 __attribute__(( vector_size(8))); +typedef int ae_int32x2 __attribute__(( vector_size(8))); + +ae_int32x2 test_ae_int32x2_from_bad_vec(ae_int16x4 a) { +// CHECK: error: passing 'ae_int16x4' {{.*}} to parameter of incompatible type +return __builtin_xtensa_ae_int32x2(a); +} From 6d4e6205b1ef408c9101b2949880489ee702a44d Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Thu, 29 Jun 2023 14:04:46 +0000 Subject: [PATCH 229/261] [Xtensa] Add HIFI3 C types and intrinsics --- clang/lib/Headers/CMakeLists.txt | 15 +- clang/lib/Headers/xtensa_defs.h | 66 + clang/lib/Headers/xtensa_protos.h | 6894 +++++++++++++++++++++++++++++ 3 files changed, 6974 insertions(+), 1 deletion(-) create mode 100644 clang/lib/Headers/xtensa_defs.h create mode 100644 clang/lib/Headers/xtensa_protos.h diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt index b9a966be73ee97..d305ad9a737086 100644 --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -252,6 +252,11 @@ set(x86_files cpuid.h ) +set(xtensa_files + xtensa_defs.h + xtensa_protos.h +) + set(windows_only_files intrin.h vadefs.h @@ -278,6 +283,7 @@ set(files ${systemz_files} ${ve_files} ${x86_files} + ${xtensa_files} ${webassembly_files} ${windows_only_files} ${utility_files} @@ -488,6 +494,7 @@ add_header_target("systemz-resource-headers" "${systemz_files}") add_header_target("ve-resource-headers" "${ve_files}") add_header_target("webassembly-resource-headers" "${webassembly_files}") add_header_target("x86-resource-headers" "${x86_files}") +add_header_target("xtensa-resource-headers" "${xtensa_files}") # Other header groupings add_header_target("hlsl-resource-headers" ${hlsl_files}) @@ -658,7 +665,13 @@ if(NOT CLANG_ENABLE_HLSL) endif() install( - FILES ${hlsl_h} + FILES ${xtensa_files} + DESTINATION ${header_install_dir} + EXCLUDE_FROM_ALL + COMPONENT xtensa-resource-headers) + +install( + FILES ${hlsl_files} DESTINATION ${header_install_dir} ${EXCLUDE_HLSL} COMPONENT hlsl-resource-headers) diff --git a/clang/lib/Headers/xtensa_defs.h b/clang/lib/Headers/xtensa_defs.h new file mode 100644 index 00000000000000..d47cacf71803b0 --- /dev/null +++ b/clang/lib/Headers/xtensa_defs.h @@ -0,0 +1,66 @@ +/*===---- xtensa_defs.h - Xtensa definitions -------------------------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ +#ifndef __XTENSAHIFI3_H +#define __XTENSAHIFI3_H + +typedef __attribute__((ext_vector_type(1))) _Bool xtbool; +typedef __attribute__((ext_vector_type(2))) _Bool xtbool2; +typedef __attribute__((ext_vector_type(4))) _Bool xtbool4; + +typedef int ae_int32 __attribute__((vector_size(4))); +typedef int ae_int32x2 __attribute__((vector_size(8))); +typedef short ae_int16 __attribute__((vector_size(2))); +typedef short ae_int16x2 __attribute__((vector_size(4))); +typedef short ae_int16x4 __attribute__((vector_size(8))); +typedef long long ae_int64 __attribute__((vector_size(8))); +typedef unsigned char ae_valign __attribute__((vector_size(8))); +typedef ae_int16x4 ae_f16x4; +typedef ae_int32x2 ae_f32x2; +typedef ae_int32 ae_f32; +typedef ae_int64 ae_f64; +typedef ae_int32 ae_f24; +typedef ae_int32x2 ae_f24x2; +typedef ae_int16 ae_f16; + +#include + +#define AE_SETCBEGIN0(x) WUR_AE_CBEGIN0(x) +#define AE_SETCEND0(x) WUR_AE_CEND0(x) +#define AE_ZERO64(x) AE_MOVI(0) +#define AE_ZERO24(x) AE_MOVI(0) +#define AE_ZERO32(x) AE_MOVI(0) +#define AE_ZERO16(x) AE_MOVI(0) +#define AE_ZEROQ56(x) AE_ZERO64(x) + +#define AE_SEL32_L(a) \ + ({ \ + ae_int32x2 _a = a; \ + __builtin_shufflevector(_a, _a, 0); \ + }) + +#define AE_INT32(a) __builtin_xtensa_ae_int32(a); +#define AE_INT32X2(a) __builtin_xtensa_ae_int32x2(a); + +#define AE_F32X2 AE_INT32X2 +#define AE_F32 AE_INT32 + +#define AE_MOVINT16X4_FROMINT32X2(a) ((ae_int32x2)(a)) + +#define AE_F32_ADDS_F32(s1, s2) \ + AE_F32(AE_ADD32S(AE_INT32X2(s1), AE_INT32X2(s2))) + +typedef float xtfloat; + +#define XT_xtfloat_storeip(x, a, i) ({ a = __builtin_xtensa_xt_ssip(x, a, i); }) +#define XT_xtfloat_loadip(x, a, i) \ + ({ x = __builtin_xtensa_xt_lsip((xtfloat **)&a, i); }) +#define XT_xtfloat_loadxp(x, a, i) \ + ({ x = __builtin_xtensa_xt_lsxp((xtfloat **)&a, i); }) + +#endif /* __XTENSAHIFI3_H */ \ No newline at end of file diff --git a/clang/lib/Headers/xtensa_protos.h b/clang/lib/Headers/xtensa_protos.h new file mode 100644 index 00000000000000..0cc75cc8431abe --- /dev/null +++ b/clang/lib/Headers/xtensa_protos.h @@ -0,0 +1,6894 @@ + +/*===---- xtensa_protos.h - Xtensa intrinsics -------------------------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ +#ifndef __XTENSAHIFI3INTRIN_H +#define __XTENSAHIFI3INTRIN_H + +#define AE_ABS16S(ae_arth_v1) \ + ({ \ + ae_int16x4 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_abs16s((__ae_arth_v1)); \ + }) + +#define AE_ABS24S(ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_abs24s((__ae_arth_v1)); \ + }) + +#define AE_ABS32(ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_abs32((__ae_arth_v1)); \ + }) + +#define AE_ABS32S(ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_abs32s((__ae_arth_v1)); \ + }) + +#define AE_ABS64(ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_abs64((__ae_arth_v1)); \ + }) + +#define AE_ABS64S(ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_abs64s((__ae_arth_v1)); \ + }) + +#define AE_ADD16(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int16x4 __ae_arth_v0 = (ae_arth_v0); \ + ae_int16x4 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_add16((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADD16S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int16x4 __ae_arth_v0 = (ae_arth_v0); \ + ae_int16x4 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_add16s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADD24S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_add24s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADD32(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_add32((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADD32_HL_LH(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_add32_hl_lh((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADD32S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_add32s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADD64(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_add64((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADD64S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_add64s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADDBRBA32(art, ars) \ + ({ \ + int __art = (int)(art); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_addbrba32((__art), (__ars)); \ + }) + +#define AE_ADDSUB32(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_addsub32((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ADDSUB32S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_addsub32s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_AND(ae_dr_to_dr_v0, ae_dr_to_dr_v1) \ + ({ \ + ae_int64 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + ae_int64 __ae_dr_to_dr_v1 = (ae_dr_to_dr_v1); \ + __builtin_xtensa_ae_and((__ae_dr_to_dr_v0), (__ae_dr_to_dr_v1)); \ + }) + +#define AE_CVT32X2F16_10(ae_to_dr_v0) \ + ({ \ + ae_int16x4 __ae_to_dr_v0 = (ae_to_dr_v0); \ + __builtin_xtensa_ae_cvt32x2f16_10((__ae_to_dr_v0)); \ + }) + +#define AE_CVT32X2F16_32(ae_to_dr_v0) \ + ({ \ + ae_int16x4 __ae_to_dr_v0 = (ae_to_dr_v0); \ + __builtin_xtensa_ae_cvt32x2f16_32((__ae_to_dr_v0)); \ + }) + +#define AE_CVT48A32(ars) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_cvt48a32((__ars)); \ + }) + +#define AE_CVT64A32(ars) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_cvt64a32((__ars)); \ + }) + +#define AE_CVT64F32_H(ae_dr_to_dr_v0) \ + ({ \ + ae_int32x2 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + __builtin_xtensa_ae_cvt64f32_h((__ae_dr_to_dr_v0)); \ + }) + +#define AE_CVTA32F24S_H(ae_dr_to_ar_v0) \ + ({ \ + ae_int32x2 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_cvta32f24s_h((__ae_dr_to_ar_v0)); \ + }) + +#define AE_CVTA32F24S_L(ae_dr_to_ar_v0) \ + ({ \ + ae_int32x2 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_cvta32f24s_l((__ae_dr_to_ar_v0)); \ + }) + +#define AE_CVTQ56A32S(ars) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_cvtq56a32s((__ars)); \ + }) + +#define AE_CVTQ56P32S_H(ae_dr_to_dr_v0) \ + ({ \ + ae_int32x2 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + __builtin_xtensa_ae_cvtq56p32s_h((__ae_dr_to_dr_v0)); \ + }) + +#define AE_CVTQ56P32S_L(ae_dr_to_dr_v0) \ + ({ \ + ae_int32x2 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + __builtin_xtensa_ae_cvtq56p32s_l((__ae_dr_to_dr_v0)); \ + }) + +#define AE_DB(ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_db((const short **)&(ars), (__art)); \ + }) + +#define AE_DB_IC(ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_db_ic((const short **)&(ars), (__art)); \ + }) + +#define AE_DB_IP(ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_db_ip((const short **)&(ars), (__art)); \ + }) + +#define AE_DBI(ars, ae_ohba) \ + ({ __builtin_xtensa_ae_dbi((const short **)&(ars), (ae_ohba)); }) + +#define AE_DBI_IC(ars, ae_ohba) \ + ({ __builtin_xtensa_ae_dbi_ic((const short **)&(ars), (ae_ohba)); }) + +#define AE_DBI_IP(ars, ae_ohba) \ + ({ __builtin_xtensa_ae_dbi_ip((const short **)&(ars), (ae_ohba)); }) + +#define AE_DIV64D32_H(ae_arth_v, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_div64d32_h((ae_int64 *)&(ae_arth_v), (__ae_arth_v1)); \ + }) + +#define AE_DIV64D32_L(ae_arth_v, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_div64d32_l((ae_int64 *)&(ae_arth_v), (__ae_arth_v1)); \ + }) + +#define AE_EQ16(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int16x4 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int16x4 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_eq16((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_EQ32(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int32x2 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int32x2 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_eq32((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_EQ64(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int64 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int64 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_eq64((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_L16_I(ars, ae_immls16) \ + ({ \ + ae_int16 *__ars = (ars); \ + __builtin_xtensa_ae_l16_i((__ars), (ae_immls16)); \ + }) + +#define AE_L16_IP(ae_ls_v, ars, ae_immls16) \ + ({ \ + __builtin_xtensa_ae_l16_ip((ae_int16x4 *)&(ae_ls_v), \ + (const ae_int16 **)&(ars), (ae_immls16)); \ + }) + +#define AE_L16_X(ars, art) \ + ({ \ + ae_int16 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16_x((__ars), (__art)); \ + }) + +#define AE_L16_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16_xc((ae_int16x4 *)&(ae_ls_v), \ + (const ae_int16 **)&(ars), (__art)); \ + }) + +#define AE_L16_XP(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16_xp((ae_int16x4 *)&(ae_ls_v), \ + (const ae_int16 **)&(ars), (__art)); \ + }) + +#define AE_L16M_I(ars, ae_immls16) \ + ({ \ + ae_int16 *__ars = (ars); \ + __builtin_xtensa_ae_l16m_i((__ars), (ae_immls16)); \ + }) + +#define AE_L16M_IU(ae_ls_v, ars, ae_immls16) \ + ({ \ + __builtin_xtensa_ae_l16m_iu((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int16 **)&(ars), (ae_immls16)); \ + }) + +#define AE_L16M_X(ars, art) \ + ({ \ + ae_int16 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16m_x((__ars), (__art)); \ + }) + +#define AE_L16M_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16m_xc((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int16 **)&(ars), (__art)); \ + }) + +#define AE_L16M_XU(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16m_xu((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int16 **)&(ars), (__art)); \ + }) + +#define AE_L16X2M_I(ars, ae_immls32) \ + ({ \ + ae_int16x2 *__ars = (ars); \ + __builtin_xtensa_ae_l16x2m_i((__ars), (ae_immls32)); \ + }) + +#define AE_L16X2M_IU(ae_ls_v, ars, ae_immls32) \ + ({ \ + __builtin_xtensa_ae_l16x2m_iu((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int16x2 **)&(ars), (ae_immls32)); \ + }) + +#define AE_L16X2M_X(ars, art) \ + ({ \ + ae_int16x2 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16x2m_x((__ars), (__art)); \ + }) + +#define AE_L16X2M_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16x2m_xc((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int16x2 **)&(ars), (__art)); \ + }) + +#define AE_L16X2M_XU(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16x2m_xu((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int16x2 **)&(ars), (__art)); \ + }) + +#define AE_L16X4_I(ars, ae_immls64) \ + ({ \ + ae_int16x4 *__ars = (ars); \ + __builtin_xtensa_ae_l16x4_i((__ars), (ae_immls64)); \ + }) + +#define AE_L16X4_IP(ae_ls_v, ars, ae_immls64pos) \ + ({ \ + __builtin_xtensa_ae_l16x4_ip((ae_int16x4 *)&(ae_ls_v), \ + (const ae_int16x4 **)&(ars), \ + (ae_immls64pos)); \ + }) + +#define AE_L16X4_RIC(ae_ls_v, ars) \ + ({ \ + __builtin_xtensa_ae_l16x4_ric((ae_int16x4 *)&(ae_ls_v), \ + (const ae_int16x4 **)&(ars)); \ + }) + +#define AE_L16X4_RIP(ae_ls_v, ars) \ + ({ \ + __builtin_xtensa_ae_l16x4_rip((ae_int16x4 *)&(ae_ls_v), \ + (const ae_int16x4 **)&(ars)); \ + }) + +#define AE_L16X4_X(ars, art) \ + ({ \ + ae_int16x4 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16x4_x((__ars), (__art)); \ + }) + +#define AE_L16X4_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16x4_xc((ae_int16x4 *)&(ae_ls_v), \ + (const ae_int16x4 **)&(ars), (__art)); \ + }) + +#define AE_L16X4_XP(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l16x4_xp((ae_int16x4 *)&(ae_ls_v), \ + (const ae_int16x4 **)&(ars), (__art)); \ + }) + +#define AE_L32_I(ars, ae_immls32) \ + ({ \ + ae_int32 *__ars = (ars); \ + __builtin_xtensa_ae_l32_i((__ars), (ae_immls32)); \ + }) + +#define AE_L32_IP(ae_ls_v, ars, ae_immls32) \ + ({ \ + __builtin_xtensa_ae_l32_ip((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (ae_immls32)); \ + }) + +#define AE_L32_X(ars, art) \ + ({ \ + ae_int32 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32_x((__ars), (__art)); \ + }) + +#define AE_L32_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32_xc((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_L32_XP(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32_xp((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_L32F24_I(ars, ae_immls32) \ + ({ \ + ae_int32 *__ars = (ars); \ + __builtin_xtensa_ae_l32f24_i((__ars), (ae_immls32)); \ + }) + +#define AE_L32F24_IP(ae_ls_v, ars, ae_immls32) \ + ({ \ + __builtin_xtensa_ae_l32f24_ip((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (ae_immls32)); \ + }) + +#define AE_L32F24_X(ars, art) \ + ({ \ + ae_int32 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32f24_x((__ars), (__art)); \ + }) + +#define AE_L32F24_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32f24_xc((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_L32F24_XP(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32f24_xp((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_L32M_I(ars, ae_immls32) \ + ({ \ + ae_int32 *__ars = (ars); \ + __builtin_xtensa_ae_l32m_i((__ars), (ae_immls32)); \ + }) + +#define AE_L32M_IU(ae_ls_v, ars, ae_immls32) \ + ({ \ + __builtin_xtensa_ae_l32m_iu((ae_int64 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (ae_immls32)); \ + }) + +#define AE_L32M_X(ars, art) \ + ({ \ + ae_int32 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32m_x((__ars), (__art)); \ + }) + +#define AE_L32M_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32m_xc((ae_int64 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_L32M_XU(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32m_xu((ae_int64 *)&(ae_ls_v), \ + (const ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_L32X2_I(ars, ae_immls64) \ + ({ \ + ae_int32x2 *__ars = (ars); \ + __builtin_xtensa_ae_l32x2_i((__ars), (ae_immls64)); \ + }) + +#define AE_L32X2_IP(ae_ls_v, ars, ae_immls64pos) \ + ({ \ + __builtin_xtensa_ae_l32x2_ip((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars), \ + (ae_immls64pos)); \ + }) + +#define AE_L32X2_RIC(ae_ls_v, ars) \ + ({ \ + __builtin_xtensa_ae_l32x2_ric((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_L32X2_RIP(ae_ls_v, ars) \ + ({ \ + __builtin_xtensa_ae_l32x2_rip((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_L32X2_X(ars, art) \ + ({ \ + ae_int32x2 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32x2_x((__ars), (__art)); \ + }) + +#define AE_L32X2_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32x2_xc((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars), (__art)); \ + }) + +#define AE_L32X2_XP(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32x2_xp((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars), (__art)); \ + }) + +#define AE_L32X2F24_I(ars, ae_immls64) \ + ({ \ + ae_int32x2 *__ars = (ars); \ + __builtin_xtensa_ae_l32x2f24_i((__ars), (ae_immls64)); \ + }) + +#define AE_L32X2F24_IP(ae_ls_v, ars, ae_immls64pos) \ + ({ \ + __builtin_xtensa_ae_l32x2f24_ip((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars), \ + (ae_immls64pos)); \ + }) + +#define AE_L32X2F24_RIC(ae_ls_v, ars) \ + ({ \ + __builtin_xtensa_ae_l32x2f24_ric((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_L32X2F24_RIP(ae_ls_v, ars) \ + ({ \ + __builtin_xtensa_ae_l32x2f24_rip((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_L32X2F24_X(ars, art) \ + ({ \ + ae_int32x2 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32x2f24_x((__ars), (__art)); \ + }) + +#define AE_L32X2F24_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32x2f24_xc((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars), (__art)); \ + }) + +#define AE_L32X2F24_XP(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l32x2f24_xp((ae_int32x2 *)&(ae_ls_v), \ + (const ae_int32x2 **)&(ars), (__art)); \ + }) + +#define AE_L64_I(ars, ae_immls64) \ + ({ \ + ae_int64 *__ars = (ars); \ + __builtin_xtensa_ae_l64_i((__ars), (ae_immls64)); \ + }) + +#define AE_L64_IP(ae_ls_v, ars, ae_immls64) \ + ({ \ + __builtin_xtensa_ae_l64_ip((ae_int64 *)&(ae_ls_v), \ + (const ae_int64 **)&(ars), (ae_immls64)); \ + }) + +#define AE_L64_X(ars, art) \ + ({ \ + ae_int64 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l64_x((__ars), (__art)); \ + }) + +#define AE_L64_XC(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l64_xc((ae_int64 *)&(ae_ls_v), \ + (const ae_int64 **)&(ars), (__art)); \ + }) + +#define AE_L64_XP(ae_ls_v, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_l64_xp((ae_int64 *)&(ae_ls_v), \ + (const ae_int64 **)&(ars), (__art)); \ + }) + +#define AE_LA16X4_IC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la16x4_ic((ae_int16x4 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int16x4 **)&(ars)); \ + }) + +#define AE_LA16X4_IP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la16x4_ip((ae_int16x4 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int16x4 **)&(ars)); \ + }) + +#define AE_LA16X4_RIC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la16x4_ric((ae_int16x4 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int16x4 **)&(ars)); \ + }) + +#define AE_LA16X4_RIP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la16x4_rip((ae_int16x4 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int16x4 **)&(ars)); \ + }) + +#define AE_LA16X4NEG_PC(ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la16x4neg_pc((ae_valign *)&(ae_ls_uu), \ + (const ae_int16x4 **)&(ars)); \ + }) + +#define AE_LA16X4POS_PC(ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la16x4pos_pc((ae_valign *)&(ae_ls_uu), \ + (const ae_int16x4 **)&(ars)); \ + }) + +#define AE_LA24_IC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24_ic((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24_IP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24_ip((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24_RIC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24_ric((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24_RIP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24_rip((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24NEG_PC(ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24neg_pc((ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24POS_PC(ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24pos_pc((ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24X2_IC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24x2_ic((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24X2_IP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24x2_ip((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24X2_RIC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24x2_ric((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24X2_RIP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24x2_rip((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24X2NEG_PC(ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24x2neg_pc((ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA24X2POS_PC(ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la24x2pos_pc((ae_valign *)&(ae_ls_uu), \ + (const void **)&(ars)); \ + }) + +#define AE_LA32X2_IC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2_ic((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2_IP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2_ip((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2_RIC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2_ric((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2_RIP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2_rip((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2F24_IC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2f24_ic((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2F24_IP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2f24_ip((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2F24_RIC(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2f24_ric((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2F24_RIP(ae_ls_av, ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2f24_rip((ae_int32x2 *)&(ae_ls_av), \ + (ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2NEG_PC(ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2neg_pc((ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA32X2POS_PC(ae_ls_uu, ars) \ + ({ \ + __builtin_xtensa_ae_la32x2pos_pc((ae_valign *)&(ae_ls_uu), \ + (const ae_int32x2 **)&(ars)); \ + }) + +#define AE_LA64_PP(ars) \ + ({ \ + void *__ars = (void *)(ars); \ + __builtin_xtensa_ae_la64_pp((__ars)); \ + }) + +#define AE_LALIGN64_I(ars, ae_immls64) \ + ({ \ + ae_valign *__ars = (ars); \ + __builtin_xtensa_ae_lalign64_i((__ars), (ae_immls64)); \ + }) + +#define AE_LB(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_lb((__art)); \ + }) + +#define AE_LBI(ae_ohba) ({ __builtin_xtensa_ae_lbi((ae_ohba)); }) + +#define AE_LBK(ars, art) \ + ({ \ + int __ars = (int)(ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_lbk((__ars), (__art)); \ + }) + +#define AE_LBKI(ars, ae_ohba) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_lbki((__ars), (ae_ohba)); \ + }) + +#define AE_LBS(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_lbs((__art)); \ + }) + +#define AE_LBSI(ae_ohba) ({ __builtin_xtensa_ae_lbsi((ae_ohba)); }) + +#define AE_LE16(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int16x4 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int16x4 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_le16((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_LE32(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int32x2 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int32x2 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_le32((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_LE64(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int64 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int64 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_le64((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_LT16(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int16x4 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int16x4 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_lt16((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_LT32(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int32x2 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int32x2 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_lt32((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_LT64(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int64 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int64 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_lt64((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MAX32(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int32x2 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int32x2 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_max32((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MAX64(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int64 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int64 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_max64((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MAXABS32S(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int32x2 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int32x2 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_maxabs32s((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MAXABS64S(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int64 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int64 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_maxabs64s((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MIN32(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int32x2 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int32x2 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_min32((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MIN64(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int64 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int64 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_min64((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MINABS32S(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int32x2 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int32x2 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_minabs32s((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MINABS64S(ae_cmpp_v0, ae_cmpp_v1) \ + ({ \ + ae_int64 __ae_cmpp_v0 = (ae_cmpp_v0); \ + ae_int64 __ae_cmpp_v1 = (ae_cmpp_v1); \ + __builtin_xtensa_ae_minabs64s((__ae_cmpp_v0), (__ae_cmpp_v1)); \ + }) + +#define AE_MOV(ae_to_dr_v0) \ + ({ \ + ae_int64 __ae_to_dr_v0 = (ae_to_dr_v0); \ + __builtin_xtensa_ae_mov((__ae_to_dr_v0)); \ + }) + +#define AE_MOVAD16_0(ae_dr_to_ar_v0) \ + ({ \ + ae_int16x4 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_movad16_0((__ae_dr_to_ar_v0)); \ + }) + +#define AE_MOVAD16_1(ae_dr_to_ar_v0) \ + ({ \ + ae_int16x4 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_movad16_1((__ae_dr_to_ar_v0)); \ + }) + +#define AE_MOVAD16_2(ae_dr_to_ar_v0) \ + ({ \ + ae_int16x4 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_movad16_2((__ae_dr_to_ar_v0)); \ + }) + +#define AE_MOVAD16_3(ae_dr_to_ar_v0) \ + ({ \ + ae_int16x4 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_movad16_3((__ae_dr_to_ar_v0)); \ + }) + +#define AE_MOVAD32_H(ae_dr_to_ar_v0) \ + ({ \ + ae_int32x2 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_movad32_h((__ae_dr_to_ar_v0)); \ + }) + +#define AE_MOVAD32_L(ae_dr_to_ar_v0) \ + ({ \ + ae_int32x2 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_movad32_l((__ae_dr_to_ar_v0)); \ + }) + +#define AE_MOVALIGN(ae_uu_v) \ + ({ \ + ae_valign __ae_uu_v = (ae_uu_v); \ + __builtin_xtensa_ae_movalign((__ae_uu_v)); \ + }) + +#define AE_MOVDA16(ars) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_movda16((__ars)); \ + }) + +#define AE_MOVDA16X2(ars, art) \ + ({ \ + int __ars = (int)(ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_movda16x2((__ars), (__art)); \ + }) + +#define AE_MOVDA32(ars) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_movda32((__ars)); \ + }) + +#define AE_MOVDA32X2(ars, art) \ + ({ \ + int __ars = (int)(ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_movda32x2((__ars), (__art)); \ + }) + +#define AE_MOVF16X4(ae_cmov_v, ae_cmov_v0, bt4) \ + ({ \ + ae_int16x4 __ae_cmov_v0 = (ae_cmov_v0); \ + xtbool4 __bt4 = (bt4); \ + __builtin_xtensa_ae_movf16x4((ae_int16x4 *)&(ae_cmov_v), (__ae_cmov_v0), \ + (__bt4)); \ + }) + +#define AE_MOVF32X2(ae_cmov_v, ae_cmov_v0, bt2) \ + ({ \ + ae_int32x2 __ae_cmov_v0 = (ae_cmov_v0); \ + xtbool2 __bt2 = (bt2); \ + __builtin_xtensa_ae_movf32x2((ae_int32x2 *)&(ae_cmov_v), (__ae_cmov_v0), \ + (__bt2)); \ + }) + +#define AE_MOVF64(ae_cmov_v, ae_cmov_v0, bt) \ + ({ \ + ae_int64 __ae_cmov_v0 = (ae_cmov_v0); \ + xtbool __bt = (bt); \ + __builtin_xtensa_ae_movf64((ae_int64 *)&(ae_cmov_v), (__ae_cmov_v0), \ + (__bt)); \ + }) + +#define AE_MOVI(movi_imm) ({ __builtin_xtensa_ae_movi((movi_imm)); }) + +#define AE_MOVT16X4(ae_cmov_v, ae_cmov_v0, bt4) \ + ({ \ + ae_int16x4 __ae_cmov_v0 = (ae_cmov_v0); \ + xtbool4 __bt4 = (bt4); \ + __builtin_xtensa_ae_movt16x4((ae_int16x4 *)&(ae_cmov_v), (__ae_cmov_v0), \ + (__bt4)); \ + }) + +#define AE_MOVT32X2(ae_cmov_v, ae_cmov_v0, bt2) \ + ({ \ + ae_int32x2 __ae_cmov_v0 = (ae_cmov_v0); \ + xtbool2 __bt2 = (bt2); \ + __builtin_xtensa_ae_movt32x2((ae_int32x2 *)&(ae_cmov_v), (__ae_cmov_v0), \ + (__bt2)); \ + }) + +#define AE_MOVT64(ae_cmov_v, ae_cmov_v0, bt) \ + ({ \ + ae_int64 __ae_cmov_v0 = (ae_cmov_v0); \ + xtbool __bt = (bt); \ + __builtin_xtensa_ae_movt64((ae_int64 *)&(ae_cmov_v), (__ae_cmov_v0), \ + (__bt)); \ + }) + +#define AE_MUL16X4(ae_mul_d1, ae_mul_d0) \ + ({ \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + __builtin_xtensa_ae_mul16x4((__ae_mul_d1), (__ae_mul_d0)); \ + }) + +#define AE_MUL32_HH(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32_hh((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32_LH(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32_lh((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32_LL(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32_ll((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32_ll_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MUL32U_LL(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32u_ll((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_H0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32x16_h0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_H0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32x16_h0_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MUL32X16_H1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32x16_h1((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_H1_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32x16_h1_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MUL32X16_H2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32x16_h2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_H2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32x16_h2_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MUL32X16_H3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32x16_h3((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_H3_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32x16_h3_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MUL32X16_L0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32x16_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32x16_l0_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MUL32X16_L1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32x16_l1((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_L1_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32x16_l1_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MUL32X16_L2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32x16_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32x16_l2_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MUL32X16_L3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mul32x16_l3((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MUL32X16_L3_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mul32x16_l3_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA16X4(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0) \ + ({ \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + __builtin_xtensa_ae_mula16x4((ae_int32x2 *)&(ae_mul_q1), \ + (ae_int32x2 *)&(ae_mul_q0), (__ae_mul_d1), \ + (__ae_mul_d0)); \ + }) + +#define AE_MULA32_HH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32_hh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32_LH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32_lh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32_LL(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32_ll((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32_ll_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA32U_LL(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32u_ll((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_H0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32x16_h0((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_H0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32x16_h0_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA32X16_H1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32x16_h1((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_H1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32x16_h1_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA32X16_H2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32x16_h2((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_H2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32x16_h2_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA32X16_H3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32x16_h3((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_H3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32x16_h3_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA32X16_L0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32x16_l0((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32x16_l0_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA32X16_L1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32x16_l1((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_L1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32x16_l1_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA32X16_L2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32x16_l2((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32x16_l2_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULA32X16_L3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mula32x16_l3((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULA32X16_L3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mula32x16_l3_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAD24_HH_LL(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaad24_hh_ll((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAAD24_HH_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaad24_hh_ll_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAD24_HL_LH(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaad24_hl_lh((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAAD24_HL_LH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaad24_hl_lh_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAD32X16_H0_L1(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaad32x16_h0_l1( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAD32X16_H0_L1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaad32x16_h0_l1_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaad32x16_h1_l0( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAD32X16_H1_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaad32x16_h1_l0_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAD32X16_H2_L3(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaad32x16_h2_l3( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAD32X16_H2_L3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaad32x16_h2_l3_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaad32x16_h3_l2( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAD32X16_H3_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaad32x16_h3_l2_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD16SS_11_00(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaafd16ss_11_00( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAFD16SS_11_00_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd16ss_11_00_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD16SS_13_02(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaafd16ss_13_02( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAFD16SS_13_02_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd16ss_13_02_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD16SS_33_22(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaafd16ss_33_22( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAFD16SS_33_22_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd16ss_33_22_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD24_HH_LL(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaafd24_hh_ll((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAAFD24_HH_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd24_hh_ll_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD24_HL_LH(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaafd24_hl_lh((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAAFD24_HL_LH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd24_hl_lh_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD32X16_H0_L1(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaafd32x16_h0_l1( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAFD32X16_H0_L1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd32x16_h0_l1_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaafd32x16_h1_l0( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAFD32X16_H1_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd32x16_h1_l0_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD32X16_H2_L3(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaafd32x16_h2_l3( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAFD32X16_H2_L3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd32x16_h2_l3_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAAFD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaafd32x16_h3_l2( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAAFD32X16_H3_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaafd32x16_h3_l2_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAC24(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulac24((ae_int32x2 *)&(ae_mul_q0), (__ae_mul_d0), \ + (__ae_mul_d1)); \ + }) + +#define AE_MULAC32X16_H(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, \ + opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulac32x16_h((ae_int32x2 *)&(opnd_ae_sem_mul_x4_q0), \ + (__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULAC32X16_L(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, \ + opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulac32x16_l((ae_int32x2 *)&(opnd_ae_sem_mul_x4_q0), \ + (__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULAF16SS_00(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf16ss_00( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF16SS_00_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf16ss_00_s2((ae_int32x2 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF16SS_10(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_10((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16SS_11(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_11((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16SS_20(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_20((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16SS_21(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_21((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16SS_22(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_22((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16SS_30(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_30((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16SS_31(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_31((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16SS_32(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_32((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16SS_33(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulaf16ss_33((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULAF16X4SS(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0) \ + ({ \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + __builtin_xtensa_ae_mulaf16x4ss((ae_int32x2 *)&(ae_mul_q1), \ + (ae_int32x2 *)&(ae_mul_q0), (__ae_mul_d1), \ + (__ae_mul_d0)); \ + }) + +#define AE_MULAF32R_HH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32r_hh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32R_LH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32r_lh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32R_LL(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32r_ll((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32R_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32r_ll_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32S_HH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32s_hh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32S_LH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32s_lh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32S_LL(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32s_ll((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32S_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32s_ll_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32X16_H0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32x16_h0((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32X16_H0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32x16_h0_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32X16_H1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32x16_h1((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32X16_H1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32x16_h1_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32X16_H2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32x16_h2((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32X16_H2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32x16_h2_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32X16_H3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32x16_h3((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32X16_H3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32x16_h3_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32X16_L0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32x16_l0((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32X16_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32x16_l0_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32X16_L1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32x16_l1((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32X16_L1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32x16_l1_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32X16_L2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32x16_l2((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32X16_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32x16_l2_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF32X16_L3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf32x16_l3((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF32X16_L3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf32x16_l3_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF48Q32SP16S_L(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int64 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf48q32sp16s_l( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF48Q32SP16S_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf48q32sp16s_l_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAF48Q32SP16U_L(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int64 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulaf48q32sp16u_l( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAF48Q32SP16U_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaf48q32sp16u_l_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAFC24RA(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, \ + opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulafc24ra((ae_int32x2 *)&(opnd_ae_sem_mul_x4_q0), \ + (__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULAFC32X16RAS_H(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, \ + opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulafc32x16ras_h( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x4_q0), (__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULAFC32X16RAS_L(opnd_ae_sem_mul_x4_q0, opnd_ae_sem_mul_x4_d0, \ + opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulafc32x16ras_l( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x4_q0), (__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULAFD24X2_FIR_H(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, \ + ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int32x2 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulafd24x2_fir_h( \ + (ae_int64 *)&(ae_mul_q0), (ae_int64 *)&(ae_mul_q1), (__ae_mul_d0), \ + (__ae_mul_d1), (__ae_mul_d2)); \ + }) + +#define AE_MULAFD24X2_FIR_L(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, \ + ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int32x2 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulafd24x2_fir_l( \ + (ae_int64 *)&(ae_mul_q0), (ae_int64 *)&(ae_mul_q1), (__ae_mul_d0), \ + (__ae_mul_d1), (__ae_mul_d2)); \ + }) + +#define AE_MULAFD32X16X2_FIR_HH(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, \ + ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulafd32x16x2_fir_hh( \ + (ae_int64 *)&(ae_mul_q0), (ae_int64 *)&(ae_mul_q1), (__ae_mul_d0), \ + (__ae_mul_d1), (__ae_mul_d2)); \ + }) + +#define AE_MULAFD32X16X2_FIR_HL(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, \ + ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulafd32x16x2_fir_hl( \ + (ae_int64 *)&(ae_mul_q0), (ae_int64 *)&(ae_mul_q1), (__ae_mul_d0), \ + (__ae_mul_d1), (__ae_mul_d2)); \ + }) + +#define AE_MULAFD32X16X2_FIR_LH(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, \ + ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulafd32x16x2_fir_lh( \ + (ae_int64 *)&(ae_mul_q0), (ae_int64 *)&(ae_mul_q1), (__ae_mul_d0), \ + (__ae_mul_d1), (__ae_mul_d2)); \ + }) + +#define AE_MULAFD32X16X2_FIR_LL(ae_mul_q0, ae_mul_q1, ae_mul_d0, ae_mul_d1, \ + ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulafd32x16x2_fir_ll( \ + (ae_int64 *)&(ae_mul_q0), (ae_int64 *)&(ae_mul_q1), (__ae_mul_d0), \ + (__ae_mul_d1), (__ae_mul_d2)); \ + }) + +#define AE_MULAFP24X2R(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulafp24x2r((ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAFP24X2R_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulafp24x2r_s2((ae_int32x2 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAFP24X2RA(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulafp24x2ra( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAFP24X2RA_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulafp24x2ra_s2((ae_int32x2 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAFP32X16X2RAS_H(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulafp32x16x2ras_h( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAFP32X16X2RAS_H_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulafp32x16x2ras_h_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAFP32X16X2RAS_L(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulafp32x16x2ras_l( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAFP32X16X2RAS_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulafp32x16x2ras_l_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAFP32X16X2RS_H(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulafp32x16x2rs_h( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAFP32X16X2RS_H_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulafp32x16x2rs_h_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAFP32X16X2RS_L(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulafp32x16x2rs_l( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAFP32X16X2RS_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulafp32x16x2rs_l_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAFP32X2RAS(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulafp32x2ras( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAFP32X2RS(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulafp32x2rs( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAFQ32SP24S_H_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulafq32sp24s_h_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAFQ32SP24S_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulafq32sp24s_l_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAP24X2(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulap24x2((ae_int32x2 *)&(ae_mul_q0), (__ae_mul_d0), \ + (__ae_mul_d1)); \ + }) + +#define AE_MULAP24X2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulap24x2_s2((ae_int32x2 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAP32X16X2_H(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulap32x16x2_h( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAP32X16X2_L(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulap32x16x2_l( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAP32X2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulap32x2((ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAQ32SP16S_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaq32sp16s_l_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAQ32SP16U_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulaq32sp16u_l_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULARFQ32SP24S_H_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mularfq32sp24s_h_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULARFQ32SP24S_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mularfq32sp24s_l_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAS32F48P16S_HH(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulas32f48p16s_hh( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAS32F48P16S_HH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulas32f48p16s_hh_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAS32F48P16S_LH(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulas32f48p16s_lh( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAS32F48P16S_LH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulas32f48p16s_lh_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULAS32F48P16S_LL(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulas32f48p16s_ll( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULAS32F48P16S_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulas32f48p16s_ll_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULASD24_HH_LL(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulasd24_hh_ll((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULASD24_HH_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulasd24_hh_ll_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULASD24_HL_LH(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulasd24_hl_lh((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULASD24_HL_LH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulasd24_hl_lh_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULASD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulasd32x16_h1_l0( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULASD32X16_H1_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulasd32x16_h1_l0_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULASD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulasd32x16_h3_l2( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULASD32X16_H3_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulasd32x16_h3_l2_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULASFD24_HH_LL(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulasfd24_hh_ll((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULASFD24_HH_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulasfd24_hh_ll_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULASFD24_HL_LH(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulasfd24_hl_lh((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULASFD24_HL_LH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulasfd24_hl_lh_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULASFD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulasfd32x16_h1_l0( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULASFD32X16_H1_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulasfd32x16_h1_l0_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULASFD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulasfd32x16_h3_l2( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULASFD32X16_H3_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulasfd32x16_h3_l2_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULC24(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulc24((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULC32X16_H(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulc32x16_h((__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULC32X16_L(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulc32x16_l((__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULF16SS_00(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf16ss_00((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF16SS_00_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf16ss_00_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF16SS_10(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_10((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16SS_11(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_11((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16SS_20(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_20((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16SS_21(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_21((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16SS_22(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_22((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16SS_30(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_30((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16SS_31(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_31((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16SS_32(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_32((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16SS_33(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulf16ss_33((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULF16X4SS(ae_mul_d1, ae_mul_d0) \ + ({ \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + __builtin_xtensa_ae_mulf16x4ss((__ae_mul_d1), (__ae_mul_d0)); \ + }) + +#define AE_MULF32R_HH(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32r_hh((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32R_LH(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32r_lh((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32R_LL(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32r_ll((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32R_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32r_ll_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32S_HH(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32s_hh((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32S_LH(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32s_lh((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32S_LL(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32s_ll((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32S_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32s_ll_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32X16_H0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32x16_h0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32X16_H0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32x16_h0_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32X16_H1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32x16_h1((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32X16_H1_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32x16_h1_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32X16_H2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32x16_h2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32X16_H2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32x16_h2_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32X16_H3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32x16_h3((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32X16_H3_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32x16_h3_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32X16_L0(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32x16_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32X16_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32x16_l0_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32X16_L1(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32x16_l1((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32X16_L1_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32x16_l1_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32X16_L2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32x16_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32X16_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32x16_l2_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF32X16_L3(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf32x16_l3((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF32X16_L3_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf32x16_l3_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF48Q32SP16S_L(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int64 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf48q32sp16s_l((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF48Q32SP16S_L_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf48q32sp16s_l_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULF48Q32SP16U_L(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int64 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulf48q32sp16u_l((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULF48Q32SP16U_L_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulf48q32sp16u_l_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULFC24RA(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulfc24ra((__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULFC32X16RAS_H(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulfc32x16ras_h((__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULFC32X16RAS_L(opnd_ae_sem_mul_x4_d0, opnd_ae_sem_mul_x4_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x4_d0 = (opnd_ae_sem_mul_x4_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x4_d1 = (opnd_ae_sem_mul_x4_d1); \ + __builtin_xtensa_ae_mulfc32x16ras_l((__opnd_ae_sem_mul_x4_d0), \ + (__opnd_ae_sem_mul_x4_d1)); \ + }) + +#define AE_MULFD24X2_FIR_H(ae_mul_d0, ae_mul_d1, ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int32x2 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulfd24x2_fir_h((__ae_mul_d0), (__ae_mul_d1), \ + (__ae_mul_d2)); \ + }) + +#define AE_MULFD24X2_FIR_L(ae_mul_d0, ae_mul_d1, ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int32x2 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulfd24x2_fir_l((__ae_mul_d0), (__ae_mul_d1), \ + (__ae_mul_d2)); \ + }) + +#define AE_MULFD32X16X2_FIR_HH(ae_mul_d0, ae_mul_d1, ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulfd32x16x2_fir_hh((__ae_mul_d0), (__ae_mul_d1), \ + (__ae_mul_d2)); \ + }) + +#define AE_MULFD32X16X2_FIR_HL(ae_mul_d0, ae_mul_d1, ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulfd32x16x2_fir_hl((__ae_mul_d0), (__ae_mul_d1), \ + (__ae_mul_d2)); \ + }) + +#define AE_MULFD32X16X2_FIR_LH(ae_mul_d0, ae_mul_d1, ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulfd32x16x2_fir_lh((__ae_mul_d0), (__ae_mul_d1), \ + (__ae_mul_d2)); \ + }) + +#define AE_MULFD32X16X2_FIR_LL(ae_mul_d0, ae_mul_d1, ae_mul_d2) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d2 = (ae_mul_d2); \ + __builtin_xtensa_ae_mulfd32x16x2_fir_ll((__ae_mul_d0), (__ae_mul_d1), \ + (__ae_mul_d2)); \ + }) + +#define AE_MULFP16X4RAS(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulfp16x4ras((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULFP16X4S(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulfp16x4s((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULFP24X2R(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulfp24x2r((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULFP24X2R_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulfp24x2r_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULFP24X2RA(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulfp24x2ra((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULFP24X2RA_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulfp24x2ra_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULFP32X16X2RAS_H(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulfp32x16x2ras_h((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULFP32X16X2RAS_H_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulfp32x16x2ras_h_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULFP32X16X2RAS_L(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulfp32x16x2ras_l((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULFP32X16X2RAS_L_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulfp32x16x2ras_l_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULFP32X16X2RS_H(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulfp32x16x2rs_h((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULFP32X16X2RS_H_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulfp32x16x2rs_h_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULFP32X16X2RS_L(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulfp32x16x2rs_l((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULFP32X16X2RS_L_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulfp32x16x2rs_l_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULFP32X2RAS(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulfp32x2ras((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULFP32X2RS(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulfp32x2rs((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULFQ32SP24S_H_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulfq32sp24s_h_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULFQ32SP24S_L_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulfq32sp24s_l_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULP24X2(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulp24x2((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULP24X2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulp24x2_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULP32X16X2_H(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulp32x16x2_h((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULP32X16X2_L(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulp32x16x2_l((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULP32X2(opnd_ae_sem_mul_x2_S1_d0, opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulp32x2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULQ32SP16S_L_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulq32sp16s_l_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULQ32SP16U_L_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulq32sp16u_l_s2((__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULRFQ32SP24S_H_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulrfq32sp24s_h_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULRFQ32SP24S_L_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulrfq32sp24s_l_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS16X4(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0) \ + ({ \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + __builtin_xtensa_ae_muls16x4((ae_int32x2 *)&(ae_mul_q1), \ + (ae_int32x2 *)&(ae_mul_q0), (__ae_mul_d1), \ + (__ae_mul_d0)); \ + }) + +#define AE_MULS32_HH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32_hh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32_LH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32_lh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32_LL(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32_ll((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32F48P16S_HH(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32f48p16s_hh((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32F48P16S_HH_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32f48p16s_hh_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32F48P16S_LH(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32f48p16s_lh((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32F48P16S_LH_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32f48p16s_lh_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32F48P16S_LL(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32f48p16s_ll((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32F48P16S_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32f48p16s_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32U_LL(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32u_ll((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_H0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32x16_h0((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_H0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32x16_h0_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32X16_H1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32x16_h1((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_H1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32x16_h1_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32X16_H2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32x16_h2((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_H2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32x16_h2_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32X16_H3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32x16_h3((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_H3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32x16_h3_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32X16_L0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32x16_l0((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32x16_l0_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32X16_L1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32x16_l1((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_L1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32x16_l1_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32X16_L2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32x16_l2((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32x16_l2_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULS32X16_L3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_muls32x16_l3((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULS32X16_L3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_muls32x16_l3_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSAD24_HH_LL(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsad24_hh_ll((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSAD24_HH_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsad24_hh_ll_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSAD32X16_H1_L0(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsad32x16_h1_l0((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSAD32X16_H1_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsad32x16_h1_l0_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSAD32X16_H3_L2(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsad32x16_h3_l2((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSAD32X16_H3_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsad32x16_h3_l2_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSAFD24_HH_LL(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsafd24_hh_ll((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSAFD24_HH_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsafd24_hh_ll_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSAFD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsafd32x16_h1_l0( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSAFD32X16_H1_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsafd32x16_h1_l0_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSAFD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsafd32x16_h3_l2( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSAFD32X16_H3_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsafd32x16_h3_l2_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF16SS_00(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf16ss_00( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF16SS_00_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf16ss_00_s2((ae_int32x2 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF16SS_10(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_10((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16SS_11(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_11((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16SS_20(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_20((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16SS_21(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_21((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16SS_22(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_22((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16SS_30(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_30((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16SS_31(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_31((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16SS_32(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_32((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16SS_33(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsf16ss_33((ae_int32x2 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSF16X4SS(ae_mul_q1, ae_mul_q0, ae_mul_d1, ae_mul_d0) \ + ({ \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + ae_int16x4 __ae_mul_d0 = (ae_mul_d0); \ + __builtin_xtensa_ae_mulsf16x4ss((ae_int32x2 *)&(ae_mul_q1), \ + (ae_int32x2 *)&(ae_mul_q0), (__ae_mul_d1), \ + (__ae_mul_d0)); \ + }) + +#define AE_MULSF32R_HH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32r_hh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32R_LH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32r_lh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32R_LL(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32r_ll((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32R_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32r_ll_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF32S_HH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32s_hh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32S_LH(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32s_lh((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32S_LL(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32s_ll((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_H0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32x16_h0((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_H0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32x16_h0_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF32X16_H1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32x16_h1((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_H1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32x16_h1_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF32X16_H2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32x16_h2((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_H2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32x16_h2_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF32X16_H3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32x16_h3((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_H3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32x16_h3_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF32X16_L0(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32x16_l0((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32x16_l0_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF32X16_L1(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32x16_l1((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_L1_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32x16_l1_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF32X16_L2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32x16_l2((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32x16_l2_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF32X16_L3(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf32x16_l3((ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF32X16_L3_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf32x16_l3_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF48Q32SP16S_L(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int64 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf48q32sp16s_l( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF48Q32SP16S_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf48q32sp16s_l_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSF48Q32SP16U_L(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int64 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsf48q32sp16u_l( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSF48Q32SP16U_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsf48q32sp16u_l_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSFP24X2R(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsfp24x2r((ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSFP24X2R_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsfp24x2r_s2((ae_int32x2 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSFP24X2RA(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsfp24x2ra( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSFP24X2RA_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsfp24x2ra_s2((ae_int32x2 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSFP32X16X2RAS_H(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsfp32x16x2ras_h( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSFP32X16X2RAS_H_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsfp32x16x2ras_h_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSFP32X16X2RAS_L(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsfp32x16x2ras_l( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSFP32X16X2RAS_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsfp32x16x2ras_l_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSFP32X16X2RS_H(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsfp32x16x2rs_h( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSFP32X16X2RS_H_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsfp32x16x2rs_h_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSFP32X16X2RS_L(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsfp32x16x2rs_l( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSFP32X16X2RS_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsfp32x16x2rs_l_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSFP32X2RAS(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsfp32x2ras( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSFP32X2RS(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsfp32x2rs( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSFQ32SP24S_H_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsfq32sp24s_h_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSFQ32SP24S_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsfq32sp24s_l_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSP24X2(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulsp24x2((ae_int32x2 *)&(ae_mul_q0), (__ae_mul_d0), \ + (__ae_mul_d1)); \ + }) + +#define AE_MULSP24X2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsp24x2_s2((ae_int32x2 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSP32X16X2_H(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsp32x16x2_h( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSP32X16X2_L(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsp32x16x2_l( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSP32X2(opnd_ae_sem_mul_x2_S1_q0, opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulsp32x2((ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSQ32SP16S_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsq32sp16s_l_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSQ32SP16U_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsq32sp16u_l_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSRFQ32SP24S_H_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsrfq32sp24s_h_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSRFQ32SP24S_L_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int64 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulsrfq32sp24s_l_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSS32F48P16S_HH(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulss32f48p16s_hh( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSS32F48P16S_HH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulss32f48p16s_hh_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSS32F48P16S_LH(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulss32f48p16s_lh( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSS32F48P16S_LH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulss32f48p16s_lh_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSS32F48P16S_LL(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulss32f48p16s_ll( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSS32F48P16S_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulss32f48p16s_ll_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSD24_HH_LL(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulssd24_hh_ll((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSSD24_HH_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssd24_hh_ll_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSD24_HL_LH(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulssd24_hl_lh((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSSD24_HL_LH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssd24_hl_lh_s2((ae_int64 *)&(ae_mul_S2_q0), \ + (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulssd32x16_h1_l0( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSSD32X16_H1_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssd32x16_h1_l0_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulssd32x16_h3_l2( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSSD32X16_H3_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssd32x16_h3_l2_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSFD16SS_11_00(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulssfd16ss_11_00( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSSFD16SS_11_00_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssfd16ss_11_00_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSFD16SS_13_02(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulssfd16ss_13_02( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSSFD16SS_13_02_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssfd16ss_13_02_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSFD16SS_33_22(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulssfd16ss_33_22( \ + (ae_int32x2 *)&(opnd_ae_sem_mul_x2_S1_q0), \ + (__opnd_ae_sem_mul_x2_S1_d0), (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSSFD16SS_33_22_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssfd16ss_33_22_s2( \ + (ae_int32x2 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSFD24_HH_LL(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulssfd24_hh_ll((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSSFD24_HH_LL_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssfd24_hh_ll_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSFD24_HL_LH(ae_mul_q0, ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulssfd24_hl_lh((ae_int64 *)&(ae_mul_q0), \ + (__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULSSFD24_HL_LH_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssfd24_hl_lh_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSFD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulssfd32x16_h1_l0( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSSFD32X16_H1_L0_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssfd32x16_h1_l0_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULSSFD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_q0, \ + opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulssfd32x16_h3_l2( \ + (ae_int64 *)&(opnd_ae_sem_mul_x2_S1_q0), (__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULSSFD32X16_H3_L2_S2(ae_mul_S2_q0, ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulssfd32x16_h3_l2_s2( \ + (ae_int64 *)&(ae_mul_S2_q0), (__ae_mul_S2_d0), (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAD24_HH_LL(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzaad24_hh_ll((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZAAD24_HH_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaad24_hh_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAD24_HL_LH(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzaad24_hl_lh((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZAAD24_HL_LH_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaad24_hl_lh_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAD32X16_H0_L1(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaad32x16_h0_l1((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAD32X16_H0_L1_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaad32x16_h0_l1_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaad32x16_h1_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAD32X16_H1_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaad32x16_h1_l0_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAD32X16_H2_L3(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaad32x16_h2_l3((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAD32X16_H2_L3_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaad32x16_h2_l3_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaad32x16_h3_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAD32X16_H3_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaad32x16_h3_l2_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD16SS_11_00(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaafd16ss_11_00((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAFD16SS_11_00_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd16ss_11_00_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD16SS_13_02(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaafd16ss_13_02((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAFD16SS_13_02_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd16ss_13_02_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD16SS_33_22(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaafd16ss_33_22((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAFD16SS_33_22_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd16ss_33_22_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD24_HH_LL(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzaafd24_hh_ll((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZAAFD24_HH_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd24_hh_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD24_HL_LH(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzaafd24_hl_lh((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZAAFD24_HL_LH_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd24_hl_lh_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD32X16_H0_L1(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaafd32x16_h0_l1((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAFD32X16_H0_L1_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd32x16_h0_l1_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaafd32x16_h1_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAFD32X16_H1_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd32x16_h1_l0_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD32X16_H2_L3(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaafd32x16_h2_l3((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAFD32X16_H2_L3_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd32x16_h2_l3_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZAAFD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzaafd32x16_h3_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZAAFD32X16_H3_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzaafd32x16_h3_l2_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZASD24_HH_LL(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzasd24_hh_ll((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZASD24_HH_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzasd24_hh_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZASD24_HL_LH(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzasd24_hl_lh((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZASD24_HL_LH_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzasd24_hl_lh_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZASD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzasd32x16_h1_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZASD32X16_H1_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzasd32x16_h1_l0_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZASD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzasd32x16_h3_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZASD32X16_H3_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzasd32x16_h3_l2_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZASFD24_HH_LL(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzasfd24_hh_ll((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZASFD24_HH_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzasfd24_hh_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZASFD24_HL_LH(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzasfd24_hl_lh((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZASFD24_HL_LH_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzasfd24_hl_lh_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZASFD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzasfd32x16_h1_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZASFD32X16_H1_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzasfd32x16_h1_l0_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZASFD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzasfd32x16_h3_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZASFD32X16_H3_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzasfd32x16_h3_l2_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSAD24_HH_LL(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzsad24_hh_ll((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZSAD24_HH_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzsad24_hh_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSAD32X16_H1_L0(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzsad32x16_h1_l0((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZSAD32X16_H1_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzsad32x16_h1_l0_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSAD32X16_H3_L2(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int16x4 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzsad32x16_h3_l2((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZSAD32X16_H3_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzsad32x16_h3_l2_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSAFD24_HH_LL(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzsafd24_hh_ll((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZSAFD24_HH_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzsafd24_hh_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSAFD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzsafd32x16_h1_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSAFD32X16_H1_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzsafd32x16_h1_l0_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSAFD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzsafd32x16_h3_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSAFD32X16_H3_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzsafd32x16_h3_l2_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSD24_HH_LL(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzssd24_hh_ll((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZSSD24_HH_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssd24_hh_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSD24_HL_LH(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzssd24_hl_lh((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZSSD24_HL_LH_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssd24_hl_lh_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzssd32x16_h1_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSSD32X16_H1_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssd32x16_h1_l0_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzssd32x16_h3_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSSD32X16_H3_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssd32x16_h3_l2_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSFD16SS_11_00(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzssfd16ss_11_00((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSSFD16SS_11_00_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssfd16ss_11_00_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSFD16SS_13_02(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzssfd16ss_13_02((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSSFD16SS_13_02_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssfd16ss_13_02_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSFD16SS_33_22(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzssfd16ss_33_22((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSSFD16SS_33_22_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int16x4 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssfd16ss_33_22_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSFD24_HH_LL(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzssfd24_hh_ll((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZSSFD24_HH_LL_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssfd24_hh_ll_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSFD24_HL_LH(ae_mul_d0, ae_mul_d1) \ + ({ \ + ae_int32x2 __ae_mul_d0 = (ae_mul_d0); \ + ae_int32x2 __ae_mul_d1 = (ae_mul_d1); \ + __builtin_xtensa_ae_mulzssfd24_hl_lh((__ae_mul_d0), (__ae_mul_d1)); \ + }) + +#define AE_MULZSSFD24_HL_LH_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int32x2 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssfd24_hl_lh_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSFD32X16_H1_L0(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzssfd32x16_h1_l0((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSSFD32X16_H1_L0_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssfd32x16_h1_l0_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_MULZSSFD32X16_H3_L2(opnd_ae_sem_mul_x2_S1_d0, \ + opnd_ae_sem_mul_x2_S1_d1) \ + ({ \ + ae_int32x2 __opnd_ae_sem_mul_x2_S1_d0 = (opnd_ae_sem_mul_x2_S1_d0); \ + ae_int16x4 __opnd_ae_sem_mul_x2_S1_d1 = (opnd_ae_sem_mul_x2_S1_d1); \ + __builtin_xtensa_ae_mulzssfd32x16_h3_l2((__opnd_ae_sem_mul_x2_S1_d0), \ + (__opnd_ae_sem_mul_x2_S1_d1)); \ + }) + +#define AE_MULZSSFD32X16_H3_L2_S2(ae_mul_S2_d0, ae_mul_S2_d1) \ + ({ \ + ae_int32x2 __ae_mul_S2_d0 = (ae_mul_S2_d0); \ + ae_int16x4 __ae_mul_S2_d1 = (ae_mul_S2_d1); \ + __builtin_xtensa_ae_mulzssfd32x16_h3_l2_s2((__ae_mul_S2_d0), \ + (__ae_mul_S2_d1)); \ + }) + +#define AE_NAND(ae_dr_to_dr_v0, ae_dr_to_dr_v1) \ + ({ \ + ae_int64 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + ae_int64 __ae_dr_to_dr_v1 = (ae_dr_to_dr_v1); \ + __builtin_xtensa_ae_nand((__ae_dr_to_dr_v0), (__ae_dr_to_dr_v1)); \ + }) + +#define AE_NEG16S(ae_arth_v1) \ + ({ \ + ae_int16x4 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_neg16s((__ae_arth_v1)); \ + }) + +#define AE_NEG24S(ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_neg24s((__ae_arth_v1)); \ + }) + +#define AE_NEG32(ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_neg32((__ae_arth_v1)); \ + }) + +#define AE_NEG32S(ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_neg32s((__ae_arth_v1)); \ + }) + +#define AE_NEG64(ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_neg64((__ae_arth_v1)); \ + }) + +#define AE_NEG64S(ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_neg64s((__ae_arth_v1)); \ + }) + +#define AE_NSA64(ae_dr_to_ar_v0) \ + ({ \ + ae_int64 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_nsa64((__ae_dr_to_ar_v0)); \ + }) + +#define AE_NSAZ16_0(ae_dr_to_ar_v0) \ + ({ \ + ae_int16x4 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_nsaz16_0((__ae_dr_to_ar_v0)); \ + }) + +#define AE_NSAZ32_L(ae_dr_to_ar_v0) \ + ({ \ + ae_int32x2 __ae_dr_to_ar_v0 = (ae_dr_to_ar_v0); \ + __builtin_xtensa_ae_nsaz32_l((__ae_dr_to_ar_v0)); \ + }) + +#define AE_OR(ae_dr_to_dr_v0, ae_dr_to_dr_v1) \ + ({ \ + ae_int64 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + ae_int64 __ae_dr_to_dr_v1 = (ae_dr_to_dr_v1); \ + __builtin_xtensa_ae_or((__ae_dr_to_dr_v0), (__ae_dr_to_dr_v1)); \ + }) + +#define AE_PKSR24(ae_pks_d, ae_pks_s, ae_imm2) \ + ({ \ + ae_int64 __ae_pks_s = (ae_pks_s); \ + __builtin_xtensa_ae_pksr24((ae_int32x2 *)&(ae_pks_d), (__ae_pks_s), \ + (ae_imm2)); \ + }) + +#define AE_PKSR32(ae_pks_d, ae_pks_s, ae_imm2) \ + ({ \ + ae_int64 __ae_pks_s = (ae_pks_s); \ + __builtin_xtensa_ae_pksr32((ae_int32x2 *)&(ae_pks_d), (__ae_pks_s), \ + (ae_imm2)); \ + }) + +#define AE_ROUND16X4F32SASYM(ae_arth_v1, ae_arth_v0) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + __builtin_xtensa_ae_round16x4f32sasym((__ae_arth_v1), (__ae_arth_v0)); \ + }) + +#define AE_ROUND16X4F32SSYM(ae_arth_v1, ae_arth_v0) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + __builtin_xtensa_ae_round16x4f32ssym((__ae_arth_v1), (__ae_arth_v0)); \ + }) + +#define AE_ROUND24X2F48SASYM(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_round24x2f48sasym((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ROUND24X2F48SSYM(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_round24x2f48ssym((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ROUND32X2F48SASYM(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_round32x2f48sasym((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ROUND32X2F48SSYM(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_round32x2f48ssym((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ROUND32X2F64SASYM(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_round32x2f64sasym((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ROUND32X2F64SSYM(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_round32x2f64ssym((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ROUNDSP16F24ASYM(ae_arth_v0) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + __builtin_xtensa_ae_roundsp16f24asym((__ae_arth_v0)); \ + }) + +#define AE_ROUNDSP16F24SYM(ae_arth_v0) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + __builtin_xtensa_ae_roundsp16f24sym((__ae_arth_v0)); \ + }) + +#define AE_ROUNDSP16Q48X2ASYM(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_roundsp16q48x2asym((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ROUNDSP16Q48X2SYM(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_roundsp16q48x2sym((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_ROUNDSQ32F48ASYM(ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_roundsq32f48asym((__ae_arth_v1)); \ + }) + +#define AE_ROUNDSQ32F48SYM(ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_roundsq32f48sym((__ae_arth_v1)); \ + }) + +#define AE_S16_0_I(ae_ls_v, ars, ae_immls16) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + ae_int16 *__ars = (ars); \ + __builtin_xtensa_ae_s16_0_i((__ae_ls_v), (__ars), (ae_immls16)); \ + }) + +#define AE_S16_0_IP(ae_ls_v, ars, ae_immls16) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s16_0_ip((__ae_ls_v), (ae_int16 **)&(ars), \ + (ae_immls16)); \ + }) + +#define AE_S16_0_X(ae_ls_v, ars, art) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + ae_int16 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16_0_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S16_0_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16_0_xc((__ae_ls_v), (ae_int16 **)&(ars), (__art)); \ + }) + +#define AE_S16_0_XP(ae_ls_v, ars, art) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16_0_xp((__ae_ls_v), (ae_int16 **)&(ars), (__art)); \ + }) + +#define AE_S16M_L_I(ae_ls_v, ars, ae_immls16) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int16 *__ars = (ars); \ + __builtin_xtensa_ae_s16m_l_i((__ae_ls_v), (__ars), (ae_immls16)); \ + }) + +#define AE_S16M_L_IU(ae_ls_v, ars, ae_immls16) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s16m_l_iu((__ae_ls_v), (ae_int16 **)&(ars), \ + (ae_immls16)); \ + }) + +#define AE_S16M_L_X(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int16 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16m_l_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S16M_L_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16m_l_xc((__ae_ls_v), (ae_int16 **)&(ars), (__art)); \ + }) + +#define AE_S16M_L_XU(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16m_l_xu((__ae_ls_v), (ae_int16 **)&(ars), (__art)); \ + }) + +#define AE_S16X2M_I(ae_ls_v, ars, ae_immls32) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int16x2 *__ars = (ars); \ + __builtin_xtensa_ae_s16x2m_i((__ae_ls_v), (__ars), (ae_immls32)); \ + }) + +#define AE_S16X2M_IU(ae_ls_v, ars, ae_immls32) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s16x2m_iu((__ae_ls_v), (ae_int16x2 **)&(ars), \ + (ae_immls32)); \ + }) + +#define AE_S16X2M_X(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int16x2 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16x2m_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S16X2M_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16x2m_xc((__ae_ls_v), (ae_int16x2 **)&(ars), \ + (__art)); \ + }) + +#define AE_S16X2M_XU(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16x2m_xu((__ae_ls_v), (ae_int16x2 **)&(ars), \ + (__art)); \ + }) + +#define AE_S16X4_I(ae_ls_v, ars, ae_immls64) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + ae_int16x4 *__ars = (ars); \ + __builtin_xtensa_ae_s16x4_i((__ae_ls_v), (__ars), (ae_immls64)); \ + }) + +#define AE_S16X4_IP(ae_ls_v, ars, ae_immls64pos) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s16x4_ip((__ae_ls_v), (ae_int16x4 **)&(ars), \ + (ae_immls64pos)); \ + }) + +#define AE_S16X4_RIC(ae_ls_v, ars) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s16x4_ric((__ae_ls_v), (ae_int16x4 **)&(ars)); \ + }) + +#define AE_S16X4_RIP(ae_ls_v, ars) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s16x4_rip((__ae_ls_v), (ae_int16x4 **)&(ars)); \ + }) + +#define AE_S16X4_X(ae_ls_v, ars, art) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + ae_int16x4 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16x4_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S16X4_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16x4_xc((__ae_ls_v), (ae_int16x4 **)&(ars), (__art)); \ + }) + +#define AE_S16X4_XP(ae_ls_v, ars, art) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s16x4_xp((__ae_ls_v), (ae_int16x4 **)&(ars), (__art)); \ + }) + +#define AE_S24RA64S_I(ae_ls_v1, ars, ae_immls32) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + ae_int32 *__ars = (ars); \ + __builtin_xtensa_ae_s24ra64s_i((__ae_ls_v1), (__ars), (ae_immls32)); \ + }) + +#define AE_S24RA64S_IP(ae_ls_v1, ars, ae_immls32) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + __builtin_xtensa_ae_s24ra64s_ip((__ae_ls_v1), (ae_int32 **)&(ars), \ + (ae_immls32)); \ + }) + +#define AE_S24RA64S_X(ae_ls_v1, ars, art) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + ae_int32 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s24ra64s_x((__ae_ls_v1), (__ars), (__art)); \ + }) + +#define AE_S24RA64S_XC(ae_ls_v1, ars, art) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s24ra64s_xc((__ae_ls_v1), (ae_int32 **)&(ars), \ + (__art)); \ + }) + +#define AE_S24RA64S_XP(ae_ls_v1, ars, art) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s24ra64s_xp((__ae_ls_v1), (ae_int32 **)&(ars), \ + (__art)); \ + }) + +#define AE_S24X2RA64S_IP(ae_ls_v2, ae_ls_v1, ars) \ + ({ \ + ae_int64 __ae_ls_v2 = (ae_ls_v2); \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + __builtin_xtensa_ae_s24x2ra64s_ip((__ae_ls_v2), (__ae_ls_v1), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_S32_L_I(ae_ls_v, ars, ae_immls32) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int32 *__ars = (ars); \ + __builtin_xtensa_ae_s32_l_i((__ae_ls_v), (__ars), (ae_immls32)); \ + }) + +#define AE_S32_L_IP(ae_ls_v, ars, ae_immls32) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32_l_ip((__ae_ls_v), (ae_int32 **)&(ars), \ + (ae_immls32)); \ + }) + +#define AE_S32_L_X(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int32 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32_l_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S32_L_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32_l_xc((__ae_ls_v), (ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_S32_L_XP(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32_l_xp((__ae_ls_v), (ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_S32F24_L_I(ae_ls_v, ars, ae_immls32) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int32 *__ars = (ars); \ + __builtin_xtensa_ae_s32f24_l_i((__ae_ls_v), (__ars), (ae_immls32)); \ + }) + +#define AE_S32F24_L_IP(ae_ls_v, ars, ae_immls32) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32f24_l_ip((__ae_ls_v), (ae_int32 **)&(ars), \ + (ae_immls32)); \ + }) + +#define AE_S32F24_L_X(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int32 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32f24_l_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S32F24_L_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32f24_l_xc((__ae_ls_v), (ae_int32 **)&(ars), \ + (__art)); \ + }) + +#define AE_S32F24_L_XP(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32f24_l_xp((__ae_ls_v), (ae_int32 **)&(ars), \ + (__art)); \ + }) + +#define AE_S32M_I(ae_ls_v, ars, ae_immls32) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + ae_int32 *__ars = (ars); \ + __builtin_xtensa_ae_s32m_i((__ae_ls_v), (__ars), (ae_immls32)); \ + }) + +#define AE_S32M_IU(ae_ls_v, ars, ae_immls32) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32m_iu((__ae_ls_v), (ae_int32 **)&(ars), \ + (ae_immls32)); \ + }) + +#define AE_S32M_X(ae_ls_v, ars, art) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + ae_int32 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32m_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S32M_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32m_xc((__ae_ls_v), (ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_S32M_XU(ae_ls_v, ars, art) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32m_xu((__ae_ls_v), (ae_int32 **)&(ars), (__art)); \ + }) + +#define AE_S32RA64S_I(ae_ls_v1, ars, ae_immls32) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + ae_int32 *__ars = (ars); \ + __builtin_xtensa_ae_s32ra64s_i((__ae_ls_v1), (__ars), (ae_immls32)); \ + }) + +#define AE_S32RA64S_IP(ae_ls_v1, ars, ae_immls32) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + __builtin_xtensa_ae_s32ra64s_ip((__ae_ls_v1), (ae_int32 **)&(ars), \ + (ae_immls32)); \ + }) + +#define AE_S32RA64S_X(ae_ls_v1, ars, art) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + ae_int32 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32ra64s_x((__ae_ls_v1), (__ars), (__art)); \ + }) + +#define AE_S32RA64S_XC(ae_ls_v1, ars, art) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32ra64s_xc((__ae_ls_v1), (ae_int32 **)&(ars), \ + (__art)); \ + }) + +#define AE_S32RA64S_XP(ae_ls_v1, ars, art) \ + ({ \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32ra64s_xp((__ae_ls_v1), (ae_int32 **)&(ars), \ + (__art)); \ + }) + +#define AE_S32X2_I(ae_ls_v, ars, ae_immls64) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int32x2 *__ars = (ars); \ + __builtin_xtensa_ae_s32x2_i((__ae_ls_v), (__ars), (ae_immls64)); \ + }) + +#define AE_S32X2_IP(ae_ls_v, ars, ae_immls64pos) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32x2_ip((__ae_ls_v), (ae_int32x2 **)&(ars), \ + (ae_immls64pos)); \ + }) + +#define AE_S32X2_RIC(ae_ls_v, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32x2_ric((__ae_ls_v), (ae_int32x2 **)&(ars)); \ + }) + +#define AE_S32X2_RIP(ae_ls_v, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32x2_rip((__ae_ls_v), (ae_int32x2 **)&(ars)); \ + }) + +#define AE_S32X2_X(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int32x2 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32x2_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S32X2_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32x2_xc((__ae_ls_v), (ae_int32x2 **)&(ars), (__art)); \ + }) + +#define AE_S32X2_XP(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32x2_xp((__ae_ls_v), (ae_int32x2 **)&(ars), (__art)); \ + }) + +#define AE_S32X2F24_I(ae_ls_v, ars, ae_immls64) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int32x2 *__ars = (ars); \ + __builtin_xtensa_ae_s32x2f24_i((__ae_ls_v), (__ars), (ae_immls64)); \ + }) + +#define AE_S32X2F24_IP(ae_ls_v, ars, ae_immls64pos) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32x2f24_ip((__ae_ls_v), (ae_int32x2 **)&(ars), \ + (ae_immls64pos)); \ + }) + +#define AE_S32X2F24_RIC(ae_ls_v, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32x2f24_ric((__ae_ls_v), (ae_int32x2 **)&(ars)); \ + }) + +#define AE_S32X2F24_RIP(ae_ls_v, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s32x2f24_rip((__ae_ls_v), (ae_int32x2 **)&(ars)); \ + }) + +#define AE_S32X2F24_X(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + ae_int32x2 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32x2f24_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S32X2F24_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32x2f24_xc((__ae_ls_v), (ae_int32x2 **)&(ars), \ + (__art)); \ + }) + +#define AE_S32X2F24_XP(ae_ls_v, ars, art) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s32x2f24_xp((__ae_ls_v), (ae_int32x2 **)&(ars), \ + (__art)); \ + }) + +#define AE_S32X2RA64S_IP(ae_ls_v2, ae_ls_v1, ars) \ + ({ \ + ae_int64 __ae_ls_v2 = (ae_ls_v2); \ + ae_int64 __ae_ls_v1 = (ae_ls_v1); \ + __builtin_xtensa_ae_s32x2ra64s_ip((__ae_ls_v2), (__ae_ls_v1), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_S64_I(ae_ls_v, ars, ae_immls64) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + ae_int64 *__ars = (ars); \ + __builtin_xtensa_ae_s64_i((__ae_ls_v), (__ars), (ae_immls64)); \ + }) + +#define AE_S64_IP(ae_ls_v, ars, ae_immls64) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_s64_ip((__ae_ls_v), (ae_int64 **)&(ars), \ + (ae_immls64)); \ + }) + +#define AE_S64_X(ae_ls_v, ars, art) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + ae_int64 *__ars = (ars); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s64_x((__ae_ls_v), (__ars), (__art)); \ + }) + +#define AE_S64_XC(ae_ls_v, ars, art) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s64_xc((__ae_ls_v), (ae_int64 **)&(ars), (__art)); \ + }) + +#define AE_S64_XP(ae_ls_v, ars, art) \ + ({ \ + ae_int64 __ae_ls_v = (ae_ls_v); \ + int __art = (int)(art); \ + __builtin_xtensa_ae_s64_xp((__ae_ls_v), (ae_int64 **)&(ars), (__art)); \ + }) + +#define AE_SA16X4_IC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa16x4_ic((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int16x4 **)&(ars)); \ + }) + +#define AE_SA16X4_IP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa16x4_ip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int16x4 **)&(ars)); \ + }) + +#define AE_SA16X4_RIC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa16x4_ric((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int16x4 **)&(ars)); \ + }) + +#define AE_SA16X4_RIP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int16x4 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa16x4_rip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int16x4 **)&(ars)); \ + }) + +#define AE_SA24_L_IC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa24_l_ic((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (void **)&(ars)); \ + }) + +#define AE_SA24_L_IP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa24_l_ip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (void **)&(ars)); \ + }) + +#define AE_SA24_L_RIC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa24_l_ric((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (void **)&(ars)); \ + }) + +#define AE_SA24_L_RIP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa24_l_rip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (void **)&(ars)); \ + }) + +#define AE_SA24X2_IC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa24x2_ic((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (void **)&(ars)); \ + }) + +#define AE_SA24X2_IP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa24x2_ip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (void **)&(ars)); \ + }) + +#define AE_SA24X2_RIC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa24x2_ric((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (void **)&(ars)); \ + }) + +#define AE_SA24X2_RIP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa24x2_rip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (void **)&(ars)); \ + }) + +#define AE_SA32X2_IC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa32x2_ic((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_SA32X2_IP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa32x2_ip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_SA32X2_RIC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa32x2_ric((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_SA32X2_RIP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa32x2_rip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_SA32X2F24_IC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa32x2f24_ic((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_SA32X2F24_IP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa32x2f24_ip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_SA32X2F24_RIC(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa32x2f24_ric((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_SA32X2F24_RIP(ae_ls_v, ae_ls_su, ars) \ + ({ \ + ae_int32x2 __ae_ls_v = (ae_ls_v); \ + __builtin_xtensa_ae_sa32x2f24_rip((__ae_ls_v), (ae_valign *)&(ae_ls_su), \ + (ae_int32x2 **)&(ars)); \ + }) + +#define AE_SA64NEG_FP(ae_ls_su, ars) \ + ({ \ + void *__ars = (void *)(ars); \ + __builtin_xtensa_ae_sa64neg_fp((ae_valign *)&(ae_ls_su), (__ars)); \ + }) + +#define AE_SA64POS_FP(ae_ls_su, ars) \ + ({ \ + void *__ars = (void *)(ars); \ + __builtin_xtensa_ae_sa64pos_fp((ae_valign *)&(ae_ls_su), (__ars)); \ + }) + +#define AE_SALIGN64_I(ae_ls_su, ars, ae_immls64) \ + ({ \ + ae_valign __ae_ls_su = (ae_ls_su); \ + ae_valign *__ars = (ars); \ + __builtin_xtensa_ae_salign64_i((__ae_ls_su), (__ars), (ae_immls64)); \ + }) + +#define AE_SAT16X4(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sat16x4((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SAT24S(ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sat24s((__ae_arth_v1)); \ + }) + +#define AE_SAT48S(ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sat48s((__ae_arth_v1)); \ + }) + +#define AE_SATQ56S(ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_satq56s((__ae_arth_v1)); \ + }) + +#define AE_SB(ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_sb((short **)&(ars), (__art)); \ + }) + +#define AE_SB_IC(ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_sb_ic((short **)&(ars), (__art)); \ + }) + +#define AE_SB_IP(ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_sb_ip((short **)&(ars), (__art)); \ + }) + +#define AE_SBF(ars) ({ __builtin_xtensa_ae_sbf((short **)&(ars)); }) + +#define AE_SBF_IC(ars) ({ __builtin_xtensa_ae_sbf_ic((short **)&(ars)); }) + +#define AE_SBF_IP(ars) ({ __builtin_xtensa_ae_sbf_ip((short **)&(ars)); }) + +#define AE_SBI(ars, art, ae_ohba2) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_sbi((short **)&(ars), (__art), (ae_ohba2)); \ + }) + +#define AE_SBI_IC(ars, art, ae_ohba2) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_sbi_ic((short **)&(ars), (__art), (ae_ohba2)); \ + }) + +#define AE_SBI_IP(ars, art, ae_ohba2) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_sbi_ip((short **)&(ars), (__art), (ae_ohba2)); \ + }) + +#define AE_SEL16I(ae_dr_to_dr_v0, ae_dr_to_dr_v1, ae_selimm) \ + ({ \ + ae_int16x4 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + ae_int16x4 __ae_dr_to_dr_v1 = (ae_dr_to_dr_v1); \ + __builtin_xtensa_ae_sel16i((__ae_dr_to_dr_v0), (__ae_dr_to_dr_v1), \ + (ae_selimm)); \ + }) + +#define AE_SEL16I_N(ae_dr_to_dr_v0, ae_dr_to_dr_v1, ae_selimm_N) \ + ({ \ + ae_int16x4 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + ae_int16x4 __ae_dr_to_dr_v1 = (ae_dr_to_dr_v1); \ + __builtin_xtensa_ae_sel16i_n((__ae_dr_to_dr_v0), (__ae_dr_to_dr_v1), \ + (ae_selimm_N)); \ + }) + +#define AE_SEXT32(ae_dr_to_dr_v0, ae_opnd_tp7) \ + ({ \ + ae_int32x2 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + __builtin_xtensa_ae_sext32((__ae_dr_to_dr_v0), (ae_opnd_tp7)); \ + }) + +#define AE_SEXT32X2D16_10(ae_to_dr_v0) \ + ({ \ + ae_int16x4 __ae_to_dr_v0 = (ae_to_dr_v0); \ + __builtin_xtensa_ae_sext32x2d16_10((__ae_to_dr_v0)); \ + }) + +#define AE_SEXT32X2D16_32(ae_to_dr_v0) \ + ({ \ + ae_int16x4 __ae_to_dr_v0 = (ae_to_dr_v0); \ + __builtin_xtensa_ae_sext32x2d16_32((__ae_to_dr_v0)); \ + }) + +#define AE_SHA32(ars) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_sha32((__ars)); \ + }) + +#define AE_SHORTSWAP(ae_to_dr_v0) \ + ({ \ + ae_int16x4 __ae_to_dr_v0 = (ae_to_dr_v0); \ + __builtin_xtensa_ae_shortswap((__ae_to_dr_v0)); \ + }) + +#define AE_SLAA16S(ae_shift_d0, ars) \ + ({ \ + ae_int16x4 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_slaa16s((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SLAA32(ae_shift_d0, ars) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_slaa32((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SLAA32S(ae_shift_d0, ars) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_slaa32s((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SLAA64(ae_shift_d0, ars) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_slaa64((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SLAA64S(ae_shift_d0, ars) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_slaa64s((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SLAAQ56(ae_shift_d0, ars) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_slaaq56((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SLAI16S(ae_shift_d0, ae_osa16) \ + ({ \ + ae_int16x4 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slai16s((__ae_shift_d0), (ae_osa16)); \ + }) + +#define AE_SLAI24(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slai24((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SLAI24S(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slai24s((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SLAI32(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slai32((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SLAI32S(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slai32s((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SLAI64(ae_shift_d0, ae_osa64) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slai64((__ae_shift_d0), (ae_osa64)); \ + }) + +#define AE_SLAI64S(ae_shift_d0, ae_osa64) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slai64s((__ae_shift_d0), (ae_osa64)); \ + }) + +#define AE_SLAISQ56S(ae_shift_d0, ae_osa64) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slaisq56s((__ae_shift_d0), (ae_osa64)); \ + }) + +#define AE_SLAS24(ae_shift_d0) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slas24((__ae_shift_d0)); \ + }) + +#define AE_SLAS24S(ae_shift_d0) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slas24s((__ae_shift_d0)); \ + }) + +#define AE_SLAS32(ae_shift_d0) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slas32((__ae_shift_d0)); \ + }) + +#define AE_SLAS32S(ae_shift_d0) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slas32s((__ae_shift_d0)); \ + }) + +#define AE_SLAS64(ae_shift_d0) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slas64((__ae_shift_d0)); \ + }) + +#define AE_SLAS64S(ae_shift_d0) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slas64s((__ae_shift_d0)); \ + }) + +#define AE_SLASQ56(ae_shift_d0) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slasq56((__ae_shift_d0)); \ + }) + +#define AE_SLASSQ56S(ae_shift_d0) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_slassq56s((__ae_shift_d0)); \ + }) + +#define AE_SRA64_32(ae_shift_d0, ars) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_sra64_32((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRAA16RS(ae_shift_d0, ars) \ + ({ \ + ae_int16x4 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_sraa16rs((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRAA16S(ae_shift_d0, ars) \ + ({ \ + ae_int16x4 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_sraa16s((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRAA32(ae_shift_d0, ars) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_sraa32((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRAA32RS(ae_shift_d0, ars) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_sraa32rs((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRAA32S(ae_shift_d0, ars) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_sraa32s((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRAA64(ae_shift_d0, ars) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_sraa64((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRAI16(ae_shift_d0, ae_osa16) \ + ({ \ + ae_int16x4 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srai16((__ae_shift_d0), (ae_osa16)); \ + }) + +#define AE_SRAI16R(ae_shift_d0, ae_osa16) \ + ({ \ + ae_int16x4 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srai16r((__ae_shift_d0), (ae_osa16)); \ + }) + +#define AE_SRAI24(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srai24((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SRAI32(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srai32((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SRAI32R(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srai32r((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SRAI64(ae_shift_d0, ae_osa64) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srai64((__ae_shift_d0), (ae_osa64)); \ + }) + +#define AE_SRAS24(ae_shift_d0) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_sras24((__ae_shift_d0)); \ + }) + +#define AE_SRAS32(ae_shift_d0) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_sras32((__ae_shift_d0)); \ + }) + +#define AE_SRAS64(ae_shift_d0) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_sras64((__ae_shift_d0)); \ + }) + +#define AE_SRLA32(ae_shift_d0, ars) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_srla32((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRLA64(ae_shift_d0, ars) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_srla64((__ae_shift_d0), (__ars)); \ + }) + +#define AE_SRLI24(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srli24((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SRLI32(ae_shift_d0, ae_osa32) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srli32((__ae_shift_d0), (ae_osa32)); \ + }) + +#define AE_SRLI64(ae_shift_d0, ae_osa64) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srli64((__ae_shift_d0), (ae_osa64)); \ + }) + +#define AE_SRLS24(ae_shift_d0) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srls24((__ae_shift_d0)); \ + }) + +#define AE_SRLS32(ae_shift_d0) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srls32((__ae_shift_d0)); \ + }) + +#define AE_SRLS64(ae_shift_d0) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + __builtin_xtensa_ae_srls64((__ae_shift_d0)); \ + }) + +#define AE_SUB16(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int16x4 __ae_arth_v0 = (ae_arth_v0); \ + ae_int16x4 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sub16((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SUB16S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int16x4 __ae_arth_v0 = (ae_arth_v0); \ + ae_int16x4 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sub16s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SUB24S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sub24s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SUB32(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sub32((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SUB32S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sub32s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SUB64(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sub64((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SUB64S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int64 __ae_arth_v0 = (ae_arth_v0); \ + ae_int64 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_sub64s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SUBADD32(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_subadd32((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_SUBADD32S(ae_arth_v0, ae_arth_v1) \ + ({ \ + ae_int32x2 __ae_arth_v0 = (ae_arth_v0); \ + ae_int32x2 __ae_arth_v1 = (ae_arth_v1); \ + __builtin_xtensa_ae_subadd32s((__ae_arth_v0), (__ae_arth_v1)); \ + }) + +#define AE_TRUNCA32F64S_L(ae_shift_d0, ae_shift_sd, ars) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + ae_int64 __ae_shift_sd = (ae_shift_sd); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_trunca32f64s_l((__ae_shift_d0), (__ae_shift_sd), \ + (__ars)); \ + }) + +#define AE_TRUNCA32X2F64S(ae_shift_d0, ae_shift_sd, ars) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + ae_int64 __ae_shift_sd = (ae_shift_sd); \ + int __ars = (int)(ars); \ + __builtin_xtensa_ae_trunca32x2f64s((__ae_shift_d0), (__ae_shift_sd), \ + (__ars)); \ + }) + +#define AE_TRUNCI32F64S_L(ae_shift_d0, ae_shift_sd, ae_osa16) \ + ({ \ + ae_int32x2 __ae_shift_d0 = (ae_shift_d0); \ + ae_int64 __ae_shift_sd = (ae_shift_sd); \ + __builtin_xtensa_ae_trunci32f64s_l((__ae_shift_d0), (__ae_shift_sd), \ + (ae_osa16)); \ + }) + +#define AE_TRUNCI32X2F64S(ae_shift_d0, ae_shift_sd, ae_osa16) \ + ({ \ + ae_int64 __ae_shift_d0 = (ae_shift_d0); \ + ae_int64 __ae_shift_sd = (ae_shift_sd); \ + __builtin_xtensa_ae_trunci32x2f64s((__ae_shift_d0), (__ae_shift_sd), \ + (ae_osa16)); \ + }) + +#define AE_VLDL16C(ars) \ + ({ __builtin_xtensa_ae_vldl16c((const short **)&(ars)); }) + +#define AE_VLDL16C_IC(ars) \ + ({ __builtin_xtensa_ae_vldl16c_ic((const short **)&(ars)); }) + +#define AE_VLDL16C_IP(ars) \ + ({ __builtin_xtensa_ae_vldl16c_ip((const short **)&(ars)); }) + +#define AE_VLDL16T(ars) \ + ({ \ + short *__ars = (short *)(ars); \ + __builtin_xtensa_ae_vldl16t((__ars)); \ + }) + +#define AE_VLDL32T(ars) \ + ({ \ + int *__ars = (int *)(ars); \ + __builtin_xtensa_ae_vldl32t((__ars)); \ + }) + +#define AE_VLDSHT(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_ae_vldsht((__art)); \ + }) + +#define AE_VLEL16T(br, art, ars) \ + ({ \ + short *__ars = (short *)(ars); \ + __builtin_xtensa_ae_vlel16t((xtbool *)&(br), (int *)&(art), (__ars)); \ + }) + +#define AE_VLEL32T(br, art, ars) \ + ({ \ + int *__ars = (int *)(ars); \ + __builtin_xtensa_ae_vlel32t((xtbool *)&(br), (int *)&(art), (__ars)); \ + }) + +#define AE_VLES16C(ars) ({ __builtin_xtensa_ae_vles16c((short **)&(ars)); }) + +#define AE_VLES16C_IC(ars) \ + ({ __builtin_xtensa_ae_vles16c_ic((short **)&(ars)); }) + +#define AE_VLES16C_IP(ars) \ + ({ __builtin_xtensa_ae_vles16c_ip((short **)&(ars)); }) + +#define AE_XOR(ae_dr_to_dr_v0, ae_dr_to_dr_v1) \ + ({ \ + ae_int64 __ae_dr_to_dr_v0 = (ae_dr_to_dr_v0); \ + ae_int64 __ae_dr_to_dr_v1 = (ae_dr_to_dr_v1); \ + __builtin_xtensa_ae_xor((__ae_dr_to_dr_v0), (__ae_dr_to_dr_v1)); \ + }) + +#define AE_ZALIGN64() ({ __builtin_xtensa_ae_zalign64(); }) + +#define RUR_AE_BITHEAD() ({ __builtin_xtensa_rur_ae_bithead(); }) + +#define RUR_AE_BITPTR() ({ __builtin_xtensa_rur_ae_bitptr(); }) + +#define RUR_AE_BITSUSED() ({ __builtin_xtensa_rur_ae_bitsused(); }) + +#define RUR_AE_CBEGIN0() ({ __builtin_xtensa_rur_ae_cbegin0(); }) + +#define RUR_AE_CEND0() ({ __builtin_xtensa_rur_ae_cend0(); }) + +#define RUR_AE_CW_SD_NO() ({ __builtin_xtensa_rur_ae_cw_sd_no(); }) + +#define RUR_AE_CWRAP() ({ __builtin_xtensa_rur_ae_cwrap(); }) + +#define RUR_AE_FIRST_TS() ({ __builtin_xtensa_rur_ae_first_ts(); }) + +#define RUR_AE_NEXTOFFSET() ({ __builtin_xtensa_rur_ae_nextoffset(); }) + +#define RUR_AE_OVERFLOW() ({ __builtin_xtensa_rur_ae_overflow(); }) + +#define RUR_AE_OVF_SAR() ({ __builtin_xtensa_rur_ae_ovf_sar(); }) + +#define RUR_AE_SAR() ({ __builtin_xtensa_rur_ae_sar(); }) + +#define RUR_AE_SEARCHDONE() ({ __builtin_xtensa_rur_ae_searchdone(); }) + +#define RUR_AE_TABLESIZE() ({ __builtin_xtensa_rur_ae_tablesize(); }) + +#define RUR_AE_TS_FTS_BU_BP() ({ __builtin_xtensa_rur_ae_ts_fts_bu_bp(); }) + +#define WUR_AE_BITHEAD(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_bithead((__art)); \ + }) + +#define WUR_AE_BITPTR(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_bitptr((__art)); \ + }) + +#define WUR_AE_BITSUSED(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_bitsused((__art)); \ + }) + +#define WUR_AE_CBEGIN0(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_cbegin0((__art)); \ + }) + +#define WUR_AE_CEND0(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_cend0((__art)); \ + }) + +#define WUR_AE_CW_SD_NO(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_cw_sd_no((__art)); \ + }) + +#define WUR_AE_CWRAP(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_cwrap((__art)); \ + }) + +#define WUR_AE_FIRST_TS(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_first_ts((__art)); \ + }) + +#define WUR_AE_NEXTOFFSET(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_nextoffset((__art)); \ + }) + +#define WUR_AE_OVERFLOW(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_overflow((__art)); \ + }) + +#define WUR_AE_OVF_SAR(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_ovf_sar((__art)); \ + }) + +#define WUR_AE_SAR(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_sar((__art)); \ + }) + +#define WUR_AE_SEARCHDONE(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_searchdone((__art)); \ + }) + +#define WUR_AE_TABLESIZE(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_tablesize((__art)); \ + }) + +#define WUR_AE_TS_FTS_BU_BP(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_wur_ae_ts_fts_bu_bp((__art)); \ + }) + +#define XT_ABS_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_abs_s((__frs)); \ + }) + +#define XT_ADD_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_add_s((__frs), (__frt)); \ + }) + +#define XT_ADDEXP_S(frr, frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_addexp_s((xtfloat *)&(frr), (__frs)); \ + }) + +#define XT_ADDEXPM_S(frr, frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_addexpm_s((xtfloat *)&(frr), (__frs)); \ + }) + +#define XT_CEIL_S(frs, imm_t) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_ceil_s((__frs), (imm_t)); \ + }) + +#define XT_DIV0_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_div0_s((__frs)); \ + }) + +#define XT_DIVN_S(frr, frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_divn_s((xtfloat *)&(frr), (__frs), (__frt)); \ + }) + +#define XT_FLOAT_S(ars, imm_t) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_xt_float_s((__ars), (imm_t)); \ + }) + +#define XT_FLOOR_S(frs, imm_t) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_floor_s((__frs), (imm_t)); \ + }) + +#define XT_LSI(ars, imm8x4) \ + ({ \ + xtfloat *__ars = (xtfloat *)(ars); \ + __builtin_xtensa_xt_lsi((__ars), (imm8x4)); \ + }) + +#define XT_LSIP(frt, ars, imm8x4) \ + ({ \ + __builtin_xtensa_xt_lsip((xtfloat *)&(frt), (const xtfloat **)&(ars), \ + (imm8x4)); \ + }) + +#define XT_LSX(ars, art) \ + ({ \ + xtfloat *__ars = (xtfloat *)(ars); \ + int __art = (int)(art); \ + __builtin_xtensa_xt_lsx((__ars), (__art)); \ + }) + +#define XT_LSXP(frr, ars, art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_xt_lsxp((xtfloat *)&(frr), (const xtfloat **)&(ars), \ + (__art)); \ + }) + +#define XT_MADD_S(frr, frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_madd_s((xtfloat *)&(frr), (__frs), (__frt)); \ + }) + +#define XT_MADDN_S(frr, frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_maddn_s((xtfloat *)&(frr), (__frs), (__frt)); \ + }) + +#define XT_MKDADJ_S(frr, frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_mkdadj_s((xtfloat *)&(frr), (__frs)); \ + }) + +#define XT_MKSADJ_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_mksadj_s((__frs)); \ + }) + +#define XT_MOV_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_mov_s((__frs)); \ + }) + +#define XT_MOVEQZ_S(frr, frs, art) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + int __art = (int)(art); \ + __builtin_xtensa_xt_moveqz_s((xtfloat *)&(frr), (__frs), (__art)); \ + }) + +#define XT_MOVF_S(frr, frs, bt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtbool __bt = (bt); \ + __builtin_xtensa_xt_movf_s((xtfloat *)&(frr), (__frs), (__bt)); \ + }) + +#define XT_MOVGEZ_S(frr, frs, art) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + int __art = (int)(art); \ + __builtin_xtensa_xt_movgez_s((xtfloat *)&(frr), (__frs), (__art)); \ + }) + +#define XT_MOVLTZ_S(frr, frs, art) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + int __art = (int)(art); \ + __builtin_xtensa_xt_movltz_s((xtfloat *)&(frr), (__frs), (__art)); \ + }) + +#define XT_MOVNEZ_S(frr, frs, art) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + int __art = (int)(art); \ + __builtin_xtensa_xt_movnez_s((xtfloat *)&(frr), (__frs), (__art)); \ + }) + +#define XT_MOVT_S(frr, frs, bt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtbool __bt = (bt); \ + __builtin_xtensa_xt_movt_s((xtfloat *)&(frr), (__frs), (__bt)); \ + }) + +#define XT_MSUB_S(frr, frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_msub_s((xtfloat *)&(frr), (__frs), (__frt)); \ + }) + +#define XT_MUL_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_mul_s((__frs), (__frt)); \ + }) + +#define XT_NEG_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_neg_s((__frs)); \ + }) + +#define XT_NEXP01_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_nexp01_s((__frs)); \ + }) + +#define XT_OEQ_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_oeq_s((__frs), (__frt)); \ + }) + +#define XT_OLE_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_ole_s((__frs), (__frt)); \ + }) + +#define XT_OLT_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_olt_s((__frs), (__frt)); \ + }) + +#define XT_RECIP0_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_recip0_s((__frs)); \ + }) + +#define XT_RFR(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_rfr((__frs)); \ + }) + +#define XT_ROUND_S(frs, imm_t) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_round_s((__frs), (imm_t)); \ + }) + +#define XT_RSQRT0_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_rsqrt0_s((__frs)); \ + }) + +#define XT_RUR_FCR() ({ __builtin_xtensa_xt_rur_fcr(); }) + +#define XT_RUR_FSR() ({ __builtin_xtensa_xt_rur_fsr(); }) + +#define XT_SQRT0_S(frs) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_sqrt0_s((__frs)); \ + }) + +#define XT_SSI(frt, ars, imm8x4) \ + ({ \ + xtfloat __frt = (xtfloat)(frt); \ + xtfloat *__ars = (xtfloat *)(ars); \ + __builtin_xtensa_xt_ssi((__frt), (__ars), (imm8x4)); \ + }) + +#define XT_SSIP(frt, ars, imm8x4) \ + ({ \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_ssip((__frt), (xtfloat **)&(ars), (imm8x4)); \ + }) + +#define XT_SSX(frr, ars, art) \ + ({ \ + xtfloat __frr = (xtfloat)(frr); \ + xtfloat *__ars = (xtfloat *)(ars); \ + int __art = (int)(art); \ + __builtin_xtensa_xt_ssx((__frr), (__ars), (__art)); \ + }) + +#define XT_SSXP(frr, ars, art) \ + ({ \ + xtfloat __frr = (xtfloat)(frr); \ + int __art = (int)(art); \ + __builtin_xtensa_xt_ssxp((__frr), (xtfloat **)&(ars), (__art)); \ + }) + +#define XT_SUB_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_sub_s((__frs), (__frt)); \ + }) + +#define XT_TRUNC_S(frs, imm_t) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_trunc_s((__frs), (imm_t)); \ + }) + +#define XT_UEQ_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_ueq_s((__frs), (__frt)); \ + }) + +#define XT_UFLOAT_S(ars, imm_t) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_xt_ufloat_s((__ars), (imm_t)); \ + }) + +#define XT_ULE_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_ule_s((__frs), (__frt)); \ + }) + +#define XT_ULT_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_ult_s((__frs), (__frt)); \ + }) + +#define XT_UN_S(frs, frt) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + xtfloat __frt = (xtfloat)(frt); \ + __builtin_xtensa_xt_un_s((__frs), (__frt)); \ + }) + +#define XT_UTRUNC_S(frs, imm_t) \ + ({ \ + xtfloat __frs = (xtfloat)(frs); \ + __builtin_xtensa_xt_utrunc_s((__frs), (imm_t)); \ + }) + +#define XT_WFR(ars) \ + ({ \ + int __ars = (int)(ars); \ + __builtin_xtensa_xt_wfr((__ars)); \ + }) + +#define XT_WUR_FCR(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_xt_wur_fcr((__art)); \ + }) + +#define XT_WUR_FSR(art) \ + ({ \ + int __art = (int)(art); \ + __builtin_xtensa_xt_wur_fsr((__art)); \ + }) + +#endif /* __XTENSAHIFI3INTRIN_H */ From 0d73ca12181634a3565d972b606f90c62b429167 Mon Sep 17 00:00:00 2001 From: Maciej Czekaj Date: Mon, 16 Oct 2023 10:42:09 +0000 Subject: [PATCH 230/261] [Xtensa] Add support for decoding from HIFI namespace --- .../Disassembler/XtensaDisassembler.cpp | 52 +++++++++++++++++-- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 2265dd99b609d7..64ce0e4ab9b4bb 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -44,6 +44,11 @@ class XtensaDisassembler : public MCDisassembler { bool hasESP32S3Ops() const { return STI.getFeatureBits()[Xtensa::FeatureESP32S3Ops]; + + } + + bool hasHIFI3() const { + return STI.getFeatureBits()[Xtensa::FeatureHIFI3]; } DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, @@ -832,7 +837,7 @@ static DecodeStatus decodeMem32nOperand(MCInst &Inst, uint64_t Imm, /// Read two bytes from the ArrayRef and return 16 bit data sorted /// according to the given endianness. static DecodeStatus readInstruction16(ArrayRef Bytes, uint64_t Address, - uint64_t &Size, uint32_t &Insn, + uint64_t &Size, uint64_t &Insn, bool IsLittleEndian) { // We want to read exactly 2 Bytes of data. if (Bytes.size() < 2) { @@ -851,7 +856,7 @@ static DecodeStatus readInstruction16(ArrayRef Bytes, uint64_t Address, /// Read three bytes from the ArrayRef and return 24 bit data static DecodeStatus readInstruction24(ArrayRef Bytes, uint64_t Address, - uint64_t &Size, uint32_t &Insn, + uint64_t &Size, uint64_t &Insn, bool IsLittleEndian) { // We want to read exactly 3 Bytes of data. if (Bytes.size() < 3) { @@ -870,7 +875,7 @@ static DecodeStatus readInstruction24(ArrayRef Bytes, uint64_t Address, /// Read three bytes from the ArrayRef and return 32 bit data static DecodeStatus readInstruction32(ArrayRef Bytes, uint64_t Address, - uint64_t &Size, uint32_t &Insn, + uint64_t &Size, uint64_t &Insn, bool IsLittleEndian) { // We want to read exactly 4 Bytes of data. if (Bytes.size() < 4) { @@ -887,13 +892,37 @@ static DecodeStatus readInstruction32(ArrayRef Bytes, uint64_t Address, return MCDisassembler::Success; } +/// Read InstSize bytes from the ArrayRef and return 24 bit data +static DecodeStatus readInstructionN(ArrayRef Bytes, uint64_t Address, + unsigned InstSize, + uint64_t &Size, uint64_t &Insn, + bool IsLittleEndian) { + // We want to read exactly 3 Bytes of data. + if (Bytes.size() < InstSize) { + Size = 0; + return MCDisassembler::Fail; + } + + if (!IsLittleEndian) { + report_fatal_error("Big-endian mode currently is not supported!"); + } else { + Insn = 0; + for (unsigned i = 0; i < InstSize; i++) + Insn |= (Bytes[i] << 8*i); + } + + Size = InstSize; + return MCDisassembler::Success; +} + + #include "XtensaGenDisassemblerTables.inc" DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef Bytes, uint64_t Address, raw_ostream &CS) const { - uint32_t Insn; + uint64_t Insn; DecodeStatus Result; // Parse 16-bit instructions @@ -946,5 +975,20 @@ DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size, } } + if (hasHIFI3()) { + LLVM_DEBUG(dbgs() << "Trying Xtensa HIFI3 24-bit instruction table :\n"); + Result = decodeInstruction(DecoderTableHIFI324, MI, Insn, Address, this, STI); + if(Result != MCDisassembler::Fail) + return Result; + + Result = readInstructionN(Bytes, Address, 48, Size, Insn, IsLittleEndian); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + + LLVM_DEBUG(dbgs() << "Trying Xtensa HIFI3 48-bit instruction table :\n"); + Result = decodeInstruction(DecoderTableHIFI348, MI, Insn, Address, this, STI); + if(Result != MCDisassembler::Fail) + return Result; + } return Result; } From fbb3d276128ae1cc1e76d758d26b672c6f500f1f Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Sat, 24 Feb 2024 11:42:37 +0100 Subject: [PATCH 231/261] [Xtensa] Implement support for `__attribute__((short__call))` and `__attribute__((near))` --- clang/include/clang/Basic/Attr.td | 16 ++++++- clang/include/clang/Basic/AttrDocs.td | 13 +++--- clang/lib/CodeGen/Targets/Xtensa.cpp | 10 +++++ clang/lib/Sema/SemaDeclAttr.cpp | 43 +++++++++++++++++++ clang/test/CodeGen/Xtensa/xtensa-short-call.c | 16 +++++++ ...a-attribute-supported-attributes-list.test | 2 +- llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 6 ++- 7 files changed, 96 insertions(+), 10 deletions(-) create mode 100644 clang/test/CodeGen/Xtensa/xtensa-short-call.c diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 58838b01b4fd7c..a48fd80aa2b99e 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -449,6 +449,7 @@ def TargetX86 : TargetArch<["x86"]>; def TargetAnyX86 : TargetArch<["x86", "x86_64"]>; def TargetWebAssembly : TargetArch<["wasm32", "wasm64"]>; def TargetNVPTX : TargetArch<["nvptx", "nvptx64"]>; +def TargetXtensa : TargetArch<["xtensa"]>; def TargetWindows : TargetSpec { let OSes = ["Win32"]; } @@ -1810,11 +1811,22 @@ def MipsLongCall : InheritableAttr, TargetSpecificAttr { def MipsShortCall : InheritableAttr, TargetSpecificAttr { let Spellings = [GCC<"short_call">, GCC<"near">]; let Subjects = SubjectList<[Function]>; - let Documentation = [MipsShortCallStyleDocs]; - let SimpleHandler = 1; + let Documentation = [ShortCallStyleDocs]; + let ParseKind = "ShortCall"; + let HasCustomParsing = 1; + let SemaHandler = 1; } def : MutualExclusions<[MipsLongCall, MipsShortCall]>; +def XtensaShortCall : InheritableAttr, TargetSpecificAttr { + let Spellings = [GCC<"short_call">, GCC<"near">]; + let Subjects = SubjectList<[Function]>; + let Documentation = [ShortCallStyleDocs]; + let ParseKind = "ShortCall"; + let HasCustomParsing = 1; + let SemaHandler = 1; +} + def M68kInterrupt : InheritableAttr, TargetSpecificAttr { // NOTE: If you add any additional spellings, ARMInterrupt's, MipsInterrupt's // MSP430Interrupt's and AnyX86Interrupt's spellings must match. diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index e02a1201e2ad79..7abee6916aee8e 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -2349,18 +2349,19 @@ as ``-mlong-calls`` and ``-mno-long-calls``. }]; } -def MipsShortCallStyleDocs : Documentation { +def ShortCallStyleDocs : Documentation { let Category = DocCatFunction; let Heading = "short_call, near"; let Content = [{ Clang supports the ``__attribute__((long_call))``, ``__attribute__((far))``, ``__attribute__((short__call))``, and ``__attribute__((near))`` attributes -on MIPS targets. These attributes may only be added to function declarations -and change the code generated by the compiler when directly calling +on MIPS and Xtensa targets. These attributes may only be added to function +declarations and change the code generated by the compiler when directly calling the function. The ``short_call`` and ``near`` attributes are synonyms and -allow calls to the function to be made using the ``jal`` instruction, which -requires the function to be located in the same naturally aligned 256MB segment -as the caller. The ``long_call`` and ``far`` attributes are synonyms and +allow calls to the function to be made using the ``jal`` instruction for MIPS and +``calln`` instruction for Xtensa, which requires the function to be located +in the same naturally aligned 256MB segment as the caller. +The ``long_call`` and ``far`` attributes are synonyms and require the use of a different call sequence that works regardless of the distance between the functions. diff --git a/clang/lib/CodeGen/Targets/Xtensa.cpp b/clang/lib/CodeGen/Targets/Xtensa.cpp index b615ce7913526f..22b11b78a249fd 100644 --- a/clang/lib/CodeGen/Targets/Xtensa.cpp +++ b/clang/lib/CodeGen/Targets/Xtensa.cpp @@ -257,6 +257,16 @@ class XtensaTargetCodeGenInfo : public TargetCodeGenInfo { public: XtensaTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) : TargetCodeGenInfo(std::make_unique(CGT)) {} + + void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, + CodeGen::CodeGenModule &CGM) const override { + const FunctionDecl *FD = dyn_cast_or_null(D); + if (!FD) + return; + llvm::Function *Fn = cast(GV); + if (FD->hasAttr()) + Fn->addFnAttr("short-call"); + } }; } // namespace diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 6f462de4be78ba..51e472b2cc2e56 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -7710,6 +7710,32 @@ static void handleAVRSignalAttr(Sema &S, Decl *D, const ParsedAttr &AL) { handleSimpleAttribute(S, D, AL); } +static void handleMipsShortCall(Sema &S, Decl *D, const ParsedAttr &AL) { + if (!isFunctionOrMethod(D)) { + S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type) + << "'short_call'" << ExpectedFunction; + return; + } + + if (!AL.checkExactlyNumArgs(S, 0)) + return; + + handleSimpleAttribute(S, D, AL); +} + +static void handleXtensaShortCall(Sema &S, Decl *D, const ParsedAttr &AL){ + if (!isFunctionOrMethod(D)) { + S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type) + << "'short_call'" << ExpectedFunction; + return; + } + + if (!AL.checkExactlyNumArgs(S, 0)) + return; + + handleSimpleAttribute(S, D, AL); +} + static void handleBPFPreserveAIRecord(Sema &S, RecordDecl *RD) { // Add preserve_access_index attribute to all fields and inner records. for (auto *D : RD->decls()) { @@ -7907,6 +7933,20 @@ static void handleRISCVInterruptAttr(Sema &S, Decl *D, D->addAttr(::new (S.Context) RISCVInterruptAttr(S.Context, AL, Kind)); } +static void handleShortCallAttr(Sema &S, Decl *D, const ParsedAttr &AL) { + switch (S.Context.getTargetInfo().getTriple().getArch()) { + case llvm::Triple::xtensa: + handleXtensaShortCall(S, D, AL); + break; + case llvm::Triple::mips64: + case llvm::Triple::mips: + handleMipsShortCall(S, D, AL); + break; + default: + break; + } +} + static void handleInterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) { // Dispatch the interrupt attribute based on the current target. switch (S.Context.getTargetInfo().getTriple().getArch()) { @@ -9851,6 +9891,9 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, case ParsedAttr::AT_UsingIfExists: handleSimpleAttribute(S, D, AL); break; + case ParsedAttr::AT_ShortCall: + handleShortCallAttr(S, D, AL); + break; } } diff --git a/clang/test/CodeGen/Xtensa/xtensa-short-call.c b/clang/test/CodeGen/Xtensa/xtensa-short-call.c new file mode 100644 index 00000000000000..54858ff5d4ec1a --- /dev/null +++ b/clang/test/CodeGen/Xtensa/xtensa-short-call.c @@ -0,0 +1,16 @@ +// RUN: %clang_cc1 -triple xtensa -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple xtensa -S -o - %s | FileCheck %s --check-prefix=ASM + +void foo1 (void); +void __attribute__((short_call)) foo (void); +void __attribute__((near)) bar (void) { foo1(); foo(); } + +// CHECK: define{{.*}} void @bar() [[NEAR:#[0-9]+]] + +// CHECK: declare void @foo() [[SHORTDECL:#[0-9]+]] + +// CHECK: attributes [[NEAR]] = { {{.*}} "short-call" {{.*}} } +// CHECK: attributes [[SHORTDECL]] = { {{.*}} "short-call" {{.*}} } + +// ASM: callx8 a8 +// ASM: call8 foo diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test index e476c15b35ded9..339ba768877a66 100644 --- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test +++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test @@ -99,7 +99,7 @@ // CHECK-NEXT: MinVectorWidth (SubjectMatchRule_function) // CHECK-NEXT: Mips16 (SubjectMatchRule_function) // CHECK-NEXT: MipsLongCall (SubjectMatchRule_function) -// CHECK-NEXT: MipsShortCall (SubjectMatchRule_function) +// CHECK-NEXT: ShortCall (SubjectMatchRule_function) // CHECK-NEXT: NSConsumed (SubjectMatchRule_variable_is_parameter) // CHECK-NEXT: NSConsumesSelf (SubjectMatchRule_objc_method) // CHECK-NEXT: NSErrorDomain (SubjectMatchRule_enum) diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 6b0964c375f97a..2260ccc43ee428 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -1403,6 +1403,7 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, std::string name; unsigned char TF = 0; + bool HasShortCallAttr = false; // Accept direct calls by converting symbolic call addresses to the // associated Target* opcodes. @@ -1422,9 +1423,12 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, const GlobalValue *GV = G->getGlobal(); name = GV->getName().str(); + if (auto *F = dyn_cast(GV)) + if (F->hasFnAttribute("short-call")) + HasShortCallAttr = true; } - if ((!name.empty()) && isLongCall(name.c_str())) { + if (!name.empty() && isLongCall(name.c_str()) && !HasShortCallAttr) { // Create a constant pool entry for the callee address XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier; From b21921c150cda4d834f3a0f2396e42ceaccb8810 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Thu, 19 Oct 2023 18:06:44 +0300 Subject: [PATCH 232/261] [RISCV] Add 'tcontrol' CSR register --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 43475e825b46fb..33eb1d850caea4 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -312,6 +312,7 @@ def : SysReg<"tselect", 0x7A0>; def : SysReg<"tdata1", 0x7A1>; def : SysReg<"tdata2", 0x7A2>; def : SysReg<"tdata3", 0x7A3>; +def : SysReg<"tcontrol", 0x7A5>; def : SysReg<"mcontext", 0x7A8>; //===----------------------------------------------------------------------===// From efb2b160ba1b97577a3a28649e5f1de718481602 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 27 Mar 2024 23:07:10 +0300 Subject: [PATCH 233/261] [Toolchain][RISCV][Xtensa] Add Espressif baremetal. --- clang/include/clang/Driver/ToolChain.h | 2 +- clang/lib/Driver/CMakeLists.txt | 1 + clang/lib/Driver/Driver.cpp | 8 +- clang/lib/Driver/ToolChains/BareMetal.cpp | 50 +- clang/lib/Driver/ToolChains/BareMetal.h | 10 +- clang/lib/Driver/ToolChains/EspBareMetal.cpp | 299 +++++++++ clang/lib/Driver/ToolChains/EspBareMetal.h | 94 +++ .../CodeGen/Xtensa/xtensa-ee-intrinsics.c | 2 +- .../bin/ld.lld} | 0 .../bin/riscv32-esp-elf-as} | 0 .../bin/riscv32-esp-elf-ld} | 0 .../lib/clang-runtimes/multilib.yaml | 248 +++++++ .../include/c++/11.2.0}/.keep | 0 .../include/c++/v1}/.keep | 0 .../include/c++/11.2.0/.keep} | 0 .../include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../bin/ld.lld} | 0 .../bin/xtensa-esp32-elf-as} | 0 .../bin/xtensa-esp32-elf-ld | 1 + .../bin/xtensa-esp32s2-elf-as | 1 + .../bin/xtensa-esp32s2-elf-ld | 1 + .../bin/xtensa-esp32s3-elf-as | 1 + .../bin/xtensa-esp32s3-elf-ld | 1 + .../lib/clang-runtimes/multilib.yaml | 236 +++++++ .../esp32/include/c++/11.2.0/.keep} | 0 .../esp32/include/c++/v1/.keep} | 0 .../esp32}/lib/libclang_rt.builtins.a | 0 .../esp32_no-rtti/include/c++/11.2.0/.keep} | 0 .../esp32_no-rtti/include/c++/v1/.keep} | 0 .../esp32_no-rtti}/lib/libclang_rt.builtins.a | 0 .../esp32_psram/include/c++/11.2.0/.keep} | 0 .../esp32_psram/include/c++/v1/.keep} | 0 .../esp32_psram}/lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../esp32_psram_no-rtti/include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../esp32s2/include/c++/11.2.0/.keep} | 0 .../esp32s2/include/c++/v1/.keep} | 0 .../esp32s2}/lib/libclang_rt.builtins.a | 0 .../esp32s2_no-rtti/include/c++/11.2.0/.keep} | 0 .../esp32s2_no-rtti/include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../esp32s3/include/c++/11.2.0/.keep} | 0 .../esp32s3/include/c++/v1/.keep} | 0 .../esp32s3}/lib/libclang_rt.builtins.a | 0 .../esp32s3_no-rtti/include/c++/11.2.0/.keep} | 0 .../esp32s3_no-rtti/include/c++/v1/.keep} | 0 .../lib/libclang_rt.builtins.a | 0 .../include/c++/11.2.0/.keep} | 0 .../8.4.0/rv32imc/ilp32/crtend.o | 0 .../8.4.0/rv32imc/ilp32/no-rtti/crtbegin.o | 0 .../8.4.0/rv32imc/ilp32/no-rtti/crtend.o | 0 .../riscv32-esp-elf/lib/crt0.o | 0 .../riscv32-esp-elf/lib/rv32i/ilp32/crt0.o | 0 .../lib/rv32i/ilp32/no-rtti/crt0.o | 0 .../riscv32-esp-elf/lib/rv32imac/ilp32/crt0.o | 0 .../lib/rv32imac/ilp32/no-rtti/crt0.o | 0 .../lib/rv32imafc/ilp32f/crt0.o | 0 .../lib/rv32imafc/ilp32f/no-rtti/crt0.o | 0 .../riscv32-esp-elf/lib/rv32imc/ilp32/crt0.o | 0 .../lib/rv32imc/ilp32/no-rtti/crt0.o | 0 .../esp32/esp32-psram/lib/clang_rt.crtbegin.o | 0 .../esp32/esp32-psram/lib/clang_rt.crtend.o | 0 .../no-rtti/lib/clang_rt.crtbegin.o | 0 .../esp32-psram/no-rtti/lib/clang_rt.crtend.o | 0 .../esp32/lib/clang_rt.crtbegin.o | 0 .../esp32/lib/clang_rt.crtend.o | 0 .../esp32/no-rtti/lib/clang_rt.crtbegin.o | 0 .../esp32/no-rtti/lib/clang_rt.crtend.o | 0 .../esp32s2/lib/clang_rt.crtbegin.o | 0 .../esp32s2/lib/clang_rt.crtend.o | 0 .../esp32s2/no-rtti/lib/clang_rt.crtbegin.o | 0 .../esp32s2/no-rtti/lib/clang_rt.crtend.o | 0 .../esp32s3/lib/clang_rt.crtbegin.o | 0 .../esp32s3/lib/clang_rt.crtend.o | 0 .../esp32s3/no-rtti/lib/clang_rt.crtbegin.o | 0 .../esp32s3/no-rtti/lib/clang_rt.crtend.o | 0 .../no-rtti/lib/libclang_rt.builtins.a | 0 .../lib/gcc/xtensa-esp32-elf/8.4.0/crtbegin.o | 0 .../lib/gcc/xtensa-esp32-elf/8.4.0/crtend.o | 0 .../8.4.0/esp32-psram/crtbegin.o | 0 .../8.4.0/esp32-psram/crtend.o | 0 .../8.4.0/esp32-psram/no-rtti/crtbegin.o | 0 .../8.4.0/esp32-psram/no-rtti/crtend.o | 0 .../xtensa-esp32-elf/8.4.0/no-rtti/crtbegin.o | 0 .../xtensa-esp32-elf/8.4.0/no-rtti/crtend.o | 0 .../gcc/xtensa-esp32s2-elf/8.4.0/crtbegin.o | 0 .../lib/gcc/xtensa-esp32s2-elf/8.4.0/crtend.o | 0 .../8.4.0/no-rtti/crtbegin.o | 0 .../xtensa-esp32s2-elf/8.4.0/no-rtti/crtend.o | 0 .../gcc/xtensa-esp32s3-elf/8.4.0/crtbegin.o | 0 .../lib/gcc/xtensa-esp32s3-elf/8.4.0/crtend.o | 0 .../8.4.0/no-rtti/crtbegin.o | 0 .../xtensa-esp32s3-elf/8.4.0/no-rtti/crtend.o | 0 .../xtensa-esp32-elf/lib/crt0.o | 0 .../xtensa-esp32-elf/lib/esp32-psram/crt0.o | 0 .../lib/esp32-psram/no-rtti/crt0.o | 0 .../xtensa-esp32-elf/lib/no-rtti/crt0.o | 0 .../xtensa-esp32s2-elf/lib/crt0.o | 0 .../xtensa-esp32s2-elf/lib/no-rtti/crt0.o | 0 .../xtensa-esp32s3-elf/lib/crt0.o | 0 .../xtensa-esp32s3-elf/lib/no-rtti/crt0.o | 0 clang/test/Driver/baremetal-esp.cpp | 618 ++++++++++++++++++ clang/test/Driver/baremetal-sysroot.cpp | 55 ++ .../test/Driver/riscv32-esp-toolchain-extra.c | 115 ---- clang/test/Driver/riscv32-esp-toolchain.c | 325 --------- .../test/Driver/xtensa-esp-toolchain-extra.c | 111 ---- clang/test/Driver/xtensa-toolchain.c | 125 ---- compiler-rt/test/builtins/Unit/lit.cfg.py | 2 +- llvm/include/llvm/TargetParser/Triple.h | 3 + .../Xtensa/AsmParser/XtensaAsmParser.cpp | 12 +- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 19 + llvm/test/MC/Xtensa/Core/processor-control.s | 4 + 135 files changed, 1635 insertions(+), 709 deletions(-) create mode 100644 clang/lib/Driver/ToolChains/EspBareMetal.cpp create mode 100644 clang/lib/Driver/ToolChains/EspBareMetal.h rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-as => basic_riscv32_esp_tree/bin/ld.lld} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld => basic_riscv32_esp_tree/bin/riscv32-esp-elf-as} (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/bin/xtensa-esp32-elf-ld => basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld} (100%) create mode 100644 clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/multilib.yaml rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++/8.4.0 => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/include/c++/11.2.0}/.keep (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0 => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/include/c++/v1}/.keep (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/clang_rt.crtbegin.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/clang_rt.crtend.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32 => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtbegin.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtend.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32 => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtbegin.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtend.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtbegin.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtend.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32 => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtbegin.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtend.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtbegin.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtend.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtbegin.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtend.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtbegin.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtend.o => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32 => basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld => basic_xtensa_esp_tree/bin/ld.lld} (100%) mode change 100755 => 100644 rename clang/test/Driver/Inputs/{multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld => basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as} (100%) create mode 100755 clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld create mode 100755 clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as create mode 100755 clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld create mode 100755 clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as create mode 100755 clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld create mode 100644 clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/multilib.yaml rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtend.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtend.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtend.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtend.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32 => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtend.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2_no-rtti/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtend.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2_no-rtti/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2 => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2_no-rtti}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s3/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/crtend.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s3/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s3}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/no-rtti/crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s3_no-rtti/include/c++/11.2.0/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f/no-rtti/crtend.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s3_no-rtti/include/c++/v1/.keep} (100%) rename clang/test/Driver/Inputs/{multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3 => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s3_no-rtti}/lib/libclang_rt.builtins.a (100%) rename clang/test/Driver/Inputs/{multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtbegin.o => basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/include/c++/11.2.0/.keep} (100%) delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/no-rtti/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/no-rtti/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32i/ilp32/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32i/ilp32/no-rtti/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imac/ilp32/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imac/ilp32/no-rtti/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imafc/ilp32f/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imafc/ilp32f/no-rtti/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/no-rtti/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/libclang_rt.builtins.a delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/no-rtti/crtbegin.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/no-rtti/crtend.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/no-rtti/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/no-rtti/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/no-rtti/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/crt0.o delete mode 100644 clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/no-rtti/crt0.o create mode 100644 clang/test/Driver/baremetal-esp.cpp delete mode 100644 clang/test/Driver/riscv32-esp-toolchain-extra.c delete mode 100644 clang/test/Driver/riscv32-esp-toolchain.c delete mode 100644 clang/test/Driver/xtensa-esp-toolchain-extra.c delete mode 100644 clang/test/Driver/xtensa-toolchain.c diff --git a/clang/include/clang/Driver/ToolChain.h b/clang/include/clang/Driver/ToolChain.h index 2d0c1f826c1728..81216f157364e6 100644 --- a/clang/include/clang/Driver/ToolChain.h +++ b/clang/include/clang/Driver/ToolChain.h @@ -306,7 +306,7 @@ class ToolChain { /// function should be extended. /// To allow users to find out what flags are returned, clang accepts a /// -print-multi-flags-experimental argument. - Multilib::flags_list getMultilibFlags(const llvm::opt::ArgList &) const; + virtual Multilib::flags_list getMultilibFlags(const llvm::opt::ArgList &) const; SanitizerArgs getSanitizerArgs(const llvm::opt::ArgList &JobArgs) const; diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt index 68e81b42acf3a1..3a07d39645cf64 100644 --- a/clang/lib/Driver/CMakeLists.txt +++ b/clang/lib/Driver/CMakeLists.txt @@ -53,6 +53,7 @@ add_clang_library(clangDriver ToolChains/Cuda.cpp ToolChains/Darwin.cpp ToolChains/DragonFly.cpp + ToolChains/EspBareMetal.cpp ToolChains/Flang.cpp ToolChains/FreeBSD.cpp ToolChains/Fuchsia.cpp diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 19f9392157f07c..15ecddca844c47 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -19,6 +19,7 @@ #include "ToolChains/Cuda.h" #include "ToolChains/Darwin.h" #include "ToolChains/DragonFly.h" +#include "ToolChains/EspBareMetal.h" #include "ToolChains/FreeBSD.h" #include "ToolChains/Fuchsia.h" #include "ToolChains/Gnu.h" @@ -6369,6 +6370,8 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args)) TC = std::make_unique(*this, Target, Args); + else if (Target.getVendor() == llvm::Triple::Espressif) + TC = std::make_unique(*this, Target, Args); else TC = std::make_unique(*this, Target, Args); break; @@ -6383,7 +6386,10 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, TC = std::make_unique(*this, Target, Args); break; case llvm::Triple::xtensa: - TC = std::make_unique(*this, Target, Args); + if (Target.getVendor() == llvm::Triple::Espressif) + TC = std::make_unique(*this, Target, Args); + else + TC = std::make_unique(*this, Target, Args); break; default: if (toolchains::BareMetal::handlesTarget(Target)) diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp b/clang/lib/Driver/ToolChains/BareMetal.cpp index 391c47f88bde2b..445cc5f3f19964 100644 --- a/clang/lib/Driver/ToolChains/BareMetal.cpp +++ b/clang/lib/Driver/ToolChains/BareMetal.cpp @@ -98,15 +98,16 @@ static bool findRISCVMultilibs(const Driver &D, } BareMetal::BareMetal(const Driver &D, const llvm::Triple &Triple, - const ArgList &Args) + const ArgList &Args, bool detectMultilibs) : ToolChain(D, Triple, Args) { getProgramPaths().push_back(getDriver().getInstalledDir()); if (getDriver().getInstalledDir() != getDriver().Dir) getProgramPaths().push_back(getDriver().Dir); - findMultilibs(D, Triple, Args); + if (detectMultilibs) + findMultilibs(D, Triple, Args); SmallString<128> SysRoot(computeSysRoot()); - if (!SysRoot.empty()) { + if (!SysRoot.empty() && detectMultilibs) { for (const Multilib &M : getOrderedMultilibs()) { SmallString<128> Dir(SysRoot); llvm::sys::path::append(Dir, M.osSuffix(), "lib"); @@ -291,6 +292,28 @@ void BareMetal::addClangTargetOptions(const ArgList &DriverArgs, CC1Args.push_back("-nostdsysteminc"); } +void BareMetal::DetectAndAppendGCCVersion(const Driver &D, + SmallString<128> &Dir) const { + std::error_code EC; + Generic_GCC::GCCVersion Version = {"", -1, -1, -1, "", "", ""}; + + // Walk the subdirs, and find the one with the newest gcc version: + for (llvm::vfs::directory_iterator LI = D.getVFS().dir_begin(Dir.str(), EC), + LE; + !EC && LI != LE; LI = LI.increment(EC)) { + StringRef VersionText = llvm::sys::path::filename(LI->path()); + auto CandidateVersion = Generic_GCC::GCCVersion::Parse(VersionText); + if (CandidateVersion.Major == -1) + continue; + if (CandidateVersion <= Version) + continue; + Version = CandidateVersion; + } + if (Version.Major == -1) + return; // no GCC version found, do not append it + llvm::sys::path::append(Dir, Version.Text); +} + void BareMetal::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { if (DriverArgs.hasArg(options::OPT_nostdinc, options::OPT_nostdlibinc, @@ -321,25 +344,8 @@ void BareMetal::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs, } case ToolChain::CST_Libstdcxx: { llvm::sys::path::append(Dir, "include", "c++"); - std::error_code EC; - Generic_GCC::GCCVersion Version = {"", -1, -1, -1, "", "", ""}; - // Walk the subdirs, and find the one with the newest gcc version: - for (llvm::vfs::directory_iterator - LI = D.getVFS().dir_begin(Dir.str(), EC), - LE; - !EC && LI != LE; LI = LI.increment(EC)) { - StringRef VersionText = llvm::sys::path::filename(LI->path()); - auto CandidateVersion = Generic_GCC::GCCVersion::Parse(VersionText); - if (CandidateVersion.Major == -1) - continue; - if (CandidateVersion <= Version) - continue; - Version = CandidateVersion; - } - if (Version.Major != -1) { - llvm::sys::path::append(Dir, Version.Text); - addSystemInclude(DriverArgs, CC1Args, Dir.str()); - } + DetectAndAppendGCCVersion(D, Dir); + addSystemInclude(DriverArgs, CC1Args, Dir.str()); break; } } diff --git a/clang/lib/Driver/ToolChains/BareMetal.h b/clang/lib/Driver/ToolChains/BareMetal.h index 67b5aa5998fc3d..f915bff8f4907b 100644 --- a/clang/lib/Driver/ToolChains/BareMetal.h +++ b/clang/lib/Driver/ToolChains/BareMetal.h @@ -22,7 +22,7 @@ namespace toolchains { class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain { public: BareMetal(const Driver &D, const llvm::Triple &Triple, - const llvm::opt::ArgList &Args); + const llvm::opt::ArgList &Args, bool detectMultilibs = true); ~BareMetal() override = default; static bool handlesTarget(const llvm::Triple &Triple); @@ -31,6 +31,8 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain { const llvm::opt::ArgList &Args); protected: + void DetectAndAppendGCCVersion(const Driver &D, + SmallString<128> &Dir) const; Tool *buildLinker() const override; Tool *buildStaticLibTool() const override; @@ -64,17 +66,17 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain { addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, Action::OffloadKind DeviceOffloadKind) const override; - void AddClangCXXStdlibIncludeArgs( + virtual void AddClangCXXStdlibIncludeArgs( const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; - void AddCXXStdlibLibArgs(const llvm::opt::ArgList &Args, + virtual void AddCXXStdlibLibArgs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const override; void AddLinkRuntimeLib(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const; std::string computeSysRoot() const override; SanitizerMask getSupportedSanitizers() const override; -private: +protected: using OrderedMultilibs = llvm::iterator_range::const_reverse_iterator>; OrderedMultilibs getOrderedMultilibs() const; diff --git a/clang/lib/Driver/ToolChains/EspBareMetal.cpp b/clang/lib/Driver/ToolChains/EspBareMetal.cpp new file mode 100644 index 00000000000000..d88d3fcc50a186 --- /dev/null +++ b/clang/lib/Driver/ToolChains/EspBareMetal.cpp @@ -0,0 +1,299 @@ +//===-- BareMetal.cpp - Bare Metal ToolChain --------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "EspBareMetal.h" + +#include "CommonArgs.h" +#include "Gnu.h" +#include "clang/Driver/InputInfo.h" + +#include "Arch/RISCV.h" +#include "clang/Driver/Compilation.h" +#include "clang/Driver/Driver.h" +#include "clang/Driver/DriverDiagnostic.h" +#include "clang/Driver/Options.h" +#include "clang/Driver/MultilibBuilder.h" +#include "llvm/ADT/StringSet.h" +#include "llvm/Option/ArgList.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/VirtualFileSystem.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; +using namespace llvm::opt; +using namespace clang; +using namespace clang::driver; +using namespace clang::driver::tools; +using namespace clang::driver::toolchains; + + +EspBareMetal::EspBareMetal(const Driver &D, const llvm::Triple &Triple, + const ArgList &Args) + : BareMetal(D, Triple, Args, false) { + + findMultilibs(D, Triple, Args); + SmallString<128> SysRoot(computeSysRoot()); + if (!SysRoot.empty()) { + for (const Multilib &M : getOrderedMultilibs()) { + SmallString<128> Dir(SysRoot); + llvm::sys::path::append(Dir, M.osSuffix(), "lib"); + getFilePaths().push_back(std::string(Dir)); + getLibraryPaths().push_back(std::string(Dir)); + } + } + + // TODO: Add full support for Xtensa to integrated asm + // LLVM-290, LLVM-291 + if (Triple.getArch() == llvm::Triple::xtensa) { + for (auto *A : Args) { + std::string Str = A->getAsString(Args); + // Currently don't use integrated assembler for assembler input files + if ((IsIntegratedAsm) && (Str.length() > 2)) { + std::string ExtSubStr = Str.substr(Str.length() - 2); + if (!ExtSubStr.compare(".s")) + IsIntegratedAsm = false; + if (!ExtSubStr.compare(".S")) + IsIntegratedAsm = false; + } + } + if (IsIntegratedAsm) { + if (Args.getLastArgValue(options::OPT_x).equals("assembler")) + IsIntegratedAsm = false; + + if (Args.getLastArgValue(options::OPT_x).equals("assembler-with-cpp")) + IsIntegratedAsm = false; + } + } +} + +void EspBareMetal::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs, + ArgStringList &CC1Args) const { + if (DriverArgs.hasArg(options::OPT_nostdinc) || + DriverArgs.hasArg(options::OPT_nostdlibinc) || + DriverArgs.hasArg(options::OPT_nostdincxx)) + return; + + const Driver &D = getDriver(); + std::string SysRoot(computeSysRoot()); + if (SysRoot.empty()) + return; + + BareMetal::AddClangCXXStdlibIncludeArgs(DriverArgs, CC1Args); + + // add include path to non-multilib libsdtcxx headers + if(GetCXXStdlibType(DriverArgs) == ToolChain::CST_Libstdcxx) { + // computed SysRoot points to clang-runtimes + SmallString<128> Dir(SysRoot); + llvm::sys::path::append(Dir, getTriple().str(), "include", "c++"); + DetectAndAppendGCCVersion(D, Dir); + addSystemInclude(DriverArgs, CC1Args, Dir.str()); + } +} + +void EspBareMetal::AddCXXStdlibLibArgs(const ArgList &Args, + ArgStringList &CmdArgs) const { + switch (GetCXXStdlibType(Args)) { + case ToolChain::CST_Libcxx: + CmdArgs.push_back("-lc++"); + if (Args.hasArg(options::OPT_fexperimental_library)) + CmdArgs.push_back("-lc++experimental"); + CmdArgs.push_back("-lc++abi"); + CmdArgs.push_back("-lunwind"); + break; + case ToolChain::CST_Libstdcxx: + CmdArgs.push_back("-lstdc++"); + break; + } +} + +static void getRISCV32MultilibFlags(const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + Multilib::flags_list &Result) { + + Result.push_back("-march=" + riscv::getRISCVArch(Args, Triple).str()); + Result.push_back("-mabi=" + riscv::getRISCVABI(Args, Triple).str()); +} + +static void getXtensaMultilibFlags(const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + Multilib::flags_list &Result) { + + if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) + Result.push_back(A->getAsString(Args)); + else + Result.push_back("-mcpu=esp32"); + + if (Args.hasArg(options::OPT_mfix_esp32_psram_cache_issue)) + Result.push_back("-mfix-esp32-psram-cache-issue"); +} + +Multilib::flags_list +EspBareMetal::getMultilibFlags(const llvm::opt::ArgList &Args) const { + + std::vector Result; + const llvm::Triple Triple(ComputeEffectiveClangTriple(Args)); + + if (Triple.getVendor() != llvm::Triple::Espressif) + return BareMetal::getMultilibFlags(Args); + + Result.push_back("--target=" + Triple.str()); + + if (Args.hasArg(options::OPT_fno_rtti)) + Result.push_back("-fno-rtti"); + + switch (Triple.getArch()) { + case llvm::Triple::riscv32: + getRISCV32MultilibFlags(Triple, Args, Result); + break; + case llvm::Triple::xtensa: + getXtensaMultilibFlags(Triple, Args, Result); + break; + default: + break; + } + + // Sort and remove duplicates. + std::sort(Result.begin(), Result.end()); + Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); + return Result; +} + +Tool *EspBareMetal::buildLinker() const { + return new tools::baremetal::esp::Linker(*this); +} + +Tool *EspBareMetal::buildAssembler() const { + return new tools::baremetal::esp::Assembler(*this); +} + +void baremetal::esp::Linker::ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, + const InputInfoList &Inputs, + const ArgList &Args, + const char *LinkingOutput) const { + auto &ToolChain = static_cast(getToolChain()); + const Driver &D = ToolChain.getDriver(); + ArgStringList CmdArgs; + + if (!D.SysRoot.empty()) + CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot)); + + if (ToolChain.getArch() == llvm::Triple::riscv32) { + CmdArgs.push_back("-m"); + CmdArgs.push_back("elf32lriscv"); + } + + CmdArgs.push_back("-o"); + CmdArgs.push_back(Output.getFilename()); + + CmdArgs.push_back("-X"); + + std::string Linker = ToolChain.GetLinkerPath(); + + bool WantCRTs = + !Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles); + + if (WantCRTs) { + /* Espressif toolcahin uses newlib. crt0.o from it refers to 'main' symbol. + In 'freestanding' mode 'main' is not marked as special symbol by clang, + so when compiling C++ program with 'clang++' 'main' gets mmangled + (if not decalred as 'extern "C"' ) and linker can not resolve it. + The problem can happen, for example, when cmake checks C++ compiler by buiding simple C++ code, + unfortunately 'main' function in that code is not decalred as 'extern "C"'. */ + bool Freestanding = + Args.hasFlag(options::OPT_ffreestanding, options::OPT_fhosted, false); + if (!Freestanding) { + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); + } + } + + AddLinkerInputs(ToolChain, Inputs, Args, CmdArgs, JA); + + Args.AddAllArgs(CmdArgs, options::OPT_L); + Args.AddAllArgs(CmdArgs, options::OPT_u); + ToolChain.AddFilePathLibArgs(Args, CmdArgs); + Args.AddAllArgs(CmdArgs, + {options::OPT_T_Group, options::OPT_e, options::OPT_s, + options::OPT_t, options::OPT_Z_Flag, options::OPT_r}); + + // TODO: add C++ includes and libs if compiling C++. + + if (!Args.hasArg(options::OPT_nostdlib) && + !Args.hasArg(options::OPT_nodefaultlibs)) { + if (ToolChain.ShouldLinkCXXStdlib(Args)) + ToolChain.AddCXXStdlibLibArgs(Args, CmdArgs); + CmdArgs.push_back("-lm"); + CmdArgs.push_back("--start-group"); + CmdArgs.push_back("-lc"); + CmdArgs.push_back("-lgloss"); + CmdArgs.push_back("-lnosys"); + CmdArgs.push_back("--end-group"); + ToolChain.AddLinkRuntimeLib(Args, CmdArgs); + } + + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), Args.MakeArgString(Linker), + CmdArgs, Inputs, Output)); +} + +void baremetal::esp::Assembler::ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, + const InputInfoList &Inputs, + const ArgList &Args, + const char *LinkingOutput) const { + const auto &TC = static_cast(getToolChain()); + + claimNoWarnArgs(Args); + ArgStringList CmdArgs; + + CmdArgs.push_back("-o"); + CmdArgs.push_back(Output.getFilename()); + + CmdArgs.push_back("-c"); + + if (Args.hasArg(options::OPT_v)) + CmdArgs.push_back("-v"); + + if (Arg *A = Args.getLastArg(options::OPT_g_Group)) + if (!A->getOption().matches(options::OPT_g0)) + CmdArgs.push_back("-g"); + + if (Args.hasFlag(options::OPT_fverbose_asm, options::OPT_fno_verbose_asm, + false)) + CmdArgs.push_back("-fverbose-asm"); + + Args.AddAllArgValues(CmdArgs, options::OPT_Wa_COMMA, options::OPT_Xassembler); + + for (const auto &II : Inputs) + CmdArgs.push_back(II.getFilename()); + + std::string AsmPrefix; + if (TC.getTriple().getArch() == llvm::Triple::xtensa) { + StringRef cpu = Args.getLastArgValue(options::OPT_mcpu_EQ, "esp32"); + // xtensa-esp32-elf + AsmPrefix = TC.getTriple().getArchName().str() + "-" + cpu.str() + "-" + + TC.getTriple().getEnvironmentName().str(); + } else { + // riscv32-esp-elf + if (Args.hasArg(options::OPT_march_EQ)) + Args.AddAllArgs(CmdArgs, options::OPT_march_EQ); + else + CmdArgs.push_back("-march=rv32imac"); + if (Args.hasArg(options::OPT_mabi_EQ)) + Args.AddAllArgs(CmdArgs, options::OPT_mabi_EQ); + else + CmdArgs.push_back("-mabi=ilp32"); + AsmPrefix = TC.getTriple().getArchName().str() + "-" + + TC.getTriple().getVendorName().str() + "-" + + TC.getTriple().getEnvironmentName().str(); + } + SmallString<128> Asm(AsmPrefix + "-" + getShortName()); + C.addCommand( + std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), + Args.MakeArgString(TC.GetProgramPath(Asm.str().str().c_str())), CmdArgs, Inputs)); +} diff --git a/clang/lib/Driver/ToolChains/EspBareMetal.h b/clang/lib/Driver/ToolChains/EspBareMetal.h new file mode 100644 index 00000000000000..ea074937dbb82a --- /dev/null +++ b/clang/lib/Driver/ToolChains/EspBareMetal.h @@ -0,0 +1,94 @@ +//===--- EspBareMetal.h - Espressif Bare Metal Tool and ToolChain ------------*- C++-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_ESPBAREMETAL_H +#define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_ESPBAREMETAL_H + +#include "BareMetal.h" + +namespace clang { +namespace driver { + +namespace toolchains { + +class LLVM_LIBRARY_VISIBILITY EspBareMetal : public BareMetal { +public: + EspBareMetal(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args); + + ~EspBareMetal() override = default; + +protected: + Tool *buildLinker() const override; + Tool *buildAssembler() const override; + +public: + // BareMetal forces to use integrated ASM, we wnat to be more flexible + // and allow users to to switch to GNU ASM using command line + bool useIntegratedAs() const override { return ToolChain::useIntegratedAs(); } + bool IsIntegratedAssemblerDefault() const override { return IsIntegratedAsm; } + + RuntimeLibType GetDefaultRuntimeLibType() const override { + return ToolChain::RLT_CompilerRT; + } + CXXStdlibType GetDefaultCXXStdlibType() const override { + return ToolChain::CST_Libstdcxx; + } + + void AddClangCXXStdlibIncludeArgs( + const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args) const override; + + const char *getDefaultLinker() const override { return "ld.lld"; } + + void AddCXXStdlibLibArgs(const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const override; + + virtual Multilib::flags_list getMultilibFlags(const llvm::opt::ArgList &) const override; + +private: + bool IsIntegratedAsm = true; +}; + +} // namespace toolchains + +namespace tools { +namespace baremetal { +namespace esp { + +class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +public: + Linker(const ToolChain &TC) : Tool("baremetal::esp::Linker", "ld", TC) {} + bool isLinkJob() const override { return true; } + bool hasIntegratedCPP() const override { return false; } + void ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, const InputInfoList &Inputs, + const llvm::opt::ArgList &TCArgs, + const char *LinkingOutput) const override; +}; + +class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +public: + Assembler(const ToolChain &TC) + : Tool("baremetal::esp::Assembler", "as", TC) {} + + bool hasIntegratedCPP() const override { return false; } + void ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, const InputInfoList &Inputs, + const llvm::opt::ArgList &TCArgs, + const char *LinkingOutput) const override; +}; + +} // namespace esp +} // namespace baremetal +} // namespace tools + +} // namespace driver +} // namespace clang + +#endif diff --git a/clang/test/CodeGen/Xtensa/xtensa-ee-intrinsics.c b/clang/test/CodeGen/Xtensa/xtensa-ee-intrinsics.c index c3ce2e107d8867..3624bff2b318a1 100644 --- a/clang/test/CodeGen/Xtensa/xtensa-ee-intrinsics.c +++ b/clang/test/CodeGen/Xtensa/xtensa-ee-intrinsics.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple xtensa -S -emit-llvm -O0 -o - %s \ +// RUN: %clang_cc1 -triple xtensa -S -emit-llvm -O0 -o - %s \ // RUN: | FileCheck %s #include diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-as b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/ld.lld similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-as rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/ld.lld diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-as similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-as diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld diff --git a/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/multilib.yaml b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/multilib.yaml new file mode 100644 index 00000000000000..c4123d3cfc039c --- /dev/null +++ b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/multilib.yaml @@ -0,0 +1,248 @@ +# +# Copyright (c) 2023, Arm Limited and affiliates. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# If you're reading this file under the name 'multilib.yaml.in' in the +# LLVM-embedded-toolchain-for-Arm source tree, then it's not valid +# YAML in its own right: it's a template that CMakeLists.txt will +# expand into a real 'multilib.yaml' containing a list of library +# variants and the flags that will select them. +# +# If you're reading it under the name 'multilib.yaml' in the build or +# install directory, then that substitution has been done. +# +# Comments in this file mostly make more sense from the +# multilib.yaml.in point of view. + +MultilibVersion: '1.0' + +# The list of library variants is substituted in by CMakeLists.txt, so +# that it can respect the LLVM_TOOLCHAIN_LIBRARY_VARIANTS setting and +# only include the set of libraries actually included in this build. + +Variants: +- Dir: riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32 + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32i_zicsr_zifencei + - -mabi=ilp32 +- Dir: riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32i_zicsr_zifencei + - -mabi=ilp32 + - -fno-rtti +- Dir: riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32 + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imc_zicsr_zifencei + - -mabi=ilp32 +- Dir: riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imc_zicsr_zifencei + - -mabi=ilp32 + - -fno-rtti +- Dir: riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32 + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imac_zicsr_zifencei + - -mabi=ilp32 +- Dir: riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imac_zicsr_zifencei + - -mabi=ilp32 + - -fno-rtti +- Dir: riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imafc_zicsr_zifencei + - -mabi=ilp32f +- Dir: riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imafc_zicsr_zifencei + - -mabi=ilp32f + - -fno-rtti +- Dir: xtensa-esp-unknown-elf/esp32 + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32 +- Dir: xtensa-esp-unknown-elf/esp32_no-rtti + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32 + - -fno-rtti +- Dir: xtensa-esp-unknown-elf/esp32_psram + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32 + - -mfix-esp32-psram-cache-issue +- Dir: xtensa-esp-unknown-elf/esp32_psram_no-rtti + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32 + - -mfix-esp32-psram-cache-issue + - -fno-rtti +- Dir: xtensa-esp-unknown-elf/esp32s2 + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32s2 +- Dir: xtensa-esp-unknown-elf/esp32s2_no-rtti + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32s2 + - -fno-rtti +- Dir: xtensa-esp-unknown-elf/esp32s3 + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32s3 +- Dir: xtensa-esp-unknown-elf/esp32s3_no-rtti + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32s3 + - -fno-rtti + + +Mappings: + +# Map higher architecture versions to subsets of them, so that a +# compatible library can be found even for architectures we don't have +# specific variants for. + +# v8-M Baseline is a superset of v6-M +- Match: --target=thumbv8m\.base-none-unknown-eabi + Flags: + - --target=thumbv6m-none-unknown-eabi + +# v8.2-M Mainline is a superset of v8.1-M Mainline, in both hard and +# soft float variants. +# +# Also, v8.1-M Mainline is also a superset of v8-M Mainline, which in +# turn is a superset of v7E-M, and then of plain v7-M. We have +# libraries for all those architecture versions, but not for every +# combination of them with FPUs, so in some cases it might be +# necessary to fall back to a lower architecture in order to provide +# the needed FPU support. +- Match: --target=thumbv8\.[2-9]m\.main-none-unknown-eabi + Flags: + - --target=thumbv8.1m.main-none-unknown-eabi + - --target=thumbv8m.main-none-unknown-eabi + - --target=thumbv7em-none-unknown-eabi + - --target=thumbv7m-none-unknown-eabi +- Match: --target=thumbv8\.[2-9]m\.main-none-unknown-eabihf + Flags: + - --target=thumbv8.1m.main-none-unknown-eabihf + - --target=thumbv8m.main-none-unknown-eabihf + - --target=thumbv7em-none-unknown-eabihf + - --target=thumbv7m-none-unknown-eabihf +- Match: --target=thumbv8\.1m\.main-none-unknown-eabi + Flags: + - --target=thumbv8m.main-none-unknown-eabi + - --target=thumbv7em-none-unknown-eabi + - --target=thumbv7m-none-unknown-eabi +- Match: --target=thumbv8\.1m\.main-none-unknown-eabihf + Flags: + - --target=thumbv8m.main-none-unknown-eabihf + - --target=thumbv7em-none-unknown-eabihf + - --target=thumbv7m-none-unknown-eabihf +- Match: --target=thumbv8m\.main-none-unknown-eabi + Flags: + - --target=thumbv7em-none-unknown-eabi + - --target=thumbv7m-none-unknown-eabi +- Match: --target=thumbv8m\.main-none-unknown-eabihf + Flags: + - --target=thumbv7em-none-unknown-eabihf + - --target=thumbv7m-none-unknown-eabihf +- Match: --target=thumbv7em-none-unknown-eabi + Flags: + - --target=thumbv7m-none-unknown-eabi +- Match: --target=thumbv7em-none-unknown-eabihf + Flags: + - --target=thumbv7m-none-unknown-eabihf + +# Higher versions of v8-A, and v9-A, are all supersets of v8-A. (And +# of each other, in the obvious way, but we don't have any libraries +# for those at present, so there's no need to generate all their +# flags.) +- Match: --target=armv(8\.[1-9]|9|9\.[1-9])a-none-unknown-eabi + Flags: + - --target=armv8a-none-unknown-eabi + +# -march extensions +- Match: -march=thumbv8\.[1-9]m\.main.*\+fp16.* + Flags: + - -march=thumbv8.1m.main+fp16 +- Match: -march=thumbv8\.[1-9]m\.main.*\+dsp.*\+mve.* + Flags: + - -march=thumbv8.1m.main+dsp+mve +- Match: -march=thumbv8\.[1-9]m\.main.*\+mve\.fp.*\+fp16.*\+lob.* + Flags: + - -march=thumbv8.1m.main+fp16+lob+mve.fp + +# Hierarchy among FPUs: fpvN-d16 is a superset of fpvN-sp-d16, and +# fpvN-d16 is a superset of fpv[N-1]-d16, for all N. +# +# We don't consider any hardware FP configuration to be compatible +# with -mfpu=none. It would work in most cases to cross-call between +# code compiled for an FPU or no FPU, if you were using the soft float +# ABI. But it wouldn't work in all cases: setjmp needs to know whether +# to save FP registers in the jmp_buf, so a non-FPU-aware setjmp would +# not behave correctly if linked into an otherwise FPU-using +# application. Similarly for exception unwinding. So we don't permit +# selecting an -mfpu=none library as a fallback for any hard-FP +# library. +- Match: -mfpu=fpv5-d16 + Flags: + - -mfpu=fpv4-d16 + - -mfpu=fpv5-sp-d16 + - -mfpu=fpv4-sp-d16 +- Match: -mfpu=fpv5-sp-d16 + Flags: + - -mfpu=fpv4-sp-d16 +- Match: -mfpu=fpv4-d16 + Flags: + - -mfpu=fpv4-sp-d16 +- Match: -mfpu=fp-armv8-fullfp16-d16 + Flags: + - -mfpu=fp-armv8-fullfp16-sp-d16 + +# RISCV -march extensions and mappings +- Match: -march=rv32i + Flags: + - -march=rv32i_zicsr_zifencei +- Match: -march=rv32ic + Flags: + - -march=rv32i_zicsr_zifencei +- Match: -march=rv32im + Flags: + - -march=rv32imc_zicsr_zifencei +- Match: -march=rv32imc + Flags: + - -march=rv32imc_zicsr_zifencei +- Match: -march=rv32imac + Flags: + - -march=rv32imac_zicsr_zifencei +- Match: -march=rv32imafc + Flags: + - -march=rv32imafc_zicsr_zifencei +- Match: -march=rv32imafdc + Flags: + - -march=rv32imafc_zicsr_zifencei +- Match: -march=rv32gc + Flags: + - -march=rv32imafc_zicsr_zifencei diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++/8.4.0/.keep b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++/8.4.0/.keep rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0/.keep b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0/.keep rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/ld.lld old mode 100755 new mode 100644 similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/ld.lld diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld new file mode 100755 index 00000000000000..b23e55619b2ff0 --- /dev/null +++ b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld @@ -0,0 +1 @@ +#!/bin/true diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/multilib.yaml b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/multilib.yaml new file mode 100644 index 00000000000000..a03c10799b2d4f --- /dev/null +++ b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/multilib.yaml @@ -0,0 +1,236 @@ +# +# Copyright (c) 2023, Arm Limited and affiliates. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# If you're reading this file under the name 'multilib.yaml.in' in the +# LLVM-embedded-toolchain-for-Arm source tree, then it's not valid +# YAML in its own right: it's a template that CMakeLists.txt will +# expand into a real 'multilib.yaml' containing a list of library +# variants and the flags that will select them. +# +# If you're reading it under the name 'multilib.yaml' in the build or +# install directory, then that substitution has been done. +# +# Comments in this file mostly make more sense from the +# multilib.yaml.in point of view. + +MultilibVersion: '1.0' + +# The list of library variants is substituted in by CMakeLists.txt, so +# that it can respect the LLVM_TOOLCHAIN_LIBRARY_VARIANTS setting and +# only include the set of libraries actually included in this build. + +Variants: +- Dir: riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32 + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32i_zicsr_zifencei + - -mabi=ilp32 +- Dir: riscv32-esp-unknown-elf/rv32i-zicsr-zifencei_ilp32_no-rtti + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32i_zicsr_zifencei + - -mabi=ilp32 + - -fno-rtti +- Dir: riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32 + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imc_zicsr_zifencei + - -mabi=ilp32 +- Dir: riscv32-esp-unknown-elf/rv32imc-zicsr-zifencei_ilp32_no-rtti + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imc_zicsr_zifencei + - -mabi=ilp32 + - -fno-rtti +- Dir: riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32 + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imac_zicsr_zifencei + - -mabi=ilp32 +- Dir: riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32_no-rtti + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imac_zicsr_zifencei + - -mabi=ilp32 + - -fno-rtti +- Dir: riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imafc_zicsr_zifencei + - -mabi=ilp32f +- Dir: riscv32-esp-unknown-elf/rv32imafc-zicsr-zifencei_ilp32f_no-rtti + Flags: + - --target=riscv32-esp-unknown-elf + - -march=rv32imafc_zicsr_zifencei + - -mabi=ilp32f + - -fno-rtti +- Dir: xtensa-esp-unknown-elf/esp32 + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32 +- Dir: xtensa-esp-unknown-elf/esp32_no-rtti + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32 + - -fno-rtti +- Dir: xtensa-esp-unknown-elf/esp32_psram + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32 + - -mfix-esp32-psram-cache-issue +- Dir: xtensa-esp-unknown-elf/esp32_psram_no-rtti + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32 + - -mfix-esp32-psram-cache-issue + - -fno-rtti +- Dir: xtensa-esp-unknown-elf/esp32s2 + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32s2 +- Dir: xtensa-esp-unknown-elf/esp32s2_no-rtti + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32s2 + - -fno-rtti +- Dir: xtensa-esp-unknown-elf/esp32s3 + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32s3 +- Dir: xtensa-esp-unknown-elf/esp32s3_no-rtti + Flags: + - --target=xtensa-esp-unknown-elf + - -mcpu=esp32s3 + - -fno-rtti + + +Mappings: + +# Map higher architecture versions to subsets of them, so that a +# compatible library can be found even for architectures we don't have +# specific variants for. + +# v8-M Baseline is a superset of v6-M +- Match: --target=thumbv8m\.base-none-unknown-eabi + Flags: + - --target=thumbv6m-none-unknown-eabi + +# v8.2-M Mainline is a superset of v8.1-M Mainline, in both hard and +# soft float variants. +# +# Also, v8.1-M Mainline is also a superset of v8-M Mainline, which in +# turn is a superset of v7E-M, and then of plain v7-M. We have +# libraries for all those architecture versions, but not for every +# combination of them with FPUs, so in some cases it might be +# necessary to fall back to a lower architecture in order to provide +# the needed FPU support. +- Match: --target=thumbv8\.[2-9]m\.main-none-unknown-eabi + Flags: + - --target=thumbv8.1m.main-none-unknown-eabi + - --target=thumbv8m.main-none-unknown-eabi + - --target=thumbv7em-none-unknown-eabi + - --target=thumbv7m-none-unknown-eabi +- Match: --target=thumbv8\.[2-9]m\.main-none-unknown-eabihf + Flags: + - --target=thumbv8.1m.main-none-unknown-eabihf + - --target=thumbv8m.main-none-unknown-eabihf + - --target=thumbv7em-none-unknown-eabihf + - --target=thumbv7m-none-unknown-eabihf +- Match: --target=thumbv8\.1m\.main-none-unknown-eabi + Flags: + - --target=thumbv8m.main-none-unknown-eabi + - --target=thumbv7em-none-unknown-eabi + - --target=thumbv7m-none-unknown-eabi +- Match: --target=thumbv8\.1m\.main-none-unknown-eabihf + Flags: + - --target=thumbv8m.main-none-unknown-eabihf + - --target=thumbv7em-none-unknown-eabihf + - --target=thumbv7m-none-unknown-eabihf +- Match: --target=thumbv8m\.main-none-unknown-eabi + Flags: + - --target=thumbv7em-none-unknown-eabi + - --target=thumbv7m-none-unknown-eabi +- Match: --target=thumbv8m\.main-none-unknown-eabihf + Flags: + - --target=thumbv7em-none-unknown-eabihf + - --target=thumbv7m-none-unknown-eabihf +- Match: --target=thumbv7em-none-unknown-eabi + Flags: + - --target=thumbv7m-none-unknown-eabi +- Match: --target=thumbv7em-none-unknown-eabihf + Flags: + - --target=thumbv7m-none-unknown-eabihf + +# Higher versions of v8-A, and v9-A, are all supersets of v8-A. (And +# of each other, in the obvious way, but we don't have any libraries +# for those at present, so there's no need to generate all their +# flags.) +- Match: --target=armv(8\.[1-9]|9|9\.[1-9])a-none-unknown-eabi + Flags: + - --target=armv8a-none-unknown-eabi + +# -march extensions +- Match: -march=thumbv8\.[1-9]m\.main.*\+fp16.* + Flags: + - -march=thumbv8.1m.main+fp16 +- Match: -march=thumbv8\.[1-9]m\.main.*\+dsp.*\+mve.* + Flags: + - -march=thumbv8.1m.main+dsp+mve +- Match: -march=thumbv8\.[1-9]m\.main.*\+mve\.fp.*\+fp16.*\+lob.* + Flags: + - -march=thumbv8.1m.main+fp16+lob+mve.fp + +# Hierarchy among FPUs: fpvN-d16 is a superset of fpvN-sp-d16, and +# fpvN-d16 is a superset of fpv[N-1]-d16, for all N. +# +# We don't consider any hardware FP configuration to be compatible +# with -mfpu=none. It would work in most cases to cross-call between +# code compiled for an FPU or no FPU, if you were using the soft float +# ABI. But it wouldn't work in all cases: setjmp needs to know whether +# to save FP registers in the jmp_buf, so a non-FPU-aware setjmp would +# not behave correctly if linked into an otherwise FPU-using +# application. Similarly for exception unwinding. So we don't permit +# selecting an -mfpu=none library as a fallback for any hard-FP +# library. +- Match: -mfpu=fpv5-d16 + Flags: + - -mfpu=fpv4-d16 + - -mfpu=fpv5-sp-d16 + - -mfpu=fpv4-sp-d16 +- Match: -mfpu=fpv5-sp-d16 + Flags: + - -mfpu=fpv4-sp-d16 +- Match: -mfpu=fpv4-d16 + Flags: + - -mfpu=fpv4-sp-d16 +- Match: -mfpu=fp-armv8-fullfp16-d16 + Flags: + - -mfpu=fp-armv8-fullfp16-sp-d16 + +# RISCV -march extensions +- Match: -march=rv32i + Flags: + - -march=rv32i_zicsr_zifencei +- Match: -march=rv32imc + Flags: + - -march=rv32imc_zicsr_zifencei +- Match: -march=rv32imac + Flags: + - -march=rv32imac_zicsr_zifencei +- Match: -march=rv32imafc + Flags: + - -march=rv32imafc_zicsr_zifencei diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtbegin.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtend.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtend.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtbegin.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtbegin.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtend.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/crtend.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_no-rtti/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtbegin.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtbegin.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtend.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/crtend.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtbegin.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtend.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32/no-rtti/crtend.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32_psram_no-rtti/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtbegin.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtbegin.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtend.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/crtend.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2_no-rtti/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtbegin.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2_no-rtti/include/c++/11.2.0/.keep diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtend.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2_no-rtti/include/c++/v1/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti/crtend.o rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2_no-rtti/include/c++/v1/.keep diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s2_no-rtti/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/libclang_rt.builtins.a rename to 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a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/libclang_rt.builtins.a b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s3_no-rtti/lib/libclang_rt.builtins.a similarity index 100% rename from clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/libclang_rt.builtins.a rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32s3_no-rtti/lib/libclang_rt.builtins.a diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtbegin.o b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/lib/clang-runtimes/xtensa-esp-unknown-elf/include/c++/11.2.0/.keep similarity index 100% rename from clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32/crtbegin.o rename to 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--git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/crt0.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib/rv32imc/ilp32/no-rtti/crt0.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtbegin.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtend.o 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a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/crtend.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtbegin.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/esp32-psram/no-rtti/crtend.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/no-rtti/crtbegin.o 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a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtbegin.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/no-rtti/crtend.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtbegin.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtbegin.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtend.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/crtend.o deleted file mode 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deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/esp32-psram/no-rtti/crt0.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32-elf/lib/no-rtti/crt0.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/crt0.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf/lib/no-rtti/crt0.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/crt0.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/no-rtti/crt0.o b/clang/test/Driver/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf/lib/no-rtti/crt0.o deleted file mode 100644 index e69de29bb2d1d6..00000000000000 diff --git a/clang/test/Driver/baremetal-esp.cpp b/clang/test/Driver/baremetal-esp.cpp new file mode 100644 index 00000000000000..18c1888daad48c --- /dev/null +++ b/clang/test/Driver/baremetal-esp.cpp @@ -0,0 +1,618 @@ +// UNSUPPORTED: system-windows + +//////////////////// RISCV ///////////////////////// + +// IMAC is default and it re-uses IMC sub-dirs + +// RUN: rm -rf %t +// RUN: mkdir -p %t/basic_riscv32_esp_tree/bin +// RUN: ln -s %clang %t/basic_riscv32_esp_tree/bin/clang +// RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/bin/ld.lld %t/basic_riscv32_esp_tree/bin/ld.lld +// RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-as %t/basic_riscv32_esp_tree/bin/riscv32-esp-elf-as +// RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld %t/basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld +// RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/lib %t/basic_riscv32_esp_tree/lib + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -march=rv32imac -mabi=ilp32 \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -rtlib=compiler-rt \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC %s +// CHECK-ESP-RV32IMAC: "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32IMAC-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMAC-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMAC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAC-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-SAME: "-x" "c++" "{{.*}}baremetal-esp.cpp" +// CHECK-ESP-RV32IMAC-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMAC-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-RV32IMAC-SAME: "-m" "elf32lriscv" +// CHECK-ESP-RV32IMAC-SAME: "-o" "a.out" +// CHECK-ESP-RV32IMAC-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-RV32IMAC-SAME: "-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for" +// CHECK-ESP-RV32IMAC-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}lib" +// CHECK-ESP-RV32IMAC-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-RV32IMAC-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -fno-integrated-as \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-FORCEAS %s +// CHECK-ESP-RV32IMAC-FORCEAS: "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-x" "c++" "{{.*}}baremetal-esp.cpp" +// CHECK-ESP-RV32IMAC-FORCEAS-NEXT: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imac" "-mabi=ilp32" +// CHECK-ESP-RV32IMAC-FORCEAS-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-m" "elf32lriscv" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-o" "a.out" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}lib" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf --ld-path=riscv32-esp-elf-ld \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-FORCELD %s +// CHECK-ESP-RV32IMAC-FORCELD: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMAC-FORCELD: riscv32-esp-elf-ld{{(.exe)?}}" +// CHECK-ESP-RV32IMAC-FORCELD-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-RV32IMAC-FORCELD-SAME: "-m" "elf32lriscv" +// CHECK-ESP-RV32IMAC-FORCELD-SAME: "-o" "a.out" +// CHECK-ESP-RV32IMAC-FORCELD-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-RV32IMAC-FORCELD-SAME: "-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for" +// CHECK-ESP-RV32IMAC-FORCELD-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}lib" +// CHECK-ESP-RV32IMAC-FORCELD-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-RV32IMAC-FORCELD-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -nostdlibinc -nobuiltininc \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-LIBINC %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -nostdinc \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-LIBINC %s +// CHECK-ESP-RV32IMAC-LIBINC-NOT: "-internal-isystem" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -rtlib=libgcc \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-LIBGCC %s +// CHECK-ESP-RV32IMAC-LIBGCC-NOT: "-lclang_rt.builtins" +// CHECK-ESP-RV32IMAC-LIBGCC: "-lgcc" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang --driver-mode=g++ %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-DEFAULTSTDCXX %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang --driver-mode=g++ %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -stdlib=libstdc++ \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-DEFAULTSTDCXX %s +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-NOT: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-m" "elf32lriscv" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-o" "a.out" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}lib" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-lstdc++" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-RV32IMAC-DEFAULTSTDCXX-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang --driver-mode=g++ %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -stdlib=libc++ \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-LIBCXX %s +// CHECK-ESP-RV32IMAC-LIBCXX: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMAC-LIBCXX-NOT: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}{{[^v].*}}" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-LIBCXX: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-m" "elf32lriscv" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-o" "a.out" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}lib" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-lc++" "-lc++abi" "-lunwind" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-RV32IMAC-LIBCXX-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang --driver-mode=g++ %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -nodefaultlibs \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-NDL %s +// CHECK-ESP-RV32IMAC-NDL: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMAC-NDL-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMAC-NDL: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMAC-NDL-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}lib" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -march=rv32i -mabi=ilp32 \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32I %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -march=rv32ic -mabi=ilp32 \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32I %s +// CHECK-ESP-RV32I: "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32I-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32I-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32I-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32i-zicsr-zifencei_ilp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32I-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32I-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32I-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32i-zicsr-zifencei_ilp32{{[/\\]+}}include" +// CHECK-ESP-RV32I-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32I-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-RV32I-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32i-zicsr-zifencei_ilp32{{[/\\]+}}lib" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -fno-integrated-as \ +// RUN: -march=rv32i -mabi=ilp32 \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32I-FORCEAS %s +// CHECK-ESP-RV32I-FORCEAS: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32i" "-mabi=ilp32" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -march=rv32i -mabi=ilp32 \ +// RUN: -fno-rtti \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32I-NORTTI %s +// CHECK-ESP-RV32I-NORTTI: "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32I-NORTTI-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32I-NORTTI-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32I-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32i-zicsr-zifencei_ilp32_no-rtti{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32I-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32I-NORTTI-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32I-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32i-zicsr-zifencei_ilp32_no-rtti{{[/\\]+}}include" +// CHECK-ESP-RV32I-NORTTI-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32I-NORTTI-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32i-zicsr-zifencei_ilp32_no-rtti{{[/\\]+}}lib" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -march=rv32im -mabi=ilp32 \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMC %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -march=rv32imc -mabi=ilp32 \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMC %s +// CHECK-ESP-RV32IMC: "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32IMC-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMC-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imc-zicsr-zifencei_ilp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMC-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32IMC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imc-zicsr-zifencei_ilp32{{[/\\]+}}include" +// CHECK-ESP-RV32IMC-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMC-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imc-zicsr-zifencei_ilp32{{[/\\]+}}lib" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ +// RUN: -march=rv32imc -mabi=ilp32 \ +// RUN: -fno-rtti \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMC-NORTTI %s +// CHECK-ESP-RV32IMC-NORTTI: "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32IMC-NORTTI-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMC-NORTTI-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMC-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imc-zicsr-zifencei_ilp32_no-rtti{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMC-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMC-NORTTI-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32IMC-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imc-zicsr-zifencei_ilp32_no-rtti{{[/\\]+}}include" +// CHECK-ESP-RV32IMC-NORTTI-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMC-NORTTI-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imc-zicsr-zifencei_ilp32_no-rtti{{[/\\]+}}lib" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -fno-integrated-as \ +// RUN: -march=rv32im -mabi=ilp32 \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IM-FORCEAS %s +// CHECK-ESP-RV32IM-FORCEAS: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32im" "-mabi=ilp32" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -fno-integrated-as \ +// RUN: -march=rv32imc -mabi=ilp32 \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMC-FORCEAS %s +// CHECK-ESP-RV32IMC-FORCEAS: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imc" "-mabi=ilp32" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -fno-integrated-as \ +// RUN: -march=rv32imac -mabi=ilp32 \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-FORCEAS2 %s +// CHECK-ESP-RV32IMAC-FORCEAS2: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imac" "-mabi=ilp32" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -march=rv32imafc -mabi=ilp32f \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -march=rv32imafdc -mabi=ilp32f \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -march=rv32gc -mabi=ilp32f \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC %s +// CHECK-ESP-RV32IMAFC: "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32IMAFC-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMAFC-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imafc-zicsr-zifencei_ilp32f{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAFC-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imafc-zicsr-zifencei_ilp32f{{[/\\]+}}include" +// CHECK-ESP-RV32IMAFC-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMAFC-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imafc-zicsr-zifencei_ilp32f{{[/\\]+}}lib" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -march=rv32imafc -mabi=ilp32f \ +// RUN: -fno-rtti \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC-NORTTI %s +// CHECK-ESP-RV32IMAFC-NORTTI: "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32IMAFC-NORTTI-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-RV32IMAFC-NORTTI-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-RV32IMAFC-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imafc-zicsr-zifencei_ilp32f_no-rtti{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAFC-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-RV32IMAFC-NORTTI-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-RV32IMAFC-NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imafc-zicsr-zifencei_ilp32f_no-rtti{{[/\\]+}}include" +// CHECK-ESP-RV32IMAFC-NORTTI-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-RV32IMAFC-NORTTI-SAME: "-L[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imafc-zicsr-zifencei_ilp32f_no-rtti{{[/\\]+}}lib" + +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -fno-integrated-as \ +// RUN: -march=rv32imafc -mabi=ilp32f \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC-FORCEAS %s +// CHECK-ESP-RV32IMAFC-FORCEAS: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imafc" "-mabi=ilp32f" + +// Check that compiler-rt library without the arch filename suffix will +// be used if present. +// RUN: rm -rf %T/baremetal_clang_rt_noarch +// RUN: mkdir -p %T/baremetal_clang_rt_noarch/lib +// RUN: touch %T/baremetal_clang_rt_noarch/lib/libclang_rt.builtins.a +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 \ +// RUN: --target=riscv32-esp-elf \ +// RUN: --sysroot=%T/baremetal_clang_rt_noarch \clang-runtimes/riscv32-esp-unknown-elf +// used if present. +// RUN: rm -rf %T/baremetal_clang_rt_arch +// RUN: mkdir -p %T/baremetal_clang_rt_arch/lib +// RUN: touch %T/baremetal_clang_rt_arch/lib/libclang_rt.builtins-riscv32.a +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 \ +// RUN: --target=riscv32-esp-elf \ +// RUN: --sysroot=%T/baremetal_clang_rt_arch \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32-CLANGRT-ARCH %s +// CHECK-ESP-RV32-CLANGRT-ARCH: "-lclang_rt.builtins-riscv32" +// CHECK-ESP-RV32-CLANGRT-ARCH-NOT: "-lclang_rt.builtins" + + +//////////////////// XTENSA ///////////////////////// + +// RUN: rm -rf %t +// RUN: mkdir -p %t/basic_xtensa_esp_tree/bin +// RUN: ln -s %clang %t/basic_xtensa_esp_tree/bin/clang +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/ld.lld %t/basic_xtensa_esp_tree/bin/ld.lld +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/lib %t/basic_xtensa_esp_tree/lib + +// ESP32 is default + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32 %s +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf -mcpu=esp32 \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32 %s +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -rtlib=compiler-rt \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32 %s +// CHECK-ESP-ESP32: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include" +// CHECK-ESP-ESP32-SAME: "-x" "c++" "{{.*}}baremetal-esp.cpp" +// CHECK-ESP-ESP32-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32-SAME: "-o" "a.out" +// CHECK-ESP-ESP32-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-ESP32-SAME: "-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for" +// CHECK-ESP-ESP32-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}lib" +// CHECK-ESP-ESP32-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-ESP32-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf -fno-integrated-as \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-FORCEAS %s +// CHECK-ESP-ESP32-FORCEAS: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-x" "c++" "{{.*}}baremetal-esp.cpp" +// CHECK-ESP-ESP32-FORCEAS-NEXT: xtensa-esp32-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" +// CHECK-ESP-ESP32-FORCEAS-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32-FORCEAS-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-o" "a.out" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}lib" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-ESP32-FORCEAS-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf --ld-path=xtensa-esp32-elf-ld \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-FORCELD %s +// CHECK-ESP-ESP32-FORCELD: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32-FORCELD-NEXT: xtensa-esp32-elf-ld{{(.exe)?}}" +// CHECK-ESP-ESP32-FORCELD-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32-FORCELD-SAME: "-o" "a.out" +// CHECK-ESP-ESP32-FORCELD-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-ESP32-FORCELD-SAME: "-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for" +// CHECK-ESP-ESP32-FORCELD-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}lib" +// CHECK-ESP-ESP32-FORCELD-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-ESP32-FORCELD-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -nostdlibinc -nobuiltininc \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-LIBINC %s +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -nostdinc \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-LIBINC %s +// CHECK-ESP-ESP32-LIBINC-NOT: "-internal-isystem" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -rtlib=libgcc \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-LIBGCC %s +// CHECK-ESP-ESP32-LIBGCC-NOT: "-lclang_rt.builtins" +// CHECK-ESP-ESP32-LIBGCC: "-lgcc" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang --driver-mode=g++ %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-DEFAULTSTDCXX %s +// RUN: %t/basic_xtensa_esp_tree/bin/clang --driver-mode=g++ %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -stdlib=libstdc++ \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-DEFAULTSTDCXX %s +// CHECK-ESP-ESP32-DEFAULTSTDCXX: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-NOT: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include" +// CHECK-ESP-ESP32-DEFAULTSTDCXX: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-o" "a.out" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}lib" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-lstdc++" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-ESP32-DEFAULTSTDCXX-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang --driver-mode=g++ %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -stdlib=libc++ \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-LIBCXX %s +// CHECK-ESP-ESP32-LIBCXX: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32-LIBCXX-NOT: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}{{[^v].*}}" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include" +// CHECK-ESP-ESP32-LIBCXX: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32-LIBCXX-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-o" "a.out" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-X" "{{.*}}.o" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}lib" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-lc++" "-lc++abi" "-lunwind" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" +// CHECK-ESP-ESP32-LIBCXX-SAME: "-lclang_rt.builtins" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang --driver-mode=g++ %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -nodefaultlibs \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-NDL %s +// CHECK-ESP-ESP32-NDL: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32-NDL-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32-NDL: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32-NDL-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -mcpu=esp32 -fno-rtti \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32_NORTTI %s +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -fno-rtti \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32_NORTTI %s +// CHECK-ESP-ESP32_NORTTI: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32_NORTTI-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32_NORTTI-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_no-rtti{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32_NORTTI-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_no-rtti{{[/\\]+}}include" +// CHECK-ESP-ESP32_NORTTI-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32_NORTTI-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32_NORTTI-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_no-rtti{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -mcpu=esp32 -mfix-esp32-psram-cache-issue \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32_PSRAM %s +// CHECK-ESP-ESP32_PSRAM: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32_PSRAM-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32_PSRAM-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32_PSRAM-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_psram{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32_PSRAM-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32_PSRAM-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32_PSRAM-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_psram{{[/\\]+}}include" +// CHECK-ESP-ESP32_PSRAM-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32_PSRAM-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32_PSRAM-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_psram{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -mcpu=esp32 -fno-rtti -mfix-esp32-psram-cache-issue \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32_PSRAM_NORTTI %s +// CHECK-ESP-ESP32_PSRAM_NORTTI: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32_PSRAM_NORTTI-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32_PSRAM_NORTTI-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32_PSRAM_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_psram_no-rtti{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32_PSRAM_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32_PSRAM_NORTTI-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32_PSRAM_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_psram_no-rtti{{[/\\]+}}include" +// CHECK-ESP-ESP32_PSRAM_NORTTI-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32_PSRAM_NORTTI-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32_PSRAM_NORTTI-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32_psram_no-rtti{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -mcpu=esp32s2 \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32S2 %s +// CHECK-ESP-ESP32S2: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32S2-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32S2-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32S2-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S2-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S2-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32S2-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2{{[/\\]+}}include" +// CHECK-ESP-ESP32S2-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32S2-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32S2-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf -fno-integrated-as \ +// RUN: -mcpu=esp32s2 \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32S2-FORCEAS %s +// CHECK-ESP-ESP32S2-FORCEAS: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32S2-FORCEAS-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32S2-FORCEAS-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32S2-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S2-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S2-FORCEAS-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32S2-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2{{[/\\]+}}include" +// CHECK-ESP-ESP32S2-FORCEAS: xtensa-esp32s2-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" +// CHECK-ESP-ESP32S2-FORCEAS-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32S2-FORCEAS-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32S2-FORCEAS-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -mcpu=esp32s2 -fno-rtti \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32S2_NORTTI %s +// CHECK-ESP-ESP32S2_NORTTI: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32S2_NORTTI-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32S2_NORTTI-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32S2_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2_no-rtti{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S2_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S2_NORTTI-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32S2_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2_no-rtti{{[/\\]+}}include" +// CHECK-ESP-ESP32S2_NORTTI-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32S2_NORTTI-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32S2_NORTTI-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2_no-rtti{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -mcpu=esp32s3 \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32S3 %s +// CHECK-ESP-ESP32S3: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32S3-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32S3-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32S3-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S3-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S3-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32S3-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3{{[/\\]+}}include" +// CHECK-ESP-ESP32S3-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32S3-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32S3-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf -fno-integrated-as \ +// RUN: -mcpu=esp32s3 \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32S3-FORCEAS %s +// CHECK-ESP-ESP32S3-FORCEAS: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32S3-FORCEAS-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32S3-FORCEAS-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32S3-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S3-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S3-FORCEAS-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32S3-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3{{[/\\]+}}include" +// CHECK-ESP-ESP32S3-FORCEAS: xtensa-esp32s3-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" +// CHECK-ESP-ESP32S3-FORCEAS-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32S3-FORCEAS-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32S3-FORCEAS-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3{{[/\\]+}}lib" + +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf \ +// RUN: -mcpu=esp32s3 -fno-rtti \ +// RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32S3_NORTTI %s +// CHECK-ESP-ESP32S3_NORTTI: "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32S3_NORTTI-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-ESP-ESP32S3_NORTTI-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-ESP-ESP32S3_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3_no-rtti{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S3_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECK-ESP-ESP32S3_NORTTI-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" +// CHECK-ESP-ESP32S3_NORTTI-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3_no-rtti{{[/\\]+}}include" +// CHECK-ESP-ESP32S3_NORTTI-NEXT: ld.lld{{(.exe)?}}" +// CHECK-ESP-ESP32S3_NORTTI-SAME: "--sysroot=[[SYSROOT]]" +// CHECK-ESP-ESP32S3_NORTTI-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3_no-rtti{{[/\\]+}}lib" + +// Check that compiler-rt library without the arch filename suffix will +// be used if present. +// RUN: rm -rf %T/baremetal_clang_rt_noarch +// RUN: mkdir -p %T/baremetal_clang_rt_noarch/lib +// RUN: touch %T/baremetal_clang_rt_noarch/lib/libclang_rt.builtins.a +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 \ +// RUN: --target=xtensa-esp-elf \ +// RUN: --sysroot=%T/baremetal_clang_rt_noarch \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32_CLANGRT-NOARCH %s +// CHECK-ESP-ESP32_CLANGRT-NOARCH: "-lclang_rt.builtins" +// CHECK-ESP-ESP32_CLANGRT-NOARCH-NOT: "-lclang_rt.builtins-xtensa" + +// Check that compiler-rt library with the arch filename suffix will be +// used if present. +// RUN: rm -rf %T/baremetal_clang_rt_arch +// RUN: mkdir -p %T/baremetal_clang_rt_arch/lib +// RUN: touch %T/baremetal_clang_rt_arch/lib/libclang_rt.builtins-xtensa.a +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 \ +// RUN: --target=xtensa-esp-elf \ +// RUN: --sysroot=%T/baremetal_clang_rt_arch \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-CLANGRT-ARCH %s +// CHECK-ESP-ESP32-CLANGRT-ARCH: "-lclang_rt.builtins-xtensa" +// CHECK-ESP-ESP32-CLANGRT-ARCH-NOT: "-lclang_rt.builtins" diff --git a/clang/test/Driver/baremetal-sysroot.cpp b/clang/test/Driver/baremetal-sysroot.cpp index fc66020772a771..840b77335bc9e1 100644 --- a/clang/test/Driver/baremetal-sysroot.cpp +++ b/clang/test/Driver/baremetal-sysroot.cpp @@ -20,3 +20,58 @@ // CHECK-V6M-C-SAME: "-L{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}armv6m-none-eabi{{[/\\]+}}lib" // CHECK-V6M-C-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" // CHECK-V6M-C-SAME: "-o" "{{.*}}.o" + +// RUN: rm -rf %T/baremetal_default_sysroot +// RUN: mkdir -p %T/baremetal_default_sysroot/bin +// RUN: mkdir -p %T/baremetal_default_sysroot/lib/clang-runtimes/riscv32-esp-unknown-elf/include/c++/11.2.0 +// RUN: mkdir -p %T/baremetal_default_sysroot/lib/clang-runtimes/riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32/include/c++/11.2.0 +// RUN: echo "MultilibVersion: '1.0'" > %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo "Variants:" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo "- Dir: riscv32-esp-unknown-elf/rv32imac-zicsr-zifencei_ilp32" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " Flags:" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " - --target=riscv32-esp-unknown-elf" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " - -march=rv32imac_zicsr_zifencei" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " - -mabi=ilp32" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo "Mappings:" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo "- Match: -march=rv32imac" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " Flags:" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " - -march=rv32imac_zicsr_zifencei" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: ln -s %clang %T/baremetal_default_sysroot/bin/clang + +// RUN: %T/baremetal_default_sysroot/bin/clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv32-esp-elf --sysroot= \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-C %s +// CHECK-ESP-RV32IMAC-C: "{{.*}}clang{{.*}}" "-cc1" "-triple" "riscv32-esp-unknown-elf" +// CHECK-ESP-RV32IMAC-C-SAME: "-internal-isystem" "{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECk-ESP-RV32IMAC-C-SAME: "-internal-isystem" "{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}include" +// CHECk-ESP-RV32IMAC-C-SAME: "-internal-isystem" "{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include" +// CHECK-ESP-RV32IMAC-C-SAME: "-x" "c++" "{{.*}}baremetal-sysroot.cpp" +// CHECK-ESP-RV32IMAC-C-NEXT: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "-m" "elf32lriscv" +// CHECK-ESP-RV32IMAC-C-SAME: "-o" "{{.*}}.o" +// CHECK-ESP-RV32IMAC-C-SAME: "-L{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}lib" +// CHECK-ESP-RV32IMAC-C-SAME: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lclang_rt.builtins-riscv32" + +// RUN: rm -rf %T/baremetal_default_sysroot +// RUN: mkdir -p %T/baremetal_default_sysroot/bin +// RUN: mkdir -p %T/baremetal_default_sysroot/lib/clang-runtimes/xtensa-esp-unknown-elf/include/c++/11.2.0 +// RUN: mkdir -p %T/baremetal_default_sysroot/lib/clang-runtimes/xtensa-esp-unknown-elf/esp32/include/c++/11.2.0 +// RUN: echo "MultilibVersion: '1.0'" > %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo "Variants:" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo "- Dir: xtensa-esp-unknown-elf/esp32" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " Flags:" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " - --target=xtensa-esp-unknown-elf" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: echo " - -mcpu=esp32" >> %T/baremetal_default_sysroot/lib/clang-runtimes/multilib.yaml +// RUN: ln -s %clang %T/baremetal_default_sysroot/bin/clang + +// RUN: %T/baremetal_default_sysroot/bin/clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target xtensa-esp-unknown-elf --sysroot= \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-C %s +// CHECK-ESP-ESP32-C: "{{.*}}clang{{.*}}" "-cc1" "-triple" "xtensa-esp-unknown-elf" +// CHECK-ESP-ESP32-C-SAME: "-internal-isystem" "{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" +// CHECk-ESP-ESP32-C-SAME: "-internal-isystem" "{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include" +// CHECk-ESP-ESP32-C-SAME: "-internal-isystem" "{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include" +// CHECK-ESP-ESP32-C-SAME: "-x" "c++" "{{.*}}baremetal-sysroot.cpp" +// CHECK-ESP-ESP32-C-NEXT: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" +// CHECK-ESP-ESP32-C-SAME: "-o" "{{.*}}.o" +// CHECK-ESP-ESP32-C-SAME: "-L{{.*}}/baremetal_default_sysroot{{[/\\]+}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}lib" +// CHECK-ESP-ESP32-C-SAME: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lclang_rt.builtins-xtensa" diff --git a/clang/test/Driver/riscv32-esp-toolchain-extra.c b/clang/test/Driver/riscv32-esp-toolchain-extra.c deleted file mode 100644 index 13e94e981553c2..00000000000000 --- a/clang/test/Driver/riscv32-esp-toolchain-extra.c +++ /dev/null @@ -1,115 +0,0 @@ -// A basic clang -cc1 command-line, and simple environment check. - -// The tests here are similar to those in xtensa-toolchain.c, however -// these tests need to create symlinks to test directory trees in order to -// set up the environment and therefore shell support is required. -// REQUIRES: shell, xtensa-registered-target -// UNSUPPORTED: system-windows - -// Compiler-rt multilibs are located at '$INSTALLDIR/lib/clang/15.0.0//mcpu/'. -// At this moment multilib feature for compiler-rt is supported only when GCC installation with the same multilib structure is found. -// It is safe because ESP toolchain still depends on libstdc++ which is part of GCC installation. -// When libc++ wil be supported by toolchain the dependency on GCC multilibs will be removed. - -// RUN: rm -rf %t -// RUN: mkdir -p %t/multilib_riscv_esp_elf_sdk/bin -// RUN: ln -s %clang %t/multilib_riscv_esp_elf_sdk/bin/clang -// RUN: ln -s %S/Inputs/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld %t/multilib_riscv_esp_elf_sdk/bin/riscv32-esp-elf-ld -// RUN: ln -s %S/Inputs/multilib_riscv_esp_elf_sdk/lib %t/multilib_riscv_esp_elf_sdk/lib -// RUN: ln -s %S/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf %t/multilib_riscv_esp_elf_sdk/riscv32-esp-elf - -// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ -// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ -// RUN: --target=riscv32-esp-elf -march=rv32i -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32I-RTLIB-COMPILERRT-NORTTI %s - -// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32i/ilp32/no-rtti{{/|\\\\}}crt0.o" -// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtbegin.o" -// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/libclang_rt.builtins.a" -// C-RV32I-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/no-rtti/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ -// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ -// RUN: --target=riscv32-esp-elf -march=rv32i -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32I-RTLIB-COMPILERRT-RTTI %s - -// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32i/ilp32{{/|\\\\}}crt0.o" -// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtbegin.o" -// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/libclang_rt.builtins.a" -// C-RV32I-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32i/ilp32/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ -// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ -// RUN: --target=riscv32-esp-elf -march=rv32imc -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMC-RTLIB-COMPILERRT-NORTTI %s - -// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imc/ilp32/no-rtti{{/|\\\\}}crt0.o" -// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtbegin.o" -// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/libclang_rt.builtins.a" -// C-RV32IMC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/no-rtti/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ -// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ -// RUN: --target=riscv32-esp-elf -march=rv32imc -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMC-RTLIB-COMPILERRT-RTTI %s - -// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imc/ilp32{{/|\\\\}}crt0.o" -// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtbegin.o" -// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/libclang_rt.builtins.a" -// C-RV32IMC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imc/ilp32/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ -// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ -// RUN: --target=riscv32-esp-elf -march=rv32imac -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMAC-RTLIB-COMPILERRT-NORTTI %s - -// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imac/ilp32/no-rtti{{/|\\\\}}crt0.o" -// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtbegin.o" -// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/libclang_rt.builtins.a" -// C-RV32IMAC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/no-rtti/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ -// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ -// RUN: --target=riscv32-esp-elf -march=rv32imac -mabi=ilp32 --rtlib=compiler-rt -fuse-ld= 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMAC-RTLIB-COMPILERRT-RTTI %s - -// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imac/ilp32{{/|\\\\}}crt0.o" -// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtbegin.o" -// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/libclang_rt.builtins.a" -// C-RV32IMAC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imac/ilp32/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ -// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ -// RUN: --target=riscv32-esp-elf -march=rv32imafc -mabi=ilp32f --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI %s - -// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imafc/ilp32f/no-rtti{{/|\\\\}}crt0.o" -// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtbegin.o" -// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/libclang_rt.builtins.a" -// C-RV32IMAFC-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/no-rtti/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_riscv_esp_elf_sdk/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_riscv_esp_elf_sdk \ -// RUN: -resource-dir=%t/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0 \ -// RUN: --target=riscv32-esp-elf -march=rv32imafc -mabi=ilp32f --rtlib=compiler-rt -fuse-ld= 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMAFC-RTLIB-COMPILERRT-RTTI %s - -// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib/rv32imafc/ilp32f{{/|\\\\}}crt0.o" -// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtbegin.o" -// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/libclang_rt.builtins.a" -// C-RV32IMAFC-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_riscv_esp_elf_sdk/lib/clang/15.0.0/riscv32-esp-elf/generic-rv32/rv32imafc/ilp32f/lib/clang_rt.crtend.o" diff --git a/clang/test/Driver/riscv32-esp-toolchain.c b/clang/test/Driver/riscv32-esp-toolchain.c deleted file mode 100644 index 34ef6871f30f0b..00000000000000 --- a/clang/test/Driver/riscv32-esp-toolchain.c +++ /dev/null @@ -1,325 +0,0 @@ -// A basic clang -cc1 command-line, and simple environment check. - -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ -// RUN: | FileCheck -check-prefix=CC1 %s -// CC1: clang{{.*}} "-cc1" "-triple" "riscv32-esp-unknown-elf" - -// Test interaction with -fuse-ld=lld, if lld is available. -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk -fuse-ld=lld 2>&1 \ -// RUN: | FileCheck -check-prefix=LLD %s -// LLD: {{(error: invalid linker name in argument '-fuse-ld=lld')|(ld.lld)}} - -// rv32imac is the default - -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk \ -// RUN: --sysroot=%S/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMAC-BAREMETAL-MULTI-ILP32 %s - -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "-mabi" "ilp32" "-march" "rv32imac" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "--sysroot={{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "-m" "elf32lriscv" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtbegin.o" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" -// C-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" - -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ -// RUN: --sysroot= \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32 %s - -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-mabi" "ilp32" "-march" "rv32imac" -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-m" "elf32lriscv" -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtbegin.o" -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" -// C-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" - -// RUN: %clangxx %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: -ffreestanding -stdlib=libstdc++ --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk \ -// RUN: --sysroot=%S/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf 2>&1 \ -// RUN: | FileCheck -check-prefix=CXX-RV32IMAC-BAREMETAL-MULTI-ILP32 %s - -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-internal-isystem" "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++{{/|\\\\}}8.4.0" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-mabi" "ilp32" "-march" "rv32imac" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "--sysroot={{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-m" "elf32lriscv" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtbegin.o" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "-lstdc++" "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" -// CXX-RV32IMAC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" - -// RUN: %clangxx %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: -ffreestanding -stdlib=libstdc++ --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ -// RUN: --sysroot= \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ -// RUN: | FileCheck -check-prefix=CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32 %s - -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-internal-isystem" "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/include/c++{{/|\\\\}}8.4.0" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-mabi" "ilp32" "-march" "rv32imac" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-m" "elf32lriscv" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtbegin.o" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "-lstdc++" "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" -// CXX-RV32IMAC-BAREMETAL-MULTI-NOSYSROOT-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32{{/|\\\\}}crtend.o" - -// RUN: %clangxx %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: -ffreestanding -stdlib=libstdc++ --rtlib=libgcc --ld-path=riscv32-esp-elf-ld \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk \ -// RUN: --sysroot=%S/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf \ -// RUN: -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32 %s - -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-internal-isystem" "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/include/c++{{/|\\\\}}8.4.0" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-mabi" "ilp32" "-march" "rv32imac" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "--sysroot={{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-m" "elf32lriscv" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti{{/|\\\\}}crtbegin.o" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/riscv32-esp-elf/lib" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "-lstdc++" "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" -// CXX-RV32IMAC-BAREMETAL-MULTI-NORTTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imac/ilp32/no-rtti{{/|\\\\}}crtend.o" - -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: -march=rv32i -mabi=ilp32 \ -// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld --sysroot= \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32I-BAREMETAL-MULTI-ILP32 %s - -// C-RV32I-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" -// C-RV32I-BAREMETAL-MULTI-ILP32: "-mabi" "ilp32" "-march" "rv32i" -// C-RV32I-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32I-BAREMETAL-MULTI-ILP32: "-m" "elf32lriscv" -// C-RV32I-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32{{/|\\\\}}crtbegin.o" -// C-RV32I-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" -// C-RV32I-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" -// C-RV32I-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" -// C-RV32I-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32i/ilp32{{/|\\\\}}crtend.o" - -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: -march=rv32imc -mabi=ilp32 \ -// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld --sysroot= \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMC-BAREMETAL-MULTI-ILP32 %s - -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "-mabi" "ilp32" "-march" "rv32imc" -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "-m" "elf32lriscv" -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32{{/|\\\\}}crtbegin.o" -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" -// C-RV32IMC-BAREMETAL-MULTI-ILP32: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imc/ilp32{{/|\\\\}}crtend.o" - -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32-esp-elf \ -// RUN: -march=rv32imafc -mabi=ilp32f \ -// RUN: -ffreestanding --rtlib=libgcc --ld-path=riscv32-esp-elf-ld --sysroot= \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_esp_elf_sdk 2>&1 \ -// RUN: | FileCheck -check-prefix=C-RV32IMAFC-BAREMETAL-MULTI-ILP32F %s - -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-as" -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "-mabi" "ilp32f" "-march" "rv32imafc" -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "{{.*}}Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}riscv32-esp-elf-ld" -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "-m" "elf32lriscv" -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f{{/|\\\\}}crtbegin.o" -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0" -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "-L{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}riscv32-esp-elf/lib" -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" "-lgcc" -// C-RV32IMAFC-BAREMETAL-MULTI-ILP32F: "{{.*}}/Inputs/multilib_riscv_esp_elf_sdk/lib/gcc/riscv32-esp-elf/8.4.0/rv32imafc/ilp32f{{/|\\\\}}crtend.o" - -// RUN: %clang -target riscv32-esp-elf %s -emit-llvm -S -o - | FileCheck %s - -typedef __builtin_va_list va_list; -typedef __SIZE_TYPE__ size_t; -typedef __PTRDIFF_TYPE__ ptrdiff_t; -typedef __WCHAR_TYPE__ wchar_t; -typedef __WINT_TYPE__ wint_t; - - -// Check Alignments - -// CHECK: @align_c = dso_local global i32 1 -int align_c = __alignof(char); - -// CHECK: @align_s = dso_local global i32 2 -int align_s = __alignof(short); - -// CHECK: @align_i = dso_local global i32 4 -int align_i = __alignof(int); - -// CHECK: @align_wc = dso_local global i32 4 -int align_wc = __alignof(wchar_t); - -// CHECK: @align_wi = dso_local global i32 4 -int align_wi = __alignof(wint_t); - -// CHECK: @align_l = dso_local global i32 4 -int align_l = __alignof(long); - -// CHECK: @align_ll = dso_local global i32 8 -int align_ll = __alignof(long long); - -// CHECK: @align_p = dso_local global i32 4 -int align_p = __alignof(void*); - -// CHECK: @align_f = dso_local global i32 4 -int align_f = __alignof(float); - -// CHECK: @align_d = dso_local global i32 8 -int align_d = __alignof(double); - -// CHECK: @align_ld = dso_local global i32 16 -int align_ld = __alignof(long double); - -// CHECK: @align_vl = dso_local global i32 4 -int align_vl = __alignof(va_list); - -// CHECK: @align_a_c = dso_local global i32 1 -int align_a_c = __alignof(_Atomic(char)); - -// CHECK: @align_a_s = dso_local global i32 2 -int align_a_s = __alignof(_Atomic(short)); - -// CHECK: @align_a_i = dso_local global i32 4 -int align_a_i = __alignof(_Atomic(int)); - -// CHECK: @align_a_wc = dso_local global i32 4 -int align_a_wc = __alignof(_Atomic(wchar_t)); - -// CHECK: @align_a_wi = dso_local global i32 4 -int align_a_wi = __alignof(_Atomic(wint_t)); - -// CHECK: @align_a_l = dso_local global i32 4 -int align_a_l = __alignof(_Atomic(long)); - -// CHECK: @align_a_ll = dso_local global i32 8 -int align_a_ll = __alignof(_Atomic(long long)); - -// CHECK: @align_a_p = dso_local global i32 4 -int align_a_p = __alignof(_Atomic(void*)); - -// CHECK: @align_a_f = dso_local global i32 4 -int align_a_f = __alignof(_Atomic(float)); - -// CHECK: @align_a_d = dso_local global i32 8 -int align_a_d = __alignof(_Atomic(double)); - -// CHECK: @align_a_ld = dso_local global i32 16 -int align_a_ld = __alignof(_Atomic(long double)); - -// CHECK: @align_a_s4 = dso_local global i32 4 -int align_a_s4 = __alignof(_Atomic(struct { char s[4]; })); - -// CHECK: @align_a_s8 = dso_local global i32 8 -int align_a_s8 = __alignof(_Atomic(struct { char s[8]; })); - -// CHECK: @align_a_s16 = dso_local global i32 16 -int align_a_s16 = __alignof(_Atomic(struct { char s[16]; })); - -// CHECK: @align_a_s32 = dso_local global i32 1 -int align_a_s32 = __alignof(_Atomic(struct { char s[32]; })); - - -// Check Sizes - -// CHECK: @size_a_c = dso_local global i32 1 -int size_a_c = sizeof(_Atomic(char)); - -// CHECK: @size_a_s = dso_local global i32 2 -int size_a_s = sizeof(_Atomic(short)); - -// CHECK: @size_a_i = dso_local global i32 4 -int size_a_i = sizeof(_Atomic(int)); - -// CHECK: @size_a_wc = dso_local global i32 4 -int size_a_wc = sizeof(_Atomic(wchar_t)); - -// CHECK: @size_a_wi = dso_local global i32 4 -int size_a_wi = sizeof(_Atomic(wint_t)); - -// CHECK: @size_a_l = dso_local global i32 4 -int size_a_l = sizeof(_Atomic(long)); - -// CHECK: @size_a_ll = dso_local global i32 8 -int size_a_ll = sizeof(_Atomic(long long)); - -// CHECK: @size_a_p = dso_local global i32 4 -int size_a_p = sizeof(_Atomic(void*)); - -// CHECK: @size_a_f = dso_local global i32 4 -int size_a_f = sizeof(_Atomic(float)); - -// CHECK: @size_a_d = dso_local global i32 8 -int size_a_d = sizeof(_Atomic(double)); - -// CHECK: @size_a_ld = dso_local global i32 16 -int size_a_ld = sizeof(_Atomic(long double)); - - -// Check types - -// CHECK: zeroext i8 @check_char() -char check_char() { return 0; } - -// CHECK: define dso_local signext i16 @check_short() -short check_short() { return 0; } - -// CHECK: define dso_local i32 @check_int() -int check_int() { return 0; } - -// CHECK: define dso_local i32 @check_wchar_t() -int check_wchar_t() { return 0; } - -// CHECK: define dso_local i32 @check_long() -long check_long() { return 0; } - -// CHECK: define dso_local i64 @check_longlong() -long long check_longlong() { return 0; } - -// CHECK: define dso_local zeroext i8 @check_uchar() -unsigned char check_uchar() { return 0; } - -// CHECK: define dso_local zeroext i16 @check_ushort() -unsigned short check_ushort() { return 0; } - -// CHECK: define dso_local i32 @check_uint() -unsigned int check_uint() { return 0; } - -// CHECK: define dso_local i32 @check_ulong() -unsigned long check_ulong() { return 0; } - -// CHECK: define dso_local i64 @check_ulonglong() -unsigned long long check_ulonglong() { return 0; } - -// CHECK: define dso_local i32 @check_size_t() -size_t check_size_t() { return 0; } - -// CHECK: define dso_local float @check_float() -float check_float() { return 0; } - -// CHECK: define dso_local double @check_double() -double check_double() { return 0; } - -// CHECK: define dso_local fp128 @check_longdouble() -long double check_longdouble() { return 0; } diff --git a/clang/test/Driver/xtensa-esp-toolchain-extra.c b/clang/test/Driver/xtensa-esp-toolchain-extra.c deleted file mode 100644 index 5e195019820d40..00000000000000 --- a/clang/test/Driver/xtensa-esp-toolchain-extra.c +++ /dev/null @@ -1,111 +0,0 @@ -// A basic clang -cc1 command-line, and simple environment check. - -// The tests here are similar to those in xtensa-toolchain.c, however -// these tests need to create symlinks to test directory trees in order to -// set up the environment and therefore shell support is required. -// REQUIRES: shell, xtensa-registered-target -// UNSUPPORTED: system-windows - -// Compiler-rt multilibs are located at '$INSTALLDIR/lib/clang/15.0.0//mcpu/'. -// At this moment multilib feature for compiler-rt is supported only when GCC installation with the same multilib structure is found. -// It is safe because ESP toolchain still depends on libstdc++ which is part of GCC installation. -// When libc++ wil be supported by toolchain the dependency on GCC multilibs will be removed. - -// RUN: rm -rf %t -// RUN: mkdir -p %t/multilib_xtensa_tree/bin -// RUN: ln -s %clang %t/multilib_xtensa_tree/bin/clang -// RUN: ln -s %S/Inputs/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld %t/multilib_xtensa_tree/bin/xtensa-esp32-elf-ld -// RUN: ln -s %S/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld %t/multilib_xtensa_tree/bin/xtensa-esp32s2-elf-ld -// RUN: ln -s %S/Inputs/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld %t/multilib_xtensa_tree/bin/xtensa-esp32s3-elf-ld -// RUN: ln -s %S/Inputs/multilib_xtensa_tree/lib %t/multilib_xtensa_tree/lib -// RUN: ln -s %S/Inputs/multilib_xtensa_tree/xtensa-esp32-elf %t/multilib_xtensa_tree/xtensa-esp32-elf -// RUN: ln -s %S/Inputs/multilib_xtensa_tree/xtensa-esp32s2-elf %t/multilib_xtensa_tree/xtensa-esp32s2-elf -// RUN: ln -s %S/Inputs/multilib_xtensa_tree/xtensa-esp32s3-elf %t/multilib_xtensa_tree/xtensa-esp32s3-elf - -// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ -// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ -// RUN: --target=xtensa-esp-elf -mcpu=esp32 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI %s - -// C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtbegin.o" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/libclang_rt.builtins.a" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/no-rtti/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ -// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ -// RUN: --target=xtensa-esp-elf -mcpu=esp32 --rtlib=compiler-rt -fuse-ld= 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI %s - -// C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtbegin.o" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/libclang_rt.builtins.a" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ -// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ -// RUN: --target=xtensa-esp-elf -mcpu=esp32 --rtlib=compiler-rt -fuse-ld= -mfix-esp32-psram-cache-issue -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI %s - -// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtbegin.o" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/libclang_rt.builtins.a" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/no-rtti/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ -// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ -// RUN: --target=xtensa-esp-elf -mcpu=esp32 --rtlib=compiler-rt -fuse-ld= -mfix-esp32-psram-cache-issue 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI %s - -// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtbegin.o" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/libclang_rt.builtins.a" -// C-XTENSA-ESP32-RTLIB-COMPILERRT-PSRAM-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32/esp32-psram/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ -// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ -// RUN: --target=xtensa-esp-elf -mcpu=esp32s2 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI %s - -// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" -// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtbegin.o" -// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/libclang_rt.builtins.a" -// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/no-rtti/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ -// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ -// RUN: --target=xtensa-esp-elf -mcpu=esp32s2 --rtlib=compiler-rt -fuse-ld= 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI %s - -// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" -// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtbegin.o" -// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/libclang_rt.builtins.a" -// C-XTENSA-ESP32S2-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s2/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ -// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ -// RUN: --target=xtensa-esp-elf -mcpu=esp32s3 --rtlib=compiler-rt -fuse-ld= -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI %s - -// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" -// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtbegin.o" -// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/libclang_rt.builtins.a" -// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-NORTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/no-rtti/lib/clang_rt.crtend.o" - -// RUN: %t/multilib_xtensa_tree/bin/clang %s -### -no-canonical-prefixes \ -// RUN: --gcc-toolchain=%t/multilib_xtensa_tree \ -// RUN: -resource-dir=%t/multilib_xtensa_tree/lib/clang/15.0.0 \ -// RUN: --target=xtensa-esp-elf -mcpu=esp32s3 --rtlib=compiler-rt -fuse-ld= 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI %s - -// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" -// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtbegin.o" -// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/libclang_rt.builtins.a" -// C-XTENSA-ESP32S3-RTLIB-COMPILERRT-RTTI: "{{.*}}/multilib_xtensa_tree/lib/clang/15.0.0/xtensa-esp-elf/esp32s3/lib/clang_rt.crtend.o" diff --git a/clang/test/Driver/xtensa-toolchain.c b/clang/test/Driver/xtensa-toolchain.c deleted file mode 100644 index 234495b0cda0ae..00000000000000 --- a/clang/test/Driver/xtensa-toolchain.c +++ /dev/null @@ -1,125 +0,0 @@ -// A basic clang -cc1 command-line, and simple environment check. - -// RUN: %clang %s -### -no-canonical-prefixes -target xtensa-esp-elf \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=CC1-ESP-DEFAULT %s -// CC1-ESP-DEFAULT: clang{{.*}} "-cc1" "-triple" "xtensa-esp-unknown-elf" - -// RUN: %clang %s -### -no-canonical-prefixes -target xtensa-esp-elf -mcpu=esp32\ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=CC1-ESP32 %s -// CC1-ESP32: clang{{.*}} "-cc1" "-triple" "xtensa-esp-unknown-elf" {{.*}}"-target-cpu" "esp32" - -// RUN: %clang %s -### -no-canonical-prefixes -target xtensa-esp-elf -mcpu=esp32s2\ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=CC1-ESP32S2 %s -// CC1-ESP32S2: clang{{.*}} "-cc1" "-triple" "xtensa-esp-unknown-elf" {{.*}}"-target-cpu" "esp32s2" - -// RUN: %clang %s -### -no-canonical-prefixes -target xtensa-esp-elf -mcpu=esp32s3\ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=CC1-ESP32S3 %s -// CC1-ESP32S3: clang{{.*}} "-cc1" "-triple" "xtensa-esp-unknown-elf" {{.*}}"-target-cpu" "esp32s3" - -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ -// RUN: -target xtensa-esp-elf --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL %s - -// C-XTENSA-ESP32-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/no-rtti" -// C-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/no-rtti" - -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ -// RUN: -target xtensa-esp-elf --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-RTTI %s - -// C-XTENSA-ESP32-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" -// C-XTENSA-ESP32-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" - -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ -// RUN: -target xtensa-esp-elf --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -fno-rtti -mfix-esp32-psram-cache-issue 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-PSRAM %s - -// C-XTENSA-ESP32-BAREMETAL-PSRAM: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram/no-rtti" -// C-XTENSA-ESP32-BAREMETAL-PSRAM: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram/no-rtti" - -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ -// RUN: -target xtensa-esp-elf --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -mfix-esp32-psram-cache-issue 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI %s - -// C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0/esp32-psram" -// C-XTENSA-ESP32-BAREMETAL-PSRAM-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib/esp32-psram" - -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ -// RUN: -target xtensa-esp-elf -mcpu=esp32s2 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-BAREMETAL %s - -// C-XTENSA-ESP32S2-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" -// C-XTENSA-ESP32S2-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s2-elf{{/|\\\\}}8.4.0/no-rtti" -// C-XTENSA-ESP32S2-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s2-elf{{/|\\\\}}lib/no-rtti" - -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ -// RUN: -target xtensa-esp-elf -mcpu=esp32s2 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S2-BAREMETAL-RTTI %s - -// C-XTENSA-ESP32S2-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s2-elf-ld" -// C-XTENSA-ESP32S2-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s2-elf{{/|\\\\}}8.4.0" -// C-XTENSA-ESP32S2-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s2-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s2-elf{{/|\\\\}}lib" - -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ -// RUN: -target xtensa-esp-elf -mcpu=esp32s3 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree -fno-rtti 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-BAREMETAL %s - -// C-XTENSA-ESP32S3-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" -// C-XTENSA-ESP32S3-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}8.4.0/no-rtti" -// C-XTENSA-ESP32S3-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}lib/no-rtti" - -// RUN: %clang %s -### -no-canonical-prefixes -fuse-ld= \ -// RUN: -target xtensa-esp-elf -mcpu=esp32s3 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32S3-BAREMETAL-RTTI %s - -// C-XTENSA-ESP32S3-BAREMETAL-RTTI: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32s3-elf-ld" -// C-XTENSA-ESP32S3-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}8.4.0" -// C-XTENSA-ESP32S3-BAREMETAL-RTTI: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32s3-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32s3-elf{{/|\\\\}}lib" - -// RUN: %clang %s -### -no-canonical-prefixes \ -// RUN: -target xtensa-esp-elf -mcpu=esp32 --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree \ -// RUN: --sysroot=%S/Inputs/multilib_xtensa_tree/xtensa-esp32-elf 2>&1 \ -// RUN: | FileCheck -check-prefix=C-XTENSA-ESP32-SYSROOT-BAREMETAL %s - -// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "--sysroot={{.*}}/Inputs/multilib_xtensa_tree/xtensa-esp32-elf" -// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" -// C-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" - -// RUN: %clangxx %s -### -no-canonical-prefixes \ -// RUN: -target xtensa-esp-elf -mcpu=esp32 -stdlib=libstdc++ --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree 2>&1 \ -// RUN: | FileCheck -check-prefix=CXX-XTENSA-ESP32-BAREMETAL %s - -// CXX-XTENSA-ESP32-BAREMETAL: "-internal-isystem" "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf/include/c++{{/|\\\\}}8.4.0" -// CXX-XTENSA-ESP32-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" -// CXX-XTENSA-ESP32-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" - -// RUN: %clangxx %s -### -no-canonical-prefixes \ -// RUN: -target xtensa-esp-elf -mcpu=esp32 -stdlib=libstdc++ --rtlib=platform \ -// RUN: --gcc-toolchain=%S/Inputs/multilib_xtensa_tree \ -// RUN: --sysroot=%S/Inputs/multilib_xtensa_tree/xtensa-esp32-elf 2>&1 \ -// RUN: | FileCheck -check-prefix=CXX-XTENSA-ESP32-SYSROOT-BAREMETAL %s - -// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-internal-isystem" "{{.*}}Inputs/multilib_xtensa_tree/xtensa-esp32-elf/include/c++/8.4.0" -// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "{{.*}}Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}bin{{/|\\\\}}xtensa-esp32-elf-ld" -// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}8.4.0" -// CXX-XTENSA-ESP32-SYSROOT-BAREMETAL: "-L{{.*}}/Inputs/multilib_xtensa_tree/lib/gcc/xtensa-esp32-elf/8.4.0/../../..{{/|\\\\}}..{{/|\\\\}}xtensa-esp32-elf{{/|\\\\}}lib" diff --git a/compiler-rt/test/builtins/Unit/lit.cfg.py b/compiler-rt/test/builtins/Unit/lit.cfg.py index 0b6b971bca0d6f..a020850fddf65d 100644 --- a/compiler-rt/test/builtins/Unit/lit.cfg.py +++ b/compiler-rt/test/builtins/Unit/lit.cfg.py @@ -105,7 +105,7 @@ def get_libgcc_file_name(): # Don't pass dosish path separator to msys bash.exe. base_lib = base_lib.replace("\\", "/") if config.target_triple in ['xtensa-esp-elf', 'riscv32-esp-elf']: - config.substitutions.append( ("%librt ", "-Wl,--start-group," + base_lib + ',-lm,-lc,--whole-archive,-lgloss,--no-whole-archive,-lc,--whole-archive,-lsys_qemu,--no-whole-archive,--end-group ') ) + config.substitutions.append( ("%librt ", "-Wl,--start-group," + base_lib + ',-lc,-lm,--end-group ') ) else: config.substitutions.append( ("%librt ", base_lib + ' -lc -lm ') ) diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 2b1a15742a0df4..c7d6161c2716b1 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -1020,6 +1020,9 @@ class Triple { return getArch() == Triple::bpfel || getArch() == Triple::bpfeb; } + /// Tests whether the target is Xtensa. + bool isXtensa() const { return getArch() == Triple::xtensa; } + /// Tests whether the target supports comdat bool supportsCOMDAT() const { return !(isOSBinFormatMachO() || isOSBinFormatXCOFF() || diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 105e40c02e2a0e..e733a20a18e6e5 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -665,9 +665,10 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, default: break; case Match_Success: - processInstruction(Inst, IDLoc, Out, STI); - Inst.setLoc(IDLoc); - Out.emitInstruction(Inst, getSTI()); + if(processInstruction(Inst, IDLoc, Out, STI)) { + Inst.setLoc(IDLoc); + Out.emitInstruction(Inst, getSTI()); + } return false; case Match_MissingFeature: return Error(IDLoc, "instruction use requires an option to be enabled"); @@ -1178,6 +1179,11 @@ bool XtensaAsmParser::parseBeginDirective(SMLoc L) { StringRef LiteralPrefixName = SE->getSymbol().getName(); TS.setLiteralSectionPrefix(LiteralPrefixName); RegionInProgress.emplace_back(BeginLoc, RegionDirectiveName, LiteralPrefixName); + } else if (RegionDirectiveName == "schedule" || RegionDirectiveName == "no-schedule") { + // Behave like GNU 'as'. + // The schedule directive is recognized only for compatibility with Tensilica’s assembler. + // This directive is ignored and has no effect on 'as'. + RegionInProgress.emplace_back(BeginLoc, RegionDirectiveName); } else { return Error(BeginLoc, "unsupported region directive"); } diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index a89a0a55f07f6f..3ac309290d9dd3 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -447,8 +447,12 @@ def BBCI : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"_bbci\t$s, $imm, $target", (BBCI AR:$s, uimm5:$imm, brtarget:$target)>; + def : InstAlias<"bbci.l\t$s, $imm, $target", (BBCI AR:$s, uimm5:$imm, brtarget:$target)>; +def : InstAlias<"_bbci.l\t$s, $imm, $target", (BBCI AR:$s, uimm5:$imm, brtarget:$target)>; + def BBSI : RRI8_Inst<0x07, (outs), (ins AR:$s, uimm5:$imm, brtarget:$target), "bbsi\t$s, $imm, $target", []> { @@ -463,6 +467,8 @@ def BBSI : RRI8_Inst<0x07, (outs), def : InstAlias<"bbsi.l\t$s, $imm, $target", (BBSI AR:$s, uimm5:$imm, brtarget:$target)>; +def : InstAlias<"_bbsi.l\t$s, $imm, $target", (BBSI AR:$s, uimm5:$imm, brtarget:$target)>; + def : Pat<(brcc SETGT, AR:$s, AR:$t, bb:$target), (BLT AR:$t, AR:$s, bb:$target)>; def : Pat<(brcc SETUGT, AR:$s, AR:$t, bb:$target), @@ -739,6 +745,8 @@ def MOVI_N : RI7_Inst<0xc, 0x0, (outs AR:$s), (ins imm32n_95:$imm7), "movi.n\t$s, $imm7", [(set AR:$s, imm32n_95:$imm7)]>, Requires<[HasDensity]>; +def : InstAlias<"_movi.n\t$s, $imm7", (MOVI_N AR:$s, imm32n_95:$imm7)>; + // Load instruction let mayLoad = 1, usesCustomInserter = 1 in { def L32I_N : RRRN_Inst<0x8, (outs AR:$t), (ins mem32n:$addr), @@ -1705,6 +1713,17 @@ let isBarrier = 1, isTerminator = 1 in { } } +//===----------------------------------------------------------------------===// +// Simulator instructions +//===----------------------------------------------------------------------===// + +def SIMCALL : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), + "simcall", []> { + let r = 0x5; + let s = 0x1; + let t = 0x0; +} + //===----------------------------------------------------------------------===// // Atomic patterns //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/Xtensa/Core/processor-control.s b/llvm/test/MC/Xtensa/Core/processor-control.s index 6295786dfb61af..64888e2aeadefa 100644 --- a/llvm/test/MC/Xtensa/Core/processor-control.s +++ b/llvm/test/MC/Xtensa/Core/processor-control.s @@ -84,3 +84,7 @@ xsr.sar a8 # CHECK-INST: xsr a8, sar # CHECK: encoding: [0x80,0x03,0x61] xsr a8, 3 + +# CHECK-INST: simcall +# CHECK: encoding: [0x00,0x51,0x00] +simcall From 8286130ce5183e9fb62ebc793fe6985357afea46 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 28 Mar 2024 11:16:21 +0300 Subject: [PATCH 234/261] [Toolchain][RISCV][Xtensa] Remove GCC installation support for Espressif toolchain --- clang/lib/Driver/CMakeLists.txt | 2 +- clang/lib/Driver/Driver.cpp | 1 - clang/lib/Driver/ToolChains/Arch/Xtensa.cpp | 42 ++ clang/lib/Driver/ToolChains/Arch/Xtensa.h | 30 ++ clang/lib/Driver/ToolChains/CommonArgs.cpp | 15 +- clang/lib/Driver/ToolChains/CommonArgs.h | 6 - clang/lib/Driver/ToolChains/EspBareMetal.cpp | 12 +- clang/lib/Driver/ToolChains/EspBareMetal.h | 4 + clang/lib/Driver/ToolChains/Gnu.cpp | 54 --- .../lib/Driver/ToolChains/RISCVToolchain.cpp | 27 +- clang/lib/Driver/ToolChains/RISCVToolchain.h | 6 - clang/lib/Driver/ToolChains/Xtensa.cpp | 378 ------------------ clang/lib/Driver/ToolChains/Xtensa.h | 91 ----- 13 files changed, 88 insertions(+), 580 deletions(-) create mode 100644 clang/lib/Driver/ToolChains/Arch/Xtensa.cpp create mode 100644 clang/lib/Driver/ToolChains/Arch/Xtensa.h delete mode 100644 clang/lib/Driver/ToolChains/Xtensa.cpp delete mode 100644 clang/lib/Driver/ToolChains/Xtensa.h diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt index 3a07d39645cf64..3c12521a9ea186 100644 --- a/clang/lib/Driver/CMakeLists.txt +++ b/clang/lib/Driver/CMakeLists.txt @@ -41,6 +41,7 @@ add_clang_library(clangDriver ToolChains/Arch/SystemZ.cpp ToolChains/Arch/VE.cpp ToolChains/Arch/X86.cpp + ToolChains/Arch/Xtensa.cpp ToolChains/AIX.cpp ToolChains/AMDGPU.cpp ToolChains/AMDGPUOpenMP.cpp @@ -82,7 +83,6 @@ add_clang_library(clangDriver ToolChains/VEToolchain.cpp ToolChains/WebAssembly.cpp ToolChains/XCore.cpp - ToolChains/Xtensa.cpp ToolChains/PPCLinux.cpp ToolChains/PPCFreeBSD.cpp ToolChains/InterfaceStubs.cpp diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 15ecddca844c47..55559423b91dda 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -49,7 +49,6 @@ #include "ToolChains/VEToolchain.h" #include "ToolChains/WebAssembly.h" #include "ToolChains/XCore.h" -#include "ToolChains/Xtensa.h" #include "ToolChains/ZOS.h" #include "clang/Basic/TargetID.h" #include "clang/Basic/Version.h" diff --git a/clang/lib/Driver/ToolChains/Arch/Xtensa.cpp b/clang/lib/Driver/ToolChains/Arch/Xtensa.cpp new file mode 100644 index 00000000000000..70d0895c92b245 --- /dev/null +++ b/clang/lib/Driver/ToolChains/Arch/Xtensa.cpp @@ -0,0 +1,42 @@ +//===--- Xtensa.cpp - Xtensa Helpers for Tools -------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "ToolChains/CommonArgs.h" +#include "clang/Driver/Driver.h" +#include "clang/Driver/DriverDiagnostic.h" +#include "llvm/TargetParser/XtensaTargetParser.h" + +using namespace clang::driver; +using namespace clang::driver::tools; +// using namespace clang; +using namespace llvm::opt; + +// Get features by CPU name +static void getXtensaFeaturesFromMcpu(const Driver &D, + const llvm::opt::ArgList &Args, + const llvm::opt::Arg *A, llvm::StringRef Mcpu, + std::vector &Features) { + if (llvm::Xtensa::parseCPUKind(Mcpu) == llvm::Xtensa::CK_INVALID) { + D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args); + } else { + llvm::SmallVector CPUFeatures; + llvm::Xtensa::getCPUFeatures(Mcpu, CPUFeatures); + for (auto &F : CPUFeatures) { + Features.push_back(F); + } + } +} + +// Xtensa target features. +void xtensa::getXtensaTargetFeatures(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + std::vector &Features) { + if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) + getXtensaFeaturesFromMcpu(D, Args, A, A->getValue(), Features); +} diff --git a/clang/lib/Driver/ToolChains/Arch/Xtensa.h b/clang/lib/Driver/ToolChains/Arch/Xtensa.h new file mode 100644 index 00000000000000..544f452042b836 --- /dev/null +++ b/clang/lib/Driver/ToolChains/Arch/Xtensa.h @@ -0,0 +1,30 @@ +//===--- Xtensa.h - Xtensa-specific Tool Helpers -----------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_ARCH_XTENSA_H +#define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_ARCH_XTENSA_H + +#include "clang/Driver/Driver.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Option/Option.h" +// #include +#include + +namespace clang { +namespace driver { +namespace tools { +namespace xtensa { +void getXtensaTargetFeatures(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + std::vector &Features); +} // end namespace xtensa +} // namespace tools +} // end namespace driver +} // end namespace clang + +#endif // LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_ARCH_XTENSA_H diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 6b2c8423dc67b0..b538c79fcbb9ce 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -19,11 +19,11 @@ #include "Arch/SystemZ.h" #include "Arch/VE.h" #include "Arch/X86.h" +#include "Arch/Xtensa.h" #include "HIPAMD.h" #include "Hexagon.h" #include "MSP430.h" #include "Solaris.h" -#include "Xtensa.h" #include "clang/Basic/CharInfo.h" #include "clang/Basic/CodeGenOptions.h" #include "clang/Basic/LangOptions.h" @@ -2802,16 +2802,3 @@ void tools::addHIPRuntimeLibArgs(const ToolChain &TC, Compilation &C, } } } - -void tools::addEspMultilibsPaths(const Driver &D, const MultilibSet &Multilibs, - const Multilib &Multilib, - StringRef CPU, - StringRef InstallPath, - ToolChain::path_list &Paths) { - if (const auto &PathsCallback = Multilibs.filePathsCallback()) - for (const auto &Path : PathsCallback(Multilib)) { - SmallString<256> LibPath(D.ResourceDir); - llvm::sys::path::append(LibPath, D.getTargetTriple(), CPU, Path, "lib"); - addPathIfExists(D, LibPath, Paths); - } -} diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h b/clang/lib/Driver/ToolChains/CommonArgs.h index cf9715f2d67d6d..807867f13a5c30 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.h +++ b/clang/lib/Driver/ToolChains/CommonArgs.h @@ -215,12 +215,6 @@ void addMachineOutlinerArgs(const Driver &D, const llvm::opt::ArgList &Args, void addOpenMPDeviceRTL(const Driver &D, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, StringRef BitcodeSuffix, const llvm::Triple &Triple); - -void addEspMultilibsPaths(const Driver &D, const MultilibSet &Multilibs, - const Multilib &Multilib, - StringRef CPU, - StringRef InstallPath, - ToolChain::path_list &Paths); } // end namespace tools } // end namespace driver } // end namespace clang diff --git a/clang/lib/Driver/ToolChains/EspBareMetal.cpp b/clang/lib/Driver/ToolChains/EspBareMetal.cpp index d88d3fcc50a186..cd4aa398919b20 100644 --- a/clang/lib/Driver/ToolChains/EspBareMetal.cpp +++ b/clang/lib/Driver/ToolChains/EspBareMetal.cpp @@ -217,9 +217,12 @@ void baremetal::esp::Linker::ConstructJob(Compilation &C, const JobAction &JA, Args.AddAllArgs(CmdArgs, options::OPT_L); Args.AddAllArgs(CmdArgs, options::OPT_u); ToolChain.AddFilePathLibArgs(Args, CmdArgs); - Args.AddAllArgs(CmdArgs, - {options::OPT_T_Group, options::OPT_e, options::OPT_s, - options::OPT_t, options::OPT_Z_Flag, options::OPT_r}); + Args.AddAllArgs(CmdArgs, options::OPT_T_Group); + Args.AddAllArgs(CmdArgs, options::OPT_e); + Args.AddAllArgs(CmdArgs, options::OPT_s); + Args.AddAllArgs(CmdArgs, options::OPT_t); + Args.AddAllArgs(CmdArgs, options::OPT_Z_Flag); + Args.AddAllArgs(CmdArgs, options::OPT_r); // TODO: add C++ includes and libs if compiling C++. @@ -263,6 +266,9 @@ void baremetal::esp::Assembler::ConstructJob(Compilation &C, const JobAction &JA if (!A->getOption().matches(options::OPT_g0)) CmdArgs.push_back("-g"); + if (Args.getLastArg(options::OPT_mtext_section_literals)) + CmdArgs.push_back("--text-section-literals"); + if (Args.hasFlag(options::OPT_fverbose_asm, options::OPT_fno_verbose_asm, false)) CmdArgs.push_back("-fverbose-asm"); diff --git a/clang/lib/Driver/ToolChains/EspBareMetal.h b/clang/lib/Driver/ToolChains/EspBareMetal.h index ea074937dbb82a..08c544e34ea023 100644 --- a/clang/lib/Driver/ToolChains/EspBareMetal.h +++ b/clang/lib/Driver/ToolChains/EspBareMetal.h @@ -84,6 +84,10 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; +void getXtensaTargetFeatures(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + std::vector &Features); + } // namespace esp } // namespace baremetal } // namespace tools diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index ef3e9e87667d31..f08be9224a1331 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1966,47 +1966,6 @@ static void findRISCVMultilibs(const Driver &D, Result.Multilibs = RISCVMultilibs; } -static void findXtensaMultilibs(const Driver &D, - const llvm::Triple &TargetTriple, - StringRef Path, const ArgList &Args, - DetectedMultilibs &Result) { - FilterNonExistent NonExistent(Path, "/crtbegin.o", D.getVFS()); - - StringRef cpu = Args.getLastArgValue(options::OPT_mcpu_EQ, "esp32"); - bool IsESP32 = cpu.equals("esp32"); - - Multilib::flags_list Flags; - - addMultilibFlag( - Args.hasFlag(options::OPT_fno_rtti, options::OPT_frtti, false), - "-fno-rtti", Flags); - - addMultilibFlag( - IsESP32 && Args.hasFlag(options::OPT_mfix_esp32_psram_cache_issue, - options::OPT_mfix_esp32_psram_cache_issue, false), - "-mfix-esp32-psram-cache-issue", Flags); - - MultilibBuilder NoRTTI = MultilibBuilder("/no-rtti").flag("-fno-rtti"); - MultilibBuilder FixPSRAM = - MultilibBuilder("/esp32-psram").flag("-mfix-esp32-psram-cache-issue"); - - MultilibSet XtensaMultilibs = MultilibSetBuilder() - .Maybe(FixPSRAM) - .Maybe(NoRTTI) - .makeMultilibSet() - .FilterOut(NonExistent); - - std::string cpu_name = cpu.str(); - XtensaMultilibs.setFilePathsCallback([cpu_name](const Multilib &M) { - return std::vector( - {M.gccSuffix(), - "/../../../../xtensa-" + cpu_name + "-elf/lib" + M.gccSuffix()}); - }); - - if (XtensaMultilibs.select(Flags, Result.SelectedMultilibs)) - Result.Multilibs = XtensaMultilibs; -} - static bool findBiarchMultilibs(const Driver &D, const llvm::Triple &TargetTriple, StringRef Path, const ArgList &Args, @@ -2643,13 +2602,6 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( "s390x-linux-gnu", "s390x-unknown-linux-gnu", "s390x-ibm-linux-gnu", "s390x-suse-linux", "s390x-redhat-linux"}; - static const char *const XtensaLibDirs[] = {"/lib"}; - static const char *const XtensaTriples[] = {"xtensa-esp-elf", - "xtensa-esp-unknown-elf", - "xtensa-esp32-elf", - "xtensa-esp32s2-elf", - "xtensa-esp32s3-elf"}; - using std::begin; using std::end; @@ -2921,10 +2873,6 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( LibDirs.append(begin(SystemZLibDirs), end(SystemZLibDirs)); TripleAliases.append(begin(SystemZTriples), end(SystemZTriples)); break; - case llvm::Triple::xtensa: - LibDirs.append(begin(XtensaLibDirs), end(XtensaLibDirs)); - TripleAliases.append(begin(XtensaTriples), end(XtensaTriples)); - break; default: // By default, just rely on the standard lib directories and the original // triple. @@ -2959,8 +2907,6 @@ bool Generic_GCC::GCCInstallationDetector::ScanGCCForMultilibs( findMSP430Multilibs(D, TargetTriple, Path, Args, Detected); } else if (TargetArch == llvm::Triple::avr) { // AVR has no multilibs. - } else if (TargetArch == llvm::Triple::xtensa) { - findXtensaMultilibs(D, TargetTriple, Path, Args, Detected); } else if (!findBiarchMultilibs(D, TargetTriple, Path, Args, NeedsBiarchSuffix, Detected)) { return false; diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp index 0a413dcca60033..5e4fa4d5331ff2 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp @@ -22,7 +22,6 @@ using namespace clang::driver::tools; using namespace clang; using namespace llvm::opt; - static void addMultilibsFilePaths(const Driver &D, const MultilibSet &Multilibs, const Multilib &Multilib, StringRef InstallPath, @@ -70,17 +69,6 @@ RISCVToolChain::RISCVToolChain(const Driver &D, const llvm::Triple &Triple, } else { getProgramPaths().push_back(D.Dir); } - - if (getTriple().getVendor() == llvm::Triple::Espressif) { - // TODO: need to detect multilibs when GCC installation is not available - addEspMultilibsPaths(D, Multilibs, SelectedMultilibs.back(), - Args.getLastArgValue(options::OPT_mcpu_EQ, "generic-rv32"), - D.getInstalledDir(), getLibraryPaths()); - addEspMultilibsPaths(D, Multilibs, SelectedMultilibs.back(), - Args.getLastArgValue(options::OPT_mcpu_EQ, "generic-rv32"), - D.getInstalledDir(), getFilePaths()); - } - getFilePaths().push_back(computeSysRoot() + "/lib"); } @@ -196,17 +184,7 @@ void RISCV::Linker::ConstructJob(Compilation &C, const JobAction &JA, } if (WantCRTs) { - /* Espressif toolcahin uses newlib. crt0.o from it refers to 'main' symbol. - In 'freestanding' mode 'main' is not marked as special symbol by clang, - so when compiling C++ program with 'clang++' 'main' gets mmangled - (if not decalred as 'extern "C"' ) and linker can not resolve it. - The problem can happen, for example, when cmake checks C++ compiler by buiding simple C++ code, - unfortunately 'main' function in that code is not decalred as 'extern "C"'. */ - bool Freestanding = - Args.hasFlag(options::OPT_ffreestanding, options::OPT_fhosted, false); - if (!Freestanding || ToolChain.getTriple().getVendor() != llvm::Triple::Espressif) { - CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); - } + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin))); } @@ -230,9 +208,6 @@ void RISCV::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("--start-group"); CmdArgs.push_back("-lc"); CmdArgs.push_back("-lgloss"); - if (ToolChain.getTriple().getVendor() == llvm::Triple::Espressif) { - CmdArgs.push_back("-lnosys"); - } CmdArgs.push_back("--end-group"); AddRunTimeLibs(ToolChain, ToolChain.getDriver(), CmdArgs, Args); } diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.h b/clang/lib/Driver/ToolChains/RISCVToolchain.h index 35f6cbeed408b1..cec817ef7190be 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.h +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.h @@ -35,12 +35,6 @@ class LLVM_LIBRARY_VISIBILITY RISCVToolChain : public Generic_ELF { addLibStdCxxIncludePaths(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; - bool IsIntegratedAssemblerDefault() const override { - if (GCCInstallation.getTriple().getVendor() == llvm::Triple::Espressif) - return false; - return Generic_ELF::IsIntegratedAssemblerDefault(); - } - protected: Tool *buildLinker() const override; diff --git a/clang/lib/Driver/ToolChains/Xtensa.cpp b/clang/lib/Driver/ToolChains/Xtensa.cpp deleted file mode 100644 index b5f90b4593504a..00000000000000 --- a/clang/lib/Driver/ToolChains/Xtensa.cpp +++ /dev/null @@ -1,378 +0,0 @@ -//===--- Xtensa.cpp - Xtensa ToolChain Implementations ----------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "Xtensa.h" -#include "CommonArgs.h" -#include "clang/Basic/Cuda.h" -#include "clang/Config/config.h" -#include "clang/Driver/Compilation.h" -#include "clang/Driver/Distro.h" -#include "clang/Driver/Driver.h" -#include "clang/Driver/DriverDiagnostic.h" -#include "clang/Driver/MultilibBuilder.h" -#include "clang/Driver/Options.h" -#include "llvm/Option/ArgList.h" -#include "llvm/Support/Path.h" -#include "llvm/Support/VirtualFileSystem.h" -#include "llvm/TargetParser/XtensaTargetParser.h" -#include - -using namespace clang::driver; -using namespace clang::driver::tools; -using namespace clang::driver::toolchains; -using namespace clang; -using namespace llvm::opt; - -/// Xtensa Toolchain -XtensaToolChain::XtensaToolChain(const Driver &D, const llvm::Triple &Triple, - const ArgList &Args) - : Generic_ELF(D, Triple, Args) { - - GCCInstallation.init(Triple, Args); - if (GCCInstallation.isValid()) { - for (auto *A : Args) { - std::string Str = A->getAsString(Args); - if (!Str.compare("-mlongcalls")) - A->claim(); - if (!Str.compare("-fno-tree-switch-conversion")) - A->claim(); - - // Currently don't use integrated assembler for assembler input files - if ((IsIntegratedAsm) && (Str.length() > 2)) { - std::string ExtSubStr = Str.substr(Str.length() - 2); - if (!ExtSubStr.compare(".s")) - IsIntegratedAsm = false; - if (!ExtSubStr.compare(".S")) - IsIntegratedAsm = false; - } - } - - // Currently don't use integrated assembler for assembler input files - if (IsIntegratedAsm) { - if (Args.getLastArgValue(options::OPT_x).equals("assembler")) - IsIntegratedAsm = false; - - if (Args.getLastArgValue(options::OPT_x).equals("assembler-with-cpp")) - IsIntegratedAsm = false; - } - - Multilibs = GCCInstallation.getMultilibs(); - SelectedMultilibs.assign({GCCInstallation.getMultilib()}); - - GCCLibAndIncVersion = GCCInstallation.getVersion().Text; - GCCToolchainName = GCCInstallation.getTriple().str(); - SmallString<128> Path(GCCInstallation.getParentLibPath()); - llvm::sys::path::append(Path, ".."); - GCCToolchainDir = Path.c_str(); - - SmallString<128> Libs1(GCCToolchainDir); - llvm::sys::path::append(Libs1, "lib", "gcc", GCCToolchainName, - GCCLibAndIncVersion); - if (!SelectedMultilibs.back().gccSuffix().empty()) - llvm::sys::path::append(Libs1, SelectedMultilibs.back().gccSuffix()); - getFilePaths().push_back(Libs1.c_str()); - - SmallString<128> Libs2(GCCToolchainDir); - llvm::sys::path::append(Libs2, GCCToolchainName, "lib"); - if (!SelectedMultilibs.back().gccSuffix().empty()) - llvm::sys::path::append(Libs2, SelectedMultilibs.back().gccSuffix()); - getFilePaths().push_back(Libs2.c_str()); - - ToolChain::path_list &PPaths = getProgramPaths(); - // Multilib cross-compiler GCC installations put ld in a triple-prefixed - // directory of the GCC installation parent dir. - StringRef ParentDir = llvm::sys::path::parent_path(GCCInstallation.getParentLibPath()); - - SmallString<128> PathTripleBin(ParentDir); - llvm::sys::path::append(PathTripleBin, GCCInstallation.getTriple().str()); - llvm::sys::path::append(PathTripleBin, "bin"); - PPaths.push_back(PathTripleBin.c_str()); - - SmallString<128> PathBin(ParentDir); - llvm::sys::path::append(PathBin, "bin"); - PPaths.push_back(PathBin.c_str()); - - if (!getDriver().SysRoot.empty()) { - SmallString<128> SysRoot(computeSysRoot()); - llvm::sys::path::append(SysRoot, "lib"); - getFilePaths().push_back(SysRoot.c_str()); - } - } else { - getProgramPaths().push_back(D.Dir); - SmallString<128> SysRoot(computeSysRoot()); - llvm::sys::path::append(SysRoot, "lib"); - getFilePaths().push_back(SysRoot.c_str()); - } - - if (getTriple().getVendor() == llvm::Triple::Espressif) { - StringRef CpuName = GetTargetCPUVersion(Args, Triple); - - // TODO: need to detect multilibs when GCC installation is not available - addEspMultilibsPaths(D, Multilibs, SelectedMultilibs.back(), CpuName, - D.getInstalledDir(), getLibraryPaths()); - addEspMultilibsPaths(D, Multilibs, SelectedMultilibs.back(), CpuName, - D.getInstalledDir(), getFilePaths()); - } -} - -Tool *XtensaToolChain::buildLinker() const { - return new tools::xtensa::Linker(*this); -} - -Tool *XtensaToolChain::buildAssembler() const { - return new tools::xtensa::Assembler(*this); -} - -void XtensaToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, - ArgStringList &CC1Args) const { - if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc)) - return; - - if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) { - SmallString<128> Dir(getDriver().ResourceDir); - llvm::sys::path::append(Dir, "include"); - addSystemInclude(DriverArgs, CC1Args, Dir.str()); - } - - if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) { - if (!getDriver().SysRoot.empty()) { - SmallString<128> Dir(getDriver().SysRoot); - llvm::sys::path::append(Dir, "include"); - addSystemInclude(DriverArgs, CC1Args, Dir.str()); - } else if (GCCInstallation.isValid()) { - SmallString<128> Path1(GCCToolchainDir); - llvm::sys::path::append(Path1, GCCToolchainName, "sys-include"); - SmallString<128> Path2(GCCToolchainDir); - llvm::sys::path::append(Path2, GCCToolchainName, "include"); - - const StringRef Paths[] = {Path1, Path2}; - addSystemIncludes(DriverArgs, CC1Args, Paths); - } else { - SmallString<128> Dir(computeSysRoot()); - llvm::sys::path::append(Dir, "include"); - addSystemInclude(DriverArgs, CC1Args, Dir.str()); - } - } -} - -void XtensaToolChain::addLibStdCxxIncludePaths( - const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CC1Args) const { - if (!GCCInstallation.isValid()) - return; - - const GCCVersion &Version = GCCInstallation.getVersion(); - StringRef TripleStr = GCCInstallation.getTriple().str(); - addLibStdCXXIncludePaths(computeSysRoot() + "/include/c++/" + Version.Text, - TripleStr, "", DriverArgs, CC1Args); -} - -std::string XtensaToolChain::computeSysRoot() const { - if (!getDriver().SysRoot.empty()) - return getDriver().SysRoot; - - SmallString<128> SysRootDir; - if (GCCInstallation.isValid()) { - StringRef LibDir = GCCInstallation.getParentLibPath(); - StringRef TripleStr = GCCInstallation.getTriple().str(); - llvm::sys::path::append(SysRootDir, LibDir, "..", TripleStr); - } else { - // Use the triple as provided to the driver. Unlike the parsed triple - // this has not been normalized to always contain every field. - llvm::sys::path::append(SysRootDir, getDriver().Dir, "..", - getDriver().getTargetTriple()); - } - - if (!llvm::sys::fs::exists(SysRootDir)) - return std::string(); - - return std::string(SysRootDir.str()); -} - -ToolChain::CXXStdlibType -XtensaToolChain::GetCXXStdlibType(const ArgList &Args) const { - Arg *A = Args.getLastArg(options::OPT_stdlib_EQ); - if (!A) - return ToolChain::CST_Libstdcxx; - - StringRef Value = A->getValue(); - if (Value != "libstdc++") - getDriver().Diag(diag::err_drv_invalid_stdlib_name) << A->getAsString(Args); - - return ToolChain::CST_Libstdcxx; -} - -ToolChain::UnwindLibType -XtensaToolChain::GetUnwindLibType(const llvm::opt::ArgList &Args) const { - return ToolChain::UNW_None; -} - -const StringRef XtensaToolChain::GetTargetCPUVersion(const ArgList &Args, const llvm::Triple &Triple) { - StringRef CPUName; - if (Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ)) { - CPUName = A->getValue(); - } else if (Triple.getVendor() == llvm::Triple::Espressif) { - // 'esp32' is default for 'xtensa-esp-xxx' targets, - // for generic 'xtensa' target CPU should be always specified explicitly with '-mcpu' - CPUName = "esp32"; - - } - return CPUName; -} - -void tools::xtensa::Assembler::ConstructJob(Compilation &C, const JobAction &JA, - const InputInfo &Output, - const InputInfoList &Inputs, - const ArgList &Args, - const char *LinkingOutput) const { - const auto &TC = - static_cast(getToolChain()); - - claimNoWarnArgs(Args); - ArgStringList CmdArgs; - - CmdArgs.push_back("-o"); - CmdArgs.push_back(Output.getFilename()); - - CmdArgs.push_back("-c"); - - if (Args.hasArg(options::OPT_v)) - CmdArgs.push_back("-v"); - - if (Arg *A = Args.getLastArg(options::OPT_g_Group)) - if (!A->getOption().matches(options::OPT_g0)) - CmdArgs.push_back("-g"); - - if (Args.getLastArg(options::OPT_mtext_section_literals)) - CmdArgs.push_back("--text-section-literals"); - - if (Args.hasFlag(options::OPT_fverbose_asm, options::OPT_fno_verbose_asm, - false)) - CmdArgs.push_back("-fverbose-asm"); - - Args.AddAllArgValues(CmdArgs, options::OPT_Wa_COMMA, options::OPT_Xassembler); - - for (const auto &II : Inputs) - CmdArgs.push_back(II.getFilename()); - - SmallString<128> Asm(TC.GCCToolchainDir); - llvm::sys::path::append(Asm, "bin", - TC.GCCToolchainName + "-" + getShortName()); - - C.addCommand( - std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), - Args.MakeArgString(Asm), CmdArgs, Inputs)); -} - -void xtensa::Linker::ConstructJob(Compilation &C, const JobAction &JA, - const InputInfo &Output, - const InputInfoList &Inputs, - const ArgList &Args, - const char *LinkingOutput) const { - ArgStringList CmdArgs; - SmallString<128> Linker; - bool WantCRTs = - !Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles); - const auto &ToolChain = - static_cast(getToolChain()); - const Driver &D = ToolChain.getDriver(); - - if (!D.SysRoot.empty()) - CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot)); - - bool LinkerIsLLD; - std::string LinkerPath = ToolChain.GetLinkerPath(&LinkerIsLLD); - if (!LinkerIsLLD) { - if (ToolChain.GCCToolchainName != "") { - Linker.assign(ToolChain.GCCToolchainDir); - llvm::sys::path::append( - Linker, "bin", ToolChain.GCCToolchainName + "-" + getShortName()); - } else if (ToolChain.getTriple().getVendor() == llvm::Triple::Espressif) { - // ESP workaround, if there is no GCC installation we need to use xtensa-espXX-elf prefix for ld. - // so guess it basing on selected mcpu - Linker.assign(ToolChain.getDriver().Dir); - llvm::sys::path::append( - Linker, "xtensa-" + ToolChain.GetTargetCPUVersion(Args, ToolChain.getTriple()) + "-elf-" + getShortName()); - } else { - Linker.assign(LinkerPath); - } - } else { - Linker.assign(LinkerPath); - } - - const char *crtbegin, *crtend; - auto RuntimeLib = ToolChain.GetRuntimeLibType(Args); - if (RuntimeLib == ToolChain::RLT_Libgcc) { - crtbegin = "crtbegin.o"; - crtend = "crtend.o"; - } else { - assert(RuntimeLib == ToolChain::RLT_CompilerRT); - crtbegin = ToolChain.getCompilerRTArgString(Args, "crtbegin", - ToolChain::FT_Object); - crtend = - ToolChain.getCompilerRTArgString(Args, "crtend", ToolChain::FT_Object); - } - - if (WantCRTs) { - // TODO: The crt0.o is not used for esp targets, but maybe used in - // future for other vendors - if (ToolChain.getTriple().getVendor() != llvm::Triple::Espressif) - CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); - CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin))); - } - - AddLinkerInputs(getToolChain(), Inputs, Args, CmdArgs, JA); - - Args.AddAllArgs(CmdArgs, options::OPT_L); - ToolChain.AddFilePathLibArgs(Args, CmdArgs); - Args.addAllArgs(CmdArgs, - {options::OPT_T_Group, options::OPT_e, options::OPT_s, - options::OPT_t, options::OPT_u_Group}); - - if (!Args.hasArg(options::OPT_nostdlib) && - !Args.hasArg(options::OPT_nodefaultlibs)) { - if (ToolChain.ShouldLinkCXXStdlib(Args)) - ToolChain.AddCXXStdlibLibArgs(Args, CmdArgs); - AddRunTimeLibs(ToolChain, ToolChain.getDriver(), CmdArgs, Args); - } - - if (WantCRTs) - CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtend))); - - CmdArgs.push_back("-o"); - CmdArgs.push_back(Output.getFilename()); - C.addCommand( - std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), - Args.MakeArgString(Linker), CmdArgs, Inputs)); -} - -// Get features by CPU name -static void getXtensaFeaturesFromMcpu(const Driver &D, - const llvm::opt::ArgList &Args, - const llvm::opt::Arg *A, StringRef Mcpu, - std::vector &Features) { - if (llvm::Xtensa::parseCPUKind(Mcpu) == llvm::Xtensa::CK_INVALID) { - D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args); - } else { - SmallVector CPUFeatures; - llvm::Xtensa::getCPUFeatures(Mcpu, CPUFeatures); - for (auto &F : CPUFeatures) { - Features.push_back(F); - } - } -} - -// Xtensa target features. -void xtensa::getXtensaTargetFeatures(const Driver &D, const llvm::Triple &Triple, - const llvm::opt::ArgList &Args, - std::vector &Features) { - if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) - getXtensaFeaturesFromMcpu(D, Args, A, A->getValue(), Features); -} diff --git a/clang/lib/Driver/ToolChains/Xtensa.h b/clang/lib/Driver/ToolChains/Xtensa.h deleted file mode 100644 index d7b68e4c10782d..00000000000000 --- a/clang/lib/Driver/ToolChains/Xtensa.h +++ /dev/null @@ -1,91 +0,0 @@ -//===--- Xtensa.h - Xtensa Tool and ToolChain Implementations ---*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_Xtensa_H -#define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_Xtensa_H - -#include "Gnu.h" -#include "clang/Driver/InputInfo.h" -#include "clang/Driver/Tool.h" -#include "clang/Driver/ToolChain.h" - -namespace clang { -namespace driver { -namespace toolchains { - -class LLVM_LIBRARY_VISIBILITY XtensaToolChain : public Generic_ELF { -protected: - Tool *buildLinker() const override; - Tool *buildAssembler() const override; - -public: - XtensaToolChain(const Driver &D, const llvm::Triple &Triple, - const llvm::opt::ArgList &Args); - void - AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CC1Args) const override; - void - addLibStdCxxIncludePaths(const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CC1Args) const override; - CXXStdlibType GetCXXStdlibType(const llvm::opt::ArgList &Args) const override; - UnwindLibType GetUnwindLibType(const llvm::opt::ArgList &Args) const override; - - bool IsIntegratedAssemblerDefault() const override { - return (IsIntegratedAsm || (GCCToolchainName == "")); - } - - static const StringRef GetTargetCPUVersion(const llvm::opt::ArgList &Args, const llvm::Triple &Triple); - - bool IsIntegratedAsm = true; - std::string GCCLibAndIncVersion = ""; - std::string GCCToolchainName = ""; - std::string GCCToolchainDir = ""; - -private: - std::string computeSysRoot() const override; -}; - -} // end namespace toolchains - -namespace tools { -namespace xtensa { -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { -public: - Linker(const ToolChain &TC) - : Tool("Xtensa::Linker", "ld", TC) {} - bool hasIntegratedCPP() const override { return false; } - bool isLinkJob() const override { return true; } - void ConstructJob(Compilation &C, const JobAction &JA, - const InputInfo &Output, const InputInfoList &Inputs, - const llvm::opt::ArgList &TCArgs, - const char *LinkingOutput) const override; -}; - -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { -public: - Assembler(const ToolChain &TC) - : Tool("Xtensa::Assembler", "as", TC) {} - - bool hasIntegratedCPP() const override { return false; } - void ConstructJob(Compilation &C, const JobAction &JA, - const InputInfo &Output, const InputInfoList &Inputs, - const llvm::opt::ArgList &TCArgs, - const char *LinkingOutput) const override; -}; - -void getXtensaTargetFeatures(const Driver &D, const llvm::Triple &Triple, - const llvm::opt::ArgList &Args, - std::vector &Features); -} // end namespace xtensa -} // end namespace tools -} // end namespace driver -} // end namespace clang - -#endif // LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_Xtensa_H From 0e66b3d6436a6469d0f8ea50502e68c5630f56ab Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Thu, 22 Feb 2024 12:54:13 +0300 Subject: [PATCH 235/261] [Clang] Fix undefined std::errc for MinGW build --- clang/lib/Interpreter/IncrementalParser.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Interpreter/IncrementalParser.cpp b/clang/lib/Interpreter/IncrementalParser.cpp index 370bcbfee8b014..3c00eeac93df5a 100644 --- a/clang/lib/Interpreter/IncrementalParser.cpp +++ b/clang/lib/Interpreter/IncrementalParser.cpp @@ -126,7 +126,7 @@ class IncrementalAction : public WrapperFrontendAction { switch (CI.getFrontendOpts().ProgramAction) { default: Err = llvm::createStringError( - std::errc::state_not_recoverable, + std::errc::not_supported, "Driver initialization failed. " "Incremental mode for action %d is not supported", CI.getFrontendOpts().ProgramAction); From 0ff979b0d9ab342047ad830fde94f95d042d5512 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Tue, 2 Apr 2024 02:46:46 +0300 Subject: [PATCH 236/261] [LLD] Disable x86_64 specific test if target is no enabled --- lld/test/ELF/lto/resolution-err.ll | 1 + 1 file changed, 1 insertion(+) diff --git a/lld/test/ELF/lto/resolution-err.ll b/lld/test/ELF/lto/resolution-err.ll index f9855abaff3279..452d942c72d81f 100644 --- a/lld/test/ELF/lto/resolution-err.ll +++ b/lld/test/ELF/lto/resolution-err.ll @@ -1,4 +1,5 @@ ; UNSUPPORTED: system-windows +; REQUIRES: target=x86_64-unknown-linux-gnu ; REQUIRES: shell, non-root-user ; RUN: llvm-as %s -o %t.bc ; RUN: touch %t.resolution.txt From 1008e23c68e44859a229e100a926e232d824fa12 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Thu, 19 Oct 2023 18:36:22 +0300 Subject: [PATCH 237/261] esp/ci: Use CMake-based build scripts --- .gitlab-ci.yml | 547 +++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 462 insertions(+), 85 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 4e11284b1b001c..09891b869dfe0b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,114 +1,491 @@ stages: + - test_build - build - pack - - macos_codesign + - sign - private_deploy - test - public_deploy + - update_idf_tools image: ${CI_DOCKER_REGISTRY}/llvm-build:4 variables: - - # move all these to CI/CD settings - REL_SFX: "llvm" - CLANG_VER: "17" - GCC_REL_VER: "12.2.0_20230208" - NEWLIB_REF: "esp-4.1.0_20230425" - BINUTILS_REF: "esp-2.39.0_20230208" - XTENSA_OVERLAYS_REF: "master" - LLVM_GCC_TESTSUITE_REF: "esp-16.0.0-20230425" - XTENSA_CLANG_TOOLCHAIN_REF: "esp-16.0.0-20230516" - + ESP_LLVM_EMBEDDED_TOOLCHAIN_REF: "master" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 - PLATFORM_NAME_LINUX: "linux-amd64" - PLATFORM_NAME_LINUX_ARMHF: "linux-armhf" - PLATFORM_NAME_LINUX_ARM64: "linux-arm64" - PLATFORM_NAME_WIN: "win64" - PLATFORM_NAME_MACOS: "macos" - PLATFORM_NAME_MACOS_ARM64: "macos-arm64" - - GCC_PLATFORM_NAME_LINUX: "i686-linux-gnu" - GCC_PLATFORM_NAME_LINUX_ARMHF: "arm-linux-gnueabihf" - GCC_PLATFORM_NAME_LINUX_ARM64: "aarch64-linux-gnu" - GCC_PLATFORM_NAME_WIN: "i686-w64-mingw32" - GCC_PLATFORM_NAME_MACOS: "x86_64-apple-darwin" - GCC_PLATFORM_NAME_MACOS_ARM64: "aarch64-apple-darwin" - - ARCHIVE_TOOL_LINUX: "tar -cJf" - UNARCHIVE_TOOL_LINUX: "tar -xf" - ARCHIVE_EXT_LINUX: "tar.xz" - - ARCHIVE_TOOL_WIN: "zip -9 -r" - UNARCHIVE_TOOL_WIN: "unzip" - ARCHIVE_EXT_WIN: "zip" - - PACK_ARCHIVE_TOOL_WIN: "tar -h -cJf" - PACK_UNARCHIVE_TOOL_WIN: "${UNARCHIVE_TOOL_LINUX}" - PACK_ARCHIVE_EXT_WIN: "${ARCHIVE_EXT_LINUX}" - - ARCHIVE_TOOL_MACOS: "tar -cJf" - UNARCHIVE_TOOL_MACOS: "tar -xf" - ARCHIVE_EXT_MACOS: "tar.xz" - - ARCHIVE_TOOL_NEWLIB: ${ARCHIVE_TOOL_LINUX} - UNARCHIVE_TOOL_NEWLIB: ${UNARCHIVE_TOOL_LINUX} - ARCHIVE_EXT_NEWLIB: ${ARCHIVE_EXT_LINUX} - - ARCHIVE_TOOL_COMPILER_RT: ${ARCHIVE_TOOL_LINUX} - UNARCHIVE_TOOL_COMPILER_RT: ${UNARCHIVE_TOOL_LINUX} - ARCHIVE_EXT_COMPILER_RT: ${ARCHIVE_EXT_LINUX} - - LIBS_ARCHIVE_TOOL: "${ARCHIVE_TOOL_LINUX}" - LIBS_UNARCHIVE_TOOL: "${UNARCHIVE_TOOL_LINUX}" - LIBS_ARCHIVE_EXT: "${ARCHIVE_EXT_LINUX}" - + CROSS_WIN_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-win:1 DIST_DIR: "dist" BUILD_DIR: "build" - DOWNLOADS_DIR: "downloads" -########################################################################### -#################### START OF TEMPORARY LEGACY CODE ####################### -# TODO: the code below is to be removed after migration to new build script - CONF_TARGET: "xtensa-esp32-elf" - XTENSA_CLANG_TOOLCHAIN: "${CONF_TARGET}-clang" -##################### END OF TEMPORARY LEGACY CODE ######################## -########################################################################### - -.use_ci_tools_snippet: &use_ci_tools_snippet | +.use_ci_tools: &use_ci_tools | curl -sSL ${CIT_LOADER_URL} -o cit_loader.sh && sh cit_loader.sh source citools/import_functions -.use_ci_tools: +.add_gitlab_key: &add_gitlab_key | + cit_add_ssh_key "${GITLAB_KEY}" + +.get_toolchain_build_scripts: &get_toolchain_build_scripts | + git clone -b ${ESP_LLVM_EMBEDDED_TOOLCHAIN_REF} ${GITLAB_SSH_SERVER}/${ESP_LLVM_EMBEDDED_TOOLCHAIN_REPO}.git + + +before_script: + - *use_ci_tools + - *add_gitlab_key + +.build_template: + tags: [ "amd64", "build" ] + artifacts: + paths: + - ${DIST_DIR}/ + - ${BUILD_DIR}/*.log + when: always + expire_in: 1 day + variables: + USE_LINKER: "ld" + CROSS_BUILD_MINGW: "OFF" + SKIP_TESTS: "ON" + PACK_DISTRO: "ON" + after_script: + # help to identify that build failed due to OOM + - > + if [ $CI_JOB_STATUS == 'failed' ]; then + [ ! -f "${BUILD_DIR}/build.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/build.log || true + [ ! -f "${BUILD_DIR}/tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/tests.log || true + [ ! -f "${BUILD_DIR}/lld-tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/lld-tests.log || true + fi script: - - *use_ci_tools_snippet + - *get_toolchain_build_scripts + - LLVM_PROJECT_PATH=$PWD + - BUILD_PATH=$PWD/${BUILD_DIR} + - INST_PATH=$PWD/_install_dir + - mkdir -p ${BUILD_PATH} + - BUILD_HOST=$(gcc -dumpmachine) + # Build target libraries once when doing native build + - > + if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then + echo "Enable target libraries build" + export USE_LIBC="newlib"; + export USE_LIBCXX="libstdcxx"; + export USE_RTLIB="compiler-rt;libgcc"; + else + echo "Disable target libraries for cross-build" + export USE_LIBC=none; + export USE_LIBCXX=""; + export USE_RTLIB=""; + fi + # build toolchain core w/o any libs and GNU components + - cmake $PWD/esp-llvm-embedded-toolchain -GNinja + -DFETCHCONTENT_SOURCE_DIR_LLVMPROJECT=${LLVM_PROJECT_PATH} + -DNEWLIB_REPO_URL="${GITLAB_SSH_SERVER}/${NEWLIB_REPO_PATH}.git" + -DBINUTILS_REPO_URL="${GITLAB_SSH_SERVER}/${BINUTILS_REPO_PATH}.git" + -DXTENSA_OVERLAYS_REPO_URL="${GITLAB_SSH_SERVER}/${XTENSA_OVERLAYS_REPO_PATH}.git" + -DFETCHCONTENT_QUIET=OFF + -DESP_GNU_TOOLCHAIN_VER="13.2.0_20230928" + -DLLVM_TOOLCHAIN_CROSS_BUILD_MINGW=${CROSS_BUILD_MINGW} + -DUSE_LIBC=${USE_LIBC} + -DUSE_LIBCXX=${USE_LIBCXX} + -DUSE_RTLIB=${USE_RTLIB} + -DUSE_BINUTILS=ON + -DESP_TOOLCHAIN=ON + -DHOST_TRIPLE=${CONF_HOST} + -DLLVM_TOOLCHAIN_ENABLED_TARGETS="${TARGET}" + -DLLVM_USE_LINKER=${USE_LINKER} + -DLLVM_PARALLEL_LINK_JOBS=2 + -DLLVM_PARALLEL_COMPILE_JOBS=2 + -DCLANG_REPOSITORY_STRING="${GH_REPO_HTTPS}" + -DCPACK_ARCHIVE_THREADS=0 + -B ${BUILD_PATH} 2>&1 + --install-prefix=$INST_PATH > ${BUILD_PATH}/build.log + # Do not run unit tests for cross-builds. + # Run as non-root user because permission tests fail when run by root. + - > + if [[ "${CONF_HOST}" == "${BUILD_HOST}" && "${SKIP_TESTS}" != "ON" ]]; then + echo "Run LLVM/Clang unit tests"; + export CUR_USER=$(whoami); + useradd -m test_runner; + chown -R test_runner ${BUILD_PATH}; + touch ${BUILD_PATH}/tests.log; + chmod o+w ${BUILD_PATH}/tests.log; + runuser -u test_runner -- ninja -C ${BUILD_PATH} check-all 2>&1 > ${BUILD_PATH}/tests.log; + echo "Run Compiler-RT unit tests"; + touch ${BUILD_PATH}/compiler-rt-tests.log; + chmod o+w ${BUILD_PATH}/compiler-rt-tests.log; + runuser -u test_runner -- ninja -C ${BUILD_PATH} check-compiler-rt 2>&1 > ${BUILD_PATH}/compiler-rt-tests.log; + echo "Run LLD unit tests"; + touch ${BUILD_PATH}/lld-tests.log; + chmod o+w ${BUILD_PATH}/lld-tests.log; + runuser -u test_runner -- ninja -C ${BUILD_PATH} check-lld 2>&1 > ${BUILD_PATH}/lld-tests.log; + chown -R ${CUR_USER} ${BUILD_PATH}; + fi + - if [ "${PACK_DISTRO}" == "OFF" ]; then exit 0; fi + # pack distro + - mkdir -p ${PWD}/${DIST_DIR} + - ninja -C ${BUILD_PATH} package-llvm-toolchain 2>&1 >> ${BUILD_PATH}/build.log + - DISTRO_PACK_PATH=$(ninja -C ${BUILD_PATH} print-llvm-toolchain-package-path | tail -n 1) + - echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" + - mv ${DISTRO_PACK_PATH} ${PWD}/${DIST_DIR}/ + - ARCHIVE_NAME=$(basename ${DISTRO_PACK_PATH}) + - echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/dist_name_${CONF_HOST}_${TARGET} + # pack distro with standalone libs + - ninja -C ${BUILD_PATH} package-llvm-standalone-libs 2>&1 >> ${BUILD_PATH}/build.log + - DISTRO_PACK_PATH=$(ninja -C ${BUILD_PATH} print-llvm-standalone-libs-package-path | tail -n 1) + - echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" + - mv ${DISTRO_PACK_PATH} ${PWD}/${DIST_DIR}/ + - ARCHIVE_NAME=$(basename ${DISTRO_PACK_PATH}) + - echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/dist_name_libs_${CONF_HOST}_${TARGET} + # pack target libraries to be re-used in distros for other platforms + - > + if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then + ninja -C ${BUILD_PATH} package-llvm-toolchain-target-libs 2>&1 >> ${BUILD_PATH}/build.log + DISTRO_PACK_PATH=$(ninja -C ${BUILD_PATH} print-llvm-toolchain-target-libs-package-path | tail -n 1) + echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" + mv ${DISTRO_PACK_PATH} ${PWD}/${DIST_DIR}/ + ARCHIVE_NAME=$(basename ${DISTRO_PACK_PATH}) + echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/target_libs_arch_name + fi -.add_gitlab_key_snippet: &add_gitlab_key_snippet | - cit_add_ssh_key "${GITLAB_KEY}" +build_and_test: + extends: .build_template + stage: test_build + variables: + TARGET: "Xtensa;RISCV" + SKIP_TESTS: "OFF" + PACK_DISTRO: "OFF" + CONF_HOST: "x86_64-linux-gnu" + USE_LINKER: "gold" + +.build_toolchain_template: + extends: .build_template + stage: build + parallel: + matrix: + - TARGET: + - Xtensa + - RISCV + +.build_linux-gnu_template: + extends: .build_toolchain_template + variables: + USE_LINKER: "gold" + +build_x86_64-linux-gnu: + extends: .build_linux-gnu_template + variables: + CONF_HOST: "x86_64-linux-gnu" + +build_x86_64-w64-mingw32: + extends: .build_toolchain_template + image: ${CROSS_WIN_IMAGE} + variables: + USE_LINKER: "" + CONF_HOST: "x86_64-w64-mingw32" + CROSS_BUILD_MINGW: "ON" + +build_arm-linux-gnueabihf: + extends: .build_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + variables: + CONF_HOST: "arm-linux-gnueabihf" + +build_aarch64-linux-gnu: + extends: .build_linux-gnu_template + image: ${CROSS_ARM_IMAGE} + variables: + CONF_HOST: "aarch64-linux-gnu" + +build_x86_64-apple-darwin: + extends: .build_toolchain_template + variables: + CONF_HOST: "x86_64-apple-darwin21.1" + +build_aarch64-apple-darwin: + extends: .build_toolchain_template + variables: + CONF_HOST: "aarch64-apple-darwin21.1" -.add_gitlab_key: +.pack_x86_64-linux-gnu_template: + stage: pack + tags: [ "amd64", "build" ] + artifacts: + paths: + - ${DIST_DIR}/ + when: always + expire_in: 1 day script: - - *add_gitlab_key_snippet + - pushd ${DIST_DIR} + - ls -l + - TARGET_LIBS_PACK_FILE=$(cat target_libs_arch_name) + - rm -f target_libs_arch_name ${TARGET_LIBS_PACK_FILE} + - ls -l -# LLVM Build System used the remote address to show detailed version info, we'll change it to the public repository -.fix_origin_remote_for_public_snippet: &fix_origin_remote_for_public_snippet | - git remote set-url origin "${GH_REPO_HTTPS}" +pack_x86_64-linux-gnu_riscv: + extends: .pack_x86_64-linux-gnu_template + needs: + - job: "build_x86_64-linux-gnu: [RISCV]" -.fix_origin_remote_for_public: +pack_x86_64-linux-gnu_xtensa: + extends: .pack_x86_64-linux-gnu_template + needs: + - job: "build_x86_64-linux-gnu: [Xtensa]" + +.pack_template: + stage: pack + tags: [ "amd64", "build" ] + artifacts: + paths: + - ${DIST_DIR}/ + when: always + expire_in: 1 day + variables: + PACK_TOOL: "tar cJf" + UNPACK_TOOL: "tar xJf" + script: + - *get_toolchain_build_scripts + # update distro + - pushd ${DIST_DIR} + - ls -l + - DISTRO_PACK_FILE=$(cat dist_name_${CONF_HOST}_${TARGET}) + - echo "DISTRO_PACK_FILE=${DISTRO_PACK_FILE}" + - ${UNPACK_TOOL} ${DISTRO_PACK_FILE} + - DISTRO_PACK_DIR=$(tar tJf ${DISTRO_PACK_FILE} | sed -e 's@/.*@@' | uniq) + - ls -l $PWD/${DISTRO_PACK_DIR}/lib/clang-runtimes/ + - echo "DISTRO_PACK_DIR=${DISTRO_PACK_DIR}" + - rm -f ${DISTRO_PACK_FILE} + - TARGET_LIBS_PACK_FILE=$(cat target_libs_arch_name) + - rm -f target_libs_arch_name + - echo "TARGET_LIBS_PACK_FILE=${TARGET_LIBS_PACK_FILE}" + - tar xJfv ${TARGET_LIBS_PACK_FILE} + - rm -f ${TARGET_LIBS_PACK_FILE} + - ls -l $PWD + - ls -l $PWD/${DISTRO_PACK_DIR} + - ls -l $PWD/${DISTRO_PACK_DIR}/lib/clang-runtimes/ + # both distro and target libs archives have the same root dir name, + # so that dir contains everything we need to re-pack after unpacking steps above + - ${PACK_TOOL} ${DISTRO_PACK_FILE} ${DISTRO_PACK_DIR} + - rm -rf ${DISTRO_PACK_DIR} + # remove x86_64-linux-gnu artifacts + - > + if [ "${CONF_HOST}" != "x86_64-linux-gnu" ]; then + DISTRO_PACK_FILE=$(cat dist_name_x86_64-linux-gnu_${TARGET}) + rm -f ${DISTRO_PACK_FILE} dist_name_x86_64-linux-gnu_${TARGET} + DISTRO_PACK_FILE=$(cat dist_name_libs_x86_64-linux-gnu_${TARGET}) + rm -f ${DISTRO_PACK_FILE} dist_name_libs_x86_64-linux-gnu_${TARGET} + fi + - ls -l + +pack_x86_64-w64-mingw32_riscv: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [RISCV]" + - job: "build_x86_64-w64-mingw32: [RISCV]" + variables: + CONF_HOST: "x86_64-w64-mingw32" + TARGET: "RISCV" + +pack_x86_64-w64-mingw32_xtensa: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [Xtensa]" + - job: "build_x86_64-w64-mingw32: [Xtensa]" + variables: + CONF_HOST: "x86_64-w64-mingw32" + TARGET: "Xtensa" + +pack_arm-linux-gnueabihf_riscv: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [RISCV]" + - job: "build_arm-linux-gnueabihf: [RISCV]" + variables: + CONF_HOST: "arm-linux-gnueabihf" + TARGET: "RISCV" + +pack_arm-linux-gnueabihf_xtensa: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [Xtensa]" + - job: "build_arm-linux-gnueabihf: [Xtensa]" + variables: + CONF_HOST: "arm-linux-gnueabihf" + TARGET: "Xtensa" + +pack_aarch64-linux-gnu_riscv: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [RISCV]" + - job: "build_aarch64-linux-gnu: [RISCV]" + variables: + CONF_HOST: "aarch64-linux-gnu" + TARGET: "RISCV" + +pack_aarch64-linux-gnu_xtensa: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [Xtensa]" + - job: "build_aarch64-linux-gnu: [Xtensa]" + variables: + CONF_HOST: "aarch64-linux-gnu" + TARGET: "Xtensa" + +pack_x86_64-apple-darwin_riscv: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [RISCV]" + - job: "build_x86_64-apple-darwin: [RISCV]" + variables: + CONF_HOST: "x86_64-apple-darwin21.1" + TARGET: "RISCV" + +pack_x86_64-apple-darwin_xtensa: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [Xtensa]" + - job: "build_x86_64-apple-darwin: [Xtensa]" + variables: + CONF_HOST: "x86_64-apple-darwin21.1" + TARGET: "Xtensa" + +pack_aarch64-apple-darwin_riscv: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [RISCV]" + - job: "build_aarch64-apple-darwin: [RISCV]" + variables: + CONF_HOST: "aarch64-apple-darwin21.1" + TARGET: "RISCV" + +pack_aarch64-apple-darwin_xtensa: + extends: .pack_template + needs: + # needs target libs archive from native build job + - job: "build_x86_64-linux-gnu: [Xtensa]" + - job: "build_aarch64-apple-darwin: [Xtensa]" + variables: + CONF_HOST: "aarch64-apple-darwin21.1" + TARGET: "Xtensa" + +.macos_codesign_template: + stage: sign + when: on_success + resource_group: macos_codesign + tags: [ "darwin", "codesign" ] + artifacts: + paths: + - ${DIST_ART_DIR} + variables: + # directory with distro archives + DIST_ART_DIR: ${DIST_DIR} + # command to archive distro + ARCHIVE_TOOL: "tar cJf" + # command to unarchive distro + UNARCHIVE_TOOL: "tar xJf" + # URL to macos codesign repo + NOTARIZATION_SCRIPTS_GIT: "${CI_SERVER_PROTOCOL}://gitlab-ci-token:${CI_JOB_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/espressif/macos_codesign_notarization.git" script: - - *fix_origin_remote_for_public_snippet + - git clone -q --depth=1 ${NOTARIZATION_SCRIPTS_GIT} -b ${CI_COMMIT_REF_NAME} || + git clone -q --depth=1 ${NOTARIZATION_SCRIPTS_GIT} + - ./macos_codesign_notarization/run.sh + +sign_x86_64-apple-darwin_riscv: + extends: .macos_codesign_template + needs: + - pack_x86_64-apple-darwin_riscv -.get_clang_toolchain_build_scripts_snippet: &get_clang_toolchain_build_scripts_snippet | - git clone -b ${XTENSA_CLANG_TOOLCHAIN_REF} ${GITLAB_SSH_SERVER}/${XTENSA_CLANG_TOOLCHAIN_REPO} - cp -r xtensa-clang-toolchain/* . +sign_x86_64-apple-darwin_xtensa: + extends: .macos_codesign_template + needs: + - pack_x86_64-apple-darwin_xtensa -.get_clang_toolchain_build_scripts: +sign_aarch64-apple-darwin_riscv: + extends: .macos_codesign_template + needs: + - pack_aarch64-apple-darwin_riscv + +sign_aarch64-apple-darwin_xtensa: + extends: .macos_codesign_template + needs: + - pack_aarch64-apple-darwin_xtensa + +upload_to_http: + stage: private_deploy + when: manual + allow_failure: true + tags: [ "deploy", "shiny" ] + variables: + # force the fetch strategy to clean old archives up in dist/ dir + GIT_STRATEGY: fetch + needs: + - job: pack_x86_64-linux-gnu_riscv + - job: pack_x86_64-linux-gnu_xtensa script: - - *get_clang_toolchain_build_scripts_snippet + - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" + # List of archives + - FILES=$(find ${DIST_DIR} -name dist_name_\* -exec cat {} \+) + - cd ${DIST_DIR} + - ls -l $FILES + - scp ${FILES} ${HTTP_UPLOAD_DIR}/ct-ng/llvm-builds + # Show info + - echo -e "\nArchives were published there:\n\n$(for n in ${FILES}; do echo "${HTTP_PUBLIC_DIR}/ct-ng/llvm-builds/${n}"; done)\n" -before_script: - - !reference [.use_ci_tools, script] - - !reference [.add_gitlab_key, script] +upload_to_github: + stage: public_deploy + when: manual + allow_failure: true + only: + - tags + tags: [ "amd64", "internet" ] + image: espressif/github-hub:2 + variables: + GIT_STRATEGY: fetch + GITHUB_TOKEN: "${GH_TOKEN}" + GITHUB_REPO: "${GH_REPO_HTTPS}" + TAG: "${CI_COMMIT_TAG}" + needs: + - job: pack_x86_64-linux-gnu_riscv + - job: pack_x86_64-linux-gnu_xtensa + - job: pack_arm-linux-gnueabihf_riscv + - job: pack_arm-linux-gnueabihf_xtensa + - job: pack_aarch64-linux-gnu_riscv + - job: pack_aarch64-linux-gnu_xtensa + - job: pack_x86_64-w64-mingw32_riscv + - job: pack_x86_64-w64-mingw32_xtensa + - job: sign_x86_64-apple-darwin_riscv + - job: sign_x86_64-apple-darwin_xtensa + - job: sign_aarch64-apple-darwin_riscv + - job: sign_aarch64-apple-darwin_xtensa + before_script: [] + script: + - ls -l dist*/ + - git remote add github ${GH_REPO_HTTPS} + - hub release show ${TAG} || { echo "Please create a release on GitHub with ${TAG} tag at first"; exit 1; } + # List of archives + - FILES=$(find ${DIST_DIR} -name dist_name_\* -exec cat {} \+) + - cd ${DIST_DIR} + - ls -l $FILES + # Upload archives + - for n in ${FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done -include: - - local: .universal-toolchain-release.yml +update_idf_tools: + stage: update_idf_tools + when: manual + allow_failure: true + only: + - tags + variables: + TOOL_NAME: openocd + TOOL_MEMBERS: openocd-esp32 + TOOL_VERSION: ${CI_COMMIT_TAG} + TOOL_SHA256_URL: https://github.com/espressif/openocd-esp32/releases/download/${CI_COMMIT_TAG}/openocd-esp32-${CI_COMMIT_TAG}-checksum.sha256 + RN_SECTION: Toolchain + trigger: + project: idf/idf-tools-updater + strategy: depend From b0d3e02c9d61601c3ae21a236af8591139727518 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Thu, 7 Mar 2024 11:00:06 +0300 Subject: [PATCH 238/261] [Xtensa] Fix disassembler. Fix disassembling of the Imm8_sh8, Imm64n_4n, Offset8m32, Entry_Imm12 immedaite operands. --- .../Xtensa/Disassembler/XtensaDisassembler.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 64ce0e4ab9b4bb..81c02b5de46524 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -562,8 +562,8 @@ static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm, static DecodeStatus decodeImm8_sh8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { - assert(isUInt<8>(Imm) && "Invalid immediate"); - Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 8))); + assert(isUInt<16>(Imm) && ((Imm & 0xff) == 0) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm))); return MCDisassembler::Success; } @@ -630,24 +630,24 @@ static DecodeStatus decodeImm8n_7Operand(MCInst &Inst, uint64_t Imm, static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { - assert(isUInt<4>(Imm) && "Invalid immediate"); - Inst.addOperand(MCOperand::createImm((~0x3f) | (Imm << 2))); + assert(isUInt<6>(Imm) && ((Imm & 0x3) == 0) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm((~0x3f) | (Imm))); return MCDisassembler::Success; } static DecodeStatus decodeOffset8m32Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { - assert(isUInt<8>(Imm) && "Invalid immediate"); - Inst.addOperand(MCOperand::createImm(Imm << 2)); + assert(isUInt<10>(Imm) && ((Imm & 0x3) == 0) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { - assert(isUInt<12>(Imm) && "Invalid immediate"); - Inst.addOperand(MCOperand::createImm(Imm << 3)); + assert(isUInt<15>(Imm) && ((Imm & 0x7) == 0) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } From 6b5bca8fbc8b6363de3f92c29312822392688505 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 15 Mar 2024 12:32:03 +0300 Subject: [PATCH 239/261] [Xtensa] Add predefined macros for core configuration --- clang/lib/Basic/Targets.cpp | 2 + clang/lib/Basic/Targets/Xtensa.cpp | 103 ++++++++++++++++++++++++++++- clang/lib/Basic/Targets/Xtensa.h | 83 ++++++++++++++++++++++- 3 files changed, 186 insertions(+), 2 deletions(-) diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index 0ff8025df08d0d..bd51b3b1810209 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -752,6 +752,8 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, } case llvm::Triple::xtensa : + if (Triple.getVendor() == llvm::Triple::Espressif) + return std::make_unique(Triple, Opts); return std::make_unique(Triple, Opts); } } diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp index 7b5346062bccb0..c99c25433df427 100644 --- a/clang/lib/Basic/Targets/Xtensa.cpp +++ b/clang/lib/Basic/Targets/Xtensa.cpp @@ -38,13 +38,36 @@ void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__ELF__"); Builder.defineMacro("__xtensa__"); Builder.defineMacro("__XTENSA__"); - Builder.defineMacro("__XTENSA_EL__"); + if (BigEndian) + Builder.defineMacro("__XTENSA_EB__"); + else + Builder.defineMacro("__XTENSA_EL__"); if (HasWindowed) Builder.defineMacro("__XTENSA_WINDOWED_ABI__"); else Builder.defineMacro("__XTENSA_CALL0_ABI__"); if (!HasFP) Builder.defineMacro("__XTENSA_SOFT_FLOAT__"); + Builder.defineMacro("__XCHAL_HAVE_BE", BigEndian ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DENSITY", HasDensity ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MAC16", HasMAC16 ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MUL32", HasMul32 ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MUL32_HIGH", HasMul32High ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DIV32", HasDiv32 ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_NSA", HasNSA ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MINMAX", HasMINMAX ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_SEXT", HasSEXT ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_LOOPS", HasLoop ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_THREADPTR", HasTHREADPTR ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_S32C1I", HasS32C1I ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_BOOLEANS", HasBoolean ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DFP_ACCEL", HasDFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_WINDOWED", HasWindowed ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DEBUG", HasDebug ? "1" : "0"); + // XSHAL_ABI + // XTHAL_ABI_WINDOWED + // XTHAL_ABI_CALL0 } void XtensaTargetInfo::fillValidCPUList( @@ -79,6 +102,32 @@ bool XtensaTargetInfo::hasFeature(StringRef Feature) const { .Case("windowed", HasWindowed) .Case("bool", HasBoolean) .Case("hifi3", HasHIFI3) + .Case("+density", HasDensity) + .Case("+loop", HasLoop) + .Case("+sext", HasSEXT) + .Case("+nsa", HasNSA) + .Case("+clamps", HasCLAPMS) + .Case("+minmax", HasMINMAX) + .Case("+mul32", HasMul32) + .Case("+mul32high", HasMul32High) + .Case("+div32", HasDiv32) + .Case("+mac16", HasMAC16) + .Case("+dfpaccel", HasDFP) + .Case("+s32c1i", HasS32C1I) + .Case("+threadptr", HasTHREADPTR) + .Case("+extendedl32r", HasExtendedL32R) + .Case("+atomctl", HasATOMCTL) + .Case("+memctl", HasMEMCTL) + .Case("+debug", HasDebug) + .Case("+exception", HasException) + .Case("+highpriinterrupts", HasHighPriInterrupts) + .Case("+coprocessor", HasCoprocessor) + .Case("+interrupt", HasInterrupt) + .Case("+rvector", HasRelocatableVector) + .Case("+timerint", HasTimerInt) + .Case("+prid", HasPRID) + .Case("+regprotect", HasRegionProtection) + .Case("+miscsr", HasMiscSR) .Default(false); } @@ -94,6 +143,58 @@ bool XtensaTargetInfo::handleTargetFeatures(std::vector &Features, HasWindowed = true; else if (Feature == "+hifi3") HasHIFI3 = true; + else if (Feature == "+density") + HasDensity = true; + else if (Feature == "+loop") + HasLoop = true; + else if (Feature == "+sext") + HasSEXT = true; + else if (Feature == "+nsa") + HasNSA = true; + else if (Feature == "+clamps") + HasCLAPMS = true; + else if (Feature == "+minmax") + HasMINMAX = true; + else if (Feature == "+mul32") + HasMul32 = true; + else if (Feature == "+mul32high") + HasMul32High = true; + else if (Feature == "+div32") + HasDiv32 = true; + else if (Feature == "+mac16") + HasMAC16 = true; + else if (Feature == "+dfpaccel") + HasDFP = true; + else if (Feature == "+s32c1i") + HasS32C1I = true; + else if (Feature == "+threadptr") + HasTHREADPTR = true; + else if (Feature == "+extendedl32r") + HasExtendedL32R = true; + else if (Feature == "+atomctl") + HasATOMCTL = true; + else if (Feature == "+memctl") + HasMEMCTL = true; + else if (Feature == "+debug") + HasDebug = true; + else if (Feature == "+exception") + HasException = true; + else if (Feature == "+highpriinterrupts") + HasHighPriInterrupts = true; + else if (Feature == "+coprocessor") + HasCoprocessor = true; + else if (Feature == "+interrupt") + HasInterrupt = true; + else if (Feature == "+rvector") + HasRelocatableVector = true; + else if (Feature == "+timerint") + HasTimerInt = true; + else if (Feature == "+prid") + HasPRID = true; + else if (Feature == "+regprotect") + HasRegionProtection = true; + else if (Feature == "+miscsr") + HasMiscSR = true; } return true; diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index b2c923b2cd24a0..ca62b8159b60a5 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -30,11 +30,38 @@ namespace clang { namespace targets { class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { +protected: std::string CPU; bool HasFP = false; bool HasWindowed = false; bool HasBoolean = false; bool HasHIFI3 = false; + bool HasDensity = false; + bool HasLoop = false; + bool HasSEXT = false; + bool HasNSA = false; + bool HasCLAPMS = false; + bool HasMINMAX = false; + bool HasMul32 = false; + bool HasMul32High = false; + bool HasDiv32 = false; + bool HasMAC16 = false; + bool HasDFP = false; + bool HasS32C1I = false; + bool HasTHREADPTR = false; + bool HasExtendedL32R = false; + bool HasATOMCTL = false; + bool HasMEMCTL = false; + bool HasDebug = false; + bool HasException = false; + bool HasHighPriInterrupts = false; + bool HasCoprocessor = false; + bool HasInterrupt = false; + bool HasRelocatableVector = false; + bool HasTimerInt = false; + bool HasPRID = false; + bool HasRegionProtection = false; + bool HasMiscSR = false; public: XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &) @@ -54,7 +81,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { resetDataLayout("e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32"); } - void getTargetDefines(const LangOptions &Opts, + virtual void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override; ArrayRef getTargetBuiltins() const override; @@ -118,6 +145,60 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { bool handleTargetFeatures(std::vector &Features, DiagnosticsEngine &Diags) override; }; + +class LLVM_LIBRARY_VISIBILITY EspXtensaTargetInfo : public XtensaTargetInfo { + +public: + EspXtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &opts) + : XtensaTargetInfo(Triple, opts) { + } + + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override { + XtensaTargetInfo::getTargetDefines(Opts, Builder); + Builder.defineMacro("__XCHAL_HAVE_CONST16", "0"); + Builder.defineMacro("__XCHAL_HAVE_ABS"); + Builder.defineMacro("__XCHAL_HAVE_ADDX"); + Builder.defineMacro("__XCHAL_HAVE_L32R"); + Builder.defineMacro("__XCHAL_HAVE_MUL16"); + // FIXME: should we enable FP options below for all Xtensa CPUs if __XCHAL_HAVE_FP is 1 + Builder.defineMacro("__XCHAL_HAVE_FP_DIV", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_RECIP", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_SQRT", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_RSQRT", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_POSTINC", HasFP ? "1" : "0"); + // FIXME: should we enable DFP options below for all Xtensa CPUs if __XCHAL_HAVE_DFP_ACCEL is 1 + Builder.defineMacro("__XCHAL_HAVE_DFP_DIV", HasDFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DFP_RECIP", HasDFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DFP_SQRT", HasDFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DFP_RSQRT", HasDFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_RELEASE_SYNC", "1"); + // XSHAL_USE_ABSOLUTE_LITERALS + // XSHAL_HAVE_TEXT_SECTION_LITERALS + Builder.defineMacro("__XCHAL_NUM_AREGS", "64"); + Builder.defineMacro("__XCHAL_HAVE_WIDE_BRANCHES", "0"); + Builder.defineMacro("__XCHAL_HAVE_PREDICTED_BRANCHES", "0"); + Builder.defineMacro("__XCHAL_ICACHE_SIZE", "0"); + Builder.defineMacro("__XCHAL_DCACHE_SIZE", "0"); + Builder.defineMacro("__XCHAL_ICACHE_LINESIZE", "16"); + Builder.defineMacro("__XCHAL_DCACHE_LINESIZE", "16"); + Builder.defineMacro("__XCHAL_ICACHE_LINEWIDTH", "4"); + Builder.defineMacro("__XCHAL_DCACHE_LINEWIDTH", "4"); + Builder.defineMacro("__XCHAL_DCACHE_IS_WRITEBACK", "0"); + Builder.defineMacro("__XCHAL_HAVE_MMU", "0"); + Builder.defineMacro("__XCHAL_NUM_IBREAK", "2"); + Builder.defineMacro("__XCHAL_NUM_DBREAK", "2"); + Builder.defineMacro("__XCHAL_DEBUGLEVEL", "6"); + if (CPU == "esp32") + Builder.defineMacro("__XCHAL_MAX_INSTRUCTION_SIZE", "3"); + else if (CPU == "esp32s2") + Builder.defineMacro("__XCHAL_MAX_INSTRUCTION_SIZE", "3"); + else if (CPU == "esp32s3") + Builder.defineMacro("__XCHAL_MAX_INSTRUCTION_SIZE", "4"); + Builder.defineMacro("__XCHAL_INST_FETCH_WIDTH", "4"); + } +}; + } // namespace targets } // namespace clang #endif // LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H From ac4aa13f6f738f5776d0180283041e61ede7012f Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 15 Mar 2024 21:27:34 +0300 Subject: [PATCH 240/261] [Clang] Add stdint preprocessor tests for Xtensa --- clang/test/Preprocessor/init.c | 2 + clang/test/Preprocessor/stdint.c | 108 +++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index a2c175a5eae875..3acb6c856c0ba1 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -2661,6 +2661,8 @@ // RISCV64-LINUX: #define linux 1 // RISCV64-LINUX: #define unix 1 +// RUN: %clang_cc1 -E -dM -ffreestanding -triple=xtensa < /dev/null \ +// RUN: | FileCheck -match-full-lines -check-prefix=XTENSA %s // RUN: %clang_cc1 -E -dM -ffreestanding -triple=xtensa-esp-unknown-elf < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix=XTENSA %s // XTENSA: #define _ILP32 1 diff --git a/clang/test/Preprocessor/stdint.c b/clang/test/Preprocessor/stdint.c index 7cb33ed54739a2..e90d6b8c9ea3a9 100644 --- a/clang/test/Preprocessor/stdint.c +++ b/clang/test/Preprocessor/stdint.c @@ -1498,6 +1498,114 @@ // XCORE:INTMAX_C_(0) 0LL // XCORE:UINTMAX_C_(0) 0ULL // +// RUN: %clang_cc1 -E -ffreestanding -triple=xtensa %s | FileCheck -check-prefix XTENSA %s +// RUN: %clang_cc1 -E -ffreestanding -triple=xtensa-esp-unknown-elf %s | FileCheck -check-prefix XTENSA %s +// +// XTENSA:typedef long long int int64_t; +// XTENSA:typedef long long unsigned int uint64_t; +// XTENSA:typedef int64_t int_least64_t; +// XTENSA:typedef uint64_t uint_least64_t; +// XTENSA:typedef int64_t int_fast64_t; +// XTENSA:typedef uint64_t uint_fast64_t; +// +// XTENSA:typedef int int32_t; +// XTENSA:typedef unsigned int uint32_t; +// XTENSA:typedef int32_t int_least32_t; +// XTENSA:typedef uint32_t uint_least32_t; +// XTENSA:typedef int32_t int_fast32_t; +// XTENSA:typedef uint32_t uint_fast32_t; +// +// XTENSA:typedef short int16_t; +// XTENSA:typedef unsigned short uint16_t; +// XTENSA:typedef int16_t int_least16_t; +// XTENSA:typedef uint16_t uint_least16_t; +// XTENSA:typedef int16_t int_fast16_t; +// XTENSA:typedef uint16_t uint_fast16_t; +// +// XTENSA:typedef signed char int8_t; +// XTENSA:typedef unsigned char uint8_t; +// XTENSA:typedef int8_t int_least8_t; +// XTENSA:typedef uint8_t uint_least8_t; +// XTENSA:typedef int8_t int_fast8_t; +// XTENSA:typedef uint8_t uint_fast8_t; +// +// XTENSA:typedef int intptr_t; +// XTENSA:typedef unsigned int uintptr_t; +// +// XTENSA:typedef long long int intmax_t; +// XTENSA:typedef long long unsigned int uintmax_t; +// +// XTENSA:INT8_MAX_ 127 +// XTENSA:INT8_MIN_ (-127 -1) +// XTENSA:UINT8_MAX_ 255 +// XTENSA:INT_LEAST8_MIN_ (-127 -1) +// XTENSA:INT_LEAST8_MAX_ 127 +// XTENSA:UINT_LEAST8_MAX_ 255 +// XTENSA:INT_FAST8_MIN_ (-127 -1) +// XTENSA:INT_FAST8_MAX_ 127 +// XTENSA:UINT_FAST8_MAX_ 255 +// +// XTENSA:INT16_MAX_ 32767 +// XTENSA:INT16_MIN_ (-32767 -1) +// XTENSA:UINT16_MAX_ 65535 +// XTENSA:INT_LEAST16_MIN_ (-32767 -1) +// XTENSA:INT_LEAST16_MAX_ 32767 +// XTENSA:UINT_LEAST16_MAX_ 65535 +// XTENSA:INT_FAST16_MIN_ (-32767 -1) +// XTENSA:INT_FAST16_MAX_ 32767 +// XTENSA:UINT_FAST16_MAX_ 65535 +// +// XTENSA:INT32_MAX_ 2147483647 +// XTENSA:INT32_MIN_ (-2147483647 -1) +// XTENSA:UINT32_MAX_ 4294967295U +// XTENSA:INT_LEAST32_MIN_ (-2147483647 -1) +// XTENSA:INT_LEAST32_MAX_ 2147483647 +// XTENSA:UINT_LEAST32_MAX_ 4294967295U +// XTENSA:INT_FAST32_MIN_ (-2147483647 -1) +// XTENSA:INT_FAST32_MAX_ 2147483647 +// XTENSA:UINT_FAST32_MAX_ 4294967295U +// +// XTENSA:INT64_MAX_ 9223372036854775807LL +// XTENSA:INT64_MIN_ (-9223372036854775807LL -1) +// XTENSA:UINT64_MAX_ 18446744073709551615ULL +// XTENSA:INT_LEAST64_MIN_ (-9223372036854775807LL -1) +// XTENSA:INT_LEAST64_MAX_ 9223372036854775807LL +// XTENSA:UINT_LEAST64_MAX_ 18446744073709551615ULL +// XTENSA:INT_FAST64_MIN_ (-9223372036854775807LL -1) +// XTENSA:INT_FAST64_MAX_ 9223372036854775807LL +// XTENSA:UINT_FAST64_MAX_ 18446744073709551615ULL +// +// XTENSA:INTPTR_MIN_ (-2147483647 -1) +// XTENSA:INTPTR_MAX_ 2147483647 +// XTENSA:UINTPTR_MAX_ 4294967295U +// XTENSA:PTRDIFF_MIN_ (-2147483647 -1) +// XTENSA:PTRDIFF_MAX_ 2147483647 +// XTENSA:SIZE_MAX_ 4294967295U +// +// XTENSA:INTMAX_MIN_ (-9223372036854775807LL -1) +// XTENSA:INTMAX_MAX_ 9223372036854775807LL +// XTENSA:UINTMAX_MAX_ 18446744073709551615ULL +// +// XTENSA:SIG_ATOMIC_MIN_ (-2147483647 -1) +// XTENSA:SIG_ATOMIC_MAX_ 2147483647 +// XTENSA:WINT_MIN_ 0U +// XTENSA:WINT_MAX_ 4294967295U +// +// XTENSA:WCHAR_MAX_ 2147483647 +// XTENSA:WCHAR_MIN_ (-2147483647 -1) +// +// XTENSA:INT8_C_(0) 0 +// XTENSA:UINT8_C_(0) 0U +// XTENSA:INT16_C_(0) 0 +// XTENSA:UINT16_C_(0) 0U +// XTENSA:INT32_C_(0) 0 +// XTENSA:UINT32_C_(0) 0U +// XTENSA:INT64_C_(0) 0LL +// XTENSA:UINT64_C_(0) 0ULL +// +// XTENSA:INTMAX_C_(0) 0LL +// XTENSA:UINTMAX_C_(0) 0ULL +// // // stdint.h forms several macro definitions by pasting together identifiers // to form names (eg. int32_t is formed from int ## 32 ## _t). The following From 9a7c2458d9c52fc1b86a806395409e89d571e387 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 15 Mar 2024 23:17:38 +0300 Subject: [PATCH 241/261] [LLVM][Xtensa] Remove DFP accelrator feature from ESP32-S3 --- clang/test/Driver/xtensa-cpus.c | 2 +- llvm/include/llvm/TargetParser/XtensaTargetParser.def | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/xtensa-cpus.c b/clang/test/Driver/xtensa-cpus.c index 44e380adbf7cac..dd798e314048fc 100644 --- a/clang/test/Driver/xtensa-cpus.c +++ b/clang/test/Driver/xtensa-cpus.c @@ -32,7 +32,7 @@ // MCPU-ESP32S3: "-target-feature" "+density" "-target-feature" "+fp" "-target-feature" "+windowed" "-target-feature" "+bool" // MCPU-ESP32S3: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+clamps" // MCPU-ESP32S3: "-target-feature" "+minmax" "-target-feature" "+mul32" "-target-feature" "+mul32high" "-target-feature" "+div32" -// MCPU-ESP32S3: "-target-feature" "+mac16" "-target-feature" "+dfpaccel" "-target-feature" "+s32c1i" +// MCPU-ESP32S3: "-target-feature" "+mac16" "-target-feature" "+s32c1i" // MCPU-ESP32S3: "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl" // MCPU-ESP32S3: "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts" // MCPU-ESP32S3: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint" diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.def b/llvm/include/llvm/TargetParser/XtensaTargetParser.def index edc178ac559f5d..82d5c45b8e8796 100644 --- a/llvm/include/llvm/TargetParser/XtensaTargetParser.def +++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.def @@ -69,7 +69,7 @@ XTENSA_CPU(ESP32S2, {"esp32s2"}, FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S2OPS)) XTENSA_CPU(ESP32S3, {"esp32s3"}, (FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN | - FK_SEXT | FK_NSA | FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | + FK_SEXT | FK_NSA | FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH | FK_S32C1I | FK_THREADPTR | FK_DIV32 | FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S3OPS)) From 09109f3751d7027b655eb397689469694b73e2f3 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 15 Mar 2024 23:20:58 +0300 Subject: [PATCH 242/261] [Clang][Xtensa] Add tests for core config pre-defined macros --- clang/test/Preprocessor/init.c | 10 +-- .../Preprocessor/xtensa-target-features.c | 89 +++++++++++++++++++ 2 files changed, 91 insertions(+), 8 deletions(-) create mode 100644 clang/test/Preprocessor/xtensa-target-features.c diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index 3acb6c856c0ba1..5a4bf3a107f20f 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -2960,11 +2960,9 @@ // XTENSA: #define __WINT_TYPE__ unsigned int // XTENSA: #define __WINT_UNSIGNED__ 1 // XTENSA: #define __WINT_WIDTH__ 32 -// XTENSA: #define __XTENSA_EL__ 1 -// XTENSA: #define __XTENSA_WINDOWED_ABI__ 1 -// XTENSA: #define __XTENSA__ 1 -// XTENSA: #define __xtensa__ 1 +// RUN: %clang_cc1 -E -dM -ffreestanding -triple=xtensa -mfast-int-min32 < /dev/null \ +// RUN: | FileCheck -match-full-lines -check-prefix=XTENSA_FAST32 %s // RUN: %clang_cc1 -E -dM -ffreestanding -triple=xtensa-esp-unknown-elf -mfast-int-min32 < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix=XTENSA_FAST32 %s // XTENSA_FAST32: #define _ILP32 1 @@ -3262,7 +3260,3 @@ // XTENSA_FAST32: #define __WINT_TYPE__ unsigned int // XTENSA_FAST32: #define __WINT_UNSIGNED__ 1 // XTENSA_FAST32: #define __WINT_WIDTH__ 32 -// XTENSA_FAST32: #define __XTENSA_EL__ 1 -// XTENSA_FAST32: #define __XTENSA_WINDOWED_ABI__ 1 -// XTENSA_FAST32: #define __XTENSA__ 1 -// XTENSA_FAST32: #define __xtensa__ 1 diff --git a/clang/test/Preprocessor/xtensa-target-features.c b/clang/test/Preprocessor/xtensa-target-features.c new file mode 100644 index 00000000000000..96a4743b3ae55b --- /dev/null +++ b/clang/test/Preprocessor/xtensa-target-features.c @@ -0,0 +1,89 @@ +// RUN: %clang -target xtensa -Wno-missing-multilib -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-XTENSA %s +// RUN: %clang -target xtensa-esp-unknown-elf -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-XTENSA %s +// CHECK-XTENSA: #define __XTENSA__ 1 +// CHECK-XTENSA: #define __xtensa__ 1 + +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP %s +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s2 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP %s +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP %s +// CHECK-ESP: #define __XCHAL_DCACHE_IS_WRITEBACK 0 +// CHECK-ESP: #define __XCHAL_DCACHE_LINESIZE 16 +// CHECK-ESP: #define __XCHAL_DCACHE_LINEWIDTH 4 +// CHECK-ESP: #define __XCHAL_DCACHE_SIZE 0 +// CHECK-ESP: #define __XCHAL_DEBUGLEVEL 6 +// CHECK-ESP: #define __XCHAL_HAVE_ABS 1 +// CHECK-ESP: #define __XCHAL_HAVE_ADDX 1 +// CHECK-ESP: #define __XCHAL_HAVE_BE 0 +// CHECK-ESP: #define __XCHAL_HAVE_CONST16 0 +// CHECK-ESP: #define __XCHAL_HAVE_DEBUG 1 +// CHECK-ESP: #define __XCHAL_HAVE_DENSITY 1 +// CHECK-ESP: #define __XCHAL_HAVE_DIV32 1 +// CHECK-ESP: #define __XCHAL_HAVE_L32R 1 +// CHECK-ESP: #define __XCHAL_HAVE_MINMAX 1 +// CHECK-ESP: #define __XCHAL_HAVE_MMU 0 +// CHECK-ESP: #define __XCHAL_HAVE_MUL16 1 +// CHECK-ESP: #define __XCHAL_HAVE_MUL32 1 +// CHECK-ESP: #define __XCHAL_HAVE_MUL32_HIGH 1 +// CHECK-ESP: #define __XCHAL_HAVE_NSA 1 +// CHECK-ESP: #define __XCHAL_HAVE_PREDICTED_BRANCHES 0 +// CHECK-ESP: #define __XCHAL_HAVE_RELEASE_SYNC 1 +// CHECK-ESP: #define __XCHAL_HAVE_SEXT 1 +// CHECK-ESP: #define __XCHAL_HAVE_THREADPTR 1 +// CHECK-ESP: #define __XCHAL_HAVE_WIDE_BRANCHES 0 +// CHECK-ESP: #define __XCHAL_HAVE_WINDOWED 1 +// CHECK-ESP: #define __XCHAL_ICACHE_LINESIZE 16 +// CHECK-ESP: #define __XCHAL_ICACHE_LINEWIDTH 4 +// CHECK-ESP: #define __XCHAL_ICACHE_SIZE 0 +// CHECK-ESP: #define __XCHAL_INST_FETCH_WIDTH 4 +// CHECK-ESP: #define __XCHAL_NUM_AREGS 64 +// CHECK-ESP: #define __XCHAL_NUM_DBREAK 2 +// CHECK-ESP: #define __XCHAL_NUM_IBREAK 2 +// CHECK-ESP: #define __XTENSA_EL__ 1 +// CHECK-ESP: #define __XTENSA_WINDOWED_ABI__ 1 + +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32_S3 %s +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32_S3 %s +// CHECK-ESP32_S3: #define __XCHAL_HAVE_BOOLEANS 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_DIV 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_POSTINC 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_RECIP 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_RSQRT 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_SQRT 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_LOOPS 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_MAC16 1 +// CHECK-ESP32_S3: #define __XCHAL_HAVE_S32C1I 1 + +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32 %s +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_ACCEL 1 +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_DIV 1 +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_RECIP 1 +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_RSQRT 1 +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_SQRT 1 +// CHECK-ESP32: #define __XCHAL_MAX_INSTRUCTION_SIZE 3 + +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32S3 %s +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_ACCEL 0 +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_DIV 0 +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_RECIP 0 +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_RSQRT 0 +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_SQRT 0 +// CHECK-ESP32S3: #define __XCHAL_MAX_INSTRUCTION_SIZE 4 + +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s2 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32S2 %s +// CHECK-ESP32S2: #define __XCHAL_HAVE_BOOLEANS 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_ACCEL 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_DIV 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_RECIP 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_RSQRT 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_SQRT 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_DIV 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_POSTINC 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_RECIP 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_RSQRT 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_SQRT 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_LOOPS 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_MAC16 0 +// CHECK-ESP32S2: #define __XCHAL_HAVE_S32C1I 0 +// CHECK-ESP32S2: #define __XCHAL_MAX_INSTRUCTION_SIZE 3 From 368640f64d1fe8192a83d6ca68ef142843d72f5c Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Thu, 21 Mar 2024 12:54:39 +0300 Subject: [PATCH 243/261] esp/ci: Upgrade GCC toolchain components version to '13.2.0_20240305' --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 09891b869dfe0b..bff2ef4f7add4c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -80,7 +80,7 @@ before_script: -DBINUTILS_REPO_URL="${GITLAB_SSH_SERVER}/${BINUTILS_REPO_PATH}.git" -DXTENSA_OVERLAYS_REPO_URL="${GITLAB_SSH_SERVER}/${XTENSA_OVERLAYS_REPO_PATH}.git" -DFETCHCONTENT_QUIET=OFF - -DESP_GNU_TOOLCHAIN_VER="13.2.0_20230928" + -DESP_GNU_TOOLCHAIN_VER="13.2.0_20240305" -DLLVM_TOOLCHAIN_CROSS_BUILD_MINGW=${CROSS_BUILD_MINGW} -DUSE_LIBC=${USE_LIBC} -DUSE_LIBCXX=${USE_LIBCXX} From 6fe6ab498c6c37f198b21d2264b80f76ba0c9131 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Fri, 29 Mar 2024 01:40:29 +0300 Subject: [PATCH 244/261] [Clang][RISCV] Fix baremetal test --- clang/test/Driver/baremetal-esp.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/baremetal-esp.cpp b/clang/test/Driver/baremetal-esp.cpp index 18c1888daad48c..bdc8388106f03d 100644 --- a/clang/test/Driver/baremetal-esp.cpp +++ b/clang/test/Driver/baremetal-esp.cpp @@ -289,8 +289,10 @@ // RUN: touch %T/baremetal_clang_rt_noarch/lib/libclang_rt.builtins.a // RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 \ // RUN: --target=riscv32-esp-elf \ -// RUN: --sysroot=%T/baremetal_clang_rt_noarch \clang-runtimes/riscv32-esp-unknown-elf -// used if present. +// RUN: --sysroot=%T/baremetal_clang_rt_noarch \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32_CLANGRT-NOARCH %s +// CHECK-ESP-RV32_CLANGRT-NOARCH: "-lclang_rt.builtins" +// CHECK-ESP-RV32_CLANGRT-NOARCH-NOT: "-lclang_rt.builtins-riscv32" // RUN: rm -rf %T/baremetal_clang_rt_arch // RUN: mkdir -p %T/baremetal_clang_rt_arch/lib // RUN: touch %T/baremetal_clang_rt_arch/lib/libclang_rt.builtins-riscv32.a From 468e952ed91251612b40feb7403164b3e3ef9be1 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Wed, 27 Mar 2024 23:22:13 +0300 Subject: [PATCH 245/261] [Toolchain][Espressif] Use custom prefixes for 'as' and 'ld' --- clang/lib/Driver/ToolChains/EspBareMetal.h | 2 +- ...32-esp-elf-as => riscv32-esp-elf-clang-as} | 0 ...32-esp-elf-ld => riscv32-esp-elf-clang-ld} | 0 ...esp32-elf-as => xtensa-esp32-elf-clang-as} | 0 ...esp32-elf-ld => xtensa-esp32-elf-clang-ld} | 0 ...2s2-elf-as => xtensa-esp32s2-elf-clang-as} | 0 ...2s2-elf-ld => xtensa-esp32s2-elf-clang-ld} | 0 ...2s3-elf-as => xtensa-esp32s3-elf-clang-as} | 0 ...2s3-elf-ld => xtensa-esp32s3-elf-clang-ld} | 0 clang/test/Driver/baremetal-esp.cpp | 42 +++++++++---------- 10 files changed, 22 insertions(+), 22 deletions(-) rename clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/{riscv32-esp-elf-as => riscv32-esp-elf-clang-as} (100%) rename clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/{riscv32-esp-elf-ld => riscv32-esp-elf-clang-ld} (100%) rename clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/{xtensa-esp32-elf-as => xtensa-esp32-elf-clang-as} (100%) rename clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/{xtensa-esp32-elf-ld => xtensa-esp32-elf-clang-ld} (100%) rename clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/{xtensa-esp32s2-elf-as => xtensa-esp32s2-elf-clang-as} (100%) rename clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/{xtensa-esp32s2-elf-ld => xtensa-esp32s2-elf-clang-ld} (100%) rename clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/{xtensa-esp32s3-elf-as => xtensa-esp32s3-elf-clang-as} (100%) rename clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/{xtensa-esp32s3-elf-ld => xtensa-esp32s3-elf-clang-ld} (100%) diff --git a/clang/lib/Driver/ToolChains/EspBareMetal.h b/clang/lib/Driver/ToolChains/EspBareMetal.h index 08c544e34ea023..5618564c0a4e9d 100644 --- a/clang/lib/Driver/ToolChains/EspBareMetal.h +++ b/clang/lib/Driver/ToolChains/EspBareMetal.h @@ -75,7 +75,7 @@ class LLVM_LIBRARY_VISIBILITY Linker : public Tool { class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { public: Assembler(const ToolChain &TC) - : Tool("baremetal::esp::Assembler", "as", TC) {} + : Tool("baremetal::esp::Assembler", "clang-as", TC) {} bool hasIntegratedCPP() const override { return false; } void ConstructJob(Compilation &C, const JobAction &JA, diff --git a/clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-as b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-clang-as similarity index 100% rename from clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-as rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-clang-as diff --git a/clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-clang-ld similarity index 100% rename from clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld rename to clang/test/Driver/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-clang-ld diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-clang-as similarity index 100% rename from clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-clang-as diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-clang-ld similarity index 100% rename from clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-clang-ld diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-clang-as similarity index 100% rename from clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-clang-as diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-clang-ld similarity index 100% rename from clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-clang-ld diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-clang-as similarity index 100% rename from clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-clang-as diff --git a/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld b/clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-clang-ld similarity index 100% rename from clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld rename to clang/test/Driver/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-clang-ld diff --git a/clang/test/Driver/baremetal-esp.cpp b/clang/test/Driver/baremetal-esp.cpp index bdc8388106f03d..140df519ca951e 100644 --- a/clang/test/Driver/baremetal-esp.cpp +++ b/clang/test/Driver/baremetal-esp.cpp @@ -8,8 +8,8 @@ // RUN: mkdir -p %t/basic_riscv32_esp_tree/bin // RUN: ln -s %clang %t/basic_riscv32_esp_tree/bin/clang // RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/bin/ld.lld %t/basic_riscv32_esp_tree/bin/ld.lld -// RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-as %t/basic_riscv32_esp_tree/bin/riscv32-esp-elf-as -// RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld %t/basic_riscv32_esp_tree/bin/riscv32-esp-elf-ld +// RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-clang-as %t/basic_riscv32_esp_tree/bin/riscv32-esp-elf-clang-as +// RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/bin/riscv32-esp-elf-clang-ld %t/basic_riscv32_esp_tree/bin/riscv32-esp-elf-clang-ld // RUN: ln -s %S/Inputs/basic_riscv32_esp_tree/lib %t/basic_riscv32_esp_tree/lib // RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ @@ -56,7 +56,7 @@ // CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" // CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}riscv32-esp-unknown-elf{{[/\\]+}}rv32imac-zicsr-zifencei_ilp32{{[/\\]+}}include" // CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-x" "c++" "{{.*}}baremetal-esp.cpp" -// CHECK-ESP-RV32IMAC-FORCEAS-NEXT: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imac" "-mabi=ilp32" +// CHECK-ESP-RV32IMAC-FORCEAS-NEXT: riscv32-esp-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imac" "-mabi=ilp32" // CHECK-ESP-RV32IMAC-FORCEAS-NEXT: ld.lld{{(.exe)?}}" // CHECK-ESP-RV32IMAC-FORCEAS-SAME: "--sysroot=[[SYSROOT]]" // CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-m" "elf32lriscv" @@ -67,12 +67,12 @@ // CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" // CHECK-ESP-RV32IMAC-FORCEAS-SAME: "-lclang_rt.builtins" -// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf --ld-path=riscv32-esp-elf-ld \ +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf --ld-path=riscv32-esp-elf-clang-ld \ // RUN: -L some/directory/user/asked/for \ // RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ // RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-FORCELD %s // CHECK-ESP-RV32IMAC-FORCELD: "-isysroot" "[[SYSROOT:[^"]*]]" -// CHECK-ESP-RV32IMAC-FORCELD: riscv32-esp-elf-ld{{(.exe)?}}" +// CHECK-ESP-RV32IMAC-FORCELD: riscv32-esp-elf-clang-ld{{(.exe)?}}" // CHECK-ESP-RV32IMAC-FORCELD-SAME: "--sysroot=[[SYSROOT]]" // CHECK-ESP-RV32IMAC-FORCELD-SAME: "-m" "elf32lriscv" // CHECK-ESP-RV32IMAC-FORCELD-SAME: "-o" "a.out" @@ -175,7 +175,7 @@ // RUN: -march=rv32i -mabi=ilp32 \ // RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ // RUN: | FileCheck --check-prefix=CHECK-ESP-RV32I-FORCEAS %s -// CHECK-ESP-RV32I-FORCEAS: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32i" "-mabi=ilp32" +// CHECK-ESP-RV32I-FORCEAS: riscv32-esp-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32i" "-mabi=ilp32" // RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf \ // RUN: -march=rv32i -mabi=ilp32 \ @@ -229,19 +229,19 @@ // RUN: -march=rv32im -mabi=ilp32 \ // RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ // RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IM-FORCEAS %s -// CHECK-ESP-RV32IM-FORCEAS: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32im" "-mabi=ilp32" +// CHECK-ESP-RV32IM-FORCEAS: riscv32-esp-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32im" "-mabi=ilp32" // RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -fno-integrated-as \ // RUN: -march=rv32imc -mabi=ilp32 \ // RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ // RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMC-FORCEAS %s -// CHECK-ESP-RV32IMC-FORCEAS: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imc" "-mabi=ilp32" +// CHECK-ESP-RV32IMC-FORCEAS: riscv32-esp-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imc" "-mabi=ilp32" // RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -fno-integrated-as \ // RUN: -march=rv32imac -mabi=ilp32 \ // RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ // RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAC-FORCEAS2 %s -// CHECK-ESP-RV32IMAC-FORCEAS2: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imac" "-mabi=ilp32" +// CHECK-ESP-RV32IMAC-FORCEAS2: riscv32-esp-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imac" "-mabi=ilp32" // RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -march=rv32imafc -mabi=ilp32f \ // RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ @@ -280,7 +280,7 @@ // RUN: -march=rv32imafc -mabi=ilp32f \ // RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ // RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC-FORCEAS %s -// CHECK-ESP-RV32IMAFC-FORCEAS: riscv32-esp-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imafc" "-mabi=ilp32f" +// CHECK-ESP-RV32IMAFC-FORCEAS: riscv32-esp-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" "-march=rv32imafc" "-mabi=ilp32f" // Check that compiler-rt library without the arch filename suffix will // be used if present. @@ -310,12 +310,12 @@ // RUN: mkdir -p %t/basic_xtensa_esp_tree/bin // RUN: ln -s %clang %t/basic_xtensa_esp_tree/bin/clang // RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/ld.lld %t/basic_xtensa_esp_tree/bin/ld.lld -// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-as -// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-ld -// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-as -// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-ld -// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-as -// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-ld +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-clang-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-clang-as +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-clang-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32-elf-clang-ld +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-clang-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-clang-as +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-clang-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32s2-elf-clang-ld +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-clang-as %t/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-clang-as +// RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-clang-ld %t/basic_xtensa_esp_tree/bin/xtensa-esp32s3-elf-clang-ld // RUN: ln -s %S/Inputs/basic_xtensa_esp_tree/lib %t/basic_xtensa_esp_tree/lib // ESP32 is default @@ -362,7 +362,7 @@ // CHECK-ESP-ESP32-FORCEAS-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" // CHECK-ESP-ESP32-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32{{[/\\]+}}include" // CHECK-ESP-ESP32-FORCEAS-SAME: "-x" "c++" "{{.*}}baremetal-esp.cpp" -// CHECK-ESP-ESP32-FORCEAS-NEXT: xtensa-esp32-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" +// CHECK-ESP-ESP32-FORCEAS-NEXT: xtensa-esp32-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" // CHECK-ESP-ESP32-FORCEAS-NEXT: ld.lld{{(.exe)?}}" // CHECK-ESP-ESP32-FORCEAS-SAME: "--sysroot=[[SYSROOT]]" // CHECK-ESP-ESP32-FORCEAS-SAME: "-o" "a.out" @@ -372,12 +372,12 @@ // CHECK-ESP-ESP32-FORCEAS-SAME: "-lm" "--start-group" "-lc" "-lgloss" "-lnosys" "--end-group" // CHECK-ESP-ESP32-FORCEAS-SAME: "-lclang_rt.builtins" -// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf --ld-path=xtensa-esp32-elf-ld \ +// RUN: %t/basic_xtensa_esp_tree/bin/clang %s -### 2>&1 --target=xtensa-esp-elf --ld-path=xtensa-esp32-elf-clang-ld \ // RUN: -L some/directory/user/asked/for \ // RUN: --sysroot=%t/basic_xtensa_esp_tree/lib/clang-runtimes \ // RUN: | FileCheck --check-prefix=CHECK-ESP-ESP32-FORCELD %s // CHECK-ESP-ESP32-FORCELD: "-isysroot" "[[SYSROOT:[^"]*]]" -// CHECK-ESP-ESP32-FORCELD-NEXT: xtensa-esp32-elf-ld{{(.exe)?}}" +// CHECK-ESP-ESP32-FORCELD-NEXT: xtensa-esp32-elf-clang-ld{{(.exe)?}}" // CHECK-ESP-ESP32-FORCELD-SAME: "--sysroot=[[SYSROOT]]" // CHECK-ESP-ESP32-FORCELD-SAME: "-o" "a.out" // CHECK-ESP-ESP32-FORCELD-SAME: "-X" "{{.*}}.o" @@ -529,7 +529,7 @@ // CHECK-ESP-ESP32S2-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" // CHECK-ESP-ESP32S2-FORCEAS-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" // CHECK-ESP-ESP32S2-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2{{[/\\]+}}include" -// CHECK-ESP-ESP32S2-FORCEAS: xtensa-esp32s2-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" +// CHECK-ESP-ESP32S2-FORCEAS: xtensa-esp32s2-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" // CHECK-ESP-ESP32S2-FORCEAS-NEXT: ld.lld{{(.exe)?}}" // CHECK-ESP-ESP32S2-FORCEAS-SAME: "--sysroot=[[SYSROOT]]" // CHECK-ESP-ESP32S2-FORCEAS-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s2{{[/\\]+}}lib" @@ -575,7 +575,7 @@ // CHECK-ESP-ESP32S3-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}11.2.0" // CHECK-ESP-ESP32S3-FORCEAS-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{[/\\]+}}include" // CHECK-ESP-ESP32S3-FORCEAS-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3{{[/\\]+}}include" -// CHECK-ESP-ESP32S3-FORCEAS: xtensa-esp32s3-elf-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" +// CHECK-ESP-ESP32S3-FORCEAS: xtensa-esp32s3-elf-clang-as{{(.exe)?}}" "-o" "{{.*}}.o" "-c" "{{.*}}.s" // CHECK-ESP-ESP32S3-FORCEAS-NEXT: ld.lld{{(.exe)?}}" // CHECK-ESP-ESP32S3-FORCEAS-SAME: "--sysroot=[[SYSROOT]]" // CHECK-ESP-ESP32S3-FORCEAS-SAME: "-L[[SYSROOT]]{{[/\\]+}}xtensa-esp-unknown-elf{{[/\\]+}}esp32s3{{[/\\]+}}lib" From 57be64d0270d5a5dddf72338a6f717ac9c7b0d43 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Wed, 27 Mar 2024 20:16:23 +0300 Subject: [PATCH 246/261] esp/ci: Switch to combined all-in-one toolchain --- .gitlab-ci.yml | 307 ++++++++++++++++++++----------------------------- 1 file changed, 123 insertions(+), 184 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index bff2ef4f7add4c..cb8aa697a551db 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -12,6 +12,7 @@ image: ${CI_DOCKER_REGISTRY}/llvm-build:4 variables: ESP_LLVM_EMBEDDED_TOOLCHAIN_REF: "master" + ESP_GNU_TOOLCHAIN_VER: "13.2.0_20240305" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 CROSS_WIN_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-win:1 DIST_DIR: "dist" @@ -32,7 +33,7 @@ before_script: - *use_ci_tools - *add_gitlab_key -.build_template: +.build_toolchain_template: tags: [ "amd64", "build" ] artifacts: paths: @@ -40,17 +41,23 @@ before_script: - ${BUILD_DIR}/*.log when: always expire_in: 1 day + dependencies: [] variables: + TARGET: "Xtensa;RISCV" USE_LINKER: "ld" CROSS_BUILD_MINGW: "OFF" - SKIP_TESTS: "ON" - PACK_DISTRO: "ON" + RUN_CORE_TESTS: "OFF" + RUN_TARGET_LIB_TESTS: "OFF" + PACK_TOOLCHAIN: "ON" + PACK_STANDALONE_LIBS: "ON" + PACK_TARGET_LIBS: "OFF" after_script: # help to identify that build failed due to OOM - > if [ $CI_JOB_STATUS == 'failed' ]; then [ ! -f "${BUILD_DIR}/build.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/build.log || true [ ! -f "${BUILD_DIR}/tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/tests.log || true + [ ! -f "${BUILD_DIR}/compiler-rt-tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/compiler-rt-tests.log || true [ ! -f "${BUILD_DIR}/lld-tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/lld-tests.log || true fi script: @@ -60,18 +67,28 @@ before_script: - INST_PATH=$PWD/_install_dir - mkdir -p ${BUILD_PATH} - BUILD_HOST=$(gcc -dumpmachine) - # Build target libraries once when doing native build + # Config to build target libraries + # TODO: do not build core tools (clang, lld, binutils etc) + # when PACK_TOOLCHAIN is OFF and PACK_TARGET_LIBS is ON. + # Re-use core tools built in another job. + # LLVM-xxx - > - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then + if [ "${PACK_TARGET_LIBS}" == "ON" ]; then echo "Enable target libraries build" export USE_LIBC="newlib"; export USE_LIBCXX="libstdcxx"; export USE_RTLIB="compiler-rt;libgcc"; else - echo "Disable target libraries for cross-build" + echo "Disable target libraries" export USE_LIBC=none; export USE_LIBCXX=""; - export USE_RTLIB=""; + if [ "${RUN_CORE_TESTS}" == "ON" ]; then + # Need to have multilib dir structure to avoid test failures due to '-Wmissing-multilib'. + # So enable copying of libgcc from GNU toolchain. It is fast and not heavy. + export USE_RTLIB="libgcc"; + else + export USE_RTLIB=""; + fi fi # build toolchain core w/o any libs and GNU components - cmake $PWD/esp-llvm-embedded-toolchain -GNinja @@ -80,7 +97,7 @@ before_script: -DBINUTILS_REPO_URL="${GITLAB_SSH_SERVER}/${BINUTILS_REPO_PATH}.git" -DXTENSA_OVERLAYS_REPO_URL="${GITLAB_SSH_SERVER}/${XTENSA_OVERLAYS_REPO_PATH}.git" -DFETCHCONTENT_QUIET=OFF - -DESP_GNU_TOOLCHAIN_VER="13.2.0_20240305" + -DESP_GNU_TOOLCHAIN_VER=${ESP_GNU_TOOLCHAIN_VER} -DLLVM_TOOLCHAIN_CROSS_BUILD_MINGW=${CROSS_BUILD_MINGW} -DUSE_LIBC=${USE_LIBC} -DUSE_LIBCXX=${USE_LIBCXX} @@ -99,43 +116,52 @@ before_script: # Do not run unit tests for cross-builds. # Run as non-root user because permission tests fail when run by root. - > - if [[ "${CONF_HOST}" == "${BUILD_HOST}" && "${SKIP_TESTS}" != "ON" ]]; then - echo "Run LLVM/Clang unit tests"; + if [[ "${CONF_HOST}" == "${BUILD_HOST}" ]]; then export CUR_USER=$(whoami); useradd -m test_runner; chown -R test_runner ${BUILD_PATH}; - touch ${BUILD_PATH}/tests.log; - chmod o+w ${BUILD_PATH}/tests.log; - runuser -u test_runner -- ninja -C ${BUILD_PATH} check-all 2>&1 > ${BUILD_PATH}/tests.log; - echo "Run Compiler-RT unit tests"; - touch ${BUILD_PATH}/compiler-rt-tests.log; - chmod o+w ${BUILD_PATH}/compiler-rt-tests.log; - runuser -u test_runner -- ninja -C ${BUILD_PATH} check-compiler-rt 2>&1 > ${BUILD_PATH}/compiler-rt-tests.log; - echo "Run LLD unit tests"; - touch ${BUILD_PATH}/lld-tests.log; - chmod o+w ${BUILD_PATH}/lld-tests.log; - runuser -u test_runner -- ninja -C ${BUILD_PATH} check-lld 2>&1 > ${BUILD_PATH}/lld-tests.log; + if [[ "${RUN_CORE_TESTS}" == "ON" ]]; then + echo "Run LLVM/Clang unit tests"; + touch ${BUILD_PATH}/tests.log; + chmod o+w ${BUILD_PATH}/tests.log; + runuser -u test_runner -- ninja -C ${BUILD_PATH} check-all 2>&1 > ${BUILD_PATH}/tests.log; + echo "Run LLD unit tests"; + touch ${BUILD_PATH}/lld-tests.log; + chmod o+w ${BUILD_PATH}/lld-tests.log; + runuser -u test_runner -- ninja -C ${BUILD_PATH} check-lld 2>&1 > ${BUILD_PATH}/lld-tests.log; + fi + if [[ "${RUN_TARGET_LIB_TESTS}" == "ON" ]]; then + echo "Run Compiler-RT unit tests"; + touch ${BUILD_PATH}/compiler-rt-tests.log; + chmod o+w ${BUILD_PATH}/compiler-rt-tests.log; + runuser -u test_runner -- ninja -C ${BUILD_PATH} check-compiler-rt 2>&1 > ${BUILD_PATH}/compiler-rt-tests.log; + fi chown -R ${CUR_USER} ${BUILD_PATH}; fi - - if [ "${PACK_DISTRO}" == "OFF" ]; then exit 0; fi # pack distro - mkdir -p ${PWD}/${DIST_DIR} - - ninja -C ${BUILD_PATH} package-llvm-toolchain 2>&1 >> ${BUILD_PATH}/build.log - - DISTRO_PACK_PATH=$(ninja -C ${BUILD_PATH} print-llvm-toolchain-package-path | tail -n 1) - - echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" - - mv ${DISTRO_PACK_PATH} ${PWD}/${DIST_DIR}/ - - ARCHIVE_NAME=$(basename ${DISTRO_PACK_PATH}) - - echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/dist_name_${CONF_HOST}_${TARGET} + - > + if [[ "${PACK_TOOLCHAIN}" == "ON" ]]; then + ninja -C ${BUILD_PATH} package-llvm-toolchain 2>&1 >> ${BUILD_PATH}/build.log + DISTRO_PACK_PATH=$(ninja -C ${BUILD_PATH} print-llvm-toolchain-package-path | tail -n 1) + echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" + mv ${DISTRO_PACK_PATH} ${PWD}/${DIST_DIR}/ + ARCHIVE_NAME=$(basename ${DISTRO_PACK_PATH}) + echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/dist_name_${CONF_HOST} + fi # pack distro with standalone libs - - ninja -C ${BUILD_PATH} package-llvm-standalone-libs 2>&1 >> ${BUILD_PATH}/build.log - - DISTRO_PACK_PATH=$(ninja -C ${BUILD_PATH} print-llvm-standalone-libs-package-path | tail -n 1) - - echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" - - mv ${DISTRO_PACK_PATH} ${PWD}/${DIST_DIR}/ - - ARCHIVE_NAME=$(basename ${DISTRO_PACK_PATH}) - - echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/dist_name_libs_${CONF_HOST}_${TARGET} + - > + if [[ "${PACK_STANDALONE_LIBS}" == "ON" ]]; then + ninja -C ${BUILD_PATH} package-llvm-standalone-libs 2>&1 >> ${BUILD_PATH}/build.log + DISTRO_PACK_PATH=$(ninja -C ${BUILD_PATH} print-llvm-standalone-libs-package-path | tail -n 1) + echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" + mv ${DISTRO_PACK_PATH} ${PWD}/${DIST_DIR}/ + ARCHIVE_NAME=$(basename ${DISTRO_PACK_PATH}) + echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/dist_name_libs_${CONF_HOST} + fi # pack target libraries to be re-used in distros for other platforms - > - if [ "${CONF_HOST}" == "${BUILD_HOST}" ]; then + if [[ "${PACK_TARGET_LIBS}" == "ON" ]]; then ninja -C ${BUILD_PATH} package-llvm-toolchain-target-libs 2>&1 >> ${BUILD_PATH}/build.log DISTRO_PACK_PATH=$(ninja -C ${BUILD_PATH} print-llvm-toolchain-target-libs-package-path | tail -n 1) echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" @@ -144,25 +170,6 @@ before_script: echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/target_libs_arch_name fi -build_and_test: - extends: .build_template - stage: test_build - variables: - TARGET: "Xtensa;RISCV" - SKIP_TESTS: "OFF" - PACK_DISTRO: "OFF" - CONF_HOST: "x86_64-linux-gnu" - USE_LINKER: "gold" - -.build_toolchain_template: - extends: .build_template - stage: build - parallel: - matrix: - - TARGET: - - Xtensa - - RISCV - .build_linux-gnu_template: extends: .build_toolchain_template variables: @@ -170,11 +177,24 @@ build_and_test: build_x86_64-linux-gnu: extends: .build_linux-gnu_template + stage: test_build variables: CONF_HOST: "x86_64-linux-gnu" + RUN_CORE_TESTS: "ON" + +build_target_libs: + extends: .build_linux-gnu_template + stage: build + variables: + CONF_HOST: "x86_64-linux-gnu" + RUN_TARGET_LIB_TESTS: "ON" + PACK_TARGET_LIBS: "ON" + PACK_TOOLCHAIN: "OFF" + PACK_STANDALONE_LIBS: "OFF" build_x86_64-w64-mingw32: extends: .build_toolchain_template + stage: build image: ${CROSS_WIN_IMAGE} variables: USE_LINKER: "" @@ -183,51 +203,30 @@ build_x86_64-w64-mingw32: build_arm-linux-gnueabihf: extends: .build_linux-gnu_template + stage: build image: ${CROSS_ARM_IMAGE} variables: CONF_HOST: "arm-linux-gnueabihf" build_aarch64-linux-gnu: extends: .build_linux-gnu_template + stage: build image: ${CROSS_ARM_IMAGE} variables: CONF_HOST: "aarch64-linux-gnu" build_x86_64-apple-darwin: extends: .build_toolchain_template + stage: build variables: CONF_HOST: "x86_64-apple-darwin21.1" build_aarch64-apple-darwin: extends: .build_toolchain_template + stage: build variables: CONF_HOST: "aarch64-apple-darwin21.1" -.pack_x86_64-linux-gnu_template: - stage: pack - tags: [ "amd64", "build" ] - artifacts: - paths: - - ${DIST_DIR}/ - when: always - expire_in: 1 day - script: - - pushd ${DIST_DIR} - - ls -l - - TARGET_LIBS_PACK_FILE=$(cat target_libs_arch_name) - - rm -f target_libs_arch_name ${TARGET_LIBS_PACK_FILE} - - ls -l - -pack_x86_64-linux-gnu_riscv: - extends: .pack_x86_64-linux-gnu_template - needs: - - job: "build_x86_64-linux-gnu: [RISCV]" - -pack_x86_64-linux-gnu_xtensa: - extends: .pack_x86_64-linux-gnu_template - needs: - - job: "build_x86_64-linux-gnu: [Xtensa]" - .pack_template: stage: pack tags: [ "amd64", "build" ] @@ -244,7 +243,7 @@ pack_x86_64-linux-gnu_xtensa: # update distro - pushd ${DIST_DIR} - ls -l - - DISTRO_PACK_FILE=$(cat dist_name_${CONF_HOST}_${TARGET}) + - DISTRO_PACK_FILE=$(cat dist_name_${CONF_HOST}) - echo "DISTRO_PACK_FILE=${DISTRO_PACK_FILE}" - ${UNPACK_TOOL} ${DISTRO_PACK_FILE} - DISTRO_PACK_DIR=$(tar tJf ${DISTRO_PACK_FILE} | sed -e 's@/.*@@' | uniq) @@ -263,115 +262,61 @@ pack_x86_64-linux-gnu_xtensa: # so that dir contains everything we need to re-pack after unpacking steps above - ${PACK_TOOL} ${DISTRO_PACK_FILE} ${DISTRO_PACK_DIR} - rm -rf ${DISTRO_PACK_DIR} - # remove x86_64-linux-gnu artifacts - - > - if [ "${CONF_HOST}" != "x86_64-linux-gnu" ]; then - DISTRO_PACK_FILE=$(cat dist_name_x86_64-linux-gnu_${TARGET}) - rm -f ${DISTRO_PACK_FILE} dist_name_x86_64-linux-gnu_${TARGET} - DISTRO_PACK_FILE=$(cat dist_name_libs_x86_64-linux-gnu_${TARGET}) - rm -f ${DISTRO_PACK_FILE} dist_name_libs_x86_64-linux-gnu_${TARGET} - fi - ls -l -pack_x86_64-w64-mingw32_riscv: +pack_x86_64-linux-gnu: extends: .pack_template needs: # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [RISCV]" - - job: "build_x86_64-w64-mingw32: [RISCV]" + - job: "build_target_libs" + - job: "build_x86_64-linux-gnu" variables: - CONF_HOST: "x86_64-w64-mingw32" - TARGET: "RISCV" + CONF_HOST: "x86_64-linux-gnu" -pack_x86_64-w64-mingw32_xtensa: +pack_x86_64-w64-mingw32: extends: .pack_template needs: # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [Xtensa]" - - job: "build_x86_64-w64-mingw32: [Xtensa]" + - job: "build_target_libs" + - job: "build_x86_64-w64-mingw32" variables: CONF_HOST: "x86_64-w64-mingw32" - TARGET: "Xtensa" -pack_arm-linux-gnueabihf_riscv: +pack_arm-linux-gnueabihf: extends: .pack_template needs: # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [RISCV]" - - job: "build_arm-linux-gnueabihf: [RISCV]" + - job: "build_target_libs" + - job: "build_arm-linux-gnueabihf" variables: CONF_HOST: "arm-linux-gnueabihf" - TARGET: "RISCV" - -pack_arm-linux-gnueabihf_xtensa: - extends: .pack_template - needs: - # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [Xtensa]" - - job: "build_arm-linux-gnueabihf: [Xtensa]" - variables: - CONF_HOST: "arm-linux-gnueabihf" - TARGET: "Xtensa" - -pack_aarch64-linux-gnu_riscv: - extends: .pack_template - needs: - # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [RISCV]" - - job: "build_aarch64-linux-gnu: [RISCV]" - variables: - CONF_HOST: "aarch64-linux-gnu" - TARGET: "RISCV" -pack_aarch64-linux-gnu_xtensa: +pack_aarch64-linux-gnu: extends: .pack_template needs: # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [Xtensa]" - - job: "build_aarch64-linux-gnu: [Xtensa]" + - job: "build_target_libs" + - job: "build_aarch64-linux-gnu" variables: CONF_HOST: "aarch64-linux-gnu" - TARGET: "Xtensa" -pack_x86_64-apple-darwin_riscv: +pack_x86_64-apple-darwin: extends: .pack_template needs: # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [RISCV]" - - job: "build_x86_64-apple-darwin: [RISCV]" + - job: "build_target_libs" + - job: "build_x86_64-apple-darwin" variables: CONF_HOST: "x86_64-apple-darwin21.1" - TARGET: "RISCV" -pack_x86_64-apple-darwin_xtensa: +pack_aarch64-apple-darwin: extends: .pack_template needs: # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [Xtensa]" - - job: "build_x86_64-apple-darwin: [Xtensa]" - variables: - CONF_HOST: "x86_64-apple-darwin21.1" - TARGET: "Xtensa" - -pack_aarch64-apple-darwin_riscv: - extends: .pack_template - needs: - # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [RISCV]" - - job: "build_aarch64-apple-darwin: [RISCV]" + - job: "build_target_libs" + - job: "build_aarch64-apple-darwin" variables: CONF_HOST: "aarch64-apple-darwin21.1" - TARGET: "RISCV" - -pack_aarch64-apple-darwin_xtensa: - extends: .pack_template - needs: - # needs target libs archive from native build job - - job: "build_x86_64-linux-gnu: [Xtensa]" - - job: "build_aarch64-apple-darwin: [Xtensa]" - variables: - CONF_HOST: "aarch64-apple-darwin21.1" - TARGET: "Xtensa" .macos_codesign_template: stage: sign @@ -395,25 +340,15 @@ pack_aarch64-apple-darwin_xtensa: git clone -q --depth=1 ${NOTARIZATION_SCRIPTS_GIT} - ./macos_codesign_notarization/run.sh -sign_x86_64-apple-darwin_riscv: - extends: .macos_codesign_template - needs: - - pack_x86_64-apple-darwin_riscv - -sign_x86_64-apple-darwin_xtensa: +sign_x86_64-apple-darwin: extends: .macos_codesign_template needs: - - pack_x86_64-apple-darwin_xtensa + - pack_x86_64-apple-darwin -sign_aarch64-apple-darwin_riscv: +sign_aarch64-apple-darwin: extends: .macos_codesign_template needs: - - pack_aarch64-apple-darwin_riscv - -sign_aarch64-apple-darwin_xtensa: - extends: .macos_codesign_template - needs: - - pack_aarch64-apple-darwin_xtensa + - pack_aarch64-apple-darwin upload_to_http: stage: private_deploy @@ -424,8 +359,7 @@ upload_to_http: # force the fetch strategy to clean old archives up in dist/ dir GIT_STRATEGY: fetch needs: - - job: pack_x86_64-linux-gnu_riscv - - job: pack_x86_64-linux-gnu_xtensa + - job: pack_x86_64-linux-gnu script: - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" # List of archives @@ -449,19 +383,14 @@ upload_to_github: GITHUB_TOKEN: "${GH_TOKEN}" GITHUB_REPO: "${GH_REPO_HTTPS}" TAG: "${CI_COMMIT_TAG}" + SHA256_FILE: esp-clang-${CI_COMMIT_TAG}-checksum.sha256 needs: - - job: pack_x86_64-linux-gnu_riscv - - job: pack_x86_64-linux-gnu_xtensa - - job: pack_arm-linux-gnueabihf_riscv - - job: pack_arm-linux-gnueabihf_xtensa - - job: pack_aarch64-linux-gnu_riscv - - job: pack_aarch64-linux-gnu_xtensa - - job: pack_x86_64-w64-mingw32_riscv - - job: pack_x86_64-w64-mingw32_xtensa - - job: sign_x86_64-apple-darwin_riscv - - job: sign_x86_64-apple-darwin_xtensa - - job: sign_aarch64-apple-darwin_riscv - - job: sign_aarch64-apple-darwin_xtensa + - job: pack_x86_64-linux-gnu + - job: pack_arm-linux-gnueabihf + - job: pack_aarch64-linux-gnu + - job: pack_x86_64-w64-mingw32 + - job: sign_x86_64-apple-darwin + - job: sign_aarch64-apple-darwin before_script: [] script: - ls -l dist*/ @@ -471,6 +400,16 @@ upload_to_github: - FILES=$(find ${DIST_DIR} -name dist_name_\* -exec cat {} \+) - cd ${DIST_DIR} - ls -l $FILES + # Generate checksum file + - > + for n in $FILES; do + sz=$(stat -c%s "${n}") >> ${SHA256_FILE}; + printf "# %s: %s bytes\n" "${n}" "${sz}" >> ${SHA256_FILE}; + sha256sum -b "${n}" >> ${SHA256_FILE}; + done + # Append FILES with checksum file + - FILES=$(echo -e "${FILES}\n${SHA256_FILE}") + - ls -l $FILES # Upload archives - for n in ${FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done @@ -481,10 +420,10 @@ update_idf_tools: only: - tags variables: - TOOL_NAME: openocd - TOOL_MEMBERS: openocd-esp32 + TOOL_NAME: esp-clang + TOOL_MEMBERS: esp-clang TOOL_VERSION: ${CI_COMMIT_TAG} - TOOL_SHA256_URL: https://github.com/espressif/openocd-esp32/releases/download/${CI_COMMIT_TAG}/openocd-esp32-${CI_COMMIT_TAG}-checksum.sha256 + TOOL_SHA256_URL: https://github.com/espressif/openocd-esp32/releases/download/esp-clang-${CI_COMMIT_TAG}/esp-clang-${CI_COMMIT_TAG}-checksum.sha256 RN_SECTION: Toolchain trigger: project: idf/idf-tools-updater From 619480b5e6bf21cac96678ce73a5b2d3c5fb7b6a Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Sat, 13 Apr 2024 00:21:19 +0300 Subject: [PATCH 247/261] esp/ci: Add special build to run tests --- .gitlab-ci.yml | 48 +++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index cb8aa697a551db..43cd6b195caa6f 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -64,7 +64,6 @@ before_script: - *get_toolchain_build_scripts - LLVM_PROJECT_PATH=$PWD - BUILD_PATH=$PWD/${BUILD_DIR} - - INST_PATH=$PWD/_install_dir - mkdir -p ${BUILD_PATH} - BUILD_HOST=$(gcc -dumpmachine) # Config to build target libraries @@ -111,8 +110,7 @@ before_script: -DLLVM_PARALLEL_COMPILE_JOBS=2 -DCLANG_REPOSITORY_STRING="${GH_REPO_HTTPS}" -DCPACK_ARCHIVE_THREADS=0 - -B ${BUILD_PATH} 2>&1 - --install-prefix=$INST_PATH > ${BUILD_PATH}/build.log + -B ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log # Do not run unit tests for cross-builds. # Run as non-root user because permission tests fail when run by root. - > @@ -170,6 +168,47 @@ before_script: echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/target_libs_arch_name fi +build_and_test: + tags: [ "amd64", "build" ] + stage: test_build + artifacts: + paths: + - ${BUILD_DIR}/*.log + when: always + expire_in: 1 day + variables: + after_script: + # help to identify that build failed due to OOM + - > + if [ $CI_JOB_STATUS == 'failed' ]; then + [ ! -f "${BUILD_DIR}/build.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/build.log || true + [ ! -f "${BUILD_DIR}/tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/tests.log || true + [ ! -f "${BUILD_DIR}/lld-tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/lld-tests.log || true + fi + script: + - BUILD_PATH=$PWD/${BUILD_DIR} + - mkdir -p ${BUILD_PATH} + - cmake -G Ninja + -S llvm + -DLLVM_ENABLE_PROJECTS="clang;lld;clang-tools-extra" + -DCMAKE_BUILD_TYPE=Release + -DLLVM_ENABLE_ASSERTIONS=ON + -DLLDB_INCLUDE_TESTS=OFF + -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=Xtensa + -B ${BUILD_PATH} 2>&1 > ${BUILD_PATH}/build.log + - export CUR_USER=$(whoami); + - useradd -m test_runner; + - chown -R test_runner ${BUILD_PATH}; + - echo "Run LLVM/Clang unit tests"; + - touch ${BUILD_PATH}/tests.log; + - chmod o+w ${BUILD_PATH}/tests.log; + - runuser -u test_runner -- ninja -C ${BUILD_PATH} check-all 2>&1 > ${BUILD_PATH}/tests.log; + - echo "Run LLD unit tests"; + - touch ${BUILD_PATH}/lld-tests.log; + - chmod o+w ${BUILD_PATH}/lld-tests.log; + - runuser -u test_runner -- ninja -C ${BUILD_PATH} check-lld 2>&1 > ${BUILD_PATH}/lld-tests.log; + - chown -R ${CUR_USER} ${BUILD_PATH}; + .build_linux-gnu_template: extends: .build_toolchain_template variables: @@ -177,10 +216,9 @@ before_script: build_x86_64-linux-gnu: extends: .build_linux-gnu_template - stage: test_build + stage: build variables: CONF_HOST: "x86_64-linux-gnu" - RUN_CORE_TESTS: "ON" build_target_libs: extends: .build_linux-gnu_template From f0f772fefe3afc11dcb61ef14a69789e568ee0b9 Mon Sep 17 00:00:00 2001 From: Andrei Safronov Date: Wed, 24 Apr 2024 01:29:09 +0300 Subject: [PATCH 248/261] [Xtensa] Fix LOOP* pseudo instructions. --- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 5 ++++- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 4 ++-- llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll | 11 ++++++----- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index a84aba944d686f..9c067f3fd5834a 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -359,6 +359,8 @@ bool XtensaInstrInfo::isBranchOffsetInRange(unsigned BranchOp, case Xtensa::JX: return true; case Xtensa::LOOPEND: + assert((BrOffset <= 0) && "Wrong hardware loop"); + return true; case Xtensa::LOOPBR: BrOffset += 4; assert((BrOffset <= 0) && "Wrong hardware loop"); @@ -787,4 +789,5 @@ bool XtensaInstrInfo::isBranch(const MachineBasicBlock::iterator &MI, assert(!MI->getDesc().isBranch() && "Unknown branch opcode"); return false; } -} \ No newline at end of file +} + diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 3ac309290d9dd3..cb28e10da6890f 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1481,13 +1481,13 @@ let isTerminator = 1, isBarrier = 1, hasSideEffects = 1, Size = 3 in { } // LOOPSTART pseudo instruction reserves 9 bytes for LOOP operation and NOP operations for possible alignment. -let isTerminator = 1, isBarrier = 1, hasSideEffects = 1, Size = 9 in { +let hasSideEffects = 1, Size = 9 in { def LOOPSTART : Pseudo<(outs), (ins AR:$s, brtarget:$target), "!loopstart $s, $target", []>; } // LOOPEND pseudo instruction reserves 6 bytes for Jump and NOP operations. -let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 0, Size = 6 in { +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 0, isNotDuplicable = 1, Size = 6 in { def LOOPEND : Pseudo<(outs), (ins brtarget:$target), "!loopend $target", [(Xtensa_loopend bb:$target)]>; } diff --git a/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll b/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll index ba188d61b5c8ea..6523d83cafe4f5 100644 --- a/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll +++ b/llvm/test/CodeGen/Xtensa/hwloop_inner_loop.ll @@ -22,10 +22,11 @@ for.body: ; preds = %entry, %for.body %inc = add nuw nsw i32 %i.09, 1 %cmp = icmp slt i32 %inc, %n br i1 %cmp, label %for.body, label %for.cond.cleanup -; CHECK: loop a4, .LBB0_5 -; CHECK: bge a8, a2, .LBB0_2 -; CHECK: mull a9, a2, a3 -; CHECK: add.n a2, a9, a2 -; CHECK: .LBB0_5 +; CHECK: [[FOR_BODY:.LBB[0-9_]+]]: +; CHECK: loop a4, [[LOOP_END:.LBB[0-9_]+]] +; CHECK: bge a8, a2, [[FOR_BODY]] +; CHECK: nop +; CHECK-NEXT: [[LOOP_END]]: +; CHECK: j .LBB } From c784bd35449d0da826dd114b95bf042d1bff8fd0 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 3 May 2024 11:23:30 +0300 Subject: [PATCH 249/261] esp/ci: Upgrade docker image for Windows build to use MinGW 10 --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 43cd6b195caa6f..02aadbc944b067 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -14,7 +14,7 @@ variables: ESP_LLVM_EMBEDDED_TOOLCHAIN_REF: "master" ESP_GNU_TOOLCHAIN_VER: "13.2.0_20240305" CROSS_ARM_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-arm:1 - CROSS_WIN_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-win:1 + CROSS_WIN_IMAGE: $CI_DOCKER_REGISTRY/llvm-build-cross-win:2 DIST_DIR: "dist" BUILD_DIR: "build" From d7da2921b15270d87a3993313483e27bc8af297a Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Thu, 18 Apr 2024 10:44:37 +0200 Subject: [PATCH 250/261] [Xtensa] Fix issue with adding scavenging frame index --- llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index f1db383620b376..6c191e2cf2f135 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -399,7 +399,8 @@ void XtensaFrameLowering::processFunctionBeforeFrameFinalized( const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); unsigned Size = TRI.getSpillSize(RC); Align Alignment = TRI.getSpillAlign(RC); - for (int i = 0; i < NeedRegs; i++) + // If NeedsRegs == 0, we still need a spill slot + for (int i = 0; i <= NeedRegs; i++) RS->addScavengingFrameIndex( MFI.CreateStackObject(Size, Alignment, false)); } From 55758c35206648fea9de7e5edbc14751bbe144ed Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 14 May 2024 23:24:55 +0300 Subject: [PATCH 251/261] esp/ci: Separate checksum files for toolchain and standalone libs distros --- .gitlab-ci.yml | 47 +++++++++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 02aadbc944b067..b28cf30282426d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -155,7 +155,7 @@ before_script: echo "DISTRO_PACK_PATH=${DISTRO_PACK_PATH}" mv ${DISTRO_PACK_PATH} ${PWD}/${DIST_DIR}/ ARCHIVE_NAME=$(basename ${DISTRO_PACK_PATH}) - echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/dist_name_libs_${CONF_HOST} + echo "${ARCHIVE_NAME}" > ${PWD}/${DIST_DIR}/libs_dist_name_${CONF_HOST} fi # pack target libraries to be re-used in distros for other platforms - > @@ -408,6 +408,17 @@ upload_to_http: # Show info - echo -e "\nArchives were published there:\n\n$(for n in ${FILES}; do echo "${HTTP_PUBLIC_DIR}/ct-ng/llvm-builds/${n}"; done)\n" +.gen_checksum_file: &gen_checksum_file | + ls -l ${FILES} + for n in ${FILES}; do + sz=$(stat -c%s "${n}") >> ${SHA256_FILE}; + printf "# %s: %s bytes\n" "${n}" "${sz}" >> ${SHA256_FILE}; + sha256sum -b "${n}" >> ${SHA256_FILE}; + done + # Append FILES with checksum file + FILES=$(echo -e "${FILES}\n${SHA256_FILE}") + ls -l ${FILES} + upload_to_github: stage: public_deploy when: manual @@ -421,7 +432,8 @@ upload_to_github: GITHUB_TOKEN: "${GH_TOKEN}" GITHUB_REPO: "${GH_REPO_HTTPS}" TAG: "${CI_COMMIT_TAG}" - SHA256_FILE: esp-clang-${CI_COMMIT_TAG}-checksum.sha256 + TOOLCHAIN_SHA256_FILE: clang-${CI_COMMIT_TAG}-checksum.sha256 + LIBS_SHA256_FILE: libs-clang-${CI_COMMIT_TAG}-checksum.sha256 needs: - job: pack_x86_64-linux-gnu - job: pack_arm-linux-gnueabihf @@ -431,25 +443,24 @@ upload_to_github: - job: sign_aarch64-apple-darwin before_script: [] script: - - ls -l dist*/ + - ls -l ${DIST_DIR} + - cd ${DIST_DIR} - git remote add github ${GH_REPO_HTTPS} - hub release show ${TAG} || { echo "Please create a release on GitHub with ${TAG} tag at first"; exit 1; } + # Generate checksum file for toolchain # List of archives - - FILES=$(find ${DIST_DIR} -name dist_name_\* -exec cat {} \+) - - cd ${DIST_DIR} - - ls -l $FILES - # Generate checksum file - - > - for n in $FILES; do - sz=$(stat -c%s "${n}") >> ${SHA256_FILE}; - printf "# %s: %s bytes\n" "${n}" "${sz}" >> ${SHA256_FILE}; - sha256sum -b "${n}" >> ${SHA256_FILE}; - done - # Append FILES with checksum file - - FILES=$(echo -e "${FILES}\n${SHA256_FILE}") - - ls -l $FILES + - FILES=$(find ${PWD} -name dist_name_\* -exec cat {} \+) + - SHA256_FILE=${TOOLCHAIN_SHA256_FILE} + - *gen_checksum_file + - DIST_FILES=${FILES} + # Generate checksum file for standalone libraries + - FILES=$(find ${PWD} -name libs_dist_name_\* -exec cat {} \+) + - SHA256_FILE=${LIBS_SHA256_FILE} + - *gen_checksum_file + - DIST_FILES=$(echo -e "${DIST_FILES}\n${FILES}") + - ls -l ${DIST_FILES} # Upload archives - - for n in ${FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done + - for n in ${DIST_FILES}; do hub release edit -m "" -a "${n}" "${TAG}"; done update_idf_tools: stage: update_idf_tools @@ -461,7 +472,7 @@ update_idf_tools: TOOL_NAME: esp-clang TOOL_MEMBERS: esp-clang TOOL_VERSION: ${CI_COMMIT_TAG} - TOOL_SHA256_URL: https://github.com/espressif/openocd-esp32/releases/download/esp-clang-${CI_COMMIT_TAG}/esp-clang-${CI_COMMIT_TAG}-checksum.sha256 + TOOL_SHA256_URL: https://github.com/espressif/llvm-project/releases/download/${CI_COMMIT_TAG}/clang-${CI_COMMIT_TAG}-checksum.sha256 RN_SECTION: Toolchain trigger: project: idf/idf-tools-updater From 6bc1f2ce10d3cd52e6498ce6b393891ae2b9bd34 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 14 May 2024 20:27:27 +0300 Subject: [PATCH 252/261] [RISCV] Add user trap CSRs --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 16 +++ llvm/test/MC/RISCV/rv32e-valid.s | 4 +- llvm/test/MC/RISCV/rv32i-valid.s | 4 +- llvm/test/MC/RISCV/user-csr-names.s | 116 +++++++++++++++++++ 4 files changed, 136 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 33eb1d850caea4..a83b956d34ee8d 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -327,6 +327,22 @@ let AltName = "dscratch" in def : SysReg<"dscratch0", 0x7B2>; def : SysReg<"dscratch1", 0x7B3>; +//===----------------------------------------------------------------------===// +// User Trap Setup +//===----------------------------------------------------------------------===// +def : SysReg<"ustatus", 0x000>; +def : SysReg<"uie", 0x004>; +def : SysReg<"utvec", 0x005>; + +//===----------------------------------------------------------------------===// +// User Trap Handling +//===----------------------------------------------------------------------===// +def : SysReg<"uscratch", 0x040>; +def : SysReg<"uepc", 0x041>; +def : SysReg<"ucause", 0x042>; +def : SysReg<"utval", 0x043>; +def : SysReg<"uip", 0x044>; + //===----------------------------------------------------------------------===// // User Vector CSRs //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/RISCV/rv32e-valid.s b/llvm/test/MC/RISCV/rv32e-valid.s index ccb47f1557c698..1c252deec83eeb 100644 --- a/llvm/test/MC/RISCV/rv32e-valid.s +++ b/llvm/test/MC/RISCV/rv32e-valid.s @@ -116,9 +116,9 @@ csrrw t0, 0xfff, t1 csrrs s0, 0xc00, x0 # CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5 csrrs s0, 0x001, a5 -# CHECK-ASM-AND-OBJ: csrrc sp, 0, ra +# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra csrrc sp, 0x000, ra -# CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0 +# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 csrrwi a5, 0x000, 0 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 csrrsi t2, 0xfff, 31 diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s index f03c2e1c23cf3b..8a561eba43b7e4 100644 --- a/llvm/test/MC/RISCV/rv32i-valid.s +++ b/llvm/test/MC/RISCV/rv32i-valid.s @@ -361,10 +361,10 @@ csrrs s0, 0xc00, x0 # CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5 # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00] csrrs s3, 0x001, s5 -# CHECK-ASM-AND-OBJ: csrrc sp, 0, ra +# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra # CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00] csrrc sp, 0x000, ra -# CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0 +# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 # CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00] csrrwi a5, 0x000, 0 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 diff --git a/llvm/test/MC/RISCV/user-csr-names.s b/llvm/test/MC/RISCV/user-csr-names.s index 9f8f029e564275..569e72832678de 100644 --- a/llvm/test/MC/RISCV/user-csr-names.s +++ b/llvm/test/MC/RISCV/user-csr-names.s @@ -466,3 +466,119 @@ csrrs t2, 0xC1E, zero csrrs t1, hpmcounter31, zero # uimm12 csrrs t2, 0xC1F, zero + +################################## +# User Trap Setup +################################## + +# ustatus +# name +# CHECK-INST: csrrs t1, ustatus, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x00] +# CHECK-INST-ALIAS: csrr t1, ustatus +# uimm12 +# CHECK-INST: csrrs t2, ustatus, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x00] +# CHECK-INST-ALIAS: csrr t2, ustatus +# name +csrrs t1, ustatus, zero +# uimm12 +csrrs t2, 0x000, zero + +# uie +# name +# CHECK-INST: csrrs t1, uie, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x00] +# CHECK-INST-ALIAS: csrr t1, uie +# uimm12 +# CHECK-INST: csrrs t2, uie, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x00] +# CHECK-INST-ALIAS: csrr t2, uie +# name +csrrs t1, uie, zero +# uimm12 +csrrs t2, 0x004, zero + +# utvec +# name +# CHECK-INST: csrrs t1, utvec, zero +# CHECK-ENC: encoding: [0x73,0x23,0x50,0x00] +# CHECK-INST-ALIAS: csrr t1, utvec +# uimm12 +# CHECK-INST: csrrs t2, utvec, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x00] +# CHECK-INST-ALIAS: csrr t2, utvec +# name +csrrs t1, utvec, zero +# uimm12 +csrrs t2, 0x005, zero + +# uscratch +# name +# CHECK-INST: csrrs t1, uscratch, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x04] +# CHECK-INST-ALIAS: csrr t1, uscratch +# uimm12 +# CHECK-INST: csrrs t2, uscratch, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x04] +# CHECK-INST-ALIAS: csrr t2, uscratch +# name +csrrs t1, uscratch, zero +# uimm12 +csrrs t2, 0x040, zero + +# uepc +# name +# CHECK-INST: csrrs t1, uepc, zero +# CHECK-ENC: encoding: [0x73,0x23,0x10,0x04] +# CHECK-INST-ALIAS: csrr t1, uepc +# uimm12 +# CHECK-INST: csrrs t2, uepc, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x04] +# CHECK-INST-ALIAS: csrr t2, uepc +# name +csrrs t1, uepc, zero +# uimm12 +csrrs t2, 0x041, zero + +# ucause +# name +# CHECK-INST: csrrs t1, ucause, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x04] +# CHECK-INST-ALIAS: csrr t1, ucause +# uimm12 +# CHECK-INST: csrrs t2, ucause, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x04] +# CHECK-INST-ALIAS: csrr t2, ucause +# name +csrrs t1, ucause, zero +# uimm12 +csrrs t2, 0x042, zero + +# utval +# name +# CHECK-INST: csrrs t1, utval, zero +# CHECK-ENC: encoding: [0x73,0x23,0x30,0x04] +# CHECK-INST-ALIAS: csrr t1, utval +# uimm12 +# CHECK-INST: csrrs t2, utval, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x04] +# CHECK-INST-ALIAS: csrr t2, utval +# name +csrrs t1, utval, zero +# uimm12 +csrrs t2, 0x043, zero + +# uip +# name +# CHECK-INST: csrrs t1, uip, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x04] +# CHECK-INST-ALIAS: csrr t1, uip +# uimm12 +# CHECK-INST: csrrs t2, uip, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x04] +# CHECK-INST-ALIAS: csrr t2, uip +# name +csrrs t1, uip, zero +# uimm12 +csrrs t2, 0x044, zero From 74a35b5348b0cfb4919b07410fce2a262ba56572 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 5 Jul 2024 17:13:34 +0300 Subject: [PATCH 253/261] [Xtensa] Add Xtensa builtins into last builtin ID calculation --- clang/include/clang/Basic/TargetBuiltins.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index 25f6526fb022ca..a84bee508c7a84 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -383,7 +383,7 @@ namespace clang { PPC::LastTSBuiltin, NVPTX::LastTSBuiltin, AMDGPU::LastTSBuiltin, X86::LastTSBuiltin, VE::LastTSBuiltin, RISCV::LastTSBuiltin, Hexagon::LastTSBuiltin, Mips::LastTSBuiltin, XCore::LastTSBuiltin, - SystemZ::LastTSBuiltin, WebAssembly::LastTSBuiltin}); + SystemZ::LastTSBuiltin, WebAssembly::LastTSBuiltin, Xtensa::LastTSBuiltin}); } // end namespace clang. From 255e3a332d1c5061845868063f56120516af544a Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Tue, 25 Jun 2024 17:13:46 +0200 Subject: [PATCH 254/261] [Xtensa] Support for asm underscore prefix --- .../Xtensa/AsmParser/XtensaAsmParser.cpp | 18 ++ .../Disassembler/XtensaDisassembler.cpp | 8 + .../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 11 ++ .../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 1 + .../MCTargetDesc/XtensaMCCodeEmitter.cpp | 16 ++ llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 119 ++++++++++++- llvm/lib/Target/Xtensa/XtensaOperands.td | 7 + llvm/test/MC/Xtensa/Core/arith.s | 10 ++ llvm/test/MC/Xtensa/Core/branch.s | 156 ++++++++++++++++++ llvm/test/MC/Xtensa/Core/invalid.s | 7 +- llvm/test/MC/Xtensa/Core/memory.s | 10 ++ llvm/test/MC/Xtensa/Core/shift.s | 5 + 12 files changed, 363 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index e733a20a18e6e5..3c86874722c2aa 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -309,6 +309,8 @@ struct XtensaOperand : public MCParsedAsmOperand { bool isImm8n_7() const { return isImm(-8, 7); } bool isShimm1_31() const { return isImm(1, 31); } + + bool isShimm0_31() const { return isImm(0, 31); } bool isImm16_31() const { return isImm(16, 31); } @@ -646,6 +648,19 @@ bool XtensaAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, Inst = TmpInst; } } break; + case Xtensa::SLLI: { + uint32_t ImmOp32 = static_cast(Inst.getOperand(2).getImm()); + int64_t Imm = ImmOp32; + if (Imm == 0) { + MCInst TmpInst; + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(Xtensa::OR); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(Inst.getOperand(1)); + Inst = TmpInst; + } + } break; default: break; } @@ -720,6 +735,9 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidShimm1_31: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [1, 31]"); + case Match_InvalidShimm0_31: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected immediate in range [0, 31]"); case Match_InvalidUimm4: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range [0, 15]"); diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp index 81c02b5de46524..e613c56e146d0e 100644 --- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp +++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp @@ -659,6 +659,14 @@ static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeShimm0_31Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<5>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(32 - Imm)); + return MCDisassembler::Success; +} + static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index a8c1aaed10b1a6..7a5809c7059f70 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -264,6 +264,17 @@ void XtensaInstPrinter::printShimm1_31_AsmOperand(const MCInst *MI, int OpNum, printOperand(MI, OpNum, O); } +void XtensaInstPrinter::printShimm0_31_AsmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 31) && + "Invalid argument, value must be in range [0,31]"); + O << Value; + } else + printOperand(MI, OpNum, O); +} + void XtensaInstPrinter::printImm1_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { if (MI->getOperand(OpNum).isImm()) { diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index 756554bcf09b96..174fb51a6f054f 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -59,6 +59,7 @@ class XtensaInstPrinter : public MCInstPrinter { void printUimm4_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printUimm5_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printShimm1_31_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printShimm0_31_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printImm1_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printImm1n_15_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printImm32n_95_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O); diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp index 958dedbaaa2e51..3ac46b07e04ddd 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp @@ -135,6 +135,10 @@ class XtensaMCCodeEmitter : public MCCodeEmitter { SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + uint32_t getShimm0_31OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + uint32_t getB4constOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -454,6 +458,18 @@ XtensaMCCodeEmitter::getShimm1_31OpValue(const MCInst &MI, unsigned OpNo, return ((32 - Res) & 0x1f); } +uint32_t +XtensaMCCodeEmitter::getShimm0_31OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint32_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 31)) && "Unexpected operand value!"); + + return ((32 - Res) & 0x1f); +} + uint32_t XtensaMCCodeEmitter::getImm1_16OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index cb28e10da6890f..76e161b6f23584 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -40,6 +40,8 @@ def AND : ArithLogic_RRR<0x01, 0x00, "and", and, 1>; def OR : ArithLogic_RRR<0x02, 0x00, "or", or, 1>; def XOR : ArithLogic_RRR<0x03, 0x00, "xor", xor, 1>; +def : InstAlias<"_add\t$r, $s, $t", (ADD AR:$r, AR:$s, AR:$t)>; + class ADDX oper, string instrAsm, list pattern> : RRR_Inst<0x00, 0x00, oper, (outs AR:$r), (ins AR:$s, AR:$t), instrAsm#"\t$r, $s, $t", pattern>; @@ -67,6 +69,8 @@ def ADDI : RRI8_Inst<0x02, (outs AR:$t), (ins AR:$s, imm8:$imm8), let r = 0x0C; } +def : InstAlias<"_addi\t$r, $s, $imm8", (ADDI AR:$r, AR:$s, imm8:$imm8)>; + def ADDMI : RRI8_Inst<0x02, (outs AR:$t), (ins AR:$s, imm8_sh8:$imm_sh8), "addmi\t$t, $s, $imm_sh8", [(set AR:$t, (add AR:$s, imm8_sh8:$imm_sh8))]> { @@ -95,6 +99,17 @@ def MOVI : RRI8_Inst<0x02, (outs AR:$t), (ins imm12m:$imm), let r = 0xa; } +def _MOVI : RRI8_Inst<0x02, (outs AR:$t), (ins imm12:$imm), + "_movi\t$t, $imm", + [(set AR:$t, imm12m:$imm)]> { + let DecoderNamespace = "Fallback"; + bits<12> imm; + + let imm8{7-0} = imm{7-0}; + let s{3-0} = imm{11-8}; + let r = 0xa; +} + def MOVEQZ : RRR_Inst<0x00, 0x03, 0x08, (outs AR:$r), (ins AR:$s, AR:$t), "moveqz\t$r, $s, $t", []>; def MOVNEZ : RRR_Inst<0x00, 0x03, 0x09, (outs AR:$r), (ins AR:$s, AR:$t), @@ -184,9 +199,18 @@ def _SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa), let s = sa; } -def SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm1_31:$sa), - "slli\t$r, $s, $sa", +def SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm0_31:$sa), + "slli\t$r, $s, $sa", []> { + bits<5> sa; + + let Inst{20} = sa{4}; + let t = sa{3-0}; +} + +def _SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm1_31:$sa), + "_slli\t$r, $s, $sa", [(set AR:$r, (shl AR:$s, shimm1_31:$sa))]> { + let DecoderNamespace = "Fallback"; bits<5> sa; let Inst{20} = sa{4}; @@ -249,6 +273,9 @@ def L8UI : Load_RRI8<0x00, "l8ui", zextloadi8, addr_ish1, mem8>; def L16SI : Load_RRI8<0x09, "l16si", sextloadi16, addr_ish2, mem16>; def L16UI : Load_RRI8<0x01, "l16ui", zextloadi16, addr_ish2, mem16>; def L32I : Load_RRI8<0x02, "l32i", load, addr_ish4, mem32>; +def _L32I : Load_RRI8<0x02, "_l32i", load, addr_ish4, mem32> { + let DecoderNamespace = "Fallback"; +} // Store instructions let mayStore = 1, usesCustomInserter = 1 in { @@ -268,6 +295,9 @@ let mayStore = 1, usesCustomInserter = 1 in { def S8I : Store_II8<0x04, "s8i", truncstorei8, addr_ish1, mem8>; def S16I : Store_II8<0x05, "s16i", truncstorei16, addr_ish2, mem16>; def S32I : Store_II8<0x06, "s32i", store, addr_ish4, mem32>; +def _S32I : Store_II8<0x06, "_s32i", store, addr_ish4, mem32> { + let DecoderNamespace = "Fallback"; +} def L32R : RI16_Inst<0x01, (outs AR:$t), (ins L32Rtarget:$label), "l32r\t$t, $label", []> { @@ -369,6 +399,14 @@ def BLT : Branch_RR<0x02, "blt", SETLT>; def BGEU : Branch_RR<0x0B, "bgeu", SETUGE>; def BLTU : Branch_RR<0x03, "bltu", SETULT>; +// RR aliases +def : InstAlias<"_beq\t$s, $t, $target", (BEQ AR:$s, AR:$t, brtarget:$target)>; +def : InstAlias<"_bne\t$s, $t, $target", (BNE AR:$s, AR:$t, brtarget:$target)>; +def : InstAlias<"_bge\t$s, $t, $target", (BGE AR:$s, AR:$t, brtarget:$target)>; +def : InstAlias<"_blt\t$s, $t, $target", (BLT AR:$s, AR:$t, brtarget:$target)>; +def : InstAlias<"_bgeu\t$s, $t, $target", (BGEU AR:$s, AR:$t, brtarget:$target)>; +def : InstAlias<"_bltu\t$s, $t, $target", (BLTU AR:$s, AR:$t, brtarget:$target)>; + def BEQI : Branch_RI<0x02, "beqi", SETEQ>; def BNEI : Branch_RI<0x06, "bnei", SETNE>; def BGEI : Branch_RI<0x0E, "bgei", SETGE>; @@ -376,11 +414,25 @@ def BLTI : Branch_RI<0x0A, "blti", SETLT>; def BGEUI : Branch_RIU<0x0F, "bgeui", SETUGE>; def BLTUI : Branch_RIU<0x0B, "bltui", SETULT>; +// RI aliases +def : InstAlias<"_beqi\t$s, $imm, $target", (BEQI AR:$s, b4const:$imm, brtarget:$target)>; +def : InstAlias<"_bnei\t$s, $imm, $target", (BNEI AR:$s, b4const:$imm, brtarget:$target)>; +def : InstAlias<"_bgei\t$s, $imm, $target", (BGEI AR:$s, b4const:$imm, brtarget:$target)>; +def : InstAlias<"_blti\t$s, $imm, $target", (BLTI AR:$s, b4const:$imm, brtarget:$target)>; +def : InstAlias<"_bgeui\t$s, $imm, $target", (BGEUI AR:$s, b4constu:$imm, brtarget:$target)>; +def : InstAlias<"_bltui\t$s, $imm, $target", (BLTUI AR:$s, b4constu:$imm, brtarget:$target)>; + def BEQZ : Branch_RZ<0x01, 0x00, "beqz", SETEQ>; def BNEZ : Branch_RZ<0x01, 0x01, "bnez", SETNE>; def BGEZ : Branch_RZ<0x01, 0x03, "bgez", SETGE>; def BLTZ : Branch_RZ<0x01, 0x02, "bltz", SETLT>; +// RZ aliases +def : InstAlias<"_beqz\t$s, $target", (BEQZ AR:$s, brtarget:$target)>; +def : InstAlias<"_bnez\t$s, $target", (BNEZ AR:$s, brtarget:$target)>; +def : InstAlias<"_bgez\t$s, $target", (BGEZ AR:$s, brtarget:$target)>; +def : InstAlias<"_bltz\t$s, $target", (BLTZ AR:$s, brtarget:$target)>; + def BALL : RRI8_Inst<0x07, (outs), (ins AR:$s, AR:$t, brtarget:$target), "ball\t$s, $t, $target", []> { @@ -390,6 +442,8 @@ def BALL : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"_ball\t$s, $t, $target", (BALL AR:$s, AR:$t, brtarget:$target)>; + def BANY : RRI8_Inst<0x07, (outs), (ins AR:$s, AR:$t, brtarget:$target), "bany\t$s, $t, $target", []> { @@ -399,6 +453,8 @@ def BANY : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"_bany\t$s, $t, $target", (BANY AR:$s, AR:$t, brtarget:$target)>; + def BBC : RRI8_Inst<0x07, (outs), (ins AR:$s, AR:$t, brtarget:$target), "bbc\t$s, $t, $target", []> { @@ -408,6 +464,8 @@ def BBC : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"_bbc\t$s, $t, $target", (BBC AR:$s, AR:$t, brtarget:$target)>; + def BBS : RRI8_Inst<0x07, (outs), (ins AR:$s, AR:$t, brtarget:$target), "bbs\t$s, $t, $target", []> { @@ -417,6 +475,8 @@ def BBS : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"_bbs\t$s, $t, $target", (BBS AR:$s, AR:$t, brtarget:$target)>; + def BNALL : RRI8_Inst<0x07, (outs), (ins AR:$s, AR:$t, brtarget:$target), "bnall\t$s, $t, $target", []> { @@ -426,6 +486,8 @@ def BNALL : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"_bnall\t$s, $t, $target", (BNALL AR:$s, AR:$t, brtarget:$target)>; + def BNONE : RRI8_Inst<0x07, (outs), (ins AR:$s, AR:$t, brtarget:$target), "bnone\t$s, $t, $target", []> { @@ -435,6 +497,8 @@ def BNONE : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"_bnone\t$s, $t, $target", (BNONE AR:$s, AR:$t, brtarget:$target)>; + def BBCI : RRI8_Inst<0x07, (outs), (ins AR:$s, uimm5:$imm, brtarget:$target), "bbci\t$s, $imm, $target", []> { @@ -465,6 +529,8 @@ def BBSI : RRI8_Inst<0x07, (outs), let imm8 = target; } +def : InstAlias<"_bbsi\t$s, $imm, $target", (BBSI AR:$s, uimm5:$imm, brtarget:$target)>; + def : InstAlias<"bbsi.l\t$s, $imm, $target", (BBSI AR:$s, uimm5:$imm, brtarget:$target)>; def : InstAlias<"_bbsi.l\t$s, $imm, $target", (BBSI AR:$s, uimm5:$imm, brtarget:$target)>; @@ -548,6 +614,8 @@ let isReturn = 1, isTerminator = 1, } } +def : InstAlias<"_ret", (RET)>; + // Call patterns def : Pat<(Xtensa_call (i32 tglobaladdr:$dst)), (CALL0 tglobaladdr:$dst)>; @@ -626,6 +694,8 @@ def NOP : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins), let t = 0x0f; } +def : InstAlias<"_nop", (NOP)>; + def WSR : RSR_Inst<0x00, 0x03, 0x01, (outs SR:$sr), (ins AR:$t), "wsr\t$t, $sr", []>; @@ -726,6 +796,8 @@ class ArithLogic_RRRN oper0, string instrAsm, def ADD_N : ArithLogic_RRRN<0x0a, "add.n", add, 1>; +def : InstAlias<"_add.n\t$r, $s, $t", (ADD_N AR:$r, AR:$s, AR:$t)>; + def ADDI_N : RRRN_Inst<0x0B, (outs AR:$r), (ins AR:$s, imm1n_15:$imm), "addi.n\t$r, $s, $imm", [(set AR:$r, (add AR:$s, imm1n_15:$imm))]>, Requires<[HasDensity]> { @@ -734,11 +806,14 @@ def ADDI_N : RRRN_Inst<0x0B, (outs AR:$r), (ins AR:$s, imm1n_15:$imm), let t = imm; } +def : InstAlias<"_addi.n\t$r, $s, $imm", (ADDI_N AR:$r, AR:$s, imm1n_15:$imm)>; + def MOV_N : RRRN_Inst<0x0D, (outs AR:$t), (ins AR:$s), "mov.n\t$t, $s", []>, Requires<[HasDensity]> { let r = 0; } +def : InstAlias<"_mov.n\t $t, $s", (MOV_N AR:$t, AR:$s)>; def : InstAlias<"mov\t $t, $s", (OR AR:$t, AR:$s, AR:$s)>; def MOVI_N : RI7_Inst<0xc, 0x0, (outs AR:$s), (ins imm32n_95:$imm7), @@ -749,7 +824,7 @@ def : InstAlias<"_movi.n\t$s, $imm7", (MOVI_N AR:$s, imm32n_95:$imm7)>; // Load instruction let mayLoad = 1, usesCustomInserter = 1 in { - def L32I_N : RRRN_Inst<0x8, (outs AR:$t), (ins mem32n:$addr), + def L32I_N : RRRN_Inst<0x8, (outs AR:$t), (ins mem32n:$addr), "l32i.n\t$t, $addr", []>, Requires<[HasDensity]> { bits<8> addr; @@ -758,6 +833,17 @@ let mayLoad = 1, usesCustomInserter = 1 in { } } +let mayLoad = 1, usesCustomInserter = 1 in { + def _L32I_N : RRRN_Inst<0x8, (outs AR:$t), (ins mem32n:$addr), + "_l32i.n\t$t, $addr", []>, Requires<[HasDensity]> { + bits<8> addr; + let DecoderNamespace = "Fallback"; + + let r{3-0} = addr{7-4}; + let s{3-0} = addr{3-0}; + } +} + // Store instruction let mayStore = 1, usesCustomInserter = 1 in { def S32I_N : RRRN_Inst<0x9, (outs), (ins AR:$t, mem32n:$addr), @@ -769,6 +855,17 @@ let mayStore = 1, usesCustomInserter = 1 in { } } +let mayStore = 1, usesCustomInserter = 1 in { + def _S32I_N : RRRN_Inst<0x9, (outs), (ins AR:$t, mem32n:$addr), + "_s32i.n\t$t, $addr", []>, Requires<[HasDensity]> { + bits<8> addr; + let DecoderNamespace = "Fallback"; + + let r{3-0} = addr{7-4}; + let s{3-0} = addr{3-0}; + } +} + //Return instruction let isReturn = 1, isTerminator = 1, isBarrier = 1, Uses = [A0] in { @@ -781,6 +878,8 @@ let isReturn = 1, isTerminator = 1, } } +def : InstAlias<"_ret.n", (RET_N)>; + //===----------------------------------------------------------------------===// // Windowed instructions //===----------------------------------------------------------------------===// @@ -868,6 +967,9 @@ let isReturn = 1, isTerminator = 1, } } +def : InstAlias<"_retw", (RETW)>; +def : InstAlias<"_retw.n", (RETW_N)>; + //Store 32-bit for Window Exceptions def S32E : RRI4_Inst<0x00, 0x09, (outs), (ins AR:$t, AR:$s, imm64n_4n:$imm), "s32e\t$t, $s, $imm", []>, Requires<[HasWindowed]> { @@ -980,6 +1082,9 @@ let isBranch = 1, isTerminator = 1, Predicates = [HasBoolean] in { } } +def : InstAlias<"_BT\t$b, $target", (BT BR:$b, brtarget:$target)>; +def : InstAlias<"_BF\t$b, $target", (BF BR:$b, brtarget:$target)>; + let Constraints = "$dr = $r,@earlyclobber $dr" in { def MOVF : RRR_Inst<0x00, 0x03, 0x0C, (outs AR:$dr), (ins AR:$r, AR:$s, BR:$t), "movf\t$r, $s, $t", []>, Requires<[HasBoolean]>; @@ -1457,6 +1562,8 @@ def LOOP : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), let imm8 = target; } +def : InstAlias<"_loop\t$s, $target", (LOOP AR:$s, ltarget:$target)>; + def LOOPGTZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), "loopgtz\t$s, $target", []>, Requires<[HasLoop]> { bits<8> target; @@ -1466,6 +1573,8 @@ def LOOPGTZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), let imm8 = target; } +def : InstAlias<"_loopgtz\t$s, $target", (LOOPGTZ AR:$s, ltarget:$target)>; + def LOOPNEZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), "loopnez\t$s, $target", []>, Requires<[HasLoop]> { bits<8> target; @@ -1475,6 +1584,8 @@ def LOOPNEZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target), let imm8 = target; } +def : InstAlias<"_loopnez\t$s, $target", (LOOPNEZ AR:$s, ltarget:$target)>; + let isTerminator = 1, isBarrier = 1, hasSideEffects = 1, Size = 3 in { def LOOPINIT : Pseudo<(outs AR:$elts), (ins AR:$eltsin), "!loopinit $elts, $eltsin", [(set AR:$elts, (int_start_loop_iterations AR:$eltsin))]>; @@ -1613,6 +1724,8 @@ let isBarrier = 1, isTerminator = 1 in { } } +def : InstAlias<"_break.n\t$imm", (BREAK_N uimm4:$imm)>; + def : Pat<(trap), (BREAK (i32 1), (i32 15))>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 3d10410a775996..1976d50b8c4bb6 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -127,6 +127,13 @@ def shimm1_31 : Immediate= 1 && Imm <= 31; }], "Shimm1_31_A let DecoderMethod = "decodeShimm1_31Operand"; } +// shimm0_31 predicate - Immediate in the range [0,31] +def Shimm0_31_AsmOperand : ImmAsmOperand<"Shimm0_31">; +def shimm0_31 : Immediate= 0 && Imm <= 31; }], "Shimm0_31_AsmOperand"> { + let EncoderMethod = "getShimm0_31OpValue"; + let DecoderMethod = "decodeShimm1_31Operand"; +} + defm imm32n_28: ImmRangeDecl<-32, 28, 4>; defm imm64n_56: ImmRangeDecl<-64, 56, 8>; defm imm0_56: ImmRangeDecl<0, 56, 8>; diff --git a/llvm/test/MC/Xtensa/Core/arith.s b/llvm/test/MC/Xtensa/Core/arith.s index fb6ac2608b0a93..1a1090e26ef878 100644 --- a/llvm/test/MC/Xtensa/Core/arith.s +++ b/llvm/test/MC/Xtensa/Core/arith.s @@ -15,6 +15,11 @@ abs a5, a6 # CHECK: encoding: [0x40,0x39,0x80] add a3, a9, a4 +# Instruction format RRR +# CHECK-INST: add a3, a9, a4 +# CHECK: encoding: [0x40,0x39,0x80] +_add a3, a9, a4 + # CHECK-INST: add a15, a9, a1 # CHECK: encoding: [0x10,0xf9,0x80] add a15, a9, sp @@ -24,6 +29,11 @@ add a15, a9, sp # CHECK: encoding: [0x82,0xc1,0x80] addi a8, sp, -128 +# Instruction format RRI8 +# CHECK-INST: addi a8, a1, -128 +# CHECK: encoding: [0x82,0xc1,0x80] +_addi a8, sp, -128 + # CHECK-INST: addi a8, a1, -12 # CHECK: encoding: [0x82,0xc1,0xf4] addi a8, a1, -12 diff --git a/llvm/test/MC/Xtensa/Core/branch.s b/llvm/test/MC/Xtensa/Core/branch.s index 66b68a610c1d25..d8e586d224591a 100644 --- a/llvm/test/MC/Xtensa/Core/branch.s +++ b/llvm/test/MC/Xtensa/Core/branch.s @@ -10,152 +10,308 @@ LBL0: # CHECK: encoding: [0x37,0x41,A] ball a1, a3, LBL0 +# Instruction format RRI8 +# CHECK-INST: ball a1, a3, LBL0 +# CHECK: encoding: [0x37,0x41,A] +_ball a1, a3, LBL0 + # Instruction format RRI8 # CHECK-INST: bany a8, a13, LBL0 # CHECK: encoding: [0xd7,0x88,A] bany a8, a13, LBL0 +# Instruction format RRI8 +# CHECK-INST: bany a8, a13, LBL0 +# CHECK: encoding: [0xd7,0x88,A] +_bany a8, a13, LBL0 + # Instruction format RRI8 # CHECK-INST: bbc a8, a7, LBL0 # CHECK: encoding: [0x77,0x58,A] bbc a8, a7, LBL0 +# Instruction format RRI8 +# CHECK-INST: bbc a8, a7, LBL0 +# CHECK: encoding: [0x77,0x58,A] +_bbc a8, a7, LBL0 + # Instruction format RRI8 # CHECK-INST: bbci a3, 16, LBL0 # CHECK: encoding: [0x07,0x73,A] bbci a3, 16, LBL0 +# Instruction format RRI8 +# CHECK-INST: bbci a3, 16, LBL0 +# CHECK: encoding: [0x07,0x73,A] +_bbci a3, 16, LBL0 + # CHECK-INST: bbci a3, 16, LBL0 # CHECK: encoding: [0x07,0x73,A] bbci a3, (16), LBL0 +# CHECK-INST: bbci a3, 16, LBL0 +# CHECK: encoding: [0x07,0x73,A] +_bbci a3, (16), LBL0 + # CHECK-INST: bbci a3, 16, LBL0 # CHECK: encoding: [0x07,0x73,A] bbci.l a3, 16, LBL0 +# CHECK-INST: bbci a3, 16, LBL0 +# CHECK: encoding: [0x07,0x73,A] +_bbci.l a3, 16, LBL0 + # Instruction format RRI8 # CHECK-INST: bbs a12, a5, LBL0 # CHECK: encoding: [0x57,0xdc,A] bbs a12, a5, LBL0 +# Instruction format RRI8 +# CHECK-INST: bbs a12, a5, LBL0 +# CHECK: encoding: [0x57,0xdc,A] +_bbs a12, a5, LBL0 + # Instruction format RRI8 # CHECK-INST: bbsi a3, 16, LBL0 # CHECK: encoding: [0x07,0xf3,A] bbsi a3, 16, LBL0 +# Instruction format RRI8 +# CHECK-INST: bbsi a3, 16, LBL0 +# CHECK: encoding: [0x07,0xf3,A] +_bbsi a3, 16, LBL0 + # CHECK-INST: bbsi a3, 16, LBL0 # CHECK: encoding: [0x07,0xf3,A] bbsi.l a3, 16, LBL0 +# CHECK-INST: bbsi a3, 16, LBL0 +# CHECK: encoding: [0x07,0xf3,A] +_bbsi.l a3, 16, LBL0 + # Instruction format RRI8 # CHECK-INST: bnall a7, a3, LBL0 # CHECK: encoding: [0x37,0xc7,A] bnall a7, a3, LBL0 +# Instruction format RRI8 +# CHECK-INST: bnall a7, a3, LBL0 +# CHECK: encoding: [0x37,0xc7,A] +_bnall a7, a3, LBL0 + # Instruction format RRI8 # CHECK-INST: bnone a2, a4, LBL0 # CHECK: encoding: [0x47,0x02,A] bnone a2, a4, LBL0 +# Instruction format RRI8 +# CHECK-INST: bnone a2, a4, LBL0 +# CHECK: encoding: [0x47,0x02,A] +_bnone a2, a4, LBL0 + # Instruction format RRI8 # CHECK-INST: beq a1, a2, LBL0 # CHECK: encoding: [0x27,0x11,A] beq a1, a2, LBL0 +# Instruction format RRI8 +# CHECK-INST: beq a1, a2, LBL0 +# CHECK: encoding: [0x27,0x11,A] +_beq a1, a2, LBL0 + # CHECK-INST: beq a11, a5, LBL0 # CHECK: encoding: [0x57,0x1b,A] beq a11, a5, LBL0 +# CHECK-INST: beq a11, a5, LBL0 +# CHECK: encoding: [0x57,0x1b,A] +_beq a11, a5, LBL0 + # Instruction format BRI8 # CHECK-INST: beqi a1, 256, LBL0 # CHECK: encoding: [0x26,0xf1,A] beqi a1, 256, LBL0 +# Instruction format BRI8 +# CHECK-INST: beqi a1, 256, LBL0 +# CHECK: encoding: [0x26,0xf1,A] +_beqi a1, 256, LBL0 + # CHECK-INST: beqi a11, -1, LBL0 # CHECK: encoding: [0x26,0x0b,A] beqi a11, -1, LBL0 +# CHECK-INST: beqi a11, -1, LBL0 +# CHECK: encoding: [0x26,0x0b,A] +_beqi a11, -1, LBL0 + # Instruction format BRI12 # CHECK-INST: beqz a8, LBL0 # CHECK: encoding: [0x16,0bAAAA1000,A] beqz a8, LBL0 +# Instruction format BRI12 +# CHECK-INST: beqz a8, LBL0 +# CHECK: encoding: [0x16,0bAAAA1000,A] +_beqz a8, LBL0 + # Instruction format RRI8 # CHECK-INST: bge a14, a2, LBL0 # CHECK: encoding: [0x27,0xae,A] bge a14, a2, LBL0 +# Instruction format RRI8 +# CHECK-INST: bge a14, a2, LBL0 +# CHECK: encoding: [0x27,0xae,A] +_bge a14, a2, LBL0 + # Instruction format BRI8 # CHECK-INST: bgei a11, -1, LBL0 # CHECK: encoding: [0xe6,0x0b,A] bgei a11, -1, LBL0 +# Instruction format BRI8 +# CHECK-INST: bgei a11, -1, LBL0 +# CHECK: encoding: [0xe6,0x0b,A] +_bgei a11, -1, LBL0 + # CHECK-INST: bgei a11, 128, LBL0 # CHECK: encoding: [0xe6,0xeb,A] bgei a11, 128, LBL0 +# CHECK-INST: bgei a11, 128, LBL0 +# CHECK: encoding: [0xe6,0xeb,A] +_bgei a11, 128, LBL0 + # Instruction format RRI8 # CHECK-INST: bgeu a14, a2, LBL0 # CHECK: encoding: [0x27,0xbe,A] bgeu a14, a2, LBL0 +# Instruction format RRI8 +# CHECK-INST: bgeu a14, a2, LBL0 +# CHECK: encoding: [0x27,0xbe,A] +_bgeu a14, a2, LBL0 + # CHECK-INST: bgeu a13, a1, LBL0 # CHECK: encoding: [0x17,0xbd,A] bgeu a13, a1, LBL0 +# CHECK-INST: bgeu a13, a1, LBL0 +# CHECK: encoding: [0x17,0xbd,A] +_bgeu a13, a1, LBL0 + # Instruction format BRI8 # CHECK-INST: bgeui a9, 32768, LBL0 # CHECK: encoding: [0xf6,0x09,A] bgeui a9, 32768, LBL0 +# Instruction format BRI8 +# CHECK-INST: bgeui a9, 32768, LBL0 +# CHECK: encoding: [0xf6,0x09,A] +_bgeui a9, 32768, LBL0 + # CHECK-INST: bgeui a7, 65536, LBL0 # CHECK: encoding: [0xf6,0x17,A] bgeui a7, 65536, LBL0 +# CHECK-INST: bgeui a7, 65536, LBL0 +# CHECK: encoding: [0xf6,0x17,A] +_bgeui a7, 65536, LBL0 + # CHECK-INST: bgeui a7, 64, LBL0 # CHECK: encoding: [0xf6,0xd7,A] bgeui a7, 64, LBL0 +# CHECK-INST: bgeui a7, 64, LBL0 +# CHECK: encoding: [0xf6,0xd7,A] +_bgeui a7, 64, LBL0 + # Instruction format BRI12 # CHECK-INST: bgez a8, LBL0 # CHECK: encoding: [0xd6,0bAAAA1000,A] bgez a8, LBL0 +# Instruction format BRI12 +# CHECK-INST: bgez a8, LBL0 +# CHECK: encoding: [0xd6,0bAAAA1000,A] +_bgez a8, LBL0 + # Instruction format RRI8 # CHECK-INST: blt a14, a2, LBL0 # CHECK: encoding: [0x27,0x2e,A] blt a14, a2, LBL0 +# Instruction format RRI8 +# CHECK-INST: blt a14, a2, LBL0 +# CHECK: encoding: [0x27,0x2e,A] +_blt a14, a2, LBL0 + # Instruction format BRI8 # CHECK-INST: blti a12, -1, LBL0 # CHECK: encoding: [0xa6,0x0c,A] blti a12, -1, LBL0 +# Instruction format BRI8 +# CHECK-INST: blti a12, -1, LBL0 +# CHECK: encoding: [0xa6,0x0c,A] +_blti a12, -1, LBL0 + # CHECK-INST: blti a0, 32, LBL0 # CHECK: encoding: [0xa6,0xc0,A] blti a0, 32, LBL0 +# CHECK-INST: blti a0, 32, LBL0 +# CHECK: encoding: [0xa6,0xc0,A] +_blti a0, 32, LBL0 + # Instruction format BRI8 # CHECK-INST: bltui a7, 16, LBL0 # CHECK: encoding: [0xb6,0xb7,A] bltui a7, 16, LBL0 +# Instruction format BRI8 +# CHECK-INST: bltui a7, 16, LBL0 +# CHECK: encoding: [0xb6,0xb7,A] +_bltui a7, 16, LBL0 + # Instruction format BRI12 # CHECK-INST: bltz a6, LBL0 # CHECK: encoding: [0x96,0bAAAA0110,A] bltz a6, LBL0 +# Instruction format BRI12 +# CHECK-INST: bltz a6, LBL0 +# CHECK: encoding: [0x96,0bAAAA0110,A] +_bltz a6, LBL0 + # Instruction format RRI8 # CHECK-INST: bne a3, a4, LBL0 # CHECK: encoding: [0x47,0x93,A] bne a3, a4, LBL0 +# Instruction format RRI8 +# CHECK-INST: bne a3, a4, LBL0 +# CHECK: encoding: [0x47,0x93,A] +_bne a3, a4, LBL0 + # Instruction format BRI8 # CHECK-INST: bnei a5, 12, LBL0 # CHECK: encoding: [0x66,0xa5,A] bnei a5, 12, LBL0 +# Instruction format BRI8 +# CHECK-INST: bnei a5, 12, LBL0 +# CHECK: encoding: [0x66,0xa5,A] +_bnei a5, 12, LBL0 + # Instruction format BRI12 # CHECK-INST: bnez a5, LBL0 # CHECK: encoding: [0x56,0bAAAA0101,A] bnez a5, LBL0 + +# Instruction format BRI12 +# CHECK-INST: bnez a5, LBL0 +# CHECK: encoding: [0x56,0bAAAA0101,A] +_bnez a5, LBL0 + diff --git a/llvm/test/MC/Xtensa/Core/invalid.s b/llvm/test/MC/Xtensa/Core/invalid.s index b36f3509ea9bc9..b8701e147dc066 100644 --- a/llvm/test/MC/Xtensa/Core/invalid.s +++ b/llvm/test/MC/Xtensa/Core/invalid.s @@ -17,8 +17,8 @@ addmi a1, a2, 33 # CHECK: :[[#@LINE-1]]:15: error: expected immediate in range [-32768, 32512], first 8 bits should be zero # shimm1_31 -slli a1, a2, 0 -# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [1, 31] +_slli a1, a2, 0 +# CHECK: :[[#@LINE-1]]:15: error: expected immediate in range [1, 31] # uimm4 _srli a1, a2, 16 @@ -122,3 +122,6 @@ bltui 16, a7, LBL0 # CHECK: :[[#@LINE-1]]:7: error: invalid operand for instruction bltui a7, LBL0, 16 # CHECK: :[[#@LINE-1]]:19: error: unknown operand + +_movi a1, -2059 +# CHECK: :[[#@LINE-1]]:11: error: expected immediate in range [-2048, 2047] \ No newline at end of file diff --git a/llvm/test/MC/Xtensa/Core/memory.s b/llvm/test/MC/Xtensa/Core/memory.s index 1e5a4578283315..876fe5871d6728 100644 --- a/llvm/test/MC/Xtensa/Core/memory.s +++ b/llvm/test/MC/Xtensa/Core/memory.s @@ -25,6 +25,11 @@ l16ui a4, sp, 6 # CHECK: encoding: [0x52,0x21,0x02] l32i a5, sp, 8 +# Instruction format RRI8 +# CHECK-INST: l32i a5, a1, 8 +# CHECK: encoding: [0x52,0x21,0x08] +_l32i a5, sp, 8 + # Instruction format RRI8 # CHECK-INST: s8i a2, a1, 3 # CHECK: encoding: [0x22,0x41,0x03] @@ -39,3 +44,8 @@ s16i a3, sp, 4 # CHECK-INST: s32i a5, a1, 8 # CHECK: encoding: [0x52,0x61,0x02] s32i a5, sp, 8 + +# Instruction format RRI8 +# CHECK-INST: s32i a5, a1, 8 +# CHECK: encoding: [0x52,0x61,0x08] +_s32i a5, sp, 8 diff --git a/llvm/test/MC/Xtensa/Core/shift.s b/llvm/test/MC/Xtensa/Core/shift.s index fbe00dc107d800..21c0e11b10366f 100644 --- a/llvm/test/MC/Xtensa/Core/shift.s +++ b/llvm/test/MC/Xtensa/Core/shift.s @@ -20,6 +20,11 @@ sll a10, a11 # CHECK: encoding: [0x10,0x51,0x11] slli a5, a1, 15 +# Instruction format RRR +# CHECK-INST: or a5, a1, a1 +# CHECK: encoding: [0x10,0x51,0x20] +slli a5, a1, 0 + # Instruction format RRR # CHECK-INST: sra a12, a3 # CHECK: encoding: [0x30,0xc0,0xb1] From e9c8e60ee8d58e21a7f3582a4695eeb99ec4c5d7 Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Wed, 22 May 2024 10:34:20 +0200 Subject: [PATCH 255/261] [RISCV] Support for ESP32-P4 instructions in RISCV backend --- .gitignore | 1 + .gitlab-ci.yml | 26 +- clang/include/clang/Basic/BuiltinsRISCV.def | 2 + .../clang/Basic/BuiltinsRISCVESP32P4.def | 354 + clang/test/CodeGen/RISCV/riscv-esp32p4.c | 1027 + clang/test/Misc/target-invalid-cpu-note.c | 4 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 4 + .../include/llvm/IR/IntrinsicsRISCVESP32P4.td | 1065 ++ llvm/lib/Support/RISCVISAInfo.cpp | 1 + .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 97 + llvm/lib/Target/RISCV/CMakeLists.txt | 1 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 153 + .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 3 + .../RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 116 + .../RISCV/MCTargetDesc/RISCVInstPrinter.h | 20 + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 187 +- .../Target/RISCV/RISCVESP32P4ISelLowering.cpp | 8468 +++++++++ llvm/lib/Target/RISCV/RISCVESP32P4Operands.td | 134 + llvm/lib/Target/RISCV/RISCVFeatures.td | 3 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 14 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 + .../Target/RISCV/RISCVInstrFormatsESP32P4.td | 42 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 6 + llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 + .../lib/Target/RISCV/RISCVInstrInfoESP32P4.td | 15603 ++++++++++++++++ llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td | 172 + llvm/lib/Target/RISCV/RISCVProcessors.td | 14 + llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 21 + llvm/test/CodeGen/RISCV/esp32p4.ll | 1289 ++ llvm/test/MC/RISCV/esp32p4-hwlp-valid.s | 22 + llvm/test/MC/RISCV/esp32p4-valid.s | 710 + llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s | 2 +- llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 + llvm/utils/TableGen/AsmMatcherEmitter.cpp | 5 +- 34 files changed, 29564 insertions(+), 8 deletions(-) create mode 100644 clang/include/clang/Basic/BuiltinsRISCVESP32P4.def create mode 100644 clang/test/CodeGen/RISCV/riscv-esp32p4.c create mode 100644 llvm/include/llvm/IR/IntrinsicsRISCVESP32P4.td create mode 100644 llvm/lib/Target/RISCV/RISCVESP32P4ISelLowering.cpp create mode 100644 llvm/lib/Target/RISCV/RISCVESP32P4Operands.td create mode 100644 llvm/lib/Target/RISCV/RISCVInstrFormatsESP32P4.td create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoESP32P4.td create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td create mode 100644 llvm/test/CodeGen/RISCV/esp32p4.ll create mode 100644 llvm/test/MC/RISCV/esp32p4-hwlp-valid.s create mode 100644 llvm/test/MC/RISCV/esp32p4-valid.s diff --git a/.gitignore b/.gitignore index 0e13e978416184..1315ce235e6550 100644 --- a/.gitignore +++ b/.gitignore @@ -73,3 +73,4 @@ pythonenv* /clang/utils/analyzer/projects/*/RefScanBuildResults # automodapi puts generated documentation files here. /lldb/docs/python_api/ +/dbg diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b28cf30282426d..d38b3dc5fd3660 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -186,7 +186,7 @@ build_and_test: [ ! -f "${BUILD_DIR}/lld-tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/lld-tests.log || true fi script: - - BUILD_PATH=$PWD/${BUILD_DIR} + - export BUILD_PATH=$PWD/${BUILD_DIR} - mkdir -p ${BUILD_PATH} - cmake -G Ninja -S llvm @@ -209,6 +209,29 @@ build_and_test: - runuser -u test_runner -- ninja -C ${BUILD_PATH} check-lld 2>&1 > ${BUILD_PATH}/lld-tests.log; - chown -R ${CUR_USER} ${BUILD_PATH}; +test_xesppie: + stage: test + dependencies: + - pack_x86_64-linux-gnu + when: manual + allow_failure: true + only: + - tags + script: + - cd ${DIST_DIR}/ + - ls -l + - DISTRO_PACK_FILE=$(cat dist_name_x86_64-linux-gnu) + - tar -xf ${DISTRO_PACK_FILE} + - ls -l + - cd esp-clang + - ls -l + - pwd + - export CC="$(pwd)/bin/clang" + - export OBJDUMP="$(pwd)/bin/llvm-objdump" + - git clone -q --depth=1 "${GITLAB_SSH_SERVER}/idf/esp-compiler-tests.git" + - cd esp-compiler-tests/build-only/xesppie + - ./test_xesppie.py + .build_linux-gnu_template: extends: .build_toolchain_template variables: @@ -441,6 +464,7 @@ upload_to_github: - job: pack_x86_64-w64-mingw32 - job: sign_x86_64-apple-darwin - job: sign_aarch64-apple-darwin + - job: test_xesppie before_script: [] script: - ls -l ${DIST_DIR} diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def index 1528b18c82eade..f295c266b0a9b6 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -89,5 +89,7 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh") TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl") TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl") +#include "clang/Basic/BuiltinsRISCVESP32P4.def" + #undef BUILTIN #undef TARGET_BUILTIN diff --git a/clang/include/clang/Basic/BuiltinsRISCVESP32P4.def b/clang/include/clang/Basic/BuiltinsRISCVESP32P4.def new file mode 100644 index 00000000000000..f9c9eab176845e --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsRISCVESP32P4.def @@ -0,0 +1,354 @@ +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s16_qacc_h, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s16_qacc_h_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s16_qacc_h_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s16_qacc_l, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s16_qacc_l_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s16_qacc_l_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s8_qacc_h, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s8_qacc_h_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s8_qacc_h_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s8_qacc_l, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s8_qacc_l_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmulas_s8_qacc_l_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_qacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_qacc_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_qacc_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_qacc_st_ip, "vUiUiUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_qacc_st_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_xacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_xacc_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_xacc_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_xacc_st_ip, "vUiUiUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_xacc_st_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_qacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_qacc_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_qacc_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_qacc_st_ip, "vUiUiUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_qacc_st_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_xacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_xacc_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_xacc_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_xacc_st_ip, "vUiUiUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_xacc_st_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_qacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_qacc_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_qacc_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_qacc_st_ip, "vUiUiUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_qacc_st_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_xacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_xacc_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_xacc_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_xacc_st_ip, "vUiUiUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_xacc_st_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_qacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_qacc_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_qacc_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_qacc_st_ip, "vUiUiUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_qacc_st_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_xacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_xacc_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_xacc_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_xacc_st_ip, "vUiUiUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_xacc_st_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s16_qacc_ldbc_incp, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_s8_qacc_ldbc_incp, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u16_qacc_ldbc_incp, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmulas_u8_qacc_ldbc_incp, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsmulas_s16_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsmulas_s16_qacc_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsmulas_s8_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsmulas_s8_qacc_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsmulas_u16_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsmulas_u16_qacc_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsmulas_u8_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsmulas_u8_qacc_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_s16, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_s16_ld_incp, "vUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_s16_st_incp, "vUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_s8, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_s8_ld_incp, "vUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_s8_st_incp, "vUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_u16, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_u16_ld_incp, "vUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_u16_st_incp, "vUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_u8, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_u8_ld_incp, "vUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_cmul_u8_st_incp, "vUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_max_s16_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_max_s32_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_max_s8_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_max_u16_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_max_u32_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_max_u8_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_min_s16_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_min_s32_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_min_s8_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_min_u16_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_min_u32_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_min_u8_a, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vabs_16, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vabs_32, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vabs_8, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s32_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s32_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_s8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u32_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u32_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vadd_u8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vclamp_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s32_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s32_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_s8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u32_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u32_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmax_u8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s32_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s32_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_s8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u32_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u32_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmin_u8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_s16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_s16_s8xs8, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_s16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_s32_s16xs16, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_s8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_s8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_u16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_u16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_u8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vmul_u8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vprelu_s16, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vprelu_s8, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vrelu_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vrelu_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsadds_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsadds_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsadds_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsadds_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsat_s16, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsat_s32, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsat_s8, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsat_u16, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsat_u32, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsat_u8, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vssubs_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vssubs_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vssubs_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vssubs_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s32_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s32_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_s8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u16_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u32_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u32_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u8_ld_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsub_u8_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_addx2, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_addx4, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_sat, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_subx2, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_subx4, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_andq, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_notq, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_orq, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_xorq, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_eq_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_eq_s32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_eq_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_eq_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_eq_u32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_eq_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_gt_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_gt_s32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_gt_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_gt_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_gt_u32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_gt_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_lt_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_lt_s32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_lt_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_lt_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_lt_u32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vcmp_lt_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_mov_s16_qacc, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_mov_s8_qacc, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_mov_u16_qacc, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_mov_u8_qacc, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movi_16_a, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movi_16_q, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movi_32_a, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movi_32_q, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movi_8_a, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movi_8_q, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_r_cfg, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_r_fft_bit_width, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_r_perf, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_r_sar, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_r_sar_bytes, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_r_xacc_h, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_r_xacc_l, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_w_cfg, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_w_fft_bit_width, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_w_perf, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_w_sar, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_w_sar_bytes, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_w_xacc_h, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_movx_w_xacc_l, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vext_s16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vext_s8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vext_u16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vext_u8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vunzip_16, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vunzip_32, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vunzip_8, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vunzipt_16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vunzipt_8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vzip_16, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vzip_32, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vzip_8, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vzipt_16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vzipt_8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_zero_q, "vUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_zero_qacc, "v", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_zero_xacc, "v", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_ams_s16_ld_incp, "vUiUiUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_ams_s16_ld_incp_uaup, "vUiUiUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_ams_s16_ld_r32_decp, "vUiUiUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_ams_s16_st_incp, "vUiUiUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_bitrev, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_cmul_s16_ld_xp, "vUiUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_cmul_s16_st_xp, "vUiUiUiUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_r2bf_s16, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_r2bf_s16_st_incp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_fft_vst_r32_decp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ld_128_usar_ip, "vUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ld_128_usar_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ld_xacc_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldqa_s16_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldqa_s16_128_xp, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldqa_s8_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldqa_s8_128_xp, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldqa_u16_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldqa_u16_128_xp, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldqa_u8_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldqa_u8_128_xp, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldbc_16_ip, "vUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldbc_16_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldbc_32_ip, "vUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldbc_32_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldbc_8_ip, "vUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldbc_8_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldext_s16_ip, "vUiIiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldext_s16_xp, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldext_s8_ip, "vUiIiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldext_s8_xp, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldext_u16_ip, "vUiIiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldext_u16_xp, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldext_u8_ip, "vUiIiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldext_u8_xp, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vldhbc_16_incp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ld_qacc_h_h_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ld_qacc_h_l_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ld_qacc_l_h_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ld_qacc_l_l_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ld_ua_state_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_ldxq_32, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_st_qacc_h_h_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_st_qacc_h_l_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_st_qacc_l_h_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_st_qacc_l_l_128_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_st_ua_state_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_stxq_32, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vld_128_ip, "vUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vld_128_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vld_h_64_ip, "vUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vld_h_64_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vld_l_64_ip, "vUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vld_l_64_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vst_128_ip, "vUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vst_128_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vst_h_64_ip, "vUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vst_h_64_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vst_l_64_ip, "vUiUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vst_l_64_xp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_slci_2q, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_slcxxp_2q, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_src_q, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_src_q_ld_ip, "vUiUiUiIiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_src_q_ld_xp, "vUiUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_src_q_qup, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srci_2q, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcmb_s16_q_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcmb_s16_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcmb_s8_q_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcmb_s8_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcmb_u16_q_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcmb_u16_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcmb_u8_q_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcmb_u8_qacc, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcq_128_st_incp, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srcxxp_2q, "vUiUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srs_s_xacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_srs_u_xacc, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsl_32, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsld_16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsld_32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsld_8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsr_s32, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsr_u32, "vUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsrd_16, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsrd_32, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_vsrd_8, "vUiUiUi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_st_s_xacc_ip, "vUiIi", "n", "xesppie") +TARGET_BUILTIN(__builtin_riscv_esp_st_u_xacc_ip, "vUiIi", "n", "xesppie") diff --git a/clang/test/CodeGen/RISCV/riscv-esp32p4.c b/clang/test/CodeGen/RISCV/riscv-esp32p4.c new file mode 100644 index 00000000000000..679ca00968b03c --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv-esp32p4.c @@ -0,0 +1,1027 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +xesppie -S -emit-llvm -O0 -o - %s \ +// RUN: | FileCheck %s + +#include + +// CHECK-LABEL: @test( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DATA:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 10, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s16.qacc.h(i32 4, i32 2) +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s16.qacc.h.ld.ip(i32 4, i32 0, i32 [[TMP0]], i32 -96, i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s16.qacc.h.ld.xp(i32 [[TMP1]], i32 5, i32 5, i32 [[TMP2]], i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s16.qacc.l(i32 6, i32 1) +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s16.qacc.l.ld.ip(i32 2, i32 3, i32 [[TMP3]], i32 -48, i32 3) +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s16.qacc.l.ld.xp(i32 [[TMP4]], i32 7, i32 2, i32 [[TMP5]], i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s8.qacc.h(i32 4, i32 4) +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s8.qacc.h.ld.ip(i32 7, i32 4, i32 [[TMP6]], i32 -128, i32 4) +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s8.qacc.h.ld.xp(i32 [[TMP7]], i32 2, i32 3, i32 [[TMP8]], i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s8.qacc.l(i32 6, i32 4) +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s8.qacc.l.ld.ip(i32 5, i32 5, i32 [[TMP9]], i32 16, i32 7) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vcmulas.s8.qacc.l.ld.xp(i32 [[TMP10]], i32 4, i32 4, i32 [[TMP11]], i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.qacc(i32 7, i32 6) +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.qacc.ld.ip(i32 0, i32 4, i32 [[TMP12]], i32 96, i32 4) +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.qacc.ld.xp(i32 [[TMP13]], i32 4, i32 4, i32 [[TMP14]], i32 7) +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.qacc.st.ip(i32 2, i32 1, i32 7, i32 [[TMP15]], i32 -128) +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.qacc.st.xp(i32 [[TMP16]], i32 1, i32 2, i32 6, i32 [[TMP17]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.xacc(i32 1, i32 3) +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.xacc.ld.ip(i32 7, i32 3, i32 [[TMP18]], i32 -96, i32 5) +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.xacc.ld.xp(i32 [[TMP19]], i32 3, i32 1, i32 [[TMP20]], i32 1) +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.xacc.st.ip(i32 2, i32 0, i32 0, i32 [[TMP21]], i32 64) +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.xacc.st.xp(i32 [[TMP22]], i32 6, i32 3, i32 6, i32 [[TMP23]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.qacc(i32 0, i32 0) +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.qacc.ld.ip(i32 0, i32 3, i32 [[TMP24]], i32 0, i32 7) +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.qacc.ld.xp(i32 [[TMP25]], i32 4, i32 3, i32 [[TMP26]], i32 4) +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.qacc.st.ip(i32 3, i32 3, i32 5, i32 [[TMP27]], i32 -64) +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.qacc.st.xp(i32 [[TMP28]], i32 4, i32 7, i32 0, i32 [[TMP29]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.xacc(i32 3, i32 3) +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.xacc.ld.ip(i32 3, i32 2, i32 [[TMP30]], i32 0, i32 5) +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.xacc.ld.xp(i32 [[TMP31]], i32 6, i32 3, i32 [[TMP32]], i32 0) +// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.xacc.st.ip(i32 1, i32 7, i32 7, i32 [[TMP33]], i32 -32) +// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.xacc.st.xp(i32 [[TMP34]], i32 6, i32 7, i32 6, i32 [[TMP35]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.qacc(i32 5, i32 4) +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.qacc.ld.ip(i32 5, i32 2, i32 [[TMP36]], i32 64, i32 6) +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.qacc.ld.xp(i32 [[TMP37]], i32 5, i32 7, i32 [[TMP38]], i32 7) +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.qacc.st.ip(i32 1, i32 4, i32 3, i32 [[TMP39]], i32 -96) +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.qacc.st.xp(i32 [[TMP40]], i32 5, i32 0, i32 2, i32 [[TMP41]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.xacc(i32 0, i32 7) +// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.xacc.ld.ip(i32 6, i32 6, i32 [[TMP42]], i32 -96, i32 4) +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.xacc.ld.xp(i32 [[TMP43]], i32 6, i32 5, i32 [[TMP44]], i32 6) +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.xacc.st.ip(i32 3, i32 0, i32 4, i32 [[TMP45]], i32 64) +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.xacc.st.xp(i32 [[TMP46]], i32 1, i32 0, i32 4, i32 [[TMP47]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.qacc(i32 5, i32 4) +// CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.qacc.ld.ip(i32 5, i32 3, i32 [[TMP48]], i32 80, i32 5) +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.qacc.ld.xp(i32 [[TMP49]], i32 4, i32 7, i32 [[TMP50]], i32 4) +// CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.qacc.st.ip(i32 3, i32 3, i32 5, i32 [[TMP51]], i32 -96) +// CHECK-NEXT: [[TMP52:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.qacc.st.xp(i32 [[TMP52]], i32 6, i32 7, i32 3, i32 [[TMP53]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.xacc(i32 0, i32 1) +// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.xacc.ld.ip(i32 6, i32 0, i32 [[TMP54]], i32 -32, i32 7) +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.xacc.ld.xp(i32 [[TMP55]], i32 3, i32 3, i32 [[TMP56]], i32 5) +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.xacc.st.ip(i32 7, i32 0, i32 4, i32 [[TMP57]], i32 32) +// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP59:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.xacc.st.xp(i32 [[TMP58]], i32 1, i32 0, i32 0, i32 [[TMP59]]) +// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s16.qacc.ldbc.incp(i32 3, i32 6, i32 [[TMP60]], i32 7) +// CHECK-NEXT: [[TMP61:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.s8.qacc.ldbc.incp(i32 5, i32 3, i32 [[TMP61]], i32 6) +// CHECK-NEXT: [[TMP62:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u16.qacc.ldbc.incp(i32 0, i32 3, i32 [[TMP62]], i32 2) +// CHECK-NEXT: [[TMP63:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmulas.u8.qacc.ldbc.incp(i32 4, i32 7, i32 [[TMP63]], i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vsmulas.s16.qacc(i32 7, i32 7, i32 4) +// CHECK-NEXT: [[TMP64:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsmulas.s16.qacc.ld.incp(i32 7, i32 7, i32 [[TMP64]], i32 4, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vsmulas.s8.qacc(i32 7, i32 0, i32 7) +// CHECK-NEXT: [[TMP65:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsmulas.s8.qacc.ld.incp(i32 5, i32 6, i32 [[TMP65]], i32 15, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vsmulas.u16.qacc(i32 7, i32 0, i32 10) +// CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsmulas.u16.qacc.ld.incp(i32 7, i32 6, i32 [[TMP66]], i32 1, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.vsmulas.u8.qacc(i32 3, i32 6, i32 5) +// CHECK-NEXT: [[TMP67:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsmulas.u8.qacc.ld.incp(i32 6, i32 1, i32 [[TMP67]], i32 4, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.s16(i32 2, i32 1, i32 3, i32 1) +// CHECK-NEXT: [[TMP68:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.s16.ld.incp(i32 2, i32 7, i32 [[TMP68]], i32 0, i32 5, i32 0) +// CHECK-NEXT: [[TMP69:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.s16.st.incp(i32 7, i32 4, i32 6, i32 [[TMP69]], i32 2, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.s8(i32 5, i32 7, i32 2, i32 4) +// CHECK-NEXT: [[TMP70:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.s8.ld.incp(i32 0, i32 6, i32 [[TMP70]], i32 2, i32 7, i32 5) +// CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.s8.st.incp(i32 1, i32 6, i32 5, i32 [[TMP71]], i32 0, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.u16(i32 7, i32 4, i32 0, i32 0) +// CHECK-NEXT: [[TMP72:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.u16.ld.incp(i32 2, i32 0, i32 [[TMP72]], i32 3, i32 1, i32 1) +// CHECK-NEXT: [[TMP73:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.u16.st.incp(i32 4, i32 3, i32 4, i32 [[TMP73]], i32 1, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.u8(i32 3, i32 4, i32 1, i32 5) +// CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.u8.ld.incp(i32 5, i32 0, i32 [[TMP74]], i32 1, i32 5, i32 1) +// CHECK-NEXT: [[TMP75:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.cmul.u8.st.incp(i32 2, i32 7, i32 4, i32 [[TMP75]], i32 3, i32 1) +// CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.max.s16.a(i32 2, i32 [[TMP76]]) +// CHECK-NEXT: [[TMP77:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.max.s32.a(i32 0, i32 [[TMP77]]) +// CHECK-NEXT: [[TMP78:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.max.s8.a(i32 7, i32 [[TMP78]]) +// CHECK-NEXT: [[TMP79:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.max.u16.a(i32 4, i32 [[TMP79]]) +// CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.max.u32.a(i32 4, i32 [[TMP80]]) +// CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.max.u8.a(i32 3, i32 [[TMP81]]) +// CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.min.s16.a(i32 0, i32 [[TMP82]]) +// CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.min.s32.a(i32 7, i32 [[TMP83]]) +// CHECK-NEXT: [[TMP84:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.min.s8.a(i32 4, i32 [[TMP84]]) +// CHECK-NEXT: [[TMP85:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.min.u16.a(i32 7, i32 [[TMP85]]) +// CHECK-NEXT: [[TMP86:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.min.u32.a(i32 6, i32 [[TMP86]]) +// CHECK-NEXT: [[TMP87:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.min.u8.a(i32 1, i32 [[TMP87]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vabs.16(i32 7, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.vabs.32(i32 0, i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vabs.8(i32 5, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s16(i32 0, i32 4, i32 0) +// CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s16.ld.incp(i32 4, i32 2, i32 [[TMP88]], i32 0, i32 7) +// CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s16.st.incp(i32 5, i32 7, i32 0, i32 [[TMP89]], i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s32(i32 6, i32 5, i32 0) +// CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s32.ld.incp(i32 5, i32 6, i32 [[TMP90]], i32 0, i32 2) +// CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s32.st.incp(i32 7, i32 7, i32 0, i32 [[TMP91]], i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s8(i32 6, i32 5, i32 5) +// CHECK-NEXT: [[TMP92:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s8.ld.incp(i32 2, i32 4, i32 [[TMP92]], i32 6, i32 7) +// CHECK-NEXT: [[TMP93:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.s8.st.incp(i32 4, i32 6, i32 4, i32 [[TMP93]], i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u16(i32 0, i32 6, i32 5) +// CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u16.ld.incp(i32 6, i32 7, i32 [[TMP94]], i32 5, i32 1) +// CHECK-NEXT: [[TMP95:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u16.st.incp(i32 1, i32 3, i32 4, i32 [[TMP95]], i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u32(i32 7, i32 3, i32 0) +// CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u32.ld.incp(i32 0, i32 4, i32 [[TMP96]], i32 5, i32 5) +// CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u32.st.incp(i32 1, i32 5, i32 6, i32 [[TMP97]], i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u8(i32 0, i32 1, i32 5) +// CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u8.ld.incp(i32 5, i32 1, i32 [[TMP98]], i32 2, i32 6) +// CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vadd.u8.st.incp(i32 1, i32 7, i32 4, i32 [[TMP99]], i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vclamp.s16(i32 3, i32 12, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s16(i32 1, i32 2, i32 2) +// CHECK-NEXT: [[TMP100:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s16.ld.incp(i32 3, i32 0, i32 [[TMP100]], i32 5, i32 1) +// CHECK-NEXT: [[TMP101:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s16.st.incp(i32 0, i32 4, i32 2, i32 [[TMP101]], i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s32(i32 0, i32 2, i32 4) +// CHECK-NEXT: [[TMP102:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s32.ld.incp(i32 3, i32 5, i32 [[TMP102]], i32 3, i32 6) +// CHECK-NEXT: [[TMP103:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s32.st.incp(i32 6, i32 0, i32 7, i32 [[TMP103]], i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s8(i32 1, i32 0, i32 3) +// CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s8.ld.incp(i32 1, i32 6, i32 [[TMP104]], i32 6, i32 6) +// CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.s8.st.incp(i32 2, i32 7, i32 1, i32 [[TMP105]], i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u16(i32 6, i32 6, i32 3) +// CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u16.ld.incp(i32 5, i32 2, i32 [[TMP106]], i32 2, i32 1) +// CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u16.st.incp(i32 3, i32 6, i32 2, i32 [[TMP107]], i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u32(i32 2, i32 3, i32 3) +// CHECK-NEXT: [[TMP108:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u32.ld.incp(i32 1, i32 4, i32 [[TMP108]], i32 5, i32 5) +// CHECK-NEXT: [[TMP109:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u32.st.incp(i32 4, i32 2, i32 1, i32 [[TMP109]], i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u8(i32 7, i32 0, i32 4) +// CHECK-NEXT: [[TMP110:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u8.ld.incp(i32 1, i32 5, i32 [[TMP110]], i32 4, i32 7) +// CHECK-NEXT: [[TMP111:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmax.u8.st.incp(i32 1, i32 2, i32 5, i32 [[TMP111]], i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s16(i32 5, i32 1, i32 7) +// CHECK-NEXT: [[TMP112:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s16.ld.incp(i32 7, i32 6, i32 [[TMP112]], i32 6, i32 4) +// CHECK-NEXT: [[TMP113:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s16.st.incp(i32 7, i32 0, i32 6, i32 [[TMP113]], i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s32(i32 7, i32 4, i32 7) +// CHECK-NEXT: [[TMP114:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s32.ld.incp(i32 0, i32 1, i32 [[TMP114]], i32 5, i32 4) +// CHECK-NEXT: [[TMP115:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s32.st.incp(i32 1, i32 6, i32 7, i32 [[TMP115]], i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s8(i32 5, i32 6, i32 4) +// CHECK-NEXT: [[TMP116:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s8.ld.incp(i32 1, i32 6, i32 [[TMP116]], i32 6, i32 5) +// CHECK-NEXT: [[TMP117:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.s8.st.incp(i32 7, i32 7, i32 6, i32 [[TMP117]], i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u16(i32 7, i32 1, i32 1) +// CHECK-NEXT: [[TMP118:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u16.ld.incp(i32 6, i32 0, i32 [[TMP118]], i32 3, i32 0) +// CHECK-NEXT: [[TMP119:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u16.st.incp(i32 0, i32 7, i32 5, i32 [[TMP119]], i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u32(i32 6, i32 5, i32 0) +// CHECK-NEXT: [[TMP120:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u32.ld.incp(i32 3, i32 7, i32 [[TMP120]], i32 1, i32 4) +// CHECK-NEXT: [[TMP121:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u32.st.incp(i32 1, i32 0, i32 2, i32 [[TMP121]], i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u8(i32 2, i32 0, i32 7) +// CHECK-NEXT: [[TMP122:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u8.ld.incp(i32 4, i32 2, i32 [[TMP122]], i32 4, i32 3) +// CHECK-NEXT: [[TMP123:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmin.u8.st.incp(i32 1, i32 7, i32 4, i32 [[TMP123]], i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.s16(i32 7, i32 5, i32 3) +// CHECK-NEXT: [[TMP124:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.s16.ld.incp(i32 5, i32 4, i32 [[TMP124]], i32 1, i32 6) +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.s16.s8xs8(i32 7, i32 6, i32 4, i32 4) +// CHECK-NEXT: [[TMP125:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.s16.st.incp(i32 0, i32 1, i32 5, i32 [[TMP125]], i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.s32.s16xs16(i32 5, i32 3, i32 1, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.s8(i32 1, i32 6, i32 0) +// CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.s8.ld.incp(i32 2, i32 1, i32 [[TMP126]], i32 6, i32 5) +// CHECK-NEXT: [[TMP127:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.s8.st.incp(i32 5, i32 2, i32 1, i32 [[TMP127]], i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.u16(i32 7, i32 3, i32 6) +// CHECK-NEXT: [[TMP128:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.u16.ld.incp(i32 3, i32 3, i32 [[TMP128]], i32 2, i32 0) +// CHECK-NEXT: [[TMP129:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.u16.st.incp(i32 6, i32 5, i32 0, i32 [[TMP129]], i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.u8(i32 2, i32 2, i32 7) +// CHECK-NEXT: [[TMP130:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.u8.ld.incp(i32 1, i32 1, i32 [[TMP130]], i32 6, i32 7) +// CHECK-NEXT: [[TMP131:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vmul.u8.st.incp(i32 5, i32 0, i32 6, i32 [[TMP131]], i32 2) +// CHECK-NEXT: [[TMP132:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vprelu.s16(i32 [[TMP132]], i32 0, i32 7, i32 3) +// CHECK-NEXT: [[TMP133:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vprelu.s8(i32 [[TMP133]], i32 6, i32 6, i32 6) +// CHECK-NEXT: [[TMP134:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP135:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vrelu.s16(i32 [[TMP134]], i32 [[TMP135]], i32 3) +// CHECK-NEXT: [[TMP136:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP137:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vrelu.s8(i32 [[TMP136]], i32 [[TMP137]], i32 7) +// CHECK-NEXT: [[TMP138:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsadds.s16(i32 [[TMP138]], i32 5, i32 4) +// CHECK-NEXT: [[TMP139:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsadds.s8(i32 [[TMP139]], i32 6, i32 6) +// CHECK-NEXT: [[TMP140:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsadds.u16(i32 [[TMP140]], i32 7, i32 2) +// CHECK-NEXT: [[TMP141:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsadds.u8(i32 [[TMP141]], i32 2, i32 0) +// CHECK-NEXT: [[TMP142:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP143:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsat.s16(i32 [[TMP142]], i32 [[TMP143]], i32 7, i32 5) +// CHECK-NEXT: [[TMP144:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP145:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsat.s32(i32 [[TMP144]], i32 [[TMP145]], i32 2, i32 5) +// CHECK-NEXT: [[TMP146:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP147:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsat.s8(i32 [[TMP146]], i32 [[TMP147]], i32 2, i32 5) +// CHECK-NEXT: [[TMP148:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP149:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsat.u16(i32 [[TMP148]], i32 [[TMP149]], i32 0, i32 2) +// CHECK-NEXT: [[TMP150:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP151:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsat.u32(i32 [[TMP150]], i32 [[TMP151]], i32 4, i32 2) +// CHECK-NEXT: [[TMP152:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP153:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsat.u8(i32 [[TMP152]], i32 [[TMP153]], i32 0, i32 2) +// CHECK-NEXT: [[TMP154:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vssubs.s16(i32 [[TMP154]], i32 3, i32 6) +// CHECK-NEXT: [[TMP155:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vssubs.s8(i32 [[TMP155]], i32 5, i32 5) +// CHECK-NEXT: [[TMP156:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vssubs.u16(i32 [[TMP156]], i32 6, i32 3) +// CHECK-NEXT: [[TMP157:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vssubs.u8(i32 [[TMP157]], i32 0, i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s16(i32 0, i32 5, i32 3) +// CHECK-NEXT: [[TMP158:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s16.ld.incp(i32 0, i32 1, i32 [[TMP158]], i32 5, i32 3) +// CHECK-NEXT: [[TMP159:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s16.st.incp(i32 5, i32 7, i32 7, i32 [[TMP159]], i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s32(i32 3, i32 0, i32 3) +// CHECK-NEXT: [[TMP160:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s32.ld.incp(i32 1, i32 2, i32 [[TMP160]], i32 0, i32 2) +// CHECK-NEXT: [[TMP161:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s32.st.incp(i32 4, i32 0, i32 0, i32 [[TMP161]], i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s8(i32 4, i32 1, i32 3) +// CHECK-NEXT: [[TMP162:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s8.ld.incp(i32 3, i32 7, i32 [[TMP162]], i32 3, i32 5) +// CHECK-NEXT: [[TMP163:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.s8.st.incp(i32 5, i32 7, i32 3, i32 [[TMP163]], i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u16(i32 4, i32 6, i32 5) +// CHECK-NEXT: [[TMP164:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u16.ld.incp(i32 4, i32 7, i32 [[TMP164]], i32 0, i32 5) +// CHECK-NEXT: [[TMP165:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u16.st.incp(i32 2, i32 2, i32 7, i32 [[TMP165]], i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u32(i32 0, i32 1, i32 2) +// CHECK-NEXT: [[TMP166:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u32.ld.incp(i32 5, i32 6, i32 [[TMP166]], i32 3, i32 5) +// CHECK-NEXT: [[TMP167:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u32.st.incp(i32 0, i32 1, i32 4, i32 [[TMP167]], i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u8(i32 4, i32 2, i32 7) +// CHECK-NEXT: [[TMP168:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u8.ld.incp(i32 2, i32 7, i32 [[TMP168]], i32 3, i32 4) +// CHECK-NEXT: [[TMP169:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vsub.u8.st.incp(i32 6, i32 4, i32 7, i32 [[TMP169]], i32 7) +// CHECK-NEXT: [[TMP170:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP171:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP172:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.addx2(i32 [[TMP170]], i32 [[TMP171]], i32 [[TMP172]]) +// CHECK-NEXT: [[TMP173:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP174:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP175:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.addx4(i32 [[TMP173]], i32 [[TMP174]], i32 [[TMP175]]) +// CHECK-NEXT: [[TMP176:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP177:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP178:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.sat(i32 [[TMP176]], i32 [[TMP177]], i32 [[TMP178]]) +// CHECK-NEXT: [[TMP179:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP180:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP181:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.subx2(i32 [[TMP179]], i32 [[TMP180]], i32 [[TMP181]]) +// CHECK-NEXT: [[TMP182:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP183:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP184:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.subx4(i32 [[TMP182]], i32 [[TMP183]], i32 [[TMP184]]) +// CHECK-NEXT: call void @llvm.riscv.esp.andq(i32 0, i32 1, i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.notq(i32 0, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.orq(i32 0, i32 6, i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.xorq(i32 7, i32 4, i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.eq.s16(i32 6, i32 6, i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.eq.s32(i32 6, i32 2, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.eq.s8(i32 7, i32 6, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.eq.u16(i32 0, i32 2, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.eq.u32(i32 6, i32 4, i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.eq.u8(i32 6, i32 4, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.gt.s16(i32 5, i32 3, i32 6) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.gt.s32(i32 2, i32 4, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.gt.s8(i32 7, i32 7, i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.gt.u16(i32 2, i32 7, i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.gt.u32(i32 6, i32 4, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.gt.u8(i32 0, i32 4, i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.lt.s16(i32 4, i32 6, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.lt.s32(i32 2, i32 4, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.lt.s8(i32 3, i32 0, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.lt.u16(i32 2, i32 4, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.lt.u32(i32 2, i32 0, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vcmp.lt.u8(i32 0, i32 2, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.mov.s16.qacc(i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.mov.s8.qacc(i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.mov.u16.qacc(i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.mov.u8.qacc(i32 5) +// CHECK-NEXT: [[TMP185:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movi.16.a(i32 2, i32 8, i32 [[TMP185]]) +// CHECK-NEXT: [[TMP186:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movi.16.q(i32 [[TMP186]], i32 12, i32 1) +// CHECK-NEXT: [[TMP187:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movi.32.a(i32 4, i32 2, i32 [[TMP187]]) +// CHECK-NEXT: [[TMP188:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movi.32.q(i32 [[TMP188]], i32 1, i32 0) +// CHECK-NEXT: [[TMP189:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movi.8.a(i32 0, i32 13, i32 [[TMP189]]) +// CHECK-NEXT: [[TMP190:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movi.8.q(i32 [[TMP190]], i32 14, i32 3) +// CHECK-NEXT: [[TMP191:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.r.cfg(i32 [[TMP191]]) +// CHECK-NEXT: [[TMP192:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.r.fft.bit.width(i32 [[TMP192]]) +// CHECK-NEXT: [[TMP193:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP194:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.r.perf(i32 [[TMP193]], i32 [[TMP194]]) +// CHECK-NEXT: [[TMP195:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.r.sar(i32 [[TMP195]]) +// CHECK-NEXT: [[TMP196:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.r.sar.bytes(i32 [[TMP196]]) +// CHECK-NEXT: [[TMP197:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.r.xacc.h(i32 [[TMP197]]) +// CHECK-NEXT: [[TMP198:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.r.xacc.l(i32 [[TMP198]]) +// CHECK-NEXT: [[TMP199:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.w.cfg(i32 [[TMP199]]) +// CHECK-NEXT: [[TMP200:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.w.fft.bit.width(i32 [[TMP200]]) +// CHECK-NEXT: [[TMP201:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.w.perf(i32 [[TMP201]]) +// CHECK-NEXT: [[TMP202:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.w.sar(i32 [[TMP202]]) +// CHECK-NEXT: [[TMP203:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.w.sar.bytes(i32 [[TMP203]]) +// CHECK-NEXT: [[TMP204:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.w.xacc.h(i32 [[TMP204]]) +// CHECK-NEXT: [[TMP205:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.movx.w.xacc.l(i32 [[TMP205]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vext.s16(i32 0, i32 4, i32 6) +// CHECK-NEXT: call void @llvm.riscv.esp.vext.s8(i32 0, i32 7, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vext.u16(i32 1, i32 0, i32 6) +// CHECK-NEXT: call void @llvm.riscv.esp.vext.u8(i32 4, i32 1, i32 6) +// CHECK-NEXT: call void @llvm.riscv.esp.vunzip.16(i32 3, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vunzip.32(i32 6, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vunzip.8(i32 3, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vunzipt.16(i32 1, i32 5, i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vunzipt.8(i32 7, i32 5, i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vzip.16(i32 2, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vzip.32(i32 0, i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.vzip.8(i32 6, i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vzipt.16(i32 6, i32 3, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.vzipt.8(i32 7, i32 0, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.zero.q(i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.zero.qacc() +// CHECK-NEXT: call void @llvm.riscv.esp.zero.xacc() +// CHECK-NEXT: [[TMP206:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.ams.s16.ld.incp(i32 1, i32 1, i32 3, i32 [[TMP206]], i32 0, i32 6, i32 0, i32 3) +// CHECK-NEXT: [[TMP207:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.ams.s16.ld.incp.uaup(i32 3, i32 0, i32 1, i32 [[TMP207]], i32 0, i32 3, i32 3, i32 1) +// CHECK-NEXT: [[TMP208:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.ams.s16.ld.r32.decp(i32 2, i32 3, i32 7, i32 [[TMP208]], i32 0, i32 1, i32 1, i32 4) +// CHECK-NEXT: [[TMP209:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP210:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.ams.s16.st.incp(i32 4, i32 4, i32 0, i32 5, i32 [[TMP209]], i32 [[TMP210]], i32 1, i32 1) +// CHECK-NEXT: [[TMP211:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.bitrev(i32 [[TMP211]], i32 6) +// CHECK-NEXT: [[TMP212:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP213:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.cmul.s16.ld.xp(i32 [[TMP212]], i32 7, i32 0, i32 [[TMP213]], i32 2, i32 1, i32 2) +// CHECK-NEXT: [[TMP214:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP215:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.cmul.s16.st.xp(i32 [[TMP214]], i32 6, i32 0, i32 7, i32 [[TMP215]], i32 0, i32 1, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.fft.r2bf.s16(i32 2, i32 5, i32 0, i32 7, i32 5) +// CHECK-NEXT: [[TMP216:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.r2bf.s16.st.incp(i32 1, i32 7, i32 [[TMP216]], i32 1, i32 6) +// CHECK-NEXT: [[TMP217:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.fft.vst.r32.decp(i32 2, i32 [[TMP217]], i32 1) +// CHECK-NEXT: [[TMP218:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ld.128.usar.ip(i32 [[TMP218]], i32 -464, i32 7) +// CHECK-NEXT: [[TMP219:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP220:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ld.128.usar.xp(i32 [[TMP219]], i32 [[TMP220]], i32 0) +// CHECK-NEXT: [[TMP221:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ld.xacc.ip(i32 [[TMP221]], i32 -224) +// CHECK-NEXT: [[TMP222:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldqa.s16.128.ip(i32 [[TMP222]], i32 288) +// CHECK-NEXT: [[TMP223:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP224:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldqa.s16.128.xp(i32 [[TMP223]], i32 [[TMP224]]) +// CHECK-NEXT: [[TMP225:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldqa.s8.128.ip(i32 [[TMP225]], i32 -1408) +// CHECK-NEXT: [[TMP226:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP227:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldqa.s8.128.xp(i32 [[TMP226]], i32 [[TMP227]]) +// CHECK-NEXT: [[TMP228:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldqa.u16.128.ip(i32 [[TMP228]], i32 -1440) +// CHECK-NEXT: [[TMP229:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP230:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldqa.u16.128.xp(i32 [[TMP229]], i32 [[TMP230]]) +// CHECK-NEXT: [[TMP231:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldqa.u8.128.ip(i32 [[TMP231]], i32 -816) +// CHECK-NEXT: [[TMP232:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP233:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldqa.u8.128.xp(i32 [[TMP232]], i32 [[TMP233]]) +// CHECK-NEXT: [[TMP234:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldbc.16.ip(i32 [[TMP234]], i32 380, i32 2) +// CHECK-NEXT: [[TMP235:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP236:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldbc.16.xp(i32 [[TMP235]], i32 [[TMP236]], i32 3) +// CHECK-NEXT: [[TMP237:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldbc.32.ip(i32 [[TMP237]], i32 -292, i32 7) +// CHECK-NEXT: [[TMP238:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP239:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldbc.32.xp(i32 [[TMP238]], i32 [[TMP239]], i32 1) +// CHECK-NEXT: [[TMP240:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldbc.8.ip(i32 [[TMP240]], i32 -416, i32 5) +// CHECK-NEXT: [[TMP241:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP242:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldbc.8.xp(i32 [[TMP241]], i32 [[TMP242]], i32 7) +// CHECK-NEXT: [[TMP243:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldext.s16.ip(i32 [[TMP243]], i32 -80, i32 0, i32 3) +// CHECK-NEXT: [[TMP244:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP245:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldext.s16.xp(i32 [[TMP244]], i32 [[TMP245]], i32 2, i32 5) +// CHECK-NEXT: [[TMP246:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldext.s8.ip(i32 [[TMP246]], i32 0, i32 2, i32 7) +// CHECK-NEXT: [[TMP247:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP248:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldext.s8.xp(i32 [[TMP247]], i32 [[TMP248]], i32 7, i32 5) +// CHECK-NEXT: [[TMP249:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldext.u16.ip(i32 [[TMP249]], i32 32, i32 0, i32 6) +// CHECK-NEXT: [[TMP250:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP251:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldext.u16.xp(i32 [[TMP250]], i32 [[TMP251]], i32 7, i32 6) +// CHECK-NEXT: [[TMP252:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldext.u8.ip(i32 [[TMP252]], i32 -16, i32 3, i32 1) +// CHECK-NEXT: [[TMP253:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP254:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldext.u8.xp(i32 [[TMP253]], i32 [[TMP254]], i32 5, i32 4) +// CHECK-NEXT: [[TMP255:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vldhbc.16.incp(i32 [[TMP255]], i32 2, i32 3) +// CHECK-NEXT: [[TMP256:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ld.qacc.h.h.128.ip(i32 [[TMP256]], i32 -240) +// CHECK-NEXT: [[TMP257:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ld.qacc.h.l.128.ip(i32 [[TMP257]], i32 -32) +// CHECK-NEXT: [[TMP258:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ld.qacc.l.h.128.ip(i32 [[TMP258]], i32 -64) +// CHECK-NEXT: [[TMP259:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ld.qacc.l.l.128.ip(i32 [[TMP259]], i32 -80) +// CHECK-NEXT: [[TMP260:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ld.ua.state.ip(i32 [[TMP260]], i32 1504) +// CHECK-NEXT: [[TMP261:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.ldxq.32(i32 [[TMP261]], i32 6, i32 1, i32 7, i32 1) +// CHECK-NEXT: [[TMP262:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.st.qacc.h.h.128.ip(i32 [[TMP262]], i32 -480) +// CHECK-NEXT: [[TMP263:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.st.qacc.h.l.128.ip(i32 [[TMP263]], i32 -1712) +// CHECK-NEXT: [[TMP264:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.st.qacc.l.h.128.ip(i32 [[TMP264]], i32 960) +// CHECK-NEXT: [[TMP265:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.st.qacc.l.l.128.ip(i32 [[TMP265]], i32 1920) +// CHECK-NEXT: [[TMP266:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.st.ua.state.ip(i32 [[TMP266]], i32 -1360) +// CHECK-NEXT: [[TMP267:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.stxq.32(i32 [[TMP267]], i32 6, i32 2, i32 3, i32 0) +// CHECK-NEXT: [[TMP268:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vld.128.ip(i32 [[TMP268]], i32 -1136, i32 0) +// CHECK-NEXT: [[TMP269:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP270:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vld.128.xp(i32 [[TMP269]], i32 [[TMP270]], i32 5) +// CHECK-NEXT: [[TMP271:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vld.h.64.ip(i32 [[TMP271]], i32 1008, i32 4) +// CHECK-NEXT: [[TMP272:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP273:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vld.h.64.xp(i32 [[TMP272]], i32 [[TMP273]], i32 2) +// CHECK-NEXT: [[TMP274:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vld.l.64.ip(i32 [[TMP274]], i32 -304, i32 6) +// CHECK-NEXT: [[TMP275:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP276:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vld.l.64.xp(i32 [[TMP275]], i32 [[TMP276]], i32 6) +// CHECK-NEXT: [[TMP277:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vst.128.ip(i32 0, i32 [[TMP277]], i32 -1216) +// CHECK-NEXT: [[TMP278:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP279:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vst.128.xp(i32 [[TMP278]], i32 6, i32 [[TMP279]]) +// CHECK-NEXT: [[TMP280:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vst.h.64.ip(i32 1, i32 [[TMP280]], i32 -456) +// CHECK-NEXT: [[TMP281:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP282:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vst.h.64.xp(i32 [[TMP281]], i32 2, i32 [[TMP282]]) +// CHECK-NEXT: [[TMP283:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vst.l.64.ip(i32 6, i32 [[TMP283]], i32 664) +// CHECK-NEXT: [[TMP284:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP285:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.vst.l.64.xp(i32 [[TMP284]], i32 4, i32 [[TMP285]]) +// CHECK-NEXT: call void @llvm.riscv.esp.slci.2q(i32 2, i32 0, i32 14) +// CHECK-NEXT: [[TMP286:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP287:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.slcxxp.2q(i32 [[TMP286]], i32 [[TMP287]], i32 0, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.src.q(i32 7, i32 3, i32 2) +// CHECK-NEXT: [[TMP288:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.src.q.ld.ip(i32 1, i32 [[TMP288]], i32 4, i32 1168, i32 4) +// CHECK-NEXT: [[TMP289:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP290:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.src.q.ld.xp(i32 [[TMP289]], i32 0, i32 [[TMP290]], i32 1, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.src.q.qup(i32 3, i32 3, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.srci.2q(i32 7, i32 4, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.srcmb.s16.q.qacc(i32 2, i32 1, i32 5) +// CHECK-NEXT: [[TMP291:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.srcmb.s16.qacc(i32 [[TMP291]], i32 0, i32 7) +// CHECK-NEXT: call void @llvm.riscv.esp.srcmb.s8.q.qacc(i32 7, i32 0, i32 3) +// CHECK-NEXT: [[TMP292:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.srcmb.s8.qacc(i32 [[TMP292]], i32 1, i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.srcmb.u16.q.qacc(i32 6, i32 1, i32 0) +// CHECK-NEXT: [[TMP293:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.srcmb.u16.qacc(i32 [[TMP293]], i32 0, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.srcmb.u8.q.qacc(i32 6, i32 0, i32 7) +// CHECK-NEXT: [[TMP294:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.srcmb.u8.qacc(i32 [[TMP294]], i32 1, i32 2) +// CHECK-NEXT: [[TMP295:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.srcq.128.st.incp(i32 0, i32 5, i32 [[TMP295]]) +// CHECK-NEXT: [[TMP296:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP297:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.srcxxp.2q(i32 [[TMP296]], i32 [[TMP297]], i32 7, i32 5) +// CHECK-NEXT: [[TMP298:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP299:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.srs.s.xacc(i32 [[TMP298]], i32 [[TMP299]]) +// CHECK-NEXT: [[TMP300:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: [[TMP301:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.srs.u.xacc(i32 [[TMP300]], i32 [[TMP301]]) +// CHECK-NEXT: call void @llvm.riscv.esp.vsl.32(i32 0, i32 3) +// CHECK-NEXT: call void @llvm.riscv.esp.vsld.16(i32 6, i32 4, i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vsld.32(i32 2, i32 7, i32 5) +// CHECK-NEXT: call void @llvm.riscv.esp.vsld.8(i32 1, i32 0, i32 0) +// CHECK-NEXT: call void @llvm.riscv.esp.vsr.s32(i32 6, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vsr.u32(i32 3, i32 2) +// CHECK-NEXT: call void @llvm.riscv.esp.vsrd.16(i32 6, i32 2, i32 1) +// CHECK-NEXT: call void @llvm.riscv.esp.vsrd.32(i32 7, i32 5, i32 4) +// CHECK-NEXT: call void @llvm.riscv.esp.vsrd.8(i32 2, i32 1, i32 4) +// CHECK-NEXT: [[TMP302:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.st.s.xacc.ip(i32 [[TMP302]], i32 912) +// CHECK-NEXT: [[TMP303:%.*]] = load i32, ptr [[DATA]], align 4 +// CHECK-NEXT: call void @llvm.riscv.esp.st.u.xacc.ip(i32 [[TMP303]], i32 -112) +// CHECK-NEXT: ret void +// +void test() { + uint32_t data = 10; + __builtin_riscv_esp_vcmulas_s16_qacc_h(4, 2); +__builtin_riscv_esp_vcmulas_s16_qacc_h_ld_ip(4, 0, data, -96, 3); +__builtin_riscv_esp_vcmulas_s16_qacc_h_ld_xp(data, 5, 5, data, 5); +__builtin_riscv_esp_vcmulas_s16_qacc_l(6, 1); +__builtin_riscv_esp_vcmulas_s16_qacc_l_ld_ip(2, 3, data, -48, 3); +__builtin_riscv_esp_vcmulas_s16_qacc_l_ld_xp(data, 7, 2, data, 1); +__builtin_riscv_esp_vcmulas_s8_qacc_h(4, 4); +__builtin_riscv_esp_vcmulas_s8_qacc_h_ld_ip(7, 4, data, -128, 4); +__builtin_riscv_esp_vcmulas_s8_qacc_h_ld_xp(data, 2, 3, data, 1); +__builtin_riscv_esp_vcmulas_s8_qacc_l(6, 4); +__builtin_riscv_esp_vcmulas_s8_qacc_l_ld_ip(5, 5, data, 16, 7); +__builtin_riscv_esp_vcmulas_s8_qacc_l_ld_xp(data, 4, 4, data, 2); +__builtin_riscv_esp_vmulas_s16_qacc(7, 6); +__builtin_riscv_esp_vmulas_s16_qacc_ld_ip(0, 4, data, 96, 4); +__builtin_riscv_esp_vmulas_s16_qacc_ld_xp(data, 4, 4, data, 7); +__builtin_riscv_esp_vmulas_s16_qacc_st_ip(2, 1, 7, data, -128); +__builtin_riscv_esp_vmulas_s16_qacc_st_xp(data, 1, 2, 6, data); +__builtin_riscv_esp_vmulas_s16_xacc(1, 3); +__builtin_riscv_esp_vmulas_s16_xacc_ld_ip(7, 3, data, -96, 5); +__builtin_riscv_esp_vmulas_s16_xacc_ld_xp(data, 3, 1, data, 1); +__builtin_riscv_esp_vmulas_s16_xacc_st_ip(2, 0, 0, data, 64); +__builtin_riscv_esp_vmulas_s16_xacc_st_xp(data, 6, 3, 6, data); +__builtin_riscv_esp_vmulas_s8_qacc(0, 0); +__builtin_riscv_esp_vmulas_s8_qacc_ld_ip(0, 3, data, 0, 7); +__builtin_riscv_esp_vmulas_s8_qacc_ld_xp(data, 4, 3, data, 4); +__builtin_riscv_esp_vmulas_s8_qacc_st_ip(3, 3, 5, data, -64); +__builtin_riscv_esp_vmulas_s8_qacc_st_xp(data, 4, 7, 0, data); +__builtin_riscv_esp_vmulas_s8_xacc(3, 3); +__builtin_riscv_esp_vmulas_s8_xacc_ld_ip(3, 2, data, 0, 5); +__builtin_riscv_esp_vmulas_s8_xacc_ld_xp(data, 6, 3, data, 0); +__builtin_riscv_esp_vmulas_s8_xacc_st_ip(1, 7, 7, data, -32); +__builtin_riscv_esp_vmulas_s8_xacc_st_xp(data, 6, 7, 6, data); +__builtin_riscv_esp_vmulas_u16_qacc(5, 4); +__builtin_riscv_esp_vmulas_u16_qacc_ld_ip(5, 2, data, 64, 6); +__builtin_riscv_esp_vmulas_u16_qacc_ld_xp(data, 5, 7, data, 7); +__builtin_riscv_esp_vmulas_u16_qacc_st_ip(1, 4, 3, data, -96); +__builtin_riscv_esp_vmulas_u16_qacc_st_xp(data, 5, 0, 2, data); +__builtin_riscv_esp_vmulas_u16_xacc(0, 7); +__builtin_riscv_esp_vmulas_u16_xacc_ld_ip(6, 6, data, -96, 4); +__builtin_riscv_esp_vmulas_u16_xacc_ld_xp(data, 6, 5, data, 6); +__builtin_riscv_esp_vmulas_u16_xacc_st_ip(3, 0, 4, data, 64); +__builtin_riscv_esp_vmulas_u16_xacc_st_xp(data, 1, 0, 4, data); +__builtin_riscv_esp_vmulas_u8_qacc(5, 4); +__builtin_riscv_esp_vmulas_u8_qacc_ld_ip(5, 3, data, 80, 5); +__builtin_riscv_esp_vmulas_u8_qacc_ld_xp(data, 4, 7, data, 4); +__builtin_riscv_esp_vmulas_u8_qacc_st_ip(3, 3, 5, data, -96); +__builtin_riscv_esp_vmulas_u8_qacc_st_xp(data, 6, 7, 3, data); +__builtin_riscv_esp_vmulas_u8_xacc(0, 1); +__builtin_riscv_esp_vmulas_u8_xacc_ld_ip(6, 0, data, -32, 7); +__builtin_riscv_esp_vmulas_u8_xacc_ld_xp(data, 3, 3, data, 5); +__builtin_riscv_esp_vmulas_u8_xacc_st_ip(7, 0, 4, data, 32); +__builtin_riscv_esp_vmulas_u8_xacc_st_xp(data, 1, 0, 0, data); +__builtin_riscv_esp_vmulas_s16_qacc_ldbc_incp(3, 6, data, 7); +__builtin_riscv_esp_vmulas_s8_qacc_ldbc_incp(5, 3, data, 6); +__builtin_riscv_esp_vmulas_u16_qacc_ldbc_incp(0, 3, data, 2); +__builtin_riscv_esp_vmulas_u8_qacc_ldbc_incp(4, 7, data, 3); +__builtin_riscv_esp_vsmulas_s16_qacc(7, 7, 4); +__builtin_riscv_esp_vsmulas_s16_qacc_ld_incp(7, 7, data, 4, 1); +__builtin_riscv_esp_vsmulas_s8_qacc(7, 0, 7); +__builtin_riscv_esp_vsmulas_s8_qacc_ld_incp(5, 6, data, 15, 2); +__builtin_riscv_esp_vsmulas_u16_qacc(7, 0, 10); +__builtin_riscv_esp_vsmulas_u16_qacc_ld_incp(7, 6, data, 1, 0); +__builtin_riscv_esp_vsmulas_u8_qacc(3, 6, 5); +__builtin_riscv_esp_vsmulas_u8_qacc_ld_incp(6, 1, data, 4, 0); +__builtin_riscv_esp_cmul_s16(2, 1, 3, 1); +__builtin_riscv_esp_cmul_s16_ld_incp(2, 7, data, 0, 5, 0); +__builtin_riscv_esp_cmul_s16_st_incp(7, 4, 6, data, 2, 5); +__builtin_riscv_esp_cmul_s8(5, 7, 2, 4); +__builtin_riscv_esp_cmul_s8_ld_incp(0, 6, data, 2, 7, 5); +__builtin_riscv_esp_cmul_s8_st_incp(1, 6, 5, data, 0, 2); +__builtin_riscv_esp_cmul_u16(7, 4, 0, 0); +__builtin_riscv_esp_cmul_u16_ld_incp(2, 0, data, 3, 1, 1); +__builtin_riscv_esp_cmul_u16_st_incp(4, 3, 4, data, 1, 2); +__builtin_riscv_esp_cmul_u8(3, 4, 1, 5); +__builtin_riscv_esp_cmul_u8_ld_incp(5, 0, data, 1, 5, 1); +__builtin_riscv_esp_cmul_u8_st_incp(2, 7, 4, data, 3, 1); +__builtin_riscv_esp_max_s16_a(2, data); +__builtin_riscv_esp_max_s32_a(0, data); +__builtin_riscv_esp_max_s8_a(7, data); +__builtin_riscv_esp_max_u16_a(4, data); +__builtin_riscv_esp_max_u32_a(4, data); +__builtin_riscv_esp_max_u8_a(3, data); +__builtin_riscv_esp_min_s16_a(0, data); +__builtin_riscv_esp_min_s32_a(7, data); +__builtin_riscv_esp_min_s8_a(4, data); +__builtin_riscv_esp_min_u16_a(7, data); +__builtin_riscv_esp_min_u32_a(6, data); +__builtin_riscv_esp_min_u8_a(1, data); +__builtin_riscv_esp_vabs_16(7, 0); +__builtin_riscv_esp_vabs_32(0, 3); +__builtin_riscv_esp_vabs_8(5, 2); +__builtin_riscv_esp_vadd_s16(0, 4, 0); +__builtin_riscv_esp_vadd_s16_ld_incp(4, 2, data, 0, 7); +__builtin_riscv_esp_vadd_s16_st_incp(5, 7, 0, data, 5); +__builtin_riscv_esp_vadd_s32(6, 5, 0); +__builtin_riscv_esp_vadd_s32_ld_incp(5, 6, data, 0, 2); +__builtin_riscv_esp_vadd_s32_st_incp(7, 7, 0, data, 1); +__builtin_riscv_esp_vadd_s8(6, 5, 5); +__builtin_riscv_esp_vadd_s8_ld_incp(2, 4, data, 6, 7); +__builtin_riscv_esp_vadd_s8_st_incp(4, 6, 4, data, 7); +__builtin_riscv_esp_vadd_u16(0, 6, 5); +__builtin_riscv_esp_vadd_u16_ld_incp(6, 7, data, 5, 1); +__builtin_riscv_esp_vadd_u16_st_incp(1, 3, 4, data, 5); +__builtin_riscv_esp_vadd_u32(7, 3, 0); +__builtin_riscv_esp_vadd_u32_ld_incp(0, 4, data, 5, 5); +__builtin_riscv_esp_vadd_u32_st_incp(1, 5, 6, data, 1); +__builtin_riscv_esp_vadd_u8(0, 1, 5); +__builtin_riscv_esp_vadd_u8_ld_incp(5, 1, data, 2, 6); +__builtin_riscv_esp_vadd_u8_st_incp(1, 7, 4, data, 2); +__builtin_riscv_esp_vclamp_s16(3, 12, 5); +__builtin_riscv_esp_vmax_s16(1, 2, 2); +__builtin_riscv_esp_vmax_s16_ld_incp(3, 0, data, 5, 1); +__builtin_riscv_esp_vmax_s16_st_incp(0, 4, 2, data, 3); +__builtin_riscv_esp_vmax_s32(0, 2, 4); +__builtin_riscv_esp_vmax_s32_ld_incp(3, 5, data, 3, 6); +__builtin_riscv_esp_vmax_s32_st_incp(6, 0, 7, data, 4); +__builtin_riscv_esp_vmax_s8(1, 0, 3); +__builtin_riscv_esp_vmax_s8_ld_incp(1, 6, data, 6, 6); +__builtin_riscv_esp_vmax_s8_st_incp(2, 7, 1, data, 0); +__builtin_riscv_esp_vmax_u16(6, 6, 3); +__builtin_riscv_esp_vmax_u16_ld_incp(5, 2, data, 2, 1); +__builtin_riscv_esp_vmax_u16_st_incp(3, 6, 2, data, 0); +__builtin_riscv_esp_vmax_u32(2, 3, 3); +__builtin_riscv_esp_vmax_u32_ld_incp(1, 4, data, 5, 5); +__builtin_riscv_esp_vmax_u32_st_incp(4, 2, 1, data, 4); +__builtin_riscv_esp_vmax_u8(7, 0, 4); +__builtin_riscv_esp_vmax_u8_ld_incp(1, 5, data, 4, 7); +__builtin_riscv_esp_vmax_u8_st_incp(1, 2, 5, data, 7); +__builtin_riscv_esp_vmin_s16(5, 1, 7); +__builtin_riscv_esp_vmin_s16_ld_incp(7, 6, data, 6, 4); +__builtin_riscv_esp_vmin_s16_st_incp(7, 0, 6, data, 2); +__builtin_riscv_esp_vmin_s32(7, 4, 7); +__builtin_riscv_esp_vmin_s32_ld_incp(0, 1, data, 5, 4); +__builtin_riscv_esp_vmin_s32_st_incp(1, 6, 7, data, 4); +__builtin_riscv_esp_vmin_s8(5, 6, 4); +__builtin_riscv_esp_vmin_s8_ld_incp(1, 6, data, 6, 5); +__builtin_riscv_esp_vmin_s8_st_incp(7, 7, 6, data, 7); +__builtin_riscv_esp_vmin_u16(7, 1, 1); +__builtin_riscv_esp_vmin_u16_ld_incp(6, 0, data, 3, 0); +__builtin_riscv_esp_vmin_u16_st_incp(0, 7, 5, data, 3); +__builtin_riscv_esp_vmin_u32(6, 5, 0); +__builtin_riscv_esp_vmin_u32_ld_incp(3, 7, data, 1, 4); +__builtin_riscv_esp_vmin_u32_st_incp(1, 0, 2, data, 3); +__builtin_riscv_esp_vmin_u8(2, 0, 7); +__builtin_riscv_esp_vmin_u8_ld_incp(4, 2, data, 4, 3); +__builtin_riscv_esp_vmin_u8_st_incp(1, 7, 4, data, 4); +__builtin_riscv_esp_vmul_s16(7, 5, 3); +__builtin_riscv_esp_vmul_s16_ld_incp(5, 4, data, 1, 6); +__builtin_riscv_esp_vmul_s16_s8xs8(7, 6, 4, 4); +__builtin_riscv_esp_vmul_s16_st_incp(0, 1, 5, data, 7); +__builtin_riscv_esp_vmul_s32_s16xs16(5, 3, 1, 2); +__builtin_riscv_esp_vmul_s8(1, 6, 0); +__builtin_riscv_esp_vmul_s8_ld_incp(2, 1, data, 6, 5); +__builtin_riscv_esp_vmul_s8_st_incp(5, 2, 1, data, 7); +__builtin_riscv_esp_vmul_u16(7, 3, 6); +__builtin_riscv_esp_vmul_u16_ld_incp(3, 3, data, 2, 0); +__builtin_riscv_esp_vmul_u16_st_incp(6, 5, 0, data, 1); +__builtin_riscv_esp_vmul_u8(2, 2, 7); +__builtin_riscv_esp_vmul_u8_ld_incp(1, 1, data, 6, 7); +__builtin_riscv_esp_vmul_u8_st_incp(5, 0, 6, data, 2); +__builtin_riscv_esp_vprelu_s16(data, 0, 7, 3); +__builtin_riscv_esp_vprelu_s8(data, 6, 6, 6); +__builtin_riscv_esp_vrelu_s16(data, data, 3); +__builtin_riscv_esp_vrelu_s8(data, data, 7); +__builtin_riscv_esp_vsadds_s16(data, 5, 4); +__builtin_riscv_esp_vsadds_s8(data, 6, 6); +__builtin_riscv_esp_vsadds_u16(data, 7, 2); +__builtin_riscv_esp_vsadds_u8(data, 2, 0); +__builtin_riscv_esp_vsat_s16(data, data, 7, 5); +__builtin_riscv_esp_vsat_s32(data, data, 2, 5); +__builtin_riscv_esp_vsat_s8(data, data, 2, 5); +__builtin_riscv_esp_vsat_u16(data, data, 0, 2); +__builtin_riscv_esp_vsat_u32(data, data, 4, 2); +__builtin_riscv_esp_vsat_u8(data, data, 0, 2); +__builtin_riscv_esp_vssubs_s16(data, 3, 6); +__builtin_riscv_esp_vssubs_s8(data, 5, 5); +__builtin_riscv_esp_vssubs_u16(data, 6, 3); +__builtin_riscv_esp_vssubs_u8(data, 0, 3); +__builtin_riscv_esp_vsub_s16(0, 5, 3); +__builtin_riscv_esp_vsub_s16_ld_incp(0, 1, data, 5, 3); +__builtin_riscv_esp_vsub_s16_st_incp(5, 7, 7, data, 4); +__builtin_riscv_esp_vsub_s32(3, 0, 3); +__builtin_riscv_esp_vsub_s32_ld_incp(1, 2, data, 0, 2); +__builtin_riscv_esp_vsub_s32_st_incp(4, 0, 0, data, 5); +__builtin_riscv_esp_vsub_s8(4, 1, 3); +__builtin_riscv_esp_vsub_s8_ld_incp(3, 7, data, 3, 5); +__builtin_riscv_esp_vsub_s8_st_incp(5, 7, 3, data, 3); +__builtin_riscv_esp_vsub_u16(4, 6, 5); +__builtin_riscv_esp_vsub_u16_ld_incp(4, 7, data, 0, 5); +__builtin_riscv_esp_vsub_u16_st_incp(2, 2, 7, data, 3); +__builtin_riscv_esp_vsub_u32(0, 1, 2); +__builtin_riscv_esp_vsub_u32_ld_incp(5, 6, data, 3, 5); +__builtin_riscv_esp_vsub_u32_st_incp(0, 1, 4, data, 2); +__builtin_riscv_esp_vsub_u8(4, 2, 7); +__builtin_riscv_esp_vsub_u8_ld_incp(2, 7, data, 3, 4); +__builtin_riscv_esp_vsub_u8_st_incp(6, 4, 7, data, 7); +__builtin_riscv_esp_addx2(data, data, data); +__builtin_riscv_esp_addx4(data, data, data); +__builtin_riscv_esp_sat(data, data, data); +__builtin_riscv_esp_subx2(data, data, data); +__builtin_riscv_esp_subx4(data, data, data); +__builtin_riscv_esp_andq(0, 1, 4); +__builtin_riscv_esp_notq(0, 1); +__builtin_riscv_esp_orq(0, 6, 3); +__builtin_riscv_esp_xorq(7, 4, 7); +__builtin_riscv_esp_vcmp_eq_s16(6, 6, 3); +__builtin_riscv_esp_vcmp_eq_s32(6, 2, 1); +__builtin_riscv_esp_vcmp_eq_s8(7, 6, 0); +__builtin_riscv_esp_vcmp_eq_u16(0, 2, 5); +__builtin_riscv_esp_vcmp_eq_u32(6, 4, 3); +__builtin_riscv_esp_vcmp_eq_u8(6, 4, 5); +__builtin_riscv_esp_vcmp_gt_s16(5, 3, 6); +__builtin_riscv_esp_vcmp_gt_s32(2, 4, 5); +__builtin_riscv_esp_vcmp_gt_s8(7, 7, 4); +__builtin_riscv_esp_vcmp_gt_u16(2, 7, 7); +__builtin_riscv_esp_vcmp_gt_u32(6, 4, 2); +__builtin_riscv_esp_vcmp_gt_u8(0, 4, 4); +__builtin_riscv_esp_vcmp_lt_s16(4, 6, 5); +__builtin_riscv_esp_vcmp_lt_s32(2, 4, 1); +__builtin_riscv_esp_vcmp_lt_s8(3, 0, 2); +__builtin_riscv_esp_vcmp_lt_u16(2, 4, 1); +__builtin_riscv_esp_vcmp_lt_u32(2, 0, 5); +__builtin_riscv_esp_vcmp_lt_u8(0, 2, 5); +__builtin_riscv_esp_mov_s16_qacc(4); +__builtin_riscv_esp_mov_s8_qacc(5); +__builtin_riscv_esp_mov_u16_qacc(5); +__builtin_riscv_esp_mov_u8_qacc(5); +__builtin_riscv_esp_movi_16_a(2, 8, data); +__builtin_riscv_esp_movi_16_q(data, 12, 1); +__builtin_riscv_esp_movi_32_a(4, 2, data); +__builtin_riscv_esp_movi_32_q(data, 1, 0); +__builtin_riscv_esp_movi_8_a(0, 13, data); +__builtin_riscv_esp_movi_8_q(data, 14, 3); +__builtin_riscv_esp_movx_r_cfg(data); +__builtin_riscv_esp_movx_r_fft_bit_width(data); +__builtin_riscv_esp_movx_r_perf(data, data); +__builtin_riscv_esp_movx_r_sar(data); +__builtin_riscv_esp_movx_r_sar_bytes(data); +__builtin_riscv_esp_movx_r_xacc_h(data); +__builtin_riscv_esp_movx_r_xacc_l(data); +__builtin_riscv_esp_movx_w_cfg(data); +__builtin_riscv_esp_movx_w_fft_bit_width(data); +__builtin_riscv_esp_movx_w_perf(data); +__builtin_riscv_esp_movx_w_sar(data); +__builtin_riscv_esp_movx_w_sar_bytes(data); +__builtin_riscv_esp_movx_w_xacc_h(data); +__builtin_riscv_esp_movx_w_xacc_l(data); +__builtin_riscv_esp_vext_s16(0, 4, 6); +__builtin_riscv_esp_vext_s8(0, 7, 1); +__builtin_riscv_esp_vext_u16(1, 0, 6); +__builtin_riscv_esp_vext_u8(4, 1, 6); +__builtin_riscv_esp_vunzip_16(3, 2); +__builtin_riscv_esp_vunzip_32(6, 1); +__builtin_riscv_esp_vunzip_8(3, 5); +__builtin_riscv_esp_vunzipt_16(1, 5, 4); +__builtin_riscv_esp_vunzipt_8(7, 5, 7); +__builtin_riscv_esp_vzip_16(2, 2); +__builtin_riscv_esp_vzip_32(0, 7); +__builtin_riscv_esp_vzip_8(6, 4); +__builtin_riscv_esp_vzipt_16(6, 3, 0); +__builtin_riscv_esp_vzipt_8(7, 0, 1); +__builtin_riscv_esp_zero_q(3); +__builtin_riscv_esp_zero_qacc(); +__builtin_riscv_esp_zero_xacc(); +__builtin_riscv_esp_fft_ams_s16_ld_incp(1, 1, 3, data, 0, 6, 0, 3); +__builtin_riscv_esp_fft_ams_s16_ld_incp_uaup(3, 0, 1, data, 0, 3, 3, 1); +__builtin_riscv_esp_fft_ams_s16_ld_r32_decp(2, 3, 7, data, 0, 1, 1, 4); +__builtin_riscv_esp_fft_ams_s16_st_incp(4, 4, 0, 5, data, data, 1, 1); +__builtin_riscv_esp_fft_bitrev(data, 6); +__builtin_riscv_esp_fft_cmul_s16_ld_xp(data, 7, 0, data, 2, 1, 2); +__builtin_riscv_esp_fft_cmul_s16_st_xp(data, 6, 0, 7, data, 0, 1, 0); +__builtin_riscv_esp_fft_r2bf_s16(2, 5, 0, 7, 5); +__builtin_riscv_esp_fft_r2bf_s16_st_incp(1, 7, data, 1, 6); +__builtin_riscv_esp_fft_vst_r32_decp(2, data, 1); +__builtin_riscv_esp_ld_128_usar_ip(data, -464, 7); +__builtin_riscv_esp_ld_128_usar_xp(data, data, 0); +__builtin_riscv_esp_ld_xacc_ip(data, -224); +__builtin_riscv_esp_ldqa_s16_128_ip(data, 288); +__builtin_riscv_esp_ldqa_s16_128_xp(data, data); +__builtin_riscv_esp_ldqa_s8_128_ip(data, -1408); +__builtin_riscv_esp_ldqa_s8_128_xp(data, data); +__builtin_riscv_esp_ldqa_u16_128_ip(data, -1440); +__builtin_riscv_esp_ldqa_u16_128_xp(data, data); +__builtin_riscv_esp_ldqa_u8_128_ip(data, -816); +__builtin_riscv_esp_ldqa_u8_128_xp(data, data); +__builtin_riscv_esp_vldbc_16_ip(data, 380, 2); +__builtin_riscv_esp_vldbc_16_xp(data, data, 3); +__builtin_riscv_esp_vldbc_32_ip(data, -292, 7); +__builtin_riscv_esp_vldbc_32_xp(data, data, 1); +__builtin_riscv_esp_vldbc_8_ip(data, -416, 5); +__builtin_riscv_esp_vldbc_8_xp(data, data, 7); +__builtin_riscv_esp_vldext_s16_ip(data, -80, 0, 3); +__builtin_riscv_esp_vldext_s16_xp(data, data, 2, 5); +__builtin_riscv_esp_vldext_s8_ip(data, 0, 2, 7); +__builtin_riscv_esp_vldext_s8_xp(data, data, 7, 5); +__builtin_riscv_esp_vldext_u16_ip(data, 32, 0, 6); +__builtin_riscv_esp_vldext_u16_xp(data, data, 7, 6); +__builtin_riscv_esp_vldext_u8_ip(data, -16, 3, 1); +__builtin_riscv_esp_vldext_u8_xp(data, data, 5, 4); +__builtin_riscv_esp_vldhbc_16_incp(data, 2, 3); +__builtin_riscv_esp_ld_qacc_h_h_128_ip(data, -240); +__builtin_riscv_esp_ld_qacc_h_l_128_ip(data, -32); +__builtin_riscv_esp_ld_qacc_l_h_128_ip(data, -64); +__builtin_riscv_esp_ld_qacc_l_l_128_ip(data, -80); +__builtin_riscv_esp_ld_ua_state_ip(data, 1504); +__builtin_riscv_esp_ldxq_32(data, 6, 1, 7, 1); +__builtin_riscv_esp_st_qacc_h_h_128_ip(data, -480); +__builtin_riscv_esp_st_qacc_h_l_128_ip(data, -1712); +__builtin_riscv_esp_st_qacc_l_h_128_ip(data, 960); +__builtin_riscv_esp_st_qacc_l_l_128_ip(data, 1920); +__builtin_riscv_esp_st_ua_state_ip(data, -1360); +__builtin_riscv_esp_stxq_32(data, 6, 2, 3, 0); +__builtin_riscv_esp_vld_128_ip(data, -1136, 0); +__builtin_riscv_esp_vld_128_xp(data, data, 5); +__builtin_riscv_esp_vld_h_64_ip(data, 1008, 4); +__builtin_riscv_esp_vld_h_64_xp(data, data, 2); +__builtin_riscv_esp_vld_l_64_ip(data, -304, 6); +__builtin_riscv_esp_vld_l_64_xp(data, data, 6); +__builtin_riscv_esp_vst_128_ip(0, data, -1216); +__builtin_riscv_esp_vst_128_xp(data, 6, data); +__builtin_riscv_esp_vst_h_64_ip(1, data, -456); +__builtin_riscv_esp_vst_h_64_xp(data, 2, data); +__builtin_riscv_esp_vst_l_64_ip(6, data, 664); +__builtin_riscv_esp_vst_l_64_xp(data, 4, data); +__builtin_riscv_esp_slci_2q(2, 0, 14); +__builtin_riscv_esp_slcxxp_2q(data, data, 0, 1); +__builtin_riscv_esp_src_q(7, 3, 2); +__builtin_riscv_esp_src_q_ld_ip(1, data, 4, 1168, 4); +__builtin_riscv_esp_src_q_ld_xp(data, 0, data, 1, 0); +__builtin_riscv_esp_src_q_qup(3, 3, 0); +__builtin_riscv_esp_srci_2q(7, 4, 1); +__builtin_riscv_esp_srcmb_s16_q_qacc(2, 1, 5); +__builtin_riscv_esp_srcmb_s16_qacc(data, 0, 7); +__builtin_riscv_esp_srcmb_s8_q_qacc(7, 0, 3); +__builtin_riscv_esp_srcmb_s8_qacc(data, 1, 3); +__builtin_riscv_esp_srcmb_u16_q_qacc(6, 1, 0); +__builtin_riscv_esp_srcmb_u16_qacc(data, 0, 0); +__builtin_riscv_esp_srcmb_u8_q_qacc(6, 0, 7); +__builtin_riscv_esp_srcmb_u8_qacc(data, 1, 2); +__builtin_riscv_esp_srcq_128_st_incp(0, 5, data); +__builtin_riscv_esp_srcxxp_2q(data, data, 7, 5); +__builtin_riscv_esp_srs_s_xacc(data, data); +__builtin_riscv_esp_srs_u_xacc(data, data); +__builtin_riscv_esp_vsl_32(0, 3); +__builtin_riscv_esp_vsld_16(6, 4, 4); +__builtin_riscv_esp_vsld_32(2, 7, 5); +__builtin_riscv_esp_vsld_8(1, 0, 0); +__builtin_riscv_esp_vsr_s32(6, 2); +__builtin_riscv_esp_vsr_u32(3, 2); +__builtin_riscv_esp_vsrd_16(6, 2, 1); +__builtin_riscv_esp_vsrd_32(7, 5, 4); +__builtin_riscv_esp_vsrd_8(2, 1, 4); +__builtin_riscv_esp_st_s_xacc_ip(data, 912); +__builtin_riscv_esp_st_u_xacc_ip(data, -112); +} diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index dc81fd74c7e5ec..58fb15d3240344 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -81,7 +81,7 @@ // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}} +// RISCV32-NEXT: note: valid target CPU values are: esp32p4, generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}} // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' @@ -89,7 +89,7 @@ // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV32-NEXT: note: valid target CPU values are: esp32p4, generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}} // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 9a63d14b0ef0a1..3220057476ea18 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1889,3 +1889,7 @@ let TargetPrefix = "riscv" in { include "llvm/IR/IntrinsicsRISCVXTHead.td" include "llvm/IR/IntrinsicsRISCVXsf.td" include "llvm/IR/IntrinsicsRISCVXCV.td" + +// Generated code +// -------------- +include "llvm/IR/IntrinsicsRISCVESP32P4.td" \ No newline at end of file diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVESP32P4.td b/llvm/include/llvm/IR/IntrinsicsRISCVESP32P4.td new file mode 100644 index 00000000000000..c1a11f90f12dd2 --- /dev/null +++ b/llvm/include/llvm/IR/IntrinsicsRISCVESP32P4.td @@ -0,0 +1,1065 @@ +let TargetPrefix = "riscv" in { +def int_riscv_esp_vcmulas_s16_qacc_h: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s16_qacc_h">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s16_qacc_h_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s16_qacc_h_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s16_qacc_h_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s16_qacc_h_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s16_qacc_l: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s16_qacc_l">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s16_qacc_l_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s16_qacc_l_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s16_qacc_l_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s16_qacc_l_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s8_qacc_h: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s8_qacc_h">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s8_qacc_h_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s8_qacc_h_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s8_qacc_h_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s8_qacc_h_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s8_qacc_l: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s8_qacc_l">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s8_qacc_l_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s8_qacc_l_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmulas_s8_qacc_l_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vcmulas_s8_qacc_l_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_qacc: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_qacc_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_qacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_qacc_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_qacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_qacc_st_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_qacc_st_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_qacc_st_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_qacc_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_xacc: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_xacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_xacc_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_xacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_xacc_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_xacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_xacc_st_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_xacc_st_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_xacc_st_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_xacc_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_qacc: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_qacc_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_qacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_qacc_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_qacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_qacc_st_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_qacc_st_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_qacc_st_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_qacc_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_xacc: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_xacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_xacc_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_xacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_xacc_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_xacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_xacc_st_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_xacc_st_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_xacc_st_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_xacc_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_qacc: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_qacc_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_qacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_qacc_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_qacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_qacc_st_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_qacc_st_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_qacc_st_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_qacc_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_xacc: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_xacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_xacc_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_xacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_xacc_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_xacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_xacc_st_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_xacc_st_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_xacc_st_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_xacc_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_qacc: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_qacc_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_qacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_qacc_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_qacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_qacc_st_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_qacc_st_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_qacc_st_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_qacc_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_xacc: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_xacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_xacc_ld_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_xacc_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_xacc_ld_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_xacc_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_xacc_st_ip: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_xacc_st_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_xacc_st_xp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_xacc_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s16_qacc_ldbc_incp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s16_qacc_ldbc_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_s8_qacc_ldbc_incp: ClangBuiltin<"__builtin_riscv_esp_vmulas_s8_qacc_ldbc_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u16_qacc_ldbc_incp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u16_qacc_ldbc_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmulas_u8_qacc_ldbc_incp: ClangBuiltin<"__builtin_riscv_esp_vmulas_u8_qacc_ldbc_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsmulas_s16_qacc: ClangBuiltin<"__builtin_riscv_esp_vsmulas_s16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsmulas_s16_qacc_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsmulas_s16_qacc_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsmulas_s8_qacc: ClangBuiltin<"__builtin_riscv_esp_vsmulas_s8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsmulas_s8_qacc_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsmulas_s8_qacc_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsmulas_u16_qacc: ClangBuiltin<"__builtin_riscv_esp_vsmulas_u16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsmulas_u16_qacc_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsmulas_u16_qacc_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsmulas_u8_qacc: ClangBuiltin<"__builtin_riscv_esp_vsmulas_u8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsmulas_u8_qacc_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsmulas_u8_qacc_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_s16: ClangBuiltin<"__builtin_riscv_esp_cmul_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_s16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_cmul_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_s16_st_incp: ClangBuiltin<"__builtin_riscv_esp_cmul_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_s8: ClangBuiltin<"__builtin_riscv_esp_cmul_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_s8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_cmul_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_s8_st_incp: ClangBuiltin<"__builtin_riscv_esp_cmul_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_u16: ClangBuiltin<"__builtin_riscv_esp_cmul_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_u16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_cmul_u16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_u16_st_incp: ClangBuiltin<"__builtin_riscv_esp_cmul_u16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_u8: ClangBuiltin<"__builtin_riscv_esp_cmul_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_u8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_cmul_u8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_cmul_u8_st_incp: ClangBuiltin<"__builtin_riscv_esp_cmul_u8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_max_s16_a: ClangBuiltin<"__builtin_riscv_esp_max_s16_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_max_s32_a: ClangBuiltin<"__builtin_riscv_esp_max_s32_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_max_s8_a: ClangBuiltin<"__builtin_riscv_esp_max_s8_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_max_u16_a: ClangBuiltin<"__builtin_riscv_esp_max_u16_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_max_u32_a: ClangBuiltin<"__builtin_riscv_esp_max_u32_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_max_u8_a: ClangBuiltin<"__builtin_riscv_esp_max_u8_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_min_s16_a: ClangBuiltin<"__builtin_riscv_esp_min_s16_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_min_s32_a: ClangBuiltin<"__builtin_riscv_esp_min_s32_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_min_s8_a: ClangBuiltin<"__builtin_riscv_esp_min_s8_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_min_u16_a: ClangBuiltin<"__builtin_riscv_esp_min_u16_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_min_u32_a: ClangBuiltin<"__builtin_riscv_esp_min_u32_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_min_u8_a: ClangBuiltin<"__builtin_riscv_esp_min_u8_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vabs_16: ClangBuiltin<"__builtin_riscv_esp_vabs_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vabs_32: ClangBuiltin<"__builtin_riscv_esp_vabs_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vabs_8: ClangBuiltin<"__builtin_riscv_esp_vabs_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s16: ClangBuiltin<"__builtin_riscv_esp_vadd_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s32: ClangBuiltin<"__builtin_riscv_esp_vadd_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s32_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_s32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s32_st_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_s32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s8: ClangBuiltin<"__builtin_riscv_esp_vadd_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_s8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u16: ClangBuiltin<"__builtin_riscv_esp_vadd_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_u16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_u16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u32: ClangBuiltin<"__builtin_riscv_esp_vadd_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u32_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_u32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u32_st_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_u32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u8: ClangBuiltin<"__builtin_riscv_esp_vadd_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_u8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vadd_u8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vadd_u8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vclamp_s16: ClangBuiltin<"__builtin_riscv_esp_vclamp_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s16: ClangBuiltin<"__builtin_riscv_esp_vmax_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s32: ClangBuiltin<"__builtin_riscv_esp_vmax_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s32_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_s32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s32_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_s32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s8: ClangBuiltin<"__builtin_riscv_esp_vmax_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_s8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u16: ClangBuiltin<"__builtin_riscv_esp_vmax_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_u16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_u16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u32: ClangBuiltin<"__builtin_riscv_esp_vmax_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u32_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_u32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u32_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_u32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u8: ClangBuiltin<"__builtin_riscv_esp_vmax_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_u8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmax_u8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmax_u8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s16: ClangBuiltin<"__builtin_riscv_esp_vmin_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s32: ClangBuiltin<"__builtin_riscv_esp_vmin_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s32_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_s32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s32_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_s32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s8: ClangBuiltin<"__builtin_riscv_esp_vmin_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_s8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u16: ClangBuiltin<"__builtin_riscv_esp_vmin_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_u16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_u16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u32: ClangBuiltin<"__builtin_riscv_esp_vmin_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u32_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_u32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u32_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_u32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u8: ClangBuiltin<"__builtin_riscv_esp_vmin_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_u8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmin_u8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmin_u8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_s16: ClangBuiltin<"__builtin_riscv_esp_vmul_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_s16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmul_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_s16_s8xs8: ClangBuiltin<"__builtin_riscv_esp_vmul_s16_s8xs8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_s16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmul_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_s32_s16xs16: ClangBuiltin<"__builtin_riscv_esp_vmul_s32_s16xs16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_s8: ClangBuiltin<"__builtin_riscv_esp_vmul_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_s8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmul_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_s8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmul_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_u16: ClangBuiltin<"__builtin_riscv_esp_vmul_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_u16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmul_u16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_u16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmul_u16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_u8: ClangBuiltin<"__builtin_riscv_esp_vmul_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_u8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vmul_u8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vmul_u8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vmul_u8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vprelu_s16: ClangBuiltin<"__builtin_riscv_esp_vprelu_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vprelu_s8: ClangBuiltin<"__builtin_riscv_esp_vprelu_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vrelu_s16: ClangBuiltin<"__builtin_riscv_esp_vrelu_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vrelu_s8: ClangBuiltin<"__builtin_riscv_esp_vrelu_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vsadds_s16: ClangBuiltin<"__builtin_riscv_esp_vsadds_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsadds_s8: ClangBuiltin<"__builtin_riscv_esp_vsadds_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsadds_u16: ClangBuiltin<"__builtin_riscv_esp_vsadds_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsadds_u8: ClangBuiltin<"__builtin_riscv_esp_vsadds_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsat_s16: ClangBuiltin<"__builtin_riscv_esp_vsat_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsat_s32: ClangBuiltin<"__builtin_riscv_esp_vsat_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsat_s8: ClangBuiltin<"__builtin_riscv_esp_vsat_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsat_u16: ClangBuiltin<"__builtin_riscv_esp_vsat_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsat_u32: ClangBuiltin<"__builtin_riscv_esp_vsat_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsat_u8: ClangBuiltin<"__builtin_riscv_esp_vsat_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vssubs_s16: ClangBuiltin<"__builtin_riscv_esp_vssubs_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vssubs_s8: ClangBuiltin<"__builtin_riscv_esp_vssubs_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vssubs_u16: ClangBuiltin<"__builtin_riscv_esp_vssubs_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vssubs_u8: ClangBuiltin<"__builtin_riscv_esp_vssubs_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s16: ClangBuiltin<"__builtin_riscv_esp_vsub_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s32: ClangBuiltin<"__builtin_riscv_esp_vsub_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s32_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_s32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s32_st_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_s32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s8: ClangBuiltin<"__builtin_riscv_esp_vsub_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_s8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_s8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_s8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u16: ClangBuiltin<"__builtin_riscv_esp_vsub_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_u16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u16_st_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_u16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u32: ClangBuiltin<"__builtin_riscv_esp_vsub_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u32_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_u32_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u32_st_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_u32_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u8: ClangBuiltin<"__builtin_riscv_esp_vsub_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u8_ld_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_u8_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsub_u8_st_incp: ClangBuiltin<"__builtin_riscv_esp_vsub_u8_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_addx2: ClangBuiltin<"__builtin_riscv_esp_addx2">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_addx4: ClangBuiltin<"__builtin_riscv_esp_addx4">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_sat: ClangBuiltin<"__builtin_riscv_esp_sat">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_subx2: ClangBuiltin<"__builtin_riscv_esp_subx2">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_subx4: ClangBuiltin<"__builtin_riscv_esp_subx4">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_andq: ClangBuiltin<"__builtin_riscv_esp_andq">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_notq: ClangBuiltin<"__builtin_riscv_esp_notq">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_orq: ClangBuiltin<"__builtin_riscv_esp_orq">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_xorq: ClangBuiltin<"__builtin_riscv_esp_xorq">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_eq_s16: ClangBuiltin<"__builtin_riscv_esp_vcmp_eq_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_eq_s32: ClangBuiltin<"__builtin_riscv_esp_vcmp_eq_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_eq_s8: ClangBuiltin<"__builtin_riscv_esp_vcmp_eq_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_eq_u16: ClangBuiltin<"__builtin_riscv_esp_vcmp_eq_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_eq_u32: ClangBuiltin<"__builtin_riscv_esp_vcmp_eq_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_eq_u8: ClangBuiltin<"__builtin_riscv_esp_vcmp_eq_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_gt_s16: ClangBuiltin<"__builtin_riscv_esp_vcmp_gt_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_gt_s32: ClangBuiltin<"__builtin_riscv_esp_vcmp_gt_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_gt_s8: ClangBuiltin<"__builtin_riscv_esp_vcmp_gt_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_gt_u16: ClangBuiltin<"__builtin_riscv_esp_vcmp_gt_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_gt_u32: ClangBuiltin<"__builtin_riscv_esp_vcmp_gt_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_gt_u8: ClangBuiltin<"__builtin_riscv_esp_vcmp_gt_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_lt_s16: ClangBuiltin<"__builtin_riscv_esp_vcmp_lt_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_lt_s32: ClangBuiltin<"__builtin_riscv_esp_vcmp_lt_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_lt_s8: ClangBuiltin<"__builtin_riscv_esp_vcmp_lt_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_lt_u16: ClangBuiltin<"__builtin_riscv_esp_vcmp_lt_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_lt_u32: ClangBuiltin<"__builtin_riscv_esp_vcmp_lt_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vcmp_lt_u8: ClangBuiltin<"__builtin_riscv_esp_vcmp_lt_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_mov_s16_qacc: ClangBuiltin<"__builtin_riscv_esp_mov_s16_qacc">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_mov_s8_qacc: ClangBuiltin<"__builtin_riscv_esp_mov_s8_qacc">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_mov_u16_qacc: ClangBuiltin<"__builtin_riscv_esp_mov_u16_qacc">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_mov_u8_qacc: ClangBuiltin<"__builtin_riscv_esp_mov_u8_qacc">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_movi_16_a: ClangBuiltin<"__builtin_riscv_esp_movi_16_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_movi_16_q: ClangBuiltin<"__builtin_riscv_esp_movi_16_q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_movi_32_a: ClangBuiltin<"__builtin_riscv_esp_movi_32_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_movi_32_q: ClangBuiltin<"__builtin_riscv_esp_movi_32_q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_movi_8_a: ClangBuiltin<"__builtin_riscv_esp_movi_8_a">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_movi_8_q: ClangBuiltin<"__builtin_riscv_esp_movi_8_q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_movx_r_cfg: ClangBuiltin<"__builtin_riscv_esp_movx_r_cfg">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_r_fft_bit_width: ClangBuiltin<"__builtin_riscv_esp_movx_r_fft_bit_width">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_r_perf: ClangBuiltin<"__builtin_riscv_esp_movx_r_perf">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_movx_r_sar: ClangBuiltin<"__builtin_riscv_esp_movx_r_sar">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_r_sar_bytes: ClangBuiltin<"__builtin_riscv_esp_movx_r_sar_bytes">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_r_xacc_h: ClangBuiltin<"__builtin_riscv_esp_movx_r_xacc_h">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_r_xacc_l: ClangBuiltin<"__builtin_riscv_esp_movx_r_xacc_l">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_w_cfg: ClangBuiltin<"__builtin_riscv_esp_movx_w_cfg">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_w_fft_bit_width: ClangBuiltin<"__builtin_riscv_esp_movx_w_fft_bit_width">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_w_perf: ClangBuiltin<"__builtin_riscv_esp_movx_w_perf">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_w_sar: ClangBuiltin<"__builtin_riscv_esp_movx_w_sar">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_w_sar_bytes: ClangBuiltin<"__builtin_riscv_esp_movx_w_sar_bytes">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_w_xacc_h: ClangBuiltin<"__builtin_riscv_esp_movx_w_xacc_h">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_movx_w_xacc_l: ClangBuiltin<"__builtin_riscv_esp_movx_w_xacc_l">, + Intrinsic<[], [llvm_i32_ty], []>; + +def int_riscv_esp_vext_s16: ClangBuiltin<"__builtin_riscv_esp_vext_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vext_s8: ClangBuiltin<"__builtin_riscv_esp_vext_s8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vext_u16: ClangBuiltin<"__builtin_riscv_esp_vext_u16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vext_u8: ClangBuiltin<"__builtin_riscv_esp_vext_u8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vunzip_16: ClangBuiltin<"__builtin_riscv_esp_vunzip_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vunzip_32: ClangBuiltin<"__builtin_riscv_esp_vunzip_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vunzip_8: ClangBuiltin<"__builtin_riscv_esp_vunzip_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vunzipt_16: ClangBuiltin<"__builtin_riscv_esp_vunzipt_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vunzipt_8: ClangBuiltin<"__builtin_riscv_esp_vunzipt_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vzip_16: ClangBuiltin<"__builtin_riscv_esp_vzip_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vzip_32: ClangBuiltin<"__builtin_riscv_esp_vzip_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vzip_8: ClangBuiltin<"__builtin_riscv_esp_vzip_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vzipt_16: ClangBuiltin<"__builtin_riscv_esp_vzipt_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vzipt_8: ClangBuiltin<"__builtin_riscv_esp_vzipt_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_zero_q: ClangBuiltin<"__builtin_riscv_esp_zero_q">, + Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_zero_qacc: ClangBuiltin<"__builtin_riscv_esp_zero_qacc">, + Intrinsic<[], [], []>; + +def int_riscv_esp_zero_xacc: ClangBuiltin<"__builtin_riscv_esp_zero_xacc">, + Intrinsic<[], [], []>; + +def int_riscv_esp_fft_ams_s16_ld_incp: ClangBuiltin<"__builtin_riscv_esp_fft_ams_s16_ld_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_fft_ams_s16_ld_incp_uaup: ClangBuiltin<"__builtin_riscv_esp_fft_ams_s16_ld_incp_uaup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_fft_ams_s16_ld_r32_decp: ClangBuiltin<"__builtin_riscv_esp_fft_ams_s16_ld_r32_decp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_fft_ams_s16_st_incp: ClangBuiltin<"__builtin_riscv_esp_fft_ams_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_fft_bitrev: ClangBuiltin<"__builtin_riscv_esp_fft_bitrev">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_fft_cmul_s16_ld_xp: ClangBuiltin<"__builtin_riscv_esp_fft_cmul_s16_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_fft_cmul_s16_st_xp: ClangBuiltin<"__builtin_riscv_esp_fft_cmul_s16_st_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_fft_r2bf_s16: ClangBuiltin<"__builtin_riscv_esp_fft_r2bf_s16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_fft_r2bf_s16_st_incp: ClangBuiltin<"__builtin_riscv_esp_fft_r2bf_s16_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_fft_vst_r32_decp: ClangBuiltin<"__builtin_riscv_esp_fft_vst_r32_decp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_ld_128_usar_ip: ClangBuiltin<"__builtin_riscv_esp_ld_128_usar_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_ld_128_usar_xp: ClangBuiltin<"__builtin_riscv_esp_ld_128_usar_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ld_xacc_ip: ClangBuiltin<"__builtin_riscv_esp_ld_xacc_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ldqa_s16_128_ip: ClangBuiltin<"__builtin_riscv_esp_ldqa_s16_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ldqa_s16_128_xp: ClangBuiltin<"__builtin_riscv_esp_ldqa_s16_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_ldqa_s8_128_ip: ClangBuiltin<"__builtin_riscv_esp_ldqa_s8_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ldqa_s8_128_xp: ClangBuiltin<"__builtin_riscv_esp_ldqa_s8_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_ldqa_u16_128_ip: ClangBuiltin<"__builtin_riscv_esp_ldqa_u16_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ldqa_u16_128_xp: ClangBuiltin<"__builtin_riscv_esp_ldqa_u16_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_ldqa_u8_128_ip: ClangBuiltin<"__builtin_riscv_esp_ldqa_u8_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ldqa_u8_128_xp: ClangBuiltin<"__builtin_riscv_esp_ldqa_u8_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_vldbc_16_ip: ClangBuiltin<"__builtin_riscv_esp_vldbc_16_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldbc_16_xp: ClangBuiltin<"__builtin_riscv_esp_vldbc_16_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vldbc_32_ip: ClangBuiltin<"__builtin_riscv_esp_vldbc_32_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldbc_32_xp: ClangBuiltin<"__builtin_riscv_esp_vldbc_32_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vldbc_8_ip: ClangBuiltin<"__builtin_riscv_esp_vldbc_8_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldbc_8_xp: ClangBuiltin<"__builtin_riscv_esp_vldbc_8_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vldext_s16_ip: ClangBuiltin<"__builtin_riscv_esp_vldext_s16_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldext_s16_xp: ClangBuiltin<"__builtin_riscv_esp_vldext_s16_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldext_s8_ip: ClangBuiltin<"__builtin_riscv_esp_vldext_s8_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldext_s8_xp: ClangBuiltin<"__builtin_riscv_esp_vldext_s8_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldext_u16_ip: ClangBuiltin<"__builtin_riscv_esp_vldext_u16_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldext_u16_xp: ClangBuiltin<"__builtin_riscv_esp_vldext_u16_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldext_u8_ip: ClangBuiltin<"__builtin_riscv_esp_vldext_u8_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldext_u8_xp: ClangBuiltin<"__builtin_riscv_esp_vldext_u8_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vldhbc_16_incp: ClangBuiltin<"__builtin_riscv_esp_vldhbc_16_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_ld_qacc_h_h_128_ip: ClangBuiltin<"__builtin_riscv_esp_ld_qacc_h_h_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ld_qacc_h_l_128_ip: ClangBuiltin<"__builtin_riscv_esp_ld_qacc_h_l_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ld_qacc_l_h_128_ip: ClangBuiltin<"__builtin_riscv_esp_ld_qacc_l_h_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ld_qacc_l_l_128_ip: ClangBuiltin<"__builtin_riscv_esp_ld_qacc_l_l_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ld_ua_state_ip: ClangBuiltin<"__builtin_riscv_esp_ld_ua_state_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_ldxq_32: ClangBuiltin<"__builtin_riscv_esp_ldxq_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_st_qacc_h_h_128_ip: ClangBuiltin<"__builtin_riscv_esp_st_qacc_h_h_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_st_qacc_h_l_128_ip: ClangBuiltin<"__builtin_riscv_esp_st_qacc_h_l_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_st_qacc_l_h_128_ip: ClangBuiltin<"__builtin_riscv_esp_st_qacc_l_h_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_st_qacc_l_l_128_ip: ClangBuiltin<"__builtin_riscv_esp_st_qacc_l_l_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_st_ua_state_ip: ClangBuiltin<"__builtin_riscv_esp_st_ua_state_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_stxq_32: ClangBuiltin<"__builtin_riscv_esp_stxq_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vld_128_ip: ClangBuiltin<"__builtin_riscv_esp_vld_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vld_128_xp: ClangBuiltin<"__builtin_riscv_esp_vld_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vld_h_64_ip: ClangBuiltin<"__builtin_riscv_esp_vld_h_64_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vld_h_64_xp: ClangBuiltin<"__builtin_riscv_esp_vld_h_64_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vld_l_64_ip: ClangBuiltin<"__builtin_riscv_esp_vld_l_64_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vld_l_64_xp: ClangBuiltin<"__builtin_riscv_esp_vld_l_64_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vst_128_ip: ClangBuiltin<"__builtin_riscv_esp_vst_128_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vst_128_xp: ClangBuiltin<"__builtin_riscv_esp_vst_128_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vst_h_64_ip: ClangBuiltin<"__builtin_riscv_esp_vst_h_64_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vst_h_64_xp: ClangBuiltin<"__builtin_riscv_esp_vst_h_64_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_vst_l_64_ip: ClangBuiltin<"__builtin_riscv_esp_vst_l_64_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vst_l_64_xp: ClangBuiltin<"__builtin_riscv_esp_vst_l_64_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_slci_2q: ClangBuiltin<"__builtin_riscv_esp_slci_2q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_slcxxp_2q: ClangBuiltin<"__builtin_riscv_esp_slcxxp_2q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_src_q: ClangBuiltin<"__builtin_riscv_esp_src_q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_src_q_ld_ip: ClangBuiltin<"__builtin_riscv_esp_src_q_ld_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_src_q_ld_xp: ClangBuiltin<"__builtin_riscv_esp_src_q_ld_xp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_src_q_qup: ClangBuiltin<"__builtin_riscv_esp_src_q_qup">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_srci_2q: ClangBuiltin<"__builtin_riscv_esp_srci_2q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcmb_s16_q_qacc: ClangBuiltin<"__builtin_riscv_esp_srcmb_s16_q_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcmb_s16_qacc: ClangBuiltin<"__builtin_riscv_esp_srcmb_s16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcmb_s8_q_qacc: ClangBuiltin<"__builtin_riscv_esp_srcmb_s8_q_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcmb_s8_qacc: ClangBuiltin<"__builtin_riscv_esp_srcmb_s8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcmb_u16_q_qacc: ClangBuiltin<"__builtin_riscv_esp_srcmb_u16_q_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcmb_u16_qacc: ClangBuiltin<"__builtin_riscv_esp_srcmb_u16_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcmb_u8_q_qacc: ClangBuiltin<"__builtin_riscv_esp_srcmb_u8_q_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcmb_u8_qacc: ClangBuiltin<"__builtin_riscv_esp_srcmb_u8_qacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcq_128_st_incp: ClangBuiltin<"__builtin_riscv_esp_srcq_128_st_incp">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_srcxxp_2q: ClangBuiltin<"__builtin_riscv_esp_srcxxp_2q">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_srs_s_xacc: ClangBuiltin<"__builtin_riscv_esp_srs_s_xacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_srs_u_xacc: ClangBuiltin<"__builtin_riscv_esp_srs_u_xacc">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; + +def int_riscv_esp_vsl_32: ClangBuiltin<"__builtin_riscv_esp_vsl_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsld_16: ClangBuiltin<"__builtin_riscv_esp_vsld_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsld_32: ClangBuiltin<"__builtin_riscv_esp_vsld_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsld_8: ClangBuiltin<"__builtin_riscv_esp_vsld_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsr_s32: ClangBuiltin<"__builtin_riscv_esp_vsr_s32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsr_u32: ClangBuiltin<"__builtin_riscv_esp_vsr_u32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsrd_16: ClangBuiltin<"__builtin_riscv_esp_vsrd_16">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsrd_32: ClangBuiltin<"__builtin_riscv_esp_vsrd_32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_vsrd_8: ClangBuiltin<"__builtin_riscv_esp_vsrd_8">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg>, ImmArg>, ImmArg>]>; + +def int_riscv_esp_st_s_xacc_ip: ClangBuiltin<"__builtin_riscv_esp_st_s_xacc_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + +def int_riscv_esp_st_u_xacc_ip: ClangBuiltin<"__builtin_riscv_esp_st_u_xacc_ip">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg>]>; + + +} diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index db2e4ca92ae40a..0654b76e3fbf84 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -71,6 +71,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"xcvmac", {1, 0}}, {"xcvmem", {1, 0}}, {"xcvsimd", {1, 0}}, + {"xesppie", {1, 0}}, {"xsfvcp", {1, 0}}, {"xsfvfnrclipxfqf", {1, 0}}, {"xsfvfwmaccqqq", {1, 0}}, diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index f6e8386aff4510..4a573236dcf24a 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -442,6 +442,14 @@ struct RISCVOperand final : public MCParsedAsmOperand { } } + static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) { + if (auto *CE = dyn_cast(Expr)) { + int64_t Value = CE->getValue(); + return Value >= MinValue && Value <= MaxValue; + } + return false; + } + bool isToken() const override { return Kind == KindTy::Token; } bool isReg() const override { return Kind == KindTy::Register; } bool isV0Reg() const { @@ -467,6 +475,43 @@ struct RISCVOperand final : public MCParsedAsmOperand { bool isRlist() const { return Kind == KindTy::Rlist; } bool isSpimm() const { return Kind == KindTy::Spimm; } + bool isImm(int64_t MinValue, int64_t MaxValue) const { + return Kind == KindTy::Immediate && inRange(getImm(), MinValue, MaxValue); + } + + bool isImm8() const { + // The addi instruction maybe expaned to addmi and addi. + return isImm((-32768 - 128), (32512 + 127)); + } + + bool isSelect_2() const { return isImm(0, 1); } + + bool isSelect_4() const { return isImm(0, 3); } + + bool isSelect_8() const { return isImm(0, 7); } + + bool isSelect_16() const { return isImm(0, 16); } + + bool isOffset_16_16() const { + return isImm(-128, 112) && + ((cast(getImm())->getValue() & 0xf) == 0); + } + + bool isOffset_256_8() const { + return isImm(-1024, 1016) && + ((cast(getImm())->getValue() & 0x7) == 0); + } + + bool isOffset_256_16() const { + return isImm(-2048, 2032) && + ((cast(getImm())->getValue() & 0xf) == 0); + } + + bool isOffset_256_4() const { + return isImm(-512, 508) && + ((cast(getImm())->getValue() & 0x3) == 0); + } + bool isGPR() const { return Kind == KindTy::Register && RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); @@ -841,6 +886,54 @@ struct RISCVOperand final : public MCParsedAsmOperand { VK == RISCVMCExpr::VK_RISCV_None; } + bool isUImm9() const { + if (!isImm()) + return false; + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<9>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + + bool isUImm10() const { + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + else + IsValid = isUInt<10>(fixImmediateForRV32(Imm, isRV64Imm())); + return IsValid && VK == RISCVMCExpr::VK_RISCV_None; + } + + bool isUImm12() const { + if (!isImm()) + return false; + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<12>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + + bool isUImm13() const { + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + else + IsValid = isUInt<13>(fixImmediateForRV32(Imm, isRV64Imm())); + return IsValid && VK == RISCVMCExpr::VK_RISCV_None; + } + bool isUImm10Lsb00NonZero() const { if (!isImm()) return false; @@ -1533,6 +1626,10 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return generateImmOutOfRangeError( Operands, ErrorInfo, -(1 << 11), (1 << 11) - 32, "immediate must be a multiple of 32 bytes in the range"); + case Match_InvalidUImm12: + return generateImmOutOfRangeError( + Operands, ErrorInfo, 0, (1 << 12) - 1, + "immediate must be in the range"); case Match_InvalidSImm13Lsb0: return generateImmOutOfRangeError( Operands, ErrorInfo, -(1 << 12), (1 << 12) - 2, diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt index ac88cd49db4e4b..30e4a150922899 100644 --- a/llvm/lib/Target/RISCV/CMakeLists.txt +++ b/llvm/lib/Target/RISCV/CMakeLists.txt @@ -43,6 +43,7 @@ add_llvm_target(RISCVCodeGen RISCVInstrInfo.cpp RISCVISelDAGToDAG.cpp RISCVISelLowering.cpp + RISCVESP32P4ISelLowering.cpp RISCVMachineFunctionInfo.cpp RISCVMergeBaseOffset.cpp RISCVOptWInstrs.cpp diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 4dd039159e29dc..0ad3325e7cb703 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -74,6 +74,20 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeGPRPIERegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + auto bit4 = RegNo & 0x8; + RegNo |= (bit4 << 4); + RegNo |= (1 << 3); + if ((RegNo >= 8 && RegNo <= 15) || (RegNo >= 24 && RegNo <= 31)) { + MCRegister Reg = RISCV::X0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; + } + return MCDisassembler::Fail; +} + static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { @@ -255,6 +269,21 @@ static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } +static const unsigned QRDecoderTable[] = {RISCV::Q0, RISCV::Q1, RISCV::Q2, + RISCV::Q3, RISCV::Q4, RISCV::Q5, + RISCV::Q6, RISCV::Q7}; + +static DecodeStatus DecodeQRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= std::size(QRDecoderTable)) + return MCDisassembler::Fail; + + unsigned Reg = QRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { @@ -374,6 +403,43 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder); +static DecodeStatus decodeSelect_2Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder); + +static DecodeStatus decodeSelect_4Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder); + +static DecodeStatus decodeSelect_8Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder); + +static DecodeStatus decodeSelect_16Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder); + +static DecodeStatus decodeOffset_16_16Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder); + +static DecodeStatus decodeOffset_256_8Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder); + +static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder); + +static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder); + +static DecodeStatus decodeUImm13_Step4Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder); + +static DecodeStatus decodeUImm10_Step4Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder); + #include "RISCVGenDisassemblerTables.inc" static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, @@ -493,6 +559,90 @@ static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, return MCDisassembler::Success; } +static DecodeStatus decodeSelect_2Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeSelect_4Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeSelect_8Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeSelect_16Operand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<8>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_16_16Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<8>(Imm) && "Invalid immediate"); + auto ImmSigned = SignExtend64<4>(Imm); + Inst.addOperand(MCOperand::createImm(ImmSigned * 16)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_256_8Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<16>(Imm) && "Invalid immediate"); + auto ImmSigned = SignExtend64<4>(Imm); + Inst.addOperand(MCOperand::createImm(ImmSigned * 8)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<16>(Imm) && "Invalid immediate"); + auto ImmSigned = SignExtend64<4>(Imm); + Inst.addOperand(MCOperand::createImm(ImmSigned * 16)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isInt<16>(Imm) && "Invalid immediate"); + auto ImmSigned = SignExtend64<4>(Imm); + Inst.addOperand(MCOperand::createImm(ImmSigned * 4)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeUImm13_Step4Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<13>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm((Imm * 2) * 2)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeUImm10_Step4Operand(MCInst &Inst, int64_t Imm, + int64_t Address, + const void *Decoder) { + assert(isUInt<10>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm * 2)); + return MCDisassembler::Success; +} + // Add implied SP operand for C.*SP compressed instructions. The SP operand // isn't explicitly encoded in the instruction. void RISCVDisassembler::addSPOperands(MCInst &MI) const { @@ -595,6 +745,9 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE( RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32, "SiFive FP32-to-int8 Ranged Clip Instructions opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorESP32P4, DecoderTableESP32P432, + "ESP32P4 Instruction opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation custom opcode table"); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index d7f7859ce4399b..faefd0e32514f8 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -51,6 +51,7 @@ enum { InstFormatCSB = 20, InstFormatCSH = 21, InstFormatOther = 22, + InstFormatESP32P4 = 23, InstFormatMask = 31, InstFormatShift = 0, @@ -294,7 +295,9 @@ enum OperandType : unsigned { OPERAND_UIMM8_GE32, OPERAND_UIMM9_LSB000, OPERAND_UIMM10_LSB00_NONZERO, + OPERAND_UIMM10_STEP4, OPERAND_UIMM12, + OPERAND_UIMM13_STEP4, OPERAND_ZERO, OPERAND_SIMM5, OPERAND_SIMM5_PLUS1, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index bd899495812f44..bff84bb9aaffad 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -329,3 +329,119 @@ const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) { return getRegisterName(Reg, ArchRegNames ? RISCV::NoRegAltName : RISCV::ABIRegAltName); } + +void RISCVInstPrinter::printImm8_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert(isInt<8>(Value) && + "Invalid argument, value must be in ranges [-128,127]"); + O << Value; + } else { + printOperand(MI, OpNum, STI, O); + } +} + +void RISCVInstPrinter::printSelect_2_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 1) && + "Invalid argument, value must be in range [0,1]"); + O << Value; + } else + printOperand(MI, OpNum, STI, O); +} + +void RISCVInstPrinter::printSelect_4_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 3) && + "Invalid argument, value must be in range [0,3]"); + O << Value; + } else + printOperand(MI, OpNum, STI, O); +} + +void RISCVInstPrinter::printSelect_8_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 7) && + "Invalid argument, value must be in range [0,7]"); + O << Value; + } else + printOperand(MI, OpNum, STI, O); +} + +void RISCVInstPrinter::printSelect_16_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= 0 && Value <= 15) && + "Invalid argument, value must be in range [0,15]"); + O << Value; + } else + printOperand(MI, OpNum, STI, O); +} + +void RISCVInstPrinter::printOffset_16_16_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -128 && Value <= 112 && (Value & 0xf) == 0) && + "Invalid argument, value must be in range [-128,112], first 4 bits " + "should be zero"); + O << Value; + } else { + printOperand(MI, OpNum, STI, O); + } +} + +void RISCVInstPrinter::printOffset_256_8_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -1024 && Value <= 1016 && (Value & 0x7) == 0) && + "Invalid argument, value must be in range [-1024,1016], first 3 " + "bits should be zero"); + O << Value; + } else + printOperand(MI, OpNum, STI, O); +} + +void RISCVInstPrinter::printOffset_256_16_AsmOperand(const MCInst *MI, + int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -2048 && Value <= 2032 && (Value & 0xf) == 0) && + "Invalid argument, value must be in range [-2048,2032], first 4 " + "bits should be zero"); + O << Value; + } else { + printOperand(MI, OpNum, STI, O); + } +} + +void RISCVInstPrinter::printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNum).isImm()) { + int64_t Value = MI->getOperand(OpNum).getImm(); + assert((Value >= -512 && Value <= 508 && (Value & 0x3) == 0) && + "Invalid argument, value must be in range [-512,508], first 2 bits " + "should be zero"); + O << Value; + } else + printOperand(MI, OpNum, STI, O); +} diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h index 4512bd5f4c4b7a..6eab3bbfe2ff26 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -67,6 +67,26 @@ class RISCVInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg, unsigned AltIdx); + + void printImm8_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printSelect_2_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printSelect_4_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printSelect_8_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printSelect_16_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printOffset_16_16_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printOffset_256_8_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printOffset_256_16_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O); + void printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); }; } // namespace llvm diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index 5ea386c3c32a3d..c1e894a35b0bc1 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -100,6 +100,54 @@ class RISCVMCCodeEmitter : public MCCodeEmitter { unsigned getRegReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + + uint32_t getImm8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getSelect_2OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getSelect_4OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getSelect_8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getSelect_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint8_t getSelect_256OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int8_t getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int16_t getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int16_t getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + int16_t getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint16_t getUImm10_Step4Operand(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + uint16_t getUImm13_Step4Operand(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; }; } // end anonymous namespace @@ -493,7 +541,8 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, // FIXME: Sub kind binary exprs have chance of underflow. if (MIFrm == RISCVII::InstFormatJ) { FixupKind = RISCV::fixup_riscv_jal; - } else if (MIFrm == RISCVII::InstFormatB) { + } else if (MIFrm == RISCVII::InstFormatB || + MIFrm == RISCVII::InstFormatESP32P4) { FixupKind = RISCV::fixup_riscv_branch; } else if (MIFrm == RISCVII::InstFormatCJ) { FixupKind = RISCV::fixup_riscv_rvc_jump; @@ -563,4 +612,140 @@ unsigned RISCVMCCodeEmitter::getRegReg(const MCInst &MI, unsigned OpNo, return Op | Op1 << 5; } +uint32_t RISCVMCCodeEmitter::getImm8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int32_t Res = MO.getImm(); + + assert(((Res >= -128) && (Res <= 127)) && "Unexpected operand value!"); + + return (Res & 0xff); +} + +uint8_t +RISCVMCCodeEmitter::getSelect_2OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 1)) && "Unexpected operand value!"); + + return Res; +} + +uint8_t +RISCVMCCodeEmitter::getSelect_4OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 3)) && "Unexpected operand value!"); + + return Res; +} + +uint8_t +RISCVMCCodeEmitter::getSelect_8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 7)) && "Unexpected operand value!"); + + return Res; +} + +uint8_t +RISCVMCCodeEmitter::getSelect_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + uint8_t Res = static_cast(MO.getImm()); + + assert(((Res >= 0) && (Res <= 15)) && "Unexpected operand value!"); + + return Res; +} + +int8_t +RISCVMCCodeEmitter::getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int8_t Res = static_cast(MO.getImm()); + + assert(((Res >= -128) && (Res <= 112) && ((Res & 0xf) == 0)) && + "Unexpected operand value!"); + + return Res / 16; +} + +int16_t +RISCVMCCodeEmitter::getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int16_t Res = static_cast(MO.getImm()); + + assert(((Res >= -1024) && (Res <= 1016) && ((Res & 0x7) == 0)) && + "Unexpected operand value!"); + + return Res / 8; +} + +int16_t +RISCVMCCodeEmitter::getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int16_t Res = static_cast(MO.getImm()); + + assert(((Res >= -2048) && (Res <= 2032) && ((Res & 0xf) == 0)) && + "Unexpected operand value!"); + + return Res / 16; +} + +int16_t +RISCVMCCodeEmitter::getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + int16_t Res = static_cast(MO.getImm()); + + assert(((Res >= -512) && (Res <= 508) && ((Res & 0x3) == 0)) && + "Unexpected operand value!"); + + return Res / 4; +} + +uint16_t +RISCVMCCodeEmitter::getUImm10_Step4Operand(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + int16_t Res = static_cast(MO.getImm()); + assert((isUInt<10>(Res) && ((Res & 0x1) == 0)) && "Unexpected operand value!"); + return Res / 2; + } + return getImmOpValue(MI, OpNo, Fixups, STI); +} + +uint16_t +RISCVMCCodeEmitter::getUImm13_Step4Operand(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + int16_t Res = static_cast(MO.getImm()); + assert((isUInt<13>(Res) && ((Res & 0x1) == 0)) && "Unexpected operand value!"); + return Res / 2; + } + return getImmOpValue(MI, OpNo, Fixups, STI); +} #include "RISCVGenMCCodeEmitter.inc" diff --git a/llvm/lib/Target/RISCV/RISCVESP32P4ISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVESP32P4ISelLowering.cpp new file mode 100644 index 00000000000000..0ec3aaf3ad1dc0 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVESP32P4ISelLowering.cpp @@ -0,0 +1,8468 @@ +//==- RISCVESP32P4ISelLowering.cpp - ESP32 P4 DAG Lowering Implementation -===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the interfaces that Xtensa uses to lower LLVM code into a +// selection DAG. +// +//===----------------------------------------------------------------------===// + +#include "RISCVISelLowering.h" +#include "RISCVSubtarget.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" + +using namespace llvm; + +MachineBasicBlock *RISCVTargetLowering::emitDSPInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *MBB, const TargetInstrInfo &TII, + MachineFunction *MF, MachineRegisterInfo &MRI, DebugLoc DL) const { + switch (MI.getOpcode()) { + default: + llvm_unreachable("Unexpected instr type to insert"); + case RISCV::ESP_VCMULAS_S16_QACC_H_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S16_QACC_H; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_h first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_h first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S16_QACC_H_LD_IP_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S16_QACC_H_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_h_ld_ip " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_h_ld_ip " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_h_ld_ip " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S16_QACC_H_LD_XP_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S16_QACC_H_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_h_ld_xp " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_h_ld_xp " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_h_ld_xp " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S16_QACC_L_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S16_QACC_L; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_l first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_l first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S16_QACC_L_LD_IP_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S16_QACC_L_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_l_ld_ip " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_l_ld_ip " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_l_ld_ip " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S16_QACC_L_LD_XP_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S16_QACC_L_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_l_ld_xp " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_l_ld_xp " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vcmulas_s16_qacc_l_ld_xp " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S8_QACC_H_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S8_QACC_H; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_h first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_h first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S8_QACC_H_LD_IP_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S8_QACC_H_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_h_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_h_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_h_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S8_QACC_H_LD_XP_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S8_QACC_H_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_h_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_h_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_h_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S8_QACC_L_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S8_QACC_L; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_l first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_l first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S8_QACC_L_LD_IP_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S8_QACC_L_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_l_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_l_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_l_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMULAS_S8_QACC_L_LD_XP_P: { + unsigned Opc = RISCV::ESP_VCMULAS_S8_QACC_L_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_l_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_l_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vcmulas_s8_qacc_l_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_QACC_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_QACC_LD_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_QACC_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_QACC_LD_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_QACC_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_QACC_ST_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_QACC_ST_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &OFFSET_16_16 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_QACC_ST_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_QACC_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_XACC_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_XACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_xacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_xacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_XACC_LD_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_XACC_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_XACC_LD_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_XACC_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_XACC_ST_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_XACC_ST_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &OFFSET_16_16 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_XACC_ST_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_XACC_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_QACC_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_QACC_LD_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_QACC_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_QACC_LD_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_QACC_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_QACC_ST_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_QACC_ST_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &OFFSET_16_16 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_QACC_ST_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_QACC_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_XACC_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_XACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_xacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_xacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_XACC_LD_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_XACC_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_XACC_LD_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_XACC_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_XACC_ST_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_XACC_ST_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &OFFSET_16_16 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_XACC_ST_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_XACC_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_QACC_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_QACC_LD_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_QACC_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_QACC_LD_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_QACC_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_QACC_ST_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_QACC_ST_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &OFFSET_16_16 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_QACC_ST_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_QACC_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_XACC_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_XACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_xacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_xacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_XACC_LD_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_XACC_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_XACC_LD_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_XACC_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_XACC_ST_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_XACC_ST_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &OFFSET_16_16 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_XACC_ST_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_XACC_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_QACC_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_QACC_LD_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_QACC_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_QACC_LD_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_QACC_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_QACC_ST_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_QACC_ST_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &OFFSET_16_16 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_QACC_ST_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_QACC_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_XACC_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_XACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_xacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_xacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_XACC_LD_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_XACC_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &OFFSET_16_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_ld_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_XACC_LD_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_XACC_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_XACC_ST_IP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_XACC_ST_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_st_ip first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &OFFSET_16_16 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_XACC_ST_XP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_XACC_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_xacc_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S16_QACC_LDBC_INCP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S16_QACC_LDBC_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s16_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_S8_QACC_LDBC_INCP_P: { + unsigned Opc = RISCV::ESP_VMULAS_S8_QACC_LDBC_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_s8_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U16_QACC_LDBC_INCP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U16_QACC_LDBC_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u16_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMULAS_U8_QACC_LDBC_INCP_P: { + unsigned Opc = RISCV::ESP_VMULAS_U8_QACC_LDBC_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmulas_u8_qacc_ldbc_incp " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSMULAS_S16_QACC_P: { + unsigned Opc = RISCV::ESP_VSMULAS_S16_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsmulas_s16_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsmulas_s16_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSMULAS_S16_QACC_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSMULAS_S16_QACC_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsmulas_s16_qacc_ld_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsmulas_s16_qacc_ld_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsmulas_s16_qacc_ld_incp " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSMULAS_S8_QACC_P: { + unsigned Opc = RISCV::ESP_VSMULAS_S8_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsmulas_s8_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsmulas_s8_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSMULAS_S8_QACC_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSMULAS_S8_QACC_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsmulas_s8_qacc_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsmulas_s8_qacc_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsmulas_s8_qacc_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSMULAS_U16_QACC_P: { + unsigned Opc = RISCV::ESP_VSMULAS_U16_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsmulas_u16_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsmulas_u16_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSMULAS_U16_QACC_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSMULAS_U16_QACC_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsmulas_u16_qacc_ld_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsmulas_u16_qacc_ld_incp " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsmulas_u16_qacc_ld_incp " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSMULAS_U8_QACC_P: { + unsigned Opc = RISCV::ESP_VSMULAS_U8_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsmulas_u8_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsmulas_u8_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSMULAS_U8_QACC_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSMULAS_U8_QACC_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsmulas_u8_qacc_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsmulas_u8_qacc_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsmulas_u8_qacc_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_S16_P: { + unsigned Opc = RISCV::ESP_CMUL_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_4 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_S16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_CMUL_S16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_4 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(5); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_cmul_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_S16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_CMUL_S16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_cmul_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &SELECT_4 = MI.getOperand(4); + MachineOperand &QZ = MI.getOperand(5); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_s16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_S8_P: { + unsigned Opc = RISCV::ESP_CMUL_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_4 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_S8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_CMUL_S8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_4 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(5); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_cmul_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_S8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_CMUL_S8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_cmul_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &SELECT_4 = MI.getOperand(4); + MachineOperand &QZ = MI.getOperand(5); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_s8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_U16_P: { + unsigned Opc = RISCV::ESP_CMUL_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_4 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_U16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_CMUL_U16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_4 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(5); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_cmul_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_U16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_CMUL_U16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_cmul_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &SELECT_4 = MI.getOperand(4); + MachineOperand &QZ = MI.getOperand(5); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_u16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_U8_P: { + unsigned Opc = RISCV::ESP_CMUL_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_4 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_U8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_CMUL_U8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_4 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(5); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_cmul_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_CMUL_U8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_CMUL_U8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_cmul_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_cmul_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_cmul_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &SELECT_4 = MI.getOperand(4); + MachineOperand &QZ = MI.getOperand(5); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_cmul_u8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MAX_S16_A_P: { + unsigned Opc = RISCV::ESP_MAX_S16_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_max_s16_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MAX_S32_A_P: { + unsigned Opc = RISCV::ESP_MAX_S32_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_max_s32_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MAX_S8_A_P: { + unsigned Opc = RISCV::ESP_MAX_S8_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_max_s8_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MAX_U16_A_P: { + unsigned Opc = RISCV::ESP_MAX_U16_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_max_u16_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MAX_U32_A_P: { + unsigned Opc = RISCV::ESP_MAX_U32_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_max_u32_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MAX_U8_A_P: { + unsigned Opc = RISCV::ESP_MAX_U8_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_max_u8_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MIN_S16_A_P: { + unsigned Opc = RISCV::ESP_MIN_S16_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_min_s16_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MIN_S32_A_P: { + unsigned Opc = RISCV::ESP_MIN_S32_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_min_s32_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MIN_S8_A_P: { + unsigned Opc = RISCV::ESP_MIN_S8_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_min_s8_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MIN_U16_A_P: { + unsigned Opc = RISCV::ESP_MIN_U16_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_min_u16_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MIN_U32_A_P: { + unsigned Opc = RISCV::ESP_MIN_U32_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_min_u32_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MIN_U8_A_P: { + unsigned Opc = RISCV::ESP_MIN_U8_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_min_u8_a first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VABS_16_P: { + unsigned Opc = RISCV::ESP_VABS_16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vabs_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(1); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vabs_16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VABS_32_P: { + unsigned Opc = RISCV::ESP_VABS_32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vabs_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(1); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vabs_32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VABS_8_P: { + unsigned Opc = RISCV::ESP_VABS_8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vabs_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(1); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vabs_8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S16_P: { + unsigned Opc = RISCV::ESP_VADD_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_S16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_S16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S32_P: { + unsigned Opc = RISCV::ESP_VADD_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S32_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_S32_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S32_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_S32_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s32_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S8_P: { + unsigned Opc = RISCV::ESP_VADD_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_S8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_S8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_S8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_s8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U16_P: { + unsigned Opc = RISCV::ESP_VADD_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_U16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_U16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U32_P: { + unsigned Opc = RISCV::ESP_VADD_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U32_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_U32_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U32_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_U32_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u32_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U8_P: { + unsigned Opc = RISCV::ESP_VADD_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_U8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VADD_U8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VADD_U8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vadd_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vadd_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vadd_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vadd_u8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCLAMP_S16_P: { + unsigned Opc = RISCV::ESP_VCLAMP_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vclamp_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(1); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vclamp_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S16_P: { + unsigned Opc = RISCV::ESP_VMAX_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_S16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_S16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S32_P: { + unsigned Opc = RISCV::ESP_VMAX_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S32_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_S32_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S32_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_S32_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s32_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S8_P: { + unsigned Opc = RISCV::ESP_VMAX_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_S8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_S8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_S8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_s8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U16_P: { + unsigned Opc = RISCV::ESP_VMAX_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_U16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_U16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U32_P: { + unsigned Opc = RISCV::ESP_VMAX_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U32_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_U32_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U32_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_U32_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u32_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U8_P: { + unsigned Opc = RISCV::ESP_VMAX_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_U8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMAX_U8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMAX_U8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmax_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmax_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmax_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmax_u8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S16_P: { + unsigned Opc = RISCV::ESP_VMIN_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_S16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_S16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S32_P: { + unsigned Opc = RISCV::ESP_VMIN_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S32_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_S32_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S32_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_S32_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s32_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S8_P: { + unsigned Opc = RISCV::ESP_VMIN_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_S8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_S8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_S8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_s8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U16_P: { + unsigned Opc = RISCV::ESP_VMIN_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_U16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_U16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U32_P: { + unsigned Opc = RISCV::ESP_VMIN_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U32_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_U32_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U32_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_U32_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u32_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U8_P: { + unsigned Opc = RISCV::ESP_VMIN_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_U8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMIN_U8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMIN_U8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmin_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmin_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmin_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmin_u8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_S16_P: { + unsigned Opc = RISCV::ESP_VMUL_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_S16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMUL_S16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmul_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_S16_S8XS8_P: { + unsigned Opc = RISCV::ESP_VMUL_S16_S8XS8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_s16_s8xs8 first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_s16_s8xs8 first " + "argument, it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_s16_s8xs8 first " + "argument, it must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vmul_s16_s8xs8 first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_S16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMUL_S16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmul_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_s16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_S32_S16XS16_P: { + unsigned Opc = RISCV::ESP_VMUL_S32_S16XS16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_s32_s16xs16 first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_s32_s16xs16 first " + "argument, it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_s32_s16xs16 first " + "argument, it must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vmul_s32_s16xs16 first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_S8_P: { + unsigned Opc = RISCV::ESP_VMUL_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_S8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMUL_S8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmul_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_S8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMUL_S8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmul_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_s8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_U16_P: { + unsigned Opc = RISCV::ESP_VMUL_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_U16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMUL_U16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmul_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_U16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMUL_U16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmul_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_u16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_U8_P: { + unsigned Opc = RISCV::ESP_VMUL_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_U8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VMUL_U8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmul_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VMUL_U8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VMUL_U8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vmul_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vmul_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vmul_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vmul_u8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VPRELU_S16_P: { + unsigned Opc = RISCV::ESP_VPRELU_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vprelu_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vprelu_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vprelu_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VPRELU_S8_P: { + unsigned Opc = RISCV::ESP_VPRELU_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vprelu_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vprelu_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vprelu_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VRELU_S16_P: { + unsigned Opc = RISCV::ESP_VRELU_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vrelu_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VRELU_S8_P: { + unsigned Opc = RISCV::ESP_VRELU_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vrelu_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSADDS_S16_P: { + unsigned Opc = RISCV::ESP_VSADDS_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsadds_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsadds_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSADDS_S8_P: { + unsigned Opc = RISCV::ESP_VSADDS_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsadds_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsadds_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSADDS_U16_P: { + unsigned Opc = RISCV::ESP_VSADDS_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsadds_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsadds_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSADDS_U8_P: { + unsigned Opc = RISCV::ESP_VSADDS_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsadds_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsadds_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSAT_S16_P: { + unsigned Opc = RISCV::ESP_VSAT_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsat_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vsat_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSAT_S32_P: { + unsigned Opc = RISCV::ESP_VSAT_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsat_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vsat_s32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSAT_S8_P: { + unsigned Opc = RISCV::ESP_VSAT_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsat_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vsat_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSAT_U16_P: { + unsigned Opc = RISCV::ESP_VSAT_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsat_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vsat_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSAT_U32_P: { + unsigned Opc = RISCV::ESP_VSAT_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsat_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vsat_u32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSAT_U8_P: { + unsigned Opc = RISCV::ESP_VSAT_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QX = MI.getOperand(2); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsat_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vsat_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSSUBS_S16_P: { + unsigned Opc = RISCV::ESP_VSSUBS_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vssubs_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vssubs_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSSUBS_S8_P: { + unsigned Opc = RISCV::ESP_VSSUBS_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vssubs_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vssubs_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSSUBS_U16_P: { + unsigned Opc = RISCV::ESP_VSSUBS_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vssubs_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vssubs_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSSUBS_U8_P: { + unsigned Opc = RISCV::ESP_VSSUBS_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vssubs_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vssubs_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S16_P: { + unsigned Opc = RISCV::ESP_VSUB_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_S16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_S16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S32_P: { + unsigned Opc = RISCV::ESP_VSUB_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S32_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_S32_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_s32_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S32_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_S32_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_s32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s32_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S8_P: { + unsigned Opc = RISCV::ESP_VSUB_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_S8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_s8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_S8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_S8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_s8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_s8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U16_P: { + unsigned Opc = RISCV::ESP_VSUB_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_U16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_u16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_U16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_u16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U32_P: { + unsigned Opc = RISCV::ESP_VSUB_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U32_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_U32_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_u32_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U32_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_U32_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_u32_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u32_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U8_P: { + unsigned Opc = RISCV::ESP_VSUB_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U8_LD_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_U8_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QV = MI.getOperand(3); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_u8_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSUB_U8_ST_INCP_P: { + unsigned Opc = RISCV::ESP_VSUB_U8_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vsub_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsub_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsub_u8_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vsub_u8_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ADDX2_P: { + unsigned Opc = RISCV::ESP_ADDX2; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ADDX4_P: { + unsigned Opc = RISCV::ESP_ADDX4; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SAT_P: { + unsigned Opc = RISCV::ESP_SAT; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS0 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &RSD = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS0.getReg()) + .addReg(RS1.getReg()) + .addReg(RSD.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SUBX2_P: { + unsigned Opc = RISCV::ESP_SUBX2; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SUBX4_P: { + unsigned Opc = RISCV::ESP_SUBX4; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ANDQ_P: { + unsigned Opc = RISCV::ESP_ANDQ; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_andq first argument, it must " + "bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_andq first argument, it must " + "bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_andq first argument, it must " + "bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_NOTQ_P: { + unsigned Opc = RISCV::ESP_NOTQ; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_notq first argument, it must " + "bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(1); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_notq first argument, it must " + "bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ORQ_P: { + unsigned Opc = RISCV::ESP_ORQ; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_orq first argument, it must " + "bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_orq first argument, it must " + "bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_orq first argument, it must " + "bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_XORQ_P: { + unsigned Opc = RISCV::ESP_XORQ; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_xorq first argument, it must " + "bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_xorq first argument, it must " + "bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_xorq first argument, it must " + "bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_EQ_S16_P: { + unsigned Opc = RISCV::ESP_VCMP_EQ_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_eq_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_eq_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_eq_s16 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_EQ_S32_P: { + unsigned Opc = RISCV::ESP_VCMP_EQ_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_eq_s32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_eq_s32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_eq_s32 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_EQ_S8_P: { + unsigned Opc = RISCV::ESP_VCMP_EQ_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_eq_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_eq_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_eq_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_EQ_U16_P: { + unsigned Opc = RISCV::ESP_VCMP_EQ_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_eq_u16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_eq_u16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_eq_u16 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_EQ_U32_P: { + unsigned Opc = RISCV::ESP_VCMP_EQ_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_eq_u32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_eq_u32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_eq_u32 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_EQ_U8_P: { + unsigned Opc = RISCV::ESP_VCMP_EQ_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_eq_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_eq_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_eq_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_GT_S16_P: { + unsigned Opc = RISCV::ESP_VCMP_GT_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_gt_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_gt_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_gt_s16 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_GT_S32_P: { + unsigned Opc = RISCV::ESP_VCMP_GT_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_gt_s32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_gt_s32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_gt_s32 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_GT_S8_P: { + unsigned Opc = RISCV::ESP_VCMP_GT_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_gt_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_gt_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_gt_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_GT_U16_P: { + unsigned Opc = RISCV::ESP_VCMP_GT_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_gt_u16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_gt_u16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_gt_u16 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_GT_U32_P: { + unsigned Opc = RISCV::ESP_VCMP_GT_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_gt_u32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_gt_u32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_gt_u32 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_GT_U8_P: { + unsigned Opc = RISCV::ESP_VCMP_GT_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_gt_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_gt_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_gt_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_LT_S16_P: { + unsigned Opc = RISCV::ESP_VCMP_LT_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_lt_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_lt_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_lt_s16 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_LT_S32_P: { + unsigned Opc = RISCV::ESP_VCMP_LT_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_lt_s32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_lt_s32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_lt_s32 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_LT_S8_P: { + unsigned Opc = RISCV::ESP_VCMP_LT_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_lt_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_lt_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_lt_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_LT_U16_P: { + unsigned Opc = RISCV::ESP_VCMP_LT_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_lt_u16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_lt_u16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_lt_u16 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_LT_U32_P: { + unsigned Opc = RISCV::ESP_VCMP_LT_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_lt_u32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_lt_u32 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_lt_u32 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VCMP_LT_U8_P: { + unsigned Opc = RISCV::ESP_VCMP_LT_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vcmp_lt_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vcmp_lt_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vcmp_lt_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOV_S16_QACC_P: { + unsigned Opc = RISCV::ESP_MOV_S16_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_mov_s16_qacc first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RISCV::Q0 + QUVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOV_S8_QACC_P: { + unsigned Opc = RISCV::ESP_MOV_S8_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_mov_s8_qacc first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RISCV::Q0 + QUVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOV_U16_QACC_P: { + unsigned Opc = RISCV::ESP_MOV_U16_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_mov_u16_qacc first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RISCV::Q0 + QUVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOV_U8_QACC_P: { + unsigned Opc = RISCV::ESP_MOV_U8_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_mov_u8_qacc first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RISCV::Q0 + QUVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVI_16_A_P: { + unsigned Opc = RISCV::ESP_MOVI_16_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_movi_16_a first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVI_16_Q_P: { + unsigned Opc = RISCV::ESP_MOVI_16_Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &SELECT_16 = MI.getOperand(1); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_movi_16_q first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RS1.getReg()) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVI_32_A_P: { + unsigned Opc = RISCV::ESP_MOVI_32_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_movi_32_a first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_4 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVI_32_Q_P: { + unsigned Opc = RISCV::ESP_MOVI_32_Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &SELECT_4 = MI.getOperand(1); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_movi_32_q first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVI_8_A_P: { + unsigned Opc = RISCV::ESP_MOVI_8_A; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_movi_8_a first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVI_8_Q_P: { + unsigned Opc = RISCV::ESP_MOVI_8_Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &SELECT_16 = MI.getOperand(1); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_movi_8_q first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RS1.getReg()) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_R_CFG_P: { + unsigned Opc = RISCV::ESP_MOVX_R_CFG; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(R1, RegState::Define); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_R_FFT_BIT_WIDTH_P: { + unsigned Opc = RISCV::ESP_MOVX_R_FFT_BIT_WIDTH; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(R1, RegState::Define); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_R_PERF_P: { + unsigned Opc = RISCV::ESP_MOVX_R_PERF; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + MachineOperand &RS1 = MI.getOperand(1); + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_R_SAR_P: { + unsigned Opc = RISCV::ESP_MOVX_R_SAR; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(R1, RegState::Define); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_R_SAR_BYTES_P: { + unsigned Opc = RISCV::ESP_MOVX_R_SAR_BYTES; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(R1, RegState::Define); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_R_XACC_H_P: { + unsigned Opc = RISCV::ESP_MOVX_R_XACC_H; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(R1, RegState::Define); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_R_XACC_L_P: { + unsigned Opc = RISCV::ESP_MOVX_R_XACC_L; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(R1, RegState::Define); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_W_CFG_P: { + unsigned Opc = RISCV::ESP_MOVX_W_CFG; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_W_FFT_BIT_WIDTH_P: { + unsigned Opc = RISCV::ESP_MOVX_W_FFT_BIT_WIDTH; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_W_PERF_P: { + unsigned Opc = RISCV::ESP_MOVX_W_PERF; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_W_SAR_P: { + unsigned Opc = RISCV::ESP_MOVX_W_SAR; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_W_SAR_BYTES_P: { + unsigned Opc = RISCV::ESP_MOVX_W_SAR_BYTES; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_W_XACC_H_P: { + unsigned Opc = RISCV::ESP_MOVX_W_XACC_H; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_MOVX_W_XACC_L_P: { + unsigned Opc = RISCV::ESP_MOVX_W_XACC_L; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + BuildMI(*MBB, MI, DL, TII.get(Opc)).addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VEXT_S16_P: { + unsigned Opc = RISCV::ESP_VEXT_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vext_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(1); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vext_s16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vext_s16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VEXT_S8_P: { + unsigned Opc = RISCV::ESP_VEXT_S8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vext_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(1); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vext_s8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vext_s8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VEXT_U16_P: { + unsigned Opc = RISCV::ESP_VEXT_U16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vext_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(1); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vext_u16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vext_u16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VEXT_U8_P: { + unsigned Opc = RISCV::ESP_VEXT_U8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vext_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(1); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vext_u8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(2); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_vext_u8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VUNZIP_16_P: { + unsigned Opc = RISCV::ESP_VUNZIP_16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vunzip_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vunzip_16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VUNZIP_32_P: { + unsigned Opc = RISCV::ESP_VUNZIP_32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vunzip_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vunzip_32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VUNZIP_8_P: { + unsigned Opc = RISCV::ESP_VUNZIP_8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vunzip_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vunzip_8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VUNZIPT_16_P: { + unsigned Opc = RISCV::ESP_VUNZIPT_16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vunzipt_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vunzipt_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vunzipt_16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VUNZIPT_8_P: { + unsigned Opc = RISCV::ESP_VUNZIPT_8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vunzipt_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vunzipt_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vunzipt_8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VZIP_16_P: { + unsigned Opc = RISCV::ESP_VZIP_16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vzip_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vzip_16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VZIP_32_P: { + unsigned Opc = RISCV::ESP_VZIP_32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vzip_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vzip_32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VZIP_8_P: { + unsigned Opc = RISCV::ESP_VZIP_8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vzip_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vzip_8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VZIPT_16_P: { + unsigned Opc = RISCV::ESP_VZIPT_16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vzipt_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vzipt_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vzipt_16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VZIPT_8_P: { + unsigned Opc = RISCV::ESP_VZIPT_8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_vzipt_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vzipt_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vzipt_8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QXVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ZERO_Q_P: { + unsigned Opc = RISCV::ESP_ZERO_Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QZ = MI.getOperand(0); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_zero_q first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ZERO_QACC_P: { + unsigned Opc = RISCV::ESP_ZERO_QACC; + MachineBasicBlock *MBB = MI.getParent(); + BuildMI(*MBB, MI, DL, TII.get(Opc)); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ZERO_XACC_P: { + unsigned Opc = RISCV::ESP_ZERO_XACC; + MachineBasicBlock *MBB = MI.getParent(); + BuildMI(*MBB, MI, DL, TII.get(Opc)); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_AMS_S16_LD_INCP_P: { + unsigned Opc = RISCV::ESP_FFT_AMS_S16_LD_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &SELECT_2 = MI.getOperand(4); + MachineOperand &QU = MI.getOperand(5); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(6); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(7); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal) + .addReg(RS1.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_AMS_S16_LD_INCP_UAUP_P: { + unsigned Opc = RISCV::ESP_FFT_AMS_S16_LD_INCP_UAUP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp_uaup " + "first argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp_uaup " + "first argument, it must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp_uaup " + "first argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &SELECT_2 = MI.getOperand(4); + MachineOperand &QU = MI.getOperand(5); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp_uaup " + "first argument, it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(6); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp_uaup " + "first argument, it must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(7); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_incp_uaup " + "first argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal) + .addReg(RS1.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_AMS_S16_LD_R32_DECP_P: { + unsigned Opc = RISCV::ESP_FFT_AMS_S16_LD_R32_DECP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_r32_decp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_r32_decp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_r32_decp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &SELECT_2 = MI.getOperand(4); + MachineOperand &QU = MI.getOperand(5); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_r32_decp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(6); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_r32_decp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(7); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_fft_ams_s16_ld_r32_decp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal) + .addReg(RS1.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_AMS_S16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_FFT_AMS_S16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_fft_ams_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_fft_ams_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_fft_ams_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_fft_ams_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + MachineOperand &RS2 = MI.getOperand(5); + MachineOperand &SELECT_2 = MI.getOperand(6); + MachineOperand &QZ = MI.getOperand(7); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_fft_ams_s16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + unsigned R2 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(R2, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_BITREV_P: { + unsigned Opc = RISCV::ESP_FFT_BITREV; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QV = MI.getOperand(1); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_fft_bitrev first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QVVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_CMUL_S16_LD_XP_P: { + unsigned Opc = RISCV::ESP_FFT_CMUL_S16_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_fft_cmul_s16_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_fft_cmul_s16_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(3); + MachineOperand &SELECT_8 = MI.getOperand(4); + MachineOperand &QZ = MI.getOperand(5); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_fft_cmul_s16_ld_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(6); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_fft_cmul_s16_ld_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_CMUL_S16_ST_XP_P: { + unsigned Opc = RISCV::ESP_FFT_CMUL_S16_ST_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QX = MI.getOperand(1); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_fft_cmul_s16_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_fft_cmul_s16_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(3); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_fft_cmul_s16_st_xp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(4); + MachineOperand &SELECT_4 = MI.getOperand(5); + MachineOperand &UPD_4 = MI.getOperand(6); + MachineOperand &SELECT_8 = MI.getOperand(7); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()) + .addImm(UPD_4.getImm()) + .addImm(SELECT_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_R2BF_S16_P: { + unsigned Opc = RISCV::ESP_FFT_R2BF_S16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_fft_r2bf_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_fft_r2bf_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &SELECT_2 = MI.getOperand(2); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_fft_r2bf_s16 first argument, " + "it must bi in range [0,7]"); + MachineOperand &QV = MI.getOperand(4); + unsigned QVVal = QV.getImm(); + assert(QVVal < 8 && "Unexpected value of esp_fft_r2bf_s16 first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QVVal, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_R2BF_S16_ST_INCP_P: { + unsigned Opc = RISCV::ESP_FFT_R2BF_S16_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QX = MI.getOperand(0); + unsigned QXVal = QX.getImm(); + assert(QXVal < 8 && "Unexpected value of esp_fft_r2bf_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_fft_r2bf_s16_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &SELECT_4 = MI.getOperand(3); + MachineOperand &QZ = MI.getOperand(4); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_fft_r2bf_s16_st_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QXVal) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addImm(SELECT_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_FFT_VST_R32_DECP_P: { + unsigned Opc = RISCV::ESP_FFT_VST_R32_DECP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_fft_vst_r32_decp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &SELECT_2 = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LD_128_USAR_IP_P: { + unsigned Opc = RISCV::ESP_LD_128_USAR_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_ld_128_usar_ip first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LD_128_USAR_XP_P: { + unsigned Opc = RISCV::ESP_LD_128_USAR_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_ld_128_usar_xp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LD_XACC_IP_P: { + unsigned Opc = RISCV::ESP_LD_XACC_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_8 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDQA_S16_128_IP_P: { + unsigned Opc = RISCV::ESP_LDQA_S16_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDQA_S16_128_XP_P: { + unsigned Opc = RISCV::ESP_LDQA_S16_128_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDQA_S8_128_IP_P: { + unsigned Opc = RISCV::ESP_LDQA_S8_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDQA_S8_128_XP_P: { + unsigned Opc = RISCV::ESP_LDQA_S8_128_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDQA_U16_128_IP_P: { + unsigned Opc = RISCV::ESP_LDQA_U16_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDQA_U16_128_XP_P: { + unsigned Opc = RISCV::ESP_LDQA_U16_128_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDQA_U8_128_IP_P: { + unsigned Opc = RISCV::ESP_LDQA_U8_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDQA_U8_128_XP_P: { + unsigned Opc = RISCV::ESP_LDQA_U8_128_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDBC_16_IP_P: { + unsigned Opc = RISCV::ESP_VLDBC_16_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_4 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldbc_16_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDBC_16_XP_P: { + unsigned Opc = RISCV::ESP_VLDBC_16_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldbc_16_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDBC_32_IP_P: { + unsigned Opc = RISCV::ESP_VLDBC_32_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_4 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldbc_32_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDBC_32_XP_P: { + unsigned Opc = RISCV::ESP_VLDBC_32_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldbc_32_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDBC_8_IP_P: { + unsigned Opc = RISCV::ESP_VLDBC_8_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_4 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldbc_8_ip first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_4.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDBC_8_XP_P: { + unsigned Opc = RISCV::ESP_VLDBC_8_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldbc_8_xp first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDEXT_S16_IP_P: { + unsigned Opc = RISCV::ESP_VLDEXT_S16_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_16_16 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldext_s16_ip first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldext_s16_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDEXT_S16_XP_P: { + unsigned Opc = RISCV::ESP_VLDEXT_S16_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldext_s16_xp first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldext_s16_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDEXT_S8_IP_P: { + unsigned Opc = RISCV::ESP_VLDEXT_S8_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_16_16 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldext_s8_ip first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldext_s8_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDEXT_S8_XP_P: { + unsigned Opc = RISCV::ESP_VLDEXT_S8_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldext_s8_xp first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldext_s8_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDEXT_U16_IP_P: { + unsigned Opc = RISCV::ESP_VLDEXT_U16_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_16_16 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldext_u16_ip first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldext_u16_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDEXT_U16_XP_P: { + unsigned Opc = RISCV::ESP_VLDEXT_U16_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldext_u16_xp first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldext_u16_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDEXT_U8_IP_P: { + unsigned Opc = RISCV::ESP_VLDEXT_U8_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_16_16 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldext_u8_ip first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldext_u8_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_16_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDEXT_U8_XP_P: { + unsigned Opc = RISCV::ESP_VLDEXT_U8_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldext_u8_xp first argument, " + "it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(3); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldext_u8_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLDHBC_16_INCP_P: { + unsigned Opc = RISCV::ESP_VLDHBC_16_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QU = MI.getOperand(1); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vldhbc_16_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_vldhbc_16_incp first " + "argument, it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LD_QACC_H_H_128_IP_P: { + unsigned Opc = RISCV::ESP_LD_QACC_H_H_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LD_QACC_H_L_128_IP_P: { + unsigned Opc = RISCV::ESP_LD_QACC_H_L_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LD_QACC_L_H_128_IP_P: { + unsigned Opc = RISCV::ESP_LD_QACC_L_H_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LD_QACC_L_L_128_IP_P: { + unsigned Opc = RISCV::ESP_LD_QACC_L_L_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LD_UA_STATE_IP_P: { + unsigned Opc = RISCV::ESP_LD_UA_STATE_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_LDXQ_32_P: { + unsigned Opc = RISCV::ESP_LDXQ_32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_ldxq_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_4 = MI.getOperand(2); + MachineOperand &SELECT_8 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_ldxq_32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QWVal) + .addImm(SELECT_4.getImm()) + .addImm(SELECT_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ST_QACC_H_H_128_IP_P: { + unsigned Opc = RISCV::ESP_ST_QACC_H_H_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ST_QACC_H_L_128_IP_P: { + unsigned Opc = RISCV::ESP_ST_QACC_H_L_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ST_QACC_L_H_128_IP_P: { + unsigned Opc = RISCV::ESP_ST_QACC_L_H_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ST_QACC_L_L_128_IP_P: { + unsigned Opc = RISCV::ESP_ST_QACC_L_L_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ST_UA_STATE_IP_P: { + unsigned Opc = RISCV::ESP_ST_UA_STATE_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_STXQ_32_P: { + unsigned Opc = RISCV::ESP_STXQ_32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_stxq_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_stxq_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_4 = MI.getOperand(3); + MachineOperand &SELECT_8 = MI.getOperand(4); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QWVal) + .addReg(RISCV::Q0 + QUVal) + .addImm(SELECT_4.getImm()) + .addImm(SELECT_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLD_128_IP_P: { + unsigned Opc = RISCV::ESP_VLD_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_16 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vld_128_ip first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLD_128_XP_P: { + unsigned Opc = RISCV::ESP_VLD_128_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vld_128_xp first argument, it " + "must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLD_H_64_IP_P: { + unsigned Opc = RISCV::ESP_VLD_H_64_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_8 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vld_h_64_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLD_H_64_XP_P: { + unsigned Opc = RISCV::ESP_VLD_H_64_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vld_h_64_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLD_L_64_IP_P: { + unsigned Opc = RISCV::ESP_VLD_L_64_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_8 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vld_l_64_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VLD_L_64_XP_P: { + unsigned Opc = RISCV::ESP_VLD_L_64_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vld_l_64_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VST_128_IP_P: { + unsigned Opc = RISCV::ESP_VST_128_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vst_128_ip first argument, it " + "must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &OFFSET_256_16 = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VST_128_XP_P: { + unsigned Opc = RISCV::ESP_VST_128_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QU = MI.getOperand(1); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vst_128_xp first argument, it " + "must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VST_H_64_IP_P: { + unsigned Opc = RISCV::ESP_VST_H_64_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vst_h_64_ip first argument, " + "it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &OFFSET_256_8 = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VST_H_64_XP_P: { + unsigned Opc = RISCV::ESP_VST_H_64_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QU = MI.getOperand(1); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vst_h_64_xp first argument, " + "it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VST_L_64_IP_P: { + unsigned Opc = RISCV::ESP_VST_L_64_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QU = MI.getOperand(0); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vst_l_64_ip first argument, " + "it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &OFFSET_256_8 = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VST_L_64_XP_P: { + unsigned Opc = RISCV::ESP_VST_L_64_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QU = MI.getOperand(1); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vst_l_64_xp first argument, " + "it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QUVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SLCI_2Q_P: { + unsigned Opc = RISCV::ESP_SLCI_2Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_slci_2q first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_slci_2q first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SLCXXP_2Q_P: { + unsigned Opc = RISCV::ESP_SLCXXP_2Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_slcxxp_2q first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(3); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_slcxxp_2q first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRC_Q_P: { + unsigned Opc = RISCV::ESP_SRC_Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_src_q first argument, it must " + "bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_src_q first argument, it must " + "bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_src_q first argument, it must " + "bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRC_Q_LD_IP_P: { + unsigned Opc = RISCV::ESP_SRC_Q_LD_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_src_q_ld_ip first argument, " + "it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(1); + MachineOperand &QW = MI.getOperand(2); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_src_q_ld_ip first argument, " + "it must bi in range [0,7]"); + MachineOperand &OFFSET_256_16 = MI.getOperand(3); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_src_q_ld_ip first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QWVal) + .addImm(OFFSET_256_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRC_Q_LD_XP_P: { + unsigned Opc = RISCV::ESP_SRC_Q_LD_XP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS2 = MI.getOperand(0); + MachineOperand &QY = MI.getOperand(1); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_src_q_ld_xp first argument, " + "it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + MachineOperand &QW = MI.getOperand(3); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_src_q_ld_xp first argument, " + "it must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(4); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_src_q_ld_xp first argument, " + "it must bi in range [0,7]"); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QYVal) + .addReg(RS1.getReg()) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRC_Q_QUP_P: { + unsigned Opc = RISCV::ESP_SRC_Q_QUP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_src_q_qup first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_src_q_qup first argument, it " + "must bi in range [0,7]"); + MachineOperand &QZ = MI.getOperand(2); + unsigned QZVal = QZ.getImm(); + assert(QZVal < 8 && "Unexpected value of esp_src_q_qup first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QZVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCI_2Q_P: { + unsigned Opc = RISCV::ESP_SRCI_2Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_srci_2q first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_srci_2q first argument, it " + "must bi in range [0,7]"); + MachineOperand &SELECT_16 = MI.getOperand(2); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal) + .addImm(SELECT_16.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCMB_S16_Q_QACC_P: { + unsigned Opc = RISCV::ESP_SRCMB_S16_Q_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_srcmb_s16_q_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &SELECT_2 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_srcmb_s16_q_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCMB_S16_QACC_P: { + unsigned Opc = RISCV::ESP_SRCMB_S16_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &SELECT_2 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_srcmb_s16_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RS1.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCMB_S8_Q_QACC_P: { + unsigned Opc = RISCV::ESP_SRCMB_S8_Q_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_srcmb_s8_q_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &SELECT_2 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_srcmb_s8_q_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCMB_S8_QACC_P: { + unsigned Opc = RISCV::ESP_SRCMB_S8_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &SELECT_2 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_srcmb_s8_qacc first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RS1.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCMB_U16_Q_QACC_P: { + unsigned Opc = RISCV::ESP_SRCMB_U16_Q_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_srcmb_u16_q_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &SELECT_2 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_srcmb_u16_q_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCMB_U16_QACC_P: { + unsigned Opc = RISCV::ESP_SRCMB_U16_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &SELECT_2 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_srcmb_u16_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RS1.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCMB_U8_Q_QACC_P: { + unsigned Opc = RISCV::ESP_SRCMB_U8_Q_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QW = MI.getOperand(0); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_srcmb_u8_q_qacc first " + "argument, it must bi in range [0,7]"); + MachineOperand &SELECT_2 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_srcmb_u8_q_qacc first " + "argument, it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCMB_U8_QACC_P: { + unsigned Opc = RISCV::ESP_SRCMB_U8_QACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &SELECT_2 = MI.getOperand(1); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_srcmb_u8_qacc first argument, " + "it must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RS1.getReg()) + .addImm(SELECT_2.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCQ_128_ST_INCP_P: { + unsigned Opc = RISCV::ESP_SRCQ_128_ST_INCP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_srcq_128_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_srcq_128_st_incp first " + "argument, it must bi in range [0,7]"); + MachineOperand &RS1 = MI.getOperand(2); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRCXXP_2Q_P: { + unsigned Opc = RISCV::ESP_SRCXXP_2Q; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &RS2 = MI.getOperand(1); + MachineOperand &QY = MI.getOperand(2); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_srcxxp_2q first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(3); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_srcxxp_2q first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QYVal, RegState::Define) + .addReg(RISCV::Q0 + QWVal, RegState::Define) + .addReg(RS1.getReg()) + .addReg(RS2.getReg()) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRS_S_XACC_P: { + unsigned Opc = RISCV::ESP_SRS_S_XACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_SRS_U_XACC_P: { + unsigned Opc = RISCV::ESP_SRS_U_XACC; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSL_32_P: { + unsigned Opc = RISCV::ESP_VSL_32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsl_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(1); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsl_32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSLD_16_P: { + unsigned Opc = RISCV::ESP_VSLD_16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsld_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vsld_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsld_16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSLD_32_P: { + unsigned Opc = RISCV::ESP_VSLD_32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsld_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vsld_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsld_32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSLD_8_P: { + unsigned Opc = RISCV::ESP_VSLD_8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsld_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vsld_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsld_8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSR_S32_P: { + unsigned Opc = RISCV::ESP_VSR_S32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsr_s32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(1); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsr_s32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSR_U32_P: { + unsigned Opc = RISCV::ESP_VSR_U32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsr_u32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(1); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsr_u32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSRD_16_P: { + unsigned Opc = RISCV::ESP_VSRD_16; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsrd_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vsrd_16 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsrd_16 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSRD_32_P: { + unsigned Opc = RISCV::ESP_VSRD_32; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsrd_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vsrd_32 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsrd_32 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_VSRD_8_P: { + unsigned Opc = RISCV::ESP_VSRD_8; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &QY = MI.getOperand(0); + unsigned QYVal = QY.getImm(); + assert(QYVal < 8 && "Unexpected value of esp_vsrd_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QW = MI.getOperand(1); + unsigned QWVal = QW.getImm(); + assert(QWVal < 8 && "Unexpected value of esp_vsrd_8 first argument, it " + "must bi in range [0,7]"); + MachineOperand &QU = MI.getOperand(2); + unsigned QUVal = QU.getImm(); + assert(QUVal < 8 && "Unexpected value of esp_vsrd_8 first argument, it " + "must bi in range [0,7]"); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(RISCV::Q0 + QUVal, RegState::Define) + .addReg(RISCV::Q0 + QYVal) + .addReg(RISCV::Q0 + QWVal); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ST_S_XACC_IP_P: { + unsigned Opc = RISCV::ESP_ST_S_XACC_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_8 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + case RISCV::ESP_ST_U_XACC_IP_P: { + unsigned Opc = RISCV::ESP_ST_U_XACC_IP; + MachineBasicBlock *MBB = MI.getParent(); + MachineOperand &RS1 = MI.getOperand(0); + MachineOperand &OFFSET_256_8 = MI.getOperand(1); + const TargetRegisterClass *RC = &RISCV::GPRPIERegClass; + unsigned R1 = MRI.createVirtualRegister(RC); + BuildMI(*MBB, MI, DL, TII.get(Opc)) + .addReg(R1, RegState::Define) + .addReg(RS1.getReg()) + .addImm(OFFSET_256_8.getImm()); + + MI.eraseFromParent(); + return MBB; + } + } +} diff --git a/llvm/lib/Target/RISCV/RISCVESP32P4Operands.td b/llvm/lib/Target/RISCV/RISCVESP32P4Operands.td new file mode 100644 index 00000000000000..0d77783aff0e24 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVESP32P4Operands.td @@ -0,0 +1,134 @@ +//===- RISCVESP32P4Operands.td - ESP32P4 instruction operands -*- tblgen-*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Immediate operands with a shared generic render method. +class P4ImmAsmOperand : AsmOperandClass { + let Name = name; + let RenderMethod = "addImmOperands"; + let DiagnosticType = !strconcat("Invalid", name); +} + +class Immediate + : Operand, ImmLeaf { + let PrintMethod = "print"#asmop; + let ParserMatchClass = !cast(asmop); +} +/// --------------------------- /// + +// imm8 predicate - Immediate in the range [-128,127] +def Imm8_AsmOperand : P4ImmAsmOperand<"Imm8">; +def imm8 : Immediate= -128 && Imm <= 127; }], "Imm8_AsmOperand"> { + let EncoderMethod = "getImm8OpValue"; + let DecoderMethod = "decodeImm8Operand"; +} + +// offset_16_16 predicate - 4-bit signed immediate in the range [-128,112] with an interval +// of 16. +def Offset_16_16_AsmOperand: P4ImmAsmOperand<"Offset_16_16">; +def offset_16_16: Immediate= -128 && Imm <= 112) && ((Imm & 0xf) == 0); }], "Offset_16_16_AsmOperand"> { + let EncoderMethod = "getOffset_16_16OpValue"; + let DecoderMethod = "decodeOffset_16_16Operand"; +} + +// offset_256_8 predicate - 4-bit signed immediate in the range [-1024,1016] with an interval +// of 8. +def Offset_256_8_AsmOperand: P4ImmAsmOperand<"Offset_256_8">; +def offset_256_8: Immediate= -1024 && Imm <= 1016) && ((Imm & 0x7) == 0); }], "Offset_256_8_AsmOperand"> { + let EncoderMethod = "getOffset_256_8OpValue"; + let DecoderMethod = "decodeOffset_256_8Operand"; +} + +// offset_256_16 predicate - 8-bit signed immediate in the range [-2048,2032] with an interval +// of 16. +def Offset_256_16_AsmOperand: P4ImmAsmOperand<"Offset_256_16">; +def offset_256_16: Immediate= -2048 && Imm <= 2032) && ((Imm & 0xf) == 0); }], "Offset_256_16_AsmOperand"> { + let EncoderMethod = "getOffset_256_16OpValue"; + let DecoderMethod = "decodeOffset_256_16Operand"; +} + +// offset_256_4 predicate - 4-bit signed immediate in the range [-512,508] with an interval +// of 4. +def Offset_256_4_AsmOperand: P4ImmAsmOperand<"Offset_256_4">; +def offset_256_4: Immediate= -512 && Imm <= 508) && ((Imm & 0x3) == 0); }], "Offset_256_4_AsmOperand"> { + let EncoderMethod = "getOffset_256_4OpValue"; + let DecoderMethod = "decodeOffset_256_4Operand"; +} + +// select_2 predicate - Immediate in the range [0,1] +def Select_2_AsmOperand: P4ImmAsmOperand<"Select_2">; +def select_2: Immediate= 0 && Imm <= 1; }], "Select_2_AsmOperand"> { + let EncoderMethod = "getSelect_2OpValue"; + let DecoderMethod = "decodeSelect_2Operand"; +} + +// select_4 predicate - Immediate in the range [0,3] +def Select_4_AsmOperand: P4ImmAsmOperand<"Select_4">; +def select_4: Immediate= 0 && Imm <= 3; }], "Select_4_AsmOperand"> { + let EncoderMethod = "getSelect_4OpValue"; + let DecoderMethod = "decodeSelect_4Operand"; +} + +// select_8 predicate - Immediate in the range [0,7] +def Select_8_AsmOperand: P4ImmAsmOperand<"Select_8">; +def select_8: Immediate= 0 && Imm <= 7; }], "Select_8_AsmOperand"> { + let EncoderMethod = "getSelect_8OpValue"; + let DecoderMethod = "decodeSelect_8Operand"; +} + +// select_16 predicate - Immediate in the range [0,15] +def Select_16_AsmOperand: P4ImmAsmOperand<"Select_16">; +def select_16: Immediate= 0 && Imm <= 15; }], "Select_16_AsmOperand"> { + let EncoderMethod = "getSelect_16OpValue"; + let DecoderMethod = "decodeSelect_16Operand"; +} + +def uimm10_step4 : Operand { + // let ParserMatchClass = Simm21Lsb0JALAsmOperand; + let ParserMatchClass = UImmAsmOperand<10>; + let PrintMethod = "printBranchOperand"; + let EncoderMethod = "getUImm10_Step4Operand"; + let DecoderMethod = "decodeUImm10_Step4Operand"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isUInt<10>(); + return MCOp.isBareSymbolRef(); + }]; + let OperandType = "OPERAND_PCREL"; +} + +def uimm13_step4 : Operand { + let ParserMatchClass = UImmAsmOperand<13>; + let PrintMethod = "printBranchOperand"; + let EncoderMethod = "getUImm13_Step4Operand"; + let DecoderMethod = "decodeUImm13_Step4Operand"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isUInt<10>(); + return MCOp.isBareSymbolRef(); + }]; + let OperandType = "OPERAND_PCREL"; +} + +// A 12-bit unsigned immediate. +def uimm12 : RISCVOp, + ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<12>; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmOperand<12>"; + let OperandType = "OPERAND_UIMM12"; + let MCOperandPredicate = [{ + uint64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isUInt<12>(Imm); + }]; +} diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 26451c80f57b42..916e163cc60c80 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -977,6 +977,9 @@ def HasVendorXCVbi AssemblerPredicate<(all_of FeatureVendorXCVbi), "'XCVbi' (CORE-V Immediate Branching)">; +def FeatureVendorESP32P4 : SubtargetFeature<"xesppie", "HasVendorESP32P4", "true", "'Espressif ESP32P4'">; +def HasVendorESP32P4 : Predicate<"Subtarget->hasVendorESP32P4()">, AssemblerPredicate<(all_of FeatureVendorESP32P4), "'Espressif ESP32P4'">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index a0cec426002b6f..396a7b8f2d1c95 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -118,6 +118,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, // Set up the register classes. addRegisterClass(XLenVT, &RISCV::GPRRegClass); + + if (Subtarget.hasVendorESP32P4()) { + static const MVT::SimpleValueType QRVec[] = {MVT::v16i8, MVT::v4i32}; + for (auto st : QRVec) + addRegisterClass(st, &RISCV::QRRegClass); + } + if (Subtarget.is64Bit() && RV64LegalI32) addRegisterClass(MVT::i32, &RISCV::GPRRegClass); @@ -17161,9 +17168,14 @@ static MachineBasicBlock *emitFROUND(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock * RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + DebugLoc DL = MI.getDebugLoc(); + switch (MI.getOpcode()) { default: - llvm_unreachable("Unexpected instr type to insert"); + return emitDSPInstrWithCustomInserter(MI, BB, TII, MF, MRI, DL); case RISCV::ReadCycleWide: assert(!Subtarget.is64Bit() && "ReadCycleWrite is only to be used on riscv32"); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 30b9ad7e6f6f32..7b506d65f218f3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -829,6 +829,10 @@ class RISCVTargetLowering : public TargetLowering { MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override; + MachineBasicBlock *emitDSPInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *MBB, const TargetInstrInfo &TII, + MachineFunction *MF, MachineRegisterInfo &MRI, DebugLoc DL) const; + /// RISCVCCAssignFn - This target-specific function extends the default /// CCValAssign with additional information used to lower RISC-V calling /// conventions. diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsESP32P4.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsESP32P4.td new file mode 100644 index 00000000000000..6adaa56cc656d0 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsESP32P4.td @@ -0,0 +1,42 @@ +//====-- RISCVInstrFormatsESP32P4.td - ESP32P4 Instr Formats -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V ESP32-P4 extension instruction formats. +// +//===----------------------------------------------------------------------===// + +class Esp32P4Inst pattern, + InstrItinClass itin = NoItinerary> + : Instruction, Requires<[HasVendorESP32P4]> { + let Namespace = "RISCV"; + let DecoderNamespace = "ESP32P4"; + field bits<32> Inst; + field bits<32> SoftFail = 0; + + let TSFlags{4-0} = 23; + let Size = 4; + + let OutOperandList = outs; + let InOperandList = ins; + + let AsmString = asmstr; + let Pattern = pattern; + + let Itinerary = itin; +} + + +// Pseudo instructions +class PseudoESP32P4 pattern> + : Esp32P4Inst { + let isPseudo = 1; + let isCodeGenOnly = 1; + let mayLoad = 1; + let mayStore = 1; + let hasSideEffects = 1; +} \ No newline at end of file diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index d5b1ddfbeb3dc9..3d63fd8ae4d459 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2007,6 +2007,12 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_UIMM10_LSB00_NONZERO: Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0); break; + case RISCVOp::OPERAND_UIMM10_STEP4: + Ok = isUInt<10>(Imm) && (Imm != 0); + break; + case RISCVOp::OPERAND_UIMM13_STEP4: + Ok = isUInt<13>(Imm) && (Imm != 0); + break; case RISCVOp::OPERAND_ZERO: Ok = Imm == 0; break; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 114329c2c7c5f3..69bbd3b411e578 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2179,6 +2179,7 @@ include "RISCVInstrInfoXVentana.td" include "RISCVInstrInfoXTHead.td" include "RISCVInstrInfoXSf.td" include "RISCVInstrInfoXCV.td" +include "RISCVInstrInfoESP32P4.td" //===----------------------------------------------------------------------===// // Global ISel diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoESP32P4.td b/llvm/lib/Target/RISCV/RISCVInstrInfoESP32P4.td new file mode 100644 index 00000000000000..bd97a927ea98f6 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoESP32P4.td @@ -0,0 +1,15603 @@ +//===- RISCVInstrInfoP4.td - RISCV Target Description -*- tablegen -*------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISCV ESP32P4 DSP instructions in TableGen format. +// +// These definitions are generated +// This file is generated +// +//===----------------------------------------------------------------------===// + +include "RISCVESP32P4Operands.td" +include "RISCVInstrFormatsESP32P4.td" +include "RISCVInstrInfoP4HWLP.td" + +// This file is generated + +def ESP_VCMULAS_S16_QACC_H: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vcmulas.s16.qacc.h\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S16_QACC_H_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vcmulas_s16_qacc_h_p $qx, $qy", + [(int_riscv_esp_vcmulas_s16_qacc_h timm:$qx, timm:$qy)]>; + +def ESP_VCMULAS_S16_QACC_H_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vcmulas.s16.qacc.h.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22-19} = off1616{3-0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S16_QACC_H_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vcmulas_s16_qacc_h_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vcmulas_s16_qacc_h_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VCMULAS_S16_QACC_H_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vcmulas.s16.qacc.h.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S16_QACC_H_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vcmulas_s16_qacc_h_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vcmulas_s16_qacc_h_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VCMULAS_S16_QACC_L: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vcmulas.s16.qacc.l\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S16_QACC_L_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vcmulas_s16_qacc_l_p $qx, $qy", + [(int_riscv_esp_vcmulas_s16_qacc_l timm:$qx, timm:$qy)]>; + +def ESP_VCMULAS_S16_QACC_L_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vcmulas.s16.qacc.l.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22-19} = off1616{3-0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S16_QACC_L_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vcmulas_s16_qacc_l_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vcmulas_s16_qacc_l_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VCMULAS_S16_QACC_L_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vcmulas.s16.qacc.l.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S16_QACC_L_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vcmulas_s16_qacc_l_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vcmulas_s16_qacc_l_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VCMULAS_S8_QACC_H: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vcmulas.s8.qacc.h\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S8_QACC_H_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vcmulas_s8_qacc_h_p $qx, $qy", + [(int_riscv_esp_vcmulas_s8_qacc_h timm:$qx, timm:$qy)]>; + +def ESP_VCMULAS_S8_QACC_H_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vcmulas.s8.qacc.h.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-19} = off1616{3-0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S8_QACC_H_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vcmulas_s8_qacc_h_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vcmulas_s8_qacc_h_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VCMULAS_S8_QACC_H_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vcmulas.s8.qacc.h.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S8_QACC_H_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vcmulas_s8_qacc_h_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vcmulas_s8_qacc_h_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VCMULAS_S8_QACC_L: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vcmulas.s8.qacc.l\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S8_QACC_L_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vcmulas_s8_qacc_l_p $qx, $qy", + [(int_riscv_esp_vcmulas_s8_qacc_l timm:$qx, timm:$qy)]>; + +def ESP_VCMULAS_S8_QACC_L_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vcmulas.s8.qacc.l.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-19} = off1616{3-0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S8_QACC_L_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vcmulas_s8_qacc_l_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vcmulas_s8_qacc_l_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VCMULAS_S8_QACC_L_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vcmulas.s8.qacc.l.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMULAS_S8_QACC_L_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vcmulas_s8_qacc_l_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vcmulas_s8_qacc_l_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_S16_QACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vmulas.s16.qacc\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vmulas_s16_qacc_p $qx, $qy", + [(int_riscv_esp_vmulas_s16_qacc timm:$qx, timm:$qy)]>; + +def ESP_VMULAS_S16_QACC_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.s16.qacc.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_QACC_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vmulas_s16_qacc_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_s16_qacc_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VMULAS_S16_QACC_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.s16.qacc.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_QACC_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_s16_qacc_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_s16_qacc_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_S16_QACC_ST_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.s16.qacc.st.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<4> off1616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_QACC_ST_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "!esp_vmulas_s16_qacc_st_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_s16_qacc_st_ip timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$off1616)]>; + +def ESP_VMULAS_S16_QACC_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmulas.s16.qacc.st.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_QACC_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1), + "!esp_vmulas_s16_qacc_st_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_s16_qacc_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VMULAS_S16_XACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vmulas.s16.xacc\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_XACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vmulas_s16_xacc_p $qx, $qy", + [(int_riscv_esp_vmulas_s16_xacc timm:$qx, timm:$qy)]>; + +def ESP_VMULAS_S16_XACC_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.s16.xacc.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_XACC_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vmulas_s16_xacc_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_s16_xacc_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VMULAS_S16_XACC_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.s16.xacc.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_XACC_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_s16_xacc_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_s16_xacc_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_S16_XACC_ST_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.s16.xacc.st.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<4> off1616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_XACC_ST_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "!esp_vmulas_s16_xacc_st_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_s16_xacc_st_ip timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$off1616)]>; + +def ESP_VMULAS_S16_XACC_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmulas.s16.xacc.st.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_XACC_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1), + "!esp_vmulas_s16_xacc_st_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_s16_xacc_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VMULAS_S8_QACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vmulas.s8.qacc\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vmulas_s8_qacc_p $qx, $qy", + [(int_riscv_esp_vmulas_s8_qacc timm:$qx, timm:$qy)]>; + +def ESP_VMULAS_S8_QACC_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.s8.qacc.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_QACC_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vmulas_s8_qacc_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_s8_qacc_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VMULAS_S8_QACC_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.s8.qacc.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_QACC_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_s8_qacc_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_s8_qacc_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_S8_QACC_ST_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.s8.qacc.st.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<4> off1616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_QACC_ST_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "!esp_vmulas_s8_qacc_st_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_s8_qacc_st_ip timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$off1616)]>; + +def ESP_VMULAS_S8_QACC_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmulas.s8.qacc.st.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_QACC_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1), + "!esp_vmulas_s8_qacc_st_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_s8_qacc_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VMULAS_S8_XACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vmulas.s8.xacc\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_XACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vmulas_s8_xacc_p $qx, $qy", + [(int_riscv_esp_vmulas_s8_xacc timm:$qx, timm:$qy)]>; + +def ESP_VMULAS_S8_XACC_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.s8.xacc.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_XACC_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vmulas_s8_xacc_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_s8_xacc_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VMULAS_S8_XACC_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.s8.xacc.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_XACC_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_s8_xacc_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_s8_xacc_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_S8_XACC_ST_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.s8.xacc.st.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<4> off1616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_XACC_ST_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "!esp_vmulas_s8_xacc_st_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_s8_xacc_st_ip timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$off1616)]>; + +def ESP_VMULAS_S8_XACC_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmulas.s8.xacc.st.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_XACC_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1), + "!esp_vmulas_s8_xacc_st_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_s8_xacc_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VMULAS_U16_QACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vmulas.u16.qacc\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vmulas_u16_qacc_p $qx, $qy", + [(int_riscv_esp_vmulas_u16_qacc timm:$qx, timm:$qy)]>; + +def ESP_VMULAS_U16_QACC_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.u16.qacc.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_QACC_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vmulas_u16_qacc_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_u16_qacc_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VMULAS_U16_QACC_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.u16.qacc.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_QACC_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_u16_qacc_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_u16_qacc_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_U16_QACC_ST_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.u16.qacc.st.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<4> off1616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_QACC_ST_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "!esp_vmulas_u16_qacc_st_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_u16_qacc_st_ip timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$off1616)]>; + +def ESP_VMULAS_U16_QACC_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmulas.u16.qacc.st.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_QACC_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1), + "!esp_vmulas_u16_qacc_st_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_u16_qacc_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VMULAS_U16_XACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vmulas.u16.xacc\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_XACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vmulas_u16_xacc_p $qx, $qy", + [(int_riscv_esp_vmulas_u16_xacc timm:$qx, timm:$qy)]>; + +def ESP_VMULAS_U16_XACC_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.u16.xacc.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_XACC_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vmulas_u16_xacc_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_u16_xacc_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VMULAS_U16_XACC_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.u16.xacc.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_XACC_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_u16_xacc_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_u16_xacc_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_U16_XACC_ST_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.u16.xacc.st.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<4> off1616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_XACC_ST_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "!esp_vmulas_u16_xacc_st_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_u16_xacc_st_ip timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$off1616)]>; + +def ESP_VMULAS_U16_XACC_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmulas.u16.xacc.st.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_XACC_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1), + "!esp_vmulas_u16_xacc_st_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_u16_xacc_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VMULAS_U8_QACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vmulas.u8.qacc\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vmulas_u8_qacc_p $qx, $qy", + [(int_riscv_esp_vmulas_u8_qacc timm:$qx, timm:$qy)]>; + +def ESP_VMULAS_U8_QACC_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.u8.qacc.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_QACC_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vmulas_u8_qacc_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_u8_qacc_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VMULAS_U8_QACC_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.u8.qacc.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_QACC_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_u8_qacc_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_u8_qacc_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_U8_QACC_ST_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.u8.qacc.st.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<4> off1616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_QACC_ST_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "!esp_vmulas_u8_qacc_st_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_u8_qacc_st_ip timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$off1616)]>; + +def ESP_VMULAS_U8_QACC_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmulas.u8.qacc.st.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_QACC_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1), + "!esp_vmulas_u8_qacc_st_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_u8_qacc_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VMULAS_U8_XACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy), + "esp.vmulas.u8.xacc\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_XACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vmulas_u8_xacc_p $qx, $qy", + [(int_riscv_esp_vmulas_u8_xacc timm:$qx, timm:$qy)]>; + +def ESP_VMULAS_U8_XACC_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.u8.xacc.ld.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_XACC_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu), + "!esp_vmulas_u8_xacc_ld_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_u8_xacc_ld_ip timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$off1616, timm:$qu)]>; + +def ESP_VMULAS_U8_XACC_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.u8.xacc.ld.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_XACC_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_u8_xacc_ld_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_u8_xacc_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_U8_XACC_ST_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vmulas.u8.xacc.st.ip\t $qu, $rs1, $off1616, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<4> off1616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21-19} = off1616{3-1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off1616{0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_XACC_ST_IP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, offset_16_16:$off1616), + "!esp_vmulas_u8_xacc_st_ip_p $qu, $rs1, $off1616, $qx, $qy", + [(int_riscv_esp_vmulas_u8_xacc_st_ip timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$off1616)]>; + +def ESP_VMULAS_U8_XACC_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmulas.u8.xacc.st.xp\t $qu, $rs1, $rs2, $qx, $qy", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_XACC_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1), + "!esp_vmulas_u8_xacc_st_xp_p $qu, $rs1, $rs2, $qx, $qy", + [(int_riscv_esp_vmulas_u8_xacc_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VMULAS_S16_QACC_LDBC_INCP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.s16.qacc.ldbc.incp\t $qu, $rs1, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S16_QACC_LDBC_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_s16_qacc_ldbc_incp_p $qu, $rs1, $qx, $qy", + [(int_riscv_esp_vmulas_s16_qacc_ldbc_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_S8_QACC_LDBC_INCP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.s8.qacc.ldbc.incp\t $qu, $rs1, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_S8_QACC_LDBC_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_s8_qacc_ldbc_incp_p $qu, $rs1, $qx, $qy", + [(int_riscv_esp_vmulas_s8_qacc_ldbc_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_U16_QACC_LDBC_INCP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.u16.qacc.ldbc.incp\t $qu, $rs1, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U16_QACC_LDBC_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_u16_qacc_ldbc_incp_p $qu, $rs1, $qx, $qy", + [(int_riscv_esp_vmulas_u16_qacc_ldbc_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VMULAS_U8_QACC_LDBC_INCP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmulas.u8.qacc.ldbc.incp\t $qu, $rs1, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMULAS_U8_QACC_LDBC_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qu), + "!esp_vmulas_u8_qacc_ldbc_incp_p $qu, $rs1, $qx, $qy", + [(int_riscv_esp_vmulas_u8_qacc_ldbc_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VSMULAS_S16_QACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy, select_16:$sel16), + "esp.vsmulas.s16.qacc\t $qx, $qy, $sel16", []> +{ + bits<3> qx; + bits<3> qy; + bits<4> sel16; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18-15} = sel16{3-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSMULAS_S16_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_16:$sel16), + "!esp_vsmulas_s16_qacc_p $qx, $qy, $sel16", + [(int_riscv_esp_vsmulas_s16_qacc timm:$qx, timm:$qy, timm:$sel16)]>; + +def ESP_VSMULAS_S16_QACC_LD_INCP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_16:$sel16), + "esp.vsmulas.s16.qacc.ld.incp\t $qu, $rs1, $qx, $qy, $sel16", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> sel16; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22-19} = sel16{3-0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSMULAS_S16_QACC_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_16:$sel16, imm8:$qu), + "!esp_vsmulas_s16_qacc_ld_incp_p $qu, $rs1, $qx, $qy, $sel16", + [(int_riscv_esp_vsmulas_s16_qacc_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel16, timm:$qu)]>; + +def ESP_VSMULAS_S8_QACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy, select_16:$sel16), + "esp.vsmulas.s8.qacc\t $qx, $qy, $sel16", []> +{ + bits<3> qx; + bits<3> qy; + bits<4> sel16; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18-15} = sel16{3-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSMULAS_S8_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_16:$sel16), + "!esp_vsmulas_s8_qacc_p $qx, $qy, $sel16", + [(int_riscv_esp_vsmulas_s8_qacc timm:$qx, timm:$qy, timm:$sel16)]>; + +def ESP_VSMULAS_S8_QACC_LD_INCP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_16:$sel16), + "esp.vsmulas.s8.qacc.ld.incp\t $qu, $rs1, $qx, $qy, $sel16", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> sel16; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22-19} = sel16{3-0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSMULAS_S8_QACC_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_16:$sel16, imm8:$qu), + "!esp_vsmulas_s8_qacc_ld_incp_p $qu, $rs1, $qx, $qy, $sel16", + [(int_riscv_esp_vsmulas_s8_qacc_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel16, timm:$qu)]>; + +def ESP_VSMULAS_U16_QACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy, select_16:$sel16), + "esp.vsmulas.u16.qacc\t $qx, $qy, $sel16", []> +{ + bits<3> qx; + bits<3> qy; + bits<4> sel16; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18-15} = sel16{3-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSMULAS_U16_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_16:$sel16), + "!esp_vsmulas_u16_qacc_p $qx, $qy, $sel16", + [(int_riscv_esp_vsmulas_u16_qacc timm:$qx, timm:$qy, timm:$sel16)]>; + +def ESP_VSMULAS_U16_QACC_LD_INCP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_16:$sel16), + "esp.vsmulas.u16.qacc.ld.incp\t $qu, $rs1, $qx, $qy, $sel16", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> sel16; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-19} = sel16{3-0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSMULAS_U16_QACC_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_16:$sel16, imm8:$qu), + "!esp_vsmulas_u16_qacc_ld_incp_p $qu, $rs1, $qx, $qy, $sel16", + [(int_riscv_esp_vsmulas_u16_qacc_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel16, timm:$qu)]>; + +def ESP_VSMULAS_U8_QACC: Esp32P4Inst<(outs), (ins QR:$qx, QR:$qy, select_16:$sel16), + "esp.vsmulas.u8.qacc\t $qx, $qy, $sel16", []> +{ + bits<3> qx; + bits<3> qy; + bits<4> sel16; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18-15} = sel16{3-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSMULAS_U8_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_16:$sel16), + "!esp_vsmulas_u8_qacc_p $qx, $qy, $sel16", + [(int_riscv_esp_vsmulas_u8_qacc timm:$qx, timm:$qy, timm:$sel16)]>; + +def ESP_VSMULAS_U8_QACC_LD_INCP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_16:$sel16), + "esp.vsmulas.u8.qacc.ld.incp\t $qu, $rs1, $qx, $qy, $sel16", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<4> sel16; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-19} = sel16{3-0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSMULAS_U8_QACC_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_16:$sel16, imm8:$qu), + "!esp_vsmulas_u8_qacc_ld_incp_p $qu, $rs1, $qx, $qy, $sel16", + [(int_riscv_esp_vsmulas_u8_qacc_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel16, timm:$qu)]>; + +def ESP_CMUL_S16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy, select_4:$sel4), + "esp.cmul.s16\t $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<2> sel4; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16-15} = sel4{1-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_4:$sel4, imm8:$qz), + "!esp_cmul_s16_p $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_s16 timm:$qx, timm:$qy, timm:$sel4, timm:$qz)]>; + +def ESP_CMUL_S16_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_4:$sel4), + "esp.cmul.s16.ld.incp\t $qu, $rs1, $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21-20} = sel4{1-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_S16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_4:$sel4, imm8:$qz, imm8:$qu), + "!esp_cmul_s16_ld_incp_p $qu, $rs1, $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_s16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel4, timm:$qz, timm:$qu)]>; + +def ESP_CMUL_S16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, select_4:$sel4), + "esp.cmul.s16.st.incp\t $qu, $rs1, $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21-20} = sel4{1-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_S16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, select_4:$sel4, imm8:$qz), + "!esp_cmul_s16_st_incp_p $qu, $rs1, $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_s16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$sel4, timm:$qz)]>; + +def ESP_CMUL_S8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy, select_4:$sel4), + "esp.cmul.s8\t $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<2> sel4; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16-15} = sel4{1-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_4:$sel4, imm8:$qz), + "!esp_cmul_s8_p $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_s8 timm:$qx, timm:$qy, timm:$sel4, timm:$qz)]>; + +def ESP_CMUL_S8_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_4:$sel4), + "esp.cmul.s8.ld.incp\t $qu, $rs1, $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21-20} = sel4{1-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_S8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_4:$sel4, imm8:$qz, imm8:$qu), + "!esp_cmul_s8_ld_incp_p $qu, $rs1, $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_s8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel4, timm:$qz, timm:$qu)]>; + +def ESP_CMUL_S8_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, select_4:$sel4), + "esp.cmul.s8.st.incp\t $qu, $rs1, $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21-20} = sel4{1-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_S8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, select_4:$sel4, imm8:$qz), + "!esp_cmul_s8_st_incp_p $qu, $rs1, $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_s8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$sel4, timm:$qz)]>; + +def ESP_CMUL_U16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy, select_4:$sel4), + "esp.cmul.u16\t $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<2> sel4; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16-15} = sel4{1-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_4:$sel4, imm8:$qz), + "!esp_cmul_u16_p $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_u16 timm:$qx, timm:$qy, timm:$sel4, timm:$qz)]>; + +def ESP_CMUL_U16_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_4:$sel4), + "esp.cmul.u16.ld.incp\t $qu, $rs1, $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21-20} = sel4{1-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_U16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_4:$sel4, imm8:$qz, imm8:$qu), + "!esp_cmul_u16_ld_incp_p $qu, $rs1, $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_u16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel4, timm:$qz, timm:$qu)]>; + +def ESP_CMUL_U16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, select_4:$sel4), + "esp.cmul.u16.st.incp\t $qu, $rs1, $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21-20} = sel4{1-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_U16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, select_4:$sel4, imm8:$qz), + "!esp_cmul_u16_st_incp_p $qu, $rs1, $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_u16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$sel4, timm:$qz)]>; + +def ESP_CMUL_U8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy, select_4:$sel4), + "esp.cmul.u8\t $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<2> sel4; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16-15} = sel4{1-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_4:$sel4, imm8:$qz), + "!esp_cmul_u8_p $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_u8 timm:$qx, timm:$qy, timm:$sel4, timm:$qz)]>; + +def ESP_CMUL_U8_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_4:$sel4), + "esp.cmul.u8.ld.incp\t $qu, $rs1, $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21-20} = sel4{1-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_U8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_4:$sel4, imm8:$qz, imm8:$qu), + "!esp_cmul_u8_ld_incp_p $qu, $rs1, $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_u8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel4, timm:$qz, timm:$qu)]>; + +def ESP_CMUL_U8_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, select_4:$sel4), + "esp.cmul.u8.st.incp\t $qu, $rs1, $qz, $qx, $qy, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21-20} = sel4{1-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_CMUL_U8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, select_4:$sel4, imm8:$qz), + "!esp_cmul_u8_st_incp_p $qu, $rs1, $qz, $qx, $qy, $sel4", + [(int_riscv_esp_cmul_u8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$sel4, timm:$qz)]>; + +def ESP_MAX_S16_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.max.s16.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MAX_S16_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_max_s16_a_p $qw, $rd", + [(int_riscv_esp_max_s16_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MAX_S32_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.max.s32.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MAX_S32_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_max_s32_a_p $qw, $rd", + [(int_riscv_esp_max_s32_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MAX_S8_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.max.s8.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MAX_S8_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_max_s8_a_p $qw, $rd", + [(int_riscv_esp_max_s8_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MAX_U16_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.max.u16.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MAX_U16_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_max_u16_a_p $qw, $rd", + [(int_riscv_esp_max_u16_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MAX_U32_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.max.u32.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MAX_U32_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_max_u32_a_p $qw, $rd", + [(int_riscv_esp_max_u32_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MAX_U8_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.max.u8.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MAX_U8_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_max_u8_a_p $qw, $rd", + [(int_riscv_esp_max_u8_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MIN_S16_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.min.s16.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MIN_S16_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_min_s16_a_p $qw, $rd", + [(int_riscv_esp_min_s16_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MIN_S32_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.min.s32.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MIN_S32_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_min_s32_a_p $qw, $rd", + [(int_riscv_esp_min_s32_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MIN_S8_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.min.s8.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MIN_S8_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_min_s8_a_p $qw, $rd", + [(int_riscv_esp_min_s8_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MIN_U16_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.min.u16.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MIN_U16_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_min_u16_a_p $qw, $rd", + [(int_riscv_esp_min_u16_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MIN_U32_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.min.u32.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MIN_U32_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_min_u32_a_p $qw, $rd", + [(int_riscv_esp_min_u32_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_MIN_U8_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qw), + "esp.min.u8.a\t $qw, $rd", []> +{ + bits<3> qw; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MIN_U8_A_P : PseudoESP32P4<(outs), (ins imm8:$qw, GPRPIE:$rd), + "!esp_min_u8_a_p $qw, $rd", + [(int_riscv_esp_min_u8_a timm:$qw, GPRPIE:$rd)]>; + +def ESP_VABS_16: Esp32P4Inst<(outs QR:$qv), (ins QR:$qy), + "esp.vabs.16\t $qv, $qy", []> +{ + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VABS_16_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qv), + "!esp_vabs_16_p $qv, $qy", + [(int_riscv_esp_vabs_16 timm:$qy, timm:$qv)]>; + +def ESP_VABS_32: Esp32P4Inst<(outs QR:$qv), (ins QR:$qy), + "esp.vabs.32\t $qv, $qy", []> +{ + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VABS_32_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qv), + "!esp_vabs_32_p $qv, $qy", + [(int_riscv_esp_vabs_32 timm:$qy, timm:$qv)]>; + +def ESP_VABS_8: Esp32P4Inst<(outs QR:$qv), (ins QR:$qy), + "esp.vabs.8\t $qv, $qy", []> +{ + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VABS_8_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qv), + "!esp_vabs_8_p $qv, $qy", + [(int_riscv_esp_vabs_8 timm:$qy, timm:$qv)]>; + +def ESP_VADD_S16: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vadd.s16\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vadd_s16_p $qv, $qx, $qy", + [(int_riscv_esp_vadd_s16 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VADD_S16_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vadd.s16.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vadd_s16_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_s16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VADD_S16_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vadd.s16.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vadd_s16_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_s16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VADD_S32: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vadd.s32\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vadd_s32_p $qv, $qx, $qy", + [(int_riscv_esp_vadd_s32 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VADD_S32_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vadd.s32.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S32_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vadd_s32_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_s32_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VADD_S32_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vadd.s32.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S32_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vadd_s32_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_s32_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VADD_S8: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vadd.s8\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vadd_s8_p $qv, $qx, $qy", + [(int_riscv_esp_vadd_s8 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VADD_S8_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vadd.s8.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vadd_s8_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_s8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VADD_S8_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vadd.s8.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_S8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vadd_s8_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_s8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VADD_U16: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vadd.u16\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vadd_u16_p $qv, $qx, $qy", + [(int_riscv_esp_vadd_u16 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VADD_U16_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vadd.u16.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vadd_u16_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_u16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VADD_U16_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vadd.u16.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vadd_u16_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_u16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VADD_U32: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vadd.u32\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vadd_u32_p $qv, $qx, $qy", + [(int_riscv_esp_vadd_u32 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VADD_U32_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vadd.u32.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U32_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vadd_u32_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_u32_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VADD_U32_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vadd.u32.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U32_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vadd_u32_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_u32_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VADD_U8: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vadd.u8\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vadd_u8_p $qv, $qx, $qy", + [(int_riscv_esp_vadd_u8 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VADD_U8_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vadd.u8.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vadd_u8_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_u8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VADD_U8_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vadd.u8.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VADD_U8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vadd_u8_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vadd_u8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VCLAMP_S16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, select_16:$sel16), + "esp.vclamp.s16\t $qz, $qx, $sel16", []> +{ + bits<3> qx; + bits<4> sel16; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = sel16{3-2}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19-18} = sel16{1-0}; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCLAMP_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, select_16:$sel16, imm8:$qz), + "!esp_vclamp_s16_p $qz, $qx, $sel16", + [(int_riscv_esp_vclamp_s16 timm:$qx, timm:$sel16, timm:$qz)]>; + +def ESP_VMAX_S16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmax.s16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmax_s16_p $qz, $qx, $qy", + [(int_riscv_esp_vmax_s16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMAX_S16_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmax.s16.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmax_s16_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_s16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMAX_S16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmax.s16.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmax_s16_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_s16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMAX_S32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmax.s32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmax_s32_p $qz, $qx, $qy", + [(int_riscv_esp_vmax_s32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMAX_S32_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmax.s32.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S32_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmax_s32_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_s32_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMAX_S32_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmax.s32.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S32_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmax_s32_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_s32_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMAX_S8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmax.s8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmax_s8_p $qz, $qx, $qy", + [(int_riscv_esp_vmax_s8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMAX_S8_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmax.s8.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmax_s8_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_s8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMAX_S8_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmax.s8.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_S8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmax_s8_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_s8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMAX_U16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmax.u16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmax_u16_p $qz, $qx, $qy", + [(int_riscv_esp_vmax_u16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMAX_U16_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmax.u16.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmax_u16_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_u16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMAX_U16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmax.u16.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmax_u16_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_u16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMAX_U32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmax.u32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmax_u32_p $qz, $qx, $qy", + [(int_riscv_esp_vmax_u32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMAX_U32_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmax.u32.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U32_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmax_u32_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_u32_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMAX_U32_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmax.u32.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U32_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmax_u32_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_u32_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMAX_U8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmax.u8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmax_u8_p $qz, $qx, $qy", + [(int_riscv_esp_vmax_u8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMAX_U8_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmax.u8.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmax_u8_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_u8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMAX_U8_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmax.u8.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMAX_U8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmax_u8_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmax_u8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMIN_S16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmin.s16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmin_s16_p $qz, $qx, $qy", + [(int_riscv_esp_vmin_s16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMIN_S16_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmin.s16.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmin_s16_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_s16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMIN_S16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmin.s16.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmin_s16_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_s16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMIN_S32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmin.s32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmin_s32_p $qz, $qx, $qy", + [(int_riscv_esp_vmin_s32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMIN_S32_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmin.s32.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S32_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmin_s32_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_s32_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMIN_S32_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmin.s32.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S32_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmin_s32_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_s32_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMIN_S8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmin.s8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmin_s8_p $qz, $qx, $qy", + [(int_riscv_esp_vmin_s8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMIN_S8_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmin.s8.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmin_s8_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_s8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMIN_S8_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmin.s8.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_S8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmin_s8_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_s8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMIN_U16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmin.u16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmin_u16_p $qz, $qx, $qy", + [(int_riscv_esp_vmin_u16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMIN_U16_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmin.u16.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmin_u16_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_u16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMIN_U16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmin.u16.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmin_u16_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_u16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMIN_U32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmin.u32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmin_u32_p $qz, $qx, $qy", + [(int_riscv_esp_vmin_u32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMIN_U32_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmin.u32.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U32_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmin_u32_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_u32_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMIN_U32_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmin.u32.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U32_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmin_u32_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_u32_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMIN_U8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmin.u8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmin_u8_p $qz, $qx, $qy", + [(int_riscv_esp_vmin_u8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMIN_U8_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmin.u8.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmin_u8_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_u8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMIN_U8_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmin.u8.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMIN_U8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmin_u8_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmin_u8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMUL_S16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmul.s16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmul_s16_p $qz, $qx, $qy", + [(int_riscv_esp_vmul_s16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMUL_S16_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmul.s16.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_S16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmul_s16_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmul_s16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMUL_S16_S8XS8: Esp32P4Inst<(outs QR:$qz, QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vmul.s16.s8xs8\t $qz, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_S16_S8XS8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz, imm8:$qv), + "!esp_vmul_s16_s8xs8_p $qz, $qv, $qx, $qy", + [(int_riscv_esp_vmul_s16_s8xs8 timm:$qx, timm:$qy, timm:$qz, timm:$qv)]>; + +def ESP_VMUL_S16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmul.s16.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_S16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmul_s16_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmul_s16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMUL_S32_S16XS16: Esp32P4Inst<(outs QR:$qz, QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vmul.s32.s16xs16\t $qz, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_S32_S16XS16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz, imm8:$qv), + "!esp_vmul_s32_s16xs16_p $qz, $qv, $qx, $qy", + [(int_riscv_esp_vmul_s32_s16xs16 timm:$qx, timm:$qy, timm:$qz, timm:$qv)]>; + +def ESP_VMUL_S8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmul.s8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmul_s8_p $qz, $qx, $qy", + [(int_riscv_esp_vmul_s8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMUL_S8_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmul.s8.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_S8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmul_s8_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmul_s8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMUL_S8_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmul.s8.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_S8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmul_s8_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmul_s8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMUL_U16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmul.u16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmul_u16_p $qz, $qx, $qy", + [(int_riscv_esp_vmul_u16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMUL_U16_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmul.u16.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_U16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmul_u16_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmul_u16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMUL_U16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmul.u16.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_U16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmul_u16_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmul_u16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VMUL_U8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vmul.u8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vmul_u8_p $qz, $qx, $qy", + [(int_riscv_esp_vmul_u8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VMUL_U8_LD_INCP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vmul.u8.ld.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_U8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qz, imm8:$qu), + "!esp_vmul_u8_ld_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmul_u8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qz, timm:$qu)]>; + +def ESP_VMUL_U8_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vmul.u8.st.incp\t $qu, $rs1, $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VMUL_U8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qz), + "!esp_vmul_u8_st_incp_p $qu, $rs1, $qz, $qx, $qy", + [(int_riscv_esp_vmul_u8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qz)]>; + +def ESP_VPRELU_S16: Esp32P4Inst<(outs QR:$qz), (ins GPRPIE:$rs1, QR:$qx, QR:$qy), + "esp.vprelu.s16\t $qz, $qy, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VPRELU_S16_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vprelu_s16_p $qz, $qy, $qx, $rs1", + [(int_riscv_esp_vprelu_s16 GPRPIE:$rs1, timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VPRELU_S8: Esp32P4Inst<(outs QR:$qz), (ins GPRPIE:$rs1, QR:$qx, QR:$qy), + "esp.vprelu.s8\t $qz, $qy, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VPRELU_S8_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vprelu_s8_p $qz, $qy, $qx, $rs1", + [(int_riscv_esp_vprelu_s8 GPRPIE:$rs1, timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VRELU_S16: Esp32P4Inst<(outs QR:$qyr), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qy), + "esp.vrelu.s16\t $qy, $rs2, $rs1", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qy; + bits<3> qyr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qyr = $qy"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VRELU_S16_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qy), + "!esp_vrelu_s16_p $qy, $rs2, $rs1", + [(int_riscv_esp_vrelu_s16 GPRPIE:$rs1, GPRPIE:$rs2, timm:$qy)]>; + +def ESP_VRELU_S8: Esp32P4Inst<(outs QR:$qyr), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qy), + "esp.vrelu.s8\t $qy, $rs2, $rs1", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qy; + bits<3> qyr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qyr = $qy"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VRELU_S8_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qy), + "!esp_vrelu_s8_p $qy, $rs2, $rs1", + [(int_riscv_esp_vrelu_s8 GPRPIE:$rs1, GPRPIE:$rs2, timm:$qy)]>; + +def ESP_VSADDS_S16: Esp32P4Inst<(outs QR:$qv), (ins GPRPIE:$rs1, QR:$qx), + "esp.vsadds.s16\t $qv, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSADDS_S16_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qv), + "!esp_vsadds_s16_p $qv, $qx, $rs1", + [(int_riscv_esp_vsadds_s16 GPRPIE:$rs1, timm:$qx, timm:$qv)]>; + +def ESP_VSADDS_S8: Esp32P4Inst<(outs QR:$qv), (ins GPRPIE:$rs1, QR:$qx), + "esp.vsadds.s8\t $qv, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSADDS_S8_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qv), + "!esp_vsadds_s8_p $qv, $qx, $rs1", + [(int_riscv_esp_vsadds_s8 GPRPIE:$rs1, timm:$qx, timm:$qv)]>; + +def ESP_VSADDS_U16: Esp32P4Inst<(outs QR:$qv), (ins GPRPIE:$rs1, QR:$qx), + "esp.vsadds.u16\t $qv, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSADDS_U16_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qv), + "!esp_vsadds_u16_p $qv, $qx, $rs1", + [(int_riscv_esp_vsadds_u16 GPRPIE:$rs1, timm:$qx, timm:$qv)]>; + +def ESP_VSADDS_U8: Esp32P4Inst<(outs QR:$qv), (ins GPRPIE:$rs1, QR:$qx), + "esp.vsadds.u8\t $qv, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSADDS_U8_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qv), + "!esp_vsadds_u8_p $qv, $qx, $rs1", + [(int_riscv_esp_vsadds_u8 GPRPIE:$rs1, timm:$qx, timm:$qv)]>; + +def ESP_VSAT_S16: Esp32P4Inst<(outs QR:$qz), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qx), + "esp.vsat.s16\t $qz, $qx, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qx; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSAT_S16_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qx, imm8:$qz), + "!esp_vsat_s16_p $qz, $qx, $rs1, $rs2", + [(int_riscv_esp_vsat_s16 GPRPIE:$rs1, GPRPIE:$rs2, timm:$qx, timm:$qz)]>; + +def ESP_VSAT_S32: Esp32P4Inst<(outs QR:$qz), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qx), + "esp.vsat.s32\t $qz, $qx, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qx; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSAT_S32_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qx, imm8:$qz), + "!esp_vsat_s32_p $qz, $qx, $rs1, $rs2", + [(int_riscv_esp_vsat_s32 GPRPIE:$rs1, GPRPIE:$rs2, timm:$qx, timm:$qz)]>; + +def ESP_VSAT_S8: Esp32P4Inst<(outs QR:$qz), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qx), + "esp.vsat.s8\t $qz, $qx, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qx; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSAT_S8_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qx, imm8:$qz), + "!esp_vsat_s8_p $qz, $qx, $rs1, $rs2", + [(int_riscv_esp_vsat_s8 GPRPIE:$rs1, GPRPIE:$rs2, timm:$qx, timm:$qz)]>; + +def ESP_VSAT_U16: Esp32P4Inst<(outs QR:$qz), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qx), + "esp.vsat.u16\t $qz, $qx, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qx; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSAT_U16_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qx, imm8:$qz), + "!esp_vsat_u16_p $qz, $qx, $rs1, $rs2", + [(int_riscv_esp_vsat_u16 GPRPIE:$rs1, GPRPIE:$rs2, timm:$qx, timm:$qz)]>; + +def ESP_VSAT_U32: Esp32P4Inst<(outs QR:$qz), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qx), + "esp.vsat.u32\t $qz, $qx, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qx; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSAT_U32_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qx, imm8:$qz), + "!esp_vsat_u32_p $qz, $qx, $rs1, $rs2", + [(int_riscv_esp_vsat_u32 GPRPIE:$rs1, GPRPIE:$rs2, timm:$qx, timm:$qz)]>; + +def ESP_VSAT_U8: Esp32P4Inst<(outs QR:$qz), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qx), + "esp.vsat.u8\t $qz, $qx, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qx; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSAT_U8_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qx, imm8:$qz), + "!esp_vsat_u8_p $qz, $qx, $rs1, $rs2", + [(int_riscv_esp_vsat_u8 GPRPIE:$rs1, GPRPIE:$rs2, timm:$qx, timm:$qz)]>; + +def ESP_VSSUBS_S16: Esp32P4Inst<(outs QR:$qv), (ins GPRPIE:$rs1, QR:$qx), + "esp.vssubs.s16\t $qv, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSSUBS_S16_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qv), + "!esp_vssubs_s16_p $qv, $qx, $rs1", + [(int_riscv_esp_vssubs_s16 GPRPIE:$rs1, timm:$qx, timm:$qv)]>; + +def ESP_VSSUBS_S8: Esp32P4Inst<(outs QR:$qv), (ins GPRPIE:$rs1, QR:$qx), + "esp.vssubs.s8\t $qv, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSSUBS_S8_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qv), + "!esp_vssubs_s8_p $qv, $qx, $rs1", + [(int_riscv_esp_vssubs_s8 GPRPIE:$rs1, timm:$qx, timm:$qv)]>; + +def ESP_VSSUBS_U16: Esp32P4Inst<(outs QR:$qv), (ins GPRPIE:$rs1, QR:$qx), + "esp.vssubs.u16\t $qv, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSSUBS_U16_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qv), + "!esp_vssubs_u16_p $qv, $qx, $rs1", + [(int_riscv_esp_vssubs_u16 GPRPIE:$rs1, timm:$qx, timm:$qv)]>; + +def ESP_VSSUBS_U8: Esp32P4Inst<(outs QR:$qv), (ins GPRPIE:$rs1, QR:$qx), + "esp.vssubs.u8\t $qv, $qx, $rs1", []> +{ + bits<5> rs1; + bits<3> qx; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSSUBS_U8_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qx, imm8:$qv), + "!esp_vssubs_u8_p $qv, $qx, $rs1", + [(int_riscv_esp_vssubs_u8 GPRPIE:$rs1, timm:$qx, timm:$qv)]>; + +def ESP_VSUB_S16: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vsub.s16\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vsub_s16_p $qv, $qx, $qy", + [(int_riscv_esp_vsub_s16 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VSUB_S16_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vsub.s16.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vsub_s16_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_s16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VSUB_S16_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vsub.s16.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vsub_s16_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_s16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VSUB_S32: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vsub.s32\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vsub_s32_p $qv, $qx, $qy", + [(int_riscv_esp_vsub_s32 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VSUB_S32_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vsub.s32.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S32_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vsub_s32_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_s32_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VSUB_S32_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vsub.s32.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S32_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vsub_s32_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_s32_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VSUB_S8: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vsub.s8\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vsub_s8_p $qv, $qx, $qy", + [(int_riscv_esp_vsub_s8 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VSUB_S8_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vsub.s8.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vsub_s8_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_s8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VSUB_S8_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vsub.s8.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 1; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_S8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vsub_s8_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_s8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VSUB_U16: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vsub.u16\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vsub_u16_p $qv, $qx, $qy", + [(int_riscv_esp_vsub_u16 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VSUB_U16_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vsub.u16.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vsub_u16_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_u16_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VSUB_U16_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vsub.u16.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vsub_u16_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_u16_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VSUB_U32: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vsub.u32\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vsub_u32_p $qv, $qx, $qy", + [(int_riscv_esp_vsub_u32 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VSUB_U32_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vsub.u32.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U32_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vsub_u32_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_u32_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VSUB_U32_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vsub.u32.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U32_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vsub_u32_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_u32_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_VSUB_U8: Esp32P4Inst<(outs QR:$qv), (ins QR:$qx, QR:$qy), + "esp.vsub.u8\t $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qv), + "!esp_vsub_u8_p $qv, $qx, $qy", + [(int_riscv_esp_vsub_u8 timm:$qx, timm:$qy, timm:$qv)]>; + +def ESP_VSUB_U8_LD_INCP: Esp32P4Inst<(outs QR:$qv, QR:$qu, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1), + "esp.vsub.u8.ld.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> qv; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U8_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, imm8:$qv, imm8:$qu), + "!esp_vsub_u8_ld_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_u8_ld_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$qv, timm:$qu)]>; + +def ESP_VSUB_U8_ST_INCP: Esp32P4Inst<(outs QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1), + "esp.vsub.u8.st.incp\t $qu, $rs1, $qv, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSUB_U8_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, imm8:$qv), + "!esp_vsub_u8_st_incp_p $qu, $rs1, $qv, $qx, $qy", + [(int_riscv_esp_vsub_u8_st_incp timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$qv)]>; + +def ESP_ADDX2: Esp32P4Inst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), + "esp.addx2\t $rd, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24-20} = rs2{4-0}; + let Inst{19-15} = rs1{4-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11-7} = rd{4-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 0; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ADDX2_P : PseudoESP32P4<(outs), (ins GPR:$rs1, GPR:$rs2, GPR:$rd), + "!esp_addx2_p $rd, $rs1, $rs2", + [(int_riscv_esp_addx2 GPR:$rs1, GPR:$rs2, GPR:$rd)]>; + +def ESP_ADDX4: Esp32P4Inst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), + "esp.addx4\t $rd, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24-20} = rs2{4-0}; + let Inst{19-15} = rs1{4-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11-7} = rd{4-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 0; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ADDX4_P : PseudoESP32P4<(outs), (ins GPR:$rs1, GPR:$rs2, GPR:$rd), + "!esp_addx4_p $rd, $rs1, $rs2", + [(int_riscv_esp_addx4 GPR:$rs1, GPR:$rs2, GPR:$rd)]>; + +def ESP_SAT: Esp32P4Inst<(outs GPR:$rsdr), (ins GPR:$rs0, GPR:$rs1, GPR:$rsd), + "esp.sat\t $rsd, $rs0, $rs1", []> +{ + bits<5> rs0; + bits<5> rs1; + bits<5> rsd; + bits<5> rsdr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rsdr = $rsd"; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24-20} = rsd{4-0}; + let Inst{19-15} = rs1{4-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11-7} = rs0{4-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 0; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SAT_P : PseudoESP32P4<(outs), (ins GPR:$rs0, GPR:$rs1, GPR:$rsd), + "!esp_sat_p $rsd, $rs0, $rs1", + [(int_riscv_esp_sat GPR:$rs0, GPR:$rs1, GPR:$rsd)]>; + +def ESP_SUBX2: Esp32P4Inst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), + "esp.subx2\t $rd, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24-20} = rs2{4-0}; + let Inst{19-15} = rs1{4-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11-7} = rd{4-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 0; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SUBX2_P : PseudoESP32P4<(outs), (ins GPR:$rs1, GPR:$rs2, GPR:$rd), + "!esp_subx2_p $rd, $rs1, $rs2", + [(int_riscv_esp_subx2 GPR:$rs1, GPR:$rs2, GPR:$rd)]>; + +def ESP_SUBX4: Esp32P4Inst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), + "esp.subx4\t $rd, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24-20} = rs2{4-0}; + let Inst{19-15} = rs1{4-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11-7} = rd{4-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 0; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SUBX4_P : PseudoESP32P4<(outs), (ins GPR:$rs1, GPR:$rs2, GPR:$rd), + "!esp_subx4_p $rd, $rs1, $rs2", + [(int_riscv_esp_subx4 GPR:$rs1, GPR:$rs2, GPR:$rd)]>; + +def ESP_ANDQ: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.andq\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ANDQ_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_andq_p $qz, $qx, $qy", + [(int_riscv_esp_andq timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_NOTQ: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx), + "esp.notq\t $qz, $qx", []> +{ + bits<3> qx; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_NOTQ_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qz), + "!esp_notq_p $qz, $qx", + [(int_riscv_esp_notq timm:$qx, timm:$qz)]>; + +def ESP_ORQ: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.orq\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ORQ_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_orq_p $qz, $qx, $qy", + [(int_riscv_esp_orq timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_XORQ: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.xorq\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_XORQ_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_xorq_p $qz, $qx, $qy", + [(int_riscv_esp_xorq timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_EQ_S16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.eq.s16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_EQ_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_eq_s16_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_eq_s16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_EQ_S32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.eq.s32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_EQ_S32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_eq_s32_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_eq_s32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_EQ_S8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.eq.s8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_EQ_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_eq_s8_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_eq_s8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_EQ_U16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.eq.u16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_EQ_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_eq_u16_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_eq_u16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_EQ_U32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.eq.u32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_EQ_U32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_eq_u32_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_eq_u32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_EQ_U8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.eq.u8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_EQ_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_eq_u8_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_eq_u8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_GT_S16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.gt.s16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_GT_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_gt_s16_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_gt_s16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_GT_S32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.gt.s32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_GT_S32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_gt_s32_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_gt_s32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_GT_S8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.gt.s8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_GT_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_gt_s8_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_gt_s8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_GT_U16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.gt.u16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_GT_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_gt_u16_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_gt_u16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_GT_U32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.gt.u32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_GT_U32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_gt_u32_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_gt_u32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_GT_U8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.gt.u8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_GT_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_gt_u8_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_gt_u8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_LT_S16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.lt.s16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_LT_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_lt_s16_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_lt_s16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_LT_S32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.lt.s32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_LT_S32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_lt_s32_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_lt_s32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_LT_S8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.lt.s8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_LT_S8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_lt_s8_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_lt_s8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_LT_U16: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.lt.u16\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_LT_U16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_lt_u16_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_lt_u16 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_LT_U32: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.lt.u32\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_LT_U32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_lt_u32_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_lt_u32 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_VCMP_LT_U8: Esp32P4Inst<(outs QR:$qz), (ins QR:$qx, QR:$qy), + "esp.vcmp.lt.u8\t $qz, $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VCMP_LT_U8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qz), + "!esp_vcmp_lt_u8_p $qz, $qx, $qy", + [(int_riscv_esp_vcmp_lt_u8 timm:$qx, timm:$qy, timm:$qz)]>; + +def ESP_MOV_S16_QACC: Esp32P4Inst<(outs), (ins QR:$qu), + "esp.mov.s16.qacc\t $qu", []> +{ + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOV_S16_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qu), + "!esp_mov_s16_qacc_p $qu", + [(int_riscv_esp_mov_s16_qacc timm:$qu)]>; + +def ESP_MOV_S8_QACC: Esp32P4Inst<(outs), (ins QR:$qu), + "esp.mov.s8.qacc\t $qu", []> +{ + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOV_S8_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qu), + "!esp_mov_s8_qacc_p $qu", + [(int_riscv_esp_mov_s8_qacc timm:$qu)]>; + +def ESP_MOV_U16_QACC: Esp32P4Inst<(outs), (ins QR:$qu), + "esp.mov.u16.qacc\t $qu", []> +{ + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOV_U16_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qu), + "!esp_mov_u16_qacc_p $qu", + [(int_riscv_esp_mov_u16_qacc timm:$qu)]>; + +def ESP_MOV_U8_QACC: Esp32P4Inst<(outs), (ins QR:$qu), + "esp.mov.u8.qacc\t $qu", []> +{ + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOV_U8_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qu), + "!esp_mov_u8_qacc_p $qu", + [(int_riscv_esp_mov_u8_qacc timm:$qu)]>; + +def ESP_MOVI_16_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qy, select_16:$sel16), + "esp.movi.16.a\t $qy, $rd, $sel16", []> +{ + bits<3> qy; + bits<4> sel16; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18-15} = sel16{3-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVI_16_A_P : PseudoESP32P4<(outs), (ins imm8:$qy, select_16:$sel16, GPRPIE:$rd), + "!esp_movi_16_a_p $qy, $rd, $sel16", + [(int_riscv_esp_movi_16_a timm:$qy, timm:$sel16, GPRPIE:$rd)]>; + +def ESP_MOVI_16_Q: Esp32P4Inst<(outs QR:$qy), (ins GPRPIE:$rs1, select_16:$sel16), + "esp.movi.16.q\t $qy, $rs1, $sel16", []> +{ + bits<5> rs1; + bits<4> sel16; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10-7} = sel16{3-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVI_16_Q_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, select_16:$sel16, imm8:$qy), + "!esp_movi_16_q_p $qy, $rs1, $sel16", + [(int_riscv_esp_movi_16_q GPRPIE:$rs1, timm:$sel16, timm:$qy)]>; + +def ESP_MOVI_32_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qy, select_4:$sel4), + "esp.movi.32.a\t $qy, $rd, $sel4", []> +{ + bits<3> qy; + bits<2> sel4; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = sel4{1}; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = sel4{0}; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVI_32_A_P : PseudoESP32P4<(outs), (ins imm8:$qy, select_4:$sel4, GPRPIE:$rd), + "!esp_movi_32_a_p $qy, $rd, $sel4", + [(int_riscv_esp_movi_32_a timm:$qy, timm:$sel4, GPRPIE:$rd)]>; + +def ESP_MOVI_32_Q: Esp32P4Inst<(outs QR:$qy), (ins GPRPIE:$rs1, select_4:$sel4), + "esp.movi.32.q\t $qy, $rs1, $sel4", []> +{ + bits<5> rs1; + bits<2> sel4; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10-9} = sel4{1-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVI_32_Q_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, select_4:$sel4, imm8:$qy), + "!esp_movi_32_q_p $qy, $rs1, $sel4", + [(int_riscv_esp_movi_32_q GPRPIE:$rs1, timm:$sel4, timm:$qy)]>; + +def ESP_MOVI_8_A: Esp32P4Inst<(outs GPRPIE:$rd), (ins QR:$qy, select_16:$sel16), + "esp.movi.8.a\t $qy, $rd, $sel16", []> +{ + bits<3> qy; + bits<4> sel16; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18-15} = sel16{3-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVI_8_A_P : PseudoESP32P4<(outs), (ins imm8:$qy, select_16:$sel16, GPRPIE:$rd), + "!esp_movi_8_a_p $qy, $rd, $sel16", + [(int_riscv_esp_movi_8_a timm:$qy, timm:$sel16, GPRPIE:$rd)]>; + +def ESP_MOVI_8_Q: Esp32P4Inst<(outs QR:$qy), (ins GPRPIE:$rs1, select_16:$sel16), + "esp.movi.8.q\t $qy, $rs1, $sel16", []> +{ + bits<5> rs1; + bits<4> sel16; + bits<3> qy; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10-7} = sel16{3-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVI_8_Q_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, select_16:$sel16, imm8:$qy), + "!esp_movi_8_q_p $qy, $rs1, $sel16", + [(int_riscv_esp_movi_8_q GPRPIE:$rs1, timm:$sel16, timm:$qy)]>; + +def ESP_MOVX_R_CFG: Esp32P4Inst<(outs GPRPIE:$rd), (ins), + "esp.movx.r.cfg\t $rd", []> +{ + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_R_CFG_P : PseudoESP32P4<(outs), (ins GPRPIE:$rd), + "!esp_movx_r_cfg_p $rd", + [(int_riscv_esp_movx_r_cfg GPRPIE:$rd)]>; + +def ESP_MOVX_R_FFT_BIT_WIDTH: Esp32P4Inst<(outs GPRPIE:$rd), (ins), + "esp.movx.r.fft.bit.width\t $rd", []> +{ + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_R_FFT_BIT_WIDTH_P : PseudoESP32P4<(outs), (ins GPRPIE:$rd), + "!esp_movx_r_fft_bit_width_p $rd", + [(int_riscv_esp_movx_r_fft_bit_width GPRPIE:$rd)]>; + +def ESP_MOVX_R_PERF: Esp32P4Inst<(outs GPRPIE:$rd), (ins GPRPIE:$rs1), + "esp.movx.r.perf\t $rd, $rs1", []> +{ + bits<5> rs1; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_R_PERF_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rd), + "!esp_movx_r_perf_p $rd, $rs1", + [(int_riscv_esp_movx_r_perf GPRPIE:$rs1, GPRPIE:$rd)]>; + +def ESP_MOVX_R_SAR: Esp32P4Inst<(outs GPRPIE:$rd), (ins), + "esp.movx.r.sar\t $rd", []> +{ + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_R_SAR_P : PseudoESP32P4<(outs), (ins GPRPIE:$rd), + "!esp_movx_r_sar_p $rd", + [(int_riscv_esp_movx_r_sar GPRPIE:$rd)]>; + +def ESP_MOVX_R_SAR_BYTES: Esp32P4Inst<(outs GPRPIE:$rd), (ins), + "esp.movx.r.sar.bytes\t $rd", []> +{ + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_R_SAR_BYTES_P : PseudoESP32P4<(outs), (ins GPRPIE:$rd), + "!esp_movx_r_sar_bytes_p $rd", + [(int_riscv_esp_movx_r_sar_bytes GPRPIE:$rd)]>; + +def ESP_MOVX_R_XACC_H: Esp32P4Inst<(outs GPRPIE:$rd), (ins), + "esp.movx.r.xacc.h\t $rd", []> +{ + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_R_XACC_H_P : PseudoESP32P4<(outs), (ins GPRPIE:$rd), + "!esp_movx_r_xacc_h_p $rd", + [(int_riscv_esp_movx_r_xacc_h GPRPIE:$rd)]>; + +def ESP_MOVX_R_XACC_L: Esp32P4Inst<(outs GPRPIE:$rd), (ins), + "esp.movx.r.xacc.l\t $rd", []> +{ + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_R_XACC_L_P : PseudoESP32P4<(outs), (ins GPRPIE:$rd), + "!esp_movx_r_xacc_l_p $rd", + [(int_riscv_esp_movx_r_xacc_l GPRPIE:$rd)]>; + +def ESP_MOVX_W_CFG: Esp32P4Inst<(outs), (ins GPRPIE:$rs1), + "esp.movx.w.cfg\t $rs1", []> +{ + bits<5> rs1; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_W_CFG_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1), + "!esp_movx_w_cfg_p $rs1", + [(int_riscv_esp_movx_w_cfg GPRPIE:$rs1)]>; + +def ESP_MOVX_W_FFT_BIT_WIDTH: Esp32P4Inst<(outs), (ins GPRPIE:$rs1), + "esp.movx.w.fft.bit.width\t $rs1", []> +{ + bits<5> rs1; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_W_FFT_BIT_WIDTH_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1), + "!esp_movx_w_fft_bit_width_p $rs1", + [(int_riscv_esp_movx_w_fft_bit_width GPRPIE:$rs1)]>; + +def ESP_MOVX_W_PERF: Esp32P4Inst<(outs), (ins GPRPIE:$rs1), + "esp.movx.w.perf\t $rs1", []> +{ + bits<5> rs1; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_W_PERF_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1), + "!esp_movx_w_perf_p $rs1", + [(int_riscv_esp_movx_w_perf GPRPIE:$rs1)]>; + +def ESP_MOVX_W_SAR: Esp32P4Inst<(outs), (ins GPRPIE:$rs1), + "esp.movx.w.sar\t $rs1", []> +{ + bits<5> rs1; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_W_SAR_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1), + "!esp_movx_w_sar_p $rs1", + [(int_riscv_esp_movx_w_sar GPRPIE:$rs1)]>; + +def ESP_MOVX_W_SAR_BYTES: Esp32P4Inst<(outs), (ins GPRPIE:$rs1), + "esp.movx.w.sar.bytes\t $rs1", []> +{ + bits<5> rs1; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_W_SAR_BYTES_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1), + "!esp_movx_w_sar_bytes_p $rs1", + [(int_riscv_esp_movx_w_sar_bytes GPRPIE:$rs1)]>; + +def ESP_MOVX_W_XACC_H: Esp32P4Inst<(outs), (ins GPRPIE:$rs1), + "esp.movx.w.xacc.h\t $rs1", []> +{ + bits<5> rs1; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_W_XACC_H_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1), + "!esp_movx_w_xacc_h_p $rs1", + [(int_riscv_esp_movx_w_xacc_h GPRPIE:$rs1)]>; + +def ESP_MOVX_W_XACC_L: Esp32P4Inst<(outs), (ins GPRPIE:$rs1), + "esp.movx.w.xacc.l\t $rs1", []> +{ + bits<5> rs1; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_MOVX_W_XACC_L_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1), + "!esp_movx_w_xacc_l_p $rs1", + [(int_riscv_esp_movx_w_xacc_l GPRPIE:$rs1)]>; + +def ESP_VEXT_S16: Esp32P4Inst<(outs QR:$qz, QR:$qv), (ins QR:$qw), + "esp.vext.s16\t $qz, $qv, $qw", []> +{ + bits<3> qw; + bits<3> qz; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VEXT_S16_P : PseudoESP32P4<(outs), (ins imm8:$qw, imm8:$qz, imm8:$qv), + "!esp_vext_s16_p $qz, $qv, $qw", + [(int_riscv_esp_vext_s16 timm:$qw, timm:$qz, timm:$qv)]>; + +def ESP_VEXT_S8: Esp32P4Inst<(outs QR:$qz, QR:$qv), (ins QR:$qw), + "esp.vext.s8\t $qz, $qv, $qw", []> +{ + bits<3> qw; + bits<3> qz; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VEXT_S8_P : PseudoESP32P4<(outs), (ins imm8:$qw, imm8:$qz, imm8:$qv), + "!esp_vext_s8_p $qz, $qv, $qw", + [(int_riscv_esp_vext_s8 timm:$qw, timm:$qz, timm:$qv)]>; + +def ESP_VEXT_U16: Esp32P4Inst<(outs QR:$qz, QR:$qv), (ins QR:$qw), + "esp.vext.u16\t $qz, $qv, $qw", []> +{ + bits<3> qw; + bits<3> qz; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VEXT_U16_P : PseudoESP32P4<(outs), (ins imm8:$qw, imm8:$qz, imm8:$qv), + "!esp_vext_u16_p $qz, $qv, $qw", + [(int_riscv_esp_vext_u16 timm:$qw, timm:$qz, timm:$qv)]>; + +def ESP_VEXT_U8: Esp32P4Inst<(outs QR:$qz, QR:$qv), (ins QR:$qw), + "esp.vext.u8\t $qz, $qv, $qw", []> +{ + bits<3> qw; + bits<3> qz; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VEXT_U8_P : PseudoESP32P4<(outs), (ins imm8:$qw, imm8:$qz, imm8:$qv), + "!esp_vext_u8_p $qz, $qv, $qw", + [(int_riscv_esp_vext_u8 timm:$qw, timm:$qz, timm:$qv)]>; + +def ESP_VUNZIP_16: Esp32P4Inst<(outs QR:$qxr, QR:$qyr), (ins QR:$qx, QR:$qy), + "esp.vunzip.16\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qxr; + bits<3> qyr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VUNZIP_16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vunzip_16_p $qx, $qy", + [(int_riscv_esp_vunzip_16 timm:$qx, timm:$qy)]>; + +def ESP_VUNZIP_32: Esp32P4Inst<(outs QR:$qxr, QR:$qyr), (ins QR:$qx, QR:$qy), + "esp.vunzip.32\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qxr; + bits<3> qyr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VUNZIP_32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vunzip_32_p $qx, $qy", + [(int_riscv_esp_vunzip_32 timm:$qx, timm:$qy)]>; + +def ESP_VUNZIP_8: Esp32P4Inst<(outs QR:$qxr, QR:$qyr), (ins QR:$qx, QR:$qy), + "esp.vunzip.8\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qxr; + bits<3> qyr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VUNZIP_8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vunzip_8_p $qx, $qy", + [(int_riscv_esp_vunzip_8 timm:$qx, timm:$qy)]>; + +def ESP_VUNZIPT_16: Esp32P4Inst<(outs QR:$qxr, QR:$qyr, QR:$qwr), (ins QR:$qx, QR:$qy, QR:$qw), + "esp.vunzipt.16\t $qx, $qy, $qw", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qw; + bits<3> qxr; + bits<3> qyr; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy, $qwr = $qw"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VUNZIPT_16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qw), + "!esp_vunzipt_16_p $qx, $qy, $qw", + [(int_riscv_esp_vunzipt_16 timm:$qx, timm:$qy, timm:$qw)]>; + +def ESP_VUNZIPT_8: Esp32P4Inst<(outs QR:$qxr, QR:$qyr, QR:$qwr), (ins QR:$qx, QR:$qy, QR:$qw), + "esp.vunzipt.8\t $qx, $qy, $qw", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qw; + bits<3> qxr; + bits<3> qyr; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy, $qwr = $qw"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VUNZIPT_8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qw), + "!esp_vunzipt_8_p $qx, $qy, $qw", + [(int_riscv_esp_vunzipt_8 timm:$qx, timm:$qy, timm:$qw)]>; + +def ESP_VZIP_16: Esp32P4Inst<(outs QR:$qxr, QR:$qyr), (ins QR:$qx, QR:$qy), + "esp.vzip.16\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qxr; + bits<3> qyr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 1; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VZIP_16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vzip_16_p $qx, $qy", + [(int_riscv_esp_vzip_16 timm:$qx, timm:$qy)]>; + +def ESP_VZIP_32: Esp32P4Inst<(outs QR:$qxr, QR:$qyr), (ins QR:$qx, QR:$qy), + "esp.vzip.32\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qxr; + bits<3> qyr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 1; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VZIP_32_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vzip_32_p $qx, $qy", + [(int_riscv_esp_vzip_32 timm:$qx, timm:$qy)]>; + +def ESP_VZIP_8: Esp32P4Inst<(outs QR:$qxr, QR:$qyr), (ins QR:$qx, QR:$qy), + "esp.vzip.8\t $qx, $qy", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qxr; + bits<3> qyr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VZIP_8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy), + "!esp_vzip_8_p $qx, $qy", + [(int_riscv_esp_vzip_8 timm:$qx, timm:$qy)]>; + +def ESP_VZIPT_16: Esp32P4Inst<(outs QR:$qxr, QR:$qyr, QR:$qwr), (ins QR:$qx, QR:$qy, QR:$qw), + "esp.vzipt.16\t $qx, $qy, $qw", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qw; + bits<3> qxr; + bits<3> qyr; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy, $qwr = $qw"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VZIPT_16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qw), + "!esp_vzipt_16_p $qx, $qy, $qw", + [(int_riscv_esp_vzipt_16 timm:$qx, timm:$qy, timm:$qw)]>; + +def ESP_VZIPT_8: Esp32P4Inst<(outs QR:$qxr, QR:$qyr, QR:$qwr), (ins QR:$qx, QR:$qy, QR:$qw), + "esp.vzipt.8\t $qx, $qy, $qw", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qw; + bits<3> qxr; + bits<3> qyr; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qxr = $qx, $qyr = $qy, $qwr = $qw"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VZIPT_8_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qw), + "!esp_vzipt_8_p $qx, $qy, $qw", + [(int_riscv_esp_vzipt_8 timm:$qx, timm:$qy, timm:$qw)]>; + +def ESP_ZERO_Q: Esp32P4Inst<(outs QR:$qz), (ins), + "esp.zero.q\t $qz", []> +{ + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ZERO_Q_P : PseudoESP32P4<(outs), (ins imm8:$qz), + "!esp_zero_q_p $qz", + [(int_riscv_esp_zero_q timm:$qz)]>; + +def ESP_ZERO_QACC: Esp32P4Inst<(outs), (ins), + "esp.zero.qacc\t", []> +{ + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ZERO_QACC_P : PseudoESP32P4<(outs), (ins), + "!esp_zero_qacc_p", + [(int_riscv_esp_zero_qacc)]>; + +def ESP_ZERO_XACC: Esp32P4Inst<(outs), (ins), + "esp.zero.xacc\t", []> +{ + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ZERO_XACC_P : PseudoESP32P4<(outs), (ins), + "!esp_zero_xacc_p", + [(int_riscv_esp_zero_xacc)]>; + +def ESP_FFT_AMS_S16_LD_INCP: Esp32P4Inst<(outs QR:$qu, QR:$qz, QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qw, GPRPIE:$rs1, select_2:$sel2), + "esp.fft.ams.s16.ld.incp\t $qu, $rs1, $qz, $qv, $qx, $qw, $qy, $sel2", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qw; + bits<5> rs1; + bits<1> sel2; + bits<3> qu; + bits<3> qz; + bits<3> qv; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = sel2{0}; + let Inst{22-20} = qv{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_AMS_S16_LD_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qw, GPRPIE:$rs1, select_2:$sel2, imm8:$qu, imm8:$qz, imm8:$qv), + "!esp_fft_ams_s16_ld_incp_p $qu, $rs1, $qz, $qv, $qx, $qw, $qy, $sel2", + [(int_riscv_esp_fft_ams_s16_ld_incp timm:$qx, timm:$qy, timm:$qw, GPRPIE:$rs1, timm:$sel2, timm:$qu, timm:$qz, timm:$qv)]>; + +def ESP_FFT_AMS_S16_LD_INCP_UAUP: Esp32P4Inst<(outs QR:$qu, QR:$qz, QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qw, GPRPIE:$rs1, select_2:$sel2), + "esp.fft.ams.s16.ld.incp.uaup\t $qu, $rs1, $qz, $qv, $qx, $qw, $qy, $sel2", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qw; + bits<5> rs1; + bits<1> sel2; + bits<3> qu; + bits<3> qz; + bits<3> qv; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = sel2{0}; + let Inst{22-20} = qv{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_AMS_S16_LD_INCP_UAUP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qw, GPRPIE:$rs1, select_2:$sel2, imm8:$qu, imm8:$qz, imm8:$qv), + "!esp_fft_ams_s16_ld_incp_uaup_p $qu, $rs1, $qz, $qv, $qx, $qw, $qy, $sel2", + [(int_riscv_esp_fft_ams_s16_ld_incp_uaup timm:$qx, timm:$qy, timm:$qw, GPRPIE:$rs1, timm:$sel2, timm:$qu, timm:$qz, timm:$qv)]>; + +def ESP_FFT_AMS_S16_LD_R32_DECP: Esp32P4Inst<(outs QR:$qu, QR:$qz, QR:$qv, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, QR:$qw, GPRPIE:$rs1, select_2:$sel2), + "esp.fft.ams.s16.ld.r32.decp\t $qu, $rs1, $qz, $qv, $qx, $qw, $qy, $sel2", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qw; + bits<5> rs1; + bits<1> sel2; + bits<3> qu; + bits<3> qz; + bits<3> qv; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = sel2{0}; + let Inst{22-20} = qv{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_AMS_S16_LD_R32_DECP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qw, GPRPIE:$rs1, select_2:$sel2, imm8:$qu, imm8:$qz, imm8:$qv), + "!esp_fft_ams_s16_ld_r32_decp_p $qu, $rs1, $qz, $qv, $qx, $qw, $qy, $sel2", + [(int_riscv_esp_fft_ams_s16_ld_r32_decp timm:$qx, timm:$qy, timm:$qw, GPRPIE:$rs1, timm:$sel2, timm:$qu, timm:$qz, timm:$qv)]>; + +def ESP_FFT_AMS_S16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r, GPRPIE:$rs2r), (ins QR:$qx, QR:$qy, QR:$qw, QR:$qu, GPRPIE:$rs1, GPRPIE:$rs2, select_2:$sel2), + "esp.fft.ams.s16.st.incp\t $qu, $qz, $rs2, $rs1, $qx, $qw, $qy, $sel2", []> +{ + bits<3> qx; + bits<3> qy; + bits<3> qw; + bits<3> qu; + bits<5> rs1; + bits<5> rs2; + bits<1> sel2; + bits<3> qz; + bits<5> rs1r; + bits<5> rs2r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1, $rs2r = $rs2"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = sel2{0}; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_AMS_S16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, imm8:$qw, imm8:$qu, GPRPIE:$rs1, GPRPIE:$rs2, select_2:$sel2, imm8:$qz), + "!esp_fft_ams_s16_st_incp_p $qu, $qz, $rs2, $rs1, $qx, $qw, $qy, $sel2", + [(int_riscv_esp_fft_ams_s16_st_incp timm:$qx, timm:$qy, timm:$qw, timm:$qu, GPRPIE:$rs1, GPRPIE:$rs2, timm:$sel2, timm:$qz)]>; + +def ESP_FFT_BITREV: Esp32P4Inst<(outs GPRPIE:$rs1r, QR:$qvr), (ins GPRPIE:$rs1, QR:$qv), + "esp.fft.bitrev\t $qv, $rs1", []> +{ + bits<5> rs1; + bits<3> qv; + bits<5> rs1r; + bits<3> qvr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1, $qvr = $qv"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_BITREV_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qv), + "!esp_fft_bitrev_p $qv, $rs1", + [(int_riscv_esp_fft_bitrev GPRPIE:$rs1, timm:$qv)]>; + +def ESP_FFT_CMUL_S16_LD_XP: Esp32P4Inst<(outs QR:$qz, QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, GPRPIE:$rs1, select_8:$sel8), + "esp.fft.cmul.s16.ld.xp\t $qu, $rs1, $rs2, $qz, $qy, $qx, $sel8", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<3> sel8; + bits<3> qz; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = sel8{2-1}; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = sel8{0}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_CMUL_S16_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_8:$sel8, imm8:$qz, imm8:$qu), + "!esp_fft_cmul_s16_ld_xp_p $qu, $rs1, $rs2, $qz, $qy, $qx, $sel8", + [(int_riscv_esp_fft_cmul_s16_ld_xp GPRPIE:$rs2, timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel8, timm:$qz, timm:$qu)]>; + +def ESP_FFT_CMUL_S16_ST_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qx, QR:$qy, QR:$qu, GPRPIE:$rs1, select_4:$sel4, select_4:$upd4, select_8:$sel8), + "esp.fft.cmul.s16.st.xp\t $qy, $qx, $qu, $rs1, $rs2, $sel8, $upd4, $sel4", []> +{ + bits<5> rs2; + bits<3> qx; + bits<3> qy; + bits<3> qu; + bits<5> rs1; + bits<2> sel4; + bits<2> upd4; + bits<3> sel8; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = sel4{1-0}; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = upd4{1}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = upd4{0}; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = sel8{2-0}; + let Inst{6} = 1; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_CMUL_S16_ST_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qx, imm8:$qy, imm8:$qu, GPRPIE:$rs1, select_4:$sel4, select_4:$upd4, select_8:$sel8), + "!esp_fft_cmul_s16_st_xp_p $qy, $qx, $qu, $rs1, $rs2, $sel8, $upd4, $sel4", + [(int_riscv_esp_fft_cmul_s16_st_xp GPRPIE:$rs2, timm:$qx, timm:$qy, timm:$qu, GPRPIE:$rs1, timm:$sel4, timm:$upd4, timm:$sel8)]>; + +def ESP_FFT_R2BF_S16: Esp32P4Inst<(outs QR:$qz, QR:$qv), (ins QR:$qx, QR:$qy, select_2:$sel2), + "esp.fft.r2bf.s16\t $qz, $qv, $qx, $qy, $sel2", []> +{ + bits<3> qx; + bits<3> qy; + bits<1> sel2; + bits<3> qz; + bits<3> qv; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22-20} = qv{2-0}; + let Inst{19} = 0; + let Inst{18} = sel2{0}; + let Inst{17} = 0; + let Inst{16} = 1; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_R2BF_S16_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, select_2:$sel2, imm8:$qz, imm8:$qv), + "!esp_fft_r2bf_s16_p $qz, $qv, $qx, $qy, $sel2", + [(int_riscv_esp_fft_r2bf_s16 timm:$qx, timm:$qy, timm:$sel2, timm:$qz, timm:$qv)]>; + +def ESP_FFT_R2BF_S16_ST_INCP: Esp32P4Inst<(outs QR:$qz, GPRPIE:$rs1r), (ins QR:$qx, QR:$qy, GPRPIE:$rs1, select_4:$sel4), + "esp.fft.r2bf.s16.st.incp\t $qz, $qx, $qy, $rs1, $sel4", []> +{ + bits<3> qx; + bits<3> qy; + bits<5> rs1; + bits<2> sel4; + bits<3> qz; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = qx{2-0}; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23-22} = sel4{1-0}; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_R2BF_S16_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qx, imm8:$qy, GPRPIE:$rs1, select_4:$sel4, imm8:$qz), + "!esp_fft_r2bf_s16_st_incp_p $qz, $qx, $qy, $rs1, $sel4", + [(int_riscv_esp_fft_r2bf_s16_st_incp timm:$qx, timm:$qy, GPRPIE:$rs1, timm:$sel4, timm:$qz)]>; + +def ESP_FFT_VST_R32_DECP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qu, GPRPIE:$rs1, select_2:$sel2), + "esp.fft.vst.r32.decp\t $qu, $rs1, $sel2", []> +{ + bits<3> qu; + bits<5> rs1; + bits<1> sel2; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = sel2{0}; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_FFT_VST_R32_DECP_P : PseudoESP32P4<(outs), (ins imm8:$qu, GPRPIE:$rs1, select_2:$sel2), + "!esp_fft_vst_r32_decp_p $qu, $rs1, $sel2", + [(int_riscv_esp_fft_vst_r32_decp timm:$qu, GPRPIE:$rs1, timm:$sel2)]>; + +def ESP_LD_128_USAR_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ld.128.usar.ip\t $qu, $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = off25616{7-5}; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off25616{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LD_128_USAR_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616, imm8:$qu), + "!esp_ld_128_usar_ip_p $qu, $rs1, $off25616", + [(int_riscv_esp_ld_128_usar_ip GPRPIE:$rs1, timm:$off25616, timm:$qu)]>; + +def ESP_LD_128_USAR_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.ld.128.usar.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LD_128_USAR_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu), + "!esp_ld_128_usar_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_ld_128_usar_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_LD_XACC_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_8:$off2568), + "esp.ld.xacc.ip\t $rs1, $off2568", []> +{ + bits<5> rs1; + bits<8> off2568; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = off2568{7}; + let Inst{30} = 0; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off2568{6-3}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = off2568{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LD_XACC_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_8:$off2568), + "!esp_ld_xacc_ip_p $rs1, $off2568", + [(int_riscv_esp_ld_xacc_ip GPRPIE:$rs1, timm:$off2568)]>; + +def ESP_LDQA_S16_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ldqa.s16.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 1; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDQA_S16_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ldqa_s16_128_ip_p $rs1, $off25616", + [(int_riscv_esp_ldqa_s16_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LDQA_S16_128_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.ldqa.s16.128.xp\t $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDQA_S16_128_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "!esp_ldqa_s16_128_xp_p $rs1, $rs2", + [(int_riscv_esp_ldqa_s16_128_xp GPRPIE:$rs2, GPRPIE:$rs1)]>; + +def ESP_LDQA_S8_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ldqa.s8.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDQA_S8_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ldqa_s8_128_ip_p $rs1, $off25616", + [(int_riscv_esp_ldqa_s8_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LDQA_S8_128_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.ldqa.s8.128.xp\t $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDQA_S8_128_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "!esp_ldqa_s8_128_xp_p $rs1, $rs2", + [(int_riscv_esp_ldqa_s8_128_xp GPRPIE:$rs2, GPRPIE:$rs1)]>; + +def ESP_LDQA_U16_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ldqa.u16.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDQA_U16_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ldqa_u16_128_ip_p $rs1, $off25616", + [(int_riscv_esp_ldqa_u16_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LDQA_U16_128_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.ldqa.u16.128.xp\t $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 1; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDQA_U16_128_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "!esp_ldqa_u16_128_xp_p $rs1, $rs2", + [(int_riscv_esp_ldqa_u16_128_xp GPRPIE:$rs2, GPRPIE:$rs1)]>; + +def ESP_LDQA_U8_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ldqa.u8.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDQA_U8_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ldqa_u8_128_ip_p $rs1, $off25616", + [(int_riscv_esp_ldqa_u8_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LDQA_U8_128_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.ldqa.u8.128.xp\t $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 1; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDQA_U8_128_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "!esp_ldqa_u8_128_xp_p $rs1, $rs2", + [(int_riscv_esp_ldqa_u8_128_xp GPRPIE:$rs2, GPRPIE:$rs1)]>; + +def ESP_VLDBC_16_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564), + "esp.vldbc.16.ip\t $qu, $rs1, $off2564", []> +{ + bits<5> rs1; + bits<8> off2564; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30-28} = off2564{7-5}; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23-20} = off2564{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off2564{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDBC_16_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_4:$off2564, imm8:$qu), + "!esp_vldbc_16_ip_p $qu, $rs1, $off2564", + [(int_riscv_esp_vldbc_16_ip GPRPIE:$rs1, timm:$off2564, timm:$qu)]>; + +def ESP_VLDBC_16_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vldbc.16.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDBC_16_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu), + "!esp_vldbc_16_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vldbc_16_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VLDBC_32_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564), + "esp.vldbc.32.ip\t $qu, $rs1, $off2564", []> +{ + bits<5> rs1; + bits<8> off2564; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31-29} = off2564{7-5}; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23-20} = off2564{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off2564{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDBC_32_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_4:$off2564, imm8:$qu), + "!esp_vldbc_32_ip_p $qu, $rs1, $off2564", + [(int_riscv_esp_vldbc_32_ip GPRPIE:$rs1, timm:$off2564, timm:$qu)]>; + +def ESP_VLDBC_32_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vldbc.32.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDBC_32_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu), + "!esp_vldbc_32_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vldbc_32_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VLDBC_8_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564), + "esp.vldbc.8.ip\t $qu, $rs1, $off2564", []> +{ + bits<5> rs1; + bits<8> off2564; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30-28} = off2564{7-5}; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23-20} = off2564{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off2564{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDBC_8_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_4:$off2564, imm8:$qu), + "!esp_vldbc_8_ip_p $qu, $rs1, $off2564", + [(int_riscv_esp_vldbc_8_ip GPRPIE:$rs1, timm:$off2564, timm:$qu)]>; + +def ESP_VLDBC_8_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vldbc.8.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDBC_8_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu), + "!esp_vldbc_8_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vldbc_8_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VLDEXT_S16_IP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vldext.s16.ip\t $qu, $qz, $rs1, $off1616", []> +{ + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 1; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off1616{3-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDEXT_S16_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu, imm8:$qz), + "!esp_vldext_s16_ip_p $qu, $qz, $rs1, $off1616", + [(int_riscv_esp_vldext_s16_ip GPRPIE:$rs1, timm:$off1616, timm:$qu, timm:$qz)]>; + +def ESP_VLDEXT_S16_XP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vldext.s16.xp\t $qu, $qz, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 1; + let Inst{29} = 1; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDEXT_S16_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu, imm8:$qz), + "!esp_vldext_s16_xp_p $qu, $qz, $rs1, $rs2", + [(int_riscv_esp_vldext_s16_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu, timm:$qz)]>; + +def ESP_VLDEXT_S8_IP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vldext.s8.ip\t $qu, $qz, $rs1, $off1616", []> +{ + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off1616{3-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDEXT_S8_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu, imm8:$qz), + "!esp_vldext_s8_ip_p $qu, $qz, $rs1, $off1616", + [(int_riscv_esp_vldext_s8_ip GPRPIE:$rs1, timm:$off1616, timm:$qu, timm:$qz)]>; + +def ESP_VLDEXT_S8_XP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vldext.s8.xp\t $qu, $qz, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = 1; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDEXT_S8_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu, imm8:$qz), + "!esp_vldext_s8_xp_p $qu, $qz, $rs1, $rs2", + [(int_riscv_esp_vldext_s8_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu, timm:$qz)]>; + +def ESP_VLDEXT_U16_IP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vldext.u16.ip\t $qu, $qz, $rs1, $off1616", []> +{ + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off1616{3-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDEXT_U16_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu, imm8:$qz), + "!esp_vldext_u16_ip_p $qu, $qz, $rs1, $off1616", + [(int_riscv_esp_vldext_u16_ip GPRPIE:$rs1, timm:$off1616, timm:$qu, timm:$qz)]>; + +def ESP_VLDEXT_U16_XP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vldext.u16.xp\t $qu, $qz, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 1; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDEXT_U16_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu, imm8:$qz), + "!esp_vldext_u16_xp_p $qu, $qz, $rs1, $rs2", + [(int_riscv_esp_vldext_u16_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu, timm:$qz)]>; + +def ESP_VLDEXT_U8_IP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_16_16:$off1616), + "esp.vldext.u8.ip\t $qu, $qz, $rs1, $off1616", []> +{ + bits<5> rs1; + bits<4> off1616; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off1616{3-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDEXT_U8_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_16_16:$off1616, imm8:$qu, imm8:$qz), + "!esp_vldext_u8_ip_p $qu, $qz, $rs1, $off1616", + [(int_riscv_esp_vldext_u8_ip GPRPIE:$rs1, timm:$off1616, timm:$qu, timm:$qz)]>; + +def ESP_VLDEXT_U8_XP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vldext.u8.xp\t $qu, $qz, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 1; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDEXT_U8_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu, imm8:$qz), + "!esp_vldext_u8_xp_p $qu, $qz, $rs1, $rs2", + [(int_riscv_esp_vldext_u8_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu, timm:$qz)]>; + +def ESP_VLDHBC_16_INCP: Esp32P4Inst<(outs QR:$qu, QR:$qz, GPRPIE:$rs1r), (ins GPRPIE:$rs1), + "esp.vldhbc.16.incp\t $qu, $qz, $rs1", []> +{ + bits<5> rs1; + bits<3> qu; + bits<3> qz; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLDHBC_16_INCP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qu, imm8:$qz), + "!esp_vldhbc_16_incp_p $qu, $qz, $rs1", + [(int_riscv_esp_vldhbc_16_incp GPRPIE:$rs1, timm:$qu, timm:$qz)]>; + +def ESP_LD_QACC_H_H_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ld.qacc.h.h.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LD_QACC_H_H_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ld_qacc_h_h_128_ip_p $rs1, $off25616", + [(int_riscv_esp_ld_qacc_h_h_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LD_QACC_H_L_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ld.qacc.h.l.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LD_QACC_H_L_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ld_qacc_h_l_128_ip_p $rs1, $off25616", + [(int_riscv_esp_ld_qacc_h_l_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LD_QACC_L_H_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ld.qacc.l.h.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LD_QACC_L_H_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ld_qacc_l_h_128_ip_p $rs1, $off25616", + [(int_riscv_esp_ld_qacc_l_h_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LD_QACC_L_L_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ld.qacc.l.l.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LD_QACC_L_L_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ld_qacc_l_l_128_ip_p $rs1, $off25616", + [(int_riscv_esp_ld_qacc_l_l_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LD_UA_STATE_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.ld.ua.state.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = off25616{7}; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{6-3}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = off25616{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LD_UA_STATE_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_ld_ua_state_ip_p $rs1, $off25616", + [(int_riscv_esp_ld_ua_state_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_LDXQ_32: Esp32P4Inst<(outs QR:$qu), (ins GPRPIE:$rs1, QR:$qw, select_4:$sel4, select_8:$sel8), + "esp.ldxq.32\t $qu, $qw, $rs1, $sel4, $sel8", []> +{ + bits<5> rs1; + bits<3> qw; + bits<2> sel4; + bits<3> sel8; + bits<3> qu; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30-29} = sel4{1-0}; + let Inst{28-26} = sel8{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_LDXQ_32_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qw, select_4:$sel4, select_8:$sel8, imm8:$qu), + "!esp_ldxq_32_p $qu, $qw, $rs1, $sel4, $sel8", + [(int_riscv_esp_ldxq_32 GPRPIE:$rs1, timm:$qw, timm:$sel4, timm:$sel8, timm:$qu)]>; + +def ESP_ST_QACC_H_H_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.st.qacc.h.h.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 1; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ST_QACC_H_H_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_st_qacc_h_h_128_ip_p $rs1, $off25616", + [(int_riscv_esp_st_qacc_h_h_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_ST_QACC_H_L_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.st.qacc.h.l.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 1; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ST_QACC_H_L_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_st_qacc_h_l_128_ip_p $rs1, $off25616", + [(int_riscv_esp_st_qacc_h_l_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_ST_QACC_L_H_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.st.qacc.l.h.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ST_QACC_L_H_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_st_qacc_l_h_128_ip_p $rs1, $off25616", + [(int_riscv_esp_st_qacc_l_h_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_ST_QACC_L_L_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.st.qacc.l.l.128.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{7-4}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-9} = off25616{3-0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ST_QACC_L_L_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_st_qacc_l_l_128_ip_p $rs1, $off25616", + [(int_riscv_esp_st_qacc_l_l_128_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_ST_UA_STATE_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.st.ua.state.ip\t $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = off25616{7}; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off25616{6-3}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = off25616{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ST_UA_STATE_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_st_ua_state_ip_p $rs1, $off25616", + [(int_riscv_esp_st_ua_state_ip GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_STXQ_32: Esp32P4Inst<(outs), (ins GPRPIE:$rs1, QR:$qw, QR:$qu, select_4:$sel4, select_8:$sel8), + "esp.stxq.32\t $qu, $qw, $rs1, $sel4, $sel8", []> +{ + bits<5> rs1; + bits<3> qw; + bits<3> qu; + bits<2> sel4; + bits<3> sel8; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30-29} = sel4{1-0}; + let Inst{28-26} = sel8{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_STXQ_32_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, imm8:$qw, imm8:$qu, select_4:$sel4, select_8:$sel8), + "!esp_stxq_32_p $qu, $qw, $rs1, $sel4, $sel8", + [(int_riscv_esp_stxq_32 GPRPIE:$rs1, timm:$qw, timm:$qu, timm:$sel4, timm:$sel8)]>; + +def ESP_VLD_128_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_16:$off25616), + "esp.vld.128.ip\t $qu, $rs1, $off25616", []> +{ + bits<5> rs1; + bits<8> off25616; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30-28} = off25616{7-5}; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23-20} = off25616{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off25616{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLD_128_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_16:$off25616, imm8:$qu), + "!esp_vld_128_ip_p $qu, $rs1, $off25616", + [(int_riscv_esp_vld_128_ip GPRPIE:$rs1, timm:$off25616, timm:$qu)]>; + +def ESP_VLD_128_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vld.128.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLD_128_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu), + "!esp_vld_128_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vld_128_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VLD_H_64_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_8:$off2568), + "esp.vld.h.64.ip\t $qu, $rs1, $off2568", []> +{ + bits<5> rs1; + bits<8> off2568; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29-27} = off2568{7-5}; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off2568{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off2568{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLD_H_64_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_8:$off2568, imm8:$qu), + "!esp_vld_h_64_ip_p $qu, $rs1, $off2568", + [(int_riscv_esp_vld_h_64_ip GPRPIE:$rs1, timm:$off2568, timm:$qu)]>; + +def ESP_VLD_H_64_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vld.h.64.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLD_H_64_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu), + "!esp_vld_h_64_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vld_h_64_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VLD_L_64_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_8:$off2568), + "esp.vld.l.64.ip\t $qu, $rs1, $off2568", []> +{ + bits<5> rs1; + bits<8> off2568; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29-27} = off2568{7-5}; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off2568{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off2568{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLD_L_64_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_8:$off2568, imm8:$qu), + "!esp_vld_l_64_ip_p $qu, $rs1, $off2568", + [(int_riscv_esp_vld_l_64_ip GPRPIE:$rs1, timm:$off2568, timm:$qu)]>; + +def ESP_VLD_L_64_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPRPIE:$rs1), + "esp.vld.l.64.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<5> rs1; + bits<3> qu; + bits<5> rs1r; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VLD_L_64_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, GPRPIE:$rs1, imm8:$qu), + "!esp_vld_l_64_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vld_l_64_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu)]>; + +def ESP_VST_128_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qu, GPRPIE:$rs1, offset_256_16:$off25616), + "esp.vst.128.ip\t $qu, $rs1, $off25616", []> +{ + bits<3> qu; + bits<5> rs1; + bits<8> off25616; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30-28} = off25616{7-5}; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23-20} = off25616{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off25616{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VST_128_IP_P : PseudoESP32P4<(outs), (ins imm8:$qu, GPRPIE:$rs1, offset_256_16:$off25616), + "!esp_vst_128_ip_p $qu, $rs1, $off25616", + [(int_riscv_esp_vst_128_ip timm:$qu, GPRPIE:$rs1, timm:$off25616)]>; + +def ESP_VST_128_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qu, GPRPIE:$rs1), + "esp.vst.128.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 1; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VST_128_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qu, GPRPIE:$rs1), + "!esp_vst_128_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vst_128_xp GPRPIE:$rs2, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VST_H_64_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qu, GPRPIE:$rs1, offset_256_8:$off2568), + "esp.vst.h.64.ip\t $qu, $rs1, $off2568", []> +{ + bits<3> qu; + bits<5> rs1; + bits<8> off2568; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 1; + let Inst{29-27} = off2568{7-5}; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off2568{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off2568{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VST_H_64_IP_P : PseudoESP32P4<(outs), (ins imm8:$qu, GPRPIE:$rs1, offset_256_8:$off2568), + "!esp_vst_h_64_ip_p $qu, $rs1, $off2568", + [(int_riscv_esp_vst_h_64_ip timm:$qu, GPRPIE:$rs1, timm:$off2568)]>; + +def ESP_VST_H_64_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qu, GPRPIE:$rs1), + "esp.vst.h.64.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VST_H_64_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qu, GPRPIE:$rs1), + "!esp_vst_h_64_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vst_h_64_xp GPRPIE:$rs2, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_VST_L_64_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qu, GPRPIE:$rs1, offset_256_8:$off2568), + "esp.vst.l.64.ip\t $qu, $rs1, $off2568", []> +{ + bits<3> qu; + bits<5> rs1; + bits<8> off2568; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29-27} = off2568{7-5}; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off2568{4-1}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off2568{0}; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VST_L_64_IP_P : PseudoESP32P4<(outs), (ins imm8:$qu, GPRPIE:$rs1, offset_256_8:$off2568), + "!esp_vst_l_64_ip_p $qu, $rs1, $off2568", + [(int_riscv_esp_vst_l_64_ip timm:$qu, GPRPIE:$rs1, timm:$off2568)]>; + +def ESP_VST_L_64_XP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, QR:$qu, GPRPIE:$rs1), + "esp.vst.l.64.xp\t $qu, $rs1, $rs2", []> +{ + bits<5> rs2; + bits<3> qu; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VST_L_64_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qu, GPRPIE:$rs1), + "!esp_vst_l_64_xp_p $qu, $rs1, $rs2", + [(int_riscv_esp_vst_l_64_xp GPRPIE:$rs2, timm:$qu, GPRPIE:$rs1)]>; + +def ESP_SLCI_2Q: Esp32P4Inst<(outs QR:$qyr, QR:$qwr), (ins QR:$qy, QR:$qw, select_16:$sel16), + "esp.slci.2q\t $qy, $qw, $sel16", []> +{ + bits<3> qy; + bits<3> qw; + bits<4> sel16; + bits<3> qyr; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qyr = $qy, $qwr = $qw"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = sel16{3}; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9-7} = sel16{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SLCI_2Q_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, select_16:$sel16), + "!esp_slci_2q_p $qy, $qw, $sel16", + [(int_riscv_esp_slci_2q timm:$qy, timm:$qw, timm:$sel16)]>; + +def ESP_SLCXXP_2Q: Esp32P4Inst<(outs QR:$qyr, QR:$qwr), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qy, QR:$qw), + "esp.slcxxp.2q\t $qy, $qw, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qy; + bits<3> qw; + bits<3> qyr; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qyr = $qy, $qwr = $qw"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SLCXXP_2Q_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qy, imm8:$qw), + "!esp_slcxxp_2q_p $qy, $qw, $rs1, $rs2", + [(int_riscv_esp_slcxxp_2q GPRPIE:$rs1, GPRPIE:$rs2, timm:$qy, timm:$qw)]>; + +def ESP_SRC_Q: Esp32P4Inst<(outs QR:$qz), (ins QR:$qy, QR:$qw), + "esp.src.q\t $qz, $qw, $qy", []> +{ + bits<3> qy; + bits<3> qw; + bits<3> qz; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRC_Q_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, imm8:$qz), + "!esp_src_q_p $qz, $qw, $qy", + [(int_riscv_esp_src_q timm:$qy, timm:$qw, timm:$qz)]>; + +def ESP_SRC_Q_LD_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r, QR:$qwr), (ins QR:$qy, GPRPIE:$rs1, QR:$qw, offset_256_16:$off25616), + "esp.src.q.ld.ip\t $qu, $rs1, $off25616, $qw, $qy", []> +{ + bits<3> qy; + bits<5> rs1; + bits<3> qw; + bits<8> off25616; + bits<3> qu; + bits<5> rs1r; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1, $qwr = $qw"; + + let Inst{31-29} = off25616{7-5}; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23-20} = off25616{4-1}; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = off25616{0}; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRC_Q_LD_IP_P : PseudoESP32P4<(outs), (ins imm8:$qy, GPRPIE:$rs1, imm8:$qw, offset_256_16:$off25616, imm8:$qu), + "!esp_src_q_ld_ip_p $qu, $rs1, $off25616, $qw, $qy", + [(int_riscv_esp_src_q_ld_ip timm:$qy, GPRPIE:$rs1, timm:$qw, timm:$off25616, timm:$qu)]>; + +def ESP_SRC_Q_LD_XP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r, QR:$qwr), (ins GPRPIE:$rs2, QR:$qy, GPRPIE:$rs1, QR:$qw), + "esp.src.q.ld.xp\t $qu, $rs1, $rs2, $qw, $qy", []> +{ + bits<5> rs2; + bits<3> qy; + bits<5> rs1; + bits<3> qw; + bits<3> qu; + bits<5> rs1r; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 1; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1, $qwr = $qw"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRC_Q_LD_XP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs2, imm8:$qy, GPRPIE:$rs1, imm8:$qw, imm8:$qu), + "!esp_src_q_ld_xp_p $qu, $rs1, $rs2, $qw, $qy", + [(int_riscv_esp_src_q_ld_xp GPRPIE:$rs2, timm:$qy, GPRPIE:$rs1, timm:$qw, timm:$qu)]>; + +def ESP_SRC_Q_QUP: Esp32P4Inst<(outs QR:$qz, QR:$qwr), (ins QR:$qy, QR:$qw), + "esp.src.q.qup\t $qz, $qw, $qy", []> +{ + bits<3> qy; + bits<3> qw; + bits<3> qz; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qwr = $qw"; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9-7} = qz{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRC_Q_QUP_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, imm8:$qz), + "!esp_src_q_qup_p $qz, $qw, $qy", + [(int_riscv_esp_src_q_qup timm:$qy, timm:$qw, timm:$qz)]>; + +def ESP_SRCI_2Q: Esp32P4Inst<(outs QR:$qyr, QR:$qwr), (ins QR:$qy, QR:$qw, select_16:$sel16), + "esp.srci.2q\t $qy, $qw, $sel16", []> +{ + bits<3> qy; + bits<3> qw; + bits<4> sel16; + bits<3> qyr; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qyr = $qy, $qwr = $qw"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 1; + let Inst{22} = sel16{3}; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 1; + let Inst{10} = 0; + let Inst{9-7} = sel16{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCI_2Q_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, select_16:$sel16), + "!esp_srci_2q_p $qy, $qw, $sel16", + [(int_riscv_esp_srci_2q timm:$qy, timm:$qw, timm:$sel16)]>; + +def ESP_SRCMB_S16_Q_QACC: Esp32P4Inst<(outs QR:$qu), (ins QR:$qw, select_2:$sel2), + "esp.srcmb.s16.q.qacc\t $qu, $qw, $sel2", []> +{ + bits<3> qw; + bits<1> sel2; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = sel2{0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCMB_S16_Q_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qw, select_2:$sel2, imm8:$qu), + "!esp_srcmb_s16_q_qacc_p $qu, $qw, $sel2", + [(int_riscv_esp_srcmb_s16_q_qacc timm:$qw, timm:$sel2, timm:$qu)]>; + +def ESP_SRCMB_S16_QACC: Esp32P4Inst<(outs QR:$qu), (ins GPRPIE:$rs1, select_2:$sel2), + "esp.srcmb.s16.qacc\t $qu, $rs1, $sel2", []> +{ + bits<5> rs1; + bits<1> sel2; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 1; + let Inst{29} = sel2{0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCMB_S16_QACC_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, select_2:$sel2, imm8:$qu), + "!esp_srcmb_s16_qacc_p $qu, $rs1, $sel2", + [(int_riscv_esp_srcmb_s16_qacc GPRPIE:$rs1, timm:$sel2, timm:$qu)]>; + +def ESP_SRCMB_S8_Q_QACC: Esp32P4Inst<(outs QR:$qu), (ins QR:$qw, select_2:$sel2), + "esp.srcmb.s8.q.qacc\t $qu, $qw, $sel2", []> +{ + bits<3> qw; + bits<1> sel2; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 1; + let Inst{26} = sel2{0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCMB_S8_Q_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qw, select_2:$sel2, imm8:$qu), + "!esp_srcmb_s8_q_qacc_p $qu, $qw, $sel2", + [(int_riscv_esp_srcmb_s8_q_qacc timm:$qw, timm:$sel2, timm:$qu)]>; + +def ESP_SRCMB_S8_QACC: Esp32P4Inst<(outs QR:$qu), (ins GPRPIE:$rs1, select_2:$sel2), + "esp.srcmb.s8.qacc\t $qu, $rs1, $sel2", []> +{ + bits<5> rs1; + bits<1> sel2; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 1; + let Inst{29} = sel2{0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCMB_S8_QACC_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, select_2:$sel2, imm8:$qu), + "!esp_srcmb_s8_qacc_p $qu, $rs1, $sel2", + [(int_riscv_esp_srcmb_s8_qacc GPRPIE:$rs1, timm:$sel2, timm:$qu)]>; + +def ESP_SRCMB_U16_Q_QACC: Esp32P4Inst<(outs QR:$qu), (ins QR:$qw, select_2:$sel2), + "esp.srcmb.u16.q.qacc\t $qu, $qw, $sel2", []> +{ + bits<3> qw; + bits<1> sel2; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = sel2{0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCMB_U16_Q_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qw, select_2:$sel2, imm8:$qu), + "!esp_srcmb_u16_q_qacc_p $qu, $qw, $sel2", + [(int_riscv_esp_srcmb_u16_q_qacc timm:$qw, timm:$sel2, timm:$qu)]>; + +def ESP_SRCMB_U16_QACC: Esp32P4Inst<(outs QR:$qu), (ins GPRPIE:$rs1, select_2:$sel2), + "esp.srcmb.u16.qacc\t $qu, $rs1, $sel2", []> +{ + bits<5> rs1; + bits<1> sel2; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = sel2{0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCMB_U16_QACC_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, select_2:$sel2, imm8:$qu), + "!esp_srcmb_u16_qacc_p $qu, $rs1, $sel2", + [(int_riscv_esp_srcmb_u16_qacc GPRPIE:$rs1, timm:$sel2, timm:$qu)]>; + +def ESP_SRCMB_U8_Q_QACC: Esp32P4Inst<(outs QR:$qu), (ins QR:$qw, select_2:$sel2), + "esp.srcmb.u8.q.qacc\t $qu, $qw, $sel2", []> +{ + bits<3> qw; + bits<1> sel2; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = sel2{0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCMB_U8_Q_QACC_P : PseudoESP32P4<(outs), (ins imm8:$qw, select_2:$sel2, imm8:$qu), + "!esp_srcmb_u8_q_qacc_p $qu, $qw, $sel2", + [(int_riscv_esp_srcmb_u8_q_qacc timm:$qw, timm:$sel2, timm:$qu)]>; + +def ESP_SRCMB_U8_QACC: Esp32P4Inst<(outs QR:$qu), (ins GPRPIE:$rs1, select_2:$sel2), + "esp.srcmb.u8.qacc\t $qu, $rs1, $sel2", []> +{ + bits<5> rs1; + bits<1> sel2; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = sel2{0}; + let Inst{28} = 1; + let Inst{27} = 1; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCMB_U8_QACC_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, select_2:$sel2, imm8:$qu), + "!esp_srcmb_u8_qacc_p $qu, $rs1, $sel2", + [(int_riscv_esp_srcmb_u8_qacc GPRPIE:$rs1, timm:$sel2, timm:$qu)]>; + +def ESP_SRCQ_128_ST_INCP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins QR:$qy, QR:$qw, GPRPIE:$rs1), + "esp.srcq.128.st.incp\t $qw, $qy, $rs1", []> +{ + bits<3> qy; + bits<3> qw; + bits<5> rs1; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 0; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCQ_128_ST_INCP_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, GPRPIE:$rs1), + "!esp_srcq_128_st_incp_p $qw, $qy, $rs1", + [(int_riscv_esp_srcq_128_st_incp timm:$qy, timm:$qw, GPRPIE:$rs1)]>; + +def ESP_SRCXXP_2Q: Esp32P4Inst<(outs QR:$qyr, QR:$qwr), (ins GPRPIE:$rs1, GPRPIE:$rs2, QR:$qy, QR:$qw), + "esp.srcxxp.2q\t $qy, $qw, $rs1, $rs2", []> +{ + bits<5> rs1; + bits<5> rs2; + bits<3> qy; + bits<3> qw; + bits<3> qyr; + bits<3> qwr; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$qyr = $qy, $qwr = $qw"; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = rs2{4}; + let Inst{22-20} = rs2{2-0}; + let Inst{19} = qw{2}; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = 1; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRCXXP_2Q_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rs2, imm8:$qy, imm8:$qw), + "!esp_srcxxp_2q_p $qy, $qw, $rs1, $rs2", + [(int_riscv_esp_srcxxp_2q GPRPIE:$rs1, GPRPIE:$rs2, timm:$qy, timm:$qw)]>; + +def ESP_SRS_S_XACC: Esp32P4Inst<(outs GPRPIE:$rd), (ins GPRPIE:$rs1), + "esp.srs.s.xacc\t $rd, $rs1", []> +{ + bits<5> rs1; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 1; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRS_S_XACC_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rd), + "!esp_srs_s_xacc_p $rd, $rs1", + [(int_riscv_esp_srs_s_xacc GPRPIE:$rs1, GPRPIE:$rd)]>; + +def ESP_SRS_U_XACC: Esp32P4Inst<(outs GPRPIE:$rd), (ins GPRPIE:$rs1), + "esp.srs.u.xacc\t $rd, $rs1", []> +{ + bits<5> rs1; + bits<5> rd; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 1; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 1; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 1; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11} = 0; + let Inst{10} = rd{4}; + let Inst{9-7} = rd{2-0}; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_SRS_U_XACC_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, GPRPIE:$rd), + "!esp_srs_u_xacc_p $rd, $rs1", + [(int_riscv_esp_srs_u_xacc GPRPIE:$rs1, GPRPIE:$rd)]>; + +def ESP_VSL_32: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy), + "esp.vsl.32\t $qu, $qy", []> +{ + bits<3> qy; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSL_32_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qu), + "!esp_vsl_32_p $qu, $qy", + [(int_riscv_esp_vsl_32 timm:$qy, timm:$qu)]>; + +def ESP_VSLD_16: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy, QR:$qw), + "esp.vsld.16\t $qu, $qy, $qw", []> +{ + bits<3> qy; + bits<3> qw; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSLD_16_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, imm8:$qu), + "!esp_vsld_16_p $qu, $qy, $qw", + [(int_riscv_esp_vsld_16 timm:$qy, timm:$qw, timm:$qu)]>; + +def ESP_VSLD_32: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy, QR:$qw), + "esp.vsld.32\t $qu, $qy, $qw", []> +{ + bits<3> qy; + bits<3> qw; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSLD_32_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, imm8:$qu), + "!esp_vsld_32_p $qu, $qy, $qw", + [(int_riscv_esp_vsld_32 timm:$qy, timm:$qw, timm:$qu)]>; + +def ESP_VSLD_8: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy, QR:$qw), + "esp.vsld.8\t $qu, $qy, $qw", []> +{ + bits<3> qy; + bits<3> qw; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSLD_8_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, imm8:$qu), + "!esp_vsld_8_p $qu, $qy, $qw", + [(int_riscv_esp_vsld_8 timm:$qy, timm:$qw, timm:$qu)]>; + +def ESP_VSR_S32: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy), + "esp.vsr.s32\t $qu, $qy", []> +{ + bits<3> qy; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 1; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSR_S32_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qu), + "!esp_vsr_s32_p $qu, $qy", + [(int_riscv_esp_vsr_s32 timm:$qy, timm:$qu)]>; + +def ESP_VSR_U32: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy), + "esp.vsr.u32\t $qu, $qy", []> +{ + bits<3> qy; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 1; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23} = 0; + let Inst{22} = 0; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = 0; + let Inst{18} = 1; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSR_U32_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qu), + "!esp_vsr_u32_p $qu, $qy", + [(int_riscv_esp_vsr_u32 timm:$qy, timm:$qu)]>; + +def ESP_VSRD_16: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy, QR:$qw), + "esp.vsrd.16\t $qu, $qy, $qw", []> +{ + bits<3> qy; + bits<3> qw; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 1; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSRD_16_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, imm8:$qu), + "!esp_vsrd_16_p $qu, $qy, $qw", + [(int_riscv_esp_vsrd_16 timm:$qy, timm:$qw, timm:$qu)]>; + +def ESP_VSRD_32: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy, QR:$qw), + "esp.vsrd.32\t $qu, $qy, $qw", []> +{ + bits<3> qy; + bits<3> qw; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 1; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSRD_32_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, imm8:$qu), + "!esp_vsrd_32_p $qu, $qy, $qw", + [(int_riscv_esp_vsrd_32 timm:$qy, timm:$qw, timm:$qu)]>; + +def ESP_VSRD_8: Esp32P4Inst<(outs QR:$qu), (ins QR:$qy, QR:$qw), + "esp.vsrd.8\t $qu, $qy, $qw", []> +{ + bits<3> qy; + bits<3> qw; + bits<3> qu; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31} = 0; + let Inst{30} = 0; + let Inst{29} = 0; + let Inst{28-26} = qy{2-0}; + let Inst{25-24} = qw{1-0}; + let Inst{23} = 0; + let Inst{22} = 1; + let Inst{21} = 0; + let Inst{20} = 0; + let Inst{19} = qw{2}; + let Inst{18} = 0; + let Inst{17} = 0; + let Inst{16} = 0; + let Inst{15} = 0; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12-10} = qu{2-0}; + let Inst{9} = 0; + let Inst{8} = 0; + let Inst{7} = 0; + let Inst{6} = 1; + let Inst{5} = 0; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 1; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_VSRD_8_P : PseudoESP32P4<(outs), (ins imm8:$qy, imm8:$qw, imm8:$qu), + "!esp_vsrd_8_p $qu, $qy, $qw", + [(int_riscv_esp_vsrd_8 timm:$qy, timm:$qw, timm:$qu)]>; + +def ESP_ST_S_XACC_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_8:$off2568), + "esp.st.s.xacc.ip\t $rs1, $off2568", []> +{ + bits<5> rs1; + bits<8> off2568; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 1; + let Inst{30} = off2568{7}; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off2568{6-3}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = off2568{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ST_S_XACC_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_8:$off2568), + "!esp_st_s_xacc_ip_p $rs1, $off2568", + [(int_riscv_esp_st_s_xacc_ip GPRPIE:$rs1, timm:$off2568)]>; + +def ESP_ST_U_XACC_IP: Esp32P4Inst<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_8:$off2568), + "esp.st.u.xacc.ip\t $rs1, $off2568", []> +{ + bits<5> rs1; + bits<8> off2568; + bits<5> rs1r; + let mayStore = 1; + let mayLoad = 0; + let hasSideEffects = 1; + + let Constraints = "$rs1r = $rs1"; + + let Inst{31} = 0; + let Inst{30} = off2568{7}; + let Inst{29} = 1; + let Inst{28} = 0; + let Inst{27} = 0; + let Inst{26} = 0; + let Inst{25} = 0; + let Inst{24} = 0; + let Inst{23-20} = off2568{6-3}; + let Inst{19} = 0; + let Inst{18} = rs1{4}; + let Inst{17-15} = rs1{2-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12-10} = off2568{2-0}; + let Inst{9} = 0; + let Inst{8} = 1; + let Inst{7} = 1; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 1; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +let usesCustomInserter = 1 in +def ESP_ST_U_XACC_IP_P : PseudoESP32P4<(outs), (ins GPRPIE:$rs1, offset_256_8:$off2568), + "!esp_st_u_xacc_ip_p $rs1, $off2568", + [(int_riscv_esp_st_u_xacc_ip GPRPIE:$rs1, timm:$off2568)]>; + diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td new file mode 100644 index 00000000000000..55eb4326575c28 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td @@ -0,0 +1,172 @@ +//===- RISCVInstrInfoP4HWLP.td - RISCV Target Description -*- tablegen -*--===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISCV ESP32P4 DSP instructions in TableGen format. +// +// These definitions are generated +// This file is generated +// +//===----------------------------------------------------------------------===// + +def ESP_LP_SETUPI: Esp32P4Inst<(outs), (ins uimm1:$id, uimm12:$count, uimm10_step4:$offset), + "esp.lp.setupi\t $id, $count, $offset", []> +{ + bits<1> id; + bits<13> count; + bits<10> offset; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-20} = count{11-0}; + let Inst{19-15} = offset{5-1}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11-8} = offset{9-6}; + let Inst{7} = id; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 0; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +def ESP_LP_SETUP: Esp32P4Inst<(outs), (ins uimm1:$id, GPRPIE:$rs1, uimm13_step4:$offset), + "esp.lp.setup\t $id, $rs1, $offset", []> +{ + bits<1> id; + bits<5> rs1; + bits<13> offset; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-20} = offset{12-1}; + let Inst{19-15} = rs1{4-0}; + let Inst{14} = 1; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11-8} = 0xb0000; + let Inst{7} = id; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 0; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +def ESP_LP_STARTI: Esp32P4Inst<(outs), (ins uimm1:$id, uimm13_step4:$offset), + "esp.lp.starti\t $id, $offset", []> +{ + bits<1> id; + bits<5> rs1; + bits<13> offset; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-20} = offset{12-1}; + let Inst{19-15} = 0xb00000; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 0; + let Inst{11-8} = 0xb0000; + let Inst{7} = id; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 0; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +def ESP_LP_ENDI: Esp32P4Inst<(outs), (ins uimm1:$id, uimm13_step4:$offset), + "esp.lp.endi\t $id, $offset", []> +{ + bits<1> id; + bits<5> rs1; + bits<13> offset; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-20} = offset{12-1}; + let Inst{19-15} = 0xb00000; + let Inst{14} = 0; + let Inst{13} = 0; + let Inst{12} = 1; + let Inst{11-8} = 0xb0000; + let Inst{7} = id; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 0; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +def ESP_LP_COUNTI: Esp32P4Inst<(outs), (ins uimm1:$id, uimm12:$count), + "esp.lp.counti\t $id, $count", []> +{ + bits<1> id; + bits<5> rs1; + bits<12> count; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-20} = count{11-0}; + let Inst{19-15} = 0xb00000; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 1; + let Inst{11-8} = 0xb0000; + let Inst{7} = id; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 0; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} + +def ESP_LP_COUNT: Esp32P4Inst<(outs), (ins uimm1:$id, GPRPIE:$rs1), + "esp.lp.count\t $id, $rs1", []> +{ + bits<1> id; + bits<5> rs1; + bits<13> offset; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + + let Inst{31-20} = 0xb000000000000; + let Inst{19-15} = 0xb00000; + let Inst{14} = 0; + let Inst{13} = 1; + let Inst{12} = 0; + let Inst{11-8} = 0xb0000; + let Inst{7} = id; + let Inst{6} = 0; + let Inst{5} = 1; + let Inst{4} = 0; + let Inst{3} = 1; + let Inst{2} = 0; + let Inst{1} = 1; + let Inst{0} = 1; +} \ No newline at end of file diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 03ca505d100df4..613957271afaf0 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -348,3 +348,17 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", FeatureStdExtSvinval, FeatureStdExtZicbom, FeatureStdExtZicboz]>; + +def ESPRESSIF_ESP32P4 : RISCVProcessorModel<"esp32p4", + NoSchedModel, + [Feature32Bit, + FeatureVendorESP32P4, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtC, + FeatureStdExtZcb, + FeatureStdExtZcmp, + FeatureStdExtZcmt]>; \ No newline at end of file diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 5a4d8c4cfece7f..c6da06f83f266d 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -116,6 +116,24 @@ let RegAltNameIndices = [ABIRegAltName] in { } } +class QRReg num, string n, listalt = []> : Register{ + let Namespace = "RISCV"; + let HWEncoding{15-0} = num; + let AltNames = alt; +} +let RegAltNameIndices = [ABIRegAltName] in { + def Q0 : QRReg<0, "q0", ["q0"]>, DwarfRegNum<[0]>; + def Q1 : QRReg<1, "q1", ["q1"]>, DwarfRegNum<[1]>; + def Q2 : QRReg<2, "q2", ["q2"]>, DwarfRegNum<[2]>; + def Q3 : QRReg<3, "q3", ["q3"]>, DwarfRegNum<[3]>; + def Q4 : QRReg<4, "q4", ["q4"]>, DwarfRegNum<[4]>; + def Q5 : QRReg<5, "q5", ["q5"]>, DwarfRegNum<[5]>; + def Q6 : QRReg<6, "q6", ["q6"]>, DwarfRegNum<[6]>; + def Q7 : QRReg<7, "q7", ["q7"]>, DwarfRegNum<[7]>; +} + +def QR : RegisterClass<"RISCV", [v16i8, v4i32], 128, (sequence "Q%u", 0, 7)>; + def XLenVT : ValueTypeByHwMode<[RV32, RV64], [i32, i64]>; // Allow f64 in GPR for ZDINX on RV64. @@ -141,6 +159,9 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17), (sequence "X%u", 18, 27), (sequence "X%u", 0, 4))>; +def GPRPIE : GPRRegisterClass<(add (sequence "X%u", 8, 15), + (sequence "X%u", 24, 31))>; + def GPRX0 : GPRRegisterClass<(add X0)>; def GPRX1 : GPRRegisterClass<(add X1)>; def GPRX5 : GPRRegisterClass<(add X5)>; diff --git a/llvm/test/CodeGen/RISCV/esp32p4.ll b/llvm/test/CodeGen/RISCV/esp32p4.ll new file mode 100644 index 00000000000000..a30afb429845e8 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/esp32p4.ll @@ -0,0 +1,1289 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O1 -mtriple=riscv32 -mcpu=esp32p4 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=CHECK + +define void @test(){ +; CHECK-LABEL: test: +; CHECK: # %bb.0: +; CHECK-NEXT: cm.push {ra, s0-s11}, -64 +; CHECK-NEXT: .cfi_def_cfa_offset 64 +; CHECK-NEXT: .cfi_offset s0, -48 +; CHECK-NEXT: .cfi_offset s1, -44 +; CHECK-NEXT: .cfi_offset s8, -16 +; CHECK-NEXT: .cfi_offset s9, -12 +; CHECK-NEXT: .cfi_offset s10, -8 +; CHECK-NEXT: .cfi_offset s11, -4 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q0, a0, 784 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q1, a0, 784 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q2, a0, 784 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q3, a0, 784 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q4, a0, 784 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q5, a0, 784 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q6, a0, 784 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q7, a0, 784 +; CHECK-NEXT: esp.vcmulas.s16.qacc.h q0, q4 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.vcmulas.s16.qacc.h.ld.ip q1, a0, -48, q6, q1 +; CHECK-NEXT: li s9, 12 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.vcmulas.s16.qacc.h.ld.xp q1, a0, s9, q2, q7 +; CHECK-NEXT: esp.vcmulas.s16.qacc.l q7, q6 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vcmulas.s16.qacc.l.ld.ip q7, a0, 48, q7, q0 +; CHECK-NEXT: li t4, 14 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.vcmulas.s16.qacc.l.ld.xp q1, a0, t4, q2, q7 +; CHECK-NEXT: esp.vcmulas.s8.qacc.h q1, q1 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vcmulas.s8.qacc.h.ld.ip q4, a0, 32, q1, q6 +; CHECK-NEXT: li s11, 7 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.vcmulas.s8.qacc.h.ld.xp q6, a0, s11, q3, q2 +; CHECK-NEXT: esp.vcmulas.s8.qacc.l q4, q5 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.vcmulas.s8.qacc.l.ld.ip q4, a0, -48, q2, q5 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.vcmulas.s8.qacc.l.ld.xp q7, a0, s11, q6, q3 +; CHECK-NEXT: esp.vmulas.s16.qacc q4, q2 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.vmulas.s16.qacc.ld.ip q1, a0, 96, q5, q7 +; CHECK-NEXT: li t3, 3 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vmulas.s16.qacc.ld.xp q6, a0, t3, q4, q2 +; CHECK-NEXT: li a5, 0 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: esp.vmulas.s16.qacc.st.ip q1, a0, 80, q7, q6 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vmulas.s16.qacc.st.xp q6, a0, a0, q0, q7 +; CHECK-NEXT: esp.vmulas.s16.xacc q3, q5 +; CHECK-NEXT: li a0, 9 +; CHECK-NEXT: esp.vmulas.s16.xacc.ld.ip q5, a0, 96, q1, q7 +; CHECK-NEXT: li a2, 8 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.vmulas.s16.xacc.ld.xp q0, a0, a2, q5, q5 +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: esp.vmulas.s16.xacc.st.ip q2, a0, 16, q4, q6 +; CHECK-NEXT: li t6, 5 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.vmulas.s16.xacc.st.xp q7, a0, t6, q7, q7 +; CHECK-NEXT: esp.vmulas.s8.qacc q6, q1 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vmulas.s8.qacc.ld.ip q2, a0, -128, q3, q5 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vmulas.s8.qacc.ld.xp q4, a0, t6, q0, q5 +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: esp.vmulas.s8.qacc.st.ip q7, a0, 16, q6, q0 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.vmulas.s8.qacc.st.xp q4, a0, s9, q6, q1 +; CHECK-NEXT: esp.vmulas.s8.xacc q3, q7 +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: esp.vmulas.s8.xacc.ld.ip q7, a0, -16, q4, q5 +; CHECK-NEXT: li t5, 10 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.vmulas.s8.xacc.ld.xp q1, a0, t5, q7, q0 +; CHECK-NEXT: li a1, 2 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vmulas.s8.xacc.st.ip q6, a0, -128, q6, q1 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.vmulas.s8.xacc.st.xp q5, a0, a1, q4, q1 +; CHECK-NEXT: esp.vmulas.u16.qacc q6, q1 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vmulas.u16.qacc.ld.ip q7, a0, -32, q0, q0 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.vmulas.u16.qacc.ld.xp q2, a0, s11, q6, q7 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vmulas.u16.qacc.st.ip q4, a0, 16, q6, q5 +; CHECK-NEXT: li s0, 9 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.vmulas.u16.qacc.st.xp q4, a0, s0, q3, q7 +; CHECK-NEXT: esp.vmulas.u16.xacc q6, q1 +; CHECK-NEXT: li a4, 6 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.vmulas.u16.xacc.ld.ip q2, a0, -48, q2, q2 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: esp.vmulas.u16.xacc.ld.xp q7, a0, a4, q3, q0 +; CHECK-NEXT: li a0, 9 +; CHECK-NEXT: esp.vmulas.u16.xacc.st.ip q0, a0, 96, q1, q4 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.vmulas.u16.xacc.st.xp q6, a0, t6, q3, q7 +; CHECK-NEXT: esp.vmulas.u8.qacc q7, q1 +; CHECK-NEXT: li a0, 9 +; CHECK-NEXT: esp.vmulas.u8.qacc.ld.ip q7, a0, -48, q7, q4 +; CHECK-NEXT: li a0, 11 +; CHECK-NEXT: esp.vmulas.u8.qacc.ld.xp q4, a0, s9, q6, q7 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.vmulas.u8.qacc.st.ip q2, a0, 0, q1, q7 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.vmulas.u8.qacc.st.xp q4, a0, a0, q0, q0 +; CHECK-NEXT: esp.vmulas.u8.xacc q6, q4 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vmulas.u8.xacc.ld.ip q3, a0, -80, q6, q2 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.vmulas.u8.xacc.ld.xp q4, a0, a0, q5, q1 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vmulas.u8.xacc.st.ip q7, a0, -128, q2, q3 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vmulas.u8.xacc.st.xp q2, a0, a4, q7, q2 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.vmulas.s16.qacc.ldbc.incp q0, a0, q0, q2 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: esp.vmulas.s8.qacc.ldbc.incp q5, a0, q2, q6 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vmulas.u16.qacc.ldbc.incp q5, a0, q7, q3 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.vmulas.u8.qacc.ldbc.incp q3, a0, q4, q4 +; CHECK-NEXT: esp.vsmulas.s16.qacc q1, q5, 14 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vsmulas.s16.qacc.ld.incp q0, a0, q7, q4, 0 +; CHECK-NEXT: esp.vsmulas.s8.qacc q3, q5, 0 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vsmulas.s8.qacc.ld.incp q1, a0, q1, q4, 6 +; CHECK-NEXT: esp.vsmulas.u16.qacc q6, q5, 15 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: esp.vsmulas.u16.qacc.ld.incp q7, a0, q7, q1, 10 +; CHECK-NEXT: esp.vsmulas.u8.qacc q0, q7, 2 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.vsmulas.u8.qacc.ld.incp q4, a0, q3, q7, 8 +; CHECK-NEXT: esp.cmul.s16 q6, q0, q7, 3 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.cmul.s16.ld.incp q5, a0, q3, q0, q3, 0 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: esp.cmul.s16.st.incp q5, a0, q0, q4, q5, 2 +; CHECK-NEXT: esp.cmul.s8 q1, q1, q0, 3 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.cmul.s8.ld.incp q4, a0, q7, q5, q4, 1 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.cmul.s8.st.incp q5, a0, q0, q6, q0, 3 +; CHECK-NEXT: esp.cmul.u16 q7, q7, q5, 2 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.cmul.u16.ld.incp q0, a0, q0, q0, q1, 1 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.cmul.u16.st.incp q2, a0, q4, q1, q4, 2 +; CHECK-NEXT: esp.cmul.u8 q3, q7, q5, 0 +; CHECK-NEXT: li a0, 11 +; CHECK-NEXT: esp.cmul.u8.ld.incp q4, a0, q0, q0, q2, 0 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.cmul.u8.st.incp q1, a0, q4, q6, q3, 2 +; CHECK-NEXT: esp.max.s16.a q6, a0 +; CHECK-NEXT: esp.max.s32.a q2, a0 +; CHECK-NEXT: esp.max.s8.a q0, a0 +; CHECK-NEXT: esp.max.u16.a q6, a0 +; CHECK-NEXT: esp.max.u32.a q6, a0 +; CHECK-NEXT: esp.max.u8.a q1, a0 +; CHECK-NEXT: esp.min.s16.a q6, a0 +; CHECK-NEXT: esp.min.s32.a q1, a0 +; CHECK-NEXT: esp.min.s8.a q0, a0 +; CHECK-NEXT: esp.min.u16.a q3, a0 +; CHECK-NEXT: esp.min.u32.a q0, a0 +; CHECK-NEXT: esp.min.u8.a q5, a0 +; CHECK-NEXT: esp.vabs.16 q6, q0 +; CHECK-NEXT: esp.vabs.32 q1, q4 +; CHECK-NEXT: esp.vabs.8 q5, q2 +; CHECK-NEXT: esp.vadd.s16 q6, q1, q5 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.vadd.s16.ld.incp q0, a0, q1, q0, q6 +; CHECK-NEXT: li a0, 11 +; CHECK-NEXT: esp.vadd.s16.st.incp q1, a0, q7, q0, q4 +; CHECK-NEXT: esp.vadd.s32 q7, q7, q3 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.vadd.s32.ld.incp q4, a0, q4, q7, q2 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.vadd.s32.st.incp q2, a0, q7, q1, q7 +; CHECK-NEXT: esp.vadd.s8 q7, q1, q7 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.vadd.s8.ld.incp q2, a0, q1, q5, q6 +; CHECK-NEXT: li a0, 9 +; CHECK-NEXT: esp.vadd.s8.st.incp q3, a0, q4, q1, q0 +; CHECK-NEXT: esp.vadd.u16 q0, q7, q7 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vadd.u16.ld.incp q6, a0, q1, q7, q5 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vadd.u16.st.incp q0, a0, q7, q6, q3 +; CHECK-NEXT: esp.vadd.u32 q4, q0, q1 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.vadd.u32.ld.incp q1, a0, q4, q5, q0 +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: esp.vadd.u32.st.incp q4, a0, q6, q0, q1 +; CHECK-NEXT: esp.vadd.u8 q5, q2, q5 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vadd.u8.ld.incp q7, a0, q1, q4, q3 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vadd.u8.st.incp q0, a0, q2, q0, q0 +; CHECK-NEXT: esp.vclamp.s16 q4, q5, 14 +; CHECK-NEXT: esp.vmax.s16 q5, q6, q5 +; CHECK-NEXT: li a0, 11 +; CHECK-NEXT: esp.vmax.s16.ld.incp q2, a0, q3, q5, q5 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.vmax.s16.st.incp q3, a0, q4, q3, q5 +; CHECK-NEXT: esp.vmax.s32 q2, q5, q2 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.vmax.s32.ld.incp q0, a0, q6, q0, q1 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.vmax.s32.st.incp q6, a0, q1, q7, q6 +; CHECK-NEXT: esp.vmax.s8 q7, q5, q7 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.vmax.s8.ld.incp q6, a0, q1, q5, q1 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.vmax.s8.st.incp q5, a0, q7, q1, q3 +; CHECK-NEXT: esp.vmax.u16 q1, q4, q1 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: esp.vmax.u16.ld.incp q3, a0, q5, q5, q4 +; CHECK-NEXT: li a0, 11 +; CHECK-NEXT: esp.vmax.u16.st.incp q5, a0, q5, q0, q7 +; CHECK-NEXT: esp.vmax.u32 q4, q0, q2 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.vmax.u32.ld.incp q6, a0, q1, q0, q6 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.vmax.u32.st.incp q0, a0, q1, q4, q7 +; CHECK-NEXT: esp.vmax.u8 q5, q2, q0 +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: esp.vmax.u8.ld.incp q0, a0, q5, q6, q1 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.vmax.u8.st.incp q7, a0, q1, q6, q7 +; CHECK-NEXT: esp.vmin.s16 q4, q1, q3 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.vmin.s16.ld.incp q2, a0, q2, q2, q1 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.vmin.s16.st.incp q2, a0, q1, q7, q6 +; CHECK-NEXT: esp.vmin.s32 q2, q0, q3 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.vmin.s32.ld.incp q1, a0, q5, q7, q6 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.vmin.s32.st.incp q7, a0, q5, q5, q1 +; CHECK-NEXT: esp.vmin.s8 q2, q3, q6 +; CHECK-NEXT: li a0, 11 +; CHECK-NEXT: esp.vmin.s8.ld.incp q7, a0, q1, q4, q3 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.vmin.s8.st.incp q1, a0, q4, q0, q1 +; CHECK-NEXT: esp.vmin.u16 q4, q3, q7 +; CHECK-NEXT: li a0, 11 +; CHECK-NEXT: esp.vmin.u16.ld.incp q4, a0, q5, q6, q6 +; CHECK-NEXT: li a0, 12 +; CHECK-NEXT: esp.vmin.u16.st.incp q1, a0, q2, q6, q0 +; CHECK-NEXT: esp.vmin.u32 q5, q0, q7 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.vmin.u32.ld.incp q7, a0, q6, q5, q6 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.vmin.u32.st.incp q5, a0, q4, q3, q7 +; CHECK-NEXT: esp.vmin.u8 q7, q5, q5 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: esp.vmin.u8.ld.incp q2, a0, q5, q0, q5 +; CHECK-NEXT: li a0, 12 +; CHECK-NEXT: esp.vmin.u8.st.incp q2, a0, q1, q6, q6 +; CHECK-NEXT: esp.vmul.s16 q6, q2, q1 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.vmul.s16.ld.incp q0, a0, q3, q6, q7 +; CHECK-NEXT: esp.vmul.s16.s8xs8 q7, q0, q3, q5 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.vmul.s16.st.incp q2, a0, q0, q7, q1 +; CHECK-NEXT: esp.vmul.s32.s16xs16 q3, q4, q5, q2 +; CHECK-NEXT: esp.vmul.s8 q3, q4, q0 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: esp.vmul.s8.ld.incp q0, a0, q2, q2, q3 +; CHECK-NEXT: li s1, 4 +; CHECK-NEXT: li s8, 13 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vmul.s8.st.incp q0, a0, q3, q0, q7 +; CHECK-NEXT: esp.vmul.u16 q2, q3, q7 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.vmul.u16.ld.incp q5, a0, q5, q6, q6 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.vmul.u16.st.incp q3, a0, q2, q4, q4 +; CHECK-NEXT: esp.vmul.u8 q7, q3, q7 +; CHECK-NEXT: li a0, 9 +; CHECK-NEXT: esp.vmul.u8.ld.incp q0, a0, q1, q0, q6 +; CHECK-NEXT: li s10, 1 +; CHECK-NEXT: li a0, 11 +; CHECK-NEXT: li a3, 6 +; CHECK-NEXT: esp.vmul.u8.st.incp q7, a3, q4, q0, q3 +; CHECK-NEXT: esp.vprelu.s16 q1, q4, q3, a2 +; CHECK-NEXT: esp.vprelu.s8 q2, q4, q5, t3 +; CHECK-NEXT: esp.vrelu.s16 q6, s0, a2 +; CHECK-NEXT: esp.vrelu.s8 q5, s10, s9 +; CHECK-NEXT: esp.vsadds.s16 q3, q3, s9 +; CHECK-NEXT: esp.vsadds.s8 q7, q1, s11 +; CHECK-NEXT: esp.vsadds.u16 q3, q2, s1 +; CHECK-NEXT: esp.vsadds.u8 q2, q3, a2 +; CHECK-NEXT: esp.vsat.s16 q5, q0, s0, s10 +; CHECK-NEXT: esp.vsat.s32 q3, q3, s9, s0 +; CHECK-NEXT: esp.vsat.s8 q0, q7, t5, a1 +; CHECK-NEXT: esp.vsat.u16 q3, q7, s11, s11 +; CHECK-NEXT: esp.vsat.u32 q3, q5, a2, a1 +; CHECK-NEXT: esp.vsat.u8 q0, q6, s10, s8 +; CHECK-NEXT: esp.vssubs.s16 q3, q7, t3 +; CHECK-NEXT: esp.vssubs.s8 q7, q0, t4 +; CHECK-NEXT: esp.vssubs.u16 q5, q4, a5 +; CHECK-NEXT: esp.vssubs.u8 q5, q1, a0 +; CHECK-NEXT: esp.vsub.s16 q0, q0, q6 +; CHECK-NEXT: li a3, 6 +; CHECK-NEXT: esp.vsub.s16.ld.incp q2, a3, q2, q3, q7 +; CHECK-NEXT: li a3, 0 +; CHECK-NEXT: esp.vsub.s16.st.incp q7, a3, q0, q0, q3 +; CHECK-NEXT: esp.vsub.s32 q7, q2, q7 +; CHECK-NEXT: li a3, 7 +; CHECK-NEXT: esp.vsub.s32.ld.incp q4, a3, q3, q2, q0 +; CHECK-NEXT: li a3, 5 +; CHECK-NEXT: esp.vsub.s32.st.incp q4, a3, q1, q1, q1 +; CHECK-NEXT: esp.vsub.s8 q7, q5, q6 +; CHECK-NEXT: li a3, 1 +; CHECK-NEXT: esp.vsub.s8.ld.incp q4, a3, q1, q2, q6 +; CHECK-NEXT: li a3, 4 +; CHECK-NEXT: esp.vsub.s8.st.incp q5, a3, q4, q2, q3 +; CHECK-NEXT: esp.vsub.u16 q5, q7, q0 +; CHECK-NEXT: li a3, 11 +; CHECK-NEXT: esp.vsub.u16.ld.incp q4, a3, q0, q7, q5 +; CHECK-NEXT: li a3, 11 +; CHECK-NEXT: esp.vsub.u16.st.incp q0, a3, q1, q3, q1 +; CHECK-NEXT: esp.vsub.u32 q5, q4, q2 +; CHECK-NEXT: li a3, 0 +; CHECK-NEXT: esp.vsub.u32.ld.incp q4, a3, q2, q4, q2 +; CHECK-NEXT: li a3, 11 +; CHECK-NEXT: esp.vsub.u32.st.incp q0, a3, q7, q7, q4 +; CHECK-NEXT: esp.vsub.u8 q6, q5, q4 +; CHECK-NEXT: li a3, 0 +; CHECK-NEXT: esp.vsub.u8.ld.incp q4, a3, q6, q2, q4 +; CHECK-NEXT: esp.vsub.u8.st.incp q3, a0, q3, q2, q0 +; CHECK-NEXT: esp.addx2 zero, t6, t4 +; CHECK-NEXT: esp.addx4 zero, t4, t6 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.sat a0, a4, a1 +; CHECK-NEXT: esp.subx2 zero, a1, a1 +; CHECK-NEXT: esp.subx4 zero, a5, s0 +; CHECK-NEXT: esp.andq q7, q6, q3 +; CHECK-NEXT: esp.notq q6, q5 +; CHECK-NEXT: esp.orq q1, q1, q0 +; CHECK-NEXT: esp.xorq q5, q1, q6 +; CHECK-NEXT: esp.vcmp.eq.s16 q1, q0, q2 +; CHECK-NEXT: esp.vcmp.eq.s32 q5, q1, q6 +; CHECK-NEXT: esp.vcmp.eq.s8 q2, q0, q3 +; CHECK-NEXT: esp.vcmp.eq.u16 q7, q7, q1 +; CHECK-NEXT: esp.vcmp.eq.u32 q2, q1, q2 +; CHECK-NEXT: esp.vcmp.eq.u8 q3, q1, q6 +; CHECK-NEXT: esp.vcmp.gt.s16 q4, q5, q6 +; CHECK-NEXT: esp.vcmp.gt.s32 q0, q6, q2 +; CHECK-NEXT: esp.vcmp.gt.s8 q2, q3, q5 +; CHECK-NEXT: esp.vcmp.gt.u16 q7, q7, q4 +; CHECK-NEXT: esp.vcmp.gt.u32 q2, q6, q2 +; CHECK-NEXT: esp.vcmp.gt.u8 q0, q2, q0 +; CHECK-NEXT: esp.vcmp.lt.s16 q7, q2, q1 +; CHECK-NEXT: esp.vcmp.lt.s32 q4, q2, q1 +; CHECK-NEXT: esp.vcmp.lt.s8 q6, q5, q2 +; CHECK-NEXT: esp.vcmp.lt.u16 q4, q1, q5 +; CHECK-NEXT: esp.vcmp.lt.u32 q2, q5, q6 +; CHECK-NEXT: esp.vcmp.lt.u8 q5, q3, q5 +; CHECK-NEXT: esp.mov.s16.qacc q2 +; CHECK-NEXT: esp.mov.s8.qacc q5 +; CHECK-NEXT: esp.mov.u16.qacc q5 +; CHECK-NEXT: esp.mov.u8.qacc q3 +; CHECK-NEXT: esp.movi.16.a q2, a0, 3 +; CHECK-NEXT: esp.movi.16.q q3, s11, 13 +; CHECK-NEXT: esp.movi.32.a q6, a0, 1 +; CHECK-NEXT: esp.movi.32.q q5, s0, 1 +; CHECK-NEXT: esp.movi.8.a q5, a0, 15 +; CHECK-NEXT: esp.movi.8.q q1, a5, 6 +; CHECK-NEXT: esp.movx.r.cfg a0 +; CHECK-NEXT: esp.movx.r.fft.bit.width a0 +; CHECK-NEXT: li a0, 33 +; CHECK-NEXT: esp.movx.r.perf a0, a0 +; CHECK-NEXT: esp.movx.r.sar a0 +; CHECK-NEXT: esp.movx.r.sar.bytes a0 +; CHECK-NEXT: esp.movx.r.xacc.h a0 +; CHECK-NEXT: esp.movx.r.xacc.l a0 +; CHECK-NEXT: esp.movx.w.cfg t5 +; CHECK-NEXT: esp.movx.w.fft.bit.width s10 +; CHECK-NEXT: esp.movx.w.perf a2 +; CHECK-NEXT: esp.movx.w.sar t3 +; CHECK-NEXT: esp.movx.w.sar.bytes s1 +; CHECK-NEXT: esp.movx.w.xacc.h a2 +; CHECK-NEXT: esp.movx.w.xacc.l s1 +; CHECK-NEXT: esp.vext.s16 q7, q0, q6 +; CHECK-NEXT: esp.vext.s8 q5, q3, q3 +; CHECK-NEXT: esp.vext.u16 q4, q2, q6 +; CHECK-NEXT: esp.vext.u8 q4, q0, q0 +; CHECK-NEXT: esp.vunzip.16 q1, q0 +; CHECK-NEXT: esp.vunzip.32 q6, q4 +; CHECK-NEXT: esp.vunzip.8 q2, q1 +; CHECK-NEXT: esp.vunzipt.16 q7, q0, q2 +; CHECK-NEXT: esp.vunzipt.8 q0, q6, q2 +; CHECK-NEXT: esp.vzip.16 q1, q6 +; CHECK-NEXT: esp.vzip.32 q4, q6 +; CHECK-NEXT: esp.vzip.8 q4, q0 +; CHECK-NEXT: esp.vzipt.16 q0, q3, q5 +; CHECK-NEXT: esp.vzipt.8 q6, q1, q5 +; CHECK-NEXT: esp.zero.q q5 +; CHECK-NEXT: esp.zero.qacc +; CHECK-NEXT: esp.zero.xacc +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.fft.ams.s16.ld.incp q6, a0, q6, q0, q3, q0, q1, 0 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.fft.ams.s16.ld.incp.uaup q3, a0, q0, q2, q3, q1, q0, 0 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.fft.ams.s16.ld.r32.decp q7, a0, q0, q6, q3, q1, q5, 1 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: li a3, 4 +; CHECK-NEXT: esp.fft.ams.s16.st.incp q5, q7, a0, a3, q5, q3, q6, 0 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.fft.bitrev q7, a0 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.fft.cmul.s16.ld.xp q2, a0, s10, q3, q7, q7, 1 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.fft.cmul.s16.st.xp q7, q0, q4, a0, a1, 4, 3, 1 +; CHECK-NEXT: esp.fft.r2bf.s16 q7, q3, q5, q1, 0 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.fft.r2bf.s16.st.incp q7, q7, q4, a0, 2 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.fft.vst.r32.decp q5, a0, 1 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.ld.128.usar.ip q1, a0, 608 +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: esp.ld.128.usar.xp q2, a0, a2 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.ld.xacc.ip a0, 400 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.ldqa.s16.128.ip a0, 912 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.ldqa.s16.128.xp a0, t5 +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: esp.ldqa.s8.128.ip a0, 1824 +; CHECK-NEXT: li a0, 9 +; CHECK-NEXT: esp.ldqa.s8.128.xp a0, s1 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.ldqa.u16.128.ip a0, -1904 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.ldqa.u16.128.xp a0, t4 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.ldqa.u8.128.ip a0, 1216 +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: esp.ldqa.u8.128.xp a0, a4 +; CHECK-NEXT: li a0, 9 +; CHECK-NEXT: esp.vldbc.16.ip q7, a0, -448 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.vldbc.16.xp q3, a0, s0 +; CHECK-NEXT: mv a0, a5 +; CHECK-NEXT: esp.vldbc.32.ip q3, a0, 220 +; CHECK-NEXT: li a0, 12 +; CHECK-NEXT: esp.vldbc.32.xp q7, a0, a1 +; CHECK-NEXT: li a0, 12 +; CHECK-NEXT: esp.vldbc.8.ip q2, a0, 396 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.vldbc.8.xp q7, a0, s0 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.vldext.s16.ip q7, q4, a0, 16 +; CHECK-NEXT: mv a0, a5 +; CHECK-NEXT: esp.vldext.s16.xp q5, q0, a0, a2 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.vldext.s8.ip q3, q6, a0, 80 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.vldext.s8.xp q1, q1, a0, a4 +; CHECK-NEXT: li a0, 14 +; CHECK-NEXT: esp.vldext.u16.ip q2, q5, a0, 48 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.vldext.u16.xp q2, q0, a0, s9 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.vldext.u8.ip q7, q2, a0, 64 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.vldext.u8.xp q7, q2, a0, a0 +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: esp.vldhbc.16.incp q4, q7, a0 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.ld.qacc.h.h.128.ip a0, 512 +; CHECK-NEXT: li a0, 5 +; CHECK-NEXT: esp.ld.qacc.h.l.128.ip a0, -784 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.ld.qacc.l.h.128.ip a0, -800 +; CHECK-NEXT: li a0, 10 +; CHECK-NEXT: esp.ld.qacc.l.l.128.ip a0, -1952 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.ld.ua.state.ip a0, -752 +; CHECK-NEXT: esp.ldxq.32 q7, q4, a5, 2, 4 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.st.qacc.h.h.128.ip a0, -336 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.st.qacc.h.l.128.ip a0, 1568 +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: esp.st.qacc.l.h.128.ip a0, 16 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.st.qacc.l.l.128.ip a0, 416 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.st.ua.state.ip a0, -1360 +; CHECK-NEXT: esp.stxq.32 q0, q6, a4, 2, 5 +; CHECK-NEXT: li a0, 8 +; CHECK-NEXT: esp.vld.128.ip q3, a0, 784 +; CHECK-NEXT: li a0, 7 +; CHECK-NEXT: esp.vld.128.xp q3, a0, s0 +; CHECK-NEXT: mv a0, a5 +; CHECK-NEXT: esp.vld.h.64.ip q0, a0, -352 +; CHECK-NEXT: esp.vld.h.64.xp q2, a1, t4 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.vld.l.64.ip q2, a0, 56 +; CHECK-NEXT: esp.vld.l.64.xp q5, s0, s10 +; CHECK-NEXT: li a0, 6 +; CHECK-NEXT: esp.vst.128.ip q5, a0, -960 +; CHECK-NEXT: li a0, 13 +; CHECK-NEXT: esp.vst.128.xp q6, a0, s11 +; CHECK-NEXT: esp.vst.h.64.ip q7, s1, 944 +; CHECK-NEXT: esp.vst.h.64.xp q7, s11, t5 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.vst.l.64.ip q5, a0, 984 +; CHECK-NEXT: li a0, 3 +; CHECK-NEXT: esp.vst.l.64.xp q5, a0, s9 +; CHECK-NEXT: esp.slci.2q q1, q5, 12 +; CHECK-NEXT: esp.slcxxp.2q q2, q3, t6, t6 +; CHECK-NEXT: esp.src.q q2, q1, q3 +; CHECK-NEXT: esp.src.q.ld.ip q0, a5, -272, q5, q5 +; CHECK-NEXT: li a0, 12 +; CHECK-NEXT: esp.src.q.ld.xp q1, a0, t3, q7, q6 +; CHECK-NEXT: esp.src.q.qup q3, q7, q4 +; CHECK-NEXT: esp.srci.2q q2, q3, 7 +; CHECK-NEXT: esp.srcmb.s16.q.qacc q2, q4, 0 +; CHECK-NEXT: esp.srcmb.s16.qacc q5, s8, 1 +; CHECK-NEXT: esp.srcmb.s8.q.qacc q5, q4, 0 +; CHECK-NEXT: esp.srcmb.s8.qacc q1, a2, 1 +; CHECK-NEXT: esp.srcmb.u16.q.qacc q0, q3, 1 +; CHECK-NEXT: esp.srcmb.u16.qacc q7, s8, 0 +; CHECK-NEXT: esp.srcmb.u8.q.qacc q3, q5, 1 +; CHECK-NEXT: esp.srcmb.u8.qacc q0, t6, 0 +; CHECK-NEXT: li a0, 12 +; CHECK-NEXT: esp.srcq.128.st.incp q0, q5, a0 +; CHECK-NEXT: esp.srcxxp.2q q4, q6, s9, a4 +; CHECK-NEXT: esp.srs.s.xacc a0, a4 +; CHECK-NEXT: esp.srs.u.xacc a0, t3 +; CHECK-NEXT: esp.vsl.32 q5, q2 +; CHECK-NEXT: esp.vsld.16 q3, q3, q7 +; CHECK-NEXT: esp.vsld.32 q3, q7, q1 +; CHECK-NEXT: esp.vsld.8 q0, q1, q5 +; CHECK-NEXT: esp.vsr.s32 q3, q0 +; CHECK-NEXT: esp.vsr.u32 q1, q2 +; CHECK-NEXT: esp.vsrd.16 q4, q3, q0 +; CHECK-NEXT: esp.vsrd.32 q0, q6, q3 +; CHECK-NEXT: esp.vsrd.8 q5, q4, q1 +; CHECK-NEXT: esp.st.s.xacc.ip a2, 80 +; CHECK-NEXT: esp.st.u.xacc.ip a4, -464 +; CHECK-NEXT: cm.popret {ra, s0-s11}, 64 + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 0) + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 1) + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 2) + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 3) + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 4) + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 5) + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 6) + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 7) + tail call void @llvm.riscv.esp.vcmulas.s16.qacc.h(i32 0, i32 4) + tail call void @llvm.riscv.esp.vcmulas.s16.qacc.h.ld.ip(i32 6, i32 1, i32 10, i32 -48, i32 1) + tail call void @llvm.riscv.esp.vcmulas.s16.qacc.h.ld.xp(i32 12, i32 2, i32 7, i32 2, i32 1) + tail call void @llvm.riscv.esp.vcmulas.s16.qacc.l(i32 7, i32 6) + tail call void @llvm.riscv.esp.vcmulas.s16.qacc.l.ld.ip(i32 7, i32 0, i32 8, i32 48, i32 7) + tail call void @llvm.riscv.esp.vcmulas.s16.qacc.l.ld.xp(i32 14, i32 2, i32 7, i32 7, i32 1) + tail call void @llvm.riscv.esp.vcmulas.s8.qacc.h(i32 1, i32 1) + tail call void @llvm.riscv.esp.vcmulas.s8.qacc.h.ld.ip(i32 1, i32 6, i32 5, i32 32, i32 4) + tail call void @llvm.riscv.esp.vcmulas.s8.qacc.h.ld.xp(i32 7, i32 3, i32 2, i32 2, i32 6) + tail call void @llvm.riscv.esp.vcmulas.s8.qacc.l(i32 4, i32 5) + tail call void @llvm.riscv.esp.vcmulas.s8.qacc.l.ld.ip(i32 2, i32 5, i32 4, i32 -48, i32 4) + tail call void @llvm.riscv.esp.vcmulas.s8.qacc.l.ld.xp(i32 7, i32 6, i32 3, i32 14, i32 7) + tail call void @llvm.riscv.esp.vmulas.s16.qacc(i32 4, i32 2) + tail call void @llvm.riscv.esp.vmulas.s16.qacc.ld.ip(i32 5, i32 7, i32 4, i32 96, i32 1) + tail call void @llvm.riscv.esp.vmulas.s16.qacc.ld.xp(i32 3, i32 4, i32 2, i32 8, i32 6) + tail call void @llvm.riscv.esp.vmulas.s16.qacc.st.ip(i32 7, i32 6, i32 1, i32 0, i32 80) + tail call void @llvm.riscv.esp.vmulas.s16.qacc.st.xp(i32 5, i32 0, i32 7, i32 6, i32 5) + tail call void @llvm.riscv.esp.vmulas.s16.xacc(i32 3, i32 5) + tail call void @llvm.riscv.esp.vmulas.s16.xacc.ld.ip(i32 1, i32 7, i32 9, i32 96, i32 5) + tail call void @llvm.riscv.esp.vmulas.s16.xacc.ld.xp(i32 8, i32 5, i32 5, i32 13, i32 0) + tail call void @llvm.riscv.esp.vmulas.s16.xacc.st.ip(i32 4, i32 6, i32 2, i32 1, i32 16) + tail call void @llvm.riscv.esp.vmulas.s16.xacc.st.xp(i32 5, i32 7, i32 7, i32 7, i32 2) + tail call void @llvm.riscv.esp.vmulas.s8.qacc(i32 6, i32 1) + tail call void @llvm.riscv.esp.vmulas.s8.qacc.ld.ip(i32 3, i32 5, i32 8, i32 -128, i32 2) + tail call void @llvm.riscv.esp.vmulas.s8.qacc.ld.xp(i32 5, i32 0, i32 5, i32 8, i32 4) + tail call void @llvm.riscv.esp.vmulas.s8.qacc.st.ip(i32 6, i32 0, i32 7, i32 1, i32 16) + tail call void @llvm.riscv.esp.vmulas.s8.qacc.st.xp(i32 12, i32 6, i32 1, i32 4, i32 10) + tail call void @llvm.riscv.esp.vmulas.s8.xacc(i32 3, i32 7) + tail call void @llvm.riscv.esp.vmulas.s8.xacc.ld.ip(i32 4, i32 5, i32 1, i32 -16, i32 7) + tail call void @llvm.riscv.esp.vmulas.s8.xacc.ld.xp(i32 10, i32 7, i32 0, i32 7, i32 1) + tail call void @llvm.riscv.esp.vmulas.s8.xacc.st.ip(i32 6, i32 1, i32 6, i32 8, i32 -128) + tail call void @llvm.riscv.esp.vmulas.s8.xacc.st.xp(i32 2, i32 4, i32 1, i32 5, i32 4) + tail call void @llvm.riscv.esp.vmulas.u16.qacc(i32 6, i32 1) + tail call void @llvm.riscv.esp.vmulas.u16.qacc.ld.ip(i32 0, i32 0, i32 8, i32 -32, i32 7) + tail call void @llvm.riscv.esp.vmulas.u16.qacc.ld.xp(i32 7, i32 6, i32 7, i32 6, i32 2) + tail call void @llvm.riscv.esp.vmulas.u16.qacc.st.ip(i32 6, i32 5, i32 4, i32 8, i32 16) + tail call void @llvm.riscv.esp.vmulas.u16.qacc.st.xp(i32 9, i32 3, i32 7, i32 4, i32 2) + tail call void @llvm.riscv.esp.vmulas.u16.xacc(i32 6, i32 1) + tail call void @llvm.riscv.esp.vmulas.u16.xacc.ld.ip(i32 2, i32 2, i32 3, i32 -48, i32 2) + tail call void @llvm.riscv.esp.vmulas.u16.xacc.ld.xp(i32 6, i32 3, i32 0, i32 0, i32 7) + tail call void @llvm.riscv.esp.vmulas.u16.xacc.st.ip(i32 1, i32 4, i32 0, i32 9, i32 96) + tail call void @llvm.riscv.esp.vmulas.u16.xacc.st.xp(i32 5, i32 3, i32 7, i32 6, i32 2) + tail call void @llvm.riscv.esp.vmulas.u8.qacc(i32 7, i32 1) + tail call void @llvm.riscv.esp.vmulas.u8.qacc.ld.ip(i32 7, i32 4, i32 9, i32 -48, i32 7) + tail call void @llvm.riscv.esp.vmulas.u8.qacc.ld.xp(i32 12, i32 6, i32 7, i32 11, i32 4) + tail call void @llvm.riscv.esp.vmulas.u8.qacc.st.ip(i32 1, i32 7, i32 2, i32 14, i32 0) + tail call void @llvm.riscv.esp.vmulas.u8.qacc.st.xp(i32 7, i32 0, i32 0, i32 4, i32 7) + tail call void @llvm.riscv.esp.vmulas.u8.xacc(i32 6, i32 4) + tail call void @llvm.riscv.esp.vmulas.u8.xacc.ld.ip(i32 6, i32 2, i32 5, i32 -80, i32 3) + tail call void @llvm.riscv.esp.vmulas.u8.xacc.ld.xp(i32 13, i32 5, i32 1, i32 13, i32 4) + tail call void @llvm.riscv.esp.vmulas.u8.xacc.st.ip(i32 2, i32 3, i32 7, i32 5, i32 -128) + tail call void @llvm.riscv.esp.vmulas.u8.xacc.st.xp(i32 6, i32 7, i32 2, i32 2, i32 5) + tail call void @llvm.riscv.esp.vmulas.s16.qacc.ldbc.incp(i32 0, i32 2, i32 14, i32 0) + tail call void @llvm.riscv.esp.vmulas.s8.qacc.ldbc.incp(i32 2, i32 6, i32 0, i32 5) + tail call void @llvm.riscv.esp.vmulas.u16.qacc.ldbc.incp(i32 7, i32 3, i32 8, i32 5) + tail call void @llvm.riscv.esp.vmulas.u8.qacc.ldbc.incp(i32 4, i32 4, i32 6, i32 3) + tail call void @llvm.riscv.esp.vsmulas.s16.qacc(i32 1, i32 5, i32 14) + tail call void @llvm.riscv.esp.vsmulas.s16.qacc.ld.incp(i32 7, i32 4, i32 5, i32 0, i32 0) + tail call void @llvm.riscv.esp.vsmulas.s8.qacc(i32 3, i32 5, i32 0) + tail call void @llvm.riscv.esp.vsmulas.s8.qacc.ld.incp(i32 1, i32 4, i32 8, i32 6, i32 1) + tail call void @llvm.riscv.esp.vsmulas.u16.qacc(i32 6, i32 5, i32 15) + tail call void @llvm.riscv.esp.vsmulas.u16.qacc.ld.incp(i32 7, i32 1, i32 0, i32 10, i32 7) + tail call void @llvm.riscv.esp.vsmulas.u8.qacc(i32 0, i32 7, i32 2) + tail call void @llvm.riscv.esp.vsmulas.u8.qacc.ld.incp(i32 3, i32 7, i32 10, i32 8, i32 4) + tail call void @llvm.riscv.esp.cmul.s16(i32 0, i32 7, i32 3, i32 6) + tail call void @llvm.riscv.esp.cmul.s16.ld.incp(i32 0, i32 3, i32 6, i32 0, i32 3, i32 5) + tail call void @llvm.riscv.esp.cmul.s16.st.incp(i32 4, i32 5, i32 5, i32 0, i32 2, i32 0) + tail call void @llvm.riscv.esp.cmul.s8(i32 1, i32 0, i32 3, i32 1) + tail call void @llvm.riscv.esp.cmul.s8.ld.incp(i32 5, i32 4, i32 5, i32 1, i32 7, i32 4) + tail call void @llvm.riscv.esp.cmul.s8.st.incp(i32 6, i32 0, i32 5, i32 14, i32 3, i32 0) + tail call void @llvm.riscv.esp.cmul.u16(i32 7, i32 5, i32 2, i32 7) + tail call void @llvm.riscv.esp.cmul.u16.ld.incp(i32 0, i32 1, i32 2, i32 1, i32 0, i32 0) + tail call void @llvm.riscv.esp.cmul.u16.st.incp(i32 1, i32 4, i32 2, i32 5, i32 2, i32 4) + tail call void @llvm.riscv.esp.cmul.u8(i32 7, i32 5, i32 0, i32 3) + tail call void @llvm.riscv.esp.cmul.u8.ld.incp(i32 0, i32 2, i32 11, i32 0, i32 0, i32 4) + tail call void @llvm.riscv.esp.cmul.u8.st.incp(i32 6, i32 3, i32 1, i32 10, i32 2, i32 4) + tail call void @llvm.riscv.esp.max.s16.a(i32 6, i32 3) + tail call void @llvm.riscv.esp.max.s32.a(i32 2, i32 0) + tail call void @llvm.riscv.esp.max.s8.a(i32 0, i32 9) + tail call void @llvm.riscv.esp.max.u16.a(i32 6, i32 6) + tail call void @llvm.riscv.esp.max.u32.a(i32 6, i32 1) + tail call void @llvm.riscv.esp.max.u8.a(i32 1, i32 4) + tail call void @llvm.riscv.esp.min.s16.a(i32 6, i32 11) + tail call void @llvm.riscv.esp.min.s32.a(i32 1, i32 14) + tail call void @llvm.riscv.esp.min.s8.a(i32 0, i32 1) + tail call void @llvm.riscv.esp.min.u16.a(i32 3, i32 14) + tail call void @llvm.riscv.esp.min.u32.a(i32 0, i32 9) + tail call void @llvm.riscv.esp.min.u8.a(i32 5, i32 8) + tail call void @llvm.riscv.esp.vabs.16(i32 0, i32 6) + tail call void @llvm.riscv.esp.vabs.32(i32 4, i32 1) + tail call void @llvm.riscv.esp.vabs.8(i32 2, i32 5) + tail call void @llvm.riscv.esp.vadd.s16(i32 1, i32 5, i32 6) + tail call void @llvm.riscv.esp.vadd.s16.ld.incp(i32 0, i32 6, i32 10, i32 1, i32 0) + tail call void @llvm.riscv.esp.vadd.s16.st.incp(i32 0, i32 4, i32 1, i32 11, i32 7) + tail call void @llvm.riscv.esp.vadd.s32(i32 7, i32 3, i32 7) + tail call void @llvm.riscv.esp.vadd.s32.ld.incp(i32 7, i32 2, i32 14, i32 4, i32 4) + tail call void @llvm.riscv.esp.vadd.s32.st.incp(i32 1, i32 7, i32 2, i32 13, i32 7) + tail call void @llvm.riscv.esp.vadd.s8(i32 1, i32 7, i32 7) + tail call void @llvm.riscv.esp.vadd.s8.ld.incp(i32 5, i32 6, i32 14, i32 1, i32 2) + tail call void @llvm.riscv.esp.vadd.s8.st.incp(i32 1, i32 0, i32 3, i32 9, i32 4) + tail call void @llvm.riscv.esp.vadd.u16(i32 7, i32 7, i32 0) + tail call void @llvm.riscv.esp.vadd.u16.ld.incp(i32 7, i32 5, i32 8, i32 1, i32 6) + tail call void @llvm.riscv.esp.vadd.u16.st.incp(i32 6, i32 3, i32 0, i32 5, i32 7) + tail call void @llvm.riscv.esp.vadd.u32(i32 0, i32 1, i32 4) + tail call void @llvm.riscv.esp.vadd.u32.ld.incp(i32 5, i32 0, i32 2, i32 4, i32 1) + tail call void @llvm.riscv.esp.vadd.u32.st.incp(i32 0, i32 1, i32 4, i32 1, i32 6) + tail call void @llvm.riscv.esp.vadd.u8(i32 2, i32 5, i32 5) + tail call void @llvm.riscv.esp.vadd.u8.ld.incp(i32 4, i32 3, i32 8, i32 1, i32 7) + tail call void @llvm.riscv.esp.vadd.u8.st.incp(i32 0, i32 0, i32 0, i32 5, i32 2) + tail call void @llvm.riscv.esp.vclamp.s16(i32 5, i32 14, i32 4) + tail call void @llvm.riscv.esp.vmax.s16(i32 6, i32 5, i32 5) + tail call void @llvm.riscv.esp.vmax.s16.ld.incp(i32 5, i32 5, i32 11, i32 3, i32 2) + tail call void @llvm.riscv.esp.vmax.s16.st.incp(i32 3, i32 5, i32 3, i32 2, i32 4) + tail call void @llvm.riscv.esp.vmax.s32(i32 5, i32 2, i32 2) + tail call void @llvm.riscv.esp.vmax.s32.ld.incp(i32 0, i32 1, i32 7, i32 6, i32 0) + tail call void @llvm.riscv.esp.vmax.s32.st.incp(i32 7, i32 6, i32 6, i32 14, i32 1) + tail call void @llvm.riscv.esp.vmax.s8(i32 5, i32 7, i32 7) + tail call void @llvm.riscv.esp.vmax.s8.ld.incp(i32 5, i32 1, i32 2, i32 1, i32 6) + tail call void @llvm.riscv.esp.vmax.s8.st.incp(i32 1, i32 3, i32 5, i32 4, i32 7) + tail call void @llvm.riscv.esp.vmax.u16(i32 4, i32 1, i32 1) + tail call void @llvm.riscv.esp.vmax.u16.ld.incp(i32 5, i32 4, i32 0, i32 5, i32 3) + tail call void @llvm.riscv.esp.vmax.u16.st.incp(i32 0, i32 7, i32 5, i32 11, i32 5) + tail call void @llvm.riscv.esp.vmax.u32(i32 0, i32 2, i32 4) + tail call void @llvm.riscv.esp.vmax.u32.ld.incp(i32 0, i32 6, i32 4, i32 1, i32 6) + tail call void @llvm.riscv.esp.vmax.u32.st.incp(i32 4, i32 7, i32 0, i32 6, i32 1) + tail call void @llvm.riscv.esp.vmax.u8(i32 2, i32 0, i32 5) + tail call void @llvm.riscv.esp.vmax.u8.ld.incp(i32 6, i32 1, i32 1, i32 5, i32 0) + tail call void @llvm.riscv.esp.vmax.u8.st.incp(i32 6, i32 7, i32 7, i32 10, i32 1) + tail call void @llvm.riscv.esp.vmin.s16(i32 1, i32 3, i32 4) + tail call void @llvm.riscv.esp.vmin.s16.ld.incp(i32 2, i32 1, i32 3, i32 2, i32 2) + tail call void @llvm.riscv.esp.vmin.s16.st.incp(i32 7, i32 6, i32 2, i32 7, i32 1) + tail call void @llvm.riscv.esp.vmin.s32(i32 0, i32 3, i32 2) + tail call void @llvm.riscv.esp.vmin.s32.ld.incp(i32 7, i32 6, i32 14, i32 5, i32 1) + tail call void @llvm.riscv.esp.vmin.s32.st.incp(i32 5, i32 1, i32 7, i32 6, i32 5) + tail call void @llvm.riscv.esp.vmin.s8(i32 3, i32 6, i32 2) + tail call void @llvm.riscv.esp.vmin.s8.ld.incp(i32 4, i32 3, i32 11, i32 1, i32 7) + tail call void @llvm.riscv.esp.vmin.s8.st.incp(i32 0, i32 1, i32 1, i32 6, i32 4) + tail call void @llvm.riscv.esp.vmin.u16(i32 3, i32 7, i32 4) + tail call void @llvm.riscv.esp.vmin.u16.ld.incp(i32 6, i32 6, i32 11, i32 5, i32 4) + tail call void @llvm.riscv.esp.vmin.u16.st.incp(i32 6, i32 0, i32 1, i32 12, i32 2) + tail call void @llvm.riscv.esp.vmin.u32(i32 0, i32 7, i32 5) + tail call void @llvm.riscv.esp.vmin.u32.ld.incp(i32 5, i32 6, i32 13, i32 6, i32 7) + tail call void @llvm.riscv.esp.vmin.u32.st.incp(i32 3, i32 7, i32 5, i32 4, i32 4) + tail call void @llvm.riscv.esp.vmin.u8(i32 5, i32 5, i32 7) + tail call void @llvm.riscv.esp.vmin.u8.ld.incp(i32 0, i32 5, i32 0, i32 5, i32 2) + tail call void @llvm.riscv.esp.vmin.u8.st.incp(i32 6, i32 6, i32 2, i32 12, i32 1) + tail call void @llvm.riscv.esp.vmul.s16(i32 2, i32 1, i32 6) + tail call void @llvm.riscv.esp.vmul.s16.ld.incp(i32 6, i32 7, i32 10, i32 3, i32 0) + tail call void @llvm.riscv.esp.vmul.s16.s8xs8(i32 3, i32 5, i32 7, i32 0) + tail call void @llvm.riscv.esp.vmul.s16.st.incp(i32 7, i32 1, i32 2, i32 3, i32 0) + tail call void @llvm.riscv.esp.vmul.s32.s16xs16(i32 5, i32 2, i32 3, i32 4) + tail call void @llvm.riscv.esp.vmul.s8(i32 4, i32 0, i32 3) + tail call void @llvm.riscv.esp.vmul.s8.ld.incp(i32 2, i32 3, i32 0, i32 2, i32 0) + tail call void @llvm.riscv.esp.vmul.s8.st.incp(i32 0, i32 7, i32 0, i32 8, i32 3) + tail call void @llvm.riscv.esp.vmul.u16(i32 3, i32 7, i32 2) + tail call void @llvm.riscv.esp.vmul.u16.ld.incp(i32 6, i32 6, i32 7, i32 5, i32 5) + tail call void @llvm.riscv.esp.vmul.u16.st.incp(i32 4, i32 4, i32 3, i32 3, i32 2) + tail call void @llvm.riscv.esp.vmul.u8(i32 3, i32 7, i32 7) + tail call void @llvm.riscv.esp.vmul.u8.ld.incp(i32 0, i32 6, i32 9, i32 1, i32 0) + tail call void @llvm.riscv.esp.vmul.u8.st.incp(i32 0, i32 3, i32 7, i32 6, i32 4) + tail call void @llvm.riscv.esp.vprelu.s16(i32 8, i32 3, i32 4, i32 1) + tail call void @llvm.riscv.esp.vprelu.s8(i32 3, i32 5, i32 4, i32 2) + tail call void @llvm.riscv.esp.vrelu.s16(i32 8, i32 9, i32 6) + tail call void @llvm.riscv.esp.vrelu.s8(i32 12, i32 1, i32 5) + tail call void @llvm.riscv.esp.vsadds.s16(i32 12, i32 3, i32 3) + tail call void @llvm.riscv.esp.vsadds.s8(i32 7, i32 1, i32 7) + tail call void @llvm.riscv.esp.vsadds.u16(i32 4, i32 2, i32 3) + tail call void @llvm.riscv.esp.vsadds.u8(i32 8, i32 3, i32 2) + tail call void @llvm.riscv.esp.vsat.s16(i32 9, i32 1, i32 0, i32 5) + tail call void @llvm.riscv.esp.vsat.s32(i32 12, i32 9, i32 3, i32 3) + tail call void @llvm.riscv.esp.vsat.s8(i32 10, i32 2, i32 7, i32 0) + tail call void @llvm.riscv.esp.vsat.u16(i32 7, i32 7, i32 7, i32 3) + tail call void @llvm.riscv.esp.vsat.u32(i32 8, i32 2, i32 5, i32 3) + tail call void @llvm.riscv.esp.vsat.u8(i32 1, i32 13, i32 6, i32 0) + tail call void @llvm.riscv.esp.vssubs.s16(i32 3, i32 7, i32 3) + tail call void @llvm.riscv.esp.vssubs.s8(i32 14, i32 0, i32 7) + tail call void @llvm.riscv.esp.vssubs.u16(i32 0, i32 4, i32 5) + tail call void @llvm.riscv.esp.vssubs.u8(i32 11, i32 1, i32 5) + tail call void @llvm.riscv.esp.vsub.s16(i32 0, i32 6, i32 0) + tail call void @llvm.riscv.esp.vsub.s16.ld.incp(i32 3, i32 7, i32 6, i32 2, i32 2) + tail call void @llvm.riscv.esp.vsub.s16.st.incp(i32 0, i32 3, i32 7, i32 0, i32 0) + tail call void @llvm.riscv.esp.vsub.s32(i32 2, i32 7, i32 7) + tail call void @llvm.riscv.esp.vsub.s32.ld.incp(i32 2, i32 0, i32 7, i32 3, i32 4) + tail call void @llvm.riscv.esp.vsub.s32.st.incp(i32 1, i32 1, i32 4, i32 5, i32 1) + tail call void @llvm.riscv.esp.vsub.s8(i32 5, i32 6, i32 7) + tail call void @llvm.riscv.esp.vsub.s8.ld.incp(i32 2, i32 6, i32 1, i32 1, i32 4) + tail call void @llvm.riscv.esp.vsub.s8.st.incp(i32 2, i32 3, i32 5, i32 4, i32 4) + tail call void @llvm.riscv.esp.vsub.u16(i32 7, i32 0, i32 5) + tail call void @llvm.riscv.esp.vsub.u16.ld.incp(i32 7, i32 5, i32 11, i32 0, i32 4) + tail call void @llvm.riscv.esp.vsub.u16.st.incp(i32 3, i32 1, i32 0, i32 11, i32 1) + tail call void @llvm.riscv.esp.vsub.u32(i32 4, i32 2, i32 5) + tail call void @llvm.riscv.esp.vsub.u32.ld.incp(i32 4, i32 2, i32 0, i32 2, i32 4) + tail call void @llvm.riscv.esp.vsub.u32.st.incp(i32 7, i32 4, i32 0, i32 11, i32 7) + tail call void @llvm.riscv.esp.vsub.u8(i32 5, i32 4, i32 6) + tail call void @llvm.riscv.esp.vsub.u8.ld.incp(i32 2, i32 4, i32 0, i32 6, i32 4) + tail call void @llvm.riscv.esp.vsub.u8.st.incp(i32 2, i32 0, i32 3, i32 11, i32 3) + tail call void @llvm.riscv.esp.addx2(i32 5, i32 14, i32 4) + tail call void @llvm.riscv.esp.addx4(i32 14, i32 5, i32 4) + tail call void @llvm.riscv.esp.sat(i32 6, i32 2, i32 4) + tail call void @llvm.riscv.esp.subx2(i32 2, i32 2, i32 9) + tail call void @llvm.riscv.esp.subx4(i32 0, i32 9, i32 3) + tail call void @llvm.riscv.esp.andq(i32 6, i32 3, i32 7) + tail call void @llvm.riscv.esp.notq(i32 5, i32 6) + tail call void @llvm.riscv.esp.orq(i32 1, i32 0, i32 1) + tail call void @llvm.riscv.esp.xorq(i32 1, i32 6, i32 5) + tail call void @llvm.riscv.esp.vcmp.eq.s16(i32 0, i32 2, i32 1) + tail call void @llvm.riscv.esp.vcmp.eq.s32(i32 1, i32 6, i32 5) + tail call void @llvm.riscv.esp.vcmp.eq.s8(i32 0, i32 3, i32 2) + tail call void @llvm.riscv.esp.vcmp.eq.u16(i32 7, i32 1, i32 7) + tail call void @llvm.riscv.esp.vcmp.eq.u32(i32 1, i32 2, i32 2) + tail call void @llvm.riscv.esp.vcmp.eq.u8(i32 1, i32 6, i32 3) + tail call void @llvm.riscv.esp.vcmp.gt.s16(i32 5, i32 6, i32 4) + tail call void @llvm.riscv.esp.vcmp.gt.s32(i32 6, i32 2, i32 0) + tail call void @llvm.riscv.esp.vcmp.gt.s8(i32 3, i32 5, i32 2) + tail call void @llvm.riscv.esp.vcmp.gt.u16(i32 7, i32 4, i32 7) + tail call void @llvm.riscv.esp.vcmp.gt.u32(i32 6, i32 2, i32 2) + tail call void @llvm.riscv.esp.vcmp.gt.u8(i32 2, i32 0, i32 0) + tail call void @llvm.riscv.esp.vcmp.lt.s16(i32 2, i32 1, i32 7) + tail call void @llvm.riscv.esp.vcmp.lt.s32(i32 2, i32 1, i32 4) + tail call void @llvm.riscv.esp.vcmp.lt.s8(i32 5, i32 2, i32 6) + tail call void @llvm.riscv.esp.vcmp.lt.u16(i32 1, i32 5, i32 4) + tail call void @llvm.riscv.esp.vcmp.lt.u32(i32 5, i32 6, i32 2) + tail call void @llvm.riscv.esp.vcmp.lt.u8(i32 3, i32 5, i32 5) + tail call void @llvm.riscv.esp.mov.s16.qacc(i32 2) + tail call void @llvm.riscv.esp.mov.s8.qacc(i32 5) + tail call void @llvm.riscv.esp.mov.u16.qacc(i32 5) + tail call void @llvm.riscv.esp.mov.u8.qacc(i32 3) + tail call void @llvm.riscv.esp.movi.16.a(i32 2, i32 3, i32 1) + tail call void @llvm.riscv.esp.movi.16.q(i32 7, i32 13, i32 3) + tail call void @llvm.riscv.esp.movi.32.a(i32 6, i32 1, i32 14) + tail call void @llvm.riscv.esp.movi.32.q(i32 9, i32 1, i32 5) + tail call void @llvm.riscv.esp.movi.8.a(i32 5, i32 15, i32 14) + tail call void @llvm.riscv.esp.movi.8.q(i32 0, i32 6, i32 1) + tail call void @llvm.riscv.esp.movx.r.cfg(i32 5) + tail call void @llvm.riscv.esp.movx.r.fft.bit.width(i32 2) + tail call void @llvm.riscv.esp.movx.r.perf(i32 3, i32 33) + tail call void @llvm.riscv.esp.movx.r.sar(i32 5) + tail call void @llvm.riscv.esp.movx.r.sar.bytes(i32 6) + tail call void @llvm.riscv.esp.movx.r.xacc.h(i32 10) + tail call void @llvm.riscv.esp.movx.r.xacc.l(i32 12) + tail call void @llvm.riscv.esp.movx.w.cfg(i32 10) + tail call void @llvm.riscv.esp.movx.w.fft.bit.width(i32 1) + tail call void @llvm.riscv.esp.movx.w.perf(i32 8) + tail call void @llvm.riscv.esp.movx.w.sar(i32 3) + tail call void @llvm.riscv.esp.movx.w.sar.bytes(i32 4) + tail call void @llvm.riscv.esp.movx.w.xacc.h(i32 8) + tail call void @llvm.riscv.esp.movx.w.xacc.l(i32 4) + tail call void @llvm.riscv.esp.vext.s16(i32 6, i32 7, i32 0) + tail call void @llvm.riscv.esp.vext.s8(i32 3, i32 5, i32 3) + tail call void @llvm.riscv.esp.vext.u16(i32 6, i32 4, i32 2) + tail call void @llvm.riscv.esp.vext.u8(i32 0, i32 4, i32 0) + tail call void @llvm.riscv.esp.vunzip.16(i32 1, i32 0) + tail call void @llvm.riscv.esp.vunzip.32(i32 6, i32 4) + tail call void @llvm.riscv.esp.vunzip.8(i32 2, i32 1) + tail call void @llvm.riscv.esp.vunzipt.16(i32 7, i32 0, i32 2) + tail call void @llvm.riscv.esp.vunzipt.8(i32 0, i32 6, i32 2) + tail call void @llvm.riscv.esp.vzip.16(i32 1, i32 6) + tail call void @llvm.riscv.esp.vzip.32(i32 4, i32 6) + tail call void @llvm.riscv.esp.vzip.8(i32 4, i32 0) + tail call void @llvm.riscv.esp.vzipt.16(i32 0, i32 3, i32 5) + tail call void @llvm.riscv.esp.vzipt.8(i32 6, i32 1, i32 5) + tail call void @llvm.riscv.esp.zero.q(i32 5) + tail call void @llvm.riscv.esp.zero.qacc() + tail call void @llvm.riscv.esp.zero.xacc() + tail call void @llvm.riscv.esp.fft.ams.s16.ld.incp(i32 3, i32 1, i32 0, i32 3, i32 0, i32 6, i32 6, i32 0) + tail call void @llvm.riscv.esp.fft.ams.s16.ld.incp.uaup(i32 3, i32 0, i32 1, i32 5, i32 0, i32 3, i32 0, i32 2) + tail call void @llvm.riscv.esp.fft.ams.s16.ld.r32.decp(i32 3, i32 5, i32 1, i32 3, i32 1, i32 7, i32 0, i32 6) + tail call void @llvm.riscv.esp.fft.ams.s16.st.incp(i32 5, i32 6, i32 3, i32 5, i32 4, i32 2, i32 0, i32 7) + tail call void @llvm.riscv.esp.fft.bitrev(i32 2, i32 7) + tail call void @llvm.riscv.esp.fft.cmul.s16.ld.xp(i32 1, i32 7, i32 7, i32 4, i32 1, i32 3, i32 2) + tail call void @llvm.riscv.esp.fft.cmul.s16.st.xp(i32 2, i32 0, i32 7, i32 4, i32 4, i32 1, i32 3, i32 4) + tail call void @llvm.riscv.esp.fft.r2bf.s16(i32 5, i32 1, i32 0, i32 7, i32 3) + tail call void @llvm.riscv.esp.fft.r2bf.s16.st.incp(i32 7, i32 4, i32 10, i32 2, i32 7) + tail call void @llvm.riscv.esp.fft.vst.r32.decp(i32 5, i32 7, i32 1) + tail call void @llvm.riscv.esp.ld.128.usar.ip(i32 4, i32 608, i32 1) + tail call void @llvm.riscv.esp.ld.128.usar.xp(i32 8, i32 1, i32 2) + tail call void @llvm.riscv.esp.ld.xacc.ip(i32 6, i32 400) + tail call void @llvm.riscv.esp.ldqa.s16.128.ip(i32 13, i32 912) + tail call void @llvm.riscv.esp.ldqa.s16.128.xp(i32 10, i32 2) + tail call void @llvm.riscv.esp.ldqa.s8.128.ip(i32 1, i32 1824) + tail call void @llvm.riscv.esp.ldqa.s8.128.xp(i32 4, i32 9) + tail call void @llvm.riscv.esp.ldqa.u16.128.ip(i32 4, i32 -1904) + tail call void @llvm.riscv.esp.ldqa.u16.128.xp(i32 14, i32 6) + tail call void @llvm.riscv.esp.ldqa.u8.128.ip(i32 3, i32 1216) + tail call void @llvm.riscv.esp.ldqa.u8.128.xp(i32 6, i32 2) + tail call void @llvm.riscv.esp.vldbc.16.ip(i32 9, i32 -448, i32 7) + tail call void @llvm.riscv.esp.vldbc.16.xp(i32 9, i32 5, i32 3) + tail call void @llvm.riscv.esp.vldbc.32.ip(i32 0, i32 220, i32 3) + tail call void @llvm.riscv.esp.vldbc.32.xp(i32 2, i32 12, i32 7) + tail call void @llvm.riscv.esp.vldbc.8.ip(i32 12, i32 396, i32 2) + tail call void @llvm.riscv.esp.vldbc.8.xp(i32 9, i32 4, i32 7) + tail call void @llvm.riscv.esp.vldext.s16.ip(i32 13, i32 16, i32 7, i32 4) + tail call void @llvm.riscv.esp.vldext.s16.xp(i32 8, i32 0, i32 5, i32 0) + tail call void @llvm.riscv.esp.vldext.s8.ip(i32 4, i32 80, i32 3, i32 6) + tail call void @llvm.riscv.esp.vldext.s8.xp(i32 6, i32 3, i32 1, i32 1) + tail call void @llvm.riscv.esp.vldext.u16.ip(i32 14, i32 48, i32 2, i32 5) + tail call void @llvm.riscv.esp.vldext.u16.xp(i32 12, i32 7, i32 2, i32 0) + tail call void @llvm.riscv.esp.vldext.u8.ip(i32 13, i32 64, i32 7, i32 2) + tail call void @llvm.riscv.esp.vldext.u8.xp(i32 6, i32 6, i32 7, i32 2) + tail call void @llvm.riscv.esp.vldhbc.16.incp(i32 1, i32 4, i32 7) + tail call void @llvm.riscv.esp.ld.qacc.h.h.128.ip(i32 6, i32 512) + tail call void @llvm.riscv.esp.ld.qacc.h.l.128.ip(i32 5, i32 -784) + tail call void @llvm.riscv.esp.ld.qacc.l.h.128.ip(i32 10, i32 -800) + tail call void @llvm.riscv.esp.ld.qacc.l.l.128.ip(i32 10, i32 -1952) + tail call void @llvm.riscv.esp.ld.ua.state.ip(i32 8, i32 -752) + tail call void @llvm.riscv.esp.ldxq.32(i32 0, i32 4, i32 2, i32 4, i32 7) + tail call void @llvm.riscv.esp.st.qacc.h.h.128.ip(i32 13, i32 -336) + tail call void @llvm.riscv.esp.st.qacc.h.l.128.ip(i32 8, i32 1568) + tail call void @llvm.riscv.esp.st.qacc.l.h.128.ip(i32 4, i32 16) + tail call void @llvm.riscv.esp.st.qacc.l.l.128.ip(i32 8, i32 416) + tail call void @llvm.riscv.esp.st.ua.state.ip(i32 7, i32 -1360) + tail call void @llvm.riscv.esp.stxq.32(i32 6, i32 6, i32 0, i32 2, i32 5) + tail call void @llvm.riscv.esp.vld.128.ip(i32 8, i32 784, i32 3) + tail call void @llvm.riscv.esp.vld.128.xp(i32 9, i32 7, i32 3) + tail call void @llvm.riscv.esp.vld.h.64.ip(i32 0, i32 -352, i32 0) + tail call void @llvm.riscv.esp.vld.h.64.xp(i32 14, i32 2, i32 2) + tail call void @llvm.riscv.esp.vld.l.64.ip(i32 6, i32 56, i32 2) + tail call void @llvm.riscv.esp.vld.l.64.xp(i32 1, i32 9, i32 5) + tail call void @llvm.riscv.esp.vst.128.ip(i32 5, i32 6, i32 -960) + tail call void @llvm.riscv.esp.vst.128.xp(i32 7, i32 6, i32 13) + tail call void @llvm.riscv.esp.vst.h.64.ip(i32 7, i32 4, i32 944) + tail call void @llvm.riscv.esp.vst.h.64.xp(i32 10, i32 7, i32 7) + tail call void @llvm.riscv.esp.vst.l.64.ip(i32 5, i32 3, i32 984) + tail call void @llvm.riscv.esp.vst.l.64.xp(i32 12, i32 5, i32 3) + tail call void @llvm.riscv.esp.slci.2q(i32 1, i32 5, i32 12) + tail call void @llvm.riscv.esp.slcxxp.2q(i32 5, i32 5, i32 2, i32 3) + tail call void @llvm.riscv.esp.src.q(i32 3, i32 1, i32 2) + tail call void @llvm.riscv.esp.src.q.ld.ip(i32 5, i32 0, i32 5, i32 -272, i32 0) + tail call void @llvm.riscv.esp.src.q.ld.xp(i32 3, i32 6, i32 12, i32 7, i32 1) + tail call void @llvm.riscv.esp.src.q.qup(i32 4, i32 7, i32 3) + tail call void @llvm.riscv.esp.srci.2q(i32 2, i32 3, i32 7) + tail call void @llvm.riscv.esp.srcmb.s16.q.qacc(i32 4, i32 0, i32 2) + tail call void @llvm.riscv.esp.srcmb.s16.qacc(i32 13, i32 1, i32 5) + tail call void @llvm.riscv.esp.srcmb.s8.q.qacc(i32 4, i32 0, i32 5) + tail call void @llvm.riscv.esp.srcmb.s8.qacc(i32 8, i32 1, i32 1) + tail call void @llvm.riscv.esp.srcmb.u16.q.qacc(i32 3, i32 1, i32 0) + tail call void @llvm.riscv.esp.srcmb.u16.qacc(i32 13, i32 0, i32 7) + tail call void @llvm.riscv.esp.srcmb.u8.q.qacc(i32 5, i32 1, i32 3) + tail call void @llvm.riscv.esp.srcmb.u8.qacc(i32 5, i32 0, i32 0) + tail call void @llvm.riscv.esp.srcq.128.st.incp(i32 5, i32 0, i32 12) + tail call void @llvm.riscv.esp.srcxxp.2q(i32 12, i32 6, i32 4, i32 6) + tail call void @llvm.riscv.esp.srs.s.xacc(i32 6, i32 13) + tail call void @llvm.riscv.esp.srs.u.xacc(i32 3, i32 12) + tail call void @llvm.riscv.esp.vsl.32(i32 2, i32 5) + tail call void @llvm.riscv.esp.vsld.16(i32 3, i32 7, i32 3) + tail call void @llvm.riscv.esp.vsld.32(i32 7, i32 1, i32 3) + tail call void @llvm.riscv.esp.vsld.8(i32 1, i32 5, i32 0) + tail call void @llvm.riscv.esp.vsr.s32(i32 0, i32 3) + tail call void @llvm.riscv.esp.vsr.u32(i32 2, i32 1) + tail call void @llvm.riscv.esp.vsrd.16(i32 3, i32 0, i32 4) + tail call void @llvm.riscv.esp.vsrd.32(i32 6, i32 3, i32 0) + tail call void @llvm.riscv.esp.vsrd.8(i32 4, i32 1, i32 5) + tail call void @llvm.riscv.esp.st.s.xacc.ip(i32 8, i32 80) + tail call void @llvm.riscv.esp.st.u.xacc.ip(i32 6, i32 -464) + ret void +} + +declare void @llvm.riscv.esp.vcmulas.s16.qacc.h(i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s16.qacc.h.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s16.qacc.h.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s16.qacc.l(i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s16.qacc.l.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s16.qacc.l.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s8.qacc.h(i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s8.qacc.h.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s8.qacc.h.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s8.qacc.l(i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s8.qacc.l.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmulas.s8.qacc.l.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.qacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.qacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.qacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.qacc.st.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.qacc.st.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.xacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.xacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.xacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.xacc.st.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.xacc.st.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.qacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.qacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.qacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.qacc.st.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.qacc.st.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.xacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.xacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.xacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.xacc.st.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.xacc.st.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.qacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.qacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.qacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.qacc.st.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.qacc.st.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.xacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.xacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.xacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.xacc.st.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.xacc.st.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.qacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.qacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.qacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.qacc.st.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.qacc.st.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.xacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.xacc.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.xacc.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.xacc.st.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.xacc.st.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s16.qacc.ldbc.incp(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.s8.qacc.ldbc.incp(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u16.qacc.ldbc.incp(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmulas.u8.qacc.ldbc.incp(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsmulas.s16.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsmulas.s16.qacc.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsmulas.s8.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsmulas.s8.qacc.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsmulas.u16.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsmulas.u16.qacc.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsmulas.u8.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsmulas.u8.qacc.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.s16(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.s16.ld.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.s16.st.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.s8(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.s8.ld.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.s8.st.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.u16(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.u16.ld.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.u16.st.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.u8(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.u8.ld.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.cmul.u8.st.incp(i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.max.s16.a(i32, i32) nounwind +declare void @llvm.riscv.esp.max.s32.a(i32, i32) nounwind +declare void @llvm.riscv.esp.max.s8.a(i32, i32) nounwind +declare void @llvm.riscv.esp.max.u16.a(i32, i32) nounwind +declare void @llvm.riscv.esp.max.u32.a(i32, i32) nounwind +declare void @llvm.riscv.esp.max.u8.a(i32, i32) nounwind +declare void @llvm.riscv.esp.min.s16.a(i32, i32) nounwind +declare void @llvm.riscv.esp.min.s32.a(i32, i32) nounwind +declare void @llvm.riscv.esp.min.s8.a(i32, i32) nounwind +declare void @llvm.riscv.esp.min.u16.a(i32, i32) nounwind +declare void @llvm.riscv.esp.min.u32.a(i32, i32) nounwind +declare void @llvm.riscv.esp.min.u8.a(i32, i32) nounwind +declare void @llvm.riscv.esp.vabs.16(i32, i32) nounwind +declare void @llvm.riscv.esp.vabs.32(i32, i32) nounwind +declare void @llvm.riscv.esp.vabs.8(i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vadd.u8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vclamp.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmax.u8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmin.u8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.s16.s8xs8(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.s32.s16xs16(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.u16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.u16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.u8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vmul.u8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vprelu.s16(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vprelu.s8(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vrelu.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vrelu.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsadds.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsadds.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsadds.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsadds.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsat.s16(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsat.s32(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsat.s8(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsat.u16(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsat.u32(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsat.u8(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vssubs.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vssubs.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vssubs.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vssubs.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.s8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u16.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u32.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u32.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u8.ld.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsub.u8.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.addx2(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.addx4(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.sat(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.subx2(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.subx4(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.andq(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.notq(i32, i32) nounwind +declare void @llvm.riscv.esp.orq(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.xorq(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.eq.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.eq.s32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.eq.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.eq.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.eq.u32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.eq.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.gt.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.gt.s32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.gt.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.gt.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.gt.u32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.gt.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.lt.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.lt.s32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.lt.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.lt.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.lt.u32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vcmp.lt.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.mov.s16.qacc(i32) nounwind +declare void @llvm.riscv.esp.mov.s8.qacc(i32) nounwind +declare void @llvm.riscv.esp.mov.u16.qacc(i32) nounwind +declare void @llvm.riscv.esp.mov.u8.qacc(i32) nounwind +declare void @llvm.riscv.esp.movi.16.a(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.movi.16.q(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.movi.32.a(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.movi.32.q(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.movi.8.a(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.movi.8.q(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.movx.r.cfg(i32) nounwind +declare void @llvm.riscv.esp.movx.r.fft.bit.width(i32) nounwind +declare void @llvm.riscv.esp.movx.r.perf(i32, i32) nounwind +declare void @llvm.riscv.esp.movx.r.sar(i32) nounwind +declare void @llvm.riscv.esp.movx.r.sar.bytes(i32) nounwind +declare void @llvm.riscv.esp.movx.r.xacc.h(i32) nounwind +declare void @llvm.riscv.esp.movx.r.xacc.l(i32) nounwind +declare void @llvm.riscv.esp.movx.w.cfg(i32) nounwind +declare void @llvm.riscv.esp.movx.w.fft.bit.width(i32) nounwind +declare void @llvm.riscv.esp.movx.w.perf(i32) nounwind +declare void @llvm.riscv.esp.movx.w.sar(i32) nounwind +declare void @llvm.riscv.esp.movx.w.sar.bytes(i32) nounwind +declare void @llvm.riscv.esp.movx.w.xacc.h(i32) nounwind +declare void @llvm.riscv.esp.movx.w.xacc.l(i32) nounwind +declare void @llvm.riscv.esp.vext.s16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vext.s8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vext.u16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vext.u8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vunzip.16(i32, i32) nounwind +declare void @llvm.riscv.esp.vunzip.32(i32, i32) nounwind +declare void @llvm.riscv.esp.vunzip.8(i32, i32) nounwind +declare void @llvm.riscv.esp.vunzipt.16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vunzipt.8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vzip.16(i32, i32) nounwind +declare void @llvm.riscv.esp.vzip.32(i32, i32) nounwind +declare void @llvm.riscv.esp.vzip.8(i32, i32) nounwind +declare void @llvm.riscv.esp.vzipt.16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vzipt.8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.zero.q(i32) nounwind +declare void @llvm.riscv.esp.zero.qacc() nounwind +declare void @llvm.riscv.esp.zero.xacc() nounwind +declare void @llvm.riscv.esp.fft.ams.s16.ld.incp(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.fft.ams.s16.ld.incp.uaup(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.fft.ams.s16.ld.r32.decp(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.fft.ams.s16.st.incp(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.fft.bitrev(i32, i32) nounwind +declare void @llvm.riscv.esp.fft.cmul.s16.ld.xp(i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.fft.cmul.s16.st.xp(i32, i32, i32, i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.fft.r2bf.s16(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.fft.r2bf.s16.st.incp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.fft.vst.r32.decp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.ld.128.usar.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.ld.128.usar.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.ld.xacc.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ldqa.s16.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ldqa.s16.128.xp(i32, i32) nounwind +declare void @llvm.riscv.esp.ldqa.s8.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ldqa.s8.128.xp(i32, i32) nounwind +declare void @llvm.riscv.esp.ldqa.u16.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ldqa.u16.128.xp(i32, i32) nounwind +declare void @llvm.riscv.esp.ldqa.u8.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ldqa.u8.128.xp(i32, i32) nounwind +declare void @llvm.riscv.esp.vldbc.16.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldbc.16.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldbc.32.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldbc.32.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldbc.8.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldbc.8.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldext.s16.ip(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldext.s16.xp(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldext.s8.ip(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldext.s8.xp(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldext.u16.ip(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldext.u16.xp(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldext.u8.ip(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldext.u8.xp(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vldhbc.16.incp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.ld.qacc.h.h.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ld.qacc.h.l.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ld.qacc.l.h.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ld.qacc.l.l.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ld.ua.state.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.ldxq.32(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.st.qacc.h.h.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.st.qacc.h.l.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.st.qacc.l.h.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.st.qacc.l.l.128.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.st.ua.state.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.stxq.32(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vld.128.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vld.128.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vld.h.64.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vld.h.64.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vld.l.64.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vld.l.64.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vst.128.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vst.128.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vst.h.64.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vst.h.64.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vst.l.64.ip(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vst.l.64.xp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.slci.2q(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.slcxxp.2q(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.src.q(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.src.q.ld.ip(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.src.q.ld.xp(i32, i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.src.q.qup(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srci.2q(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcmb.s16.q.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcmb.s16.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcmb.s8.q.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcmb.s8.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcmb.u16.q.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcmb.u16.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcmb.u8.q.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcmb.u8.qacc(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcq.128.st.incp(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srcxxp.2q(i32, i32, i32, i32) nounwind +declare void @llvm.riscv.esp.srs.s.xacc(i32, i32) nounwind +declare void @llvm.riscv.esp.srs.u.xacc(i32, i32) nounwind +declare void @llvm.riscv.esp.vsl.32(i32, i32) nounwind +declare void @llvm.riscv.esp.vsld.16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsld.32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsld.8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsr.s32(i32, i32) nounwind +declare void @llvm.riscv.esp.vsr.u32(i32, i32) nounwind +declare void @llvm.riscv.esp.vsrd.16(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsrd.32(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.vsrd.8(i32, i32, i32) nounwind +declare void @llvm.riscv.esp.st.s.xacc.ip(i32, i32) nounwind +declare void @llvm.riscv.esp.st.u.xacc.ip(i32, i32) nounwind diff --git a/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s b/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s new file mode 100644 index 00000000000000..f2d8e11550ec89 --- /dev/null +++ b/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s @@ -0,0 +1,22 @@ +# RUN: llvm-mc %s -triple=riscv32 -mcpu=esp32p4 -show-encoding | FileCheck -check-prefixes=CHECK %s + +dl_hwlp_test: +# CHECK: dl_hwlp_test: + esp.lp.setup 0, a1, loop_last_instruction +# CHECK: esp.lp.setup 0, a1, loop_last_instruction # encoding: [0x2b'A',0xc0'A',0x05'A',A] + esp.lp.starti 0, loop_last_instruction +# CHECK: esp.lp.starti 0, loop_last_instruction # encoding: [0x2b'A',A,A,A] + esp.lp.counti 0, 4000 +# CHECK: esp.lp.counti 0, 4000 # encoding: [0x2b,0x30,0x00,0xfa] + esp.lp.count 0, a1 +# CHECK: esp.lp.count 0, a1 # encoding: [0x2b,0x20,0x00,0x00] + esp.lp.setupi 0, 1234, loop_last_instruction +# CHECK: esp.lp.setupi 0, 1234, loop_last_instruction # encoding: [0x2b'A',0x50'A',0x20'A',0x4d'A'] + # lp.setup 0, a1, loop_last_instruction +# CHECK: # fixup A - offset: 0, value: loop_last_instruction, kind: fixup_riscv_branch + loop_last_instruction: +# CHECK: loop_last_instruction: + addi a0, a0, 1 +# CHECK: addi a0, a0, 1 # encoding: [0x05,0x05] + ret +# CHECK: ret # encoding: [0x82,0x80] diff --git a/llvm/test/MC/RISCV/esp32p4-valid.s b/llvm/test/MC/RISCV/esp32p4-valid.s new file mode 100644 index 00000000000000..d64dadffb322f1 --- /dev/null +++ b/llvm/test/MC/RISCV/esp32p4-valid.s @@ -0,0 +1,710 @@ +# RUN: llvm-mc %s -triple=riscv32 -mcpu=esp32p4 -show-encoding | FileCheck -check-prefixes=CHECK %s + +esp.vcmulas.s16.qacc.h q2, q2 +# CHECK: esp.vcmulas.s16.qacc.h q2, q2 # encoding: [0x5f,0x80,0x87,0x4a] +esp.vcmulas.s16.qacc.h.ld.ip q5, a3, -16, q0, q4 +# CHECK: esp.vcmulas.s16.qacc.h.ld.ip q5, a3, -16, q0, q4 # encoding: [0x3b,0xf7,0xfa,0x13] +esp.vcmulas.s16.qacc.h.ld.xp q0, a4, a5, q2, q3 +# CHECK: esp.vcmulas.s16.qacc.h.ld.xp q0, a4, a5, q2, q3 # encoding: [0x7f,0x20,0x73,0x4f] +esp.vcmulas.s16.qacc.l q3, q5 +# CHECK: esp.vcmulas.s16.qacc.l q3, q5 # encoding: [0x5f,0x80,0x83,0x76] +esp.vcmulas.s16.qacc.l.ld.ip q6, a1, -32, q6, q5 +# CHECK: esp.vcmulas.s16.qacc.l.ld.ip q6, a1, -32, q6, q5 # encoding: [0x3b,0xfb,0xf1,0xd5] +esp.vcmulas.s16.qacc.l.ld.xp q6, a2, a0, q4, q5 +# CHECK: esp.vcmulas.s16.qacc.l.ld.xp q6, a2, a0, q4, q5 # encoding: [0x7f,0x38,0x22,0x95] +esp.vcmulas.s8.qacc.h q4, q2 +# CHECK: esp.vcmulas.s8.qacc.h q4, q2 # encoding: [0x5f,0x80,0x85,0x8a] +esp.vcmulas.s8.qacc.h.ld.ip q5, a1, 96, q3, q4 +# CHECK: esp.vcmulas.s8.qacc.h.ld.ip q5, a1, 96, q3, q4 # encoding: [0x3b,0xf7,0xb1,0x72] +esp.vcmulas.s8.qacc.h.ld.xp q6, a1, a3, q1, q6 +# CHECK: esp.vcmulas.s8.qacc.h.ld.xp q6, a1, a3, q1, q6 # encoding: [0x7f,0xb8,0x51,0x3a] +esp.vcmulas.s8.qacc.l q0, q2 +# CHECK: esp.vcmulas.s8.qacc.l q0, q2 # encoding: [0x5f,0x80,0x81,0x0a] +esp.vcmulas.s8.qacc.l.ld.ip q4, a2, -128, q0, q2 +# CHECK: esp.vcmulas.s8.qacc.l.ld.ip q4, a2, -128, q0, q2 # encoding: [0x3b,0x73,0xc2,0x08] +esp.vcmulas.s8.qacc.l.ld.xp q0, a5, a1, q2, q2 +# CHECK: esp.vcmulas.s8.qacc.l.ld.xp q0, a5, a1, q2, q2 # encoding: [0x7f,0xa0,0x33,0x48] +esp.vmulas.s16.qacc q2, q3 +# CHECK: esp.vmulas.s16.qacc q2, q3 # encoding: [0x5f,0x00,0xc7,0x4e] +esp.vmulas.s16.qacc.ld.ip q1, a5, -112, q1, q4 +# CHECK: esp.vmulas.s16.qacc.ld.ip q1, a5, -112, q1, q4 # encoding: [0xbb,0xe6,0xe3,0x32] +esp.vmulas.s16.qacc.ld.xp q4, a4, a1, q6, q3 +# CHECK: esp.vmulas.s16.qacc.ld.xp q4, a4, a1, q6, q3 # encoding: [0xff,0x32,0x3b,0xce] +esp.vmulas.s16.qacc.st.ip q6, a5, -96, q5, q2 +# CHECK: esp.vmulas.s16.qacc.st.ip q6, a5, -96, q5, q2 # encoding: [0xbb,0xf8,0xeb,0xab] +esp.vmulas.s16.qacc.st.xp q4, a2, a5, q3, q1 +# CHECK: esp.vmulas.s16.qacc.st.xp q4, a2, a5, q3, q1 # encoding: [0xff,0x32,0x7a,0x67] +esp.vmulas.s16.xacc q5, q2 +# CHECK: esp.vmulas.s16.xacc q5, q2 # encoding: [0x5f,0x00,0xc3,0xaa] +esp.vmulas.s16.xacc.ld.ip q4, a3, 48, q3, q6 +# CHECK: esp.vmulas.s16.xacc.ld.ip q4, a3, 48, q3, q6 # encoding: [0xbb,0xf2,0xca,0x78] +esp.vmulas.s16.xacc.ld.xp q6, a2, a5, q0, q0 +# CHECK: esp.vmulas.s16.xacc.ld.xp q6, a2, a5, q0, q0 # encoding: [0xff,0x3a,0x7a,0x00] +esp.vmulas.s16.xacc.st.ip q1, a1, 16, q4, q3 +# CHECK: esp.vmulas.s16.xacc.st.ip q1, a1, 16, q4, q3 # encoding: [0xbb,0xe6,0xc1,0x8d] +esp.vmulas.s16.xacc.st.xp q2, a4, a0, q5, q0 +# CHECK: esp.vmulas.s16.xacc.st.xp q2, a4, a0, q5, q0 # encoding: [0xff,0x2a,0x2b,0xa1] +esp.vmulas.s8.qacc q4, q6 +# CHECK: esp.vmulas.s8.qacc q4, q6 # encoding: [0x5f,0x00,0xc5,0x9a] +esp.vmulas.s8.qacc.ld.ip q5, a2, 64, q5, q0 +# CHECK: esp.vmulas.s8.qacc.ld.ip q5, a2, 64, q5, q0 # encoding: [0xbb,0x74,0x52,0xa2] +esp.vmulas.s8.qacc.ld.xp q1, a1, a3, q5, q0 +# CHECK: esp.vmulas.s8.qacc.ld.xp q1, a1, a3, q5, q0 # encoding: [0xff,0xa6,0x51,0xa2] +esp.vmulas.s8.qacc.st.ip q5, a3, 16, q5, q1 +# CHECK: esp.vmulas.s8.qacc.st.ip q5, a3, 16, q5, q1 # encoding: [0xbb,0xf6,0x42,0xa7] +esp.vmulas.s8.qacc.st.xp q5, a1, a4, q4, q0 +# CHECK: esp.vmulas.s8.qacc.st.xp q5, a1, a4, q4, q0 # encoding: [0xff,0xb6,0x61,0x83] +esp.vmulas.s8.xacc q1, q0 +# CHECK: esp.vmulas.s8.xacc q1, q0 # encoding: [0x5f,0x00,0xc1,0x22] +esp.vmulas.s8.xacc.ld.ip q0, a4, 16, q4, q4 +# CHECK: esp.vmulas.s8.xacc.ld.ip q0, a4, 16, q4, q4 # encoding: [0xbb,0x62,0x43,0x90] +esp.vmulas.s8.xacc.ld.xp q0, a5, a2, q4, q2 +# CHECK: esp.vmulas.s8.xacc.ld.xp q0, a5, a2, q4, q2 # encoding: [0xff,0xa2,0x43,0x88] +esp.vmulas.s8.xacc.st.ip q3, a3, -32, q0, q5 +# CHECK: esp.vmulas.s8.xacc.st.ip q3, a3, -32, q0, q5 # encoding: [0xbb,0xec,0x7a,0x15] +esp.vmulas.s8.xacc.st.xp q0, a5, a4, q3, q3 +# CHECK: esp.vmulas.s8.xacc.st.xp q0, a5, a4, q3, q3 # encoding: [0xff,0xa2,0x63,0x6d] +esp.vmulas.u16.qacc q2, q0 +# CHECK: esp.vmulas.u16.qacc q2, q0 # encoding: [0x5f,0x00,0xc6,0x42] +esp.vmulas.u16.qacc.ld.ip q5, a4, 80, q1, q3 +# CHECK: esp.vmulas.u16.qacc.ld.ip q5, a4, 80, q1, q3 # encoding: [0xbb,0x76,0x93,0x2e] +esp.vmulas.u16.qacc.ld.xp q5, a5, a3, q6, q3 +# CHECK: esp.vmulas.u16.qacc.ld.xp q5, a5, a3, q6, q3 # encoding: [0xff,0xb4,0x5b,0xce] +esp.vmulas.u16.qacc.st.ip q5, a3, -80, q2, q0 +# CHECK: esp.vmulas.u16.qacc.st.ip q5, a3, -80, q2, q0 # encoding: [0xbb,0xf6,0xaa,0x43] +esp.vmulas.u16.qacc.st.xp q0, a2, a4, q5, q5 +# CHECK: esp.vmulas.u16.qacc.st.xp q0, a2, a4, q5, q5 # encoding: [0xff,0x20,0x6a,0xb7] +esp.vmulas.u16.xacc q2, q6 +# CHECK: esp.vmulas.u16.xacc q2, q6 # encoding: [0x5f,0x00,0xc2,0x5a] +esp.vmulas.u16.xacc.ld.ip q1, a3, 16, q5, q2 +# CHECK: esp.vmulas.u16.xacc.ld.ip q1, a3, 16, q5, q2 # encoding: [0xbb,0xe6,0x82,0xa8] +esp.vmulas.u16.xacc.ld.xp q2, a3, a4, q1, q3 +# CHECK: esp.vmulas.u16.xacc.ld.xp q2, a3, a4, q1, q3 # encoding: [0xff,0xa8,0x6a,0x2c] +esp.vmulas.u16.xacc.st.ip q3, a4, -112, q1, q3 +# CHECK: esp.vmulas.u16.xacc.st.ip q3, a4, -112, q1, q3 # encoding: [0xbb,0x6e,0xa3,0x2d] +esp.vmulas.u16.xacc.st.xp q4, a0, a2, q0, q3 +# CHECK: esp.vmulas.u16.xacc.st.xp q4, a0, a2, q0, q3 # encoding: [0xff,0x30,0x49,0x0d] +esp.vmulas.u8.qacc q6, q1 +# CHECK: esp.vmulas.u8.qacc q6, q1 # encoding: [0x5f,0x00,0xc4,0xc6] +esp.vmulas.u8.qacc.ld.ip q0, a4, -80, q0, q3 +# CHECK: esp.vmulas.u8.qacc.ld.ip q0, a4, -80, q0, q3 # encoding: [0xbb,0x62,0x2b,0x0e] +esp.vmulas.u8.qacc.ld.xp q0, a3, a0, q1, q3 +# CHECK: esp.vmulas.u8.qacc.ld.xp q0, a3, a0, q1, q3 # encoding: [0xff,0xa0,0x22,0x2e] +esp.vmulas.u8.qacc.st.ip q2, a3, 64, q0, q0 +# CHECK: esp.vmulas.u8.qacc.st.ip q2, a3, 64, q0, q0 # encoding: [0xbb,0xe8,0x12,0x03] +esp.vmulas.u8.qacc.st.xp q6, a2, a2, q3, q1 +# CHECK: esp.vmulas.u8.qacc.st.xp q6, a2, a2, q3, q1 # encoding: [0xff,0x38,0x42,0x67] +esp.vmulas.u8.xacc q3, q3 +# CHECK: esp.vmulas.u8.xacc q3, q3 # encoding: [0x5f,0x00,0xc0,0x6e] +esp.vmulas.u8.xacc.ld.ip q0, a5, 16, q0, q1 +# CHECK: esp.vmulas.u8.xacc.ld.ip q0, a5, 16, q0, q1 # encoding: [0xbb,0xe2,0x03,0x04] +esp.vmulas.u8.xacc.ld.xp q4, a0, a2, q1, q5 +# CHECK: esp.vmulas.u8.xacc.ld.xp q4, a0, a2, q1, q5 # encoding: [0xff,0x30,0x41,0x34] +esp.vmulas.u8.xacc.st.ip q4, a1, -48, q4, q6 +# CHECK: esp.vmulas.u8.xacc.st.ip q4, a1, -48, q4, q6 # encoding: [0xbb,0xf2,0x31,0x99] +esp.vmulas.u8.xacc.st.xp q4, a2, a3, q0, q2 +# CHECK: esp.vmulas.u8.xacc.st.xp q4, a2, a3, q0, q2 # encoding: [0xff,0x30,0x52,0x09] +esp.vmulas.s16.qacc.ldbc.incp q5, a2, q0, q6 +# CHECK: esp.vmulas.s16.qacc.ldbc.incp q5, a2, q0, q6 # encoding: [0xbb,0x75,0x62,0x18] +esp.vmulas.s8.qacc.ldbc.incp q3, a5, q4, q2 +# CHECK: esp.vmulas.s8.qacc.ldbc.incp q3, a5, q4, q2 # encoding: [0xbb,0xed,0x23,0x88] +esp.vmulas.u16.qacc.ldbc.incp q2, a1, q1, q3 +# CHECK: esp.vmulas.u16.qacc.ldbc.incp q2, a1, q1, q3 # encoding: [0xbb,0xe9,0x41,0x2c] +esp.vmulas.u8.qacc.ldbc.incp q0, a1, q2, q0 +# CHECK: esp.vmulas.u8.qacc.ldbc.incp q0, a1, q2, q0 # encoding: [0xbb,0xe1,0x01,0x40] +esp.vsmulas.s16.qacc q0, q5, 5 +# CHECK: esp.vsmulas.s16.qacc q0, q5, 5 # encoding: [0x5f,0x80,0xf2,0x16] +esp.vsmulas.s16.qacc.ld.incp q1, a2, q4, q2, 4 +# CHECK: esp.vsmulas.s16.qacc.ld.incp q1, a2, q4, q2, 4 # encoding: [0xbb,0x67,0xa2,0x8b] +esp.vsmulas.s8.qacc q2, q1, 13 +# CHECK: esp.vsmulas.s8.qacc q2, q1, 13 # encoding: [0x5f,0x80,0xb6,0x46] +esp.vsmulas.s8.qacc.ld.incp q2, a5, q1, q3, 0 +# CHECK: esp.vsmulas.s8.qacc.ld.incp q2, a5, q1, q3, 0 # encoding: [0xbb,0xeb,0x83,0x2d] +esp.vsmulas.u16.qacc q6, q1, 5 +# CHECK: esp.vsmulas.u16.qacc q6, q1, 5 # encoding: [0x5f,0x80,0xd2,0xc6] +esp.vsmulas.u16.qacc.ld.incp q0, a0, q6, q6, 0 +# CHECK: esp.vsmulas.u16.qacc.ld.incp q0, a0, q6, q6, 0 # encoding: [0xbb,0x63,0x81,0xda] +esp.vsmulas.u8.qacc q0, q3, 7 +# CHECK: esp.vsmulas.u8.qacc q0, q3, 7 # encoding: [0x5f,0x80,0x93,0x0e] +esp.vsmulas.u8.qacc.ld.incp q6, a0, q6, q5, 8 +# CHECK: esp.vsmulas.u8.qacc.ld.incp q6, a0, q6, q5, 8 # encoding: [0xbb,0x7b,0xc1,0xd4] +esp.cmul.s16 q0, q2, q4, 3 +# CHECK: esp.cmul.s16 q0, q2, q4, 3 # encoding: [0x5f,0xa4,0x07,0x50] +esp.cmul.s16.ld.incp q6, a4, q1, q1, q5, 0 +# CHECK: esp.cmul.s16.ld.incp q6, a4, q1, q1, q5, 0 # encoding: [0xbf,0x58,0xc3,0x34] +esp.cmul.s16.st.incp q4, a0, q0, q5, q0, 0 +# CHECK: esp.cmul.s16.st.incp q4, a0, q0, q5, q0, 0 # encoding: [0x3f,0x50,0xc1,0xa2] +esp.cmul.s8 q6, q1, q6, 2 +# CHECK: esp.cmul.s8 q6, q1, q6, 2 # encoding: [0x5f,0x27,0x03,0x38] +esp.cmul.s8.ld.incp q4, a3, q0, q4, q2, 3 +# CHECK: esp.cmul.s8.ld.incp q4, a3, q0, q4, q2, 3 # encoding: [0x3f,0xd0,0x72,0x88] +esp.cmul.s8.st.incp q5, a1, q5, q2, q0, 3 +# CHECK: esp.cmul.s8.st.incp q5, a1, q5, q2, q0, 3 # encoding: [0xbf,0xd6,0x71,0x42] +esp.cmul.u16 q2, q3, q5, 1 +# CHECK: esp.cmul.u16 q2, q3, q5, 1 # encoding: [0x5f,0xa5,0x04,0x74] +esp.cmul.u16.ld.incp q1, a1, q6, q5, q1, 0 +# CHECK: esp.cmul.u16.ld.incp q1, a1, q6, q5, q1, 0 # encoding: [0x3f,0xc7,0x81,0xa4] +esp.cmul.u16.st.incp q6, a1, q2, q2, q4, 0 +# CHECK: esp.cmul.u16.st.incp q6, a1, q2, q2, q4, 0 # encoding: [0x3f,0xd9,0x81,0x52] +esp.cmul.u8 q1, q4, q3, 3 +# CHECK: esp.cmul.u8 q1, q4, q3, 3 # encoding: [0xdf,0xa4,0x01,0x8c] +esp.cmul.u8.ld.incp q2, a5, q3, q0, q5, 1 +# CHECK: esp.cmul.u8.ld.incp q2, a5, q3, q0, q5, 1 # encoding: [0xbf,0xc9,0x13,0x14] +esp.cmul.u8.st.incp q4, a2, q0, q4, q4, 0 +# CHECK: esp.cmul.u8.st.incp q4, a2, q0, q4, q4, 0 # encoding: [0x3f,0x50,0x02,0x92] +esp.max.s16.a q5, a2 +# CHECK: esp.max.s16.a q5, a2 # encoding: [0x5b,0x52,0xc8,0x91] +esp.max.s32.a q5, a5 +# CHECK: esp.max.s32.a q5, a5 # encoding: [0xdb,0x53,0xa8,0x91] +esp.max.s8.a q2, a0 +# CHECK: esp.max.s8.a q2, a0 # encoding: [0x5b,0x51,0x40,0x92] +esp.max.u16.a q6, a3 +# CHECK: esp.max.u16.a q6, a3 # encoding: [0xdb,0x52,0x88,0x92] +esp.max.u32.a q0, a2 +# CHECK: esp.max.u32.a q0, a2 # encoding: [0x5b,0x52,0x20,0x90] +esp.max.u8.a q5, a0 +# CHECK: esp.max.u8.a q5, a0 # encoding: [0x5b,0x51,0x08,0x91] +esp.min.s16.a q0, a3 +# CHECK: esp.min.s16.a q0, a3 # encoding: [0xdb,0x52,0xd0,0x90] +esp.min.s32.a q1, a1 +# CHECK: esp.min.s32.a q1, a1 # encoding: [0xdb,0x51,0xb0,0x91] +esp.min.s8.a q3, a4 +# CHECK: esp.min.s8.a q3, a4 # encoding: [0x5b,0x53,0x50,0x93] +esp.min.u16.a q6, a0 +# CHECK: esp.min.u16.a q6, a0 # encoding: [0x5b,0x51,0x98,0x92] +esp.min.u32.a q2, a3 +# CHECK: esp.min.u32.a q2, a3 # encoding: [0xdb,0x52,0x30,0x92] +esp.min.u8.a q1, a3 +# CHECK: esp.min.u8.a q1, a3 # encoding: [0xdb,0x52,0x10,0x91] +esp.vabs.16 q5, q2 +# CHECK: esp.vabs.16 q5, q2 # encoding: [0x5b,0x10,0x50,0x88] +esp.vabs.32 q0, q3 +# CHECK: esp.vabs.32 q0, q3 # encoding: [0x5b,0x08,0x00,0x8c] +esp.vabs.8 q6, q1 +# CHECK: esp.vabs.8 q6, q1 # encoding: [0x5b,0x00,0x60,0x84] +esp.vadd.s16 q1, q0, q3 +# CHECK: esp.vadd.s16 q1, q0, q3 # encoding: [0x5f,0x06,0x94,0x0e] +esp.vadd.s16.ld.incp q2, a3, q4, q3, q1 +# CHECK: esp.vadd.s16.ld.incp q2, a3, q4, q3, q1 # encoding: [0x3b,0xe8,0x4a,0x65] +esp.vadd.s16.st.incp q6, a2, q1, q3, q1 +# CHECK: esp.vadd.s16.st.incp q6, a2, q1, q3, q1 # encoding: [0x3b,0x78,0x1a,0x67] +esp.vadd.s32 q2, q5, q3 +# CHECK: esp.vadd.s32 q2, q5, q3 # encoding: [0x5f,0x05,0xa4,0xae] +esp.vadd.s32.ld.incp q5, a0, q0, q6, q2 +# CHECK: esp.vadd.s32.ld.incp q5, a0, q0, q6, q2 # encoding: [0x3b,0x75,0x01,0xc9] +esp.vadd.s32.st.incp q5, a0, q2, q6, q1 +# CHECK: esp.vadd.s32.st.incp q5, a0, q2, q6, q1 # encoding: [0x3b,0x75,0x21,0xc7] +esp.vadd.s8 q6, q4, q1 +# CHECK: esp.vadd.s8 q6, q4, q1 # encoding: [0x5f,0x06,0xe0,0x86] +esp.vadd.s8.ld.incp q6, a0, q3, q0, q4 +# CHECK: esp.vadd.s8.ld.incp q6, a0, q3, q0, q4 # encoding: [0x3b,0x78,0x39,0x10] +esp.vadd.s8.st.incp q0, a5, q0, q0, q4 +# CHECK: esp.vadd.s8.st.incp q0, a5, q0, q0, q4 # encoding: [0x3b,0xe0,0x0b,0x12] +esp.vadd.u16 q3, q5, q0 +# CHECK: esp.vadd.u16 q3, q5, q0 # encoding: [0x5f,0x04,0xb4,0xa2] +esp.vadd.u16.ld.incp q6, a1, q4, q6, q4 +# CHECK: esp.vadd.u16.ld.incp q6, a1, q4, q6, q4 # encoding: [0x3b,0xf8,0x41,0xd1] +esp.vadd.u16.st.incp q5, a2, q4, q3, q5 +# CHECK: esp.vadd.u16.st.incp q5, a2, q4, q3, q5 # encoding: [0x3b,0x74,0x42,0x77] +esp.vadd.u32 q5, q2, q2 +# CHECK: esp.vadd.u32 q5, q2, q2 # encoding: [0x5f,0x05,0xd0,0x4a] +esp.vadd.u32.ld.incp q3, a0, q6, q1, q2 +# CHECK: esp.vadd.u32.ld.incp q3, a0, q6, q1, q2 # encoding: [0x3b,0x6d,0x61,0x28] +esp.vadd.u32.st.incp q1, a1, q2, q6, q6 +# CHECK: esp.vadd.u32.st.incp q1, a1, q2, q6, q6 # encoding: [0x3b,0xe5,0x21,0xda] +esp.vadd.u8 q0, q0, q3 +# CHECK: esp.vadd.u8 q0, q0, q3 # encoding: [0x5f,0x04,0x80,0x0e] +esp.vadd.u8.ld.incp q3, a1, q0, q0, q1 +# CHECK: esp.vadd.u8.ld.incp q3, a1, q0, q0, q1 # encoding: [0x3b,0xec,0x01,0x04] +esp.vadd.u8.st.incp q1, a1, q0, q4, q6 +# CHECK: esp.vadd.u8.st.incp q1, a1, q0, q4, q6 # encoding: [0x3b,0xe4,0x01,0x9a] +esp.vclamp.s16 q0, q5, 4 +# CHECK: esp.vclamp.s16 q0, q5, 4 # encoding: [0x5b,0x50,0x00,0xa1] +esp.vmax.s16 q4, q1, q2 +# CHECK: esp.vmax.s16 q4, q1, q2 # encoding: [0x5f,0xae,0x06,0x28] +esp.vmax.s16.ld.incp q3, a5, q3, q4, q4 +# CHECK: esp.vmax.s16.ld.incp q3, a5, q3, q4, q4 # encoding: [0xbf,0xcd,0x6b,0x90] +esp.vmax.s16.st.incp q4, a4, q0, q5, q6 +# CHECK: esp.vmax.s16.st.incp q4, a4, q0, q5, q6 # encoding: [0x3f,0x50,0xeb,0xb8] +esp.vmax.s32 q4, q0, q4 +# CHECK: esp.vmax.s32 q4, q0, q4 # encoding: [0x5f,0xae,0x05,0x10] +esp.vmax.s32.ld.incp q2, a0, q2, q2, q1 +# CHECK: esp.vmax.s32.ld.incp q2, a0, q2, q2, q1 # encoding: [0x3f,0x49,0x59,0x44] +esp.vmax.s32.st.incp q4, a1, q1, q4, q2 +# CHECK: esp.vmax.s32.st.incp q4, a1, q1, q4, q2 # encoding: [0xbf,0xd0,0xd9,0x88] +esp.vmax.s8 q3, q1, q0 +# CHECK: esp.vmax.s8 q3, q1, q0 # encoding: [0xdf,0xad,0x02,0x20] +esp.vmax.s8.ld.incp q4, a3, q5, q2, q5 +# CHECK: esp.vmax.s8.ld.incp q4, a3, q5, q2, q5 # encoding: [0xbf,0xd2,0x2a,0x54] +esp.vmax.s8.st.incp q0, a3, q3, q4, q5 +# CHECK: esp.vmax.s8.st.incp q0, a3, q3, q4, q5 # encoding: [0xbf,0xc1,0xaa,0x94] +esp.vmax.u16 q6, q3, q2 +# CHECK: esp.vmax.u16 q6, q3, q2 # encoding: [0x5f,0xaf,0x04,0x68] +esp.vmax.u16.ld.incp q5, a1, q5, q5, q3 +# CHECK: esp.vmax.u16.ld.incp q5, a1, q5, q5, q3 # encoding: [0xbf,0xd6,0x49,0xac] +esp.vmax.u16.st.incp q2, a4, q3, q2, q5 +# CHECK: esp.vmax.u16.st.incp q2, a4, q3, q2, q5 # encoding: [0xbf,0x49,0xcb,0x54] +esp.vmax.u32 q1, q0, q3 +# CHECK: esp.vmax.u32 q1, q0, q3 # encoding: [0xdf,0xac,0x01,0x0c] +esp.vmax.u32.ld.incp q3, a1, q5, q0, q4 +# CHECK: esp.vmax.u32.ld.incp q3, a1, q5, q0, q4 # encoding: [0xbf,0xce,0x19,0x10] +esp.vmax.u32.st.incp q1, a3, q2, q5, q5 +# CHECK: esp.vmax.u32.st.incp q1, a3, q2, q5, q5 # encoding: [0x3f,0xc5,0x9a,0xb4] +esp.vmax.u8 q1, q4, q0 +# CHECK: esp.vmax.u8 q1, q4, q0 # encoding: [0xdf,0xac,0x00,0x80] +esp.vmax.u8.ld.incp q1, a2, q3, q4, q6 +# CHECK: esp.vmax.u8.ld.incp q1, a2, q3, q4, q6 # encoding: [0xbf,0x45,0x0a,0x98] +esp.vmax.u8.st.incp q2, a3, q5, q3, q5 +# CHECK: esp.vmax.u8.st.incp q2, a3, q5, q3, q5 # encoding: [0xbf,0xca,0x8a,0x74] +esp.vmin.s16 q5, q3, q2 +# CHECK: esp.vmin.s16 q5, q3, q2 # encoding: [0xdf,0x3e,0x06,0x68] +esp.vmin.s16.ld.incp q6, a3, q1, q4, q5 +# CHECK: esp.vmin.s16.ld.incp q6, a3, q1, q4, q5 # encoding: [0xbf,0xd8,0x6a,0x95] +esp.vmin.s16.st.incp q0, a1, q5, q0, q3 +# CHECK: esp.vmin.s16.st.incp q0, a1, q5, q0, q3 # encoding: [0xbf,0xc2,0xe9,0x0d] +esp.vmin.s32 q3, q1, q4 +# CHECK: esp.vmin.s32 q3, q1, q4 # encoding: [0xdf,0x3d,0x05,0x30] +esp.vmin.s32.ld.incp q4, a0, q1, q6, q3 +# CHECK: esp.vmin.s32.ld.incp q4, a0, q1, q6, q3 # encoding: [0xbf,0x50,0x59,0xcd] +esp.vmin.s32.st.incp q6, a5, q4, q6, q2 +# CHECK: esp.vmin.s32.st.incp q6, a5, q4, q6, q2 # encoding: [0x3f,0xda,0xdb,0xc9] +esp.vmin.s8 q3, q2, q1 +# CHECK: esp.vmin.s8 q3, q2, q1 # encoding: [0xdf,0x3d,0x02,0x44] +esp.vmin.s8.ld.incp q1, a4, q5, q5, q6 +# CHECK: esp.vmin.s8.ld.incp q1, a4, q5, q5, q6 # encoding: [0xbf,0x46,0x2b,0xb9] +esp.vmin.s8.st.incp q5, a1, q6, q2, q0 +# CHECK: esp.vmin.s8.st.incp q5, a1, q6, q2, q0 # encoding: [0x3f,0xd7,0xa9,0x41] +esp.vmin.u16 q5, q0, q1 +# CHECK: esp.vmin.u16 q5, q0, q1 # encoding: [0xdf,0x3e,0x04,0x04] +esp.vmin.u16.ld.incp q3, a5, q5, q3, q5 +# CHECK: esp.vmin.u16.ld.incp q3, a5, q5, q3, q5 # encoding: [0xbf,0xce,0x4b,0x75] +esp.vmin.u16.st.incp q2, a3, q5, q6, q3 +# CHECK: esp.vmin.u16.st.incp q2, a3, q5, q6, q3 # encoding: [0xbf,0xca,0xca,0xcd] +esp.vmin.u32 q5, q0, q2 +# CHECK: esp.vmin.u32 q5, q0, q2 # encoding: [0xdf,0x3e,0x01,0x08] +esp.vmin.u32.ld.incp q4, a5, q4, q4, q2 +# CHECK: esp.vmin.u32.ld.incp q4, a5, q4, q4, q2 # encoding: [0x3f,0xd2,0x1b,0x89] +esp.vmin.u32.st.incp q4, a2, q1, q6, q3 +# CHECK: esp.vmin.u32.st.incp q4, a2, q1, q6, q3 # encoding: [0xbf,0x50,0x9a,0xcd] +esp.vmin.u8 q0, q0, q0 +# CHECK: esp.vmin.u8 q0, q0, q0 # encoding: [0x5f,0x3c,0x00,0x00] +esp.vmin.u8.ld.incp q2, a5, q1, q0, q6 +# CHECK: esp.vmin.u8.ld.incp q2, a5, q1, q0, q6 # encoding: [0xbf,0xc8,0x0b,0x19] +esp.vmin.u8.st.incp q1, a2, q0, q1, q1 +# CHECK: esp.vmin.u8.st.incp q1, a2, q0, q1, q1 # encoding: [0x3f,0x44,0x8a,0x25] +esp.vmul.s16 q1, q2, q1 +# CHECK: esp.vmul.s16 q1, q2, q1 # encoding: [0xdf,0xbc,0x06,0x44] +esp.vmul.s16.ld.incp q4, a3, q1, q4, q2 +# CHECK: esp.vmul.s16.ld.incp q4, a3, q1, q4, q2 # encoding: [0xbf,0xd0,0x6a,0x8b] +esp.vmul.s16.s8xs8 q4, q5, q1, q1 +# CHECK: esp.vmul.s16.s8xs8 q4, q5, q1, q1 # encoding: [0x5f,0x06,0xd3,0x26] +esp.vmul.s16.st.incp q2, a3, q1, q4, q0 +# CHECK: esp.vmul.s16.st.incp q2, a3, q1, q4, q0 # encoding: [0xbf,0xc8,0xea,0x83] +esp.vmul.s32.s16xs16 q4, q5, q2, q1 +# CHECK: esp.vmul.s32.s16xs16 q4, q5, q2, q1 # encoding: [0x5f,0x06,0xd7,0x46] +esp.vmul.s8 q1, q4, q1 +# CHECK: esp.vmul.s8 q1, q4, q1 # encoding: [0xdf,0xbc,0x02,0x84] +esp.vmul.s8.ld.incp q0, a0, q4, q0, q4 +# CHECK: esp.vmul.s8.ld.incp q0, a0, q4, q0, q4 # encoding: [0x3f,0x42,0x29,0x13] +esp.vmul.s8.st.incp q4, a3, q5, q6, q6 +# CHECK: esp.vmul.s8.st.incp q4, a3, q5, q6, q6 # encoding: [0xbf,0xd2,0xaa,0xdb] +esp.vmul.u16 q6, q6, q1 +# CHECK: esp.vmul.u16 q6, q6, q1 # encoding: [0x5f,0xbf,0x04,0xc4] +esp.vmul.u16.ld.incp q1, a5, q5, q4, q6 +# CHECK: esp.vmul.u16.ld.incp q1, a5, q5, q4, q6 # encoding: [0xbf,0xc6,0x4b,0x9b] +esp.vmul.u16.st.incp q3, a4, q5, q3, q3 +# CHECK: esp.vmul.u16.st.incp q3, a4, q5, q3, q3 # encoding: [0xbf,0x4e,0xcb,0x6f] +esp.vmul.u8 q0, q1, q5 +# CHECK: esp.vmul.u8 q0, q1, q5 # encoding: [0x5f,0xbc,0x00,0x34] +esp.vmul.u8.ld.incp q5, a3, q0, q4, q5 +# CHECK: esp.vmul.u8.ld.incp q5, a3, q0, q4, q5 # encoding: [0x3f,0xd4,0x0a,0x97] +esp.vmul.u8.st.incp q5, a0, q2, q4, q5 +# CHECK: esp.vmul.u8.st.incp q5, a0, q2, q4, q5 # encoding: [0x3f,0x55,0x89,0x97] +esp.vprelu.s16 q0, q3, q2, a4 +# CHECK: esp.vprelu.s16 q0, q3, q2, a4 # encoding: [0x5f,0x60,0xa3,0x4e] +esp.vprelu.s8 q4, q5, q5, a3 +# CHECK: esp.vprelu.s8 q4, q5, q5, a3 # encoding: [0x5f,0xe2,0x22,0xb6] +esp.vrelu.s16 q1, a1, a4 +# CHECK: esp.vrelu.s16 q1, a1, a4 # encoding: [0x5b,0x5c,0x33,0x86] +esp.vrelu.s8 q6, a1, a5 +# CHECK: esp.vrelu.s8 q6, a1, a5 # encoding: [0x5b,0xd8,0x33,0x9a] +esp.vsadds.s16 q5, q6, a4 +# CHECK: esp.vsadds.s16 q5, q6, a4 # encoding: [0x5f,0x02,0xd3,0xda] +esp.vsadds.s8 q6, q1, a4 +# CHECK: esp.vsadds.s8 q6, q1, a4 # encoding: [0x5f,0x02,0xe3,0x2a] +esp.vsadds.u16 q0, q6, a2 +# CHECK: esp.vsadds.u16 q0, q6, a2 # encoding: [0x5f,0x02,0x82,0xd2] +esp.vsadds.u8 q3, q3, a1 +# CHECK: esp.vsadds.u8 q3, q3, a1 # encoding: [0x5f,0x82,0xb1,0x62] +esp.vsat.s16 q3, q6, a0, a4 +# CHECK: esp.vsat.s16 q3, q6, a0, a4 # encoding: [0xbb,0x59,0x61,0xd8] +esp.vsat.s32 q6, q4, a3, a2 +# CHECK: esp.vsat.s32 q6, q4, a3, a2 # encoding: [0x3b,0xd7,0x42,0x98] +esp.vsat.s8 q3, q2, a2, a1 +# CHECK: esp.vsat.s8 q3, q2, a2, a1 # encoding: [0xbb,0x49,0x32,0x58] +esp.vsat.u16 q5, q5, a0, a1 +# CHECK: esp.vsat.u16 q5, q5, a0, a1 # encoding: [0xbb,0x52,0x31,0xb8] +esp.vsat.u32 q6, q5, a3, a3 +# CHECK: esp.vsat.u32 q6, q5, a3, a3 # encoding: [0x3b,0xc7,0x52,0xb8] +esp.vsat.u8 q4, q1, a0, a3 +# CHECK: esp.vsat.u8 q4, q1, a0, a3 # encoding: [0x3b,0x42,0x51,0x38] +esp.vssubs.s16 q1, q6, a1 +# CHECK: esp.vssubs.s16 q1, q6, a1 # encoding: [0x5f,0x82,0x91,0xde] +esp.vssubs.s8 q6, q0, a3 +# CHECK: esp.vssubs.s8 q6, q0, a3 # encoding: [0x5f,0x82,0xe2,0x0e] +esp.vssubs.u16 q6, q1, a2 +# CHECK: esp.vssubs.u16 q6, q1, a2 # encoding: [0x5f,0x02,0xe2,0x36] +esp.vssubs.u8 q2, q4, a1 +# CHECK: esp.vssubs.u8 q2, q4, a1 # encoding: [0x5f,0x82,0xa1,0x86] +esp.vsub.s16 q3, q1, q2 +# CHECK: esp.vsub.s16 q3, q1, q2 # encoding: [0xdf,0x06,0xb4,0x2a] +esp.vsub.s16.ld.incp q5, a2, q6, q3, q5 +# CHECK: esp.vsub.s16.ld.incp q5, a2, q6, q3, q5 # encoding: [0x3b,0x75,0xea,0x75] +esp.vsub.s16.st.incp q4, a0, q1, q1, q1 +# CHECK: esp.vsub.s16.st.incp q4, a0, q1, q1, q1 # encoding: [0x3b,0x71,0x99,0x27] +esp.vsub.s32 q4, q1, q0 +# CHECK: esp.vsub.s32 q4, q1, q0 # encoding: [0xdf,0x05,0xc4,0x22] +esp.vsub.s32.ld.incp q2, a2, q5, q0, q5 +# CHECK: esp.vsub.s32.ld.incp q2, a2, q5, q0, q5 # encoding: [0x3b,0x6b,0x52,0x15] +esp.vsub.s32.st.incp q5, a5, q4, q1, q6 +# CHECK: esp.vsub.s32.st.incp q5, a5, q4, q1, q6 # encoding: [0x3b,0xf7,0x43,0x3b] +esp.vsub.s8 q2, q1, q3 +# CHECK: esp.vsub.s8 q2, q1, q3 # encoding: [0xdf,0x06,0xa0,0x2e] +esp.vsub.s8.ld.incp q4, a4, q5, q4, q0 +# CHECK: esp.vsub.s8.ld.incp q4, a4, q5, q4, q0 # encoding: [0x3b,0x71,0xdb,0x80] +esp.vsub.s8.st.incp q1, a5, q0, q1, q1 +# CHECK: esp.vsub.s8.st.incp q1, a5, q0, q1, q1 # encoding: [0x3b,0xe5,0x8b,0x26] +esp.vsub.u16 q1, q2, q1 +# CHECK: esp.vsub.u16 q1, q2, q1 # encoding: [0xdf,0x04,0x94,0x46] +esp.vsub.u16.ld.incp q6, a4, q1, q6, q1 +# CHECK: esp.vsub.u16.ld.incp q6, a4, q1, q6, q1 # encoding: [0x3b,0x79,0x93,0xc5] +esp.vsub.u16.st.incp q1, a0, q0, q1, q6 +# CHECK: esp.vsub.u16.st.incp q1, a0, q0, q1, q6 # encoding: [0x3b,0x65,0x81,0x3b] +esp.vsub.u32 q2, q2, q5 +# CHECK: esp.vsub.u32 q2, q2, q5 # encoding: [0xdf,0x05,0xa0,0x56] +esp.vsub.u32.ld.incp q4, a5, q2, q4, q3 +# CHECK: esp.vsub.u32.ld.incp q4, a5, q2, q4, q3 # encoding: [0x3b,0xf3,0x23,0x8c] +esp.vsub.u32.st.incp q0, a0, q3, q3, q1 +# CHECK: esp.vsub.u32.st.incp q0, a0, q3, q3, q1 # encoding: [0x3b,0x63,0x31,0x66] +esp.vsub.u8 q1, q4, q1 +# CHECK: esp.vsub.u8 q1, q4, q1 # encoding: [0xdf,0x04,0x90,0x86] +esp.vsub.u8.ld.incp q4, a1, q4, q5, q2 +# CHECK: esp.vsub.u8.ld.incp q4, a1, q4, q5, q2 # encoding: [0x3b,0xf1,0xc1,0xa8] +esp.vsub.u8.st.incp q6, a4, q6, q5, q5 +# CHECK: esp.vsub.u8.st.incp q6, a4, q6, q5, q5 # encoding: [0x3b,0x79,0xe3,0xb6] +esp.addx2 a1, a4, a2 +# CHECK: esp.addx2 a1, a4, a2 # encoding: [0xb3,0x05,0xc7,0x04] +esp.addx4 a1, a3, a3 +# CHECK: esp.addx4 a1, a3, a3 # encoding: [0xb3,0x85,0xd6,0x08] +esp.sat a5, a1, a2 +# CHECK: esp.sat a5, a1, a2 # encoding: [0xb3,0x25,0xf6,0x40] +esp.subx2 a0, a3, a5 +# CHECK: esp.subx2 a0, a3, a5 # encoding: [0x33,0x85,0xf6,0x44] +esp.subx4 a5, a4, a0 +# CHECK: esp.subx4 a5, a4, a0 # encoding: [0xb3,0x07,0xa7,0x48] +esp.andq q4, q2, q2 +# CHECK: esp.andq q4, q2, q2 # encoding: [0x5f,0x22,0x04,0x48] +esp.notq q0, q1 +# CHECK: esp.notq q0, q1 # encoding: [0x5f,0x20,0x06,0x20] +esp.orq q4, q3, q1 +# CHECK: esp.orq q4, q3, q1 # encoding: [0x5f,0x22,0x00,0x64] +esp.xorq q2, q1, q1 +# CHECK: esp.xorq q2, q1, q1 # encoding: [0x5f,0x21,0x02,0x24] +esp.vcmp.eq.s16 q1, q5, q1 +# CHECK: esp.vcmp.eq.s16 q1, q5, q1 # encoding: [0xdf,0xb4,0x01,0xa4] +esp.vcmp.eq.s32 q3, q3, q2 +# CHECK: esp.vcmp.eq.s32 q3, q3, q2 # encoding: [0xdf,0x2d,0x01,0x68] +esp.vcmp.eq.s8 q3, q6, q6 +# CHECK: esp.vcmp.eq.s8 q3, q6, q6 # encoding: [0xdf,0xb5,0x00,0xd8] +esp.vcmp.eq.u16 q6, q2, q5 +# CHECK: esp.vcmp.eq.u16 q6, q2, q5 # encoding: [0x5f,0x37,0x01,0x54] +esp.vcmp.eq.u32 q0, q6, q6 +# CHECK: esp.vcmp.eq.u32 q0, q6, q6 # encoding: [0x5f,0x2c,0x00,0xd8] +esp.vcmp.eq.u8 q4, q2, q4 +# CHECK: esp.vcmp.eq.u8 q4, q2, q4 # encoding: [0x5f,0x36,0x00,0x50] +esp.vcmp.gt.s16 q4, q0, q2 +# CHECK: esp.vcmp.gt.s16 q4, q0, q2 # encoding: [0x5f,0xb6,0x05,0x08] +esp.vcmp.gt.s32 q1, q1, q0 +# CHECK: esp.vcmp.gt.s32 q1, q1, q0 # encoding: [0xdf,0x2c,0x05,0x20] +esp.vcmp.gt.s8 q4, q0, q2 +# CHECK: esp.vcmp.gt.s8 q4, q0, q2 # encoding: [0x5f,0xb6,0x04,0x08] +esp.vcmp.gt.u16 q5, q6, q2 +# CHECK: esp.vcmp.gt.u16 q5, q6, q2 # encoding: [0xdf,0x36,0x05,0xc8] +esp.vcmp.gt.u32 q1, q5, q2 +# CHECK: esp.vcmp.gt.u32 q1, q5, q2 # encoding: [0xdf,0x2c,0x04,0xa8] +esp.vcmp.gt.u8 q1, q4, q4 +# CHECK: esp.vcmp.gt.u8 q1, q4, q4 # encoding: [0xdf,0x34,0x04,0x90] +esp.vcmp.lt.s16 q6, q2, q5 +# CHECK: esp.vcmp.lt.s16 q6, q2, q5 # encoding: [0x5f,0xb7,0x03,0x54] +esp.vcmp.lt.s32 q2, q3, q2 +# CHECK: esp.vcmp.lt.s32 q2, q3, q2 # encoding: [0x5f,0x2d,0x03,0x68] +esp.vcmp.lt.s8 q0, q6, q2 +# CHECK: esp.vcmp.lt.s8 q0, q6, q2 # encoding: [0x5f,0xb4,0x02,0xc8] +esp.vcmp.lt.u16 q0, q2, q5 +# CHECK: esp.vcmp.lt.u16 q0, q2, q5 # encoding: [0x5f,0x34,0x03,0x54] +esp.vcmp.lt.u32 q1, q0, q3 +# CHECK: esp.vcmp.lt.u32 q1, q0, q3 # encoding: [0xdf,0x2c,0x02,0x0c] +esp.vcmp.lt.u8 q1, q1, q4 +# CHECK: esp.vcmp.lt.u8 q1, q1, q4 # encoding: [0xdf,0x34,0x02,0x30] +esp.mov.s16.qacc q5 +# CHECK: esp.mov.s16.qacc q5 # encoding: [0x5b,0x14,0x60,0x10] +esp.mov.s8.qacc q3 +# CHECK: esp.mov.s8.qacc q3 # encoding: [0x5b,0x0c,0x20,0x10] +esp.mov.u16.qacc q6 +# CHECK: esp.mov.u16.qacc q6 # encoding: [0x5b,0x18,0x40,0x10] +esp.mov.u8.qacc q3 +# CHECK: esp.mov.u8.qacc q3 # encoding: [0x5b,0x0c,0x00,0x10] +esp.movi.16.a q5, a4, 2 +# CHECK: esp.movi.16.a q5, a4, 2 # encoding: [0x5f,0x03,0xc1,0x14] +esp.movi.16.q q1, a3, 7 +# CHECK: esp.movi.16.q q1, a3, 7 # encoding: [0xdf,0x83,0xe2,0x84] +esp.movi.32.a q6, a0, 2 +# CHECK: esp.movi.32.a q6, a0, 2 # encoding: [0x5f,0x01,0xc0,0x98] +esp.movi.32.q q6, a4, 2 +# CHECK: esp.movi.32.q q6, a4, 2 # encoding: [0x5f,0x04,0x93,0x98] +esp.movi.8.a q5, a5, 6 +# CHECK: esp.movi.8.a q5, a5, 6 # encoding: [0xdf,0x03,0x83,0x14] +esp.movi.8.q q2, a1, 15 +# CHECK: esp.movi.8.q q2, a1, 15 # encoding: [0xdf,0x87,0xa1,0x88] +esp.movx.r.cfg a4 +# CHECK: esp.movx.r.cfg a4 # encoding: [0x5f,0x03,0xd0,0x80] +esp.movx.r.fft.bit.width a2 +# CHECK: esp.movx.r.fft.bit.width a2 # encoding: [0x5f,0x02,0xd0,0x84] +esp.movx.r.perf a4, a1 +# CHECK: esp.movx.r.perf a4, a1 # encoding: [0x5f,0x83,0xd1,0x8c] +esp.movx.r.sar a5 +# CHECK: esp.movx.r.sar a5 # encoding: [0xdf,0x03,0xb0,0x80] +esp.movx.r.sar.bytes a4 +# CHECK: esp.movx.r.sar.bytes a4 # encoding: [0x5f,0x03,0xb0,0x88] +esp.movx.r.xacc.h a5 +# CHECK: esp.movx.r.xacc.h a5 # encoding: [0xdf,0x03,0xb0,0x8c] +esp.movx.r.xacc.l a3 +# CHECK: esp.movx.r.xacc.l a3 # encoding: [0xdf,0x02,0xb0,0x84] +esp.movx.w.cfg a1 +# CHECK: esp.movx.w.cfg a1 # encoding: [0x5f,0x80,0xd1,0x90] +esp.movx.w.fft.bit.width a1 +# CHECK: esp.movx.w.fft.bit.width a1 # encoding: [0x5f,0x80,0xd1,0x94] +esp.movx.w.perf a1 +# CHECK: esp.movx.w.perf a1 # encoding: [0x5f,0x80,0xd1,0x9c] +esp.movx.w.sar a2 +# CHECK: esp.movx.w.sar a2 # encoding: [0x5f,0x00,0xb2,0x90] +esp.movx.w.sar.bytes a1 +# CHECK: esp.movx.w.sar.bytes a1 # encoding: [0x5f,0x80,0xb1,0x98] +esp.movx.w.xacc.h a5 +# CHECK: esp.movx.w.xacc.h a5 # encoding: [0x5f,0x80,0xb3,0x9c] +esp.movx.w.xacc.l a2 +# CHECK: esp.movx.w.xacc.l a2 # encoding: [0x5f,0x00,0xb2,0x94] +esp.vext.s16 q3, q1, q5 +# CHECK: esp.vext.s16 q3, q1, q5 # encoding: [0xdb,0x59,0x18,0x19] +esp.vext.s8 q0, q0, q6 +# CHECK: esp.vext.s8 q0, q0, q6 # encoding: [0x5b,0x58,0x08,0x0a] +esp.vext.u16 q4, q2, q6 +# CHECK: esp.vext.u16 q4, q2, q6 # encoding: [0x5b,0x5a,0x28,0x12] +esp.vext.u8 q1, q2, q5 +# CHECK: esp.vext.u8 q1, q2, q5 # encoding: [0xdb,0x58,0x28,0x01] +esp.vunzip.16 q2, q3 +# CHECK: esp.vunzip.16 q2, q3 # encoding: [0x5f,0x00,0x86,0x4e] +esp.vunzip.32 q2, q1 +# CHECK: esp.vunzip.32 q2, q1 # encoding: [0x5f,0x80,0x84,0x46] +esp.vunzip.8 q3, q5 +# CHECK: esp.vunzip.8 q3, q5 # encoding: [0x5f,0x00,0x84,0x76] +esp.vunzipt.16 q5, q4, q5 +# CHECK: esp.vunzipt.16 q5, q4, q5 # encoding: [0x5b,0x4c,0xc8,0xb1] +esp.vunzipt.8 q3, q6, q4 +# CHECK: esp.vunzipt.8 q3, q6, q4 # encoding: [0x5b,0x4c,0x88,0x78] +esp.vzip.16 q1, q0 +# CHECK: esp.vzip.16 q1, q0 # encoding: [0x5f,0x00,0x82,0x22] +esp.vzip.32 q1, q1 +# CHECK: esp.vzip.32 q1, q1 # encoding: [0x5f,0x80,0x80,0x26] +esp.vzip.8 q2, q2 +# CHECK: esp.vzip.8 q2, q2 # encoding: [0x5f,0x00,0x80,0x4a] +esp.vzipt.16 q1, q2, q1 +# CHECK: esp.vzipt.16 q1, q2, q1 # encoding: [0x5b,0x4c,0x40,0x29] +esp.vzipt.8 q3, q3, q5 +# CHECK: esp.vzipt.8 q3, q3, q5 # encoding: [0x5b,0x4c,0x08,0x6d] +esp.zero.q q0 +# CHECK: esp.zero.q q0 # encoding: [0x5b,0x00,0x40,0x00] +esp.zero.qacc +# CHECK: esp.zero.qacc # encoding: [0x5b,0x02,0x00,0x00] +esp.zero.xacc +# CHECK: esp.zero.xacc # encoding: [0x5b,0x00,0x00,0x00] +esp.fft.ams.s16.ld.incp q5, a4, q6, q2, q3, q3, q0, 1 +# CHECK: esp.fft.ams.s16.ld.incp q5, a4, q6, q2, q3, q3, q0, 1 # encoding: [0x7b,0x17,0xa3,0x63] +esp.fft.ams.s16.ld.incp.uaup q1, a5, q3, q5, q6, q2, q0, 0 +# CHECK: esp.fft.ams.s16.ld.incp.uaup q1, a5, q3, q5, q6, q2, q0, 0 # encoding: [0xfb,0xa5,0x53,0xc2] +esp.fft.ams.s16.ld.r32.decp q4, a5, q3, q6, q5, q6, q6, 1 +# CHECK: esp.fft.ams.s16.ld.r32.decp q4, a5, q3, q6, q5, q6, q6, 1 # encoding: [0xfb,0xf1,0xeb,0xba] +esp.fft.ams.s16.st.incp q5, q3, a3, a1, q6, q2, q3, 0 +# CHECK: esp.fft.ams.s16.st.incp q5, q3, a3, a1, q6, q2, q3, 0 # encoding: [0xbf,0xb5,0x51,0xce] +esp.fft.bitrev q3, a5 +# CHECK: esp.fft.bitrev q3, a5 # encoding: [0x5b,0x82,0x33,0x10] +esp.fft.cmul.s16.ld.xp q3, a3, a4, q1, q3, q2, 4 +# CHECK: esp.fft.cmul.s16.ld.xp q3, a3, a4, q1, q3, q2, 4 # encoding: [0xbf,0x8c,0x62,0x4e] +esp.fft.cmul.s16.st.xp q1, q2, q3, a4, a0, 7, 1, 1 +# CHECK: esp.fft.cmul.s16.st.xp q1, q2, q3, a4, a0, 7, 1, 1 # encoding: [0xff,0x4f,0x23,0x45] +esp.fft.r2bf.s16 q3, q2, q5, q1, 1 +# CHECK: esp.fft.r2bf.s16 q3, q2, q5, q1, 1 # encoding: [0xdf,0x05,0xa5,0xa6] +esp.fft.r2bf.s16.st.incp q5, q4, q4, a5, 1 +# CHECK: esp.fft.r2bf.s16.st.incp q5, q4, q4, a5, 1 # encoding: [0xdf,0xe2,0x43,0x92] +esp.fft.vst.r32.decp q1, a4, 1 +# CHECK: esp.fft.vst.r32.decp q1, a4, 1 # encoding: [0x3b,0x24,0x03,0x80] +esp.ld.128.usar.ip q5, a4, -896 +# CHECK: esp.ld.128.usar.ip q5, a4, -896 # encoding: [0x3b,0x34,0x43,0xc8] +esp.ld.128.usar.xp q5, a2, a5 +# CHECK: esp.ld.128.usar.xp q5, a2, a5 # encoding: [0x5f,0x54,0x72,0x80] +esp.ld.xacc.ip a1, 616 +# CHECK: esp.ld.xacc.ip a1, 616 # encoding: [0x3b,0xd7,0x91,0x20] +esp.ldqa.s16.128.ip a3, -672 +# CHECK: esp.ldqa.s16.128.ip a3, -672 # encoding: [0xbb,0xcc,0xd2,0xe0] +esp.ldqa.s16.128.xp a4, a1 +# CHECK: esp.ldqa.s16.128.xp a4, a1 # encoding: [0x5b,0x53,0x33,0x13] +esp.ldqa.s8.128.ip a4, 1808 +# CHECK: esp.ldqa.s8.128.ip a4, 1808 # encoding: [0xbb,0x42,0x73,0x60] +esp.ldqa.s8.128.xp a0, a4 +# CHECK: esp.ldqa.s8.128.xp a0, a4 # encoding: [0x5b,0x51,0x61,0x13] +esp.ldqa.u16.128.ip a3, -496 +# CHECK: esp.ldqa.u16.128.ip a3, -496 # encoding: [0xbb,0xc2,0xe2,0xa0] +esp.ldqa.u16.128.xp a2, a4 +# CHECK: esp.ldqa.u16.128.xp a2, a4 # encoding: [0x5b,0x52,0x62,0x13] +esp.ldqa.u8.128.ip a2, 1200 +# CHECK: esp.ldqa.u8.128.ip a2, 1200 # encoding: [0xbb,0x56,0x42,0x20] +esp.ldqa.u8.128.xp a2, a5 +# CHECK: esp.ldqa.u8.128.xp a2, a5 # encoding: [0x5b,0x50,0x72,0x13] +esp.vldbc.16.ip q4, a3, 408 +# CHECK: esp.vldbc.16.ip q4, a3, 408 # encoding: [0x3b,0xb0,0x32,0xb6] +esp.vldbc.16.xp q5, a2, a1 +# CHECK: esp.vldbc.16.xp q5, a2, a1 # encoding: [0x5f,0x54,0x32,0x96] +esp.vldbc.32.ip q6, a2, -176 +# CHECK: esp.vldbc.32.ip q6, a2, -176 # encoding: [0x3b,0x38,0xa2,0xce] +esp.vldbc.32.xp q0, a1, a2 +# CHECK: esp.vldbc.32.xp q0, a1, a2 # encoding: [0x5f,0xc0,0x41,0x8e] +esp.vldbc.8.ip q6, a0, 200 +# CHECK: esp.vldbc.8.ip q6, a0, 200 # encoding: [0x3b,0x38,0x91,0x16] +esp.vldbc.8.xp q5, a4, a2 +# CHECK: esp.vldbc.8.xp q5, a4, a2 # encoding: [0x5f,0x54,0x43,0x86] +esp.vldext.s16.ip q4, q1, a3, -112 +# CHECK: esp.vldext.s16.ip q4, q1, a3, -112 # encoding: [0xbb,0xd0,0x92,0xc8] +esp.vldext.s16.xp q2, q4, a1, a0 +# CHECK: esp.vldext.s16.xp q2, q4, a1, a0 # encoding: [0x5f,0xea,0x21,0xf0] +esp.vldext.s8.ip q3, q2, a4, 0 +# CHECK: esp.vldext.s8.ip q3, q2, a4, 0 # encoding: [0x3b,0x4d,0x03,0x48] +esp.vldext.s8.xp q3, q6, a4, a1 +# CHECK: esp.vldext.s8.xp q3, q6, a4, a1 # encoding: [0x5f,0x6f,0x33,0x70] +esp.vldext.u16.ip q2, q1, a1, 48 +# CHECK: esp.vldext.u16.ip q2, q1, a1, 48 # encoding: [0xbb,0xc8,0x31,0x88] +esp.vldext.u16.xp q1, q2, a3, a1 +# CHECK: esp.vldext.u16.xp q1, q2, a3, a1 # encoding: [0x5f,0xe5,0x32,0xb0] +esp.vldext.u8.ip q5, q6, a0, -48 +# CHECK: esp.vldext.u8.ip q5, q6, a0, -48 # encoding: [0x3b,0x57,0xd1,0x08] +esp.vldext.u8.xp q0, q6, a3, a1 +# CHECK: esp.vldext.u8.xp q0, q6, a3, a1 # encoding: [0x5f,0xe3,0x32,0x30] +esp.vldhbc.16.incp q4, q2, a2 +# CHECK: esp.vldhbc.16.incp q4, q2, a2 # encoding: [0x3b,0x51,0x02,0x28] +esp.ld.qacc.h.h.128.ip a0, 816 +# CHECK: esp.ld.qacc.h.h.128.ip a0, 816 # encoding: [0x3b,0x46,0x31,0x40] +esp.ld.qacc.h.l.128.ip a2, -496 +# CHECK: esp.ld.qacc.h.l.128.ip a2, -496 # encoding: [0x3b,0x42,0xe2,0x60] +esp.ld.qacc.l.h.128.ip a1, -432 +# CHECK: esp.ld.qacc.l.h.128.ip a1, -432 # encoding: [0x3b,0xca,0xe1,0x00] +esp.ld.qacc.l.l.128.ip a0, 1840 +# CHECK: esp.ld.qacc.l.l.128.ip a0, 1840 # encoding: [0x3b,0x46,0x71,0x20] +esp.ld.ua.state.ip a4, -1392 +# CHECK: esp.ld.ua.state.ip a4, -1392 # encoding: [0x3b,0x45,0x53,0x60] +esp.ldxq.32 q5, q4, a4, 3, 6 +# CHECK: esp.ldxq.32 q5, q4, a4, 3, 6 # encoding: [0x5f,0x34,0x8b,0x78] +esp.st.qacc.h.h.128.ip a4, 656 +# CHECK: esp.st.qacc.h.h.128.ip a4, 656 # encoding: [0x3b,0x52,0x23,0xc0] +esp.st.qacc.h.l.128.ip a3, -1072 +# CHECK: esp.st.qacc.h.l.128.ip a3, -1072 # encoding: [0x3b,0xda,0xb2,0xe0] +esp.st.qacc.l.h.128.ip a2, 784 +# CHECK: esp.st.qacc.l.h.128.ip a2, 784 # encoding: [0x3b,0x42,0x32,0x80] +esp.st.qacc.l.l.128.ip a3, -736 +# CHECK: esp.st.qacc.l.l.128.ip a3, -736 # encoding: [0x3b,0xc4,0xd2,0xa0] +esp.st.ua.state.ip a5, 1376 +# CHECK: esp.st.ua.state.ip a5, 1376 # encoding: [0x3b,0xd9,0xa3,0xa0] +esp.stxq.32 q6, q5, a5, 3, 4 +# CHECK: esp.stxq.32 q6, q5, a5, 3, 4 # encoding: [0x5f,0xb8,0x8b,0xf1] +esp.vld.128.ip q1, a3, 560 +# CHECK: esp.vld.128.ip q1, a3, 560 # encoding: [0x3b,0xa6,0x12,0x12] +esp.vld.128.xp q1, a5, a3 +# CHECK: esp.vld.128.xp q1, a5, a3 # encoding: [0x5f,0xc4,0x53,0x82] +esp.vld.h.64.ip q4, a5, -568 +# CHECK: esp.vld.h.64.ip q4, a5, -568 # encoding: [0x3b,0xb2,0xc3,0x6c] +esp.vld.h.64.xp q1, a1, a2 +# CHECK: esp.vld.h.64.xp q1, a1, a2 # encoding: [0x5f,0xc4,0x41,0x8c] +esp.vld.l.64.ip q2, a3, -696 +# CHECK: esp.vld.l.64.ip q2, a3, -696 # encoding: [0x3b,0xaa,0x42,0x2c] +esp.vld.l.64.xp q5, a4, a4 +# CHECK: esp.vld.l.64.xp q5, a4, a4 # encoding: [0x5f,0x54,0x63,0x84] +esp.vst.128.ip q3, a4, 1088 +# CHECK: esp.vst.128.ip q3, a4, 1088 # encoding: [0x3b,0x2c,0x23,0xa2] +esp.vst.128.xp q1, a4, a0 +# CHECK: esp.vst.128.xp q1, a4, a0 # encoding: [0x5f,0x44,0x23,0x92] +esp.vst.h.64.ip q5, a4, -136 +# CHECK: esp.vst.h.64.ip q5, a4, -136 # encoding: [0x3b,0x36,0x73,0xfc] +esp.vst.h.64.xp q1, a0, a2 +# CHECK: esp.vst.h.64.xp q1, a0, a2 # encoding: [0x5f,0x44,0x41,0x9c] +esp.vst.l.64.ip q5, a0, -440 +# CHECK: esp.vst.l.64.ip q5, a0, -440 # encoding: [0x3b,0x36,0x41,0xb4] +esp.vst.l.64.xp q2, a5, a3 +# CHECK: esp.vst.l.64.xp q2, a5, a3 # encoding: [0x5f,0xc8,0x53,0x94] +esp.slci.2q q2, q6, 10 +# CHECK: esp.slci.2q q2, q6, 10 # encoding: [0x5b,0x49,0x48,0x0a] +esp.slcxxp.2q q2, q1, a0, a3 +# CHECK: esp.slcxxp.2q q2, q1, a0, a3 # encoding: [0x5f,0x40,0x51,0x09] +esp.src.q q5, q6, q2 +# CHECK: esp.src.q q5, q6, q2 # encoding: [0xdb,0x02,0x2c,0x8a] +esp.src.q.ld.ip q3, a4, 48, q6, q6 +# CHECK: esp.src.q.ld.ip q3, a4, 48, q6, q6 # encoding: [0x3b,0x2f,0x1b,0x1a] +esp.src.q.ld.xp q6, a5, a0, q6, q6 +# CHECK: esp.src.q.ld.xp q6, a5, a0, q6, q6 # encoding: [0x3b,0x98,0x2b,0x1a] +esp.src.q.qup q1, q5, q0 +# CHECK: esp.src.q.qup q1, q5, q0 # encoding: [0xdb,0x10,0x2c,0x81] +esp.srci.2q q5, q5, 11 +# CHECK: esp.srci.2q q5, q5, 11 # encoding: [0xdb,0x49,0xc8,0x15] +esp.srcmb.s16.q.qacc q6, q2, 0 +# CHECK: esp.srcmb.s16.q.qacc q6, q2, 0 # encoding: [0x5b,0x18,0x64,0x9a] +esp.srcmb.s16.qacc q2, a2, 0 +# CHECK: esp.srcmb.s16.qacc q2, a2, 0 # encoding: [0x3b,0x28,0x02,0xd8] +esp.srcmb.s8.q.qacc q5, q3, 0 +# CHECK: esp.srcmb.s8.q.qacc q5, q3, 0 # encoding: [0x5b,0x14,0x64,0x8b] +esp.srcmb.s8.qacc q1, a3, 1 +# CHECK: esp.srcmb.s8.qacc q1, a3, 1 # encoding: [0x3b,0xa4,0x02,0x78] +esp.srcmb.u16.q.qacc q3, q4, 0 +# CHECK: esp.srcmb.u16.q.qacc q3, q4, 0 # encoding: [0x5b,0x0c,0x6c,0x90] +esp.srcmb.u16.qacc q1, a0, 1 +# CHECK: esp.srcmb.u16.qacc q1, a0, 1 # encoding: [0x3b,0x24,0x01,0xb8] +esp.srcmb.u8.q.qacc q0, q5, 1 +# CHECK: esp.srcmb.u8.q.qacc q0, q5, 1 # encoding: [0x5b,0x00,0x6c,0x85] +esp.srcmb.u8.qacc q1, a3, 1 +# CHECK: esp.srcmb.u8.qacc q1, a3, 1 # encoding: [0x3b,0xa4,0x02,0x38] +esp.srcq.128.st.incp q1, q2, a0 +# CHECK: esp.srcq.128.st.incp q1, q2, a0 # encoding: [0x5b,0x40,0x01,0x09] +esp.srcxxp.2q q3, q3, a4, a4 +# CHECK: esp.srcxxp.2q q3, q3, a4, a4 # encoding: [0x5f,0x44,0x63,0x0f] +esp.srs.s.xacc a0, a0 +# CHECK: esp.srs.s.xacc a0, a0 # encoding: [0x5f,0x01,0xf1,0x94] +esp.srs.u.xacc a0, a3 +# CHECK: esp.srs.u.xacc a0, a3 # encoding: [0x5f,0x81,0xf2,0x84] +esp.vsl.32 q6, q4 +# CHECK: esp.vsl.32 q6, q4 # encoding: [0x5b,0x18,0x04,0x90] +esp.vsld.16 q6, q5, q1 +# CHECK: esp.vsld.16 q6, q5, q1 # encoding: [0x5f,0x18,0x20,0x15] +esp.vsld.32 q2, q4, q3 +# CHECK: esp.vsld.32 q2, q4, q3 # encoding: [0x5f,0x08,0x10,0x13] +esp.vsld.8 q1, q1, q4 +# CHECK: esp.vsld.8 q1, q1, q4 # encoding: [0x5f,0x04,0x08,0x04] +esp.vsr.s32 q1, q3 +# CHECK: esp.vsr.s32 q1, q3 # encoding: [0x5b,0x07,0x04,0x8c] +esp.vsr.u32 q5, q2 +# CHECK: esp.vsr.u32 q5, q2 # encoding: [0x5b,0x15,0x04,0x88] +esp.vsrd.16 q1, q5, q5 +# CHECK: esp.vsrd.16 q1, q5, q5 # encoding: [0x5f,0x04,0x68,0x15] +esp.vsrd.32 q1, q6, q3 +# CHECK: esp.vsrd.32 q1, q6, q3 # encoding: [0x5f,0x04,0x50,0x1b] +esp.vsrd.8 q0, q3, q1 +# CHECK: esp.vsrd.8 q0, q3, q1 # encoding: [0x5f,0x00,0x40,0x0d] +esp.st.s.xacc.ip a1, 304 +# CHECK: esp.st.s.xacc.ip a1, 304 # encoding: [0xbb,0xd9,0x41,0xa0] +esp.st.u.xacc.ip a2, 976 +# CHECK: esp.st.u.xacc.ip a2, 976 # encoding: [0xbb,0x49,0xf2,0x20] diff --git a/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s b/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s index fe6d0de0a4b001..e45c43a50048ad 100644 --- a/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s +++ b/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s @@ -1,7 +1,7 @@ # RUN: not llvm-mc -triple riscv32 -mattr=+xtheadmemidx < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+xtheadmemidx < %s 2>&1 | FileCheck %s -th.ldia 0(a0), (a1), 0, 0 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction +th.ldia 0(a0), (a1), 0, 0 # CHECK: :[[@LINE]]:26: error: invalid operand for instruction th.ldib a0, 2(a1), 15, 1 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction th.lwia a0, (a1), 30, 2 # CHECK: :[[@LINE]]:20: error: immediate must be an integer in the range [-16, 15] th.lwib a0, (a1), -16, 43 # CHECK: :[[@LINE]]:25: error: immediate must be an integer in the range [0, 3] diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 24ed3e2e4b0561..5dff9c66bbb523 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -769,6 +769,7 @@ R"(All available -march extensions for RISC-V xcvmac 1.0 xcvmem 1.0 xcvsimd 1.0 + xesppie 1.0 xsfvcp 1.0 xsfvfnrclipxfqf 1.0 xsfvfwmaccqqq 1.0 diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index 73724e662f9e87..3ee0d9b39d8756 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -2008,10 +2008,11 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName, << " &>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n"; CvtOS << " break;\n"; CvtOS << " case CVT_Tied: {\n"; - CvtOS << " assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n"; + CvtOS << " unsigned OpIdxTied = *(p + 1);\n"; + CvtOS << " assert(OpIdxTied < (size_t)(std::end(TiedAsmOperandTable) -\n"; CvtOS << " std::begin(TiedAsmOperandTable)) &&\n"; CvtOS << " \"Tied operand not found\");\n"; - CvtOS << " unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];\n"; + CvtOS << " unsigned TiedResOpnd = TiedAsmOperandTable[OpIdxTied][0];\n"; CvtOS << " if (TiedResOpnd != (uint8_t)-1)\n"; CvtOS << " Inst.addOperand(Inst.getOperand(TiedResOpnd));\n"; CvtOS << " break;\n"; From 8230af693db19ea09b1ffd12249dd4d8066bc850 Mon Sep 17 00:00:00 2001 From: Stefan Stipanovic Date: Thu, 22 Aug 2024 09:56:30 +0200 Subject: [PATCH 256/261] [RISCV][ESP32P4] Don't yet consider v16i8 and v4i32 legal --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 ------ 1 file changed, 6 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 396a7b8f2d1c95..98b372a30c0537 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -119,12 +119,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, // Set up the register classes. addRegisterClass(XLenVT, &RISCV::GPRRegClass); - if (Subtarget.hasVendorESP32P4()) { - static const MVT::SimpleValueType QRVec[] = {MVT::v16i8, MVT::v4i32}; - for (auto st : QRVec) - addRegisterClass(st, &RISCV::QRRegClass); - } - if (Subtarget.is64Bit() && RV64LegalI32) addRegisterClass(MVT::i32, &RISCV::GPRRegClass); From 4cbf3360d7b114014d7a5d1873c5ca091dff8e3c Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Wed, 21 Aug 2024 18:04:35 +0300 Subject: [PATCH 257/261] toolchain/esp: Add test for 'xesppie' multilib mapping for esp32-p4 --- .../lib/clang-runtimes/multilib.yaml | 9 +++++++++ clang/test/Driver/baremetal-esp.cpp | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/multilib.yaml b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/multilib.yaml index c4123d3cfc039c..f882427769012c 100644 --- a/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/multilib.yaml +++ b/clang/test/Driver/Inputs/basic_riscv32_esp_tree/lib/clang-runtimes/multilib.yaml @@ -246,3 +246,12 @@ Mappings: - Match: -march=rv32gc Flags: - -march=rv32imafc_zicsr_zifencei + +# Below is a workaround to support multilib for xesppie variant +# Currently it is added for ESP32-P4 arch only +- Match: -march=rv32imafc_xesppie + Flags: + - -march=rv32imafc_zicsr_zifencei +- Match: -march=rv32imafc_zicsr_zifencei_xesppie + Flags: + - -march=rv32imafc_zicsr_zifencei diff --git a/clang/test/Driver/baremetal-esp.cpp b/clang/test/Driver/baremetal-esp.cpp index 140df519ca951e..12d8a1fb0643be 100644 --- a/clang/test/Driver/baremetal-esp.cpp +++ b/clang/test/Driver/baremetal-esp.cpp @@ -252,6 +252,12 @@ // RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -march=rv32gc -mabi=ilp32f \ // RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ // RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -march=rv32imafc_zicsr_zifencei_xesppie -mabi=ilp32f \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC %s +// RUN: %t/basic_riscv32_esp_tree/bin/clang %s -### 2>&1 --target=riscv32-esp-elf -march=rv32imafc_xesppie -mabi=ilp32f \ +// RUN: --sysroot=%t/basic_riscv32_esp_tree/lib/clang-runtimes \ +// RUN: | FileCheck --check-prefix=CHECK-ESP-RV32IMAFC %s // CHECK-ESP-RV32IMAFC: "-cc1" "-triple" "riscv32-esp-unknown-elf" // CHECK-ESP-RV32IMAFC-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" // CHECK-ESP-RV32IMAFC-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" From 87287861ca4e7659db58b88a222bbf80e04e5640 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Thu, 22 Aug 2024 15:48:47 +0300 Subject: [PATCH 258/261] esp/ci: Add esp-dsp build test job --- .gitlab-ci.yml | 81 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 72 insertions(+), 9 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d38b3dc5fd3660..ad3a371c941a7d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -288,6 +288,17 @@ build_aarch64-apple-darwin: variables: CONF_HOST: "aarch64-apple-darwin21.1" +.unpack_distro: &unpack_distro | + pushd ${DIST_DIR} + ls -l + DISTRO_PACK_FILE=$(cat dist_name_${CONF_HOST}) + echo "DISTRO_PACK_FILE=${DISTRO_PACK_FILE}" + ${UNPACK_TOOL} ${DISTRO_PACK_FILE} + DISTRO_PACK_DIR=$(tar tJf ${DISTRO_PACK_FILE} | sed -e 's@/.*@@' | uniq) + ls -l $PWD/${DISTRO_PACK_DIR}/lib/clang-runtimes/ + echo "DISTRO_PACK_DIR=${DISTRO_PACK_DIR}" + rm -f ${DISTRO_PACK_FILE} + .pack_template: stage: pack tags: [ "amd64", "build" ] @@ -302,15 +313,7 @@ build_aarch64-apple-darwin: script: - *get_toolchain_build_scripts # update distro - - pushd ${DIST_DIR} - - ls -l - - DISTRO_PACK_FILE=$(cat dist_name_${CONF_HOST}) - - echo "DISTRO_PACK_FILE=${DISTRO_PACK_FILE}" - - ${UNPACK_TOOL} ${DISTRO_PACK_FILE} - - DISTRO_PACK_DIR=$(tar tJf ${DISTRO_PACK_FILE} | sed -e 's@/.*@@' | uniq) - - ls -l $PWD/${DISTRO_PACK_DIR}/lib/clang-runtimes/ - - echo "DISTRO_PACK_DIR=${DISTRO_PACK_DIR}" - - rm -f ${DISTRO_PACK_FILE} + - *unpack_distro - TARGET_LIBS_PACK_FILE=$(cat target_libs_arch_name) - rm -f target_libs_arch_name - echo "TARGET_LIBS_PACK_FILE=${TARGET_LIBS_PACK_FILE}" @@ -411,6 +414,66 @@ sign_aarch64-apple-darwin: needs: - pack_aarch64-apple-darwin +.prepare_test_app_build: &prepare_test_app_build | + if [ -z "${TEST_APP_IDF_CUSTOM_BRANCH:-}" ]; then + # Use the same idf branch name if exists + git ls-remote https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/espressif/esp-idf.git | grep "refs/heads/$CI_COMMIT_REF_NAME" + test $? -eq 0 && echo "Use IDF branch \"$CI_COMMIT_REF_NAME\"" && TEST_APP_IDF_CUSTOM_BRANCH=$CI_COMMIT_REF_NAME + fi + + # Use custom idf in case custom branch is present + if [ -n "${TEST_APP_IDF_CUSTOM_BRANCH:-}" ]; then + echo "TEST_APP_IDF_CUSTOM_BRANCH=$TEST_APP_IDF_CUSTOM_BRANCH" + #pushd $BUILD_TEST_APP_DIR + # Clone esp-idf + git clone --shallow-submodules --recursive --single-branch --branch $TEST_APP_IDF_CUSTOM_BRANCH -- https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/espressif/esp-idf.git esp-idf + export IDF_PATH=$PWD/esp-idf + # Activate pyenv + if [ $(command -v pyenv) ]; then + source /opt/pyenv/activate + pyenv global $(pyenv versions --bare) + fi + # cannot exec '. ${IDF_PATH}/export.sh' here because not all tools distros are presented + # in the image and `export.sh` fails w/o adding tools to $PATH + idf_exports=$(${IDF_PATH}/tools/idf_tools.py export) || true + eval "${idf_exports}" + #popd + fi + idf.py --version || true + pushd $IDF_PATH/components + git clone --shallow-submodules --recursive --single-branch --branch $TEST_APP_ESP_DSP_CUSTOM_BRANCH -- https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/idf/esp-dsp.git esp-dsp + pushd $PWD/esp-dsp/test_app + +test_esp_dsp: + image: espressif/idf:latest + tags: [ "amd64", "build" ] + allow_failure: true + artifacts: + paths: + - ${BUILD_DIR}/*.log + when: always + expire_in: 1 day + parallel: + matrix: + - CHIP: esp32p4 + needs: + - job: "pack_x86_64-linux-gnu" + variables: + TEST_APP_IDF_CUSTOM_BRANCH: "master" + TEST_APP_ESP_DSP_CUSTOM_BRANCH: "master" + CONF_HOST: "x86_64-linux-gnu" + UNPACK_TOOL: "tar xJf" + script: + - mkdir -p $PWD/${BUILD_DIR} + - export BUILD_LOG=$PWD/${BUILD_DIR}/build.log + - *unpack_distro + - export PATH=$PWD/${DISTRO_PACK_DIR}/bin:${PATH} + - which clang + - *prepare_test_app_build + - export IDF_TOOLCHAIN=clang + - idf.py set-target ${CHIP} 2>&1 | tee ${BUILD_LOG} + - idf.py build 2>&1 | tee -a ${BUILD_LOG} + upload_to_http: stage: private_deploy when: manual From 8e1d87c14ce080222e4167de9ce493b275b2135a Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 27 Aug 2024 17:45:55 +0300 Subject: [PATCH 259/261] [RISCV] Fix registers class for esp32p4 HW loop instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td | 6 +++--- llvm/test/MC/RISCV/esp32p4-hwlp-valid.s | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td index 55eb4326575c28..95b4bbd5d58b30 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td @@ -41,7 +41,7 @@ def ESP_LP_SETUPI: Esp32P4Inst<(outs), (ins uimm1:$id, uimm12:$count, uimm10_ste let Inst{0} = 1; } -def ESP_LP_SETUP: Esp32P4Inst<(outs), (ins uimm1:$id, GPRPIE:$rs1, uimm13_step4:$offset), +def ESP_LP_SETUP: Esp32P4Inst<(outs), (ins uimm1:$id, GPR:$rs1, uimm13_step4:$offset), "esp.lp.setup\t $id, $rs1, $offset", []> { bits<1> id; @@ -145,7 +145,7 @@ def ESP_LP_COUNTI: Esp32P4Inst<(outs), (ins uimm1:$id, uimm12:$count), let Inst{0} = 1; } -def ESP_LP_COUNT: Esp32P4Inst<(outs), (ins uimm1:$id, GPRPIE:$rs1), +def ESP_LP_COUNT: Esp32P4Inst<(outs), (ins uimm1:$id, GPR:$rs1), "esp.lp.count\t $id, $rs1", []> { bits<1> id; @@ -156,7 +156,7 @@ def ESP_LP_COUNT: Esp32P4Inst<(outs), (ins uimm1:$id, GPRPIE:$rs1), let hasSideEffects = 1; let Inst{31-20} = 0xb000000000000; - let Inst{19-15} = 0xb00000; + let Inst{19-15} = rs1{4-0}; let Inst{14} = 0; let Inst{13} = 1; let Inst{12} = 0; diff --git a/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s b/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s index f2d8e11550ec89..a9205f3b590a86 100644 --- a/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s +++ b/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s @@ -9,7 +9,7 @@ dl_hwlp_test: esp.lp.counti 0, 4000 # CHECK: esp.lp.counti 0, 4000 # encoding: [0x2b,0x30,0x00,0xfa] esp.lp.count 0, a1 -# CHECK: esp.lp.count 0, a1 # encoding: [0x2b,0x20,0x00,0x00] +# CHECK: esp.lp.count 0, a1 # encoding: [0x2b,0xa0,0x05,0x00] esp.lp.setupi 0, 1234, loop_last_instruction # CHECK: esp.lp.setupi 0, 1234, loop_last_instruction # encoding: [0x2b'A',0x50'A',0x20'A',0x4d'A'] # lp.setup 0, a1, loop_last_instruction From 8af78ed9719e0024843b2965372feb3fae6884eb Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Wed, 11 Sep 2024 01:57:28 +0300 Subject: [PATCH 260/261] [Xtensa] Fix atomic store operands order It was changed in LLVM 18 --- llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 6 +- llvm/test/CodeGen/Xtensa/atomic-load-store.ll | 107 ++++++++++++++++++ 2 files changed, 110 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/Xtensa/atomic-load-store.ll diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 76e161b6f23584..cb0986fac161ab 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -1845,9 +1845,9 @@ def : Pat<(i32 (atomic_load_8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>; def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>; def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>; -def : Pat<(atomic_store_8 addr_ish1:$addr, AR:$t), (S8I AR:$t, addr_ish1:$addr)>; -def : Pat<(atomic_store_16 addr_ish2:$addr, AR:$t), (S16I AR:$t, addr_ish2:$addr)>; -def : Pat<(atomic_store_32 addr_ish4:$addr, AR:$t), (S32I AR:$t, addr_ish4:$addr)>; +def : Pat<(atomic_store_8 AR:$t, addr_ish1:$addr), (S8I AR:$t, addr_ish1:$addr)>; +def : Pat<(atomic_store_16 AR:$t, addr_ish2:$addr), (S16I AR:$t, addr_ish2:$addr)>; +def : Pat<(atomic_store_32 AR:$t, addr_ish4:$addr), (S32I AR:$t, addr_ish4:$addr)>; let usesCustomInserter = 1, Predicates = [HasS32C1I] in { def ATOMIC_CMP_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap), diff --git a/llvm/test/CodeGen/Xtensa/atomic-load-store.ll b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll new file mode 100644 index 00000000000000..8047fd2914d219 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll @@ -0,0 +1,107 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA,XTENSA_OPT +; RUN: llc -mtriple=xtensa -O0 < %s | FileCheck %s --check-prefixes=XTENSA,XTENSA_OPT_NONE + +define void @store32(ptr %ptr, i32 %val1) { +; XTENSA-LABEL: store32: +; XTENSA: entry a1, 32 +; XTENSA-NEXT: memw +; XTENSA-NEXT: s32i.n a3, a2, 0 +; XTENSA-NEXT: memw +; XTENSA-NEXT: retw.n + store atomic i32 %val1, ptr %ptr seq_cst, align 4 + ret void +} + +define i32 @load32(ptr %ptr) { +; XTENSA-LABEL: load32: +; XTENSA: entry a1, 32 +; XTENSA-NEXT: l32i.n a2, a2, 0 +; XTENSA-NEXT: memw +; XTENSA-NEXT: retw.n + %val = load atomic i32, ptr %ptr seq_cst, align 4 + ret i32 %val +} + +define i8 @load8(ptr %p) { +; XTENSA-LABEL: load8: +; XTENSA: entry a1, 32 +; XTENSA-NEXT: l8ui a2, a2, 0 +; XTENSA-NEXT: memw +; XTENSA-NEXT: retw.n + %v = load atomic i8, ptr %p seq_cst, align 1 + ret i8 %v +} + +define void @store8(ptr %p, i8 %val1) { +; XTENSA_OPT-LABEL: store8: +; XTENSA_OPT: entry a1, 32 +; XTENSA_OPT-NEXT: memw +; XTENSA_OPT-NEXT: s8i a3, a2, 0 +; XTENSA_OPT-NEXT: memw +; XTENSA_OPT-NEXT: retw.n +; +; XTENSA_OPT_NONE-LABEL: store8: +; XTENSA_OPT_NONE: entry a1, 32 +; XTENSA_OPT_NONE-NEXT: # kill: def $a8 killed $a3 +; XTENSA_OPT_NONE-NEXT: memw +; XTENSA_OPT_NONE-NEXT: s8i a3, a2, 0 +; XTENSA_OPT_NONE-NEXT: memw +; XTENSA_OPT_NONE-NEXT: retw.n + store atomic i8 %val1, ptr %p seq_cst, align 1 + ret void +} + +define i16 @load16(ptr %p) { +; XTENSA-LABEL: load16: +; XTENSA: entry a1, 32 +; XTENSA-NEXT: l16ui a2, a2, 0 +; XTENSA-NEXT: memw +; XTENSA-NEXT: retw.n + %v = load atomic i16, ptr %p seq_cst, align 2 + ret i16 %v +} + +define void @store16(ptr %p, i16 %val1) { +; XTENSA_OPT-LABEL: store16: +; XTENSA_OPT: entry a1, 32 +; XTENSA_OPT-NEXT: memw +; XTENSA_OPT-NEXT: s16i a3, a2, 0 +; XTENSA_OPT-NEXT: memw +; XTENSA_OPT-NEXT: retw.n +; +; XTENSA_OPT_NONE-LABEL: store16: +; XTENSA_OPT_NONE: entry a1, 32 +; XTENSA_OPT_NONE-NEXT: # kill: def $a8 killed $a3 +; XTENSA_OPT_NONE-NEXT: memw +; XTENSA_OPT_NONE-NEXT: s16i a3, a2, 0 +; XTENSA_OPT_NONE-NEXT: memw +; XTENSA_OPT_NONE-NEXT: retw.n + store atomic i16 %val1, ptr %p seq_cst, align 2 + ret void +} + +define void @test1(ptr %ptr1, ptr %ptr2) { +; XTENSA-LABEL: test1: +; XTENSA: entry a1, 32 +; XTENSA-NEXT: l8ui a8, a2, 0 +; XTENSA-NEXT: s8i a8, a3, 0 +; XTENSA-NEXT: retw.n + %val = load atomic i8, ptr %ptr1 unordered, align 1 + store atomic i8 %val, ptr %ptr2 unordered, align 1 + ret void +} + +define void @test2(ptr %ptr1, ptr %ptr2) { +; XTENSA-LABEL: test2: +; XTENSA: entry a1, 32 +; XTENSA-NEXT: l8ui a8, a2, 0 +; XTENSA-NEXT: memw +; XTENSA-NEXT: memw +; XTENSA-NEXT: s8i a8, a3, 0 +; XTENSA-NEXT: memw +; XTENSA-NEXT: retw.n + %val = load atomic i8, ptr %ptr1 seq_cst, align 1 + store atomic i8 %val, ptr %ptr2 seq_cst, align 1 + ret void +} From 7da625481b2265d8da3f08a772e6f442544225ab Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Wed, 11 Sep 2024 16:19:02 +0300 Subject: [PATCH 261/261] esp/ci: Use IDF from docker image for esp-dsp test build --- .gitlab-ci.yml | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index ad3a371c941a7d..6d9eaa9138a5b9 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -415,16 +415,9 @@ sign_aarch64-apple-darwin: - pack_aarch64-apple-darwin .prepare_test_app_build: &prepare_test_app_build | - if [ -z "${TEST_APP_IDF_CUSTOM_BRANCH:-}" ]; then - # Use the same idf branch name if exists - git ls-remote https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/espressif/esp-idf.git | grep "refs/heads/$CI_COMMIT_REF_NAME" - test $? -eq 0 && echo "Use IDF branch \"$CI_COMMIT_REF_NAME\"" && TEST_APP_IDF_CUSTOM_BRANCH=$CI_COMMIT_REF_NAME - fi - # Use custom idf in case custom branch is present if [ -n "${TEST_APP_IDF_CUSTOM_BRANCH:-}" ]; then echo "TEST_APP_IDF_CUSTOM_BRANCH=$TEST_APP_IDF_CUSTOM_BRANCH" - #pushd $BUILD_TEST_APP_DIR # Clone esp-idf git clone --shallow-submodules --recursive --single-branch --branch $TEST_APP_IDF_CUSTOM_BRANCH -- https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/espressif/esp-idf.git esp-idf export IDF_PATH=$PWD/esp-idf @@ -437,7 +430,6 @@ sign_aarch64-apple-darwin: # in the image and `export.sh` fails w/o adding tools to $PATH idf_exports=$(${IDF_PATH}/tools/idf_tools.py export) || true eval "${idf_exports}" - #popd fi idf.py --version || true pushd $IDF_PATH/components @@ -459,7 +451,8 @@ test_esp_dsp: needs: - job: "pack_x86_64-linux-gnu" variables: - TEST_APP_IDF_CUSTOM_BRANCH: "master" + # use IDF 'master' from docker image + TEST_APP_IDF_CUSTOM_BRANCH: "" TEST_APP_ESP_DSP_CUSTOM_BRANCH: "master" CONF_HOST: "x86_64-linux-gnu" UNPACK_TOOL: "tar xJf"