From b8a8713f961c212f1734655d15f140b126056db0 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 20 Jul 2023 16:35:43 +0800 Subject: [PATCH] feat(clk): Add support to get xtaL freq for ESP32P4 --- .../port/esp32p4/esp_clk_tree.c | 36 +++++++++++++ .../soc/esp32h2/include/soc/clk_tree_defs.h | 4 +- .../soc/esp32p4/include/soc/clk_tree_defs.h | 52 ++++++++++++++----- 3 files changed, 76 insertions(+), 16 deletions(-) diff --git a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c index e69de29bb2d..3a1c3598b3d 100644 --- a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_clk_tree.h" +#include "esp_err.h" +#include "esp_check.h" +#include "soc/rtc.h" + +static const char *TAG = "esp_clk_tree"; + +// TODO: IDF-7526 +esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, +uint32_t *freq_value) +{ + ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src"); + ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision"); + ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + + uint32_t clk_src_freq = 0; + switch (clk_src) { + case SOC_MOD_CLK_XTAL: + clk_src_freq = 40 * MHZ; + break; + default: + break; + } + + ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG, + "freq shouldn't be 0, calibration failed"); + *freq_value = clk_src_freq; + return ESP_OK; +} diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h index 39a6b9d6db3..6fbb9325250 100644 --- a/components/soc/esp32h2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h @@ -122,9 +122,9 @@ typedef enum { */ typedef enum { // For CPU domain - SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or PLL2 by configuring soc_cpu_clk_src_t */ + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or FLASH_PLL by configuring soc_cpu_clk_src_t */ // For RTC domain - SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */ SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */ // For digital domain: peripherals, WIFI, BLE SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */ diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index e6a690eb8b6..5450aaa3bf0 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -37,13 +37,26 @@ extern "C" { * * 6) External Slow Clock (optional): OSC_SLOW * - * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the + * A slow clock signal generated by an external circuit can be connected to GPIO1 to be the clock source for the * RTC_SLOW_CLK. * * OSC_SLOW_CLK can also be calibrated to get its exact frequency. + * + * + * PLL Clocks: + * + * from 40MHz XTAL oscillator frequency multipliers: + * 1) CPLL (400MHz), used for CPU clock source + * 2) MPLL (500MHz), used for MSPI-PSRAM clock source; and is further divided to PLL_F50M, PLL_F25M, to be used for peripheral's clock sources + * 3) SPLL (480MHz), directly used for MSPI-Flash, MSPI-PSRAM, GPSPI clock sources; and is further divided to PLL_F240M, PLL_F160M, PLL_F120M, PLL_F80M, PLL_F20M, to be used for peripherals' clock sources + * 4) APLL (configurable), can be the clock source for peripherals (GPSPI, I2S, LCD, CAM, etc.) + * 5) SDIO_PLL0/1/2 + * + * from 32kHz slow clock oscillator frequency multiplier: + * 6) LP_PLL (8MHz), used for RTC_FAST_CLK clock source and LP peripherals' clock sources */ -/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ +/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ // TODO: check #define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ #define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ #define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ @@ -63,7 +76,7 @@ typedef enum { SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ - SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ + SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin1 */ } soc_root_clk_t; /** @@ -72,7 +85,7 @@ typedef enum { */ typedef enum { SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select (C)PLL_CLK as CPU_CLK source (CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 400MHz) */ SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ } soc_cpu_clk_src_t; @@ -95,13 +108,24 @@ typedef enum { */ typedef enum { SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ - SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ - SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_XTAL = 1, /*!< Select XTAL_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL` */ + SOC_RTC_FAST_CLK_SRC_LP_PLL = 2, /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K) */ SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; +/** + * @brief LP_PLL_CLK mux inputs, which are the supported clock sources for the LP_PLL_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_LP_PLL_CLK_SRC_RC32K = 0, /*!< Select RC32K_CLK as LP_PLL_CLK source */ + SOC_LP_PLL_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as LP_PLL_CLK source */ + SOC_LP_PLL_CLK_SRC_INVALID, /*!< Invalid LP_PLL_CLK source */ +} soc_lp_pll_clk_src_t; + // Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] -// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// {[upstream]clock_name}: XTAL, (S/M/A)PLL, etc. // [attr] - optional: FAST, SLOW, D, F /** * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) @@ -110,14 +134,14 @@ typedef enum { */ typedef enum { // For CPU domain - SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, CPLL, or RC_FAST by configuring soc_cpu_clk_src_t */ // For RTC domain - SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */ SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ - // For digital domain: peripherals, WIFI, BLE - SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ - SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ - SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + // For digital domain: peripherals + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ + SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from SPLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */