From e732b2debbcab4769f9bd2340502d13e5a327152 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Wed, 17 Jul 2024 09:52:43 +0000 Subject: [PATCH] Remove `core-isa-parser` package, prepare to transfer packages (#41) * Derive `serde` traits for `core-isa-parser` types, serialize parsed ISA config to TOML files * Remove the `core-isa-parser` package entirely * Fix some warnings in `xtensa-lx-rt` * Add notice to `README.md` stating that the packages have moved --- .gitmodules | 3 - README.md | 14 +- core-isa-parser/Cargo.toml | 18 - core-isa-parser/src/lib.rs | 130 -- core-isa-parser/xtensa-overlays | 1 - xtensa-lx-rt/Cargo.toml | 8 +- xtensa-lx-rt/build.rs | 134 +- xtensa-lx-rt/config/xtensa_esp32.toml | 1337 ++++++++++++++++++++ xtensa-lx-rt/config/xtensa_esp32s2.toml | 1475 +++++++++++++++++++++++ xtensa-lx-rt/config/xtensa_esp32s3.toml | 1409 ++++++++++++++++++++++ xtensa-lx-rt/src/lib.rs | 11 +- 11 files changed, 4335 insertions(+), 205 deletions(-) delete mode 100644 .gitmodules delete mode 100644 core-isa-parser/Cargo.toml delete mode 100644 core-isa-parser/src/lib.rs delete mode 160000 core-isa-parser/xtensa-overlays create mode 100644 xtensa-lx-rt/config/xtensa_esp32.toml create mode 100644 xtensa-lx-rt/config/xtensa_esp32s2.toml create mode 100644 xtensa-lx-rt/config/xtensa_esp32s3.toml diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index 196a4aa..0000000 --- a/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "core-isa-parser/xtensa-overlays"] - path = core-isa-parser/xtensa-overlays - url = https://github.com/espressif/xtensa-overlays.git diff --git a/README.md b/README.md index 2da6ee9..61cda63 100644 --- a/README.md +++ b/README.md @@ -1,18 +1,22 @@ # xtensa-lx crates +--- + +## This project has moved! It can now be found in the [esp-rs/esp-hal](https://github.com/esp-rs/esp-hal/) repository. + +--- + This repository contains various crates useful for writing Rust programs on xtensa-lx microcontrollers: -* [`xtensa-lx`]: CPU peripheral access and intrinsics. -* [`xtensa-lx-rt`]: Startup code and interrupt handling. -* [`core-isa-parser`]: A parser for XCHAL ISA configuration files. +- [`xtensa-lx`]: CPU peripheral access and intrinsics. +- [`xtensa-lx-rt`]: Startup code and interrupt handling. [`xtensa-lx`]: https://crates.io/crates/xtensa-lx [`xtensa-lx-rt`]: https://crates.io/crates/xtensa-lx-rt -[`core-isa-parser`]: https://crates.io/crates/core-isa-parser ### Contribution Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any -additional terms or conditions. \ No newline at end of file +additional terms or conditions. diff --git a/core-isa-parser/Cargo.toml b/core-isa-parser/Cargo.toml deleted file mode 100644 index 22aef12..0000000 --- a/core-isa-parser/Cargo.toml +++ /dev/null @@ -1,18 +0,0 @@ -[package] -name = "core-isa-parser" -version = "0.2.0" -authors = [ - "Jesse Braham ", - "Björn Quentin ", -] -edition = "2021" -description = "Parse the core-isa.h headers from Espressif's xtensa-overlays repository" -repository = "https://github.com/esp-rs/xtensa-lx-rt" -license = "MIT OR Apache-2.0" - -[dependencies] -anyhow = "1.0" -enum-as-inner = "0.4.0" -regex = "1.5" -strum = "0.24.0" -strum_macros = "0.24.0" diff --git a/core-isa-parser/src/lib.rs b/core-isa-parser/src/lib.rs deleted file mode 100644 index bcf66d6..0000000 --- a/core-isa-parser/src/lib.rs +++ /dev/null @@ -1,130 +0,0 @@ -//! Parse the core-isa.h headers from Espressif's xtensa-overlays repository. -//! -//! - -use std::{collections::HashMap, env, fs, path::PathBuf, str::FromStr}; - -use anyhow::Result; -use enum_as_inner::EnumAsInner; -use regex::Regex; -use strum_macros::{Display, EnumIter, EnumString}; - -/// The chips which are present in the xtensa-overlays repository -/// -/// When `.to_string()` is called on a variant, the resulting string is the path -/// to the chip's corresponding directory. -#[derive(Debug, Clone, Copy, PartialEq, Display, EnumIter)] -pub enum Chip { - #[strum(to_string = "xtensa_esp32")] - Esp32, - #[strum(to_string = "xtensa_esp32s2")] - Esp32s2, - #[strum(to_string = "xtensa_esp32s3")] - Esp32s3, -} - -impl Chip { - fn core_isa_path(&self) -> Result { - let path = PathBuf::from(env!("CARGO_MANIFEST_DIR")) - .join("xtensa-overlays") - .join(self.to_string()) - .join("newlib/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h") - .canonicalize()?; - - Ok(path) - } -} - -/// The valid interrupt types declared in the `core-isa.h` headers -#[derive(Debug, Clone, Copy, PartialEq, EnumString)] -pub enum InterruptType { - #[strum(serialize = "XTHAL_INTTYPE_EXTERN_EDGE")] - ExternEdge, - #[strum(serialize = "XTHAL_INTTYPE_EXTERN_LEVEL")] - ExternLevel, - #[strum(serialize = "XTHAL_INTTYPE_NMI")] - Nmi, - #[strum(serialize = "XTHAL_INTTYPE_PROFILING")] - Profiling, - #[strum(serialize = "XTHAL_INTTYPE_SOFTWARE")] - Software, - #[strum(serialize = "XTHAL_INTTYPE_TIMER")] - Timer, - #[strum(serialize = "XTHAL_TIMER_UNCONFIGURED")] - TimerUnconfigured, -} - -/// The allowable value types for definitions -#[derive(Debug, Clone, PartialEq, EnumAsInner)] -pub enum Value { - Integer(i64), - Interrupt(InterruptType), - String(String), -} - -/// Parse the configuration for the given chip -/// -/// Returns a hashmap with the definition identifiers as keys and the -/// corresponding parsed values as values. -pub fn get_config(chip: Chip) -> Result> { - let re_define = Regex::new(r"^#define[\s]+([a-zA-Z\d_]+)[\s]+([^\s]+)")?; - let re_ident = Regex::new(r"^[a-zA-Z\d_]+$")?; - let re_string = Regex::new(r#""([^"]+)""#)?; - - // Iterate through each line containing a definition. Attempt to match the - // various components and map identifiers to values. - let mut map: HashMap = HashMap::new(); - for define in find_all_defines(chip)? { - if !re_define.is_match(&define) { - println!("Define not matched: {}", define); - continue; - } - - let captures = re_define.captures(&define).unwrap(); - let identifier = captures.get(1).unwrap().as_str().to_string(); - let value = captures.get(2).unwrap().as_str().to_string(); - - let value = if let Ok(integer) = value.parse::() { - // Decimal integer literal - Value::Integer(integer) - } else if let Ok(integer) = i64::from_str_radix(&value.replace("0x", ""), 16) { - // Hexadecimal integer literal - Value::Integer(integer) - } else if let Ok(interrupt) = InterruptType::from_str(&value) { - // Interrupt type - Value::Interrupt(interrupt) - } else if re_string.is_match(&value) { - // String - Value::String(value.replace("\"", "")) - } else if re_ident.is_match(&value) && map.contains_key(&value) { - // Identifier - map.get(&value).unwrap().to_owned() - } else { - // We will handle this particular case after, so no need to report it. - if chip != Chip::Esp32 && identifier != "XCHAL_USE_MEMCTL" { - println!("Unable to process definition: {} = {}", identifier, value); - } - continue; - }; - - map.insert(identifier, value); - } - - Ok(map) -} - -fn find_all_defines(chip: Chip) -> Result> { - let path = chip.core_isa_path()?; - let lines = fs::read_to_string(path)? - .lines() - .filter_map(|line| { - if line.starts_with("#define") { - Some(line.to_string()) - } else { - None - } - }) - .collect::>(); - - Ok(lines) -} diff --git a/core-isa-parser/xtensa-overlays b/core-isa-parser/xtensa-overlays deleted file mode 160000 index dd1cf19..0000000 --- a/core-isa-parser/xtensa-overlays +++ /dev/null @@ -1 +0,0 @@ -Subproject commit dd1cf19f6eb327a9db51043439974a6de13f5c7f diff --git a/xtensa-lx-rt/Cargo.toml b/xtensa-lx-rt/Cargo.toml index dcf62f8..a013c86 100644 --- a/xtensa-lx-rt/Cargo.toml +++ b/xtensa-lx-rt/Cargo.toml @@ -20,8 +20,12 @@ r0 = "1.0.0" xtensa-lx = { version = "0.9.0", path = "../xtensa-lx" } [build-dependencies] -core-isa-parser = { version = "0.2.0", path = "../core-isa-parser" } -minijinja = "1.0.16" +anyhow = "1.0.86" +enum-as-inner = "0.6.0" +minijinja = "2.0.3" +serde = { version = "1.0.204", features = ["derive"] } +strum = { version = "0.26.3", features = ["derive"] } +toml = "0.8.10" [features] ## Save and restore float registers for exceptions diff --git a/xtensa-lx-rt/build.rs b/xtensa-lx-rt/build.rs index a5dabc2..0997eab 100644 --- a/xtensa-lx-rt/build.rs +++ b/xtensa-lx-rt/build.rs @@ -1,33 +1,76 @@ use std::{ collections::{HashMap, HashSet}, env, - fs::File, + fs::{self, File}, io::Write, path::PathBuf, }; -use core_isa_parser::{get_config, Chip, Value}; +use anyhow::Result; +use enum_as_inner::EnumAsInner; use minijinja::{context, Environment}; +use serde::Deserialize; +use strum::{Display, EnumIter, EnumString}; + +/// The chips which are present in the xtensa-overlays repository +/// +/// When `.to_string()` is called on a variant, the resulting string is the path +/// to the chip's corresponding directory. +#[derive(Debug, Clone, Copy, PartialEq, Display, EnumIter, Deserialize)] +enum Chip { + #[strum(to_string = "xtensa_esp32")] + Esp32, + #[strum(to_string = "xtensa_esp32s2")] + Esp32s2, + #[strum(to_string = "xtensa_esp32s3")] + Esp32s3, +} + +/// The valid interrupt types declared in the `core-isa.h` headers +#[derive(Debug, Clone, Copy, PartialEq, EnumString, Deserialize)] +enum InterruptType { + #[strum(serialize = "XTHAL_INTTYPE_EXTERN_EDGE")] + ExternEdge, + #[strum(serialize = "XTHAL_INTTYPE_EXTERN_LEVEL")] + ExternLevel, + #[strum(serialize = "XTHAL_INTTYPE_NMI")] + Nmi, + #[strum(serialize = "XTHAL_INTTYPE_PROFILING")] + Profiling, + #[strum(serialize = "XTHAL_INTTYPE_SOFTWARE")] + Software, + #[strum(serialize = "XTHAL_INTTYPE_TIMER")] + Timer, + #[strum(serialize = "XTHAL_TIMER_UNCONFIGURED")] + TimerUnconfigured, +} + +/// The allowable value types for definitions +#[derive(Debug, Clone, PartialEq, EnumAsInner, Deserialize)] +enum Value { + Integer(i64), + Interrupt(InterruptType), + String(String), +} -fn main() { +fn main() -> Result<()> { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); // Put the linker script somewhere the linker can find it - File::create(out.join("link.x")) - .unwrap() - .write_all(include_bytes!("xtensa.in.x")) - .unwrap(); - println!("cargo:rustc-link-search={}", out.display()); - handle_esp32(); + File::create(out.join("link.x"))?.write_all(include_bytes!("xtensa.in.x"))?; + + handle_esp32()?; // Only re-run the build script when xtensa.in.x is changed, // instead of when any part of the source code changes. println!("cargo:rerun-if-changed=xtensa.in.x"); + + Ok(()) } -fn handle_esp32() { +fn handle_esp32() -> Result<()> { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); let rustflags = env::var_os("CARGO_ENCODED_RUSTFLAGS") @@ -67,43 +110,50 @@ fn handle_esp32() { (false, false, true) => Chip::Esp32s3, _ => panic!("Either the esp32, esp32s2, esp32s3 feature must be enabled"), }; - let isa_config = get_config(chip).expect("Unable to parse ISA config"); + + let isa_toml = fs::read_to_string(format!("config/{chip}.toml"))?; + let isa_config: HashMap = toml::from_str(&isa_toml)?; inject_cfgs(&isa_config, &features_to_disable); inject_cpu_cfgs(&isa_config); - generate_exception_x(&out, &isa_config); - generate_interrupt_level_masks(&out, &isa_config); + generate_exception_x(&out, &isa_config)?; + generate_interrupt_level_masks(&out, &isa_config)?; + + Ok(()) } -fn generate_interrupt_level_masks(out: &PathBuf, isa_config: &HashMap) { - let mut env = Environment::new(); +fn generate_interrupt_level_masks( + out: &PathBuf, + isa_config: &HashMap, +) -> Result<()> { let exception_source_template = &include_str!("interrupt_level_masks.rs.jinja")[..]; - env.add_template("interrupt_level_masks.rs", exception_source_template) - .unwrap(); + + let mut env = Environment::new(); + env.add_template("interrupt_level_masks.rs", exception_source_template)?; + let template = env.get_template("interrupt_level_masks.rs").unwrap(); - let exception_source = template - .render(context! { - XCHAL_INTLEVEL1_MASK => isa_config.get("XCHAL_INTLEVEL1_MASK").unwrap().as_integer(), - XCHAL_INTLEVEL2_MASK => isa_config.get("XCHAL_INTLEVEL2_MASK").unwrap().as_integer(), - XCHAL_INTLEVEL3_MASK => isa_config.get("XCHAL_INTLEVEL3_MASK").unwrap().as_integer(), - XCHAL_INTLEVEL4_MASK => isa_config.get("XCHAL_INTLEVEL4_MASK").unwrap().as_integer(), - XCHAL_INTLEVEL5_MASK => isa_config.get("XCHAL_INTLEVEL5_MASK").unwrap().as_integer(), - XCHAL_INTLEVEL6_MASK => isa_config.get("XCHAL_INTLEVEL6_MASK").unwrap().as_integer(), - XCHAL_INTLEVEL7_MASK => isa_config.get("XCHAL_INTLEVEL7_MASK").unwrap().as_integer(), - }) - .unwrap(); - File::create(out.join("interrupt_level_masks.rs")) - .unwrap() - .write_all(exception_source.as_bytes()) - .unwrap(); + let exception_source = template.render(context! { + XCHAL_INTLEVEL1_MASK => isa_config.get("XCHAL_INTLEVEL1_MASK").unwrap().as_integer(), + XCHAL_INTLEVEL2_MASK => isa_config.get("XCHAL_INTLEVEL2_MASK").unwrap().as_integer(), + XCHAL_INTLEVEL3_MASK => isa_config.get("XCHAL_INTLEVEL3_MASK").unwrap().as_integer(), + XCHAL_INTLEVEL4_MASK => isa_config.get("XCHAL_INTLEVEL4_MASK").unwrap().as_integer(), + XCHAL_INTLEVEL5_MASK => isa_config.get("XCHAL_INTLEVEL5_MASK").unwrap().as_integer(), + XCHAL_INTLEVEL6_MASK => isa_config.get("XCHAL_INTLEVEL6_MASK").unwrap().as_integer(), + XCHAL_INTLEVEL7_MASK => isa_config.get("XCHAL_INTLEVEL7_MASK").unwrap().as_integer(), + })?; + + File::create(out.join("interrupt_level_masks.rs"))?.write_all(exception_source.as_bytes())?; + + Ok(()) } -fn generate_exception_x(out: &PathBuf, isa_config: &HashMap) { - let mut env = Environment::new(); +fn generate_exception_x(out: &PathBuf, isa_config: &HashMap) -> Result<()> { let exception_source_template = &include_str!("exception-esp32.x.jinja")[..]; - env.add_template("exception.x", exception_source_template) - .unwrap(); - let template = env.get_template("exception.x").unwrap(); + + let mut env = Environment::new(); + env.add_template("exception.x", exception_source_template)?; + + let template = env.get_template("exception.x")?; let exception_source = template.render( context! { XCHAL_WINDOW_OF4_VECOFS => isa_config.get("XCHAL_WINDOW_OF4_VECOFS").unwrap().as_integer(), @@ -122,11 +172,11 @@ fn generate_exception_x(out: &PathBuf, isa_config: &HashMap) { XCHAL_USER_VECOFS => isa_config.get("XCHAL_USER_VECOFS").unwrap().as_integer(), XCHAL_DOUBLEEXC_VECOFS => isa_config.get("XCHAL_DOUBLEEXC_VECOFS").unwrap().as_integer(), } - ).unwrap(); - File::create(out.join("exception.x")) - .unwrap() - .write_all(exception_source.as_bytes()) - .unwrap(); + )?; + + File::create(out.join("exception.x"))?.write_all(exception_source.as_bytes())?; + + Ok(()) } fn inject_cfgs(isa_config: &HashMap, disabled_features: &HashSet) { diff --git a/xtensa-lx-rt/config/xtensa_esp32.toml b/xtensa-lx-rt/config/xtensa_esp32.toml new file mode 100644 index 0000000..0d719dd --- /dev/null +++ b/xtensa-lx-rt/config/xtensa_esp32.toml @@ -0,0 +1,1337 @@ +[XCHAL_RESET_VECTOR1_PADDR] +Integer = 1073742848 + +[XCHAL_HAVE_DCACHE_DYN_WAYS] +Integer = 0 + +[XCHAL_HAVE_DFPU_SINGLE_ONLY] +Integer = 1 + +[XCHAL_DATARAM0_ECC_PARITY] +Integer = 0 + +[XCHAL_HAVE_HIFI3] +Integer = 0 + +[XCHAL_EXTINT13_NUM] +Integer = 18 + +[XCHAL_HAVE_CP] +Integer = 1 + +[XCHAL_INT20_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INSTROM0_SIZE] +Integer = 4194304 + +[XCHAL_INTTYPE_MASK_EXTERN_EDGE] +Integer = 1346372608 + +[XCHAL_HAVE_XLT_CACHEATTR] +Integer = 0 + +[XCHAL_INT17_LEVEL] +Integer = 1 + +[XCHAL_INTLEVEL3_ANDBELOW_MASK] +Integer = 687783935 + +[XCHAL_INT8_LEVEL] +Integer = 1 + +[XCHAL_SW_VERSION] +Integer = 1100003 + +[XCHAL_HAVE_IMEM_LOADSTORE] +Integer = 1 + +[XCHAL_NUM_WRITEBUFFER_ENTRIES] +Integer = 4 + +[XCHAL_HAVE_FUSION_FP] +Integer = 0 + +[XCHAL_HW_VERSION] +Integer = 260003 + +[XCHAL_DATA_PIPE_DELAY] +Integer = 2 + +[XCHAL_HAVE_FULL_RESET] +Integer = 1 + +[XCHAL_DATARAM0_VADDR] +Integer = 1073217536 + +[XCHAL_INT24_LEVEL] +Integer = 4 + +[XCHAL_HAVE_FP_SQRT] +Integer = 1 + +[XCHAL_NUM_INSTRAM] +Integer = 2 + +[XCHAL_HAVE_DFP_accel] +Integer = 1 + +[XCHAL_INT4_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT9_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_EXTINT7_NUM] +Integer = 9 + +[XCHAL_EXTINT16_NUM] +Integer = 21 + +[XCHAL_INT13_EXTNUM] +Integer = 10 + +[XCHAL_HAVE_VECTOR_SELECT] +Integer = 1 + +[XCHAL_PREFETCH_BLOCK_ENTRIES] +Integer = 0 + +[XCHAL_PREFETCH_CASTOUT_LINES] +Integer = 0 + +[XCHAL_INT28_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_INT0_EXTNUM] +Integer = 0 + +[XCHAL_BUILD_UNIQUE_ID] +Integer = 392854 + +[XCHAL_HAVE_DCACHE_TEST] +Integer = 0 + +[XCHAL_INTLEVEL1_MASK] +Integer = 407551 + +[XCHAL_HAVE_DEBUG_EXTERN_INT] +Integer = 1 + +[XCHAL_HAVE_DFP_RECIP] +Integer = 0 + +[XCHAL_EXTINT8_NUM] +Integer = 10 + +[XCHAL_INTLEVEL3_MASK] +Integer = 683706368 + +[XCHAL_DCACHE_ACCESS_SIZE] +Integer = 1 + +[XCHAL_INT3_LEVEL] +Integer = 1 + +[XCHAL_INT8_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT3_EXTNUM] +Integer = 3 + +[XCHAL_INTLEVEL2_MASK] +Integer = 3670016 + +[XCHAL_INT11_TYPE] +Interrupt = "Profiling" + +[XCHAL_HAVE_BOOTLOADER] +Integer = 0 + +[XCHAL_VECBASE_RESET_VADDR] +Integer = 1073741824 + +[XCHAL_INTLEVEL3_VECTOR_PADDR] +Integer = 1073742272 + +[XCHAL_INTLEVEL4_VECOFS] +Integer = 512 + +[XCHAL_DOUBLEEXC_VECTOR_PADDR] +Integer = 1073742784 + +[XCHAL_INTTYPE_MASK_TIMER] +Integer = 98368 + +[XCHAL_XEA_VERSION] +Integer = 2 + +[XCHAL_EXTINT24_NUM] +Integer = 30 + +[XCHAL_USER_VECOFS] +Integer = 832 + +[XCHAL_HAVE_OCD] +Integer = 1 + +[XCHAL_INTLEVEL2_VECTOR_PADDR] +Integer = 1073742208 + +[XCHAL_HW_REL_LX6] +Integer = 1 + +[XCHAL_NUM_XLMI] +Integer = 1 + +[XCHAL_HAVE_HIGHPRI_INTERRUPTS] +Integer = 1 + +[XCHAL_INT29_LEVEL] +Integer = 3 + +[XCHAL_INT28_LEVEL] +Integer = 4 + +[XCHAL_EXTINT19_NUM] +Integer = 24 + +[XCHAL_TIMER3_INTERRUPT] +Interrupt = "TimerUnconfigured" + +[XCHAL_RESET_VECTOR_VADDR] +Integer = 1073742848 + +[XCHAL_HAVE_HIFI_MINI] +Integer = 0 + +[XCHAL_INTLEVEL3_VECTOR_VADDR] +Integer = 1073742272 + +[XCHAL_INTLEVEL5_VECOFS] +Integer = 576 + +[XCHAL_HAVE_TAP_MASTER] +Integer = 0 + +[XCHAL_INT9_EXTNUM] +Integer = 7 + +[XCHAL_EXTINT25_NUM] +Integer = 31 + +[XCHAL_INT14_LEVEL] +Integer = 7 + +[XCHAL_INT30_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_INSTRAM0_VADDR] +Integer = 1073741824 + +[XCHAL_INT14_TYPE] +Interrupt = "Nmi" + +[XCHAL_ICACHE_ACCESS_SIZE] +Integer = 1 + +[XCHAL_HAVE_SPECULATION] +Integer = 0 + +[XCHAL_INT20_LEVEL] +Integer = 2 + +[XCHAL_HAVE_VECTRALX] +Integer = 0 + +[XCHAL_DATARAM0_BANKS] +Integer = 1 + +[XCHAL_INT27_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HW_VERSION_MINOR] +Integer = 3 + +[XCHAL_CP_MAXCFG] +Integer = 8 + +[XCHAL_ICACHE_ECC_PARITY] +Integer = 0 + +[XCHAL_INSTRAM0_ECC_PARITY] +Integer = 0 + +[XCHAL_INT14_EXTNUM] +Integer = 11 + +[XCHAL_INT18_EXTNUM] +Integer = 13 + +[XCHAL_RESET_VECTOR0_VADDR] +Integer = 1342177280 + +[XCHAL_USER_VECTOR_VADDR] +Integer = 1073742656 + +[XCHAL_TRAX_TIME_WIDTH] +Integer = 0 + +[XCHAL_DCACHE_IS_COHERENT] +Integer = 0 + +[XCHAL_INT22_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_HAVE_DFP_ACCEL] +Integer = 1 + +[XCHAL_NUM_LOADSTORE_UNITS] +Integer = 1 + +[XCHAL_HAVE_BSP3_TRANSPOSE] +Integer = 0 + +[XCHAL_DEBUG_VECTOR_PADDR] +Integer = 1073742464 + +[XCHAL_DATARAM1_VADDR] +Integer = 1065353216 + +[XCHAL_HAVE_SSP16] +Integer = 0 + +[XCHAL_INSTRAM1_SIZE] +Integer = 4194304 + +[XCHAL_PREFETCH_ENTRIES] +Integer = 0 + +[XCHAL_INT26_LEVEL] +Integer = 5 + +[XCHAL_INTLEVEL7_VECTOR_PADDR] +Integer = 1073742528 + +[XCHAL_INTTYPE_MASK_SOFTWARE] +Integer = 536871040 + +[XCHAL_HAVE_BE] +Integer = 0 + +[XCHAL_HAVE_PREDICTED_BRANCHES] +Integer = 0 + +[XCHAL_ICACHE_LINEWIDTH] +Integer = 2 + +[XCHAL_CLOCK_GATING_GLOBAL] +Integer = 1 + +[XCHAL_HAVE_ABS] +Integer = 1 + +[XCHAL_HAVE_FUSION] +Integer = 0 + +[XCHAL_HAVE_PIF] +Integer = 1 + +[XCHAL_INSTRAM1_VADDR] +Integer = 1077936128 + +[XCHAL_HAVE_DFP] +Integer = 0 + +[XCHAL_HAVE_GRIVPEP] +Integer = 0 + +[XCHAL_NUM_MISC_REGS] +Integer = 4 + +[XCHAL_ICACHE_LINESIZE] +Integer = 4 + +[XCHAL_INTLEVEL4_MASK] +Integer = 1392508928 + +[XCHAL_INT18_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_XLMI0_ECC_PARITY] +Integer = 0 + +[XCHAL_INT29_TYPE] +Interrupt = "Software" + +[XCHAL_HAVE_DEBUG] +Integer = 1 + +[XCHAL_INTLEVEL1_ANDBELOW_MASK] +Integer = 407551 + +[XCHAL_INTTYPE_MASK_NMI] +Integer = 16384 + +[XCHAL_HAVE_TURBO16] +Integer = 0 + +[XCHAL_TIMER0_INTERRUPT] +Integer = 6 + +[XCHAL_INT25_LEVEL] +Integer = 4 + +[XCHAL_INT3_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_EXTINT10_NUM] +Integer = 13 + +[XCHAL_EXTINT18_NUM] +Integer = 23 + +[XCHAL_INT5_EXTNUM] +Integer = 5 + +[XCHAL_HAVE_THREADPTR] +Integer = 1 + +[XCHAL_INT31_EXTNUM] +Integer = 25 + +[XCHAL_RESET_VECTOR_PADDR] +Integer = 1073742848 + +[XCHAL_DOUBLEEXC_VECTOR_VADDR] +Integer = 1073742784 + +[XCHAL_INTLEVEL4_VECTOR_PADDR] +Integer = 1073742336 + +[XCHAL_INT22_LEVEL] +Integer = 3 + +[XCHAL_HW_MAX_VERSION_MAJOR] +Integer = 2600 + +[XCHAL_INT30_EXTNUM] +Integer = 24 + +[XCHAL_INT25_EXTNUM] +Integer = 20 + +[XCHAL_HAVE_FUSION_BITOPS] +Integer = 0 + +[XCHAL_DATARAM1_PADDR] +Integer = 1065353216 + +[XCHAL_DATARAM0_SIZE] +Integer = 524288 + +[XCHAL_INTLEVEL2_ANDBELOW_MASK] +Integer = 4077567 + +[XCHAL_INT6_TYPE] +Interrupt = "Timer" + +[XCHAL_INT23_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_FUSION_LFSR_CRC] +Integer = 0 + +[XCHAL_INT5_LEVEL] +Integer = 1 + +[XCHAL_HAVE_BBE16_RSQRT] +Integer = 0 + +[XCHAL_CA_BITS] +Integer = 4 + +[XCHAL_HAVE_CALL4AND12] +Integer = 1 + +[XCHAL_HAVE_GRIVPEP_HISTOGRAM] +Integer = 0 + +[XCHAL_INTTYPE_MASK_EXTERN_LEVEL] +Integer = 2411606847 + +[XCHAL_EXTINT20_NUM] +Integer = 25 + +[XCHAL_DCACHE_ECC_PARITY] +Integer = 0 + +[XCHAL_NUM_DATAROM] +Integer = 1 + +[XCHAL_INTLEVEL7_ANDBELOW_MASK] +Integer = 4294967295 + +[XCHAL_NMI_INTERRUPT] +Integer = 14 + +[XCHAL_INT2_EXTNUM] +Integer = 2 + +[XCHAL_HAVE_XEAX] +Integer = 0 + +[XCHAL_ICACHE_SETWIDTH] +Integer = 0 + +[XCHAL_INSTRAM1_PADDR] +Integer = 1077936128 + +[XCHAL_HW_MIN_VERSION_MINOR] +Integer = 3 + +[XCHAL_INT13_LEVEL] +Integer = 1 + +[XCHAL_TIMER1_INTERRUPT] +Integer = 15 + +[XCHAL_EXTINT23_NUM] +Integer = 28 + +[XCHAL_INT12_EXTNUM] +Integer = 9 + +[XCHAL_INT27_EXTNUM] +Integer = 22 + +[XCHAL_WINDOW_UF4_VECOFS] +Integer = 64 + +[XCHAL_WINDOW_VECTORS_PADDR] +Integer = 1073741824 + +[XCHAL_HAVE_MUL32_HIGH] +Integer = 1 + +[XCHAL_UNALIGNED_STORE_HW] +Integer = 1 + +[XCHAL_INTLEVEL5_VECTOR_VADDR] +Integer = 1073742400 + +[XCHAL_EXTINT11_NUM] +Integer = 14 + +[XCHAL_INTLEVEL6_VECOFS] +Integer = 640 + +[XCHAL_EXTINT1_NUM] +Integer = 1 + +[XCHAL_HAVE_ADDX] +Integer = 1 + +[XCHAL_HAVE_FUSION_SOFTDEMAP] +Integer = 0 + +[XCHAL_HAVE_BSP3] +Integer = 0 + +[XCHAL_HAVE_PIF_WR_RESP] +Integer = 0 + +[XCHAL_NUM_PERF_COUNTERS] +Integer = 2 + +[XCHAL_HAVE_FP_RSQRT] +Integer = 1 + +[XCHAL_MMU_RING_BITS] +Integer = 0 + +[XCHAL_HW_MIN_VERSION] +Integer = 260003 + +[XCHAL_HAVE_HIFIPRO] +Integer = 0 + +[XCHAL_INT0_LEVEL] +Integer = 1 + +[XCHAL_HAVE_IDENTITY_MAP] +Integer = 1 + +[XCHAL_INT8_EXTNUM] +Integer = 6 + +[XCHAL_INT10_EXTNUM] +Integer = 8 + +[XCHAL_INT15_TYPE] +Interrupt = "Timer" + +[XCHAL_EXTINT5_NUM] +Integer = 5 + +[XCHAL_HAVE_EXCEPTIONS] +Integer = 1 + +[XCHAL_NUM_DATARAM] +Integer = 2 + +[XCHAL_HAVE_PSO] +Integer = 0 + +[XCHAL_HW_MIN_VERSION_MAJOR] +Integer = 2600 + +[XCHAL_DATARAM1_ECC_PARITY] +Integer = 0 + +[XCHAL_HAVE_FP_DIV] +Integer = 1 + +[XCHAL_INT16_TYPE] +Interrupt = "Timer" + +[XCHAL_EXTINT4_NUM] +Integer = 4 + +[XCHAL_WINDOW_OF4_VECOFS] +Integer = 0 + +[XCHAL_INTLEVEL4_VECTOR_VADDR] +Integer = 1073742336 + +[XCHAL_HAVE_USER_DPFPU] +Integer = 0 + +[XCHAL_UNALIGNED_LOAD_EXCEPTION] +Integer = 0 + +[XCHAL_INST_FETCH_WIDTH] +Integer = 4 + +[XCHAL_HAVE_VECTORFPU2005] +Integer = 0 + +[XCHAL_INT20_EXTNUM] +Integer = 15 + +[XCHAL_KERNEL_VECTOR_VADDR] +Integer = 1073742592 + +[XCHAL_INT21_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_WINDOW_OF8_VECOFS] +Integer = 128 + +[XCHAL_DATAROM0_SIZE] +Integer = 4194304 + +[XCHAL_HAVE_ABSOLUTE_LITERALS] +Integer = 0 + +[XCHAL_ICACHE_SIZE] +Integer = 0 + +[XCHAL_DCACHE_SIZE] +Integer = 0 + +[XCHAL_DATARAM0_PADDR] +Integer = 1073217536 + +[XCHAL_INT0_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_CLOCK_GATING_FUNCUNIT] +Integer = 1 + +[XCHAL_KERNEL_VECTOR_PADDR] +Integer = 1073742592 + +[XCHAL_NUM_INTLEVELS] +Integer = 6 + +[XCHAL_HAVE_ICACHE_TEST] +Integer = 0 + +[XCHAL_INTLEVEL5_VECTOR_PADDR] +Integer = 1073742400 + +[XCHAL_DEBUG_VECOFS] +Integer = 640 + +[XCHAL_NMI_VECOFS] +Integer = 704 + +[XCHAL_HAVE_OCD_DIR_ARRAY] +Integer = 0 + +[XCHAL_HAVE_TLBS] +Integer = 1 + +[XCHAL_NMILEVEL] +Integer = 7 + +[XCHAL_HAVE_S32C1I] +Integer = 1 + +[XCHAL_INSTRAM1_ECC_PARITY] +Integer = 0 + +[XCHAL_TRAX_MEM_SHAREABLE] +Integer = 1 + +[XCHAL_HAVE_PIF_REQ_ATTR] +Integer = 0 + +[XCHAL_DATA_WIDTH] +Integer = 4 + +[XCHAL_INT24_EXTNUM] +Integer = 19 + +[XCHAL_INTLEVEL7_VECOFS] +Integer = 704 + +[XCHAL_EXTINT3_NUM] +Integer = 3 + +[XCHAL_EXTINT0_NUM] +Integer = 0 + +[XCHAL_TRAX_ATB_WIDTH] +Integer = 32 + +[XCHAL_DATARAM1_BANKS] +Integer = 1 + +[XCHAL_HAVE_MIMIC_CACHEATTR] +Integer = 1 + +[XCHAL_INT11_LEVEL] +Integer = 3 + +[XCHAL_INT22_EXTNUM] +Integer = 17 + +[XCHAL_HAVE_MUL32] +Integer = 1 + +[XCHAL_HAVE_MX] +Integer = 0 + +[XCHAL_NUM_URAM] +Integer = 0 + +[XCHAL_HAVE_DEPBITS] +Integer = 0 + +[XCHAL_HW_MAX_VERSION_MINOR] +Integer = 3 + +[XCHAL_DEBUGLEVEL] +Integer = 6 + +[XCHAL_EXTINT2_NUM] +Integer = 2 + +[XCHAL_EXTINT12_NUM] +Integer = 17 + +[XCHAL_EXTINT15_NUM] +Integer = 20 + +[XCHAL_HAVE_HIFI4_VFPU] +Integer = 0 + +[XCHAL_HAVE_MAC16] +Integer = 1 + +[XCHAL_HAVE_AXI] +Integer = 0 + +[XCHAL_NUM_AREGS] +Integer = 64 + +[XCHAL_HAVE_CONNXD2_DUALLSFLIX] +Integer = 0 + +[XCHAL_INT16_LEVEL] +Integer = 5 + +[XCHAL_EXTINT17_NUM] +Integer = 22 + +[XCHAL_INT26_EXTNUM] +Integer = 21 + +[XCHAL_HAVE_MEM_ECC_PARITY] +Integer = 0 + +[XCHAL_INT21_LEVEL] +Integer = 2 + +[XCHAL_RESET_VECTOR1_VADDR] +Integer = 1073742848 + +[XCHAL_HAVE_CACHE_BLOCKOPS] +Integer = 0 + +[XCHAL_WINDOW_VECTORS_VADDR] +Integer = 1073741824 + +[XCHAL_INTLEVEL2_VECTOR_VADDR] +Integer = 1073742208 + +[XCHAL_NMI_VECTOR_PADDR] +Integer = 1073742528 + +[XCHAL_HAVE_VECTRA1] +Integer = 0 + +[XCHAL_DCACHE_SETWIDTH] +Integer = 0 + +[XCHAL_HAVE_PREFETCH] +Integer = 0 + +[XCHAL_INT4_LEVEL] +Integer = 1 + +[XCHAL_INT12_LEVEL] +Integer = 1 + +[XCHAL_LOOP_BUFFER_SIZE] +Integer = 256 + +[XCHAL_WINDOW_UF12_VECOFS] +Integer = 320 + +[XCHAL_NUM_INTERRUPTS_LOG2] +Integer = 5 + +[XCHAL_INT7_TYPE] +Interrupt = "Software" + +[XCHAL_HAVE_USER_SPFPU] +Integer = 0 + +[XCHAL_INTLEVEL6_VECTOR_PADDR] +Integer = 1073742464 + +[XCHAL_INT4_EXTNUM] +Integer = 4 + +[XCHAL_HAVE_PSO_FULL_RETENTION] +Integer = 0 + +[XCHAL_HAVE_XEA2] +Integer = 1 + +[XCHAL_HAVE_PTP_MMU] +Integer = 0 + +[XCHAL_HAVE_FUSION_CONVENC] +Integer = 0 + +[XCHAL_HW_REL_LX6_0_3] +Integer = 1 + +[XCHAL_HAVE_ICACHE_DYN_WAYS] +Integer = 0 + +[XCHAL_INTLEVEL6_MASK] +Integer = 0 + +[XCHAL_HAVE_FUSION_16BIT_BASEBAND] +Integer = 0 + +[XCHAL_HAVE_BBE16_DESPREAD] +Integer = 0 + +[XCHAL_XLMI0_VADDR] +Integer = 1072693248 + +[XCHAL_INT15_LEVEL] +Integer = 3 + +[XCHAL_INT12_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INTLEVEL7_NUM] +Integer = 14 + +[XCHAL_INT5_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT26_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INTTYPE_MASK_WRITE_ERROR] +Integer = 0 + +[XCHAL_HAVE_DEBUG_JTAG] +Integer = 1 + +[XCHAL_HAVE_WINDOWED] +Integer = 1 + +[XCHAL_HAVE_MP_RUNSTALL] +Integer = 0 + +[XCHAL_NUM_INSTROM] +Integer = 1 + +[XCHAL_DATAROM0_BANKS] +Integer = 1 + +[XCHAL_HAVE_NMI] +Integer = 1 + +[XCHAL_HAVE_HALT] +Integer = 0 + +[XCHAL_NUM_IBREAK] +Integer = 2 + +[XCHAL_TRAX_MEM_SIZE] +Integer = 16384 + +[XCHAL_HW_CONFIGID0] +Integer = 3267166206 + +[XCHAL_INT17_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_PROFILING_INTERRUPT] +Integer = 11 + +[XCHAL_EXTINT22_NUM] +Integer = 27 + +[XCHAL_HW_CONFIGID1] +Integer = 482737814 + +[XCHAL_NUM_INTERRUPTS] +Integer = 32 + +[XCHAL_INT23_LEVEL] +Integer = 3 + +[XCHAL_DCACHE_LINE_LOCKABLE] +Integer = 0 + +[XCHAL_INT21_EXTNUM] +Integer = 16 + +[XCHAL_EXTINT9_NUM] +Integer = 12 + +[XCHAL_NMI_VECTOR_VADDR] +Integer = 1073742528 + +[XCHAL_UNALIGNED_STORE_EXCEPTION] +Integer = 0 + +[XCHAL_HW_VERSION_MAJOR] +Integer = 2600 + +[XCHAL_HAVE_FUSION_AES] +Integer = 0 + +[XCHAL_HAVE_TRAX] +Integer = 1 + +[XCHAL_HAVE_DFP_SQRT] +Integer = 0 + +[XCHAL_HAVE_DENSITY] +Integer = 1 + +[XCHAL_HAVE_MP_INTERRUPTS] +Integer = 0 + +[XCHAL_DATAROM0_ECC_PARITY] +Integer = 0 + +[XCHAL_INT27_LEVEL] +Integer = 3 + +[XCHAL_INT19_EXTNUM] +Integer = 14 + +[XCHAL_VECBASE_RESET_PADDR] +Integer = 1073741824 + +[XCHAL_INT1_EXTNUM] +Integer = 1 + +[XCHAL_HAVE_DEBUG_APB] +Integer = 1 + +[XCHAL_INTLEVEL5_ANDBELOW_MASK] +Integer = 4294950911 + +[XCHAL_INT31_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT28_EXTNUM] +Integer = 23 + +[XCHAL_NUM_DBREAK] +Integer = 2 + +[XCHAL_CORE_ID] +String = "esp32_v3_49_prod" + +[XCHAL_HAVE_EXTERN_REGS] +Integer = 1 + +[XCHAL_HAVE_RELEASE_SYNC] +Integer = 1 + +[XCHAL_NUM_EXTINTERRUPTS] +Integer = 26 + +[XCHAL_INT1_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_MUL16] +Integer = 1 + +[XCHAL_XLMI0_PADDR] +Integer = 1072693248 + +[XCHAL_INT19_LEVEL] +Integer = 2 + +[XCHAL_NUM_AREGS_LOG2] +Integer = 6 + +[XCHAL_INTLEVEL6_ANDBELOW_MASK] +Integer = 4294950911 + +[XCHAL_INTLEVEL5_MASK] +Integer = 2214658048 + +[XCHAL_EXTINT21_NUM] +Integer = 26 + +[XCHAL_HAVE_BBE16] +Integer = 0 + +[XCHAL_HAVE_HIFI4] +Integer = 0 + +[XCHAL_RESET_VECBASE_OVERLAP] +Integer = 0 + +[XCHAL_HAVE_BBENEP] +Integer = 0 + +[XCHAL_DOUBLEEXC_VECOFS] +Integer = 960 + +[XCHAL_MAX_INSTRUCTION_SIZE] +Integer = 3 + +[XCHAL_DATARAM1_SIZE] +Integer = 4194304 + +[XCHAL_NUM_TIMERS] +Integer = 3 + +[XCHAL_INTLEVEL2_VECOFS] +Integer = 384 + +[XCHAL_ICACHE_WAYS] +Integer = 1 + +[XCHAL_INTLEVEL7_VECTOR_VADDR] +Integer = 1073742528 + +[XCHAL_INT30_LEVEL] +Integer = 4 + +[XCHAL_HAVE_DEBUG_ERI] +Integer = 1 + +[XCHAL_HAVE_DFP_RSQRT] +Integer = 0 + +[XCHAL_INSTRAM0_PADDR] +Integer = 1073741824 + +[XCHAL_INT24_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_XEA1] +Integer = 0 + +[XCHAL_HAVE_CONNXD2] +Integer = 0 + +[XCHAL_INT9_LEVEL] +Integer = 1 + +[XCHAL_INT31_LEVEL] +Integer = 5 + +[XCHAL_HAVE_FP] +Integer = 1 + +[XCHAL_INTTYPE_MASK_UNCONFIGURED] +Integer = 0 + +[XCHAL_RESET_VECTOR0_PADDR] +Integer = 1342177280 + +[XCHAL_HW_VERSION_NAME] +String = "LX6.0.3" + +[XCHAL_INTLEVEL6_VECTOR_VADDR] +Integer = 1073742464 + +[XCHAL_HAVE_SPANNING_WAY] +Integer = 1 + +[XCHAL_MMU_RINGS] +Integer = 1 + +[XCHAL_HAVE_DIV32] +Integer = 1 + +[XCHAL_KERNEL_VECOFS] +Integer = 768 + +[XCHAL_HAVE_SSP16_VITERBI] +Integer = 0 + +[XCHAL_HAVE_BBP16] +Integer = 0 + +[XCHAL_HW_REL_LX6_0] +Integer = 1 + +[XCHAL_HW_CONFIGID_RELIABLE] +Integer = 1 + +[XCHAL_HAVE_L32R] +Integer = 1 + +[XCHAL_DATAROM0_VADDR] +Integer = 1061158912 + +[XCHAL_HAVE_INTERRUPTS] +Integer = 1 + +[XCHAL_INT1_LEVEL] +Integer = 1 + +[XCHAL_INT6_LEVEL] +Integer = 1 + +[XCHAL_INT10_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_INTTYPE_MASK_PROFILING] +Integer = 2048 + +[XCHAL_EXCM_LEVEL] +Integer = 3 + +[XCHAL_HAVE_DFPU_SINGLE_DOUBLE] +Integer = 0 + +[XCHAL_DCACHE_WAYS] +Integer = 1 + +[XCHAL_INSTROM0_PADDR] +Integer = 1082130432 + +[XCHAL_INT10_LEVEL] +Integer = 1 + +[XCHAL_INTLEVEL3_VECOFS] +Integer = 448 + +[XCHAL_ICACHE_LINE_LOCKABLE] +Integer = 0 + +[XCHAL_HAVE_FLIX3] +Integer = 0 + +[XCHAL_HAVE_CCOUNT] +Integer = 1 + +[XCHAL_SPANNING_WAY] +Integer = 0 + +[XCHAL_HAVE_FUSION_LOW_POWER] +Integer = 0 + +[XCHAL_INT7_LEVEL] +Integer = 1 + +[XCHAL_EXTINT14_NUM] +Integer = 19 + +[XCHAL_HAVE_FUSION_AVS] +Integer = 0 + +[XCHAL_INT17_EXTNUM] +Integer = 12 + +[XCHAL_INT19_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_NUM_CONTEXTS] +Integer = 1 + +[XCHAL_HAVE_HIFI2EP] +Integer = 0 + +[XCHAL_HAVE_PDX4] +Integer = 0 + +[XCHAL_INT23_EXTNUM] +Integer = 18 + +[XCHAL_DCACHE_IS_WRITEBACK] +Integer = 0 + +[XCHAL_INTLEVEL7_MASK] +Integer = 16384 + +[XCHAL_USER_VECTOR_PADDR] +Integer = 1073742656 + +[XCHAL_INTLEVEL4_ANDBELOW_MASK] +Integer = 2080292863 + +[XCHAL_DATAROM0_PADDR] +Integer = 1061158912 + +[XCHAL_UNALIGNED_LOAD_HW] +Integer = 1 + +[XCHAL_HAVE_WIDE_BRANCHES] +Integer = 0 + +[XCHAL_EXTINT6_NUM] +Integer = 8 + +[XCHAL_HAVE_MINMAX] +Integer = 1 + +[XCHAL_HAVE_OCD_LS32DDR] +Integer = 1 + +[XCHAL_XLMI0_SIZE] +Integer = 524288 + +[XCHAL_WINDOW_UF8_VECOFS] +Integer = 192 + +[XCHAL_MMU_ASID_BITS] +Integer = 0 + +[XCHAL_HAVE_BBE16_VECDIV] +Integer = 0 + +[XCHAL_HAVE_DFP_DIV] +Integer = 0 + +[XCHAL_HAVE_FUSION_VITERBI] +Integer = 0 + +[XCHAL_HAVE_PRID] +Integer = 1 + +[XCHAL_HAVE_HIFI3_VFPU] +Integer = 0 + +[XCHAL_HAVE_BOOLEANS] +Integer = 1 + +[XCHAL_INSTROM0_ECC_PARITY] +Integer = 0 + +[XCHAL_HAVE_FP_RECIP] +Integer = 1 + +[XCHAL_INT2_LEVEL] +Integer = 1 + +[XCHAL_INT13_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_PREFETCH_L1] +Integer = 0 + +[XCHAL_TIMER2_INTERRUPT] +Integer = 16 + +[XCHAL_HAVE_PSO_CDM] +Integer = 0 + +[XCHAL_DCACHE_BANKS] +Integer = 0 + +[XCHAL_HAVE_SEXT] +Integer = 1 + +[XCHAL_INSTRAM0_SIZE] +Integer = 4194304 + +[XCHAL_HAVE_CLAMPS] +Integer = 1 + +[XCHAL_DCACHE_LINESIZE] +Integer = 4 + +[XCHAL_INT2_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_VECBASE] +Integer = 1 + +[XCHAL_HAVE_NSA] +Integer = 1 + +[XCHAL_INSTROM0_VADDR] +Integer = 1082130432 + +[XCHAL_WINDOW_OF12_VECOFS] +Integer = 256 + +[XCHAL_DEBUG_VECTOR_VADDR] +Integer = 1073742464 + +[XCHAL_HAVE_HIFI2] +Integer = 0 + +[XCHAL_HAVE_CONST16] +Integer = 0 + +[XCHAL_INT18_LEVEL] +Integer = 1 + +[XCHAL_DCACHE_LINEWIDTH] +Integer = 2 + +[XCHAL_INT25_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_LOOPS] +Integer = 1 + +[XCHAL_HW_MAX_VERSION] +Integer = 260003 + +[XCHAL_HAVE_CACHEATTR] +Integer = 0 diff --git a/xtensa-lx-rt/config/xtensa_esp32s2.toml b/xtensa-lx-rt/config/xtensa_esp32s2.toml new file mode 100644 index 0000000..76be1e2 --- /dev/null +++ b/xtensa-lx-rt/config/xtensa_esp32s2.toml @@ -0,0 +1,1475 @@ +[XCHAL_DATARAM1_SIZE] +Integer = 4194304 + +[XCHAL_INT5_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INTLEVEL6_VECTOR_PADDR] +Integer = 1073742464 + +[XCHAL_INTTYPE_MASK_WRITE_ERROR] +Integer = 0 + +[XCHAL_HAVE_PREFETCH] +Integer = 0 + +[XCHAL_INTLEVEL3_MASK] +Integer = 683706368 + +[XCHAL_EXTINT21_NUM] +Integer = 26 + +[XCHAL_RESET_VECTOR0_PADDR] +Integer = 1342177280 + +[XCHAL_INSTRAM1_VADDR] +Integer = 1077936128 + +[XCHAL_EXTINT4_NUM] +Integer = 4 + +[XCHAL_EXTINT19_NUM] +Integer = 24 + +[XCHAL_XLMI0_PADDR] +Integer = 1061158912 + +[XCHAL_INT7_TYPE] +Interrupt = "Software" + +[XCHAL_HAVE_FP] +Integer = 0 + +[XCHAL_EXTINT6_NUM] +Integer = 8 + +[XCHAL_EXTINT18_NUM] +Integer = 23 + +[XCHAL_DATAROM0_BANKS] +Integer = 1 + +[XCHAL_INT11_LEVEL] +Integer = 3 + +[XCHAL_RESET_VECTOR_PADDR] +Integer = 1073742848 + +[XCHAL_HAVE_PDX16] +Integer = 0 + +[XCHAL_INTLEVEL7_ANDBELOW_MASK] +Integer = 4294967295 + +[XCHAL_EXTINT2_NUM] +Integer = 2 + +[XCHAL_MPU_BG_CACHEADRDIS] +Integer = 0 + +[XCHAL_MPU_BACKGROUND_ENTRIES] +Integer = 0 + +[XCHAL_INT22_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_RESET_VECTOR1_VADDR] +Integer = 1073742848 + +[XCHAL_INTLEVEL2_VECTOR_PADDR] +Integer = 1073742208 + +[XCHAL_HAVE_RELEASE_SYNC] +Integer = 1 + +[XCHAL_VISION_SIMD16] +Integer = 0 + +[XCHAL_HAVE_PREDICTED_BRANCHES] +Integer = 0 + +[XCHAL_MMU_RINGS] +Integer = 1 + +[XCHAL_HAVE_PTP_MMU] +Integer = 0 + +[XCHAL_EXTINT14_NUM] +Integer = 19 + +[XCHAL_INTLEVEL7_MASK] +Integer = 16384 + +[XCHAL_INT8_EXTNUM] +Integer = 6 + +[XCHAL_DATAROM0_VADDR] +Integer = 1056964608 + +[XCHAL_NUM_INTERRUPTS] +Integer = 32 + +[XCHAL_HAVE_MIMIC_CACHEATTR] +Integer = 1 + +[XCHAL_INTLEVEL3_VECOFS] +Integer = 448 + +[XCHAL_RESET_VECTOR_VADDR] +Integer = 1073742848 + +[XCHAL_HAVE_MUL32_HIGH] +Integer = 1 + +[XCHAL_MPU_ALIGN] +Integer = 0 + +[XCHAL_HAVE_CACHE_BLOCKOPS] +Integer = 0 + +[XCHAL_HAVE_PIF_WR_RESP] +Integer = 0 + +[XCHAL_DCACHE_ACCESS_SIZE] +Integer = 1 + +[XCHAL_DOUBLEEXC_VECOFS] +Integer = 960 + +[XCHAL_INT30_EXTNUM] +Integer = 24 + +[XCHAL_SW_VERSION] +Integer = 1200009 + +[XCHAL_INT4_LEVEL] +Integer = 1 + +[XCHAL_INT20_LEVEL] +Integer = 2 + +[XCHAL_MPU_ALIGN_BITS] +Integer = 0 + +[XCHAL_INTLEVEL5_VECOFS] +Integer = 576 + +[XCHAL_HAVE_BBENEP_SP_VFPU] +Integer = 0 + +[XCHAL_INT14_EXTNUM] +Integer = 11 + +[XCHAL_INT30_LEVEL] +Integer = 4 + +[XCHAL_INT1_LEVEL] +Integer = 1 + +[XCHAL_DOUBLEEXC_VECTOR_PADDR] +Integer = 1073742784 + +[XCHAL_HAVE_HIFI2EP] +Integer = 0 + +[XCHAL_INT27_EXTNUM] +Integer = 22 + +[XCHAL_HAVE_USER_DPFPU] +Integer = 0 + +[XCHAL_HAVE_SSP16] +Integer = 0 + +[XCHAL_HAVE_HIFI4_VFPU] +Integer = 0 + +[XCHAL_HAVE_MUL32] +Integer = 1 + +[XCHAL_EXTINT20_NUM] +Integer = 25 + +[XCHAL_INT9_EXTNUM] +Integer = 7 + +[XCHAL_INTLEVEL7_VECOFS] +Integer = 704 + +[XCHAL_HAVE_CONST16] +Integer = 0 + +[XCHAL_ICACHE_LINESIZE] +Integer = 4 + +[XCHAL_HAVE_TURBO16] +Integer = 0 + +[XCHAL_HAVE_MAC16] +Integer = 0 + +[XCHAL_HAVE_DCACHE_TEST] +Integer = 0 + +[XCHAL_EXTINT0_NUM] +Integer = 0 + +[XCHAL_WINDOW_OF12_VECOFS] +Integer = 256 + +[XCHAL_DCACHE_BANKS] +Integer = 0 + +[XCHAL_INT11_TYPE] +Interrupt = "Profiling" + +[XCHAL_UNALIGNED_LOAD_EXCEPTION] +Integer = 0 + +[XCHAL_INT19_EXTNUM] +Integer = 14 + +[XCHAL_CLOCK_GATING_GLOBAL] +Integer = 0 + +[XCHAL_XLMI0_ECC_PARITY] +Integer = 0 + +[XCHAL_EXTINT13_NUM] +Integer = 18 + +[XCHAL_RESET_VECTOR1_PADDR] +Integer = 1073742848 + +[XCHAL_INSTROM0_VADDR] +Integer = 1082130432 + +[XCHAL_NUM_PERF_COUNTERS] +Integer = 2 + +[XCHAL_HAVE_BBE16] +Integer = 0 + +[XCHAL_ICACHE_LINEWIDTH] +Integer = 2 + +[XCHAL_HAVE_DIV32] +Integer = 1 + +[XCHAL_NUM_AREGS] +Integer = 64 + +[XCHAL_INT3_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT12_LEVEL] +Integer = 1 + +[XCHAL_INT18_EXTNUM] +Integer = 13 + +[XCHAL_HAVE_CACHEATTR] +Integer = 0 + +[XCHAL_MPU_ALIGN_REQ] +Integer = 1 + +[XCHAL_HAVE_PREFETCH_L1] +Integer = 0 + +[XCHAL_HAVE_HIFI4] +Integer = 0 + +[XCHAL_HAVE_HIFI2] +Integer = 0 + +[XCHAL_NUM_EXTINTERRUPTS] +Integer = 26 + +[XCHAL_USER_VECTOR_PADDR] +Integer = 1073742656 + +[XCHAL_HAVE_DFP_DIV] +Integer = 0 + +[XCHAL_INTLEVEL2_MASK] +Integer = 3670016 + +[XCHAL_HAVE_TAP_MASTER] +Integer = 0 + +[XCHAL_ICACHE_SETWIDTH] +Integer = 0 + +[XCHAL_HAVE_FUSION_VITERBI] +Integer = 0 + +[XCHAL_HW_VERSION_MAJOR] +Integer = 2700 + +[XCHAL_INT9_LEVEL] +Integer = 1 + +[XCHAL_NMI_VECOFS] +Integer = 704 + +[XCHAL_TRAX_MEM_SIZE] +Integer = 16384 + +[XCHAL_INSTRAM0_HAVE_IDMA] +Integer = 0 + +[XCHAL_EXTINT22_NUM] +Integer = 27 + +[XCHAL_HAVE_PDX4] +Integer = 0 + +[XCHAL_HAVE_FP_RECIP] +Integer = 0 + +[XCHAL_DCACHE_SIZE] +Integer = 0 + +[XCHAL_INT30_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_INT15_TYPE] +Interrupt = "Timer" + +[XCHAL_XEA_VERSION] +Integer = 2 + +[XCHAL_HAVE_HALT] +Integer = 0 + +[XCHAL_TRAX_MEM_SHAREABLE] +Integer = 1 + +[XCHAL_MPU_ENTRIES] +Integer = 0 + +[XCHAL_DATARAM0_BANKS] +Integer = 1 + +[XCHAL_HW_REL_LX7_0_9] +Integer = 1 + +[XCHAL_HAVE_HIFI3] +Integer = 0 + +[XCHAL_VISION_QUAD_MAC_TYPE] +Integer = 0 + +[XCHAL_INT6_TYPE] +Interrupt = "Timer" + +[XCHAL_HAVE_HIFI3Z_VFPU] +Integer = 0 + +[XCHAL_HAVE_XLT_CACHEATTR] +Integer = 0 + +[XCHAL_HAVE_IDMA_TRANSPOSE] +Integer = 0 + +[XCHAL_WINDOW_OF8_VECOFS] +Integer = 128 + +[XCHAL_CP_MAXCFG] +Integer = 8 + +[XCHAL_HAVE_ACELITE] +Integer = 0 + +[XCHAL_DATAROM0_SIZE] +Integer = 4194304 + +[XCHAL_INTLEVEL5_MASK] +Integer = 2214658048 + +[XCHAL_HAVE_CCOUNT] +Integer = 1 + +[XCHAL_DCACHE_IS_WRITEBACK] +Integer = 0 + +[XCHAL_HW_VERSION] +Integer = 270009 + +[XCHAL_INTLEVEL5_VECTOR_PADDR] +Integer = 1073742400 + +[XCHAL_INT27_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT13_LEVEL] +Integer = 1 + +[XCHAL_HAVE_ICACHE_TEST] +Integer = 0 + +[XCHAL_INTLEVEL4_VECOFS] +Integer = 512 + +[XCHAL_HAVE_FUSION] +Integer = 0 + +[XCHAL_INT1_EXTNUM] +Integer = 1 + +[XCHAL_INTLEVEL2_VECTOR_VADDR] +Integer = 1073742208 + +[XCHAL_DCACHE_LINESIZE] +Integer = 4 + +[XCHAL_HAVE_PSO_FULL_RETENTION] +Integer = 0 + +[XCHAL_HAVE_CONNXD2_DUALLSFLIX] +Integer = 0 + +[XCHAL_INSTRAM0_VADDR] +Integer = 1073741824 + +[XCHAL_NUM_INSTROM] +Integer = 1 + +[XCHAL_EXCM_LEVEL] +Integer = 3 + +[XCHAL_INTTYPE_MASK_EXTERN_LEVEL] +Integer = 2411606847 + +[XCHAL_RESET_VECBASE_OVERLAP] +Integer = 0 + +[XCHAL_DATA_WIDTH] +Integer = 4 + +[XCHAL_EXTINT23_NUM] +Integer = 28 + +[XCHAL_TRAX_ATB_WIDTH] +Integer = 0 + +[XCHAL_HW_REL_LX7] +Integer = 1 + +[XCHAL_DATARAM0_ECC_PARITY] +Integer = 0 + +[XCHAL_EXTINT5_NUM] +Integer = 5 + +[XCHAL_INT31_LEVEL] +Integer = 5 + +[XCHAL_HAVE_VISION_HISTOGRAM] +Integer = 0 + +[XCHAL_INT14_TYPE] +Interrupt = "Nmi" + +[XCHAL_HAVE_MP_RUNSTALL] +Integer = 0 + +[XCHAL_DEBUG_VECTOR_PADDR] +Integer = 1073742464 + +[XCHAL_NMI_VECTOR_VADDR] +Integer = 1073742528 + +[XCHAL_HAVE_WINDOWED] +Integer = 1 + +[XCHAL_INT4_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_DFP_ACCEL] +Integer = 0 + +[XCHAL_HW_VERSION_MINOR] +Integer = 9 + +[XCHAL_HW_MAX_VERSION] +Integer = 270009 + +[XCHAL_HAVE_AXI_ECC] +Integer = 0 + +[XCHAL_UNALIGNED_LOAD_HW] +Integer = 1 + +[XCHAL_MMU_RING_BITS] +Integer = 0 + +[XCHAL_INT5_EXTNUM] +Integer = 5 + +[XCHAL_HW_MIN_VERSION] +Integer = 270009 + +[XCHAL_TRAX_TIME_WIDTH] +Integer = 0 + +[XCHAL_HAVE_DFPU_SINGLE_ONLY] +Integer = 0 + +[XCHAL_SPANNING_WAY] +Integer = 0 + +[XCHAL_RESET_VECTOR0_VADDR] +Integer = 1342177280 + +[XCHAL_INTTYPE_MASK_SOFTWARE] +Integer = 536871040 + +[XCHAL_INT17_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INTTYPE_MASK_IDMA_ERR] +Integer = 0 + +[XCHAL_EXTINT17_NUM] +Integer = 22 + +[XCHAL_USER_VECTOR_VADDR] +Integer = 1073742656 + +[XCHAL_HAVE_DEBUG_ERI] +Integer = 1 + +[XCHAL_HAVE_DENSITY] +Integer = 1 + +[XCHAL_DEBUG_VECTOR_VADDR] +Integer = 1073742464 + +[XCHAL_INT25_LEVEL] +Integer = 4 + +[XCHAL_WINDOW_UF4_VECOFS] +Integer = 64 + +[XCHAL_NUM_DATARAM] +Integer = 2 + +[XCHAL_HAVE_DFP_RSQRT] +Integer = 0 + +[XCHAL_HAVE_AXI] +Integer = 0 + +[XCHAL_INT2_LEVEL] +Integer = 1 + +[XCHAL_INT19_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_DATARAM0_VADDR] +Integer = 1069547520 + +[XCHAL_HAVE_BOOTLOADER] +Integer = 0 + +[XCHAL_HAVE_OCD_LS32DDR] +Integer = 1 + +[XCHAL_HAVE_FLIX3] +Integer = 0 + +[XCHAL_NUM_DATAROM] +Integer = 1 + +[XCHAL_INSTRAM1_PADDR] +Integer = 1077936128 + +[XCHAL_PROFILING_INTERRUPT] +Integer = 11 + +[XCHAL_INT28_EXTNUM] +Integer = 23 + +[XCHAL_NUM_TIMERS] +Integer = 3 + +[XCHAL_EXTINT9_NUM] +Integer = 12 + +[XCHAL_INTLEVEL7_VECTOR_VADDR] +Integer = 1073742528 + +[XCHAL_INT22_EXTNUM] +Integer = 17 + +[XCHAL_INT23_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT25_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INTTYPE_MASK_PROFILING] +Integer = 2048 + +[XCHAL_HAVE_THREADPTR] +Integer = 1 + +[XCHAL_VISION_TYPE] +Integer = 0 + +[XCHAL_EXTINT15_NUM] +Integer = 20 + +[XCHAL_HAVE_BE] +Integer = 0 + +[XCHAL_HAVE_SPECULATION] +Integer = 0 + +[XCHAL_DATARAM1_PADDR] +Integer = 1065353216 + +[XCHAL_INTTYPE_MASK_TIMER] +Integer = 98368 + +[XCHAL_INT29_LEVEL] +Integer = 3 + +[XCHAL_DCACHE_IS_COHERENT] +Integer = 0 + +[XCHAL_HAVE_BBE16_DESPREAD] +Integer = 0 + +[XCHAL_INSTRAM0_PADDR] +Integer = 1073741824 + +[XCHAL_TIMER2_INTERRUPT] +Integer = 16 + +[XCHAL_HAVE_FUSION_16BIT_BASEBAND] +Integer = 0 + +[XCHAL_ICACHE_ACCESS_SIZE] +Integer = 1 + +[XCHAL_INT21_LEVEL] +Integer = 2 + +[XCHAL_INTLEVEL3_VECTOR_VADDR] +Integer = 1073742272 + +[XCHAL_HAVE_HIFIPRO] +Integer = 0 + +[XCHAL_HAVE_SPANNING_WAY] +Integer = 1 + +[XCHAL_DATARAM1_HAVE_IDMA] +Integer = 0 + +[XCHAL_INT31_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_FUSION_LFSR_CRC] +Integer = 0 + +[XCHAL_HAVE_FUSIONG_DP_VFPU] +Integer = 0 + +[XCHAL_MAX_INSTRUCTION_SIZE] +Integer = 3 + +[XCHAL_INT0_LEVEL] +Integer = 1 + +[XCHAL_HW_CONFIGID_RELIABLE] +Integer = 1 + +[XCHAL_HAVE_DFP_accel] +Integer = 0 + +[XCHAL_HAVE_MINMAX] +Integer = 1 + +[XCHAL_HAVE_VECBASE] +Integer = 1 + +[XCHAL_WINDOW_VECTORS_VADDR] +Integer = 1073741824 + +[XCHAL_INTLEVEL5_ANDBELOW_MASK] +Integer = 4294950911 + +[XCHAL_INT15_LEVEL] +Integer = 3 + +[XCHAL_INT18_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_WIDE_BRANCHES] +Integer = 0 + +[XCHAL_EXTINT3_NUM] +Integer = 3 + +[XCHAL_ICACHE_LINE_LOCKABLE] +Integer = 0 + +[XCHAL_DATARAM0_HAVE_IDMA] +Integer = 0 + +[XCHAL_INSTROM0_PADDR] +Integer = 1082130432 + +[XCHAL_DATARAM1_VADDR] +Integer = 1065353216 + +[XCHAL_HAVE_BBENEP] +Integer = 0 + +[XCHAL_INTLEVEL1_ANDBELOW_MASK] +Integer = 407551 + +[XCHAL_EXTINT11_NUM] +Integer = 14 + +[XCHAL_DOUBLEEXC_VECTOR_VADDR] +Integer = 1073742784 + +[XCHAL_HAVE_PDX] +Integer = 0 + +[XCHAL_HAVE_EXTERN_REGS] +Integer = 1 + +[XCHAL_HAVE_DATARAM0] +Integer = 1 + +[XCHAL_ICACHE_WAYS] +Integer = 1 + +[XCHAL_INT26_LEVEL] +Integer = 5 + +[XCHAL_INT20_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INSTRAM1_SIZE] +Integer = 4194304 + +[XCHAL_HAVE_XEA1] +Integer = 0 + +[XCHAL_EXTINT16_NUM] +Integer = 21 + +[XCHAL_HAVE_ABS] +Integer = 1 + +[XCHAL_INT28_LEVEL] +Integer = 4 + +[XCHAL_WINDOW_OF4_VECOFS] +Integer = 0 + +[XCHAL_HAVE_HIGHPRI_INTERRUPTS] +Integer = 1 + +[XCHAL_HAVE_BSP3] +Integer = 0 + +[XCHAL_INT22_LEVEL] +Integer = 3 + +[XCHAL_HAVE_FUSIONG3] +Integer = 0 + +[XCHAL_HAVE_ICACHE_DYN_WAYS] +Integer = 0 + +[XCHAL_INTLEVEL1_MASK] +Integer = 407551 + +[XCHAL_NUM_XLMI] +Integer = 1 + +[XCHAL_HAVE_FP_SQRT] +Integer = 0 + +[XCHAL_INTLEVEL2_VECOFS] +Integer = 384 + +[XCHAL_DATARAM1_ECC_PARITY] +Integer = 0 + +[XCHAL_INT6_LEVEL] +Integer = 1 + +[XCHAL_NMI_VECTOR_PADDR] +Integer = 1073742528 + +[XCHAL_HAVE_PDX8] +Integer = 0 + +[XCHAL_HAVE_FP_RSQRT] +Integer = 0 + +[XCHAL_HAVE_MUL16] +Integer = 1 + +[XCHAL_DATARAM0_SIZE] +Integer = 4194304 + +[XCHAL_HAVE_DEBUG_JTAG] +Integer = 1 + +[XCHAL_INTLEVEL3_VECTOR_PADDR] +Integer = 1073742272 + +[XCHAL_INTLEVEL3_ANDBELOW_MASK] +Integer = 687783935 + +[XCHAL_HAVE_MPU] +Integer = 0 + +[XCHAL_INT7_LEVEL] +Integer = 1 + +[XCHAL_HAVE_FUSIONG6] +Integer = 0 + +[XCHAL_HW_REL_LX7_0] +Integer = 1 + +[XCHAL_INT24_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_VISION_HP_VFPU] +Integer = 0 + +[XCHAL_INTLEVEL6_VECOFS] +Integer = 640 + +[XCHAL_DEBUGLEVEL] +Integer = 6 + +[XCHAL_INTTYPE_MASK_GS_ERR] +Integer = 0 + +[XCHAL_ICACHE_SIZE] +Integer = 0 + +[XCHAL_CLOCK_GATING_FUNCUNIT] +Integer = 0 + +[XCHAL_HAVE_HIFI5_VFPU] +Integer = 0 + +[XCHAL_INT16_LEVEL] +Integer = 5 + +[XCHAL_HAVE_DFPU_SINGLE_DOUBLE] +Integer = 0 + +[XCHAL_HAVE_S32C1I] +Integer = 0 + +[XCHAL_INT10_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_HAVE_MEM_ECC_PARITY] +Integer = 0 + +[XCHAL_NUM_DBREAK] +Integer = 2 + +[XCHAL_DATAROM0_ECC_PARITY] +Integer = 0 + +[XCHAL_INTLEVEL7_NUM] +Integer = 14 + +[XCHAL_INT3_LEVEL] +Integer = 1 + +[XCHAL_HAVE_HIFI3Z] +Integer = 0 + +[XCHAL_HAVE_GRIVPEP_HISTOGRAM] +Integer = 0 + +[XCHAL_HW_MIN_VERSION_MAJOR] +Integer = 2700 + +[XCHAL_INT17_LEVEL] +Integer = 1 + +[XCHAL_HAVE_DEBUG] +Integer = 1 + +[XCHAL_UNALIGNED_STORE_EXCEPTION] +Integer = 0 + +[XCHAL_HAVE_VISION_SP_VFPU] +Integer = 0 + +[XCHAL_HAVE_NMI] +Integer = 1 + +[XCHAL_INT2_EXTNUM] +Integer = 2 + +[XCHAL_HAVE_FUSION_FP] +Integer = 0 + +[XCHAL_HAVE_VECTORFPU2005] +Integer = 0 + +[XCHAL_NMI_INTERRUPT] +Integer = 14 + +[XCHAL_HAVE_IMEM_LOADSTORE] +Integer = 1 + +[XCHAL_INTLEVEL4_ANDBELOW_MASK] +Integer = 2080292863 + +[XCHAL_EXTINT10_NUM] +Integer = 13 + +[XCHAL_INT10_LEVEL] +Integer = 1 + +[XCHAL_HAVE_ADDX] +Integer = 1 + +[XCHAL_HAVE_HIFI5] +Integer = 0 + +[XCHAL_NUM_INTERRUPTS_LOG2] +Integer = 5 + +[XCHAL_EXTINT24_NUM] +Integer = 30 + +[XCHAL_HW_MAX_VERSION_MAJOR] +Integer = 2700 + +[XCHAL_EXTINT7_NUM] +Integer = 9 + +[XCHAL_INT3_EXTNUM] +Integer = 3 + +[XCHAL_INT27_LEVEL] +Integer = 3 + +[XCHAL_HAVE_VECTOR_SELECT] +Integer = 1 + +[XCHAL_INT20_EXTNUM] +Integer = 15 + +[XCHAL_HAVE_CLAMPS] +Integer = 1 + +[XCHAL_EXTINT8_NUM] +Integer = 10 + +[XCHAL_LOOP_BUFFER_SIZE] +Integer = 0 + +[XCHAL_HAVE_DFP] +Integer = 0 + +[XCHAL_DCACHE_ECC_PARITY] +Integer = 0 + +[XCHAL_NUM_URAM] +Integer = 0 + +[XCHAL_INT4_EXTNUM] +Integer = 4 + +[XCHAL_INTLEVEL6_ANDBELOW_MASK] +Integer = 4294950911 + +[XCHAL_HW_CONFIGID1] +Integer = 575113137 + +[XCHAL_HAVE_DEPBITS] +Integer = 0 + +[XCHAL_INTTYPE_MASK_IDMA_DONE] +Integer = 0 + +[XCHAL_FUSIONG_SIMD32] +Integer = 0 + +[XCHAL_HAVE_L32R] +Integer = 1 + +[XCHAL_INT24_LEVEL] +Integer = 4 + +[XCHAL_HW_VERSION_NAME] +String = "LX7.0.9" + +[XCHAL_INT12_EXTNUM] +Integer = 9 + +[XCHAL_HAVE_HIFI_MINI] +Integer = 0 + +[XCHAL_INT29_TYPE] +Interrupt = "Software" + +[XCHAL_INST_FETCH_WIDTH] +Integer = 4 + +[XCHAL_HAVE_BBE16_VECDIV] +Integer = 0 + +[XCHAL_XLMI0_SIZE] +Integer = 4194304 + +[XCHAL_INT1_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INSTROM0_ECC_PARITY] +Integer = 0 + +[XCHAL_ICACHE_ECC_PARITY] +Integer = 0 + +[XCHAL_INTTYPE_MASK_UNCONFIGURED] +Integer = 0 + +[XCHAL_NUM_MISC_REGS] +Integer = 4 + +[XCHAL_HAVE_VECTRALX] +Integer = 0 + +[XCHAL_KERNEL_VECTOR_VADDR] +Integer = 1073742592 + +[XCHAL_INT10_EXTNUM] +Integer = 8 + +[XCHAL_HAVE_BSP3_TRANSPOSE] +Integer = 0 + +[XCHAL_PREFETCH_CASTOUT_LINES] +Integer = 0 + +[XCHAL_HAVE_XEA2] +Integer = 1 + +[XCHAL_HAVE_OCD] +Integer = 1 + +[XCHAL_DATA_PIPE_DELAY] +Integer = 2 + +[XCHAL_HAVE_INSTRAM0] +Integer = 1 + +[XCHAL_BUILD_UNIQUE_ID] +Integer = 493489 + +[XCHAL_NMILEVEL] +Integer = 7 + +[XCHAL_HAVE_CONNXD2] +Integer = 0 + +[XCHAL_INT0_EXTNUM] +Integer = 0 + +[XCHAL_DCACHE_LINE_LOCKABLE] +Integer = 0 + +[XCHAL_HAVE_PSO] +Integer = 0 + +[XCHAL_HW_MIN_VERSION_MINOR] +Integer = 9 + +[XCHAL_INT26_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_PSO_CDM] +Integer = 0 + +[XCHAL_VECBASE_RESET_PADDR] +Integer = 1073741824 + +[XCHAL_HAVE_VECTRA1] +Integer = 0 + +[XCHAL_PDX_SIMD32] +Integer = 0 + +[XCHAL_NUM_AREGS_LOG2] +Integer = 6 + +[XCHAL_HAVE_ABSOLUTE_LITERALS] +Integer = 0 + +[XCHAL_HAVE_DCACHE_DYN_WAYS] +Integer = 0 + +[XCHAL_NUM_IBREAK] +Integer = 2 + +[XCHAL_DCACHE_SETWIDTH] +Integer = 0 + +[XCHAL_EXTINT1_NUM] +Integer = 1 + +[XCHAL_WINDOW_UF8_VECOFS] +Integer = 192 + +[XCHAL_INT19_LEVEL] +Integer = 2 + +[XCHAL_HAVE_FUSION_AVS] +Integer = 0 + +[XCHAL_INT5_LEVEL] +Integer = 1 + +[XCHAL_HW_CONFIGID0] +Integer = 3270310654 + +[XCHAL_HAVE_FULL_RESET] +Integer = 1 + +[XCHAL_INT14_LEVEL] +Integer = 7 + +[XCHAL_INSTRAM1_HAVE_IDMA] +Integer = 0 + +[XCHAL_NUM_CONTEXTS] +Integer = 1 + +[XCHAL_HAVE_MX] +Integer = 0 + +[XCHAL_XLMI0_VADDR] +Integer = 1061158912 + +[XCHAL_HAVE_EXCLUSIVE] +Integer = 0 + +[XCHAL_HAVE_DEBUG_APB] +Integer = 0 + +[XCHAL_HAVE_VISION] +Integer = 0 + +[XCHAL_HAVE_INTERRUPTS] +Integer = 1 + +[XCHAL_INTTYPE_MASK_EXTERN_EDGE] +Integer = 1346372608 + +[XCHAL_HAVE_FUSIONG] +Integer = 0 + +[XCHAL_INTLEVEL6_MASK] +Integer = 0 + +[XCHAL_INT25_EXTNUM] +Integer = 20 + +[XCHAL_INT2_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_PIF] +Integer = 1 + +[XCHAL_HAVE_DEBUG_EXTERN_INT] +Integer = 1 + +[XCHAL_NUM_LOADSTORE_UNITS] +Integer = 1 + +[XCHAL_INTLEVEL6_VECTOR_VADDR] +Integer = 1073742464 + +[XCHAL_HAVE_FP_DIV] +Integer = 0 + +[XCHAL_HAVE_DFP_SQRT] +Integer = 0 + +[XCHAL_HAVE_TRAX] +Integer = 1 + +[XCHAL_HAVE_OCD_DIR_ARRAY] +Integer = 0 + +[XCHAL_INTLEVEL2_ANDBELOW_MASK] +Integer = 4077567 + +[XCHAL_HAVE_XEAX] +Integer = 0 + +[XCHAL_UNALIGNED_STORE_HW] +Integer = 1 + +[XCHAL_CORE_ID] +String = "esp_core_722_f" + +[XCHAL_INT12_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_TLBS] +Integer = 1 + +[XCHAL_NUM_INTLEVELS] +Integer = 6 + +[XCHAL_HAVE_NSA] +Integer = 1 + +[XCHAL_WINDOW_VECTORS_PADDR] +Integer = 1073741824 + +[XCHAL_PREFETCH_ENTRIES] +Integer = 0 + +[XCHAL_INT8_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_TIMER1_INTERRUPT] +Integer = 15 + +[XCHAL_INT24_EXTNUM] +Integer = 19 + +[XCHAL_INT21_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_KERNEL_VECTOR_PADDR] +Integer = 1073742592 + +[XCHAL_HAVE_LOOPS] +Integer = 0 + +[XCHAL_INT23_EXTNUM] +Integer = 18 + +[XCHAL_NUM_WRITEBUFFER_ENTRIES] +Integer = 4 + +[XCHAL_HAVE_PIF_REQ_ATTR] +Integer = 1 + +[XCHAL_INTLEVEL4_MASK] +Integer = 1392508928 + +[XCHAL_MMU_ASID_BITS] +Integer = 0 + +[XCHAL_INT28_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_HAVE_USER_SPFPU] +Integer = 0 + +[XCHAL_HAVE_FUSION_LOW_POWER] +Integer = 0 + +[XCHAL_HAVE_SSP16_VITERBI] +Integer = 0 + +[XCHAL_HAVE_INSTRAM1] +Integer = 1 + +[XCHAL_INSTRAM1_ECC_PARITY] +Integer = 0 + +[XCHAL_HAVE_IDMA] +Integer = 0 + +[XCHAL_HAVE_FUSION_AES] +Integer = 0 + +[XCHAL_INTTYPE_MASK_NMI] +Integer = 16384 + +[XCHAL_HAVE_FUSIONG_SP_VFPU] +Integer = 0 + +[XCHAL_HAVE_GRIVPEP] +Integer = 0 + +[XCHAL_HAVE_CALL4AND12] +Integer = 1 + +[XCHAL_INTLEVEL4_VECTOR_PADDR] +Integer = 1073742336 + +[XCHAL_INT0_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_DATARAM1_BANKS] +Integer = 1 + +[XCHAL_INTLEVEL4_VECTOR_VADDR] +Integer = 1073742336 + +[XCHAL_HAVE_CP] +Integer = 1 + +[XCHAL_PREFETCH_BLOCK_ENTRIES] +Integer = 0 + +[XCHAL_DEBUG_VECOFS] +Integer = 640 + +[XCHAL_INT23_LEVEL] +Integer = 3 + +[XCHAL_TIMER0_INTERRUPT] +Integer = 6 + +[XCHAL_HAVE_VISIONC] +Integer = 0 + +[XCHAL_DATARAM0_PADDR] +Integer = 1069547520 + +[XCHAL_VECBASE_RESET_VADDR] +Integer = 1073741824 + +[XCHAL_HAVE_IDENTITY_MAP] +Integer = 1 + +[XCHAL_HAVE_PRID] +Integer = 1 + +[XCHAL_NUM_INSTRAM] +Integer = 2 + +[XCHAL_INT17_EXTNUM] +Integer = 12 + +[XCHAL_TIMER3_INTERRUPT] +Interrupt = "TimerUnconfigured" + +[XCHAL_INT21_EXTNUM] +Integer = 16 + +[XCHAL_DCACHE_WAYS] +Integer = 1 + +[XCHAL_HAVE_SEXT] +Integer = 1 + +[XCHAL_INSTRAM0_ECC_PARITY] +Integer = 0 + +[XCHAL_INT26_EXTNUM] +Integer = 21 + +[XCHAL_KERNEL_VECOFS] +Integer = 768 + +[XCHAL_INT31_EXTNUM] +Integer = 25 + +[XCHAL_EXTINT12_NUM] +Integer = 17 + +[XCHAL_HAVE_BBP16] +Integer = 0 + +[XCHAL_INT13_EXTNUM] +Integer = 10 + +[XCHAL_INT16_TYPE] +Interrupt = "Timer" + +[XCHAL_DATAROM0_PADDR] +Integer = 1056964608 + +[XCHAL_WINDOW_UF12_VECOFS] +Integer = 320 + +[XCHAL_INTLEVEL7_VECTOR_PADDR] +Integer = 1073742528 + +[XCHAL_INTLEVEL5_VECTOR_VADDR] +Integer = 1073742400 + +[XCHAL_HAVE_FUSION_CONVENC] +Integer = 0 + +[XCHAL_HAVE_HIFI3_VFPU] +Integer = 0 + +[XCHAL_DCACHE_LINEWIDTH] +Integer = 2 + +[XCHAL_CA_BITS] +Integer = 4 + +[XCHAL_HAVE_EXCEPTIONS] +Integer = 1 + +[XCHAL_HAVE_DATARAM1] +Integer = 1 + +[XCHAL_INSTRAM0_SIZE] +Integer = 4194304 + +[XCHAL_HAVE_MP_INTERRUPTS] +Integer = 0 + +[XCHAL_HAVE_FUSION_SOFTDEMAP] +Integer = 0 + +[XCHAL_EXTINT25_NUM] +Integer = 31 + +[XCHAL_USER_VECOFS] +Integer = 832 + +[XCHAL_INSTROM0_SIZE] +Integer = 4194304 + +[XCHAL_HAVE_BOOLEANS] +Integer = 0 + +[XCHAL_HAVE_FUSION_BITOPS] +Integer = 0 + +[XCHAL_INT8_LEVEL] +Integer = 1 + +[XCHAL_HAVE_DFP_RECIP] +Integer = 0 + +[XCHAL_INT13_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_BBE16_RSQRT] +Integer = 0 + +[XCHAL_HW_MAX_VERSION_MINOR] +Integer = 9 + +[XCHAL_INT9_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT18_LEVEL] +Integer = 1 diff --git a/xtensa-lx-rt/config/xtensa_esp32s3.toml b/xtensa-lx-rt/config/xtensa_esp32s3.toml new file mode 100644 index 0000000..73cc317 --- /dev/null +++ b/xtensa-lx-rt/config/xtensa_esp32s3.toml @@ -0,0 +1,1409 @@ +[XCHAL_INTLEVEL7_VECTOR_VADDR] +Integer = 1073742528 + +[XCHAL_HAVE_EXTERN_REGS] +Integer = 1 + +[XCHAL_WINDOW_VECTORS_PADDR] +Integer = 1073741824 + +[XCHAL_HAVE_MX] +Integer = 0 + +[XCHAL_HAVE_FP_RSQRT] +Integer = 1 + +[XCHAL_UNALIGNED_STORE_HW] +Integer = 1 + +[XCHAL_INTLEVEL6_MASK] +Integer = 0 + +[XCHAL_VECBASE_RESET_PADDR] +Integer = 1073741824 + +[XCHAL_KERNEL_VECTOR_PADDR] +Integer = 1073742592 + +[XCHAL_HAVE_MPU] +Integer = 0 + +[XCHAL_NUM_INSTRAM] +Integer = 1 + +[XCHAL_INT2_LEVEL] +Integer = 1 + +[XCHAL_INTTYPE_MASK_PROFILING] +Integer = 2048 + +[XCHAL_INT28_EXTNUM] +Integer = 23 + +[XCHAL_HAVE_HIFI4] +Integer = 0 + +[XCHAL_HAVE_USER_DPFPU] +Integer = 0 + +[XCHAL_HAVE_HIFI5_VFPU] +Integer = 0 + +[XCHAL_DCACHE_LINE_LOCKABLE] +Integer = 0 + +[XCHAL_HAVE_VISION_HISTOGRAM] +Integer = 0 + +[XCHAL_HAVE_L32R] +Integer = 1 + +[XCHAL_HAVE_BBE16] +Integer = 0 + +[XCHAL_TIMER0_INTERRUPT] +Integer = 6 + +[XCHAL_EXTINT12_NUM] +Integer = 17 + +[XCHAL_TIMER2_INTERRUPT] +Integer = 16 + +[XCHAL_EXTINT23_NUM] +Integer = 28 + +[XCHAL_MPU_ALIGN_REQ] +Integer = 1 + +[XCHAL_NMI_VECOFS] +Integer = 704 + +[XCHAL_HW_VERSION_MAJOR] +Integer = 2700 + +[XCHAL_INT30_LEVEL] +Integer = 4 + +[XCHAL_EXTINT14_NUM] +Integer = 19 + +[XCHAL_HAVE_DEBUG_ERI] +Integer = 1 + +[XCHAL_HAVE_DFPU_SINGLE_ONLY] +Integer = 1 + +[XCHAL_INTLEVEL3_VECTOR_VADDR] +Integer = 1073742272 + +[XCHAL_INTLEVEL7_VECOFS] +Integer = 704 + +[XCHAL_HAVE_MEM_ECC_PARITY] +Integer = 0 + +[XCHAL_WINDOW_UF8_VECOFS] +Integer = 192 + +[XCHAL_SPANNING_WAY] +Integer = 0 + +[XCHAL_INT3_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT26_LEVEL] +Integer = 5 + +[XCHAL_INT4_LEVEL] +Integer = 1 + +[XCHAL_HAVE_FP_DIV] +Integer = 1 + +[XCHAL_INTLEVEL2_MASK] +Integer = 3670016 + +[XCHAL_EXTINT13_NUM] +Integer = 18 + +[XCHAL_INT13_LEVEL] +Integer = 1 + +[XCHAL_HAVE_CLAMPS] +Integer = 1 + +[XCHAL_INT31_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_EXTINT0_NUM] +Integer = 0 + +[XCHAL_HAVE_PDX16] +Integer = 0 + +[XCHAL_INT30_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_HAVE_IDMA_TRANSPOSE] +Integer = 0 + +[XCHAL_HAVE_WIDE_BRANCHES] +Integer = 0 + +[XCHAL_HAVE_DFP_ACCEL] +Integer = 0 + +[XCHAL_HAVE_CCOUNT] +Integer = 1 + +[XCHAL_CORE_ID] +String = "LX7_ESP32_S3_MP" + +[XCHAL_HAVE_HALT] +Integer = 0 + +[XCHAL_INT13_EXTNUM] +Integer = 10 + +[XCHAL_HW_REL_LX7_0_12] +Integer = 1 + +[XCHAL_INT16_TYPE] +Interrupt = "Timer" + +[XCHAL_HAVE_CONST16] +Integer = 0 + +[XCHAL_HAVE_SPECULATION] +Integer = 0 + +[XCHAL_NUM_CONTEXTS] +Integer = 1 + +[XCHAL_INTLEVEL5_MASK] +Integer = 2214658048 + +[XCHAL_HAVE_MAC16] +Integer = 1 + +[XCHAL_DEBUGLEVEL] +Integer = 6 + +[XCHAL_TRAX_ATB_WIDTH] +Integer = 0 + +[XCHAL_HAVE_HIFI3Z_VFPU] +Integer = 0 + +[XCHAL_INTLEVEL4_VECTOR_VADDR] +Integer = 1073742336 + +[XCHAL_INT5_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT9_EXTNUM] +Integer = 7 + +[XCHAL_INT11_TYPE] +Interrupt = "Profiling" + +[XCHAL_HAVE_HIFI2] +Integer = 0 + +[XCHAL_HAVE_IMEM_LOADSTORE] +Integer = 1 + +[XCHAL_HAVE_CACHE_BLOCKOPS] +Integer = 0 + +[XCHAL_HAVE_ICACHE_TEST] +Integer = 0 + +[XCHAL_INTLEVEL7_VECTOR_PADDR] +Integer = 1073742528 + +[XCHAL_TRAX_TIME_WIDTH] +Integer = 0 + +[XCHAL_EXTINT9_NUM] +Integer = 12 + +[XCHAL_INT4_EXTNUM] +Integer = 4 + +[XCHAL_HAVE_PRID] +Integer = 1 + +[XCHAL_INT27_LEVEL] +Integer = 3 + +[XCHAL_DATARAM0_VADDR] +Integer = 1006632960 + +[XCHAL_EXTINT19_NUM] +Integer = 24 + +[XCHAL_ICACHE_LINE_LOCKABLE] +Integer = 0 + +[XCHAL_HAVE_HIFI5_NN_MAC] +Integer = 0 + +[XCHAL_DCACHE_LINESIZE] +Integer = 16 + +[XCHAL_HAVE_ADDX] +Integer = 1 + +[XCHAL_HAVE_AXI_ECC] +Integer = 0 + +[XCHAL_INT25_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_HIFI3Z] +Integer = 0 + +[XCHAL_HAVE_PSO_CDM] +Integer = 0 + +[XCHAL_MMU_RING_BITS] +Integer = 0 + +[XCHAL_HAVE_INTERRUPTS] +Integer = 1 + +[XCHAL_EXTINT15_NUM] +Integer = 20 + +[XCHAL_HAVE_SSP16_VITERBI] +Integer = 0 + +[XCHAL_INTLEVEL6_VECOFS] +Integer = 640 + +[XCHAL_HAVE_FUSIONG6] +Integer = 0 + +[XCHAL_TRAX_MEM_SIZE] +Integer = 16384 + +[XCHAL_INTLEVEL6_VECTOR_VADDR] +Integer = 1073742464 + +[XCHAL_NUM_MISC_REGS] +Integer = 4 + +[XCHAL_INT2_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_MIMIC_CACHEATTR] +Integer = 1 + +[XCHAL_HAVE_HIFI2EP] +Integer = 0 + +[XCHAL_HAVE_MP_INTERRUPTS] +Integer = 0 + +[XCHAL_WINDOW_UF4_VECOFS] +Integer = 64 + +[XCHAL_NUM_AREGS_LOG2] +Integer = 6 + +[XCHAL_INT1_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_XLT_CACHEATTR] +Integer = 0 + +[XCHAL_INT19_LEVEL] +Integer = 2 + +[XCHAL_INTLEVEL3_VECTOR_PADDR] +Integer = 1073742272 + +[XCHAL_DATA_PIPE_DELAY] +Integer = 1 + +[XCHAL_INTLEVEL2_VECTOR_PADDR] +Integer = 1073742208 + +[XCHAL_MPU_ALIGN] +Integer = 0 + +[XCHAL_HAVE_FUSION_LFSR_CRC] +Integer = 0 + +[XCHAL_INT23_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_CLOCK_GATING_GLOBAL] +Integer = 1 + +[XCHAL_INT12_EXTNUM] +Integer = 9 + +[XCHAL_INTTYPE_MASK_EXTERN_LEVEL] +Integer = 2411606847 + +[XCHAL_EXTINT5_NUM] +Integer = 5 + +[XCHAL_HAVE_VISION] +Integer = 0 + +[XCHAL_DOUBLEEXC_VECTOR_VADDR] +Integer = 1073742784 + +[XCHAL_NMI_INTERRUPT] +Integer = 14 + +[XCHAL_EXTINT7_NUM] +Integer = 9 + +[XCHAL_EXTINT22_NUM] +Integer = 27 + +[XCHAL_HAVE_XEAX] +Integer = 0 + +[XCHAL_INTLEVEL5_VECTOR_VADDR] +Integer = 1073742400 + +[XCHAL_INTTYPE_MASK_IDMA_DONE] +Integer = 0 + +[XCHAL_NUM_URAM] +Integer = 0 + +[XCHAL_INT1_LEVEL] +Integer = 1 + +[XCHAL_HAVE_DFP] +Integer = 0 + +[XCHAL_INT8_EXTNUM] +Integer = 6 + +[XCHAL_HAVE_SSP16] +Integer = 0 + +[XCHAL_HW_CONFIGID1] +Integer = 587796255 + +[XCHAL_HAVE_MUL32] +Integer = 1 + +[XCHAL_DATARAM0_SIZE] +Integer = 67108864 + +[XCHAL_DCACHE_WAYS] +Integer = 1 + +[XCHAL_HAVE_EXCLUSIVE] +Integer = 0 + +[XCHAL_HAVE_MINMAX] +Integer = 1 + +[XCHAL_INT27_EXTNUM] +Integer = 22 + +[XCHAL_INT15_LEVEL] +Integer = 3 + +[XCHAL_INTLEVEL3_VECOFS] +Integer = 448 + +[XCHAL_HAVE_FP_SQRT] +Integer = 1 + +[XCHAL_HAVE_ACELITE] +Integer = 0 + +[XCHAL_HAVE_BE] +Integer = 0 + +[XCHAL_INTLEVEL1_MASK] +Integer = 407551 + +[XCHAL_KERNEL_VECTOR_VADDR] +Integer = 1073742592 + +[XCHAL_INT12_LEVEL] +Integer = 1 + +[XCHAL_ICACHE_SIZE] +Integer = 0 + +[XCHAL_HW_MIN_VERSION_MAJOR] +Integer = 2700 + +[XCHAL_HAVE_HIFI3] +Integer = 0 + +[XCHAL_USER_VECTOR_VADDR] +Integer = 1073742656 + +[XCHAL_HW_VERSION_MINOR] +Integer = 12 + +[XCHAL_INT17_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_DCACHE_ECC_PARITY] +Integer = 0 + +[XCHAL_INT20_LEVEL] +Integer = 2 + +[XCHAL_INTLEVEL5_VECTOR_PADDR] +Integer = 1073742400 + +[XCHAL_HAVE_HIFI_MINI] +Integer = 0 + +[XCHAL_HW_MAX_VERSION_MAJOR] +Integer = 2700 + +[XCHAL_DATARAM0_HAVE_IDMA] +Integer = 0 + +[XCHAL_WINDOW_OF12_VECOFS] +Integer = 256 + +[XCHAL_HAVE_VECTRALX] +Integer = 0 + +[XCHAL_DCACHE_IS_COHERENT] +Integer = 0 + +[XCHAL_INT24_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INTLEVEL1_ANDBELOW_MASK] +Integer = 407551 + +[XCHAL_HAVE_BBENEP] +Integer = 0 + +[XCHAL_NUM_DATAROM] +Integer = 0 + +[XCHAL_NUM_DATARAM] +Integer = 1 + +[XCHAL_HAVE_FULL_RESET] +Integer = 1 + +[XCHAL_HW_MAX_VERSION] +Integer = 270012 + +[XCHAL_EXTINT11_NUM] +Integer = 14 + +[XCHAL_INT5_EXTNUM] +Integer = 5 + +[XCHAL_VISION_SIMD16] +Integer = 0 + +[XCHAL_INT19_EXTNUM] +Integer = 14 + +[XCHAL_NUM_INSTROM] +Integer = 0 + +[XCHAL_HAVE_CP] +Integer = 1 + +[XCHAL_NUM_TIMERS] +Integer = 3 + +[XCHAL_ICACHE_ECC_WIDTH] +Integer = 1 + +[XCHAL_ICACHE_LINEWIDTH] +Integer = 2 + +[XCHAL_INSTRAM0_SIZE] +Integer = 67108864 + +[XCHAL_HW_VERSION_NAME] +String = "LX7.0.12" + +[XCHAL_HAVE_XEA2] +Integer = 1 + +[XCHAL_INTLEVEL7_ANDBELOW_MASK] +Integer = 4294967295 + +[XCHAL_INT16_LEVEL] +Integer = 5 + +[XCHAL_INT9_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_BSP3_TRANSPOSE] +Integer = 0 + +[XCHAL_INT6_TYPE] +Interrupt = "Timer" + +[XCHAL_INT7_LEVEL] +Integer = 1 + +[XCHAL_NUM_PERF_COUNTERS] +Integer = 2 + +[XCHAL_INT0_EXTNUM] +Integer = 0 + +[XCHAL_TRAX_MEM_SHAREABLE] +Integer = 1 + +[XCHAL_INT30_EXTNUM] +Integer = 24 + +[XCHAL_EXCM_LEVEL] +Integer = 3 + +[XCHAL_INT3_LEVEL] +Integer = 1 + +[XCHAL_HAVE_DFPU_SINGLE_DOUBLE] +Integer = 0 + +[XCHAL_HAVE_BBE16_DESPREAD] +Integer = 0 + +[XCHAL_INT24_EXTNUM] +Integer = 19 + +[XCHAL_EXTINT17_NUM] +Integer = 22 + +[XCHAL_HAVE_IDMA] +Integer = 0 + +[XCHAL_HAVE_DFP_accel] +Integer = 0 + +[XCHAL_HAVE_DEBUG_JTAG] +Integer = 1 + +[XCHAL_INT18_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_DCACHE_ECC_WIDTH] +Integer = 1 + +[XCHAL_INT10_LEVEL] +Integer = 1 + +[XCHAL_MPU_ALIGN_BITS] +Integer = 0 + +[XCHAL_HAVE_PIF_REQ_ATTR] +Integer = 1 + +[XCHAL_INT9_LEVEL] +Integer = 1 + +[XCHAL_INTLEVEL3_MASK] +Integer = 683706368 + +[XCHAL_NUM_INTERRUPTS] +Integer = 32 + +[XCHAL_HAVE_AXI] +Integer = 0 + +[XCHAL_INT19_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT23_EXTNUM] +Integer = 18 + +[XCHAL_HAVE_DEPBITS] +Integer = 0 + +[XCHAL_HAVE_NSA] +Integer = 1 + +[XCHAL_HAVE_CONNXD2_DUALLSFLIX] +Integer = 0 + +[XCHAL_XEA_VERSION] +Integer = 2 + +[XCHAL_INTLEVEL7_NUM] +Integer = 14 + +[XCHAL_INT15_TYPE] +Interrupt = "Timer" + +[XCHAL_INSTRAM0_HAVE_IDMA] +Integer = 0 + +[XCHAL_INTLEVEL3_ANDBELOW_MASK] +Integer = 687783935 + +[XCHAL_INT10_EXTNUM] +Integer = 8 + +[XCHAL_HAVE_PREFETCH] +Integer = 0 + +[XCHAL_INT4_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_DCACHE_TEST] +Integer = 0 + +[XCHAL_INT22_LEVEL] +Integer = 3 + +[XCHAL_ICACHE_ECC_PARITY] +Integer = 0 + +[XCHAL_INTTYPE_MASK_TIMER] +Integer = 98368 + +[XCHAL_INTTYPE_MASK_SOFTWARE] +Integer = 536871040 + +[XCHAL_HAVE_FP_RECIP] +Integer = 1 + +[XCHAL_INTTYPE_MASK_EXTERN_EDGE] +Integer = 1346372608 + +[XCHAL_EXTINT20_NUM] +Integer = 25 + +[XCHAL_MAX_INSTRUCTION_SIZE] +Integer = 4 + +[XCHAL_HAVE_PTP_MMU] +Integer = 0 + +[XCHAL_HAVE_VECTRA1] +Integer = 0 + +[XCHAL_WINDOW_VECTORS_VADDR] +Integer = 1073741824 + +[XCHAL_HAVE_FUSION_VITERBI] +Integer = 0 + +[XCHAL_INTLEVEL5_ANDBELOW_MASK] +Integer = 4294950911 + +[XCHAL_HAVE_FUSIONG_SP_VFPU] +Integer = 0 + +[XCHAL_HAVE_CACHEATTR] +Integer = 0 + +[XCHAL_INT8_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT11_LEVEL] +Integer = 3 + +[XCHAL_HAVE_FUSION_BITOPS] +Integer = 0 + +[XCHAL_HAVE_FUSION_LOW_POWER] +Integer = 0 + +[XCHAL_VISION_QUAD_MAC_TYPE] +Integer = 0 + +[XCHAL_INT21_LEVEL] +Integer = 2 + +[XCHAL_INTLEVEL4_ANDBELOW_MASK] +Integer = 2080292863 + +[XCHAL_UNALIGNED_LOAD_EXCEPTION] +Integer = 0 + +[XCHAL_HAVE_FUSION_CONVENC] +Integer = 0 + +[XCHAL_HAVE_SEXT] +Integer = 1 + +[XCHAL_HAVE_DATARAM0] +Integer = 1 + +[XCHAL_HAVE_FUSION] +Integer = 0 + +[XCHAL_HAVE_PREFETCH_L1] +Integer = 0 + +[XCHAL_INT29_LEVEL] +Integer = 3 + +[XCHAL_HAVE_MUL16] +Integer = 1 + +[XCHAL_HAVE_FLIX3] +Integer = 0 + +[XCHAL_UNALIGNED_LOAD_HW] +Integer = 1 + +[XCHAL_NUM_INTERRUPTS_LOG2] +Integer = 5 + +[XCHAL_HAVE_EXCEPTIONS] +Integer = 1 + +[XCHAL_HAVE_FUSIONG_DP_VFPU] +Integer = 0 + +[XCHAL_HW_CONFIGID_RELIABLE] +Integer = 1 + +[XCHAL_INT14_EXTNUM] +Integer = 11 + +[XCHAL_NMI_VECTOR_VADDR] +Integer = 1073742528 + +[XCHAL_HW_REL_LX7] +Integer = 1 + +[XCHAL_INT28_LEVEL] +Integer = 4 + +[XCHAL_HAVE_SPANNING_WAY] +Integer = 1 + +[XCHAL_HAVE_OCD] +Integer = 1 + +[XCHAL_HAVE_OCD_DIR_ARRAY] +Integer = 0 + +[XCHAL_INTLEVEL4_VECOFS] +Integer = 512 + +[XCHAL_DATARAM0_BANKS] +Integer = 1 + +[XCHAL_HW_MAX_VERSION_MINOR] +Integer = 12 + +[XCHAL_HAVE_ICACHE_DYN_WAYS] +Integer = 0 + +[XCHAL_DCACHE_BANKS] +Integer = 0 + +[XCHAL_INT21_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_TAP_MASTER] +Integer = 0 + +[XCHAL_HAVE_DEBUG_APB] +Integer = 0 + +[XCHAL_HAVE_VECBASE] +Integer = 1 + +[XCHAL_INT21_EXTNUM] +Integer = 16 + +[XCHAL_PREFETCH_CASTOUT_LINES] +Integer = 0 + +[XCHAL_HAVE_DIV32] +Integer = 1 + +[XCHAL_DATA_WIDTH] +Integer = 16 + +[XCHAL_EXTINT18_NUM] +Integer = 23 + +[XCHAL_WINDOW_OF4_VECOFS] +Integer = 0 + +[XCHAL_HAVE_HIFI5] +Integer = 0 + +[XCHAL_INSTRAM0_PADDR] +Integer = 1073741824 + +[XCHAL_PREFETCH_ENTRIES] +Integer = 0 + +[XCHAL_INTLEVEL2_ANDBELOW_MASK] +Integer = 4077567 + +[XCHAL_HAVE_USER_SPFPU] +Integer = 0 + +[XCHAL_INT12_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_MPU_ENTRIES] +Integer = 0 + +[XCHAL_HW_VERSION] +Integer = 270012 + +[XCHAL_HAVE_PIF_WR_RESP] +Integer = 0 + +[XCHAL_INT29_TYPE] +Interrupt = "Software" + +[XCHAL_ICACHE_SETWIDTH] +Integer = 0 + +[XCHAL_DATARAM0_PADDR] +Integer = 1006632960 + +[XCHAL_INT20_EXTNUM] +Integer = 15 + +[XCHAL_HAVE_HIGHPRI_INTERRUPTS] +Integer = 1 + +[XCHAL_HAVE_DENSITY] +Integer = 1 + +[XCHAL_INT26_EXTNUM] +Integer = 21 + +[XCHAL_LOOP_BUFFER_SIZE] +Integer = 256 + +[XCHAL_HAVE_FUSION_AVS] +Integer = 0 + +[XCHAL_INTTYPE_MASK_IDMA_ERR] +Integer = 0 + +[XCHAL_EXTINT25_NUM] +Integer = 31 + +[XCHAL_HAVE_BBE16_VECDIV] +Integer = 0 + +[XCHAL_DEBUG_VECTOR_PADDR] +Integer = 1073742464 + +[XCHAL_HAVE_TLBS] +Integer = 1 + +[XCHAL_EXTINT1_NUM] +Integer = 1 + +[XCHAL_MPU_BACKGROUND_ENTRIES] +Integer = 0 + +[XCHAL_NUM_INTLEVELS] +Integer = 6 + +[XCHAL_HAVE_FUSIONG] +Integer = 0 + +[XCHAL_INT0_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_HAVE_PDX4] +Integer = 0 + +[XCHAL_INT23_LEVEL] +Integer = 3 + +[XCHAL_RESET_VECTOR0_PADDR] +Integer = 1342177280 + +[XCHAL_INT17_EXTNUM] +Integer = 12 + +[XCHAL_HAVE_ABS] +Integer = 1 + +[XCHAL_INST_FETCH_WIDTH] +Integer = 4 + +[XCHAL_DCACHE_LINEWIDTH] +Integer = 4 + +[XCHAL_ICACHE_ACCESS_SIZE] +Integer = 1 + +[XCHAL_INT14_TYPE] +Interrupt = "Nmi" + +[XCHAL_HAVE_PREDICTED_BRANCHES] +Integer = 0 + +[XCHAL_CA_BITS] +Integer = 4 + +[XCHAL_INTTYPE_MASK_WRITE_ERROR] +Integer = 0 + +[XCHAL_HAVE_DEBUG_EXTERN_INT] +Integer = 1 + +[XCHAL_HAVE_DCACHE_DYN_WAYS] +Integer = 0 + +[XCHAL_NUM_XLMI] +Integer = 0 + +[XCHAL_EXTINT4_NUM] +Integer = 4 + +[XCHAL_HAVE_DFP_RECIP] +Integer = 0 + +[XCHAL_INT1_EXTNUM] +Integer = 1 + +[XCHAL_INT2_EXTNUM] +Integer = 2 + +[XCHAL_INT13_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INTLEVEL2_VECOFS] +Integer = 384 + +[XCHAL_EXTINT8_NUM] +Integer = 10 + +[XCHAL_HAVE_CALL4AND12] +Integer = 1 + +[XCHAL_INT22_EXTNUM] +Integer = 17 + +[XCHAL_EXTINT6_NUM] +Integer = 8 + +[XCHAL_HAVE_THREADPTR] +Integer = 1 + +[XCHAL_NMILEVEL] +Integer = 7 + +[XCHAL_HAVE_PSO] +Integer = 0 + +[XCHAL_HAVE_IDENTITY_MAP] +Integer = 1 + +[XCHAL_MPU_BG_CACHEADRDIS] +Integer = 0 + +[XCHAL_RESET_VECTOR1_VADDR] +Integer = 1073742848 + +[XCHAL_HAVE_NMI] +Integer = 1 + +[XCHAL_HAVE_MUL32_HIGH] +Integer = 1 + +[XCHAL_PREFETCH_BLOCK_ENTRIES] +Integer = 0 + +[XCHAL_RESET_VECTOR1_PADDR] +Integer = 1073742848 + +[XCHAL_HAVE_FUSION_AES] +Integer = 0 + +[XCHAL_HAVE_FUSIONG3] +Integer = 0 + +[XCHAL_MMU_RINGS] +Integer = 1 + +[XCHAL_FUSIONG_SIMD32] +Integer = 0 + +[XCHAL_RESET_VECBASE_OVERLAP] +Integer = 0 + +[XCHAL_KERNEL_VECOFS] +Integer = 768 + +[XCHAL_HAVE_GRIVPEP_HISTOGRAM] +Integer = 0 + +[XCHAL_HAVE_FUSION_16BIT_BASEBAND] +Integer = 0 + +[XCHAL_HAVE_RELEASE_SYNC] +Integer = 1 + +[XCHAL_NUM_WRITEBUFFER_ENTRIES] +Integer = 4 + +[XCHAL_INT31_EXTNUM] +Integer = 25 + +[XCHAL_HAVE_DFP_SQRT] +Integer = 0 + +[XCHAL_HW_MIN_VERSION] +Integer = 270012 + +[XCHAL_DCACHE_SIZE] +Integer = 0 + +[XCHAL_HAVE_DEBUG] +Integer = 1 + +[XCHAL_INT26_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_EXTINT10_NUM] +Integer = 13 + +[XCHAL_INT25_LEVEL] +Integer = 4 + +[XCHAL_NUM_EXTINTERRUPTS] +Integer = 26 + +[XCHAL_INT18_EXTNUM] +Integer = 13 + +[XCHAL_EXTINT16_NUM] +Integer = 21 + +[XCHAL_USER_VECTOR_PADDR] +Integer = 1073742656 + +[XCHAL_HAVE_VISIONC] +Integer = 0 + +[XCHAL_HW_REL_LX7_0] +Integer = 1 + +[XCHAL_HAVE_BBE16_RSQRT] +Integer = 0 + +[XCHAL_HAVE_WINDOWED] +Integer = 1 + +[XCHAL_BUILD_UNIQUE_ID] +Integer = 593695 + +[XCHAL_INTLEVEL4_MASK] +Integer = 1392508928 + +[XCHAL_NUM_LOADSTORE_UNITS] +Integer = 1 + +[XCHAL_INT25_EXTNUM] +Integer = 20 + +[XCHAL_HAVE_FUSION_FP] +Integer = 0 + +[XCHAL_INSTRAM0_VADDR] +Integer = 1073741824 + +[XCHAL_WINDOW_OF8_VECOFS] +Integer = 128 + +[XCHAL_INTLEVEL2_VECTOR_VADDR] +Integer = 1073742208 + +[XCHAL_INTLEVEL5_VECOFS] +Integer = 576 + +[XCHAL_HAVE_TRAX] +Integer = 1 + +[XCHAL_DOUBLEEXC_VECOFS] +Integer = 960 + +[XCHAL_HAVE_FUSION_SOFTDEMAP] +Integer = 0 + +[XCHAL_DEBUG_VECTOR_VADDR] +Integer = 1073742464 + +[XCHAL_NUM_DBREAK] +Integer = 2 + +[XCHAL_ICACHE_WAYS] +Integer = 1 + +[XCHAL_INT17_LEVEL] +Integer = 1 + +[XCHAL_INT18_LEVEL] +Integer = 1 + +[XCHAL_INT14_LEVEL] +Integer = 7 + +[XCHAL_HAVE_MP_RUNSTALL] +Integer = 0 + +[XCHAL_HAVE_TURBO16] +Integer = 0 + +[XCHAL_HAVE_VECTOR_SELECT] +Integer = 1 + +[XCHAL_HAVE_BOOLEANS] +Integer = 1 + +[XCHAL_HAVE_GRIVPEP] +Integer = 0 + +[XCHAL_HAVE_DFP_DIV] +Integer = 0 + +[XCHAL_DCACHE_ACCESS_SIZE] +Integer = 1 + +[XCHAL_INT10_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_HAVE_LOOPS] +Integer = 1 + +[XCHAL_HAVE_HIFIPRO] +Integer = 0 + +[XCHAL_SW_VERSION] +Integer = 1200012 + +[XCHAL_HW_MIN_VERSION_MINOR] +Integer = 12 + +[XCHAL_ICACHE_LINESIZE] +Integer = 4 + +[XCHAL_HAVE_PDX] +Integer = 0 + +[XCHAL_INT24_LEVEL] +Integer = 4 + +[XCHAL_INT20_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INT3_EXTNUM] +Integer = 3 + +[XCHAL_WINDOW_UF12_VECOFS] +Integer = 320 + +[XCHAL_HAVE_VISION_SP_VFPU] +Integer = 0 + +[XCHAL_HAVE_PIF] +Integer = 1 + +[XCHAL_INT27_TYPE] +Interrupt = "ExternLevel" + +[XCHAL_INTTYPE_MASK_GS_ERR] +Integer = 0 + +[XCHAL_HAVE_PSO_FULL_RETENTION] +Integer = 0 + +[XCHAL_INTLEVEL4_VECTOR_PADDR] +Integer = 1073742336 + +[XCHAL_HAVE_HIFI5_HP_VFPU] +Integer = 0 + +[XCHAL_INT5_LEVEL] +Integer = 1 + +[XCHAL_HAVE_ABSOLUTE_LITERALS] +Integer = 0 + +[XCHAL_HAVE_CONNXD2] +Integer = 0 + +[XCHAL_DOUBLEEXC_VECTOR_PADDR] +Integer = 1073742784 + +[XCHAL_NUM_AREGS] +Integer = 64 + +[XCHAL_HAVE_HIFI3_VFPU] +Integer = 0 + +[XCHAL_HAVE_VECTORFPU2005] +Integer = 0 + +[XCHAL_INT28_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_INTTYPE_MASK_NMI] +Integer = 16384 + +[XCHAL_HAVE_S32C1I] +Integer = 1 + +[XCHAL_VECBASE_RESET_VADDR] +Integer = 1073741824 + +[XCHAL_VISION_TYPE] +Integer = 0 + +[XCHAL_DCACHE_IS_WRITEBACK] +Integer = 0 + +[XCHAL_PROFILING_INTERRUPT] +Integer = 11 + +[XCHAL_HAVE_BSP3] +Integer = 0 + +[XCHAL_INT8_LEVEL] +Integer = 1 + +[XCHAL_INTLEVEL7_MASK] +Integer = 16384 + +[XCHAL_HW_CONFIGID0] +Integer = 3270574078 + +[XCHAL_EXTINT21_NUM] +Integer = 26 + +[XCHAL_EXTINT24_NUM] +Integer = 30 + +[XCHAL_DCACHE_SETWIDTH] +Integer = 0 + +[XCHAL_HAVE_OCD_LS32DDR] +Integer = 1 + +[XCHAL_DEBUG_VECOFS] +Integer = 640 + +[XCHAL_INTTYPE_MASK_UNCONFIGURED] +Integer = 0 + +[XCHAL_INT0_LEVEL] +Integer = 1 + +[XCHAL_RESET_VECTOR_VADDR] +Integer = 1073742848 + +[XCHAL_CLOCK_GATING_FUNCUNIT] +Integer = 1 + +[XCHAL_TIMER1_INTERRUPT] +Integer = 15 + +[XCHAL_NUM_IBREAK] +Integer = 2 + +[XCHAL_DATARAM0_ECC_PARITY] +Integer = 0 + +[XCHAL_HAVE_BBP16] +Integer = 0 + +[XCHAL_HAVE_PDX8] +Integer = 0 + +[XCHAL_NMI_VECTOR_PADDR] +Integer = 1073742528 + +[XCHAL_UNALIGNED_STORE_EXCEPTION] +Integer = 0 + +[XCHAL_HAVE_HIFI4_VFPU] +Integer = 0 + +[XCHAL_INSTRAM0_ECC_PARITY] +Integer = 0 + +[XCHAL_RESET_VECTOR0_VADDR] +Integer = 1342177280 + +[XCHAL_INTLEVEL6_VECTOR_PADDR] +Integer = 1073742464 + +[XCHAL_PDX_SIMD32] +Integer = 0 + +[XCHAL_INT6_LEVEL] +Integer = 1 + +[XCHAL_HAVE_DFP_RSQRT] +Integer = 0 + +[XCHAL_HAVE_INSTRAM0] +Integer = 1 + +[XCHAL_RESET_VECTOR_PADDR] +Integer = 1073742848 + +[XCHAL_USER_VECOFS] +Integer = 832 + +[XCHAL_CP_MAXCFG] +Integer = 8 + +[XCHAL_MMU_ASID_BITS] +Integer = 0 + +[XCHAL_INTLEVEL6_ANDBELOW_MASK] +Integer = 4294950911 + +[XCHAL_INT22_TYPE] +Interrupt = "ExternEdge" + +[XCHAL_HAVE_XEA1] +Integer = 0 + +[XCHAL_HAVE_FP] +Integer = 1 + +[XCHAL_HAVE_BBENEP_SP_VFPU] +Integer = 0 + +[XCHAL_EXTINT3_NUM] +Integer = 3 + +[XCHAL_TIMER3_INTERRUPT] +Interrupt = "TimerUnconfigured" + +[XCHAL_HAVE_BOOTLOADER] +Integer = 0 + +[XCHAL_INT7_TYPE] +Interrupt = "Software" + +[XCHAL_INT31_LEVEL] +Integer = 5 + +[XCHAL_EXTINT2_NUM] +Integer = 2 + +[XCHAL_HAVE_VISION_HP_VFPU] +Integer = 0 diff --git a/xtensa-lx-rt/src/lib.rs b/xtensa-lx-rt/src/lib.rs index a5e4e0d..699e446 100644 --- a/xtensa-lx-rt/src/lib.rs +++ b/xtensa-lx-rt/src/lib.rs @@ -12,7 +12,10 @@ #![feature(asm_experimental_arch, naked_functions)] #![no_std] -use core::arch::asm; +use core::{ + arch::asm, + ptr::{addr_of, addr_of_mut}, +}; pub use macros::{entry, exception, interrupt, pre_init}; pub use r0::{init_data, zero_bss}; @@ -58,11 +61,11 @@ pub unsafe extern "C" fn Reset() -> ! { __pre_init(); if __zero_bss() { - r0::zero_bss(&mut _bss_start, &mut _bss_end); + r0::zero_bss(addr_of_mut!(_bss_start), addr_of_mut!(_bss_end)); } if __init_data() { - r0::init_data(&mut _data_start, &mut _data_end, &_sidata); + r0::init_data(addr_of_mut!(_data_start), addr_of_mut!(_data_end), &_sidata); } // Copy of data segment is done by bootloader @@ -72,7 +75,7 @@ pub unsafe extern "C" fn Reset() -> ! { reset_internal_timers(); // move vec table - set_vecbase(&_init_start as *const u32); + set_vecbase(addr_of!(_init_start) as *const u32); __post_init();