diff --git a/Makefile b/Makefile index d0579fcc0..23d8369e3 100644 --- a/Makefile +++ b/Makefile @@ -43,6 +43,8 @@ X_HEEP_CFG ?= configs/general.hjson PAD_CFG ?= pad_cfg.hjson EXT_PAD_CFG ?= +PAD_RING_TEMPLATE ?= hw/system/pad_ring.sv.tpl + # Compiler options are 'gcc' (default) and 'clang' COMPILER ?= gcc @@ -107,7 +109,7 @@ mcu-gen: $(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/memory_subsystem.sv.tpl $(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl $(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir tb/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv tb/tb_util.svh.tpl - $(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/pad_ring.sv.tpl + $(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv $(PAD_RING_TEMPLATE) $(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl $(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/x_heep_system.sv.tpl $(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu.h.tpl diff --git a/hw/fpga/pad_cell_bypass_input_xilinx.sv b/hw/fpga/pad_cell_bypass_input_xilinx.sv index 79477c3da..68fd15b5a 100644 --- a/hw/fpga/pad_cell_bypass_input_xilinx.sv +++ b/hw/fpga/pad_cell_bypass_input_xilinx.sv @@ -3,13 +3,22 @@ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 module pad_cell_bypass_input #( - parameter PADATTR = 16 + parameter PADATTR = 16, + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, + parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, + //do not touch these parameters + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout logic pad_io, - input logic [PADATTR-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o ); assign pad_out_o = pad_io; diff --git a/hw/fpga/pad_cell_bypass_output_xilinx.sv b/hw/fpga/pad_cell_bypass_output_xilinx.sv index ad4f97a93..19225e59d 100644 --- a/hw/fpga/pad_cell_bypass_output_xilinx.sv +++ b/hw/fpga/pad_cell_bypass_output_xilinx.sv @@ -3,13 +3,22 @@ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 module pad_cell_bypass_output #( - parameter PADATTR = 16 + parameter PADATTR = 16, + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, + parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, + //do not touch these parameters + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout logic pad_io, - input logic [PADATTR-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o ); assign pad_out_o = 1'b0; diff --git a/hw/fpga/pad_cell_inout_xilinx.sv b/hw/fpga/pad_cell_inout_xilinx.sv index 5c68364ba..01a1aec0f 100644 --- a/hw/fpga/pad_cell_inout_xilinx.sv +++ b/hw/fpga/pad_cell_inout_xilinx.sv @@ -4,13 +4,21 @@ module pad_cell_inout #( parameter PADATTR = 16, - parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, + parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, + //do not touch these parameters + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout logic pad_io, - input logic [PADATTR-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o ); IOBUF xilinx_iobuf_i ( diff --git a/hw/fpga/pad_cell_input_xilinx.sv b/hw/fpga/pad_cell_input_xilinx.sv index 470a651a7..885e066dd 100644 --- a/hw/fpga/pad_cell_input_xilinx.sv +++ b/hw/fpga/pad_cell_input_xilinx.sv @@ -4,13 +4,21 @@ module pad_cell_input #( parameter PADATTR = 16, - parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, + parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, + //do not touch these parameters + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout logic pad_io, - input logic [PADATTR-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o ); assign pad_out_o = pad_io; diff --git a/hw/fpga/pad_cell_output_xilinx.sv b/hw/fpga/pad_cell_output_xilinx.sv index 43592acd1..081a81ed7 100644 --- a/hw/fpga/pad_cell_output_xilinx.sv +++ b/hw/fpga/pad_cell_output_xilinx.sv @@ -4,13 +4,21 @@ module pad_cell_output #( parameter PADATTR = 16, - parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, + parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, + //do not touch these parameters + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout logic pad_io, - input logic [PADATTR-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o ); assign pad_out_o = 1'b0; diff --git a/hw/simulation/pad_cell_bypass_input.sv b/hw/simulation/pad_cell_bypass_input.sv index 6e4bfd92d..c6661b4cd 100644 --- a/hw/simulation/pad_cell_bypass_input.sv +++ b/hw/simulation/pad_cell_bypass_input.sv @@ -5,14 +5,23 @@ /* verilator lint_off UNUSED */ module pad_cell_bypass_input #( parameter PADATTR = 16, + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, + parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, //do not touch these parameters - parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout logic pad_io, - input logic [PADATTR_RND-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + /* verilator lint_off UNDRIVEN */ + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o + ); // when ported to another technology, they remain like this diff --git a/hw/simulation/pad_cell_bypass_output.sv b/hw/simulation/pad_cell_bypass_output.sv index f0f5ee8d0..df1c63bf2 100644 --- a/hw/simulation/pad_cell_bypass_output.sv +++ b/hw/simulation/pad_cell_bypass_output.sv @@ -5,14 +5,22 @@ /* verilator lint_off UNUSED */ module pad_cell_bypass_output #( parameter PADATTR = 16, + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, + parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, //do not touch these parameters - parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout logic pad_io, - input logic [PADATTR_RND-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + /* verilator lint_off UNDRIVEN */ + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o ); logic pad; diff --git a/hw/simulation/pad_cell_inout.sv b/hw/simulation/pad_cell_inout.sv index 3529b2570..001f9aa13 100644 --- a/hw/simulation/pad_cell_inout.sv +++ b/hw/simulation/pad_cell_inout.sv @@ -5,15 +5,22 @@ /* verilator lint_off UNUSED */ module pad_cell_inout #( parameter PADATTR = 16, + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, //do not touch these parameters - parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout wire pad_io, - input logic [PADATTR_RND-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + /* verilator lint_off UNDRIVEN */ + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o ); logic pad; diff --git a/hw/simulation/pad_cell_input.sv b/hw/simulation/pad_cell_input.sv index 5a7b053ad..d7e9e2b04 100644 --- a/hw/simulation/pad_cell_input.sv +++ b/hw/simulation/pad_cell_input.sv @@ -5,15 +5,22 @@ /* verilator lint_off UNUSED */ module pad_cell_input #( parameter PADATTR = 16, + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, //do not touch these parameters - parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout wire pad_io, - input logic [PADATTR_RND-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + /* verilator lint_off UNDRIVEN */ + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o ); logic pad; diff --git a/hw/simulation/pad_cell_output.sv b/hw/simulation/pad_cell_output.sv index 794e177d0..167000b74 100644 --- a/hw/simulation/pad_cell_output.sv +++ b/hw/simulation/pad_cell_output.sv @@ -5,15 +5,23 @@ /* verilator lint_off UNUSED */ module pad_cell_output #( parameter PADATTR = 16, + parameter EXTRA_INPUTS = 4, + parameter EXTRA_OUTPUTS = 4, parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP, //do not touch these parameters - parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR + parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR, + parameter EXTRA_INPUTS_RND = EXTRA_INPUTS == 0 ? 1 : EXTRA_INPUTS, + parameter EXTRA_OUTPUTS_RND = EXTRA_OUTPUTS == 0 ? 1 : EXTRA_OUTPUTS ) ( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, inout wire pad_io, - input logic [PADATTR_RND-1:0] pad_attributes_i + input logic [PADATTR_RND-1:0] pad_attributes_i, + input logic [EXTRA_INPUTS_RND-1:0] pad_extra_inputs_i, + /* verilator lint_off UNDRIVEN */ + output logic [EXTRA_OUTPUTS_RND-1:0] pad_extra_outputs_o + ); logic pad; diff --git a/hw/system/pad_ring.sv.tpl b/hw/system/pad_ring.sv.tpl index a10c0bb98..b4c86e183 100644 --- a/hw/system/pad_ring.sv.tpl +++ b/hw/system/pad_ring.sv.tpl @@ -14,11 +14,23 @@ ${external_pad.pad_ring_ctrl_interface} % endfor % if pads_attributes != None: - input logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][${pads_attributes['bits']}] pad_attributes_i + input logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][${pads_attributes['bits']}] pad_attributes_i, % else: // here just for simplicity /* verilator lint_off UNUSED */ - input logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][0:0] pad_attributes_i + input logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][0:0] pad_attributes_i, +% endif +% if pads_extra_inputs != None: + input logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][${pads_extra_inputs['bits']}] pad_extra_inputs_i, +% else: + /* verilator lint_off UNUSED */ + input logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][0:0] pad_extra_inputs_i, +% endif +% if pads_extra_outputs != None: + output logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][${pads_extra_outputs['bits']}] pad_extra_outputs_o +% else: + /* verilator lint_off UNDRIVEN */ + output logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][0:0] pad_extra_outputs_o % endif ); diff --git a/hw/system/x_heep_system.sv.tpl b/hw/system/x_heep_system.sv.tpl index d268d5e4c..1a2c7f1d6 100644 --- a/hw/system/x_heep_system.sv.tpl +++ b/hw/system/x_heep_system.sv.tpl @@ -94,6 +94,15 @@ ${pad.x_heep_system_interface} % if total_pad_muxed > 0: logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][${max_total_pad_mux_bitlengh-1}:0] pad_muxes; % endif +% if pads_attributes != None: + /* verilator lint_off UNUSED */ + logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][${pads_extra_inputs['bits']}] pad_extra_inputs; +% endif +% if pads_attributes != None: + /* verilator lint_off UNUSED */ + logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][${pads_extra_outputs['bits']}] pad_extra_outputs; +% endif + logic rst_ngen; @@ -165,9 +174,19 @@ ${pad.core_v_mini_mcu_bonding} ${pad.pad_ring_bonding_bonding} % endfor % if pads_attributes != None: - .pad_attributes_i(pad_attributes) + .pad_attributes_i(pad_attributes), +% else: + .pad_attributes_i('0), +% endif +% if pads_extra_inputs != None: + .pad_extra_inputs_i(pad_extra_inputs), +% else: + .pad_extra_inputs_i('0), +% endif +% if pads_extra_outputs != None: + .pad_extra_outputs_o(pad_extra_outputs) % else: - .pad_attributes_i('0) + .pad_extra_outputs_o() % endif ); diff --git a/pad_cfg.hjson b/pad_cfg.hjson index 1cfa8c798..77951f6c4 100644 --- a/pad_cfg.hjson +++ b/pad_cfg.hjson @@ -17,11 +17,17 @@ // skip_declaration: (optional) - skip the declaration of the pad in the top level (default False) // keep_internal: (optional) - keep the pad internal to the design (default False) // -// Add this field at the same level of pads (not inside) if you want to define PADs attributes +// Add these fields at the same level of pads (not inside) if you want to define PADs attributes, extra inputs, and extra outputs // attributes: { // bits: 7:0 // resval: 0x3 // }, +// extra_inputs: { +// bits: 5:0 +// }, +// extra_outputs: { +// bits: 2:0 +// }, { diff --git a/util/mcu_gen.py b/util/mcu_gen.py index c661d780d..7db4be1fc 100755 --- a/util/mcu_gen.py +++ b/util/mcu_gen.py @@ -42,7 +42,7 @@ def create_pad_ring(self): mapping = '' if self.pad_mapping is not None: - mapping = ', .SIDE(' + mapping_dict[self.pad_mapping] + ')' + mapping = ',\n.SIDE(' + mapping_dict[self.pad_mapping] + ')' self.interface = ' inout wire ' + self.name + '_io,\n' @@ -50,7 +50,11 @@ def create_pad_ring(self): self.pad_ring_io_interface = ' inout wire ' + self.io_interface + ',' self.pad_ring_ctrl_interface += ' output logic ' + self.signal_name + 'o,' self.pad_ring_instance = \ - 'pad_cell_input #(.PADATTR('+ str(self.attribute_bits) +')' + mapping + ') ' + self.cell_name + ' ( \n' + \ + 'pad_cell_input #(\n' + \ + '.PADATTR('+ str(self.attribute_bits) +'),\n' + \ + '.EXTRA_INPUTS('+ str(self.extra_inputs_bits) +'),\n' + \ + '.EXTRA_OUTPUTS('+ str(self.extra_outputs_bits) +')' + \ + mapping + ') ' + self.cell_name + '( \n' + \ ' .pad_in_i(1\'b0),\n' + \ ' .pad_oe_i(1\'b0),\n' + \ ' .pad_out_o(' + self.signal_name + 'o),\n' + \ @@ -59,7 +63,11 @@ def create_pad_ring(self): self.pad_ring_io_interface = ' inout wire ' + self.io_interface + ',' self.pad_ring_ctrl_interface += ' input logic ' + self.signal_name + 'i,' self.pad_ring_instance = \ - 'pad_cell_output #(.PADATTR('+ str(self.attribute_bits) +')' + mapping + ') ' + self.cell_name + ' ( \n' + \ + 'pad_cell_output #(\n' + \ + '.PADATTR('+ str(self.attribute_bits) +'),\n' + \ + '.EXTRA_INPUTS('+ str(self.extra_inputs_bits) +'),\n' + \ + '.EXTRA_OUTPUTS('+ str(self.extra_outputs_bits) +')' + \ + mapping + ') ' + self.cell_name + '( \n' + \ ' .pad_in_i(' + self.signal_name + 'i),\n' + \ ' .pad_oe_i(1\'b1),\n' + \ ' .pad_out_o(),\n' + \ @@ -70,21 +78,40 @@ def create_pad_ring(self): self.pad_ring_ctrl_interface += ' output logic ' + self.signal_name + 'o,\n' self.pad_ring_ctrl_interface += ' input logic ' + self.signal_name + 'oe_i,' self.pad_ring_instance = \ - 'pad_cell_inout #(.PADATTR('+ str(self.attribute_bits) +')' + mapping + ') ' + self.cell_name + ' ( \n' + \ + 'pad_cell_inout #(\n' + \ + '.PADATTR('+ str(self.attribute_bits) +'),\n' + \ + '.EXTRA_INPUTS('+ str(self.extra_inputs_bits) +'),\n' + \ + '.EXTRA_OUTPUTS('+ str(self.extra_outputs_bits) +')' + \ + mapping + ') ' + self.cell_name + '( \n' + \ ' .pad_in_i(' + self.signal_name + 'i),\n' + \ ' .pad_oe_i(' + self.signal_name + 'oe_i),\n' + \ ' .pad_out_o(' + self.signal_name + 'o),\n' + \ ' .pad_io(' + self.signal_name + 'io),\n' if self.pad_type == 'input' or self.pad_type == 'output' or self.pad_type == 'inout': + if self.has_attribute: self.pad_ring_instance += \ - ' .pad_attributes_i(pad_attributes_i[core_v_mini_mcu_pkg::' + self.localparam + '])\n' + \ - ');\n\n' + ' .pad_attributes_i(pad_attributes_i[core_v_mini_mcu_pkg::' + self.localparam + ']),\n' + else: + self.pad_ring_instance += \ + ' .pad_attributes_i(\'0),\n' + + if self.has_extra_inputs: + self.pad_ring_instance += \ + ' .pad_extra_inputs_i(pad_extra_inputs_i[core_v_mini_mcu_pkg::' + self.localparam + ']),\n' else: self.pad_ring_instance += \ - ' .pad_attributes_i(\'0)' + \ - ');\n\n' + ' .pad_extra_inputs_i(\'0),\n' + + if self.has_extra_outputs: + self.pad_ring_instance += \ + ' .pad_extra_outputs_o(pad_extra_outputs_o[core_v_mini_mcu_pkg::' + self.localparam + '])\n' + else: + self.pad_ring_instance += \ + ' .pad_extra_outputs_o()\n' + + self.pad_ring_instance += ');\n\n' def create_core_v_mini_mcu_ctrl(self): @@ -209,7 +236,8 @@ def create_pad_ring_bonding(self): self.pad_ring_bonding_bonding += ' .' + self.signal_name + 'oe_i(' + oe_internal_signals + '),' self.x_heep_system_interface += ' inout wire ' + self.signal_name + 'io,' - def __init__(self, name, cell_name, pad_type, pad_mapping, index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, has_attribute, attribute_bits): + def __init__(self, name, cell_name, pad_type, pad_mapping, index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, has_attribute, attribute_bits, \ + has_extra_inputs, extra_inputs_bits, has_extra_outputs, extra_outputs_bits): self.name = name self.cell_name = cell_name @@ -229,6 +257,12 @@ def __init__(self, name, cell_name, pad_type, pad_mapping, index, pad_active, pa self.has_attribute = has_attribute self.attribute_bits = int(attribute_bits.split(":")[0]) - int(attribute_bits.split(":")[1]) + 1 + self.has_extra_inputs = has_extra_inputs + self.extra_inputs_bits = int(extra_inputs_bits.split(":")[0]) - int(extra_inputs_bits.split(":")[1]) + 1 + + self.has_extra_outputs = has_extra_outputs + self.extra_outputs_bits = int(extra_outputs_bits.split(":")[0]) - int(extra_outputs_bits.split(":")[1]) + 1 + self.signal_name_drive = [] self.pad_type_drive = [] self.driven_manually = [] @@ -547,6 +581,20 @@ def len_extracted_peripherals(peripherals): pads_attributes = None pads_attributes_bits = "-1:0" + try: + pads_extra_inputs = obj_pad['extra_inputs'] + pads_extra_inputs_bits = pads_extra_inputs['bits'] + except KeyError: + pads_extra_inputs = None + pads_extra_inputs_bits = "-1:0" + + try: + pads_extra_outputs = obj_pad['extra_outputs'] + pads_extra_outputs_bits = pads_extra_outputs['bits'] + except KeyError: + pads_extra_outputs = None + pads_extra_outputs_bits = "-1:0" + # Read HJSON description of External Pads if args.external_pads != None: with args.external_pads as file_external_pads: @@ -646,13 +694,16 @@ def len_extracted_peripherals(peripherals): except KeyError: pad_skip_declaration_mux = False - p = Pad(pad_mux, '', pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits) + p = Pad(pad_mux, '', pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], \ + pads_attributes!=None, pads_attributes_bits, pads_extra_inputs != None, pads_extra_inputs_bits, pads_extra_outputs != None, pads_extra_outputs_bits) + pad_mux_list.append(p) if pad_num > 1: for p in range(pad_num): pad_cell_name = "pad_" + key + "_" + str(p+pad_offset) + "_i" - pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits) + pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, \ + pads_attributes!=None, pads_attributes_bits, pads_extra_inputs != None, pads_extra_inputs_bits, pads_extra_outputs != None, pads_extra_outputs_bits) if not pad_keep_internal: pad_obj.create_pad_ring() pad_obj.create_core_v_mini_mcu_ctrl() @@ -671,7 +722,9 @@ def len_extracted_peripherals(peripherals): else: pad_cell_name = "pad_" + key + "_i" - pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits) + pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, \ + pads_attributes!=None, pads_attributes_bits, pads_extra_inputs != None, pads_extra_inputs_bits, pads_extra_outputs != None, pads_extra_outputs_bits) + if not pad_keep_internal: pad_obj.create_pad_ring() pad_obj.create_core_v_mini_mcu_ctrl() @@ -757,13 +810,16 @@ def len_extracted_peripherals(peripherals): except KeyError: pad_skip_declaration_mux = False - p = Pad(pad_mux, '', external_pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits) + p = Pad(pad_mux, '', external_pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], \ + pads_attributes!=None, pads_attributes_bits, pads_extra_inputs != None, pads_extra_inputs_bits, pads_extra_outputs != None, pads_extra_outputs_bits) pad_mux_list.append(p) if pad_num > 1: for p in range(pad_num): pad_cell_name = "pad_" + key + "_" + str(p+pad_offset) + "_i" - pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits) + pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, \ + pads_attributes!=None, pads_attributes_bits, pads_extra_inputs != None, pads_extra_inputs_bits, pads_extra_outputs != None, pads_extra_outputs_bits) + pad_obj.create_pad_ring() pad_obj.create_pad_ring_bonding() pad_obj.create_internal_signals() @@ -779,7 +835,8 @@ def len_extracted_peripherals(peripherals): else: pad_cell_name = "pad_" + key + "_i" - pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits) + pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, \ + pads_attributes!=None, pads_attributes_bits, pads_extra_inputs != None, pads_extra_inputs_bits, pads_extra_outputs != None, pads_extra_outputs_bits) pad_obj.create_pad_ring() pad_obj.create_pad_ring_bonding() pad_obj.create_internal_signals() @@ -845,6 +902,8 @@ def len_extracted_peripherals(peripherals): "total_pad_muxed" : total_pad_muxed, "max_total_pad_mux_bitlengh" : max_total_pad_mux_bitlengh, "pads_attributes" : pads_attributes, + "pads_extra_inputs" : pads_extra_inputs, + "pads_extra_outputs" : pads_extra_outputs, } ###########