From a440e2e54f49c56dca332fe9c90c220077c7dd76 Mon Sep 17 00:00:00 2001 From: Leon Tomenendal Date: Fri, 1 Apr 2022 11:38:46 +0200 Subject: [PATCH 1/4] connect own module to riscv --- Makefile | 3 +- common/add_module.tcl | 72 +++++++++++++++++++++++++++++++++ common/common_addr_segments.tcl | 10 ++++- common/ip_repo_path.tcl | 1 + common/module_info.tcl | 29 +++++++++++++ common/parse_args.tcl | 3 +- riscv_pe_project.tcl | 14 +++++++ 7 files changed, 128 insertions(+), 4 deletions(-) create mode 100644 common/add_module.tcl create mode 100644 common/module_info.tcl diff --git a/Makefile b/Makefile index 1b5990b..5045e63 100644 --- a/Makefile +++ b/Makefile @@ -4,6 +4,7 @@ PYNQ=xc7z020clg400-1 XLEN?=32 CACHE?=false MAXI?=1 +ADD_MODULE?="false" ifndef TAPASCO_HOME $(error TAPASCO_HOME is not set, make sure to source setup.sh in TaPaSCo dir) @@ -26,7 +27,7 @@ list: @echo $(CORE_LIST) %_pe: %_setup - vivado -nolog -nojournal -mode batch -source riscv_pe_project.tcl -tclargs --part $(PYNQ) --bram $(BRAM_SIZE) --cache $(CACHE) --maxi $(MAXI) --project_name $@ + vivado -nolog -nojournal -mode batch -source riscv_pe_project.tcl -tclargs --part $(PYNQ) --bram $(BRAM_SIZE) --cache $(CACHE) --add_module $(ADD_MODULE) --maxi $(MAXI) --project_name $@ @PE_ID=$$(($$(echo $(PE_LIST) | sed s/$@.*// | wc -w) + 1742)); \ tapasco -v import IP/$@/esa.informatik.tu-darmstadt.de_tapasco_$@_1.0.zip as $$PE_ID --skipEvaluation diff --git a/common/add_module.tcl b/common/add_module.tcl new file mode 100644 index 0000000..782f3ab --- /dev/null +++ b/common/add_module.tcl @@ -0,0 +1,72 @@ +source common/module_info.tcl +# read component.xml +set component $moddir/component.xml +set rc [open $component r] +set fi [read $rc] +close $rc +set vendorList [lsearch -inline $fi "*spirit:vendor*"] +set libraryList [lsearch -inline $fi "*spirit:library*"] +set nameList [lsearch -inline $fi "*spirit:name*"] +set versionList [lsearch -inline $fi "*spirit:version*"] + +set List {$vendorList $libraryList $nameList $versionList} +set xL {vendor library name version} +set i 0 +foreach elem $List { +lassign [lindex [split [lindex [split [subst $elem] "<"] 1] ">"] 1] [lindex $xL $i] +incr i +} + +set rv_cell [get_bd_cells -filter "VLNV==$current_core"] +delete_bd_objs [get_bd_intf_nets axi_mem_intercon_1_M00_AXI] + +#create modules +set $name [ create_bd_cell -type ip -vlnv $vendor:$library:$name:$version $name ] +if {$project_name == "swerv_pe"} { + set project_obj swerv_0 +} +if {$project_name == "orca_pe"} { + set project_obj orca_0 +} +set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] +if {${if_type} == "AXI_APB"} { + set axi_apb_bridge_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_apb_bridge:3.0 axi_apb_bridge_0] + set_property -dict [list CONFIG.C_M_APB_PROTOCOL {apb4}] [get_bd_cells axi_apb_bridge_0] + set_property -dict [list CONFIG.C_APB_NUM_SLAVES {1}] [get_bd_cells axi_apb_bridge_0] +} +set_property -dict [list CONFIG.NUM_SI {2}] [get_bd_cells smartconnect_0] +set_property -dict [list CONFIG.NUM_MI {2}] [get_bd_cells axi_interconnect_0] + +#connect intf +connect_bd_intf_net [get_bd_intf_pins -filter {MODE==Master} -of [get_bd_cells $name]] [get_bd_intf_pins smartconnect_0/S00_AXI] +connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins dmaOffset/S_AXI] +if {${if_type} == "AXI_APB"} { + connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_apb_bridge_0/APB_M] [get_bd_intf_pins -filter {MODE==Slave} -of [get_bd_cells $name]] + connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins axi_apb_bridge_0/AXI4_LITE] +} +if {${if_type} == "AXI4_LITE"} { + connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins -filter {MODE==Slave} -of [get_bd_cells $name]] +} + +make_bd_intf_pins_external [get_bd_intf_pins axi_offset_0/M_AXI] +connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_mem_intercon_1/M00_AXI] [get_bd_intf_pins smartconnect_0/S01_AXI] + +#connect ports + +#CLK +connect_bd_net [get_bd_ports CLK] [get_bd_pins -filter {TYPE=="clk"} -of [get_bd_cells $name]] [get_bd_pins smartconnect_0/aclk] [get_bd_pins axi_interconnect_0/M01_ACLK] +if {${if_type} == "AXI_APB"} { + connect_bd_net [get_bd_ports CLK] [get_bd_pins axi_apb_bridge_0/s_axi_aclk] +} + +#RST +connect_bd_net [get_bd_pins rst_CLK_100M/peripheral_aresetn] [get_bd_pins -filter {TYPE=="rst"} -of [get_bd_cells $name]] [get_bd_pins axi_interconnect_0/M01_ARESETN] +if {${if_type} == "AXI_APB"} { + connect_bd_net [get_bd_pins rst_CLK_100M/peripheral_aresetn] [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] +} +connect_bd_net [get_bd_pins smartconnect_0/aresetn] [get_bd_pins rst_CLK_100M/interconnect_aresetn] + +#INTR +if {${module_has_intr} == "true"} { + connect_bd_net [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $name]] [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $project_obj]] +} diff --git a/common/common_addr_segments.tcl b/common/common_addr_segments.tcl index f82ff43..d75d48f 100644 --- a/common/common_addr_segments.tcl +++ b/common/common_addr_segments.tcl @@ -41,6 +41,12 @@ if {$maxi_ports == 2} { create_bd_addr_seg -range 0x00010000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_CTRL] [get_bd_addr_segs AXIGate_0/saxi/reg0] SEG_AXIGate_0_reg0 create_bd_addr_seg -range $lmem -offset $lmem [get_bd_addr_spaces S_AXI_BRAM] [get_bd_addr_segs ps_dmem_ctrl/S_AXI/Mem0] SEG_ps_dmem_ctrl_Mem0 create_bd_addr_seg -range $lmem -offset 0x00000000 [get_bd_addr_spaces S_AXI_BRAM] [get_bd_addr_segs ps_imem_ctrl/S_AXI/Mem0] SEG_ps_imem_ctrl_Mem0 - - create_specific_addr_segs + +if { ${add_module} eq "true" } { + assign_bd_address + set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]] + set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]] + set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]] + set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]] +} diff --git a/common/ip_repo_path.tcl b/common/ip_repo_path.tcl index 7f7a59d..8409265 100644 --- a/common/ip_repo_path.tcl +++ b/common/ip_repo_path.tcl @@ -4,4 +4,5 @@ set_property "ip_repo_paths" "\ [file normalize "$origin_dir/IP/axi_offset"] \ [file normalize "$origin_dir/IP/axi_ctrl"] \ [file normalize "$origin_dir/IP/riscv"] \ + [file normalize ${moddir}] \ " $obj diff --git a/common/module_info.tcl b/common/module_info.tcl new file mode 100644 index 0000000..53ebe0e --- /dev/null +++ b/common/module_info.tcl @@ -0,0 +1,29 @@ + +#THIS IS THE INFO FILE FOR THE MODULE YOU WANT TO ADD + + +#directory path to the module +set moddir "" + +#input interface information +#supported IF Types: "AXI_APB" "AXI4_LITE" +set if_type "" +set in_if_range "" +set in_if_offset "" + +#output interface information +set out_if_range "" +set out_if_offset "" + +#registers +#set if module has INTR to true/false +set module_has_intr "false" + + + + + + + + + diff --git a/common/parse_args.tcl b/common/parse_args.tcl index 5c8c9fe..dbd829b 100644 --- a/common/parse_args.tcl +++ b/common/parse_args.tcl @@ -34,7 +34,8 @@ if { $::argc > 0 } { "--part" { incr i; set part [lindex $::argv $i] } "--bram" { incr i; set lmem [lindex $::argv $i] } "--maxi" { incr i; set maxi_ports [lindex $::argv $i] } - "--cache" { incr i; set cache [lindex $::argv $i] } + "--cache" { incr i; set cache [lindex $::argv $i] } + "--add_module" { incr i; set add_module [lindex $::argv $i] } "--project_name" { incr i; set project_name [lindex $::argv $i] } "--help" { help } default { diff --git a/riscv_pe_project.tcl b/riscv_pe_project.tcl index 8e18120..66eebba 100644 --- a/riscv_pe_project.tcl +++ b/riscv_pe_project.tcl @@ -81,6 +81,13 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set IP repository paths set obj [get_filesets sources_1] +variable add_module +variable moddir +if { ${add_module} eq "true" } { + source common/module_info.tcl + } +puts $add_module +puts $moddir source common/ip_repo_path.tcl set ip_paths [get_property "ip_repo_paths" $obj] puts $ip_paths @@ -93,6 +100,8 @@ update_ip_catalog -rebuild proc cr_bd_riscv_pe { parentCell lmem } { variable project_name variable cache + variable add_module + variable moddir variable maxi_ports # CHANGE DESIGN NAME HERE set design_name ${project_name} @@ -144,6 +153,11 @@ proc cr_bd_riscv_pe { parentCell lmem } { source common/connect_common_ports.tcl + # Connect modules + + if { ${add_module} eq "true" } { + source common/add_module.tcl + } # Create address segments source common/common_addr_segments.tcl From a660b7f3dfa1b0f808b3e31defd4cb993daeac8d Mon Sep 17 00:00:00 2001 From: Leon Tomenendal Date: Fri, 1 Apr 2022 12:49:02 +0200 Subject: [PATCH 2/4] add orca support --- common/add_module.tcl | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/common/add_module.tcl b/common/add_module.tcl index 782f3ab..8a54e41 100644 --- a/common/add_module.tcl +++ b/common/add_module.tcl @@ -68,5 +68,14 @@ connect_bd_net [get_bd_pins smartconnect_0/aresetn] [get_bd_pins rst_CLK_100M/in #INTR if {${module_has_intr} == "true"} { - connect_bd_net [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $name]] [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $project_obj]] + if {$project_name == "swerv_pe"} { + connect_bd_net [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $name]] [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $project_obj]] + } + if {$project_name == "orca_pe"} { + startgroup + set_property -dict [list CONFIG.ENABLE_EXCEPTIONS {1} CONFIG.ENABLE_EXT_INTERRUPTS {1}] [get_bd_cells $project_obj] + endgroup + connect_bd_net [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $name]] [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $project_obj]] + } + } From ece6df82c238e5010602b166876773a204e98cb2 Mon Sep 17 00:00:00 2001 From: Leon Tomenendal Date: Fri, 1 Apr 2022 13:24:31 +0200 Subject: [PATCH 3/4] full range and offset function --- common/common_addr_segments.tcl | 13 +++++++++---- common/module_info.tcl | 4 +++- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/common/common_addr_segments.tcl b/common/common_addr_segments.tcl index d75d48f..6665412 100644 --- a/common/common_addr_segments.tcl +++ b/common/common_addr_segments.tcl @@ -45,8 +45,13 @@ create_specific_addr_segs if { ${add_module} eq "true" } { assign_bd_address - set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]] - set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]] - set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]] - set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]] + if { ${change_range_n_offset} eq "true" } { + set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]] + set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]] + set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]] + set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]] + set_property range ${out_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $name]] *dmaOffset*]] + set_property offset ${out_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $name]] *dmaOffset*]] + + } } diff --git a/common/module_info.tcl b/common/module_info.tcl index 53ebe0e..1de9689 100644 --- a/common/module_info.tcl +++ b/common/module_info.tcl @@ -6,6 +6,8 @@ set moddir "" #input interface information +#set if you need to change the ranges and offsets with true/false +set change_range_n_offset "false" #supported IF Types: "AXI_APB" "AXI4_LITE" set if_type "" set in_if_range "" @@ -16,7 +18,7 @@ set out_if_range "" set out_if_offset "" #registers -#set if module has INTR to true/false +#set if your module has an intr with true/false set module_has_intr "false" From b1575864ae238b01bbc3abef34794f4c5986f99b Mon Sep 17 00:00:00 2001 From: Leon Tomenendal Date: Sun, 3 Apr 2022 23:24:57 +0200 Subject: [PATCH 4/4] seperate Interface IN and OUT --- common/common_addr_segments.tcl | 4 +++- common/module_info.tcl | 6 +++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/common/common_addr_segments.tcl b/common/common_addr_segments.tcl index 6665412..397d0da 100644 --- a/common/common_addr_segments.tcl +++ b/common/common_addr_segments.tcl @@ -45,11 +45,13 @@ create_specific_addr_segs if { ${add_module} eq "true" } { assign_bd_address - if { ${change_range_n_offset} eq "true" } { + if { ${change_IN} eq "true" } { set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]] set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]] set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]] set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]] + } + if { ${change_OUT} eq "true" } { set_property range ${out_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $name]] *dmaOffset*]] set_property offset ${out_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $name]] *dmaOffset*]] diff --git a/common/module_info.tcl b/common/module_info.tcl index 1de9689..af3f249 100644 --- a/common/module_info.tcl +++ b/common/module_info.tcl @@ -6,19 +6,19 @@ set moddir "" #input interface information -#set if you need to change the ranges and offsets with true/false -set change_range_n_offset "false" #supported IF Types: "AXI_APB" "AXI4_LITE" +set change_IN "false" set if_type "" set in_if_range "" set in_if_offset "" #output interface information +set change_OUT "false" set out_if_range "" set out_if_offset "" #registers -#set if your module has an intr with true/false +#has your module an intr? true/false set module_has_intr "false"