diff --git a/Makefile b/Makefile index 1b5990b..ba23b99 100644 --- a/Makefile +++ b/Makefile @@ -49,3 +49,5 @@ clean: uninstall rm -rf riscv/cva5/{cva5,openhwgroup_risc-v_cva5.zip} rm -rf riscv/vexriscv/{SpinalHDL,VexRiscv} rm -rf riscv/cva6/cva6 + rm -rf riscv/taiga32_bsv/Taiga-bsv + rm -rf riscv/taiga64_bsv/Taiga-bsv diff --git a/common/cpu_vlnv.tcl b/common/cpu_vlnv.tcl index b6c027f..7b21955 100644 --- a/common/cpu_vlnv.tcl +++ b/common/cpu_vlnv.tcl @@ -12,4 +12,6 @@ set cpu_vlnv [list \ "cva6_pe" {openhwgroup:cva6:cva6:0.1} \ "swerv_eh2_pe" {wdc:swerv_eh2:swerv_eh2:1.4} \ "cva5_pe" {openhwgroup:cva5:cva5} \ + "taiga32_bsv_pe" {esa.informatik.tu-darmstadt.de:user:taiga32_bsv:1.0}\ + "taiga64_bsv_pe" {esa.informatik.tu-darmstadt.de:user:taiga64_bsv:1.0}\ ] diff --git a/riscv/taiga32_bsv/setup.sh b/riscv/taiga32_bsv/setup.sh new file mode 100755 index 0000000..5822297 --- /dev/null +++ b/riscv/taiga32_bsv/setup.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +mkdir -p IP/riscv +cd riscv/taiga32_bsv +git clone --recursive git@github.com:esa-tu-darmstadt/Taiga-bsv.git +cd Taiga-bsv +git apply ../taiga32_bsv_tapasco.patch +cd .. +cd Taiga-bsv/core && make clean && make SIM_TYPE=VERILOG ip +cp -r build/ip/* ../../../../IP/riscv +echo "Finished taiga32_bsv Setup!" diff --git a/riscv/taiga32_bsv/taiga32_bsv_tapasco.patch b/riscv/taiga32_bsv/taiga32_bsv_tapasco.patch new file mode 100644 index 0000000..599a7d8 --- /dev/null +++ b/riscv/taiga32_bsv/taiga32_bsv_tapasco.patch @@ -0,0 +1,13 @@ +diff --git a/core/Makefile b/core/Makefile +index 7553ef6..33431a2 100644 +--- a/core/Makefile ++++ b/core/Makefile +@@ -18,7 +18,7 @@ EXTRA_BSV_LIBS:= + EXTRA_LIBRARIES:= + RUN_FLAGS:= + +-PROJECT_NAME=Taiga ++PROJECT_NAME=taiga32_bsv + + ifeq ($(RUN_TEST),) + RUN_TEST=TestsMainTest diff --git a/riscv/taiga64_bsv/setup.sh b/riscv/taiga64_bsv/setup.sh new file mode 100755 index 0000000..024b86c --- /dev/null +++ b/riscv/taiga64_bsv/setup.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +mkdir -p IP/riscv +cd riscv/taiga64_bsv +git clone --recursive git@github.com:esa-tu-darmstadt/Taiga-bsv.git + +cd Taiga-bsv +git apply ../taiga64_bsv_tapasco.patch +cd .. + +cd Taiga-bsv/core && make clean && make SIM_TYPE=VERILOG ARCH=RV64 ip +cp -r build/ip/* ../../../../IP/riscv +echo "Finished taiga64_bsv Setup!" diff --git a/riscv/taiga64_bsv/taiga64_bsv_tapasco.patch b/riscv/taiga64_bsv/taiga64_bsv_tapasco.patch new file mode 100644 index 0000000..faefcdb --- /dev/null +++ b/riscv/taiga64_bsv/taiga64_bsv_tapasco.patch @@ -0,0 +1,13 @@ +diff --git a/core/Makefile b/core/Makefile +index 7553ef6..dca81a6 100644 +--- a/core/Makefile ++++ b/core/Makefile +@@ -18,7 +18,7 @@ EXTRA_BSV_LIBS:= + EXTRA_LIBRARIES:= + RUN_FLAGS:= + +-PROJECT_NAME=Taiga ++PROJECT_NAME=taiga64_bsv + + ifeq ($(RUN_TEST),) + RUN_TEST=TestsMainTest diff --git a/specific_tcl/taiga32_bsv_pe_project.tcl b/specific_tcl/taiga32_bsv_pe_project.tcl new file mode 100644 index 0000000..852ff55 --- /dev/null +++ b/specific_tcl/taiga32_bsv_pe_project.tcl @@ -0,0 +1,28 @@ +# Create instance: taiga_0, and set properties +set taiga_0 [ create_bd_cell -type ip -vlnv [dict get $cpu_vlnv $project_name] taiga_0 ] +set cpu_clk [get_bd_pins taiga_0/clk] + +# Create interface connections +set axi_io_port [get_bd_intf_pins taiga_0/m_axi] +set axi_mem_port [get_bd_intf_pins taiga_0/m_axi_cache] + +set ibram [get_bd_intf_pins taiga_0/instruction_bram] +set dbram [get_bd_intf_pins taiga_0/data_bram] + +# Create port connections +connect_bd_net [get_bd_pins RVController_0/rv_rstn] [get_bd_pins taiga_0/rstn] +connect_bd_net [get_bd_ports CLK] [get_bd_pins dmem/clka] +connect_bd_net [get_bd_pins dmem/rsta] [get_bd_pins RVController_0/rv_reset] +connect_bd_net [get_bd_ports CLK] [get_bd_pins imem/clka] +connect_bd_net [get_bd_pins imem/rsta] [get_bd_pins RVController_0/rv_reset] + +proc create_specific_addr_segs {} { + variable lmem + # Create specific address segments + create_bd_addr_seg -range 0x00010000 -offset 0x11000000 [get_bd_addr_spaces taiga_0/m_axi] [get_bd_addr_segs RVController_0/saxi/reg0] SEG_RVController_0_reg0 +} + +proc get_external_mem_addr_space {} { + return [get_bd_addr_spaces taiga_0/m_axi_cache] +} + diff --git a/specific_tcl/taiga64_bsv_pe_project.tcl b/specific_tcl/taiga64_bsv_pe_project.tcl new file mode 100644 index 0000000..6a7dd66 --- /dev/null +++ b/specific_tcl/taiga64_bsv_pe_project.tcl @@ -0,0 +1,38 @@ +# Create instance: taiga_0, and set properties +set taiga_0 [ create_bd_cell -type ip -vlnv [dict get $cpu_vlnv $project_name] taiga_0 ] +set cpu_clk [get_bd_pins taiga_0/clk] + +# Create interface connections +set axi_io_port [get_bd_intf_pins taiga_0/m_axi] +set axi_mem_port [get_bd_intf_pins taiga_0/m_axi_cache] + +set ibram [get_bd_intf_pins taiga_0/instruction_bram] +set dbram [get_bd_intf_pins taiga_0/data_bram] + +# Create port connections +connect_bd_net [get_bd_pins RVController_0/rv_rstn] [get_bd_pins taiga_0/rstn] +connect_bd_net [get_bd_ports CLK] [get_bd_pins dmem/clka] +connect_bd_net [get_bd_pins dmem/rsta] [get_bd_pins RVController_0/rv_reset] +connect_bd_net [get_bd_ports CLK] [get_bd_pins imem/clka] +connect_bd_net [get_bd_pins imem/rsta] [get_bd_pins RVController_0/rv_reset] + + +startgroup +set_property -dict [list CONFIG.Enable_32bit_Address {true} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {64} CONFIG.Write_Depth_A [expr $lmem / 8] CONFIG.Read_Width_A {64} CONFIG.Write_Width_B {64} CONFIG.Read_Width_B {64} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true} CONFIG.Use_RSTB_Pin {true} CONFIG.use_bram_block {Stand_Alone} CONFIG.EN_SAFETY_CKT {false}] [get_bd_cells dmem] +endgroup + +startgroup +set_property -dict [list CONFIG.Enable_32bit_Address {true} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {64} CONFIG.Write_Depth_A [expr $lmem / 8] CONFIG.Read_Width_A {64} CONFIG.Write_Width_B {64} CONFIG.Read_Width_B {64} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true} CONFIG.Use_RSTB_Pin {true} CONFIG.use_bram_block {Stand_Alone} CONFIG.EN_SAFETY_CKT {false}] [get_bd_cells imem] +endgroup + + +proc create_specific_addr_segs {} { + variable lmem + # Create specific address segments + create_bd_addr_seg -range 0x00010000 -offset 0x11000000 [get_bd_addr_spaces taiga_0/m_axi] [get_bd_addr_segs RVController_0/saxi/reg0] SEG_RVController_0_reg0 +} + +proc get_external_mem_addr_space {} { + return [get_bd_addr_spaces taiga_0/m_axi_cache] +} +