-
Notifications
You must be signed in to change notification settings - Fork 3
/
emu.py
2044 lines (1809 loc) · 64.8 KB
/
emu.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
import struct
import sys
import socket
import os
from subprocess import call
regs = [0]*17
stacksyms = {}
pc = 0
pd = 0
ram = "\x00"*(0x10000-1)
prevpc = 0
# Internal RAM 0x0000 - 0x3FFF
# Hardware Interrupts 0x0000 - 0x007F
# Software Interrupts 0x0080 - 0x00FF
# Primary Register Bank 0x0100 - 0x010F
# Swapped Register Bank 0x0120 - 0x013F
# HPI Interrupt and Mailbox 0x0140 - 0x0148
# LCP CMD Processor Variables 0x014A - 0x01FF
# USB Control Registers 0x0200 - 0x02FF
# Slave Setup Packet 0x0300 - 0x030F
# BIOS Stack 0x0310 - 0x03FF
# USB Slave and OTG Variables 0x0400 - 0x04A2
# User Code/Data Space (Internal RAM) 0x04A4 - 0x3FFF
regs[15] = 0x0400
jmpdests = {}
# we assume regbank is null
REGBANK = 0x0
updaterefs = False
BPs = set()
HBPw = set()
ADDR_LOG = set()
LOG = False
HBPr = set()
BUFFER_IN =""
BUFFER_OUT =""
SYMEXEC = False
SYMEXEC_LOG = {}
EXECUTED = set()
MARKS = {}
VM_IPS = {}
def rol(a,b) :
return ((a << (b%16)) | (a >> ((16 -b)%16))) & 0xFFFF
def ror(a,b) :
return ((a >> (b%16)) | (a << ((16 -b)%16))) & 0xFFFF
class Sym(object) :
def __init__(self, a, op = None, b = None) :
self.a = a
self.op = op
self.b = b
self.isCst = False
self.isVar = False
self.isSym = True
self.v = None
if not op :
if isinstance(a, int) or isinstance(a, long) :
self.isCst = True
self.v = a
elif isinstance(a, str) :
self.isVar = True
self.v = a
elif isinstance(a, Sym) :
self.isSym = True
self.a = a.a
self.op = a.op
self.b = a.b
self.v = a.v
else :
raise Exception("Invalid Argument")
return
if not b :
if a.isCst :
self.isCst = True
self.v = a
if op == "~" :
self.v = 0xFFFF ^ a.v
elif op == "-" :
self.v = 0xFFFF & (-a.v)
elif op == "cbw" :
if a & 0x80 :
self.v = 0xFF00 | a.v
else :
self.v = a.v
else :
raise Exception()
return
elif a.isSym and not a.b and a.op == op :
self.isCst = a.a.isCst
self.isVar = a.a.isVar
self.isSym = a.a.isSym
self.a = a.a.a
self.op = a.a.op
self.b = a.a.b
self.v = a.a.v
return
else :
return
if (not b.isCst) and a.isCst and (op in {"+","&","|","^"}) :
c = a
a = b
b = c
if b.isCst :
if a.isCst :
self.isCst = True
if op in ("rol","ror") :
self.v = eval("%s(%s,%s)"%(op, a.v, b.v))
return
self.v = eval(str(a.v)+op+str(b.v)) & 0xFFFF
return
elif a.isVar :
return
elif isinstance(a, Sym) :
if a.b.isCst :
if a.op in ("+","-") and op in ("+","-") :
nv = eval(a.op+str(a.b.v)+op+str(b.v))
if not nv :
self.a = a.a
self.op = a.op
self.b = a.b
self.isCst = a.isCst
self.isVar = a.isVar
self.isSym = a.isSym
return
self.a = a.a
self.op = (nv < 0) and "-" or "+"
self.b = Sym((nv < 0) and -nv or nv)
return
elif a.op in ("rol","ror") and op in ("rol","ror") :
if a.op != op :
rval = (a.b.v - b.v) % 16
else :
rval = (a.b.v + b.v) % 16
if not rval :
self.a = a.a
self.op = a.op
self.b = a.b
self.isCst = a.isCst
self.isVar = a.isVar
self.isSym = a.isSym
return
self.a = a.a
self.op = a.op
self.b = Sym(rval)
return
elif a.op == op :
if op in ("&","|","^") :
self.a = a.a
self.op = a.op
self.b = Sym(eval(str(a.b.v)+op+str(b.v)))
return
elif op in (">>", "<<") :
nv = eval(str(a.b.v)+"+"+str(b.v))
if not nv :
self.a = a.a
self.op = a.op
self.b = a.b
self.isCst = a.isCst
self.isVar = a.isVar
self.isSym = a.isSym
return
self.a = a.a
self.op = a.op
self.b = Sym(nv)
return
else :
raise Exception("Unknown op : %s"%op)
else :
raise Exception()
elif op in ("&","|") and str(a) == str(b) :
self.isCst = a.isCst
self.isVar = a.isVar
self.isSym = a.isSym
self.a = a.a
self.op = a.op
self.b = a.b
self.v = a.v
elif op == "^" and str(a) == str(b) :
self.isCst = True
self.isSym = False
self.a = 0
self.op = None
self.b = None
self.v = 0
def __str__(self) :
if self.isCst :
return "%04X"%self.v
elif self.isVar :
return self.v
elif self.isSym :
if self.b :
return "(%s %s %s)"%(self.a, self.op, self.b)
else :
return "%s(%s)"%(self.op, self.a)
raise Exception("Invalid Sym")
regssym = [Sym("R%02d"%i) for i in xrange(0x17)]
INTERRUPTIONS = {
48:"Reserved for LCP status message",
49:"Reserved for LCP asynchronous message",
50:"Reserved",
64 :"Two-wire serial EEPROM (from 256-byte to 2K-byte)",
65 :"Two-wire serial EEPROM from (4k-byte to 16k byte)",
66:"UART_INT",
67:"SCAN_INT",
68:"ALLOC_INT",
69:"Variable Data Pointer : start of free memory",
70:"IDLE_INT",
71:"IDLER_INT",
72:"INSERT_IDLE_INT",
73:"PUSHALL_INT",
74:"POPALL_INT",
75:"FREE_INT",
76:"REDO_ARENA",
77:"HW_SWAP_REG",
78:"HW_REST_REG",
79:"SCAN_DECODE_INT",
80:"SUSB1_SEND_INT",
81:"SUSB1_RECEIVE_INT",
82:"SUSB1_STALL_INT",
83:"SUSB1_STANDARD_INT",
84:"OTG_SRP_INT",
85:"SUSB1_VENDOR_INT (default=SUSB1_STALL_INT)",
86:"REMOTE_WAKEUP_INT",
87:"SUSB1_CLASS_INT (default=SUSB1_STALL_INT)",
88:"Variable Data pointer : OTG descriptor",
89:"SUSB1_FINISH_INT",
90:"Variable Data pointer : SUSB1 Device Descriptor.",
91:"Variable Data pointer : SUSB1Configuration Descriptor.",
92:"Variable Data pointer : SUSB1 String Descriptor.",
93 :"Reserved for future BIOS",
94:"SUSB1_LOADER_INT",
95:"SUSB1_DELTA_CONFIG_INT",
96:"SUSB2_SEND_INT",
97:"SUSB2_RECEIVE_INT",
98:"SUSB2_STALL_INT",
99:"SUSB2_STANDARD_INT",
100:"Reserved for future BIOS",
101:"SUSB2_VENDOR_INT (default: SUSB2_STALL_INT)",
102 :"Reserved for future BIOS",
103 :"SUSB2_CLASS_INT (default: SUSB2_STALL_INT)",
104 :"Reserved for future BIOS",
105:"SUSB2_FINISH_INT",
106:"Variable Data pointer : SUSB2 Device Descriptor.",
107:"Variable Data pointer : SUSB2Configuration Descriptor.",
108:"Variable Data pointer :SUSB2 String Descriptor.",
109:"Reserved for future BIOS",
110:"SUSB2_LOADER_INT",
111:"SUSB2_DELTA_CONFIG_INT",
112:"Reserved for future BIOS on OTG_STATE_INT",
113:"SUSB_INIT_NT",
114:"HUSB_SIE1_INIT_INT",
115:"HUSB_SIE2_INIT_INT",
116:"HUSB_RESET",
117:"KBHIT_INT"
}
class Flags(object) :
FLAGS = {"Z":0,"C":1,"O":2,"S":3,"I":4,"U":5}
SYMS = {"Z":Sym("Unknown"),"C":Sym("Unknown"),"O":Sym("Unknown"),"S":Sym("Unknown"),"I":Sym("Unknown")}
def __init__(self) :
pass
def __setitem__(self, item, val) :
assert item in Flags.FLAGS
assert val == 0 or val == 1
f = getw(0xc000)
if f & 0x10 :
global pc
print "%04X I SET"%pc
f = (f & (~(1 << Flags.FLAGS[item]))) | (val << Flags.FLAGS[item])
setw(0xc000, f)
def __getitem__(self, item) :
assert item in Flags.FLAGS
if getw(0xc000) & 0x10 :
global pc
print "%04X I SET"%pc
return (getw(0xc000) >> Flags.FLAGS[item]) & 1
def setsym(self, item, sym) :
assert item in Flags.FLAGS
Flags.SYMS[item] = sym
def getsym(self, item) :
assert item in Flags.FLAGS
return Flags.SYMS[item]
def update(self, dic) :
for i, j in dic.items() :
self[i] = j
flags = Flags()
class Operand(object) :
def __init__(self, operand, n = 0) :
global ram, pd, pc, DEBUG
self.read = False
self.size = 0
self.regnum = 0
self.wide = None
self.flags = {}
if operand == "tmp" :
self.type = "reg"
self.regnum = 16
return
if operand == "vector" :
self.type = "direct"
self.regnum = n*2
return
if operand == "reg" :
self.type = "reg"
self.regnum = n
return
if operand == "imm" :
self.type = "imm"
self.val = n
return
if operand >> 4 == 0 :
self.type = "reg"
self.regnum = operand & 0xF
return
elif operand == 0x1F :
self.type = "imm"
self.val = getw(pd)
self.size = 2
pd += 2
return
self.wide = ((operand >> 3) & 1) and 1 or 2
if operand & 0x37 == 0x27 :
self.type = "direct"
self.addr = getw(pd)
self.size = 2
pd += 2
return
self.regnum = (operand & 0x7) | 0x8
if self.regnum == 15 and self.wide == 1 :
raise Exception("%04X : Byte-wide accesses are prohibited in indirect mode when R15 is used"%(pc))
if operand >> 4 == 1 :
self.type = "indirect"
return
elif operand >> 4 == 2 :
self.type = "indAI"
if self.regnum == 15 :
raise Exception("Instruction encoding change")
return
elif operand >> 4 == 3 :
self.type = "indInd"
self.index = getw(pd)
self.size = 2
pd += 2
return
raise Exception("Invalid Operand")
def update(self) :
global regssym
if self.type == "indirect" and self.regnum == 15 :
assert self.wide == 2
if self.read :
regs[self.regnum] += 2
else :
regs[self.regnum] -= 2
elif self.type == "indAI" :
regs[self.regnum] += self.wide
def symupdate(self) :
global regssym
if self.type == "indirect" and self.regnum == 15 :
assert self.wide == 2
if self.read :
regssym[self.regnum] = Sym(regssym[self.regnum],"+", Sym(2))
else :
regssym[self.regnum] = Sym(regssym[self.regnum],"-", Sym(2))
elif self.type == "indAI" :
regssym[self.regnum] = Sym(regssym[self.regnum],"-", Sym(2))
@property
def v(self):
global ram, HBPr, DEBUG, LOG, ADDR_LOG
self.read = True
if self.type == "reg" :
val = regs[self.regnum]
elif self.type == "imm" :
val = self.val
else :
if self.type == "direct" :
addr = self.addr
elif self.type == "indirect" :
addr = regs[self.regnum]
elif self.type == "indAI" :
addr = regs[self.regnum]
elif self.type == "indInd" :
addr = regs[self.regnum]
addr += self.index
else :
raise Exception("Invalid Operand")
if addr in HBPr :
print "HBP Break on Read : %04X"%addr
DEBUG = True
if LOG and self.regnum != 15 :
ADDR_LOG.add("r %s %04X"%(self.wide == 1 and "b" or "w", addr))
val = getw(addr)
if self.wide == 1 :
return val & 0xFF
return val
@v.setter
def v(self, value):
global ram, HBPw, DEBUG, LOG, ADDR_LOG
self.read = False
self.flags["C"] = (value & 0x10000) and 1 or 0
self.flags["S"] = (value & 0x8000) and 1 or 0
value &= 0xFFFF
self.flags["Z"] = (value == 0) and 1 or 0
if self.type == "reg" :
regs[self.regnum] = value
return
elif self.type == "imm" :
raise Exception("you cannot set an immediate !")
if self.type == "direct" :
addr = self.addr
elif self.type == "indirect" :
if self.regnum == 15 :
assert self.wide == 2
addr = regs[self.regnum] - 2
else :
addr = regs[self.regnum]
elif self.type == "indAI" :
addr = regs[self.regnum]
elif self.type == "indInd" :
addr = regs[self.regnum]
addr += self.index
self.addr = addr
if LOG and self.regnum != 15 :
ADDR_LOG.add("w %s %04X"%(self.wide == 1 and "b" or "w", addr))
if self.wide == 1 :
if addr in HBPw :
print "HBP Break on Write : %04X %02X -> %02X"%(addr, getb(addr), value)
DEBUG = True
return setb(addr, value&0xFF)
elif self.wide == 2 :
if addr in HBPw :
print "HBP Break on Write : %04X %04X -> %04X"%(addr, getw(addr), value)
DEBUG = True
if addr+1 in HBPw :
print "HBP Break on Write : %04X %04X -> %04X"%(addr+1, getb(addr+1), value >> 8)
DEBUG = True
return setw(addr, value)
raise Exception("Invalid Operand")
@property
def signed(self) :
return (self.v & 0x8000) != 0
@property
def sym(self) :
global regssym, regs
if self.type == "reg" :
return regssym[self.regnum]
elif self.type == "imm" :
return Sym(self.val)
elif self.type == "direct" :
return Sym("%s[%X]"%(self.wide == 1 and "b" or "w", self.addr))
elif self.type == "indirect" or self.type == "indAI" :
return Sym("%s[%s]"%(self.wide == 1 and "b" or "w", regssym[self.regnum]))
elif self.type == "indInd" :
return Sym("%s[%s+%X]"%(self.wide == 1 and "b" or "w", regssym[self.regnum], self.index))
@sym.setter
def sym(self, sym) :
global regssym, SYMEXEC, regs, prevpc
if self.type == "reg" :
regssym[self.regnum] = sym
return
elif self.type == "imm" :
return
if SYMEXEC :
if self.type == "indInd" and self.regnum == 15 :
stacksyms[self.addr] = sym
return
SYMEXEC_LOG[prevpc] = "%s[%X] = %s"%(self.wide == 1 and "b" or "w", self.addr, sym)
print CFG.addLabels("%04X : "%prevpc + SYMEXEC_LOG[prevpc])
def __str__(self) :
if self.type == "reg" :
return "R%02d"%self.regnum
elif self.type == "imm" :
return "%X"%self.val
if self.type == "direct" :
return "%s[%04X]"%(self.wide == 1 and "b" or "w", self.addr)
if self.type == "indirect" :
return "%s[R%02d]"%(self.wide == 1 and "b" or "w", self.regnum)
if self.type == "indAI" :
return "%s[R%02d++]"%(self.wide == 1 and "b" or "w", self.regnum)
if self.type == "indInd" :
return "%s[R%02d+%X]"%(self.wide == 1 and "b" or "w", self.regnum, self.index)
INSTRUCTIONS = {}
class Instruction :
def __init__(self, name, *operands) :
global pd, updaterefs
self.isRet = False
self.isRcc = False
self.isJmp = False
self.isJcc = False
self.isCst = False
self.isCall = False
self.name = name
self.operands = operands
if len(operands) == 2 :
self.src = operands[0]
self.dst = operands[1]
elif len(operands) == 1 :
self.dst = operands[0]
self.wide = 2
for op in operands :
if op.wide :
self.wide = op.wide
break
self.size = 2
for op in operands :
self.size += op.size
if not all(op.wide == self.wide for op in operands if op.wide) :
raise Exception()
self.addr = pd - self.size
for op in operands :
op.wide = self.wide
if isinstance(self, Jcc) or isinstance(self, JccL) :
if self.dst.type == "imm" and updaterefs :
jmpdests[self.dst.val] = jmpdests.get(self.dst.val, []) + ["%04X"%self.addr]
def __str__(self) :
global jmpdests
if isinstance(self, Jcc) or isinstance(self, JccL) :
if self.addr in jmpdests :
dasm = " << %2d >> %04X : "%(len(jmpdests[self.addr]), self.addr)
else :
dasm = " << %04X : "%self.addr
elif isinstance(self, Call) :
dasm = " -> %04X : "%self.addr
elif isinstance(self, Ret) :
dasm = " <- %04X : "%self.addr
elif self.addr in jmpdests :
dasm = " %2d >> %04X : "%(len(jmpdests[self.addr]), self.addr)
else :
dasm = " %04X : "%self.addr
dasm = CFG.addLabels(dasm)
for i in xrange(self.addr, self.addr+self.size, 2) :
dasm += "%04X "%getw(i)
dasm += " "*(36-len(dasm))
reprs = []
for op in self.operands[::-1] :
reprs.append(str(op))
dasm = (self.addr in EXECUTED and "*" or " ") + dasm + CFG.addLabels("%-5s"%self.name + ", ".join(str(op) for op in reprs))
return dasm + " "*(66-len(dasm)) + "| "+ SYMEXEC_LOG.get(self.addr, "")
def lightDisas(self) :
return self.name + " "*(5 - len(self.name)) + ", ".join("%10s"%op for op in self.operands[::-1])
def emu(self) :
self._emu()
for op in self.operands :
op.update()
def symexec(self) :
self._symexec()
for op in self.operands :
op.symupdate()
class Mov(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "mov", src, dest)
def _emu(self) :
global pc
self.dst.v = self.src.v
pc += self.size
def _symexec(self) :
self.dst.sym = self.src.sym
INSTRUCTIONS[0] = Mov
# macro instruction
class Push(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "push", src)
self.src = src
self.dst = dest
def _emu(self) :
global pc
self.dst.v = self.src.v
self.dst.update()
pc += self.size
def _symexec(self) :
global stacksyms, regs
stacksyms[regs[15]] = self.src.sym
# macro instruction
class Pop(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "pop", dest)
self.src = src
self.dst = dest
def _emu(self) :
global pc
self.dst.v = self.src.v
self.src.update()
pc += self.size
def _symexec(self) :
global stacksyms, regs
if regs[15] - 2 in stacksyms :
self.dst.sym = stacksyms.pop(regs[15] - 2)
else :
self.dst.sym = Sym("Unknown")
class Add(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "add", src, dest)
def _emu(self) :
global pc, flags
if self.dst.signed and self.src.signed :
signed = 1
elif (not self.dst.signed) and (not self.src.signed) :
signed = 0
else :
signed = None
self.dst.v += self.src.v
if self.wide == 2 :
flags.update(self.dst.flags)
if signed is not None :
flags["O"] = flags["S"] ^ signed
pc += self.size
def _symexec(self) :
ss, sd = self.src.sym, self.dst.sym
self.dst.sym = Sym(sd, "+", ss)
INSTRUCTIONS[1] = Add
class Addc(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "addc", src, dest)
def _emu(self) :
global pc, flags
if self.dst.signed and self.src.signed :
signed = 1
elif (not self.dst.signed) and (not self.src.signed) :
signed = 0
else :
signed = None
self.dst.v += self.src.v + flags["C"]
if self.wide == 2 :
flags.update(self.dst.flags)
if signed is not None :
flags["O"] = flags["S"] ^ signed
pc += self.size
def _symexec(self) :
ss, sd = self.src.sym, self.dst.sym
self.dst.sym = Sym(Sym(sd, "+", ss), "CF")
INSTRUCTIONS[2] = Addc
class Sub(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "sub", src, dest)
def _emu(self) :
global pc, flags
if self.dst.signed and (not self.src.signed) :
signed = 1
elif (not self.dst.signed) and self.src.signed :
signed = 0
else :
signed = None
self.dst.v = self.dst.v + ((-self.src.v) & 0xFFFF)
if self.wide == 2 :
flags.update(self.dst.flags)
if signed is not None :
flags["O"] = flags["S"] ^ signed
pc += self.size
def _symexec(self) :
ss, sd = self.src.sym, self.dst.sym
self.dst.sym = Sym(sd, "-", ss)
INSTRUCTIONS[3] = Sub
class Subb(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "subb", src, dest)
def _emu(self) :
global pc, flags
if self.dst.signed and (not self.src.signed) :
signed = 1
elif (not self.dst.signed) and self.src.signed :
signed = 0
else :
signed = None
self.dst.v = self.dst.v + ((-self.src.v - flags["C"]) & 0xFFFF)
if self.wide == 2 :
flags.update(self.dst.flags)
if signed is not None :
flags["O"] = flags["S"] ^ signed
pc += self.size
def _symexec(self) :
ss, sd = self.src.sym, self.dst.sym
self.dst.sym = Sym(Sym(sd, "-", ss), "CF")
INSTRUCTIONS[4] = Subb
class Cmp(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "cmp", src, dest)
def _emu(self) :
global pc, flags
if self.dst.signed and (not self.src.signed) :
signed = 1
elif (not self.dst.signed) and self.src.signed :
signed = 0
else :
signed = None
tmp = Operand("tmp")
tmp.v = self.dst.v - self.src.v
if self.wide == 2 :
flags.update(tmp.flags)
if signed is not None :
flags["O"] = flags["S"] ^ signed
pc += self.size
def _symexec(self) :
global SYMEXEC_LOG
SYMEXEC_LOG[prevpc] = "%s CMP %s"%(self.dst.sym, self.src.sym)
INSTRUCTIONS[5] = Cmp
class And(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "and", src, dest)
def _emu(self) :
global pc, flags
self.dst.v &= self.src.v
if self.wide == 2 :
flags["Z"] = self.dst.flags["Z"]
flags["S"] = self.dst.flags["S"]
pc += self.size
def _symexec(self) :
ss, sd = self.src.sym, self.dst.sym
self.dst.sym = Sym(sd, "&", ss)
INSTRUCTIONS[6] = And
class Test(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "test", src, dest)
def _emu(self) :
global pc, flags
tmp = Operand("tmp")
tmp.v = self.dst.v & self.src.v
if self.wide == 2 :
flags["Z"] = self.dst.flags["Z"]
flags["S"] = self.dst.flags["S"]
pc += self.size
def _symexec(self) :
pass
INSTRUCTIONS[7] = Test
class Or(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "or", src, dest)
def _emu(self) :
global pc, flags
self.dst.v |= self.src.v
if self.wide == 2 :
flags["Z"] = self.dst.flags["Z"]
flags["S"] = self.dst.flags["S"]
pc += self.size
def _symexec(self) :
ss, sd = self.src.sym, self.dst.sym
self.dst.sym = Sym(sd, "|", ss)
INSTRUCTIONS[8] = Or
class Xor(Instruction) :
def __init__(self, src, dest) :
Instruction.__init__(self, "xor", src, dest)
def _emu(self) :
global pc, flags
self.dst.v ^= self.src.v
if self.wide == 2 :
flags["Z"] = self.dst.flags["Z"]
flags["S"] = self.dst.flags["S"]
pc += self.size
def _symexec(self) :
ss, sd = self.src.sym, self.dst.sym
self.dst.sym = Sym(sd, "^", ss)
INSTRUCTIONS[9] = Xor
BRANCH = 0xC
CONDITIONS = {
0 : ("z", lambda flags : flags["Z"]),
1 : ("nz", lambda flags : 1^flags["Z"]),
2 : ("b", lambda flags : flags["C"]),
3 : ("ae", lambda flags : 1^flags["C"]),
4 : ("s", lambda flags : flags["S"]),
5 : ("ns", lambda flags : 1^flags["S"]),
6 : ("o", lambda flags : flags["O"]),
7 : ("no", lambda flags : 1^flags["O"]),
8 : ("a", lambda flags : (1^flags["Z"]) & (1^flags["C"])),
9 : ("be", lambda flags : (flags["Z"]) | (flags["C"])),
10: ("g", lambda flags : (flags["O"] == flags["S"]) and (1^flags["Z"]) or 0),
11: ("ge", lambda flags : (flags["O"] == flags["S"]) and 1 or 0),
12: ("l", lambda flags : (flags["O"] != flags["S"]) and 1 or 0),
13: ("le", lambda flags : (flags["O"] != flags["S"]) and 1 or flags["Z"]),
15: ("", lambda flags : 1)
}
class Jcc(Instruction) :
def __init__(self, condition, offset) :
self.cc, self.taken = CONDITIONS[condition]
if not self.cc :
self.cc = "mp"
if offset & 0x40 :
self.offset = -(-offset & 0x7F)
else :
self.offset = offset
Instruction.__init__(self, "j%-2s"%self.cc, Operand("imm", pd + self.offset * 2))
if self.cc == "mp" :
self.isJmp = True
else :
self.isJcc = True
self.isCst = True
def _emu(self) :
global pc, flags
if self.taken(flags) :
pc = self.dst.v
else :
pc += self.size
def _symexec(self) :
global flags
# if self.cc != "mp" :
# if self.taken(flags) :
# print "%04X : j%s to %s"%(pc, self.cc, self.dst)
# else :
# print "%04X : do not j%s to %s"%(pc, self.cc, self.dst)
# else :
# print "%04X : jump to %s"%(pc, self.dst)
class JccL(Instruction) :
def __init__(self, condition, dest) :
self.cc, self.taken = CONDITIONS[condition]
if not self.cc :
self.cc = "mp"
elif dest.type == "indAI" :
raise Exception()
Instruction.__init__(self, "j%-2s"%self.cc, dest)
if self.cc == "mp" :
self.isJmp = True
else :
self.isJcc = True
self.isCst = self.dst.type == "imm"
def _emu(self) :
global pc, flags
if self.taken(flags) :
pc = self.dst.v
else :
pc += self.size
def _symexec(self) :
global flags
# if self.cc != "mp" :
# if self.taken(flags) :
# print "%04X : j%s to %s"%(pc, self.cc, self.dst)
# else :
# print "%04X : do not j%s to %s"%(pc, self.cc, self.dst)
# else :
# print "%04X : jump to %s"%(pc, self.dst)
class Ret(Instruction) :
def __init__(self, condition) :
self.cc, self.taken = CONDITIONS[condition]
if not self.cc :
self.cc = "et"
else :
raise Exception()
Instruction.__init__(self, "r%-2s"%self.cc)
if self.cc == "et" :
self.isRet = True
else :
self.isRcc = True
def _emu(self) :
global pc, flags, regs
if self.taken(flags) :
pc = getw(regs[15])
regs[15] += 2
else :
pc += self.size
def _symexec(self) :
global flags
# if self.cc != "et" :
# if self.taken(flags) :
# print "%04X : r%s to %s"%(pc, self.cc, getw(regs[15]-2))
# else :
# print "%04X : do not r%s to %s"%(pc, self.cc, getw(regs[15]-2))
# else :
# print "%04X : return to %s"%(pc, getw(regs[15]-2))
CALL = 0xA
class Call(Instruction) :
def __init__(self, condition, dest) :
self.cc, self.taken = CONDITIONS[condition]
if not self.cc :
self.cc = "all"
elif dest.type == "indAI" :
raise Exception()
Instruction.__init__(self, "c%-3s"%self.cc, dest)
self.isCall = True
self.isCst = self.dst.type == "imm"
def _emu(self) :
global pc, flags, regs
if self.taken(flags) :
regs[15] -= 2
setw(regs[15], pc + self.size)
pc = self.dst.v
else :
pc += self.size
def _symexec(self) :
global flags
# if self.cc != "all" :
# if self.taken(flags) :
# print "%04X : c%s %s"%(pc, self.cc, self.dst)
# else :
# print "%04X : do not c%s %s"%(pc, self.cc, self.dst)
# else :
# print "%04X : call %s"%(pc, self.dst)
class Int(Instruction) :