From a325a5ff7d3f2ee191dd3d605db6340df7d6ba44 Mon Sep 17 00:00:00 2001 From: Christoph Berganski Date: Fri, 14 Jun 2024 12:27:14 +0200 Subject: [PATCH 1/3] [StreamingDataWidthConverter_hls] Remove duplicate intermediate stream --- .../fpgadataflow/hls/streamingdatawidthconverter_hls.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py index d1f58d3e87..67d2f8b6d0 100644 --- a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py @@ -95,9 +95,6 @@ def docompute(self): op = "StreamingDataWidthConverter_Batch" if self.needs_lcm(): self.code_gen_dict["$DOCOMPUTE$"] = [ - 'hls::stream> intermediate ("intermediate");'.format( - self.get_iowidth_lcm() - ), "%s(in0_%s, intermediate, numReps);" % (op, self.hls_sname()), "%s(intermediate, out_%s, numReps);" From 7b80e1abf3613323d6601fc6883990f7de064952 Mon Sep 17 00:00:00 2001 From: Christoph Berganski Date: Fri, 14 Jun 2024 12:49:06 +0200 Subject: [PATCH 2/3] [StreamingDataWidthConverter_hls] Remove the other duplicate stream --- .../fpgadataflow/hls/streamingdatawidthconverter_hls.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py index 67d2f8b6d0..4619a1756b 100644 --- a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py @@ -78,12 +78,6 @@ def strm_decl(self): self.get_instream_width(), self.hls_sname(), self.hls_sname() ) ) - if self.needs_lcm(): - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> intermediate ("intermediate");'.format( - self.get_iowidth_lcm() - ) - ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( 'hls::stream> out_{} ("out_{}");'.format( self.get_outstream_width(), self.hls_sname(), self.hls_sname() @@ -95,6 +89,9 @@ def docompute(self): op = "StreamingDataWidthConverter_Batch" if self.needs_lcm(): self.code_gen_dict["$DOCOMPUTE$"] = [ + 'hls::stream> intermediate ("intermediate");'.format( + self.get_iowidth_lcm() + ), "%s(in0_%s, intermediate, numReps);" % (op, self.hls_sname()), "%s(intermediate, out_%s, numReps);" From 961e48ba6cb15e00928089a78077737f120a4a32 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 19 Jun 2024 11:55:47 +0100 Subject: [PATCH 3/3] [Tests] Update dwc testing to test rtl and hls variant --- tests/fpgadataflow/test_fpgadataflow_dwc.py | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py index 1454433d87..6b79a39ed5 100644 --- a/tests/fpgadataflow/test_fpgadataflow_dwc.py +++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py @@ -47,7 +47,7 @@ from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype): +def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style): inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, shape) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, shape) @@ -63,6 +63,7 @@ def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype): inWidth=inWidth, outWidth=outWidth, dataType=str(finn_dtype.name), + preferred_impl_style=impl_style, ) graph = helper.make_graph(nodes=[DWC_node], name="dwc_graph", inputs=[inp], outputs=[outp]) @@ -86,17 +87,17 @@ def prepare_inputs(input_tensor, dt): ([1, 24], 6, 4, DataType["INT2"]), ([1, 24], 4, 6, DataType["INT2"]), ([1, 4], 2, 4, DataType["BIPOLAR"]), - ([1, 2, 8], 2, 4, DataType["BIPOLAR"]), ([1, 4], 4, 2, DataType["INT2"]), ([1, 2, 8], 4, 4, DataType["INT2"]), ([1, 2, 8], 8, 16, DataType["INT2"]), ], ) @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) +@pytest.mark.parametrize("impl_style", ["hls", "rtl"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_dwc(config, exec_mode): +def test_fpgadataflow_dwc(config, exec_mode, impl_style): shape, inWidth, outWidth, finn_dtype = config test_fpga_part = "xc7z020clg400-1" @@ -104,7 +105,7 @@ def test_fpgadataflow_dwc(config, exec_mode): x = gen_finn_dt_tensor(finn_dtype, shape) input_dict = prepare_inputs(x, finn_dtype) - model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype) + model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style) # verify abstraction level execution y = oxe.execute_onnx(model, input_dict)["outp"] assert ( @@ -136,19 +137,17 @@ def test_fpgadataflow_dwc(config, exec_mode): @pytest.mark.parametrize( "config", [ - ([1, 24], 6, 4, DataType["INT2"]), - ([1, 24], 4, 6, DataType["INT2"]), ([1, 4], 2, 4, DataType["BIPOLAR"]), - ([1, 2, 8], 2, 4, DataType["BIPOLAR"]), ([1, 4], 4, 2, DataType["INT2"]), ([1, 2, 8], 4, 4, DataType["INT2"]), ([1, 2, 8], 8, 16, DataType["INT2"]), ], ) +@pytest.mark.parametrize("impl_style", ["hls", "rtl"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_dwc_stitched_rtlsim(config): +def test_fpgadataflow_dwc_stitched_rtlsim(config, impl_style): shape, inWidth, outWidth, finn_dtype = config test_fpga_part = "xc7z020clg400-1" @@ -157,7 +156,7 @@ def test_fpgadataflow_dwc_stitched_rtlsim(config): x = gen_finn_dt_tensor(finn_dtype, shape) input_dict = prepare_inputs(x, finn_dtype) - model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype) + model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style) model = model.transform(SpecializeLayers(test_fpga_part)) model = model.transform(InsertFIFO(create_shallow_fifos=True)) model = model.transform(SpecializeLayers(test_fpga_part))