From ec93c72d18736243a111f9f1bafdfec1de2f539e Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Wed, 8 Dec 2021 12:16:19 -0500
Subject: [PATCH] Modified simple_por.v RTL to avoid the wire declaration that
 "cvc" doesn't like (even though it's perfectly legal).

---
 verilog/rtl/simple_por.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 0129f4c7..d5a8a9d3 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -28,7 +28,7 @@ module simple_por(
     output por_l
 );
 
-    wire mid, porb_h;
+    wire mid;
     reg inode;
 
     // This is a behavioral model!  Actual circuit is a resitor dumping