From 06376a9e4cddb4e2f9eb872ceab695e9f3ed2c34 Mon Sep 17 00:00:00 2001
From: NouranAbdelaziz <nouran.abdelaziz@aucegypt.edu>
Date: Tue, 17 Sep 2024 10:02:11 +0300
Subject: [PATCH] include clock gate sky 130 cell inside ifdef block for fpga
 implmentation

---
 EF_UART.yaml                          |  4 ++--
 hdl/rtl/bus_wrappers/EF_UART_APB.pp.v | 30 +++++++++++++++------------
 hdl/rtl/bus_wrappers/EF_UART_APB.v    | 30 +++++++++++++++------------
 3 files changed, 36 insertions(+), 28 deletions(-)

diff --git a/EF_UART.yaml b/EF_UART.yaml
index 8394ce7..c7a19a4 100644
--- a/EF_UART.yaml
+++ b/EF_UART.yaml
@@ -7,8 +7,8 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: mshalan@efabless.com
-  version: v1.1.6
-  date: 08-07-2024
+  version: v1.1.7
+  date: 16-09-2024
   category: digital
   tags:
     - peripheral
diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v b/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
index ef03860..e4c1481 100644
--- a/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
+++ b/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
@@ -69,19 +69,23 @@ module EF_UART_APB #(
         wire clk_g;
         wire clk_gated_en = GCLK_REG[0];
 
-    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
-	`ifdef USE_POWER_PINS
-        .VPWR(VPWR), 
-        .VGND(VGND), 
-        .VNB(VGND),
-		.VPB(VPWR),
-    `endif
-        .GCLK(clk_g), 
-        .GATE(clk_gated_en), 
-        .CLK(PCLK)
-        );
-        
-	wire		clk = clk_g;
+	`ifdef FPGA
+		wire clk = PCLK;
+	`else
+		(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+		`ifdef USE_POWER_PINS 
+			.VPWR(VPWR), 
+			.VGND(VGND), 
+			.VNB(VGND),
+			.VPB(VPWR),
+		`endif
+			.GCLK(clk_g), 
+			.GATE(clk_gated_en), 
+			.CLK(PCLK)
+			);
+			
+		wire		clk = clk_g;
+	`endif
 	wire		rst_n = PRESETn;
 
 
diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.v b/hdl/rtl/bus_wrappers/EF_UART_APB.v
index 113c49e..5e73392 100644
--- a/hdl/rtl/bus_wrappers/EF_UART_APB.v
+++ b/hdl/rtl/bus_wrappers/EF_UART_APB.v
@@ -63,19 +63,23 @@ module EF_UART_APB #(
         wire clk_g;
         wire clk_gated_en = GCLK_REG[0];
 
-    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
-    `ifdef USE_POWER_PINS 
-        .VPWR(VPWR), 
-        .VGND(VGND), 
-        .VNB(VGND),
-		.VPB(VPWR),
-    `endif 
-        .GCLK(clk_g), 
-        .GATE(clk_gated_en), 
-        .CLK(PCLK)
-        );
-        
-	wire		clk = clk_g;
+	`ifdef FPGA
+		wire clk = PCLK;
+	`else
+		(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+		`ifdef USE_POWER_PINS 
+			.VPWR(VPWR), 
+			.VGND(VGND), 
+			.VNB(VGND),
+			.VPB(VPWR),
+		`endif
+			.GCLK(clk_g), 
+			.GATE(clk_gated_en), 
+			.CLK(PCLK)
+			);
+			
+		wire		clk = clk_g;
+	`endif
 	wire		rst_n = PRESETn;