From 3d4a582e997c0fba7f342ce4763b6aa9101e6b7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Luis=20Bueno=20L=C3=B3pez?= <69244257+JLBuenoLopez-eProsima@users.noreply.github.com> Date: Tue, 3 Oct 2023 09:28:13 +0200 Subject: [PATCH] Add IDL modules (#569) Signed-off-by: JLBuenoLopez-eProsima --- docs/fastddsgen/dataTypes/dataTypes.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/fastddsgen/dataTypes/dataTypes.rst b/docs/fastddsgen/dataTypes/dataTypes.rst index 7d9b351a3..5b8aca60f 100644 --- a/docs/fastddsgen/dataTypes/dataTypes.rst +++ b/docs/fastddsgen/dataTypes/dataTypes.rst @@ -404,6 +404,12 @@ If omitted, it will be 32 bits. For each ``flag``, the user can use the annotation ``position`` to define the position of the flag. If omitted, it will be auto incremented from the last defined flag, starting at 0. +Modules +^^^^^^^ + +In order to avoid collision between variable names, modules can be defined within the IDL file. +A module would be converted into a namespace in C++. + Data types with a key ^^^^^^^^^^^^^^^^^^^^^