| Name | Description |
|---|---|
TLB.L1.LOAD.ACCESS.SPEC |
Address translation requests for load instructions. Speculatively executed instructions are also taken into account. |
TLB.L1.CODE.ACCESS |
Address translation requests for instructions fetch |
TLB.L1.LOAD.MISS.SPEC |
Address translation requests for load instructions which missed L1 TLB. Speculatively executed instructions are also taken into account. |
TLB.L1.CODE.MISS.SPEC |
Address translation requests for instructions fetch which missed L1 TLB |
TLB.L1.LOAD.MISS_OUTSTANDING.CYCLES |
Cycles while at least one load L1 TLB miss in progress. |
TLB.L1.CODE.MISS_OUTSTANDING.CYCLES |
Cycles while at least one L1 TLB miss for instructions fetch in progress |
TLB.L1.STORE.ACCESS.SPEC |
Address translation requests for store instructions. Speculatively executed instructions are also taken into account. |
TLB.L1.STORE.MISS.SPEC |
Address translation requests for store instructions which missed L1 TLB. Speculatively executed instructions are also taken into account. |
TLB.L2.LOAD.MISS.SPEC |
Address translation requests for load instructions which missed L2 TLB. Speculatively executed instructions are also taken into account. |
TLB.L2.STORE.MISS.SPEC |
Address translation requests for store instructions which missed L2 TLB. Speculatively executed instructions are also taken into account. |
TLB.L2.CODE.MISS.SPEC |
Address translation requests for instruction fetch which missed L2 TLB |
TLB.L2.LOAD.MISS_OUTSTANDING.CYCLES |
Cycles while at least one load L2 TLB miss in progress. Speculatively executed instructions are also taken into account. |
TLB.L2.CODE.MISS_OUTSTANDING.CYCLES |
Cycles while at least one L2 TLB miss for instructions fetch in progress |