The most recent version of the NEORV32 project can be found at the top of this list.
"Stable releases" are linked and highlighted 🚀.
The latest release is 
ℹ️ Starting with version 1.5.7 this project uses semantic versioning syntax for official releases.
The hardware version identifier uses an addtional custom version element (i.e. MAJOR.MINOR.PATCH.individual) to track individual changes.
ℹ️ The processor can determine its version from the mimpid CSR (at CSR address 0xf13). A 8x4-bit BCD representation is used.
Leading zeros are optional. Example: CSR(mimpid) = 0x01040312 => 01.04.03.12 = Version 01.04.03.12 = v1.4.3.12. The version number is globally
defined by the hw_version_c constant in the main VHDL package file rtl/core/neorv32_package.vhd.
- 🐛 = bug-fix
- ✨ = new feature
⚠️ = (major) change that might impact compatibility with previous versions- 🔒 = security issue
- 🚀 = release
| Date (dd.mm.yyyy) | Version | Comment |
|---|---|---|
| 08.08.2021 | 1.5.8.9 | reworked CPU register file logic: any write access to x0 will be masked to actually write zero - no special treatment by the CPU control unit required anymore; slighlty less hardware ressources required; first instruction after hardware reset should write x0 (any value; implemented in start-up code crt0.S) |
| 07.08.2021 | 1.5.8.8 | 🐛 fixed bug in execution (trapping) of xRET instructions: dret (return from debug-mode handler) has to raise an illegal instruction exception if executed outside of debug-mode, mret (return from machine-mode handler) has to raise an illegal instruction exception if executed in lower-privileged modes (lower than machine-mode) |
| 05.08.2021 | 1.5.8.7 | ✨ added mstatus.FS and mstatus.SD CSR bits: control the state of the FPU (Zfinx) extension; supported states for mstatus.FS: 00 = off, 11 = dirty; writing other states will always set dirty state; note that all FPU instructions including FPU CSR access instructions will raise an illegal instrution exception if mstatus.FS = off |
| 03.08.2021 | 1.5.8.6 | 🐛 fixed bug in linker script #134: .rodata.* "sub"-sections were missing, caused wrong linking of implicit constants (like strings); added mconfigptr CSR (RISC-V priv. ISA spec. v1.12-draft ;read-only): holds a pointer to a platfrom/system configuration structure - not actually used yet |
| 30.07.2021 | 1.5.8.5 | fixed minor bug in top entity / AXI4 wrapper (Vivado "issue": generic defaults need a fixed-size intialization value) #113 |
| 26.07.2021 | 1.5.8.4 | 🐛 fixed major bug in CPU interrupt system: interrupts during memory accesses (load/store instruction) terminated those memory accesses violating the crucial "instruction atomicity" concept: traps (interrupts and exceptions) must only intervent between instructions |
| 25.07.2021 | 1.5.8.3 | ✨ added mstauts.TW CSR flag (when set executing wfi instruction outside of machine-mode will raise an illegal instruction exception); flag is hardwired to zero if user mode is not implemented |
| 25.07.2021 | 1.5.8.2 | 🐛 fixed bug in E ISA extension: extension could not be enabled due to missing generic propagation; clean-up of generic defaults: only the processor top entity provides defaults for the configuration generics |
| 24.07.2021 | 1.5.8.1 | machine-level interrupts (top entity signals; "external" mext_irq_i, "software" msw_irq_i, "mtime" mtime_irq_i and "non-maskable" nm_irq_i) now trigger on rising edges; exposed advanced external bus interface configuration options as new top entity generics (moved from package constants): MEM_EXT_PIPE_MODE, MEM_EXT_BIG_ENDIAN, MEM_EXT_ASYNC_RX |
| 22.07.2021 | 🚀1.5.8 | New release |
| 22.07.2021 | 1.5.7.16 | (re-)added mstatush CSR (all bits are hardwired to zero: writes are ignored, reads will always return zero) - CSR address is assigned to comply with RISC-V priv. arch. spec. 1.12 |
| 21.07.2021 | 1.5.7.15 | 🐛 fixed minor bug in SLINK module (signals were missing in sensitivity lists); IO_NEOLED_TX_FIFO to configure NEOLED FIFO depth |
| 18.07.2021 | 1.5.7.14 | exposed new generic CPU_IPB_ENTRIES to configure size of CPU instruction prefetch buffer |
| 18.07.2021 | 1.5.7.13 | clean-up of processor top entity: using more sophisticated default values for all input signals and generics (all generics are "off" by default; input signals use L for control lines and U for data lines by default) |
| 14.07.2021 | 1.5.7.12 | reworked SLINK interrupt concept (now using FIFO fill level "half-full" as interrupt condition, see #122); added fill level output to processor FIFO component |
| 09.07.2021 | 1.5.7.11 | 🐛 fixed minor bug in FIFO component (mapping might fail if FIFO_DEPTH = 1); fixed broken sw/example/demo_freeRTOS makefile (all freeRTOS includes were missing) |
| 03.07.2021 | 1.5.7.10 | ✨ added new component: External Interrupt Controller (XIRQ): up to 32 external interrupt channels xirq_i (via XIRQ_NUM_CH generic), configurable trigger (via XIRQ_TRIGGER_TYPE and XIRQ_TRIGGER_POLARITY generics), prioritized or non-prioritized servicing |
| 02.07.2021 | 1.5.7.9 | relocated base addresses of watchdog timer (WDT) and true-random number generator (TRNG); removed CPU's firq_ack_o signal (was not used at all) |
| 30.06.2021 | 1.5.7.8 | |
| 29.06.2021 | 1.5.7.7 | ✨ added new processor module stream link interface (SLINK): up to 8 individual RX and TX stream links, comptaible to AXI4-Stream base protocol; added software driver files; added documentation |
| 27.06.2021 | 1.5.7.6 | 🐛 fixed bug in CFS (custom functions subsystem) address map layout |
| 27.06.2021 | 1.5.7.5 | neorv32_nco.vhd) module as it appears to be an over-engineered clock-generator without many use cases (if you really need this module, you can wrap it within the custom functions subsystem CFS) |
| 27.06.2021 | 1.5.7.4 | soc_firq_i: the FIRQs are reserved for processor-internal usage only, use the mext_irq_i RISC-V external interrupt signal for all external interrupt applications (via dedicated interrupt conttoller), a follow-up version of the project will introduce a customizable external interrupt controller; sourced-out FIFOs into new HDL component neorv32_fifo.vhd |
| 26.06.2021 | 1.5.7.3 | edit of v1.5.7.2: RISC-V spec claims to leave destination registers of trapping load operation unchanged (do not set to zero); minor CPU control logic optimizations; ✨ reworked bootloader to provide several new configuration and customization options |
| 25.06.2021 | 1.5.7.2 | optimized instruction execution FSM: less hardware utilization, 🔒 now ensures to write ZERO to destination register if there is an exception during a load operation; made default bootloader even more HW configuration independent (GPIO, SPI and MTIME are optional; UART is optional but highly recommended); |
| 24.06.2021 | 1.5.7.1 | ✨ added RISC-V Zmmul ISA extension (via CPU_EXTENSION_RISCV_Zmmul generic; default = false): implements only the integer multiplication instructions sub-set of the M extension; for size-constrained setups, requires ~50% less hardware ressources than the M extension |
| 23.06.2021 | 🚀1.5.7 | New release one year NEORV32! 🎉 |
| 21.06.2021 | 1.5.6.14 | 🐛 fixed bug in debugger "park loop": fence.i instruction was missing before executing the DM's program buffer - this caused execution of outdated instructions from the program buffer if the instruction cache is implemented |
| 21.06.2021 | 1.5.6.13 | removed TINY_SHIFT_EN generic; clean-up of CPU co-processor system: removed "dummy co-processor" for CSR read access, moved CPU shifter core into new co-processor; simplified default (bit-serial) shifter logic (single bit-shifts only) and multi-cycl instructions decode logic |
| 18.06.2021 | 1.5.6.12 | clean-up of CPU co-processor system (removed unused co-processor slots 4,5,6,7) |
| 15.06.2021 | 1.5.6.11 | made bootloader more configuration-independent: bootloader now only uses the first 512 bytes of internal/external DMEM for runtime data - hence, the DMEM size is not further relevant as long as it greater than or equal to 512 bytes |
| 14.06.2021 | 1.5.6.10 | ✨ physical size of bootloader ROM (BOOTROM) is atutomatically determined during synthesis based on the size of the initialization image, max physical size is 32kB; simplified BOOTROM access check logic; added size check when using IMEM as ROM (check if application image fits); simplified linker script: logical instruction address space 2GB now, no need to adapt this to hardware configuration, hardware checks if application fits into physical memory size (which configured via generics) |
| 13.06.2021 | 1.5.6.9 | MEM_INT_IMEM_ROM and BOOTLOADER_EN generics, replaced by single INT_BOOTLOADER_EN generic (type boolean): true = implement processor-internal (default) bootloader, implement processor-internal IMEM (if implemented) as RAM; false = boot from processor-internal IMEM implemented (if enabled) as pre-intialized ROM; reworked IMEM, DMEM and BOOTROM memory architecture; reworked image generator and generated application image files (now using unconstrained array as init images + unified array/memory types) |
| 12.06.2021 | 1.5.6.8 | 🐛 fixed bug in instruction cache (cache controller might have missed resync/"clear-and-reload" requests from fence.i instructions); mino project/repo clean-ups |
| 08.06.2021 | 1.5.6.7 | clean-up of Wishbone interface module (dead code removal); added new package constant wb_rx_buffer_c to configure SYNC (default) or ASYNC Wishbone RX path (allows trade-off between performance/latency and timing closure) |
| 06.06.2021 | 1.5.6.6 | 🐛 fixed bug in PWM base address configuration; hpmcounter3[h]:hpmcounter3[h] CSRs, hardwaired according mcounteren bits to zero: HPM can only be used in machine mode; reworded 64-bit counters (cycle, instret, hpmcounter + mtime) overflow logic: now using dedicated CARRY chain instead of overflow detector (can improve timing); |
| 05.06.2021 | 1.5.6.5 | removed debug mode's stepie flag (used to allow interrupts during single-stepping) as the debugger can emulate interrupts |
| 04.06.2021 | 1.5.6.4 | IO_PWM_EN generic, replaced by IO_PWM_NUM_CH generic - PWM ontroller now supports implementation of up to 60 channels via IO_PWM_NUM_CH (IO_PWM_NUM_CH = 0 will omit the PWM controller); 🐛 fixed minor bug in minstreth counter logic |
| 04.06.2021 | 1.5.6.3 | |
| 03.06.2021 | 1.5.6.2 | B ISA extension (bit manipulation) has been (temporarily) removed from the project. See B ISA Extension project board. |
| 03.06.2021 | 1.5.6.1 | CPU/HPM counter size configuration (CPU_CNT_WIDTH and HPM_CNT_WIDTH generics) can now be 0-bit (no counters implemented at all) to 64-bit (full-scale / RISC-V standard) wide |
| 01.06.2021 | 🚀1.5.6.0 | New release |
| 01.06.2021 | 1.5.5.13 | sw/image_gen) and bootloader to generate/use little-endian executables; external memory interface is little-endian by default; removed mstatus.ube bit (reads as zero now); removed mstatush CSR |
| 31.05.2021 | 1.5.5.12 | mret instruction now clears mstatus.mpp (according to new RISC-V privileged specs.) |
| 31.05.2021 | 1.5.5.11 | mtval CSR is now read-only; a write access will raise an illegal instruction exception |
| 30.05.2021 | 1.5.5.10 | 🐛 fixed bug in processor's reset system (system reset stuck at 0 if on-chip debugger not implemented); reworked processor's reset generator system; VHDL code clean-up; reworked SoC's bus infrastructure (now using array of records for module bus response) |
| 28.05.2021 | 1.5.5.9 | integrated DBMEM (debug memory) component into DM (debug module); removing now-obsolete neorv32_debug_dbmem.vhd component |
| 22.05.2021 | 1.5.5.8 | ✨ on-chip debugger (OCD): added debug module (DM) component; OCD is operational now (but still experimental) |
| 22.05.2021 | 1.5.5.7 | 🐛 fixed bug in internal memory monitoring: if accessing an unused address which is not re-directed to the external bus interface (because WISHBONE module is disabled) caused the CPU to stall since that bus access was not correctly monitored and aborted by the BUS_KEEPER |
| 21.05.2021 | 1.5.5.6 | on-chip debugger: added debug transport module (DTM) component |
| 20.05.2021 | 1.5.5.5 | added system time output mtime_o (64-bit) driven by processor-internal MTIME unit (idea #29) |
| 20.05.2021 | 1.5.5.4 | on-chip debugger: added debug memory (DBMEM) component |
| 20.05.2021 | 1.5.5.3 | added flag (SYSINFO.FEATURES) to allow software to discover if on-chip debugger is implemented (SYSINFO_FEATURES_OCD); added documentation https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd |
| 19.05.2021 | 1.5.5.2 | ✨ added RISC-V CPU Debug Mode, compatible to RISC-V debug spec; new CSRs: dcsr, dpc, dscratch; new instructions: dret; fence.i will not longer trap if executed but not implemented (CPU_EXTENSION_RISCV_Zifencei = false) |
| 13.05.2021 | 1.5.5.1 | added UPduino_v3 example setup; renamed signal in watchdog module (rtl/core/neorv32_wdt.vhd) - collision with reserved keyword in vhdl-2008 (fixing issue #24) |
| 10.05.2021 | 🚀1.5.5.0 | New release |
| 10.05.2021 | 1.5.4.12 | mip CSR is now read-only (pending IRQs can be cleared by disabling (and re-enabling) the according mie bit), writing to mip will raise an illegal instruction exception; ✨ added non-maskable interrupt (NMI), top entity port nm_irq_i; added new NMI to NEORV32 runtime environment |
| 09.05.2021 | 1.5.4.11 | added new flags to mzext CSR: CSR_MZEXT_PMP (set if at least 1 PMP region is implemented at all), CSR_MZEXT_HPM (set if at least 1 HPM counter is implemented) |
| 03.05.2021 | 1.5.4.10 | minor code clean-ups; moved FIRQ synchronization registers to top, removed sync FFs for processor-internal sources; |
| 30.04.2021 | 1.5.4.9 | moved definitions of IO area from crt0.S to linker script; reworked CPU's CSR access system - highly reducing area overhead (removing decoding logic of not implemented CSRs by heavily using VHDL's NULL statement in case constructs) |
| 29.04.2021 | 1.5.4.8 | minor edits in CPU instruction fetch engine; reduced processor-internal bus timeout (max_proc_int_response_time_c) to 15 cycles; added flag to SYSINGO module (SYSINFO_FEATURES_HW_RESET) to check if a dedicated hardware reset of all core register is implemented (via package's dedicated_reset_c constant) |
| 28.04.2021 | 1.5.4.7 | 🐛 fixed bug in instruction cache (iCACHE) when using two sets - ICACHE_ASSOCIATIVITY = 2: cache was corrupting the non-active set |
| 26.04.2021 | 1.5.4.6 | optimized CPU's instruction fetch unit: less overhead for branches, reduced unit's hardware complexity |
| 25.04.2021 | 1.5.4.5 | ✨ cancel signals from processor-internal bus system; removed CPU's internal bus access timeout counter; added new top generic: MEM_EXT_TIMEOUT - type natural, default = 255; used to configure optional auto-timeout of Wishbone interface (if an external device is not responding within MEM_EXT_TIMEOUT clock cycles); set to zero to disable auto-timeout (required to comply with AXI4-Lite specs. when using the top's AXI wrapper) |
| 25.04.2021 | 1.5.4.3 | ✨ converted NEORV32.pdf data sheet to asciidoc using asciidoctor; added data sheet sources to docs/src_adoc |
| 21.04.2021 | 1.5.4.3 | wb_tag_i signal, pruned one bit of top's wb_tag_o signal (atomic access), added top's wb_lock_o signal; updated sections in NEORV32.pdf regarding atomic memory accesses |
| 19.04.2021 | 1.5.4.1 | added register stage to MTIME.time write access to improve timing closure |
| 17.04.2021 | 🚀1.5.4.0 | New release |
| 16.04.2021 | 1.5.3.13 | TINY_SHIFT_EN (type = boolean, default = false) to configure a tiny single-bit (iterative) shifter for CPU ALU shift operations (for highly area-constrained setups) |
| 16.04.2021 | 1.5.3.12 | ✨ reworked reset system of the complete CPU: by default most registers (= "uncritical registers") do not provide an initialization via hardware reset; a defined reset value can be enabled by setting a constant from the main VHDL package (rtl/core/neorv32_package.vhd): constant dedicated_reset_c : boolean := false; (set true to enable CPU-wide dedicated register reset); see new section "2.11. CPU Hardware Reset" of NEORV32.pdf for more information |
| 14.04.2021 | 1.5.3.11 | minor rtl edits to allow synthesis using ghdl-yosys-plugin (:construction: work in progress :construction:) |
| 13.04.2021 | 1.5.3.10 | 🐛 fixed bug when configuring HPM_CNT_WIDTH less than 32; CPU_CNT_WIDTH to configure total size of CPU's cycle and instret CSRs (default = 64-bit); added Zxnocnt (no counters) and Zxscnt (small counters) flags to mzexr CSR to check if CPU_CNT_WIDTH is zero or less than 64, respectively; 🐛 fixed bug in crt0.S start-up code: stack pointer has to be initialized before an exception can occur; updated cpu_test example program |
| 11.04.2021 | 1.5.3.9 | |
| 09.04.2021 | 1.5.3.8 | optimized CPU control: register write back during multi-cycle ALU operation only when result is really available (reducing switching activity; avoids possible source operand corruption); optimized M extension's co-processor: multiplications and divisions are 2 cycles faster |
| 08.04.2021 | 1.5.3.7 | 🐛 fixed bug in HPM event configuration via mhpmevent* CSRs - there was a CSR address decoding overlap between the HPM event CSRs and the machine trap setup CSRs (introduced in version 1.5.3.6); |
| 02.04.2021 | 1.5.3.6 | 🐛 fixed bug in external memory interface (neorv32_wishbone.vhd) that caused bus exceptions when using external memories with very high access latencies (race condition in bus timeouts); VHDL code clean-up |
| 30.03.2021 | 1.5.3.5 | added new top's generic HPM_CNT_WIDTH (type natural, default=40) to configure the total bit width of the hardware performance monitors (HPM) counter (min 1, max 64); mofified crt0.S: stops all counters (incl. HPMs), no user-level access to ANY counter; neorv32.h: added missing mcounteren and mcountinhibit CSR bit definitions |
| 28.03.2021 | 1.5.3.4 | default "test setup" rtl/top_templetes/neorv32_test_setup.vhd: disabled PMP, implementing 4 HPM counters; ✨ added boards folder for exemplary FPGA setups |
| 27.03.2021 | 1.5.3.3 | minor optimization in CPU control engine; FPU comparator now uses comparatos results from main ALU (reduces FPU hardware footprint) |
| 26.03.2021 | 1.5.3.2 | ✨ added single-precision floating-point unit (FPU) rtl/core/neorv32_cpu_cp_fpu.vhd implementing the Zfinx CPU extension; added/updated Zfinx intrinsic library and verification framework: sw/example/floating_point_test; added co-processor timeout counter to CPU to auto-terminate co-processor operations (for debugging only; defaullt=deactivated) |
| 25.03.2021 | 1.5.3.1 | 🐛 fixed bug in invalid floating-point instruction detection (caused CPU to stall if executing an invalid floating-point operation); intrinsic core library (mainly used for not-yet-supported CPU extensions like B and Zfinx): clean-up, added R3 instruction type |
| 24.03.2021 | 🚀1.5.3.0 | New release |
| 23.03.2021 | 1.5.2.9 | ✨ added new top generic to enable single-precision floating-point extensions Zfinx: CPU_EXTENSION_RISCV_Zfinx - type boolean, default = false, Z* extensions (from mzext CSR) like Zifencei |
| 21.03.2021 | 1.5.2.8 | 🐛 fixed problem with linking math.h library in makefile; added floating-point-related global definitions to main VHDL package; added intrinsic core library file sw/lib/include/neorv32_intrinsics.h - intrinsic library support for CPU extensions, which are not yet supported by the upstream GCC, are based on this |
| 18.03.2021 | 1.5.2.7 | 🐛 fixed bug in sw/common/crt0.S dummy exception handler (wrong order of register push/pop); changed upcoming floating-point extension (orignally F extension) to Zfinx extension (-> RISC-V Zfinx spec) - updated CPU infrastructure |
| 16.03.2021 | 1.5.2.6 | reworked atomic/exclusive memory access interface: removed CPU's d_bus_lock_o and i_bus_lock_o signal (was always zero anyway); removed top's wb_lock_o signal; added exclusive access request to Wishbone tag signal wb_tag_o (is now one bit wider); added more details to NEORV32.pdf regarding excluisve/atomic memory accesses (interface/protocol) |
| 09.03.2021 | 1.5.2.5 | added bit-manipulation Zba sub-extension (shifted-adds: SH1ADD SH2ADD SH3ADD) |
| 07.03.2021 | 1.5.2.4 | ✨ added new IO/peripheral module: Smart LED Interface (NEOLED) to interface intelligent LEDs (WS2812/WS2811/NeoPixel(c) compatible; supports RGB and RGBW LEDs in parallel) with internal TX buffer; new top generics: IO_NEOLED_EN: implement NEOLED interface when true; new top signals: neoled_o: single-wire async. serial data interface; FIFO re-fill interrupt via fast interrupt request channel 9 FIRQ9; added new "NEOLED" section to data sheet; added SW driver library and simple NEOLED example program (sw/example/demo_neopixel) |
| 06.03.2021 | 1.5.2.3 | clean-up of CPU control code: fixed minor bug in F-exension's instruction decoding; changed coding style for CSR write access (old version might have caused "inferring latch..." warning in Intel Quartus); fixed default values for CSRs when according extensions are disabled |
| 04.03.2021 | 1.5.2.2 | added two new generics to configure CFS IO conduit sizes (implementing issue #13): IO_CFS_IN_SIZE - type: positive, configures the size of cfs_in_i signal; IO_CFS_OUT_SIZE - type: positive, configures the size of cfs_out_o signal; minor edits to floating-point CPU infrastructure |
| 03.03.2021 | 1.5.2.1 | added CPU core infrastructure for upcoming single-precision floating-point extension F; rtl/core/neorv32_cpu_cp_fpu.vhd (blank template!) |
| 01.03.2021 | 🚀1.5.2.0 | New release |
| 27.02.2021 | 1.5.1.11 | 🐛 fixed several small bugs in bitmanipulation extension instruction decoding (not all B instructions triggered and illegal instruction exception when B-extension = disabled) |
| 25.02.2021 | 1.5.1.10 | 🐛 fixed bugs in UART RTS/CTS hardware control flow - the new setup was verified on real hardware; added double-buffering to UART RX engine |
| 24.02.2021 | 1.5.1.9 | mcounteren CSR is hardwired to zero if user mode is not implemented (CPU_EXTENSION_RISCV_U = false); added Zbs (single-bit operations) sub-extension to bitmanipulation unit |
| 22.02.2021 | 1.5.1.8 | added programmable RTS/CTS hardware flow control to UARTs; new top signals: uart0_rts_o, uart0_cts_i, uart1_rts_o, uart1_cts_i; UART.TX engine will only start sending (if CTS flow control is activated) if uart*_cts_i is asserted (low-active); UART.RX engine signals (if RTS flow control is activated) via uart*_rts_o if it is ready to receive new data (low-active); added hw flow control parameter to uart setup functions neorv32_uart*_setup() |
| 20.02.2021 | 1.5.1.7 | removed err_o signal from custom functions subsystem CFS; processor SoC fast interrupt input soc_firq_i reduced to 6 channels (was 8) - mapped to CPU's FIRQ_10 - FIRQ_15; added individual fast IRQs for UART1 "RX complete" and "TX complete" conditions (-> FIRQ_4 & FIRQ_5); changed FIRQ channels of TWI/SPI/GPIO interrupts |
| 18.02.2021 | 1.5.1.6 | added register buffer for enable signals to processor-internal clock generator; 🐛 fixed bug in sw/example/demo_twi program: TWI clock speed messsage was wrong (factor 1/4 was missing) |
| 17.02.2021 | 1.5.1.5 | added a second independent UART: new UART is secondary UART UART0, the "old" UART is now the primary UART UART0; by default the primary UART (UART0) is used for all user interface connection; reworked fast interrupt FIRQ assignment/priority list - added UART1 RTX (receive or send done) fast interrupt; added hardware driver functions for new UART1 - the "old" neorv32_uart_* function calls will map to the primary UART UART0 for compatibility; renamed compiler flag to enable UART "simulation mode": UART_SIM_MODE -> UART0_SIM_MODE for primary UART, UART1_SIM_MODE for secondary UART (UART_SIM_MODE is still supported for compatibility and maps to UART0_SIM_MODE); added second simulation UART receiver for UART1 to testbench; renamed UART simulation output files: neorv32.testbench_uart.out -> neorv32.testbench_uart0.out (testbench UART0 receiver), new: neorv32.testbench_uart1.out (testbench UART1 receiver), neorv32.uart.sim_mode.text.out and neorv32.uart.sim_mode.data.out -> neorv32.uart0.sim_mode.text.out and neorv32.uart0.sim_mode.data.out (for UART0), new neorv32.uart1.sim_mode.text.out and neorv32.uart1.sim_mode.data.out (for UART1) |
| 13.02.2021 | 1.5.1.4 | HW_THREAD_ID generic is now of type natural; mret instruction now requires an additional cycle to execute; logic optimization of CPU's control logic -> smaller hardware footprint and higher f_max; updated CPU synthesis results; removed top module's generic initialization using (others => '0') (targeting issue #8) |
| 09.02.2021 | 1.5.1.3 | modified CPU architecture: now using a "pseudo" ALU co-processor to get the result of a CSR read operation into data path, removing one input from register file input mux -> shorter critical path |
| 08.02.2021 | 1.5.1.2 | added new peripheral/IO module: Numerically-Controlled Oscillator NCO: three independent channels, 20-bit phase accu, 20-bit tuning word, fixed 50% duty cycle mode or pulsed mode; added according HW drivers and example program |
| 07.02.2021 | 🚀1.5.1.0 | New release |
| 05.02.2021 | 1.5.0.11 | 🐛 fixed error in atomic instruction LR.W |
| 05.02.2021 | 1.5.0.10 | CPU now provides 16 fast interrupt request lines (FIRQ0 .. FIRQ15) with according mie/mip CSR bits and mcause trap codes; removed IRQ enable flags from SPI, UART & TWI; reworked processor-internal interrupt system - assignment/priority list; UART now features individual IRQs for "RX-done" and "TX-done" conditions; changed bit order in TWI control register |
| 29.01.2021 | 1.5.0.9 | removed custom function units CFU0 & CFU1; ✨ replaced them by new Custom Functions Subsystem CFS, which provides up to 32x32-bit memory-mapped registers; new configuration generics: IO_CFS_EN, IO_CFS_CONFIG; new top entity signals: cfs_in_i, cfs_out_o; increased processor's IO area from 128 bytes to 256 bytes, now starting at 0xFFFFFF00 |
| 28.01.2021 | 1.5.0.8 | added critical limit for number of implemented PMP regions: When implementing more PMP regions that a certain critical limit an additional register stage is automatically inserted into the CPU’s memory interfaces increasing the latency of instruction fetches and data access by +1 cycle. The critical limit can be adapted for custom use by a constant from the main VHDL package file (rtl/core/neorv32_package.vhd). The default value is 8: constant pmp_num_regions_critical_c : natural := 8; |
| 27.01.2021 | 1.5.0.7 | added four additional fast interrupt channels FIRQ4..7, available via processor's top soc_firq_i(3:0) signal for custom platform use; fixed minor error in UART setup function (baud rate prescaler calculation for very high baud rates) |
| 26.01.2021 | 1.5.0.6 | minor logic optimization of CPU's B extension co-processor (reducing area); minor logic optimization or HPM triggers (reducing area); reworked CPU's co-processor interface; minor logic optimiztation of branch condition check (to shorten critical path) |
| 23.01.2021 | 1.5.0.5 | reworked true random number generator TRNG: architecture is now based on several simple ring oscillators with incrementing length; changed control register bits; updated according driver functions and demo program |
| 22.01.2021 | 1.5.0.4 | 🐛 fixed BUG in bootloader (that caused it to immediately crash after reset if SPI/MTIME/GPIO peripherals were not implemented); reworked watchdog timer WDT: removed watchdog access password, added option to lock configuration until next system reset, changed control register bits - updated driver functions and demo/test programs |
| 17.01.2021 | 1.5.0.3 | CPU data register file can now be mapped to a single "true dual-port" block RAM by the synthesizer (requiring only 1024 memory bits instead of 2048); 🐛 fixed typo error in sim/rtl_modules/neorv32_imem.vhd; modified M co-processor (due to register file read access modification), reduced switching activity when co-processor is idle; logic/arithmetic operations of B extension only require 3 cycles now, reduced switching activity when co-processor is idle |
| 15.01.2021 | 1.5.0.2 | added instruction cache associativity configuration (number of sets); new configuration generic: ICACHE_ASSOCIATIVITY -> number of sets (1 = direct mapped, 2 = 2-way set-associative), has to be a power of two; if associativity is > 1 the used replacement policy is least recently used (LRU); 🐛 fixed bug in sw/lib/source/neorv32_cpu.c PMP.CFG configuration function |
| 14.01.2021 | 1.5.0.1 | added new HPM trigger event: multi-cycle ALU operation wait cycle (HPMCNT_EVENT_WAIT_MC); renamed neorv32_cache.vhd -> neorv32_icache.vhd |
| 10.01.2021 | 🚀1.5.0.0 | Renamed configuration generics: *_USE -> *_EN |
| 10.01.2021 | 1.4.9.10 | ✨ Added support for bit manipulation extension (B) - base subset Zbb only (:warning: RISC-V B (sub-)extensions are not officially ratified yet; compatible to version "0.94-draft"); enabled via new configuration constant CPU_EXTENSION_RISCV_B (default = false); uported Zbb instructions: CLZ CTZ CPOP SEXT.B SEXT.H MIN[U] MAX[U] ANDN ORN XNOR ROL ROR RORI zext(pseudo-instruction for PACK rd, rs, zero) rev8(pseudo-instruction for GREVI rd, rs, -8) orc.b(pseudo-instruction for GORCI rd, rs, 7); added B flag to misa CSR; added Zbb flag to mzext CSR |
| 03.01.2021 | 1.4.9.8 | Added HPM trigger for instruction issue wait cycle (caused by pipeline flush); all HPM counters do not increment if CPU is sleep mode; fixed CoreMark timer overflow issues; rtl/core/neorv32_busswitch.vhd: removed wait states, less load/store wait cycles -> faster execution; updated CoreMark results |
| 02.01.2021 | 1.4.9.7 | ✨ added RISC-V hardware performance monitors (HPM); new CSRs: mhpmevent*(3..31), [m]hpmcounter*[h](3..31), amount configurable via top's generic HPM_NUM_CNTS; supported counter events: active cycle, retired instruction, retired compressed instruction, instruction fetcch memory wait cycle, load operation, store operation, load/store memory wait cycle, unconditional jump, conditional branche (all), conditional taken branch, entered trap, illegal instruction exception; PMP can now have up to 64 regions; number of regions configured via top's PMP_NUM_REGIONS generic; removed obsolete top's PMP_USE generic; removed PMP flag from mzext CSR; minimal region granularity (in bytes) configured via top's PMP_MIN_GRANULARITY generic, has to be a power of two and >= 8 bytes; 🐛 fixed bug in sleep (wfi) instruction |
| 29.12.2020 | 1.4.9.5 | New UART features: "frame check" (test if stop bit is set), error indicated via UART_DATA reg's UART_DATA_FERR flag; configurable parity bit (UART_CT.UART_CT_PMODE1:UART_CT_PMODE0, 00=no parity; 10=even parity; 11=odd parity); parity error indicated via UART_DATA reg's UART_DATA_PERR flag; moved UART's RX overrun flag to UART_DATA.UART_DATA_OVERR |
| 26.12.2020 | 1.4.9.4 | removed zicnt_en option (was used to discard the standard RISC-V counters and timers from implementation); added missing mcounteren CSR (to allow read-access from user-level code to cycle[h] / time[h] / [m]instret[h] CSRs); available bits: 0: CY, 1: TM, 2: IR; added missing mcountinhibit CSR (to disable auto-increment of [m]cycle[h] / [m]instret[h] CSRs); available bits: 0: CY, 2: IR; CPU_* -> CSR_* |
| 25.12.2020 | 1.4.9.3 | Added missing UBE flag to mstatus CSR, indicates Endianness for load/stores in user mode (always set indicating BIG-endian mode), is a copy of mstatush.mbe |
| 23.12.2020 | 1.4.9.2 | ✨ added processor-internal instruction cache rtl/core/neorv32_cache.vhd (direct mapped); new configuration generics: ICACHE_USE (implement cache), ICACHE_BLOCK_SIZE (cache block/page/line size), ICACHE_NUM_BLOCKS (number of cache blocks); added SYSINFO_CACHE register to SYSINFO to check cache configuration by software |
| 20.12.2020 | 1.4.9.1 | 🐛 fixed bug in CPU's instruction fetch engine (alignment_errros/bus_errors were not acknowledged correctly); added BUS_TIMEOUT generic to CPU (defines the amount of cycles after which an unacknowledged bus access will get terminated and raises a bus access fault exception) |
| 19.12.2020 | 🚀1.4.9.0 | Testbench: added memory-mapped triggers to trigger core's "machine software & external interrupts"; sw/example/cpu_test: removed CFU tests, added MEI and MSI tests; added RISC-V-Compliance Test Framework to repository (riscv-compliance/), core passes all rv32 tests (riscv-compliance v2.1) |
| 18.12.2020 | 1.4.8.13 | Added additional simulation files: simulation-optimized IMEM-ROM (so far, this is only relevant for the new NEORV32 RISC-V Compliance test framework v2.0); ✨ Processor now passes all rv32 tests of the new RISC-V Compliance Test Framework v2.0 ✨ |
| 16.12.2020 | 1.4.8.12 | mtval CSR generation (wrong value for "breakpoint" trap); updated mtval value table in data sheet; fixed bug in load/store operation (intoroduced in version 1.4.8.10) |
| 16.12.2020 | 1.4.8.11 | mtval CSR generation (wrong values for some traps); fixed bug in mip CSR (writing zero to implemented bits now actually clears pending interrupts); fixed bug in IRQ priority encoding (machine software interrupt MSI comes before machine timer interrupt MTI) |
| 12.12.2020 | 1.4.8.10 | trap_reset_c encoding (in it's expanded form it should be 0x80000000) and reset logic: hardware mcause register is now set to trap_reset_c after a hardware reset; crt0.S start-up code now sets mcause to trap_reset_c after finishing hardware setup |
| 11.12.2020 | 1.4.8.9 | Added option to exclude standard RISC-V performance counters ([m]cycle[h] and [m]instret[h]) for size-constrained implementations; disabled by setting VHDL package's zicnt_en_c constant to false; software can determine state of zicnt_en_c via mzext CSR's CPU_MZEXT_ZICNT bit; added new signal to processor top entity: mtime_i, this signal is used for updateting the time[h] CSRs if the processor-internal MTIME unit is disabled (via IO_MTIME_USE = false) |
| 10.12.2020 | 1.4.8.8 | Added missing mstatush CSR (only bit MBE is implemented yet); added option to configure external bus interface for BIG- or little-endian byte-order, configured via VHDL package xbus_big_endian_c constant, default = BIG-endian, software can check endianness of the interface via SYSINFO's SYSINFO_FEATURES(SYSINFO_FEATURES_MEM_EXT_ENDIAN) flag; added mstatush CSR and endianness information to data sheet |
| 09.12.2020 | 1.4.8.7 | Added missing environment call from U-mode exception (via ecall instruction in user-mode); added environment call from U-mode to data sheet |
| 09.12.2020 | 1.4.8.6 | A extension could not be used without MULDIV M extension, CPU might have permanently stalled when executing an instruction from a disabled ISA extension; 🔒 added security feature: illegal user-level CSR read access will always return zero; added new section Execution Safety to neorv32.pdf data sheet |
| 07.12.2020 | 1.4.8.5 | |
| 05.12.2020 | 1.4.8.4 | PMP_NUM_REGIONS and PMP_GRANULARITY CPU/processor generics (PMP configuration now via package constants); reworked section 2.4. Instruction Sets and CPU Extensions of neorv32.pdf |
| 04.12.2020 | 1.4.8.2 | Added PMA (physical memory attribute) to processor-internal IO region: NO EXECUTE; added 3.3.Address Space/Physical Memory Attributes (PMAs) section to neorv32.pdf |
| 03.12.2020 | 1.4.8.1 | Optimized CPU program counter (PC) update logic and "next PC" computation (shortend critical path); updated bootloader (configuration option for direct-boot-from-SPI-flash only) and customization text in neorv32.pdf |
| 01.12.2020 | 🚀1.4.8.0 | A (atomic) extension support (only lr.w and sc.w instructions yet); added lock signal to CPU and processor's external bus interface |
| 28.11.2020 | 1.4.7.6 | Split ALU core operations: shortened critical path - replaced ALU output 8:1 mux by a 4:1 mux |
| 26.11.2020 | 1.4.7.5 | Minor rtl clean-up; CSR access instructions are one cycle faster now (3 cycles now); system/environemnt instructions (ecall ebreak mret wfi) need one additional cycle (4 cycles now) |
| 25.11.2020 | 1.4.7.4 | FENCE.I instruction that corrupted instruction fetch when executing code from processor-external memory; default testbench (sim/neorv32_tb.vhd) now features external IMEM, external DMEM and external IO connected via external bus interface; simulation now allows CPU to execute code using external memories only (no internal IMEM/DMEM); optimized CPU's instruction fetch interface (no more unnecessary transfer cancel requests) |
| 20.11.2020 | 1.4.7.2 | wishbone) now makes sure that a canceled bus transfer is really understood by the accessed peripheral |
| 20.11.2020 | 1.4.7.1 | Removed deprecated "update_enable signal" from IMEM |
| 11.11.2020 | 🚀1.4.7.0 | Further optimized pipeline front-end: Jumps and branches are one cycle faster (+5% coremark performance); updated synthesis results; updated performance results; added hello_world example program |
| 07.11.2020 | 1.4.6.7 | Updated bootloader (size optimization) and changed processor version output; added project logo; minor data sheet edits |
| 03.11.2020 | 1.4.6.6 | Removed SPI module's buggy "LSB-first mode", SPI module now always sends data MSB-first; removed SPI.CTRL SPI_CT_DIR bit; modfied bit order in SPI CTRL register; updated SPI SW library |
| 02.11.2020 | 1.4.6.5 | |
| 01.11.2020 | 1.4.6.4 | [m]instret[h] and [m]cycle[h] carry logic; CPU hardware optimizations (area reduction, shortend critical path) |
| 29.10.2020 | 1.4.6.3 | rtl code clean-up; made preparations for additional co-processors |
| 25.10.2020 | 1.4.6.2 | Added tag signal (wb_tag_o) to processor's Wishbone bus; removed processors's priv_o - privilege level is now encoded in Wishbone tag signal; added a more sophisticated FreeRTOS example ("full_demo") |
| 24.10.2020 | 🚀1.4.6.0 | Completely reworked external memory interface (WISHBONE), removed now-obsolete processor generic MEM_EXT_REG_STAGES; added processor wrapper with AXI4-Lite master interface |
| 22.10.2020 | 1.4.5.11 | TWI: Added new control register flag to enable/disable SCL clock stretching by peripheral devices |
| 22.10.2020 | 1.4.5.10 | Added i_bus_priv_o and d_bus_priv_o signals to CPU_top and priv_o to Processor_top to show privilege level of bus access (from mstatus MPP); |
| 20.10.2020 | 1.4.5.9 | WFI - wait for interrupt) |
| 20.10.2020 | 1.4.5.8 | Machine timer interrupt is available as processor input pin (mtime_irq_i) if internal MTIME is not implemented (IO_MTIME_USE = false) |
| 18.10.2020 | 1.4.5.7 | Added new IO peripheral/Device: Second CFU (CFU1); renamed old CFU to CFU0; CFU VHDL files: neorv32_cfu0.vhd & neorv32_cfu1.vhd; removed CFU interrupt |
| 17.10.2020 | 1.4.5.5 | New makefile target upload allows to directly upload an executable to the bootloader from the console |
| 17.10.2020 | 1.4.5.4 | Added new CPU/Processor generic FAST_SHIFT_EN (default = false) to enable implementation of a fast (but large) barrel shifter for accelerating CPU shift instructions; updated CoreMark performance results |
| 16.10.2020 | 1.4.5.2 | Added read-only flag to custom mzext CSR to check if physical memory protection (PMP) is implemented; added [C] mzext CSR name aliases to neorv32.h |
| 15.10.2020 | 1.4.5.1 | Fixed "unprecise exceptions": mtval did not always reflect the correct value according to the instruction that caused the exceptions; fixed bug in RTE: Debug trap handler was not showing the correct mepc value |
| 13.10.2020 | 🚀1.4.5.0 | An official open-soucre RISC-V architecture ID was assigned to the project: decimal = 19, 32-bit hexadecimal = 0x00000013 - software can retrieve the ID from the marchid CSR |
| 12.10.2020 | 1.4.4.9 | Added alignment flags to makefiles: branch/jump/call targets are forced to be 32-bit aligned -> increases performance when using the C extension; added makefile flag listing to NEORV32.pdf; updated performance results for CPUs with C extension; crt0.S will initialize all registers with zero if not using E extension and not compiling bootloader |
| 11.10.2020 | 1.4.4.8 | Reworked pipeline frontend: Optimized fetch enginge, added issue engine, faster instruction fetch after taken branches + reduced hardware requirements; updated synthesis and performance results |
| 11.10.2020 | 1.4.4.6 | Added option to configure external memory interface (Wishbone) to either use standard/classic protocol (default) or pipelined protocol (for better timing): via wb_pipe_mode_c constant in VHDL package file (rtl/core/neorv32_package.vhd); added help text to NEORV32.pdf section "3.4.4. Processor-External Memory Interface (WISHBONE)" |
| 08.10.2020 | 1.4.4.5 | Removed CPU's BUS_TIMEOUT and processor's MEM_EXT_TIMEOUT generics; instead, a global configuration bus_timeout_c in the VHDL package file is used now |
| 08.10.2020 | 1.4.4.4 | Removed DEVNULL device; all simulation output options from this device are now available as SIM_MODE in the UART; mcause CSR can now also be written; FIXED: trying to write a read-only CSR will cause an illegal instruction exception; for compatibility reasons any write access to the misa CSR will be ignored and will NOT cause an exception |
| 07.10.2020 | 1.4.4.2 | Simplified ALU's set of core operations; removed co-processor data mux right after ALU -> shorter critical path; CPU control VHDL code clean-up and CSR write logic optimization; optimized IMEM/DMEM access logic; added note regarding alignment of IMEM/DMEM |
| 05.10.2020 | 🚀1.4.4.0 | |
| 02.10.2020 | 1.4.3.9 | [m]cycleh and [m]instreth CSRs are now 32-bit wide (-> fully RISC-V-compliant) |
| 01.10.2020 | 1.4.3.8 | Added CPU top entity wrapper with resolved port signals rtl/top_templetes/neorv32_cpu_stdlogic.vhd; optimized ALU core functions – shorter critical path, less control overhead, reduced HW footprint |
| 27.09.2020 | 1.4.3.3 | Further improved ALU and control logic; CSR access instruction require one additional cycle now (to let side effects kick in); updated synthesis results; added CFU hardware driver dummy |
| 26.09.2020 | 1.4.3.2 | CSRRWI instruction (introduced with version 1.4.3.1); further ALU operand logic optimizations; updated CPU data path figure |
| 25.09.2020 | 1.4.3.1 | Register file's x0 is now a physical register; this register is initialized by the hardware and locked afterwards; removed "set to zero" stage -> smaller hardware footprint and shorter critical path; added processor top entity wrapper with resolved signals rtl/top_templetes/neorv32_top_stdlogic.vhd |
| 16.09.2020 | 🚀1.4.3.0 | Simplified memory configuration: removed processor top's memory space configuration generics (MEM_ISPACE_BASE, MEM_ISPACE_SIZE, MEM_DSPACE_BASE, MEM_DSPACE_SIZE); data/instruction space sizes are irrelevant for hardware; instruction/data space base addresses are fixed (but can be modified in NEORV32 VHDL package file); modified SYSINFO registers; adapted bootloader, crt0 start-up code and linker script; stack configuration is now done via linker script; reworked chapter "address space"; added CFU interrupt -> fast interrupt channel 1 (shared with GPIO) |
| 14.09.2020 | 1.4.2.0 | Removed option to disable CSR counters (via CSR_COUNTERS_USE generic) since these counters are mandatory according to the RISC-V specs; added new IO/peripheral device: custom functions unit (CFU) for tightly-coupled custom co-processors; improved timing of processor-internal clock generator; fixed wrong labels in address space figure and removed dedicated exception vectors box; added mask register to GPIO unit to specify which input pins can trigger a pin-change interrupt |
| 11.09.2020 | 1.4.0.4 | Reworked TRNG architecture and interface; added text regarding fast interrupt channels usage for the NEORV32 processor |
| 02.09.2020 | 1.4.0.2 | |
| 01.09.2020 | 1.4.0.1 | Using registers above x15 when the E extensions is enabled will now correctly cause an illegal instruction exception |
| 29.08.2020 | 🚀1.4.0.0 | Rearranged and reworked data sheet; added FreeRTOS port, demo & short referencing chapter; removed booloader-specific linker scripts – main linker script is used for both, applications and bootloader; bootloader can now have .data and .bss sections; improved IMEM and BOOTROM memory initialization – faster synthesis; image generator now constrains init array size to actual executable size; peripheral/IO devices can only be written in full word mode (= 32-bit); GPIO ports are now 32-bit wide |
| 23.08.2020 | 1.3.7.3 | Added custom mzext CSR to check for available Z* CPU extensions; multiplier's FAST_MUL mode is one cycle faster now; updated performance data |
| 20.08.2020 | 1.3.7.2 | Removed bootloader-specific crt0 – bootloader now uses std crt0; makefiles now also support asm and cpp files; made linker scripts more general; renamed makefile "compile" (which is still available for compatibility) target into "exe" |
| 14.08.2020 | 🚀1.3.7.0 | Simplified CPU fetch engine; added configurable CPU instruction prefetch buffer (ipb) FIFO; optimized CPU execute engine; updated performance data |
| 06.08.2020 | 1.3.6.5 | Added FAST_MUL_EN generic to enable mapping of the multiplier core to DSP blocks; ALU.shifter is no more triggered when executing MULDIV operations; added benchmark results for DSP-based multiplier configurations; updated implementation and performance results; simplified makefiles – using implicit libc definition; crt0 only initializes lowest 16 registers |
| 03.08.2020 | 🚀1.3.6.0 | Relocated DEVNULL (changed base address); minor edits, optimization and clean-ups |
| 30.07.2020 | 1.3.5.2 | Added register stage to PMP mask generation to shorten critical path; removed automatic IRQ enable/disable from RTE install/uninstall functions |
| 30.07.2020 | 1.3.5.1 | misa.Z flag is not yet defined by the RISC-V specs., hence it is read-only and read as zero |
| 29.07.2020 | 1.3.5.0 | Added user privilege level, enabled via new CPU_EXTENSION_RISCV_U generic; mstatus(mpie) logic; implemented RISC-V spec.-compliant Physical Memory Protection (PMP); allows up to 8 regions but only NAPOT mode is supported yet |
| 25.07.2020 | 1.3.0.0 | mcause CSR is read-only now!; removed CLIC, added 4 fast IRQ channels to CPU with according flags in mie and mip and trap IDs; updated core libraries; updated NEORV32 RTE; highly reworked data sheet; updated synthesis and performance results |
| 21.07.2020 | 1.2.0.6 | Added doc section regarding the CPU's data and instruction interfaces; optimized CPU fetch engine; updated iCE40 synthesis results |
| 20.07.2020 | 1.2.0.5 | Less penalty for taken branches and jumps (2 cycles faster) |
| 19.07.2020 | 1.2.0.0 | CPU bus unit now has independent busses for instruction fetch and data access – merged into single processor bus via new bus switch unit; doubled speed of ALU shifter unit again; all bits of mcause CSR can now be modified by application program (full RISC-V-compliant); performance counters CSRs [m]cycleh and [m]instreth are only 20-bit wide; removed NEORV32-specific custom CSRs – all processor-related information can be obtained from the new SYSINFO IO module (CPU is now more independent from processor configuration); changed IO address of DEVNULL; fixed bug in bootloader's trap handler; added USER_CODE generic to assign a custom user code that can be read by software (from SYSINFO) |
| 14.07.2020 | 1.1.0.0 | Added fence_o and fencei_o signals to top entity to show if a fence or fencei instruction is executed; added mvendorid and marchid CSRs (both are always zero); ALU shift unit is faster now; two lowest bits of mtvec are always zero; fixed wrong instruction exception priority; removed HART_ID generic – mhartid CSR is always read as zero; performance counters ([m]cycle[h], [m]instret[h] and time[h]) are also available in embedded mode – but can be explicitly disabled via the CSR_COUNTERS_USE generic; mcause CSR only allows write access to bit 31 and bits 3:0; updated synthesis reports |
| 10.07.2020 | 1.0.6.0 | Non-taken branches are now 1 cycle faster; the time[h] CSR now correctly reflects the system time from the MTIME unit; fixed WFI instruction permanently stalling the CPU; [m]cycle[h] counters now stop counting when CPU is in sleep mode; minstret[h] and mcycle[h] now also allow write-access |
| 09.07.2020 | 1.0.5.0 | X flag of misa CSR is zero now; the default SPI flash boot address of the bootloader is now 0x0080000; new exemplary FPGA utilization results for Intel, Lattice and Xilinx; misa CSR is read-only again, switching compressed extension on/off is pretty bad for the fetch engine; mtval and mcause CSRs now allow write accesses and are finally RISC-V-compliant; time low and high registers of MTIME peripheral can now also be written by user; MTIME registers only allow full-word write accesses |
| 06.07.2020 | 1.0.1.0 | Added missing fence instruction; added new generic to enable optional Zifencei CPU extension for instruction stream synchronization |
| 05.07.2020 | 1.0.0.0 | New CPU architecture: Fetch and execute engines; increased CPI; timer and counter CSRs are now all 64-bit wide; C.LW decompression logic; misa flags C and M are now r/w – compressed mode and multiplier/divider support can be switched on/off during runtime; PC(0) is now always zero; |
| 25.06.2020 | 0.0.2.5 | Added DEVNULL device; added chapter regarding processor simulation; fixed/added links; fixed typos; added FPGA implementation results for iCE40 UP |
| 23.06.2020 | 🚀0.0.2.3 | Publication |