diff --git a/xm_v1_0/rtl/mac/axis2xgmii32.v b/xm_v1_0/rtl/mac/axis2xgmii32.v index 2aeac7c..5ed7186 100644 --- a/xm_v1_0/rtl/mac/axis2xgmii32.v +++ b/xm_v1_0/rtl/mac/axis2xgmii32.v @@ -63,10 +63,10 @@ module axis2xgmii32 ( reg [1:0] r_crc_left; reg [31:0] r_d; reg [3:0] r_c; - reg [ 6:0] r_sequence; - reg [ 6:0] r_sequence_d1; - reg [ 6:0] r_sequence_d2; - reg [ 6:0] r_sequence_d3; + // reg [ 6:0] r_sequence; + // reg [ 6:0] r_sequence_d1; + // reg [ 6:0] r_sequence_d2; + // reg [ 6:0] r_sequence_d3; reg [31:0] r_crc_final; reg [31:0] r_crc_32_4b; @@ -88,34 +88,41 @@ module axis2xgmii32 ( always @(posedge clk_i) begin if(rst_i) begin r_66count <= 'd0; - r_sequence <= 'd0; - r_sequence_d1 <= 'd0; - r_sequence_d2 <= 'd0; - r_sequence_d3 <= 'd0; - r_66b64b_ready <= 1'b0; + // r_sequence <= 'd0; + // r_sequence_d1 <= 'd0; + // r_sequence_d2 <= 'd0; + // r_sequence_d3 <= 'd0; + r_66b64b_ready <= 1'b1; r_start_ready <= 1'b0; end else begin - if(r_66count == 65) begin + if(r_66count == 7'd65) begin r_66count <= 'd0; end else begin r_66count <= r_66count + 'd1; end - r_sequence <= r_66count; - r_sequence_d1 <= r_sequence; - r_sequence_d2 <= r_sequence_d1; - r_sequence_d3 <= r_sequence_d2; - if(r_66count >= 64) begin - r_66b64b_ready <= 1'b0; - end else begin - r_66b64b_ready <= 1'b1; - end - if(r_66count >= 62 && r_66count <= 63) begin - r_start_ready <= 1'b0; + // r_sequence <= r_66count; + // r_sequence_d1 <= r_sequence; + // r_sequence_d2 <= r_sequence_d1; + // r_sequence_d3 <= r_sequence_d2; + + if(r_state == P_IDLE) begin + if(tvalid_i && (r_66count == 7'd63 || r_66count == 7'd64)) begin + r_66b64b_ready <= 1'b0; + end end else begin - r_start_ready <= 1'b1; + r_66b64b_ready <= (r_66count != 7'd63 && r_66count != 7'd64); + if(r_state == P_IPG && r_66b64b_ready && (r_ipg_count == P_IPG_COUNT-1)) begin + r_66b64b_ready <= 1'b1; + end end + // if(r_66count >= 62 && r_66count <= 63) begin + // r_start_ready <= 1'b0; + // end else begin + // r_start_ready <= 1'b1; + // end end end + // assign s_ready = (r_66b64b_ready & r_state_ready & (r_state != P_IDLE)) | (r_state_ready & r_start_ready & r_state == P_IDLE); assign s_ready = r_66b64b_ready & r_state_ready; always @(posedge clk_i) begin @@ -125,12 +132,12 @@ module axis2xgmii32 ( // if(r_66b64b_ready) begin case(r_state) P_IDLE : begin - if(tvalid_i & ~tlast_i & r_state_ready & r_start_ready) begin + if(tvalid_i & ~tlast_i & r_66b64b_ready) begin r_state <= P_START; end end P_START : begin - if(r_start_ready == 1'b1) begin + if(r_66b64b_ready == 1'b1) begin if(tlast_i == 1) begin r_state <= P_PADDING; end else begin @@ -237,26 +244,28 @@ module axis2xgmii32 ( end else begin if(tvalid_i && s_ready) begin if(tlast_i) begin - if(r_input_count >= 60) begin - r_tdata_d1 <= tdata_i; - r_tvldb_d1 <= tvldb_i; - end else begin - r_tvldb_d1 <= 2'd3; - case(tvldb_i) - 2'd0: r_tdata_d1 <= {24'h0, tdata_i[7:0]}; - 2'd1: r_tdata_d1 <= {16'h0, tdata_i[15:0]}; - 2'd2: r_tdata_d1 <= { 8'h0, tdata_i[23:0]}; - 2'd3: r_tdata_d1 <= tdata_i[31:0]; - default : r_tdata_d1 <= 'd0; - endcase - end + r_tdata_d1 <= tdata_i; + r_tvldb_d1 <= tvldb_i; + // if(r_input_count >= 60) begin + // r_tdata_d1 <= tdata_i; + // r_tvldb_d1 <= tvldb_i; + // end else begin + // r_tvldb_d1 <= 2'd3; + // case(tvldb_i) + // 2'd0: r_tdata_d1 <= {24'h0, tdata_i[7:0]}; + // 2'd1: r_tdata_d1 <= {16'h0, tdata_i[15:0]}; + // 2'd2: r_tdata_d1 <= { 8'h0, tdata_i[23:0]}; + // 2'd3: r_tdata_d1 <= tdata_i[31:0]; + // default : r_tdata_d1 <= 'd0; + // endcase + // end end else begin r_tdata_d1 <= tdata_i; r_tvldb_d1 <= 2'd3; end - end else begin - r_tdata_d1 <= 'd0; - r_tvldb_d1 <= 2'd3; + // end else begin + // r_tdata_d1 <= 'd0; + // r_tvldb_d1 <= 2'd3; end end end @@ -267,8 +276,10 @@ module axis2xgmii32 ( r_tvldb_d2 <= 'd0; r_crc_left <= 'd0; end else begin - r_tdata_d2 <= r_tdata_d1; - r_tvldb_d2 <= r_tvldb_d1; + if(r_66b64b_ready) begin + r_tdata_d2 <= r_tdata_d1; + r_tvldb_d2 <= r_tvldb_d1; + end if(r_state == P_CRC) begin r_crc_left <= r_tvldb_d2; end @@ -313,64 +324,66 @@ module axis2xgmii32 ( r_d <= 'd0; r_c <= 'd0; end else begin - case(r_state) - P_IDLE : begin - if(tvalid_i & r_state_ready & r_start_ready & ~tlast_i) begin - r_d <= PREAMBLE_LANE0_D[31:0]; - r_c <= PREAMBLE_LANE0_C[3:0]; - end else begin - r_d <= {4{I}}; + if(r_66b64b_ready) begin + case(r_state) + P_IDLE : begin + if(tvalid_i & ~tlast_i) begin + r_d <= PREAMBLE_LANE0_D[31:0]; + r_c <= PREAMBLE_LANE0_C[3:0]; + end else begin + r_d <= {4{I}}; + r_c <= 4'hf; + end + end + P_START : begin + r_d <= PREAMBLE_LANE0_D[63:32]; + r_c <= PREAMBLE_LANE0_C[7:4]; + end + P_DATA : begin + r_d <= r_tdata_d2; + r_c <= 4'h0; + end + P_PADDING : begin + r_d <= r_tdata_d2; + r_c <= 4'h0; + end + P_END : begin + r_d <= r_tdata_d2; + r_c <= 4'h0; + end + P_CRC : begin + r_c <= 4'h0; + case(r_tvldb_d2) + 2'd0: r_d <= {s_crc_32_1b[23:0],r_tdata_d2[7:0]}; + 2'd1: r_d <= {s_crc_32_2b[15:0],r_tdata_d2[15:0]}; + 2'd2: r_d <= {s_crc_32_3b[7:0],r_tdata_d2[23:0]}; + default: r_d <= r_tdata_d2[31:0]; + endcase + end + P_CRC_1 : begin + // r_d <= s_crc_final; + case(r_crc_left) + 2'd0 : begin r_d <= {{2{I}},T,s_crc_final[7:0]}; r_c <= 4'b1110; end + 2'd1 : begin r_d <= {{{I}},T,s_crc_final[15:0]}; r_c <= 4'b1100; end + 2'd2 : begin r_d <= {T,s_crc_final[23:0]}; r_c <= 4'b1000; end + default : begin r_d <= {s_crc_final[31:0]}; r_c <= 4'b0000; end + endcase + // r_state <= P_IPG; + end + P_IPG : begin r_c <= 4'hf; + if(r_ipg_count == 0 && r_crc_left == 2'd3) begin + r_d <= {{3{I}},T}; + end else begin + r_d <= {4{I}}; + end end - end - P_START : begin - r_d <= PREAMBLE_LANE0_D[63:32]; - r_c <= PREAMBLE_LANE0_C[7:4]; - end - P_DATA : begin - r_d <= r_tdata_d2; - r_c <= 4'h0; - end - P_PADDING : begin - r_d <= r_tdata_d2; - r_c <= 4'h0; - end - P_END : begin - r_d <= r_tdata_d2; - r_c <= 4'h0; - end - P_CRC : begin - r_c <= 4'h0; - case(r_tvldb_d2) - 2'd0: r_d <= {s_crc_32_1b[23:0],r_tdata_d2[7:0]}; - 2'd1: r_d <= {s_crc_32_2b[15:0],r_tdata_d2[15:0]}; - 2'd2: r_d <= {s_crc_32_3b[7:0],r_tdata_d2[23:0]}; - default: r_d <= r_tdata_d2[31:0]; - endcase - end - P_CRC_1 : begin - // r_d <= s_crc_final; - case(r_crc_left) - 2'd0 : begin r_d <= {{2{I}},T,s_crc_final[7:0]}; r_c <= 4'b1110; end - 2'd1 : begin r_d <= {{{I}},T,s_crc_final[15:0]}; r_c <= 4'b1100; end - 2'd2 : begin r_d <= {T,s_crc_final[23:0]}; r_c <= 4'b1000; end - default : begin r_d <= {s_crc_final[31:0]}; r_c <= 4'b0000; end - endcase - // r_state <= P_IPG; - end - P_IPG : begin - r_c <= 4'hf; - if(r_ipg_count == 0 && r_crc_left == 2'd3) begin - r_d <= {{3{I}},T}; - end else begin + default : begin r_d <= {4{I}}; + r_c <= 4'hf; end - end - default : begin - r_d <= {4{I}}; - r_c <= 4'hf; - end - endcase + endcase + end end end @@ -396,7 +409,7 @@ module axis2xgmii32 ( assign tready_o = s_ready; assign xgmii_d_o = r_d; assign xgmii_c_o = r_c; - assign sequence_o = r_sequence_d3; + assign sequence_o = r_66count; endmodule // axis2xgmii32 diff --git a/xm_v1_0/rtl/phy/loopback.v b/xm_v1_0/rtl/mac/loopback.v similarity index 100% rename from xm_v1_0/rtl/phy/loopback.v rename to xm_v1_0/rtl/mac/loopback.v diff --git a/xm_v1_0/rtl/mac/teng_mac.v b/xm_v1_0/rtl/mac/teng_mac.v index 0b34214..5ea61f5 100644 --- a/xm_v1_0/rtl/mac/teng_mac.v +++ b/xm_v1_0/rtl/mac/teng_mac.v @@ -13,11 +13,11 @@ module teng_mac #( parameter P_GEARBOX_LOOPBACK = 1'b0 )( input rx_user_clk_i, - input rx_fsm_reset_done_i, + input rx_ready_i, input [NUMBER_OF_LANES*32-1:0] rx_data_i, //---------------- Transmit Ports - FPGA TX Interface Ports ---------------- input tx_user_clk_i, - input tx_fsm_reset_done_i, + input tx_ready_i, output [NUMBER_OF_LANES*32-1:0] tx_data_o, output [NUMBER_OF_LANES-1:0] link_up_o, @@ -45,10 +45,10 @@ module teng_mac #( `include "xgmii_includes.vh" //************************** Register Declarations **************************** - (* ASYNC_REG = "TRUE" *)reg r_tx_fsm_reset_done_d; - (* ASYNC_REG = "TRUE" *)reg r_tx_fsm_reset_done_d2; - (* ASYNC_REG = "TRUE" *)reg r_rx_fsm_reset_done_d; - (* ASYNC_REG = "TRUE" *)reg r_rx_fsm_reset_done_d2; + (* ASYNC_REG = "TRUE" *)reg r_tx_ready_d; + (* ASYNC_REG = "TRUE" *)reg r_tx_ready_d2; + (* ASYNC_REG = "TRUE" *)reg r_rx_ready_d; + (* ASYNC_REG = "TRUE" *)reg r_rx_ready_d2; // =========================================================================== // register & wire // =========================================================================== @@ -68,31 +68,31 @@ module teng_mac #( // wire [NUMBER_OF_LANES*1-1:0] s_rx_header_valid; - always @(posedge rx_user_clk_i or negedge rx_fsm_reset_done_i) begin - if (!rx_fsm_reset_done_i) begin - r_rx_fsm_reset_done_d <= `DLY 1'b0; - r_rx_fsm_reset_done_d2 <= `DLY 1'b0; + always @(posedge rx_user_clk_i or negedge rx_ready_i) begin + if (!rx_ready_i) begin + r_rx_ready_d <= `DLY 1'b0; + r_rx_ready_d2 <= `DLY 1'b0; end else begin - r_rx_fsm_reset_done_d <= `DLY rx_fsm_reset_done_i; - r_rx_fsm_reset_done_d2 <= `DLY r_rx_fsm_reset_done_d; + r_rx_ready_d <= `DLY rx_ready_i; + r_rx_ready_d2 <= `DLY r_rx_ready_d; end end - always @(posedge tx_user_clk_i or negedge tx_fsm_reset_done_i) begin - if (!tx_fsm_reset_done_i) begin - r_tx_fsm_reset_done_d <= `DLY 1'b0; - r_tx_fsm_reset_done_d2 <= `DLY 1'b0; + always @(posedge tx_user_clk_i or negedge tx_ready_i) begin + if (!tx_ready_i) begin + r_tx_ready_d <= `DLY 1'b0; + r_tx_ready_d2 <= `DLY 1'b0; end else begin - r_tx_fsm_reset_done_d <= `DLY tx_fsm_reset_done_i; - r_tx_fsm_reset_done_d2 <= `DLY r_tx_fsm_reset_done_d; + r_tx_ready_d <= `DLY tx_ready_i; + r_tx_ready_d2 <= `DLY r_tx_ready_d; end end - assign rx_user_rst_o = ~r_rx_fsm_reset_done_d2; - assign tx_user_rst_o = ~r_tx_fsm_reset_done_d2; + assign rx_user_rst_o = ~r_rx_ready_d2; + assign tx_user_rst_o = ~r_tx_ready_d2; // assign tx_user_clk_o = tx_user_clk_i; - // assign tx_user_rst_o = ~r_tx_fsm_reset_done_d2; + // assign tx_user_rst_o = ~r_tx_ready_d2; generate genvar i; @@ -117,7 +117,7 @@ module teng_mac #( tx u_tx ( // Clks and resets .clk_i (tx_user_clk_i), - .rst_i (~r_tx_fsm_reset_done_d2), + .rst_i (~r_tx_ready_d2), // XGMII .data_o (s_tx_data), @@ -139,7 +139,7 @@ module teng_mac #( // Clks and resets .clk_i (tx_user_clk_i), - .rst_i (~r_tx_fsm_reset_done_d2), + .rst_i (~r_tx_ready_d2), .data_i (s_tx_data), .head_i (s_tx_header[1:0]), @@ -158,12 +158,12 @@ module teng_mac #( // endgenerate // assign rx_user_clk_o = rx_user_clk_i; - // assign rx_user_rst_o = ~r_rx_fsm_reset_done_d2; + // assign rx_user_rst_o = ~r_rx_ready_d2; gearbox_64b_66b u_gearbox_64_66 ( // Clks and resets .clk_i (rx_user_clk_i), - .rst_i (~r_rx_fsm_reset_done_d2), + .rst_i (~r_rx_ready_d2), .data_o (s_gb_rx_data), .head_o (s_gb_rx_head), @@ -209,7 +209,7 @@ module teng_mac #( rx u_rx ( // Clks and resets .clk_i (rx_user_clk_i), - .rst_i (~r_rx_fsm_reset_done_d2), + .rst_i (~r_rx_ready_d2), // PCS .data_i (s_rx_data), diff --git a/xm_v1_0/rtl/mac/xgmii2axis32.v b/xm_v1_0/rtl/mac/xgmii2axis32.v index dd2f815..fe57c77 100644 --- a/xm_v1_0/rtl/mac/xgmii2axis32.v +++ b/xm_v1_0/rtl/mac/xgmii2axis32.v @@ -307,7 +307,7 @@ module xgmii2axis32 ( assign bad_frames_o = r_bad_frames; assign tdata_o = r_tdata_d2; - assign tvldb_o = r_tvldb_d2; + assign tvldb_o = r_tvldb_d1; assign tvalid_o = r_tvalid_d2 & s_xgmii_valid; assign tlast_o = r_tlast_d1 | s_first_byte_tchar; assign tuser_o = r_tuser_d1; diff --git a/xm_v1_0/sim/mac/sim.do b/xm_v1_0/sim/mac/sim.do new file mode 100644 index 0000000..5812d4c --- /dev/null +++ b/xm_v1_0/sim/mac/sim.do @@ -0,0 +1,40 @@ +## +## By David +## +## 2019.4.17 +##//////////////////////////////////////////////////////////////////////////// + +vlib work +vmap work work + +vlog -work work +incdir+../../rtl/include ../../rtl/mac/teng_mac.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/decode_64b_66b.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/descramble.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/encode_64b_66b.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/scramble.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/rx_alignment.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/axis2xgmii32.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/xgmii2axis32.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/rx.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/tx.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/gearbox_64b_66b.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/gearbox_66b_64b.v +vlog -work work +incdir+../../rtl/include ../../rtl/mac/loopback.v + +vlog -sv -work work ../normal_pkg.sv +vlog -sv -work work ../stream_pkg.sv +vlog -sv -work work ./tb_mac_loopback.sv + + +vsim -voptargs="+acc" -lib work work.tb_mac_loopback + +do wave.do + +set NumericStdNoWarnings 1 +set StdArithNoWarnings 1 + +view wave +view structure +view signals + +run -a diff --git a/xm_v1_0/sim/mac/tb_mac_loopback.sv b/xm_v1_0/sim/mac/tb_mac_loopback.sv new file mode 100644 index 0000000..38222b8 --- /dev/null +++ b/xm_v1_0/sim/mac/tb_mac_loopback.sv @@ -0,0 +1,181 @@ +// +// By David +// +// 2019.4.17 +////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + +import normal_pkg::*; +import stream_pkg::*; + +module tb_mac_loopback(); + + parameter SIM_NUM_OF_PACKETS = 100; + + parameter NUMBER_OF_LANES = 1; + parameter P_SCRAMBLE_LOOPBACK = 1'b0; + parameter P_GEARBOX_LOOPBACK = 1'b0; + + logic s_user_clk; // 156.25*2 clk + logic s_user_ready; + logic [31:0] s_pma_rx_data; + logic [31:0] s_pma_tx_data; + + logic [ 0:0] s_link_up; + logic [ 0:0] s_tx_status; + logic [ 0:0] s_tx_rsp_valid; + + logic s_tx_user_rst; // sync to user_clk_o + logic s_rx_user_rst; // sync to user_clk_o + + + stream #(32) mac_tx(s_user_clk); + stream #(32) mac_rx(s_user_clk); + + teng_mac #( + .NUMBER_OF_LANES (NUMBER_OF_LANES ), + .P_SCRAMBLE_LOOPBACK (P_SCRAMBLE_LOOPBACK ), + .P_GEARBOX_LOOPBACK (P_GEARBOX_LOOPBACK ) + )u_teng_mac( + .rx_user_clk_i (s_user_clk), + .rx_ready_i (s_user_ready), + .rx_data_i (s_pma_rx_data), + //---------------- Transmit Ports - FPGA TX Interface Ports ---------------- + .tx_user_clk_i (s_user_clk), + .tx_ready_i (s_user_ready), + .tx_data_o (s_pma_tx_data), + + .link_up_o (s_link_up), + // AXIS tx + // input tx_user_clk_i, + .tx_user_rst_o (s_tx_user_rst), + .tx_data_i (mac_tx.data), + .tx_vldb_i (mac_tx.vldb), + .tx_valid_i (mac_tx.valid), + .tx_ready_o (mac_tx.ready), + .tx_last_i (mac_tx.eop), + .tx_user_i (mac_tx.user), + + .tx_status_o (s_tx_status), + .tx_rsp_valid_o (s_tx_rsp_valid), + // AXIS rx + // input rx_user_clk_i, + .rx_user_rst_o (s_rx_user_rst), + .rx_data_o (mac_rx.data), + .rx_vldb_o (mac_rx.vldb), + .rx_valid_o (mac_rx.valid), + .rx_last_o (mac_rx.eop), + .rx_user_o (mac_rx.user) + ); + + + assign mac_rx.ready = 1'b1; + + initial begin + s_user_clk = 1'b0; + s_user_ready = 1'b0; + #100; + s_user_ready = 1'b1; + end + always #5 s_user_clk = ~s_user_clk; + + assign s_pma_rx_data = s_pma_tx_data; + + reg r_global_rst; + always @(posedge s_user_clk) begin + if(s_tx_user_rst | s_rx_user_rst | ~s_link_up) begin + r_global_rst <= 1'b1; + end else begin + r_global_rst <= 1'b0; + end + end + + reg r_mac_rx_sop; + always @(posedge s_user_clk) begin + if(s_rx_user_rst) begin + r_mac_rx_sop <= 1'b1; + end else begin + if(mac_rx.valid) begin + if(mac_rx.eop) begin + r_mac_rx_sop <= 1'b1; + end else begin + r_mac_rx_sop <= 1'b0; + end + end + end + end + assign mac_rx.sop = r_mac_rx_sop; + + StreamMasterBfm #(32) mac_master; + StreamSlaveBfm #(32) mac_slave; + + q_pkt_t q_check_bytes; + q_int_t q_check_len; + + + initial begin + mac_master = new(mac_tx); + mac_slave = new(mac_rx); + + mac_master.init(); + mac_slave.init(); + #100; + @(negedge r_global_rst); + #1us; + + fork + begin : tx + q_pkt_t q_packet; + int packet_len; + packet_len = 59; + repeat(SIM_NUM_OF_PACKETS) begin + packet_len = packet_len + 1; + // packet_len = random_between(60, 1514); + + q_packet = {}; + repeat(packet_len) begin + q_packet.push_back(ramdom_bytes()); + end + + q_check_bytes = {q_check_bytes, q_packet}; + q_check_len.push_back(q_packet.size()); + mac_master.write(q_packet); + + end + end + + begin : rx + q_pkt_t q_packet; + int packet_len; + int check_len; + logic [7:0] expect_bytes; + logic [7:0] actual_bytes; + for(int j = 0; j < SIM_NUM_OF_PACKETS; j = j + 1) begin + mac_slave.read(q_packet); + packet_len = q_packet.size(); + check_len = q_check_len.pop_front(); + assert(packet_len == check_len) + else begin + $error("receive packet length error, packet is %x, expect is %x, actual is %x", j, check_len, packet_len); + $stop; + end + for(int i = 0; i < packet_len; i = i + 1) begin + expect_bytes = q_check_bytes.pop_front(); + actual_bytes = q_packet.pop_front(); + assert (expect_bytes == actual_bytes) + else begin + $error("receive bytes error, packet is %x, offset is %x, expect is %x, actual is %x", j, i, expect_bytes, actual_bytes); + $stop; + end + end + end + end + join + + #5us; + $display("sim done"); + $stop; + end + +endmodule \ No newline at end of file diff --git a/xm_v1_0/sim/mac/wave.do b/xm_v1_0/sim/mac/wave.do new file mode 100644 index 0000000..12bd403 --- /dev/null +++ b/xm_v1_0/sim/mac/wave.do @@ -0,0 +1,199 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_user_clk_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_ready_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_data_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_user_clk_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_ready_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_data_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/link_up_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_user_rst_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_data_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_vldb_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_valid_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_ready_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_last_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_user_i +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_status_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/tx_rsp_valid_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_user_rst_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_data_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_vldb_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_valid_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_last_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/rx_user_o +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/r_tx_ready_d +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/r_tx_ready_d2 +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/r_rx_ready_d +add wave -noupdate -group mac /tb_mac_loopback/u_teng_mac/r_rx_ready_d2 +add wave -noupdate -group tb_top /tb_mac_loopback/s_user_clk +add wave -noupdate -group tb_top /tb_mac_loopback/s_user_ready +add wave -noupdate -group tb_top /tb_mac_loopback/s_pma_rx_data +add wave -noupdate -group tb_top /tb_mac_loopback/s_pma_tx_data +add wave -noupdate -group tb_top /tb_mac_loopback/s_link_up +add wave -noupdate -group tb_top /tb_mac_loopback/s_tx_status +add wave -noupdate -group tb_top /tb_mac_loopback/s_tx_rsp_valid +add wave -noupdate -group tb_top /tb_mac_loopback/s_tx_user_rst +add wave -noupdate -group tb_top /tb_mac_loopback/s_rx_user_rst +add wave -noupdate -group tb_top /tb_mac_loopback/r_global_rst +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/clk_i} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/rst_i} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/data_o} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/head_o} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/sequence_o} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/tdata_i} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/tvldb_i} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/tvalid_i} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/tready_o} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/tlast_i} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/tuser_i} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/tx_status_o} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/tx_rsp_valid_o} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_xgmii_d} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_xgmii_c} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_xgmii_d} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_xgmii_c} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_xgmii_txd_64} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_xgmii_txc_64} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_xgmii_txd_vld_64} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_encode_data} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_encode_head} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_encode_data_vld} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_encode_error} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_tx_scrambled_data} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_tx_scrambled_head} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_tx_scrambled_valid} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/s_sequence} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_sequence_d1} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_sequence_d2} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_sequence_d3} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_sequence_d4} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_sequence_d5} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_data} +add wave -noupdate -group tx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/r_head} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/clk_i} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/rst_i} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/data_i} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/head_i} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/head_valid_i} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/slip_o} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/tdata_o} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/tvldb_o} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/tvalid_o} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/tlast_o} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/tuser_o} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/link_up_o} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_rx_lane_locked} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/r_data} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/r_head} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_rx_descrambled_data} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_rx_descrambled_head} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_rx_descrambled_data_rev} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_rx_descrambled_head_rev} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/r_rx_descrambled_valid} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_decode_data} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_decode_head} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_decode_data_vld} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_decode_error} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_xgmii_rxd_64} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_xgmii_rxc_64} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/s_xgmii_rxd_vld_64} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/r_xgmii_rxd_vld_64} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/r_xgmii_d_32} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/r_xgmii_c_32} +add wave -noupdate -group rx {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/r_xgmii_v_32} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/clk_i} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/rst_i} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/good_frames_o} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/bad_frames_o} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/xgmii_d_i} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/xgmii_c_i} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/xgmii_v_i} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/tdata_o} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/tvldb_o} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/tvalid_o} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/tlast_o} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/tuser_o} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/s_xgmii_valid} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_state} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_tdata_d1} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_tvldb_d1} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_tvalid_d1} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_tlast_d1} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_tuser_d1} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/s_first_byte_tchar} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_tdata_d2} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_tvldb_d2} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_tvalid_d2} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/s_d} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/s_c} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_d} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_c} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_crc_32} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_crc_32_3b} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_crc_32_2b} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_crc_32_1b} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/s_crc_32_4b} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/s_crc_32_3b} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/s_crc_32_2b} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/s_crc_32_1b} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_good_frames} +add wave -noupdate -group xgmii2axi32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_rx/u_xgmii2axis32/r_bad_frames} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/clk_i} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/rst_i} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/xgmii_d_o} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/xgmii_c_o} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/sequence_o} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/tdata_i} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/tvldb_i} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/tvalid_i} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/tready_o} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/tlast_i} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/tuser_i} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/tx_status_o} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/tx_rsp_valid_o} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_66count} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_66b64b_ready} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_start_ready} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_state} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_state_ready} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/s_ready} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_input_count} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_ipg_count} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_tdata_d1} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_tvldb_d1} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_tdata_d2} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_tvldb_d2} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_crc_left} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_d} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_c} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_crc_final} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_crc_32_4b} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_crc_32_3b} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_crc_32_2b} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/r_crc_32_1b} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/s_crc_final} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/s_crc_32_4b} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/s_crc_32_3b} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/s_crc_32_2b} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/s_crc_32_1b} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/xgmii_d} +add wave -noupdate -expand -group axis2xgmii32 {/tb_mac_loopback/u_teng_mac/g_mac[0]/u_tx/u_axis2xgmii32/xgmii_c} +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {159655543 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 191 +configure wave -valuecolwidth 199 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {159552991 ps} {159776801 ps} diff --git a/xm_v1_0/sim/normal_pkg.sv b/xm_v1_0/sim/normal_pkg.sv new file mode 100644 index 0000000..30d792e --- /dev/null +++ b/xm_v1_0/sim/normal_pkg.sv @@ -0,0 +1,55 @@ + + +package normal_pkg; + + typedef logic [7:0] q_pkt_t[$]; + typedef int q_int_t[$]; + + + function q_pkt_t string2bq; + input string string_in; + automatic q_pkt_t q = {}; + automatic integer len = 0; + automatic integer i = 0; + begin + len = string_in.len(); + if(string_in.len() % 2 != 0) begin + $display("error : function string2bq input string is not even , len is %d", string_in.len() ); + return q; + end + while(i < len/2) begin + q.push_back(string_in.substr(i*2,i*2+1).atohex()); + i = i + 1; + end + return q; + end + endfunction + + function int ramdom_int(); + begin + ramdom_int = {$random}; + end + endfunction + + function logic [7:0] ramdom_bytes(); + begin + ramdom_bytes = {$random} % 256; + end + endfunction + + function int random_between(int min, int max); + begin + random_between = min+{$random}%(max-min+1); + end + endfunction + + function integer clog2( + input integer data_i + ); + begin + for (clog2 = 0; data_i > 0; clog2 = clog2 + 1) + data_i = data_i >> 1; + end + endfunction + +endpackage diff --git a/xm_v1_0/sim/stream_pkg.sv b/xm_v1_0/sim/stream_pkg.sv new file mode 100644 index 0000000..3fd7925 --- /dev/null +++ b/xm_v1_0/sim/stream_pkg.sv @@ -0,0 +1,197 @@ + +package stream_pkg; + import normal_pkg::*; + + class StreamMasterBfm #(int DATA_WIDTH = 64); + virtual stream.master #(DATA_WIDTH) tx_ck; + + function new(virtual stream.master #(DATA_WIDTH) tx_ck); + this.tx_ck = tx_ck; + endfunction + + task write(input q_pkt_t q_payload); + logic [DATA_WIDTH-1:0] buf_data; + integer length; + + // $display("%t, mac tx start", $time); + length = q_payload.size(); + if(length <= 0) begin + return; + end + // @(posedge tx_ck.clk); + @(this.tx_ck.driver_cb) begin + if(length > DATA_WIDTH/8) begin + for(int i = 0; i < DATA_WIDTH/8 ; i = i + 1) begin + buf_data[i*8 +: 8] = q_payload[i]; + end + // ##0 + tx_ck.driver_cb.valid <= 1'b1; + tx_ck.driver_cb.data <= buf_data; + tx_ck.driver_cb.vldb <= DATA_WIDTH/8-1; + tx_ck.driver_cb.sop <= 1'b1; + tx_ck.driver_cb.eop <= 1'b0; + end else begin + buf_data = 64'h0; + for(int i = 0; i < length ; i = i + 1) begin + buf_data[i*8 +: 8] = q_payload[i]; + end + // ##0 + tx_ck.driver_cb.valid <= 1'b1; + tx_ck.driver_cb.data <= buf_data; + tx_ck.driver_cb.vldb <= length - 1; + tx_ck.driver_cb.sop <= 1'b1; + tx_ck.driver_cb.eop <= 1'b1; + end + end + while(length > 0) begin + // do + // @(this.tx_ck.driver_cb); + // while(!tx_ck.driver_cb.ready); + @(this.tx_ck.driver_cb) begin + if(tx_ck.driver_cb.ready) begin + // tx_ck.driver_cb.valid <= 1'b0; + // if(($random%100) > 50) begin + // @(this.tx_ck.driver_cb); + // end + if(length > DATA_WIDTH/8) begin + repeat(DATA_WIDTH/8) begin + q_payload.pop_front(); + end + length -= DATA_WIDTH/8; + end else begin + q_payload.delete(); + length = 0; + break; + end + if(length > DATA_WIDTH/8) begin + for(int i = 0; i < DATA_WIDTH/8 ; i = i + 1) begin + buf_data[i*8 +: 8] = q_payload[i]; + end + // ##0 + tx_ck.driver_cb.valid <= 1'b1; + tx_ck.driver_cb.data <= buf_data; + tx_ck.driver_cb.vldb <= DATA_WIDTH/8-1; + tx_ck.driver_cb.sop <= 1'b0; + tx_ck.driver_cb.eop <= 1'b0; + end else begin + buf_data = 64'h0102030405060708; + for(int i = 0; i < length ; i = i + 1) begin + buf_data[i*8 +: 8] = q_payload[i]; + end + // ##0 + tx_ck.driver_cb.valid <= 1'b1; + tx_ck.driver_cb.data <= buf_data; + tx_ck.driver_cb.vldb <= length - 1; + tx_ck.driver_cb.sop <= 1'b0; + tx_ck.driver_cb.eop <= 1'b1; + end + end + end + end + tx_ck.driver_cb.valid <= 1'b0; + tx_ck.driver_cb.data <= 'b0; + tx_ck.driver_cb.vldb <= 'b0; + tx_ck.driver_cb.sop <= 1'b0; + tx_ck.driver_cb.eop <= 1'b0; + // $display("%t, mac tx end", $time); + endtask //write + + task init(); + tx_ck.driver_cb.valid <= 1'b0; + tx_ck.driver_cb.data <= 'b0; + tx_ck.driver_cb.vldb <= 'b0; + tx_ck.driver_cb.sop <= 1'b0; + tx_ck.driver_cb.eop <= 1'b0; + tx_ck.driver_cb.user <= 1'b0; + endtask //init + + task idle(int unsigned cycles); + repeat(cycles) + @(this.tx_ck.driver_cb); + endtask //idle + endclass + + class StreamSlaveBfm #(int DATA_WIDTH = 64); + virtual stream.slave #(DATA_WIDTH) rx_ck; + + function new(virtual stream.slave #(DATA_WIDTH) rx_ck); + this.rx_ck = rx_ck; + endfunction + + task read(output q_pkt_t q_payload); + q_pkt_t this_packet_q; + @(this.rx_ck.mon_cb); + rx_ck.mon_cb.ready <= 1'b1; + while(1) begin + // ## 1; + @(this.rx_ck.mon_cb) begin + if(rx_ck.mon_cb.valid) begin + // if(rx_ck.mon_cb.valid & rx_ck.mon_cb.ready) begin + if(rx_ck.mon_cb.sop) begin + this_packet_q = {}; + end else begin + end + for(int i = 0; i <= rx_ck.mon_cb.vldb; i = i + 1) begin + this_packet_q.push_back(rx_ck.mon_cb.data[i*8 +: 8]); + end + if(rx_ck.mon_cb.eop) begin + q_payload = this_packet_q; + rx_ck.mon_cb.ready <= 1'b0; + break; + end + end + end + end + endtask //read + + task init(); + rx_ck.mon_cb.ready <= 1'b0; + endtask //init + + task idle(int unsigned cycles); + repeat(cycles) + @(this.rx_ck.mon_cb); + endtask //idle + endclass + +endpackage + +interface stream #(parameter DATA_WIDTH = 64) + (input bit clk); + import normal_pkg::*; + // parameter DATA_WIDTH = 64; + localparam DATA_BE_BIT = clog2(DATA_WIDTH/8 - 1); + // localparam DATA_BE_BIT = `_bit_width(DATA_WIDTH/8 - 1); + wire valid; + wire [DATA_WIDTH-1:0] data; + wire [DATA_BE_BIT-1:0] vldb; + wire sop; + wire eop; + wire user; + wire ready; + + clocking driver_cb @(posedge clk); + output valid, data, vldb, sop, eop, user; + input ready; + endclocking + + clocking mon_cb @(posedge clk); + input valid, data, vldb, sop, eop, user; + output ready; + endclocking + + modport slave( + // input valid, data, vldb, sop, eop, clk, + // output ready + clocking mon_cb + ); + + modport master( + // output valid, data, vldb, sop, eop, clk, + // input ready + clocking driver_cb + ); + + + // MacContreteBfm bfm = new; +endinterface //stream \ No newline at end of file