From dea849271cd69ea724863e291bc641a1840e6ad3 Mon Sep 17 00:00:00 2001 From: jack_mac Date: Mon, 18 Mar 2019 21:51:34 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0prbs=E4=BB=BF=E7=9C=9F?= =?UTF-8?q?=EF=BC=8C=E5=A4=84=E7=90=86=E6=8E=89=E4=B8=A4=E4=B8=AAbug?= =?UTF-8?q?=EF=BC=9A=201=E3=80=81axis2xgmii32.v=E9=87=8C=E9=9D=A2=E7=94=B1?= =?UTF-8?q?=E4=BA=8E=E8=BE=93=E5=87=BA=E6=95=B0=E6=8D=AE=E9=9C=80=E8=A6=81?= =?UTF-8?q?=E6=AF=8F66=E4=B8=AA=E6=97=B6=E9=92=9F=E6=9A=82=E5=81=9C2?= =?UTF-8?q?=E4=B8=AA=E6=97=B6=E9=92=9F=EF=BC=8C=E6=89=80=E4=BB=A5=E5=9C=A8?= =?UTF-8?q?=E8=AF=BB=E5=85=A5=E6=95=B0=E6=8D=AE=E7=9A=84=E6=97=B6=E5=80=99?= =?UTF-8?q?=E8=A6=81=E6=8F=90=E5=89=8D=E6=8E=A7=E5=88=B6=E4=B8=80=E4=B8=8B?= =?UTF-8?q?=EF=BC=9B=202=E3=80=81xgmii2axis32.v=E9=87=8C=E9=9D=A2=E4=B9=9F?= =?UTF-8?q?=E6=98=AF=E5=A4=84=E7=90=86~xgmii=5Fvalid=E6=97=B6=EF=BC=8C?= =?UTF-8?q?=E5=AF=BC=E8=87=B4last=E4=BF=A1=E5=8F=B7=E6=97=A0=E6=B3=95?= =?UTF-8?q?=E6=9C=89=E6=95=88=E8=BE=93=E5=87=BA=E3=80=82(DATA,CRC,IDLE,IDL?= =?UTF-8?q?E,T)=E8=BF=99=E7=A7=8D=E6=83=85=E5=86=B5last=E4=BF=A1=E5=8F=B7?= =?UTF-8?q?=E8=BE=93=E5=87=BA=E6=9C=89=E9=97=AE=E9=A2=98=E3=80=82=20IDLE?= =?UTF-8?q?=E6=8C=87xgmii=E9=9D=9Evalid=20#6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- gth_no_buffer_with_gearbox/rtl/axis2xgmii32.v | 66 ++- gth_no_buffer_with_gearbox/rtl/xgmii2axis32.v | 28 +- gtx/rtl/pcs_top.v | 382 +++++++++++------- gtx/rtl/prbs_check.v | 14 +- gtx/rtl/prbs_test.v | 12 +- gtx/sim/prbs_wave.do | 189 +++++++-- gtx/sim/tb_prbs_loopback.sv | 12 +- 7 files changed, 496 insertions(+), 207 deletions(-) diff --git a/gth_no_buffer_with_gearbox/rtl/axis2xgmii32.v b/gth_no_buffer_with_gearbox/rtl/axis2xgmii32.v index 5d0a47d..2aeac7c 100644 --- a/gth_no_buffer_with_gearbox/rtl/axis2xgmii32.v +++ b/gth_no_buffer_with_gearbox/rtl/axis2xgmii32.v @@ -47,6 +47,7 @@ module axis2xgmii32 ( ******************************************************************************/ reg [6:0] r_66count; reg r_66b64b_ready; + reg r_start_ready; reg [P_STATE_WIDTH-1:0] r_state = P_IDLE; reg r_state_ready; @@ -92,6 +93,7 @@ module axis2xgmii32 ( r_sequence_d2 <= 'd0; r_sequence_d3 <= 'd0; r_66b64b_ready <= 1'b0; + r_start_ready <= 1'b0; end else begin if(r_66count == 65) begin r_66count <= 'd0; @@ -107,6 +109,11 @@ module axis2xgmii32 ( end else begin r_66b64b_ready <= 1'b1; end + if(r_66count >= 62 && r_66count <= 63) begin + r_start_ready <= 1'b0; + end else begin + r_start_ready <= 1'b1; + end end end assign s_ready = r_66b64b_ready & r_state_ready; @@ -115,55 +122,67 @@ module axis2xgmii32 ( if(rst_i) begin r_state <= P_IDLE; end else begin - if(r_66b64b_ready) begin + // if(r_66b64b_ready) begin case(r_state) P_IDLE : begin - if(tvalid_i & r_state_ready & ~tlast_i) begin + if(tvalid_i & ~tlast_i & r_state_ready & r_start_ready) begin r_state <= P_START; end end P_START : begin - // if(tvalid_i == 1'b1) begin + if(r_start_ready == 1'b1) begin if(tlast_i == 1) begin r_state <= P_PADDING; end else begin r_state <= P_DATA; end - // end + end end P_DATA : begin - if(tlast_i == 1) begin - if(r_input_count >= 56) begin - r_state <= P_END; - end else begin - r_state <= P_PADDING; + if(r_66b64b_ready) begin + if(tlast_i == 1) begin + if(r_input_count >= 56) begin + r_state <= P_END; + end else begin + r_state <= P_PADDING; + end end end end P_PADDING : begin - if(r_input_count >= 56) begin - r_state <= P_CRC; + if(r_66b64b_ready) begin + if(r_input_count >= 56) begin + r_state <= P_CRC; + end end end P_END : begin - r_state <= P_CRC; + if(r_66b64b_ready) begin + r_state <= P_CRC; + end end P_CRC : begin - r_state <= P_CRC_1; + if(r_66b64b_ready) begin + r_state <= P_CRC_1; + end end P_CRC_1 : begin - r_state <= P_IPG; + if(r_66b64b_ready) begin + r_state <= P_IPG; + end end P_IPG : begin - if(r_ipg_count == P_IPG_COUNT-1) begin - r_state <= P_IDLE; + if(r_66b64b_ready) begin + if(r_ipg_count == P_IPG_COUNT-1) begin + r_state <= P_IDLE; + end end end default : begin r_state <= P_IDLE; end endcase - end + // end end end @@ -174,7 +193,11 @@ module axis2xgmii32 ( if(r_state == P_IDLE && tvalid_i && s_ready && ~tlast_i) begin r_input_count <= 'd4; end else if(r_state == P_START || r_state == P_DATA || r_state == P_PADDING) begin - r_input_count <= r_input_count + 'd4; + if(tvalid_i && s_ready) begin + if(r_input_count < 56) begin + r_input_count <= r_input_count + 'd4; + end + end end else begin r_input_count <= 'd0; end @@ -292,7 +315,7 @@ module axis2xgmii32 ( end else begin case(r_state) P_IDLE : begin - if(tvalid_i & r_state_ready & ~tlast_i) begin + if(tvalid_i & r_state_ready & r_start_ready & ~tlast_i) begin r_d <= PREAMBLE_LANE0_D[31:0]; r_c <= PREAMBLE_LANE0_C[3:0]; end else begin @@ -333,7 +356,7 @@ module axis2xgmii32 ( 2'd2 : begin r_d <= {T,s_crc_final[23:0]}; r_c <= 4'b1000; end default : begin r_d <= {s_crc_final[31:0]}; r_c <= 4'b0000; end endcase - r_state <= P_IPG; + // r_state <= P_IPG; end P_IPG : begin r_c <= 4'hf; @@ -344,7 +367,8 @@ module axis2xgmii32 ( end end default : begin - r_state <= P_IDLE; + r_d <= {4{I}}; + r_c <= 4'hf; end endcase end diff --git a/gth_no_buffer_with_gearbox/rtl/xgmii2axis32.v b/gth_no_buffer_with_gearbox/rtl/xgmii2axis32.v index 8a0d13a..dd2f815 100644 --- a/gth_no_buffer_with_gearbox/rtl/xgmii2axis32.v +++ b/gth_no_buffer_with_gearbox/rtl/xgmii2axis32.v @@ -47,6 +47,7 @@ module xgmii2axis32 ( reg r_tlast_d1; reg [0:0] r_tuser_d1; + wire s_first_byte_tchar; reg [31:0] r_tdata_d2; reg [1:0] r_tvldb_d2; reg r_tvalid_d2; @@ -126,6 +127,7 @@ module xgmii2axis32 ( end // not rst_i end //always + assign s_first_byte_tchar = (s_c == 4'b1111) && (is_tchar(s_d[7:0])); always @(posedge clk_i) begin if(rst_i) begin r_good_frames <= 'b0; @@ -244,12 +246,12 @@ module xgmii2axis32 ( r_tuser_d1 <= 'd0; end endcase - end else begin - r_tdata_d1 <= 'd0; - r_tvldb_d1 <= 'd0; - r_tvalid_d1 <= 'd0; - r_tlast_d1 <= 'd0; - r_tuser_d1 <= 'd0; + // end else begin + // r_tdata_d1 <= 'd0; + // r_tvldb_d1 <= 'd0; + // r_tvalid_d1 <= 'd0; + // r_tlast_d1 <= 'd0; + // r_tuser_d1 <= 'd0; end end end @@ -261,9 +263,11 @@ module xgmii2axis32 ( r_tvldb_d2 <= 'd0; r_tvalid_d2 <= 'd0; end else begin // not rst_i - r_tdata_d2 <= r_tdata_d1; - r_tvldb_d2 <= r_tvldb_d1; - if(r_tlast_d1 & r_tvalid_d1) begin + if(s_xgmii_valid) begin + r_tdata_d2 <= r_tdata_d1; + r_tvldb_d2 <= r_tvldb_d1; + end + if((r_tlast_d1 & r_tvalid_d1) | (s_first_byte_tchar)) begin r_tvalid_d2 <= 1'b0; end else begin r_tvalid_d2 <= r_tvalid_d1; @@ -291,7 +295,7 @@ module xgmii2axis32 ( end end end - + assign s_crc_32_4b = ~crc_rev(r_crc_32); assign s_crc_32_3b = ~crc_rev(r_crc_32_3b); assign s_crc_32_2b = ~crc_rev(r_crc_32_2b); @@ -304,7 +308,7 @@ module xgmii2axis32 ( assign tdata_o = r_tdata_d2; assign tvldb_o = r_tvldb_d2; - assign tvalid_o = r_tvalid_d2; - assign tlast_o = r_tlast_d1; + assign tvalid_o = r_tvalid_d2 & s_xgmii_valid; + assign tlast_o = r_tlast_d1 | s_first_byte_tchar; assign tuser_o = r_tuser_d1; endmodule // xgmii2axis32 \ No newline at end of file diff --git a/gtx/rtl/pcs_top.v b/gtx/rtl/pcs_top.v index e68fb88..8f2ee31 100644 --- a/gtx/rtl/pcs_top.v +++ b/gtx/rtl/pcs_top.v @@ -1,26 +1,26 @@ //////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx // \ \ \/ Version : 3.6 -// \ \ Application : 7 Series FPGAs Transceivers Wizard +// \ \ Application : 7 Series FPGAs Transceivers Wizard // / / Filename : gtwizard_0_exdes.v -// /___/ /\ -// \ \ / \ -// \___\/\___\ +// /___/ /\ +// \ \ / \ +// \___\/\___\ // // // Module gtwizard_0_exdes // Generated by Xilinx 7 Series FPGAs Transceivers Wizard -// -// +// +// // (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. -// +// // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. -// +// // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as @@ -42,7 +42,7 @@ // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. -// +// // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe @@ -56,22 +56,25 @@ // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. -// +// // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. +// PART OF THIS FILE AT ALL TIMES. `timescale 1ns / 1ps `define DLY #1 -(* DowngradeIPIdentifiedWarnings="yes" *) +//(* DowngradeIPIdentifiedWarnings="yes" *) //***********************************Entity Declaration************************ -(* CORE_GENERATION_INFO = "gtwizard_0,gtwizard_v3_6_9,{protocol_file=Start_from_scratch}" *) +//(* CORE_GENERATION_INFO = "gtwizard_0,gtwizard_v3_6_9,{protocol_file=Start_from_scratch}" *) module pcs_top # ( parameter EXAMPLE_CONFIG_INDEPENDENT_LANES = 1,//configuration for frame gen and check parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "TRUE", // simulation setting for GT SecureIP model - parameter STABLE_CLOCK_PERIOD = 16 + parameter STABLE_CLOCK_PERIOD = 16, + + parameter P_SCRAMBLE_LOOPBACK = 1'b0, + parameter P_GEARBOX_LOOPBACK = 1'b0 ) ( @@ -84,7 +87,7 @@ module pcs_top # input wire gthrxp_i, output wire gthtxn_o, output wire gthtxp_o, - + // User-provided ports for reset helper block(s) input wire hb_gtwiz_reset_clk_freerun_in, input wire hb_gtwiz_reset_all_in, @@ -116,8 +119,8 @@ module pcs_top # // Parameter // =========================================================================== // parameter P_XGMII_LOOPBACK = 1'b0; - parameter P_SCRAMBLE_LOOPBACK = 1'b0; - parameter P_GEARBOX_LOOPBACK = 1'b0; + // parameter P_SCRAMBLE_LOOPBACK = 1'b0; + // parameter P_GEARBOX_LOOPBACK = 1'b0; wire soft_reset_i; (*mark_debug = "TRUE" *) wire soft_reset_vio_i; @@ -237,27 +240,27 @@ module pcs_top # wire QPLLRESET_IN; //--------------------------- User Clocks --------------------------------- - wire gt0_txusrclk_i; - wire gt0_txusrclk2_i; - wire gt0_rxusrclk_i; - wire gt0_rxusrclk2_i; + wire gt0_txusrclk_i; + wire gt0_txusrclk2_i; + wire gt0_rxusrclk_i; + wire gt0_rxusrclk2_i; wire gt0_txmmcm_lock_i; wire gt0_txmmcm_reset_i; - + //--------------------------- Reference Clocks ---------------------------- - + wire q2_clk1_refclk_i; //--------------------- Frame check/gen Module Signals -------------------- wire gt0_matchn_i; - + wire [3:0] gt0_txcharisk_float_i; - + wire [15:0] gt0_txdata_float16_i; wire [31:0] gt0_txdata_float_i; - - + + wire gt0_block_sync_i; wire gt0_track_data_i; wire [7:0] gt0_error_count_i; @@ -268,7 +271,7 @@ module pcs_top # wire reset_on_data_error_i; wire track_data_out_i; - + //--------------------- Chipscope Signals --------------------------------- (*mark_debug = "TRUE" *)wire rxresetdone_vio_i; @@ -323,18 +326,18 @@ module pcs_top # wire user_tx_reset_i; wire user_rx_reset_i; wire tx_vio_clk_i; - wire tx_vio_clk_mux_out_i; + wire tx_vio_clk_mux_out_i; wire rx_vio_ila_clk_i; wire rx_vio_ila_clk_mux_out_i; wire qpllreset_i; - + wire [(80 -32) -1:0] zero_vector_rx_80 ; wire [(8 -4) -1:0] zero_vector_rx_8 ; wire [79:0] gt0_rxdata_ila ; - wire [1:0] gt0_rxdatavalid_ila; + wire [1:0] gt0_rxdatavalid_ila; wire [7:0] gt0_rxcharisk_ila ; wire gt0_txmmcm_lock_ila ; wire gt0_rxmmcm_lock_ila ; @@ -347,7 +350,7 @@ module pcs_top # wire [31:0] s_rx_data; wire [ 5:0] s_rx_head; wire [ 1:0] s_rx_head_valid; - + wire [0:0] rxgearboxslip_int; wire [31:0] txdata_int; wire [5:0] txheader_int; @@ -359,7 +362,7 @@ module pcs_top # wire rxheadervalid_int; //**************************** Main Body of Code ******************************* - // Static signal Assigments + // Static signal Assigments assign tied_to_ground_i = 1'b0; assign tied_to_ground_vec_i = 64'h0000000000000000; assign tied_to_vcc_i = 1'b1; @@ -368,7 +371,7 @@ module pcs_top # assign zero_vector_rx_80 = 0; assign zero_vector_rx_8 = 0; - + assign q2_clk1_refclk_i = 1'b0; //***********************************************************************// @@ -376,124 +379,219 @@ assign q2_clk1_refclk_i = 1'b0; //--------------------------- The GT Wrapper ----------------------------// // // //***********************************************************************// - + // Use the instantiation template in the example directory to add the GT wrapper to your design. - // In this example, the wrapper is wired up for basic operation with a frame generator and frame - // checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is + // In this example, the wrapper is wired up for basic operation with a frame generator and frame + // checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is // enabled, bonding should occur after alignment. // While connecting the GT TX/RX Reset ports below, please add a delay of // minimum 500ns as mentioned in AR 43482. - + generate + if(P_SCRAMBLE_LOOPBACK == 0 && P_GEARBOX_LOOPBACK == 0) begin : g_gtwizard_on + gtwizard_0_support # + ( + .EXAMPLE_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP), + .STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD) + ) + gtwizard_0_support_i + ( + .soft_reset_tx_in (soft_reset_i), + .soft_reset_rx_in (soft_reset_i), + .dont_reset_on_data_error_in (tied_to_ground_i), + .q2_clk1_gtrefclk_pad_n_in(refclk_n_i), + .q2_clk1_gtrefclk_pad_p_in(refclk_p_i), + .gt0_tx_mmcm_lock_out (gt0_txmmcm_lock_i), + .gt0_tx_fsm_reset_done_out (gt0_txfsmresetdone_i), + .gt0_rx_fsm_reset_done_out (gt0_rxfsmresetdone_i), + .gt0_data_valid_in (gt0_track_data_i), + + .gt0_txusrclk_out(gt0_txusrclk_i), + .gt0_txusrclk2_out(gt0_txusrclk2_i), + .gt0_rxusrclk_out(gt0_rxusrclk_i), + .gt0_rxusrclk2_out(gt0_rxusrclk2_i), + + + //_____________________________________________________________________ + //_____________________________________________________________________ + //GT0 (X1Y8) + + //-------------------------- Channel - DRP Ports -------------------------- + .gt0_drpaddr_in (gt0_drpaddr_i), + .gt0_drpdi_in (gt0_drpdi_i), + .gt0_drpdo_out (gt0_drpdo_i), + .gt0_drpen_in (gt0_drpen_i), + .gt0_drprdy_out (gt0_drprdy_i), + .gt0_drpwe_in (gt0_drpwe_i), + //------------------------- Digital Monitor Ports -------------------------- + .gt0_dmonitorout_out (gt0_dmonitorout_i), + //------------------- RX Initialization and Reset Ports -------------------- + .gt0_eyescanreset_in (tied_to_ground_i), + .gt0_rxuserrdy_in (tied_to_vcc_i), + //------------------------ RX Margin Analysis Ports ------------------------ + .gt0_eyescandataerror_out (gt0_eyescandataerror_i), + .gt0_eyescantrigger_in (tied_to_ground_i), + //---------------- Receive Ports - FPGA RX interface Ports ----------------- + .gt0_rxdata_out (gt0_rxdata_i), + //------------------------- Receive Ports - RX AFE ------------------------- + .gt0_gtxrxp_in (gthrxp_i), + //---------------------- Receive Ports - RX AFE Ports ---------------------- + .gt0_gtxrxn_in (gthrxn_i), + //----------------- Receive Ports - RX Buffer Bypass Ports ----------------- + .gt0_rxphmonitor_out (gt0_rxphmonitor_i), + .gt0_rxphslipmonitor_out (gt0_rxphslipmonitor_i), + //------------------- Receive Ports - RX Equalizer Ports ------------------- + .gt0_rxdfelpmreset_in (tied_to_ground_i), + .gt0_rxmonitorout_out (gt0_rxmonitorout_i), + .gt0_rxmonitorsel_in (2'b00), + //------------- Receive Ports - RX Fabric Output Control Ports ------------- + .gt0_rxoutclkfabric_out (gt0_rxoutclkfabric_i), + //----------- Receive Ports - RX Initialization and Reset Ports ------------ + .gt0_gtrxreset_in (tied_to_ground_i), + .gt0_rxpmareset_in (gt0_rxpmareset_i), + //------------ Receive Ports -RX Initialization and Reset Ports ------------ + .gt0_rxresetdone_out (gt0_rxresetdone_i), + //------------------- TX Initialization and Reset Ports -------------------- + .gt0_gttxreset_in (tied_to_ground_i), + .gt0_txuserrdy_in (tied_to_vcc_i), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .gt0_txdata_in (bit32_rev(gt0_txdata_i)), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .gt0_gtxtxn_out (gthtxn_o), + .gt0_gtxtxp_out (gthtxp_o), + //--------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + .gt0_txoutclkfabric_out (gt0_txoutclkfabric_i), + .gt0_txoutclkpcs_out (gt0_txoutclkpcs_i), + //----------- Transmit Ports - TX Initialization and Reset Ports ----------- + .gt0_txresetdone_out (gt0_txresetdone_i), + + + //____________________________COMMON PORTS________________________________ + .gt0_qplllock_out(), + .gt0_qpllrefclklost_out(), + .gt0_qplloutclk_out(), + .gt0_qplloutrefclk_out(), + .sysclk_in(hb_gtwiz_reset_clk_freerun_in) + ); + + end else begin : g_gtwizard_off gtwizard_0_support # ( - .EXAMPLE_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP), - .STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD) + .EXAMPLE_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP), + .STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD) ) gtwizard_0_support_i ( - .soft_reset_tx_in (soft_reset_i), - .soft_reset_rx_in (soft_reset_i), - .dont_reset_on_data_error_in (tied_to_ground_i), - .q2_clk1_gtrefclk_pad_n_in(refclk_n_i), - .q2_clk1_gtrefclk_pad_p_in(refclk_p_i), - .gt0_tx_mmcm_lock_out (gt0_txmmcm_lock_i), - .gt0_tx_fsm_reset_done_out (gt0_txfsmresetdone_i), - .gt0_rx_fsm_reset_done_out (gt0_rxfsmresetdone_i), - .gt0_data_valid_in (gt0_track_data_i), - - .gt0_txusrclk_out(gt0_txusrclk_i), - .gt0_txusrclk2_out(gt0_txusrclk2_i), - .gt0_rxusrclk_out(gt0_rxusrclk_i), - .gt0_rxusrclk2_out(gt0_rxusrclk2_i), - - - //_____________________________________________________________________ - //_____________________________________________________________________ - //GT0 (X1Y8) - - //-------------------------- Channel - DRP Ports -------------------------- - .gt0_drpaddr_in (gt0_drpaddr_i), - .gt0_drpdi_in (gt0_drpdi_i), - .gt0_drpdo_out (gt0_drpdo_i), - .gt0_drpen_in (gt0_drpen_i), - .gt0_drprdy_out (gt0_drprdy_i), - .gt0_drpwe_in (gt0_drpwe_i), - //------------------------- Digital Monitor Ports -------------------------- - .gt0_dmonitorout_out (gt0_dmonitorout_i), - //------------------- RX Initialization and Reset Ports -------------------- - .gt0_eyescanreset_in (tied_to_ground_i), - .gt0_rxuserrdy_in (tied_to_vcc_i), - //------------------------ RX Margin Analysis Ports ------------------------ - .gt0_eyescandataerror_out (gt0_eyescandataerror_i), - .gt0_eyescantrigger_in (tied_to_ground_i), - //---------------- Receive Ports - FPGA RX interface Ports ----------------- - .gt0_rxdata_out (gt0_rxdata_i), - //------------------------- Receive Ports - RX AFE ------------------------- - .gt0_gtxrxp_in (gthrxp_i), - //---------------------- Receive Ports - RX AFE Ports ---------------------- - .gt0_gtxrxn_in (gthrxn_i), - //----------------- Receive Ports - RX Buffer Bypass Ports ----------------- - .gt0_rxphmonitor_out (gt0_rxphmonitor_i), - .gt0_rxphslipmonitor_out (gt0_rxphslipmonitor_i), - //------------------- Receive Ports - RX Equalizer Ports ------------------- - .gt0_rxdfelpmreset_in (tied_to_ground_i), - .gt0_rxmonitorout_out (gt0_rxmonitorout_i), - .gt0_rxmonitorsel_in (2'b00), - //------------- Receive Ports - RX Fabric Output Control Ports ------------- - .gt0_rxoutclkfabric_out (gt0_rxoutclkfabric_i), - //----------- Receive Ports - RX Initialization and Reset Ports ------------ - .gt0_gtrxreset_in (tied_to_ground_i), - .gt0_rxpmareset_in (gt0_rxpmareset_i), - //------------ Receive Ports -RX Initialization and Reset Ports ------------ - .gt0_rxresetdone_out (gt0_rxresetdone_i), - //------------------- TX Initialization and Reset Ports -------------------- - .gt0_gttxreset_in (tied_to_ground_i), - .gt0_txuserrdy_in (tied_to_vcc_i), - //---------------- Transmit Ports - TX Data Path interface ----------------- - .gt0_txdata_in (bit32_rev(gt0_txdata_i)), - //-------------- Transmit Ports - TX Driver and OOB signaling -------------- - .gt0_gtxtxn_out (gthtxn_o), - .gt0_gtxtxp_out (gthtxp_o), - //--------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - .gt0_txoutclkfabric_out (gt0_txoutclkfabric_i), - .gt0_txoutclkpcs_out (gt0_txoutclkpcs_i), - //----------- Transmit Ports - TX Initialization and Reset Ports ----------- - .gt0_txresetdone_out (gt0_txresetdone_i), + .soft_reset_tx_in (soft_reset_i), + .soft_reset_rx_in (soft_reset_i), + .dont_reset_on_data_error_in (tied_to_ground_i), + .q2_clk1_gtrefclk_pad_n_in(refclk_n_i), + .q2_clk1_gtrefclk_pad_p_in(refclk_p_i), + .gt0_tx_mmcm_lock_out (gt0_txmmcm_lock_i), + .gt0_tx_fsm_reset_done_out (), + .gt0_rx_fsm_reset_done_out (), + .gt0_data_valid_in (gt0_track_data_i), + + .gt0_txusrclk_out(gt0_txusrclk_i), + .gt0_txusrclk2_out(gt0_txusrclk2_i), + .gt0_rxusrclk_out(gt0_rxusrclk_i), + .gt0_rxusrclk2_out(), + + + //_____________________________________________________________________ + //_____________________________________________________________________ + //GT0 (X1Y8) + + //-------------------------- Channel - DRP Ports -------------------------- + .gt0_drpaddr_in (gt0_drpaddr_i), + .gt0_drpdi_in (gt0_drpdi_i), + .gt0_drpdo_out (gt0_drpdo_i), + .gt0_drpen_in (gt0_drpen_i), + .gt0_drprdy_out (gt0_drprdy_i), + .gt0_drpwe_in (gt0_drpwe_i), + //------------------------- Digital Monitor Ports -------------------------- + .gt0_dmonitorout_out (gt0_dmonitorout_i), + //------------------- RX Initialization and Reset Ports -------------------- + .gt0_eyescanreset_in (tied_to_ground_i), + .gt0_rxuserrdy_in (tied_to_vcc_i), + //------------------------ RX Margin Analysis Ports ------------------------ + .gt0_eyescandataerror_out (gt0_eyescandataerror_i), + .gt0_eyescantrigger_in (tied_to_ground_i), + //---------------- Receive Ports - FPGA RX interface Ports ----------------- + .gt0_rxdata_out (gt0_rxdata_i), + //------------------------- Receive Ports - RX AFE ------------------------- + .gt0_gtxrxp_in (gthrxp_i), + //---------------------- Receive Ports - RX AFE Ports ---------------------- + .gt0_gtxrxn_in (gthrxn_i), + //----------------- Receive Ports - RX Buffer Bypass Ports ----------------- + .gt0_rxphmonitor_out (gt0_rxphmonitor_i), + .gt0_rxphslipmonitor_out (gt0_rxphslipmonitor_i), + //------------------- Receive Ports - RX Equalizer Ports ------------------- + .gt0_rxdfelpmreset_in (tied_to_ground_i), + .gt0_rxmonitorout_out (gt0_rxmonitorout_i), + .gt0_rxmonitorsel_in (2'b00), + //------------- Receive Ports - RX Fabric Output Control Ports ------------- + .gt0_rxoutclkfabric_out (gt0_rxoutclkfabric_i), + //----------- Receive Ports - RX Initialization and Reset Ports ------------ + .gt0_gtrxreset_in (tied_to_ground_i), + .gt0_rxpmareset_in (gt0_rxpmareset_i), + //------------ Receive Ports -RX Initialization and Reset Ports ------------ + .gt0_rxresetdone_out (), + //------------------- TX Initialization and Reset Ports -------------------- + .gt0_gttxreset_in (tied_to_ground_i), + .gt0_txuserrdy_in (tied_to_vcc_i), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .gt0_txdata_in (bit32_rev(gt0_txdata_i)), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .gt0_gtxtxn_out (gthtxn_o), + .gt0_gtxtxp_out (gthtxp_o), + //--------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + .gt0_txoutclkfabric_out (gt0_txoutclkfabric_i), + .gt0_txoutclkpcs_out (gt0_txoutclkpcs_i), + //----------- Transmit Ports - TX Initialization and Reset Ports ----------- + .gt0_txresetdone_out (), + + + //____________________________COMMON PORTS________________________________ + .gt0_qplllock_out(), + .gt0_qpllrefclklost_out(), + .gt0_qplloutclk_out(), + .gt0_qplloutrefclk_out(), + .sysclk_in(hb_gtwiz_reset_clk_freerun_in) + ); + reg [7:0] rx_clk_count = 'd0; + reg [7:0] tx_clk_count = 'd0; + + assign gt0_rxusrclk2_i = gt0_txusrclk2_i; + always @(posedge gt0_rxusrclk2_i) begin + if(~rx_clk_count[7]) begin + rx_clk_count <= rx_clk_count + 8'd1; + end + end + + always @(posedge gt0_txusrclk2_i) begin + if(~tx_clk_count[7]) begin + tx_clk_count <= tx_clk_count + 8'd1; + end + end + assign gt0_rxfsmresetdone_i = rx_clk_count[7]; + assign gt0_txfsmresetdone_i = tx_clk_count[7]; + assign gt0_rxresetdone_i = rx_clk_count[7]; + assign gt0_txresetdone_i = tx_clk_count[7]; + end + endgenerate - //____________________________COMMON PORTS________________________________ - .gt0_qplllock_out(), - .gt0_qpllrefclklost_out(), - .gt0_qplloutclk_out(), - .gt0_qplloutrefclk_out(), - .sysclk_in(hb_gtwiz_reset_clk_freerun_in) - ); - - // IBUFDS IBUFDS_DRP_CLK - // ( - // .I (DRP_CLK_IN_P), - // .IB (DRP_CLK_IN_N), - // .O (DRPCLK_IN) - // ); - - // BUFG DRP_CLK_BUFG - // ( - // .I (DRPCLK_IN), - // .O (hb_gtwiz_reset_clk_freerun_in) - // ); - - //***********************************************************************// // // //--------------------------- User Module Resets-------------------------// // // //***********************************************************************// // All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules - // are held in reset till the RESETDONE goes high. - // The RESETDONE is registered a couple of times on *USRCLK2 and connected + // are held in reset till the RESETDONE goes high. + // The RESETDONE is registered a couple of times on *USRCLK2 and connected // to the reset of the modules - + always @(posedge gt0_rxusrclk2_i or negedge gt0_rxresetdone_i) begin @@ -526,8 +624,8 @@ always @(posedge gt0_rxusrclk2_i or negedge gt0_rxfsmresetdone_i) end end - - + + always @(posedge gt0_txusrclk2_i or negedge gt0_txfsmresetdone_i) begin @@ -547,7 +645,7 @@ always @(posedge gt0_txusrclk2_i or negedge gt0_txfsmresetdone_i) assign gt0_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt0_matchn_i; - // gt0_frame_check0 is always connected to the lane with the start of char + // gt0_frame_check0 is always connected to the lane with the start of char // and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off assign gt0_inc_in_i = 1'b0; @@ -591,7 +689,7 @@ always @(posedge gt0_txusrclk2_i or negedge gt0_txfsmresetdone_i) ); - generate + generate if(P_GEARBOX_LOOPBACK == 1) begin : g_gearbox_loopback_on assign s_gt_rx_data = gt0_txdata_i; end else begin : g_gearbox_loopback_off @@ -616,7 +714,7 @@ always @(posedge gt0_txusrclk2_i or negedge gt0_txfsmresetdone_i) // .data_i (gtwiz_userdata_tx_int) ); - generate + generate if(P_SCRAMBLE_LOOPBACK == 1) begin : g_scramble_loopback_on assign s_rx_data = txdata_int; assign s_rx_head = txheader_int; @@ -671,5 +769,5 @@ always @(posedge gt0_txusrclk2_i or negedge gt0_txfsmresetdone_i) assign soft_reset_i = tied_to_ground_i; endmodule - + diff --git a/gtx/rtl/prbs_check.v b/gtx/rtl/prbs_check.v index 761a293..4aa4921 100644 --- a/gtx/rtl/prbs_check.v +++ b/gtx/rtl/prbs_check.v @@ -21,7 +21,7 @@ module prbs_check ( reg [7:0] r_err1_cnt; reg [7:0] r_err2_cnt; reg [7:0] r_err3_cnt; - + always @(posedge rx_user_clk_i) begin if(rx_user_rst_i) begin r_count <= 'd0; @@ -57,7 +57,7 @@ module prbs_check ( r_err2_cnt <= 'd0; end else begin if(rx_valid_i) begin - if(rx_vldb_i == 2'b11) begin + if(rx_vldb_i != 2'b11) begin r_err2_cnt <= r_err2_cnt + 8'd1; end end @@ -74,16 +74,17 @@ module prbs_check ( r_err3_cnt <= r_err3_cnt + 8'd1; end end - end + end // ------------------------------------------------------------------------------------------------------------------- - // PRBS generator block + // PRBS checker block // ------------------------------------------------------------------------------------------------------------------- // The prbs_any block, described in Xilinx Application Note 884 (XAPP884), "An Attribute-Programmable PRBS Generator // and Checker", generates or checks a parameterizable PRBS sequence. Instantiate and parameterize a prbs_any block - // to generate a PRBS31 sequence with parallel data sized to the transmitter user data width. + // to check a PRBS31 sequence with parallel data sized to the receiver user data width. + gtwizard_ultrascale_0_prbs_any # ( - .CHK_MODE (0), + .CHK_MODE (1), .INV_PATTERN (1), .POLY_LENGHT (31), .POLY_TAP (28), @@ -96,4 +97,5 @@ module prbs_check ( .DATA_OUT (s_rx_prbs_check) ); + endmodule diff --git a/gtx/rtl/prbs_test.v b/gtx/rtl/prbs_test.v index f8821c5..087b2bb 100644 --- a/gtx/rtl/prbs_test.v +++ b/gtx/rtl/prbs_test.v @@ -20,6 +20,13 @@ module prbs_test ( input rst_i, output link_status_out ); + // =========================================================================== + // Parameter + // =========================================================================== + // parameter P_XGMII_LOOPBACK = 1'b0; + parameter P_SCRAMBLE_LOOPBACK = 1'b0; + parameter P_GEARBOX_LOOPBACK = 1'b0; + // AXIS tx wire s_tx_user_clk; wire s_tx_user_rst; @@ -41,7 +48,10 @@ module prbs_test ( wire s_rx_last; wire [0:0] s_rx_user; - pcs_top u_pcs_top + pcs_top #( + .P_SCRAMBLE_LOOPBACK (P_SCRAMBLE_LOOPBACK), + .P_GEARBOX_LOOPBACK (P_GEARBOX_LOOPBACK) + )u_pcs_top ( .refclk_n_i (refclk_n_i), .refclk_p_i (refclk_p_i), diff --git a/gtx/sim/prbs_wave.do b/gtx/sim/prbs_wave.do index de0ae66..89ef5d7 100644 --- a/gtx/sim/prbs_wave.do +++ b/gtx/sim/prbs_wave.do @@ -27,31 +27,172 @@ add wave -noupdate -group prbs_test /tb_prbs_loopback/u_prbs_test/s_rx_vldb add wave -noupdate -group prbs_test /tb_prbs_loopback/u_prbs_test/s_rx_valid add wave -noupdate -group prbs_test /tb_prbs_loopback/u_prbs_test/s_rx_last add wave -noupdate -group prbs_test /tb_prbs_loopback/u_prbs_test/s_rx_user -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_clk_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_rst_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_data_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_vldb_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_valid_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_last_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_count -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/s_rx_prbs_check -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err1_cnt -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err2_cnt -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err3_cnt -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_user_clk_i -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_user_rst_i -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_data_o -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_vldb_o -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_valid_o -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_ready_i -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_last_o -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_user_o -add wave -noupdate -expand -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/r_count +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_clk_i +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_rst_i +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_data_i +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_vldb_i +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_valid_i +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_last_i +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_i +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_count +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/s_rx_prbs_check +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err1_cnt +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err2_cnt +add wave -noupdate -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err3_cnt +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_user_clk_i +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_user_rst_i +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_data_o +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_vldb_o +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_valid_o +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_ready_i +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_last_o +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/tx_user_o +add wave -noupdate -group prbs_gen /tb_prbs_loopback/u_prbs_test/u_prbs_gen/r_count +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/clk_i +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/rst_i +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/xgmii_d_o +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/xgmii_c_o +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/sequence_o +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/tdata_i +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/tvldb_i +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/tvalid_i +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/tready_o +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/tlast_i +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/tuser_i +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/tx_status_o +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/tx_rsp_valid_o +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_66count +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_66b64b_ready +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_state +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_state_ready +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/s_ready +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_input_count +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_ipg_count +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_tdata_d1 +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_tvldb_d1 +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_tdata_d2 +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_tvldb_d2 +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_crc_left +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_d +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_c +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_sequence +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_sequence_d1 +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_sequence_d2 +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_sequence_d3 +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_crc_final +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_crc_32_4b +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_crc_32_3b +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_crc_32_2b +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/r_crc_32_1b +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/s_crc_final +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/s_crc_32_4b +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/s_crc_32_3b +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/s_crc_32_2b +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/s_crc_32_1b +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/xgmii_d +add wave -noupdate -group axi2xgmii32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_tx/u_axis2xgmii32/xgmii_c +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/clk_i +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/rst_i +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/good_frames_o +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/bad_frames_o +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/xgmii_d_i +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/xgmii_c_i +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/xgmii_v_i +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/tdata_o +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/tvldb_o +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/tvalid_o +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/tlast_o +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/tuser_o +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/s_xgmii_valid +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_state +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_tdata_d1 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_tvldb_d1 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_tvalid_d1 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_tlast_d1 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_tuser_d1 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/s_first_byte_tchar +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_tdata_d2 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_tvldb_d2 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_tvalid_d2 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/s_d +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/s_c +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_d +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_c +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_crc_32 +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_crc_32_3b +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_crc_32_2b +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_crc_32_1b +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/s_crc_32_4b +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/s_crc_32_3b +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/s_crc_32_2b +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/s_crc_32_1b +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_good_frames +add wave -noupdate -group xgmii2axi32 /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_xgmii2axis32/r_bad_frames +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/clk_i +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/rst_i +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/data_i +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/head_i +add wave -noupdate -expand -group rx -expand /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/head_valid_i +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/slip_o +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/tdata_o +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/tvldb_o +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/tvalid_o +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/tlast_o +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/tuser_o +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_rx_lane_locked +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/r_data +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/r_head +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_rx_descrambled_data +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_rx_descrambled_head +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_rx_descrambled_data_rev +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_rx_descrambled_head_rev +add wave -noupdate -expand -group rx {/tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/head_valid_i[0]} +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/r_rx_descrambled_valid +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_decode_data +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_decode_head +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_decode_data_vld +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_decode_error +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_xgmii_rxd_64 +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_xgmii_rxc_64 +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/s_xgmii_rxd_vld_64 +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/r_xgmii_rxd_vld_64 +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/r_xgmii_d_32 +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/r_xgmii_c_32 +add wave -noupdate -expand -group rx /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/r_xgmii_v_32 +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/clk_i +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/rst_i +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/data_i +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/head_i +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/data_vld_i +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/data_o +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/head_o +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/data_vld_o +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/r_descramble_register +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/s_data_in +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/s_head_in +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/r_data_in_buf +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/s_descrambled_data +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/r_descrambled_data_d2 +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/r_descrambled_data_vld_d1 +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/r_descrambled_data_vld_d2 +add wave -noupdate -group descramble /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_descramble/i +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/clk_i +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/rst_i +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/decode_data_i +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/decode_head_i +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/decode_data_vld_i +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/xgmii_rxd_o +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/xgmii_rxc_o +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/xgmii_rxd_vld_o +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/decode_error_o +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/r_rxd_d1 +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/r_rxc_d1 +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/r_rxd_vld_d1 +add wave -noupdate -expand -group decode_64b_66b /tb_prbs_loopback/u_prbs_test/u_pcs_top/u_rx/u_decode_64b_66b/r_decode_error_d1 TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {95929203 ps} 0} {{Cursor 2} {95828166 ps} 1} +WaveRestoreCursors {{Cursor 1} {22640478 ps} 0} {{Cursor 2} {95828166 ps} 1} quietly wave cursor active 1 -configure wave -namecolwidth 150 +configure wave -namecolwidth 224 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 1 @@ -65,4 +206,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ps update -WaveRestoreZoom {95818031 ps} {96089639 ps} +WaveRestoreZoom {22612266 ps} {22638002 ps} diff --git a/gtx/sim/tb_prbs_loopback.sv b/gtx/sim/tb_prbs_loopback.sv index 28521cf..934b7d0 100644 --- a/gtx/sim/tb_prbs_loopback.sv +++ b/gtx/sim/tb_prbs_loopback.sv @@ -7,6 +7,13 @@ module tb_prbs_loopback(); + // =========================================================================== + // Parameter + // =========================================================================== + // parameter P_XGMII_LOOPBACK = 1'b0; + parameter P_SCRAMBLE_LOOPBACK = 1'b1; + parameter P_GEARBOX_LOOPBACK = 1'b0; + // ------------------------------------------------------------------------------------------------------------------- // Signal declarations and basic example design stimulus // ------------------------------------------------------------------------------------------------------------------- @@ -47,7 +54,10 @@ module tb_prbs_loopback(); reset_all = 1'b0; end - prbs_test u_prbs_test ( + prbs_test #( + .P_SCRAMBLE_LOOPBACK (P_SCRAMBLE_LOOPBACK), + .P_GEARBOX_LOOPBACK (P_GEARBOX_LOOPBACK) + ) u_prbs_test ( .refclk_n_i (~ref_clk), .refclk_p_i (ref_clk),