From 5e153c0d31db04707e549a5e059d45876c16ab2f Mon Sep 17 00:00:00 2001 From: jack_mac Date: Mon, 8 Apr 2019 21:07:51 +0800 Subject: [PATCH] =?UTF-8?q?=E6=94=AF=E6=8C=81num=5Fof=5Flane=E4=B8=BA2?= =?UTF-8?q?=E7=9A=84=E9=85=8D=E7=BD=AE=20#12?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- gtx/xm_v1_0/rtl/mac/prbs_test.v | 106 +++++++++++++++------------- gtx/xm_v1_0/rtl/phy/teng_phy.v | 11 +-- gtx/xm_v1_0/rtl/xm_top.v | 4 +- gtx/xm_v1_0/sim/tb_prbs_loopback.sv | 10 +-- gtx/xm_v1_0/sim/wave.do | 13 ---- 5 files changed, 71 insertions(+), 73 deletions(-) diff --git a/gtx/xm_v1_0/rtl/mac/prbs_test.v b/gtx/xm_v1_0/rtl/mac/prbs_test.v index b0ac42d..7e2472f 100644 --- a/gtx/xm_v1_0/rtl/mac/prbs_test.v +++ b/gtx/xm_v1_0/rtl/mac/prbs_test.v @@ -19,43 +19,44 @@ module prbs_test # ) ( - input ref_clk_n_i, - input ref_clk_p_i, - output debug_o, - input gt_rxn_i, - input gt_rxp_i, - output gt_txn_o, - output gt_txp_o, + input ref_clk_n_i, + input ref_clk_p_i, + output debug_o, + input [NUMBER_OF_LANES-1:0] gt_rxn_i, + input [NUMBER_OF_LANES-1:0] gt_rxp_i, + output [NUMBER_OF_LANES-1:0] gt_txn_o, + output [NUMBER_OF_LANES-1:0] gt_txp_o, // User-provided ports for reset helper block(s) - input sys_clk_i, - input sys_reset_i, - output link_up_o + input sys_clk_i, + input sys_reset_i, + output [NUMBER_OF_LANES-1:0] link_up_o ); // =========================================================================== // Parameter // =========================================================================== // AXIS tx - wire s_tx_user_clk; - wire s_tx_user_rst; - wire [31:0] s_tx_data; - wire [1:0] s_tx_vldb; - wire s_tx_valid; - wire s_tx_ready; - wire s_tx_last; - wire [0:0] s_tx_user; - - wire s_tx_status; - wire s_tx_rsp_valid; + wire s_tx_user_clk; + wire s_tx_user_rst; + wire [NUMBER_OF_LANES*32-1:0] s_tx_data; + wire [NUMBER_OF_LANES*2-1:0] s_tx_vldb; + wire [NUMBER_OF_LANES-1:0] s_tx_valid; + wire [NUMBER_OF_LANES-1:0] s_tx_ready; + wire [NUMBER_OF_LANES-1:0] s_tx_last; + wire [NUMBER_OF_LANES-1:0] s_tx_user; + + wire [NUMBER_OF_LANES-1:0] s_tx_status; + wire [NUMBER_OF_LANES-1:0] s_tx_rsp_valid; // AXIS rx - wire s_rx_user_clk; - wire s_rx_user_rst; - wire [31:0] s_rx_data; - wire [1:0] s_rx_vldb; - wire s_rx_valid; - wire s_rx_last; - wire [0:0] s_rx_user; + wire s_rx_user_clk; + wire s_rx_user_rst; + wire [NUMBER_OF_LANES*32-1:0] s_rx_data; + wire [NUMBER_OF_LANES*2-1:0] s_rx_vldb; + wire [NUMBER_OF_LANES-1:0] s_rx_valid; + wire [NUMBER_OF_LANES-1:0] s_rx_last; + wire [NUMBER_OF_LANES-1:0] s_rx_user; + wire [NUMBER_OF_LANES-1:0] s_debug_out; xm_top #( .CHOOSE_REFCLK0 (CHOOSE_REFCLK0 ), @@ -104,27 +105,34 @@ module prbs_test # ); - prbs_gen u_prbs_gen ( - .tx_user_clk_i (s_tx_user_clk), - .tx_user_rst_i (s_tx_user_rst), - .tx_data_o (s_tx_data), - .tx_vldb_o (s_tx_vldb), - .tx_valid_o (s_tx_valid), - .tx_ready_i (s_tx_ready), - .tx_last_o (s_tx_last), - .tx_user_o (s_tx_user) - ); - - prbs_check u_prbs_check ( - .rx_user_clk_i (s_rx_user_clk), - .rx_user_rst_i (s_rx_user_rst), - .rx_data_i (s_rx_data), - .rx_vldb_i (s_rx_vldb), - .rx_valid_i (s_rx_valid), - .rx_last_i (s_rx_last), - .rx_user_i (s_rx_user), - .err_o (debug_o) - ); + generate + genvar i; + for(i = 0; i < NUMBER_OF_LANES; i = i + 1) begin : g_prbs + prbs_gen u_prbs_gen ( + .tx_user_clk_i (s_tx_user_clk), + .tx_user_rst_i (s_tx_user_rst), + .tx_data_o (s_tx_data[i*32 +: 32]), + .tx_vldb_o (s_tx_vldb[i*2 +: 2]), + .tx_valid_o (s_tx_valid[i]), + .tx_ready_i (s_tx_ready[i]), + .tx_last_o (s_tx_last[i]), + .tx_user_o (s_tx_user[i]) + ); + + prbs_check u_prbs_check ( + .rx_user_clk_i (s_rx_user_clk), + .rx_user_rst_i (s_rx_user_rst), + .rx_data_i (s_rx_data[i*32 +: 32]), + .rx_vldb_i (s_rx_vldb[i*2 +: 2]), + .rx_valid_i (s_rx_valid[i]), + .rx_last_i (s_rx_last[i]), + .rx_user_i (s_rx_user[i]), + .err_o (s_debug_out[i]) + ); + end + endgenerate + + assign debug_o = |s_debug_out; endmodule diff --git a/gtx/xm_v1_0/rtl/phy/teng_phy.v b/gtx/xm_v1_0/rtl/phy/teng_phy.v index 57a7342..3e13b80 100644 --- a/gtx/xm_v1_0/rtl/phy/teng_phy.v +++ b/gtx/xm_v1_0/rtl/phy/teng_phy.v @@ -24,8 +24,6 @@ module teng_phy # input gt_ref_clk_pad_n_i, input gt_ref_clk_pad_p_i, input dont_reset_on_data_error_i, - // output [NUMBER_OF_LANES-1:0] tx_fsm_reset_done_o, - // output [NUMBER_OF_LANES-1:0] rx_fsm_reset_done_o, input [NUMBER_OF_LANES-1:0] data_valid_i,//rx数据稳定，在100us之内不稳定，且DONT_RESET_ON_DATA_ERROR为0会整体复位 // input [NUMBER_OF_LANES-1:0] tx_mmcm_lock_i, // output [NUMBER_OF_LANES-1:0] tx_mmcm_reset_o, @@ -61,6 +59,8 @@ module teng_phy # wire s_qpll_out_ref_clk; wire s_common_reset; + wire [NUMBER_OF_LANES-1:0] s_tx_fsm_reset_done; + wire [NUMBER_OF_LANES-1:0] s_rx_fsm_reset_done; // wire [NUMBER_OF_LANES-1:0] s_rx_usr_clk; // wire [NUMBER_OF_LANES-1:0] s_rx_usr_clk2; wire [NUMBER_OF_LANES-1:0] s_rx_pcs_reset; @@ -135,6 +135,9 @@ assign s_rx_pma_reset = {NUMBER_OF_LANES{s_tied_to_ground} assign s_tx_pcs_reset = {NUMBER_OF_LANES{s_tied_to_ground}}; assign s_tx_pma_reset = {NUMBER_OF_LANES{s_tied_to_ground}}; +assign tx_fsm_reset_done_o = s_tx_fsm_reset_done; +assign rx_fsm_reset_done_o = s_rx_fsm_reset_done; + multi_lane_init # ( .GTREFCLKSEL (GTREFCLKSEL ), @@ -150,8 +153,8 @@ multi_lane_init # .soft_reset_tx_i (soft_reset_tx_i ), .soft_reset_rx_i (soft_reset_rx_i ), .dont_reset_on_data_error_i (dont_reset_on_data_error_i ), - .tx_fsm_reset_done_o (tx_fsm_reset_done_o ), - .rx_fsm_reset_done_o (rx_fsm_reset_done_o ), + .tx_fsm_reset_done_o (s_tx_fsm_reset_done ), + .rx_fsm_reset_done_o (s_rx_fsm_reset_done ), .data_valid_i (data_valid_i ),//rx数据稳定，在100us之内不稳定，且DONT_RESET_ON_DATA_ERROR为0会整体复位 .tx_mmcm_lock_i (s_tx_clk_lock ), .tx_mmcm_reset_o (s_tx_mmcm_reset ), diff --git a/gtx/xm_v1_0/rtl/xm_top.v b/gtx/xm_v1_0/rtl/xm_top.v index 32ae8b7..34caef2 100644 --- a/gtx/xm_v1_0/rtl/xm_top.v +++ b/gtx/xm_v1_0/rtl/xm_top.v @@ -30,8 +30,8 @@ module xm_top # output [NUMBER_OF_LANES-1:0] gt_txp_o, // User-provided ports for reset helper block(s) - input [NUMBER_OF_LANES-1:0] sys_clk_i, - input [NUMBER_OF_LANES-1:0] sys_reset_i, + input sys_clk_i, + input sys_reset_i, output [NUMBER_OF_LANES-1:0] link_up_o, // AXIS tx output tx_user_clk_o, diff --git a/gtx/xm_v1_0/sim/tb_prbs_loopback.sv b/gtx/xm_v1_0/sim/tb_prbs_loopback.sv index 6b70164..e85ef8f 100644 --- a/gtx/xm_v1_0/sim/tb_prbs_loopback.sv +++ b/gtx/xm_v1_0/sim/tb_prbs_loopback.sv @@ -11,22 +11,22 @@ module tb_prbs_loopback(); // Parameter // =========================================================================== parameter CHOOSE_REFCLK0 = 1; - parameter NUMBER_OF_LANES = 1; + parameter NUMBER_OF_LANES = 2; parameter MASTER_LANE_ID = 0; parameter SIM_GTRESET_SPEEDUP = "TRUE"; // Simulation setting for GT SecureIP model parameter SIMULATION = 0; // Set to 1 for simulation parameter STABLE_CLOCK_PERIOD = 10; //Period of the stable clock driving this state-machine, unit is [ns] - parameter P_SCRAMBLE_LOOPBACK = 1'b0; - parameter P_GEARBOX_LOOPBACK = 1'b0; + parameter P_SCRAMBLE_LOOPBACK = 1'b0; + parameter P_GEARBOX_LOOPBACK = 1'b0; // ------------------------------------------------------------------------------------------------------------------- // Signal declarations and basic example design stimulus // ------------------------------------------------------------------------------------------------------------------- // Declare wires to loop back serial data ports for transceiver channel 0 - wire gthxn; - wire gthxp; + wire [NUMBER_OF_LANES-1:0] gthxn; + wire [NUMBER_OF_LANES-1:0] gthxp; // Declare register to drive reference clock at location ref_clk reg ref_clk = 1'b0; diff --git a/gtx/xm_v1_0/sim/wave.do b/gtx/xm_v1_0/sim/wave.do index f780f39..ecd8a8d 100644 --- a/gtx/xm_v1_0/sim/wave.do +++ b/gtx/xm_v1_0/sim/wave.do @@ -485,19 +485,6 @@ add wave -noupdate -group rx_alignment {/tb_prbs_loopback/u_prbs_test/u_xm_top/u add wave -noupdate -group rx_alignment {/tb_prbs_loopback/u_prbs_test/u_xm_top/u_teng_mac/g_mac[0]/u_rx/u_rx_alignment/r_aligned_count} add wave -noupdate -group rx_alignment {/tb_prbs_loopback/u_prbs_test/u_xm_top/u_teng_mac/g_mac[0]/u_rx/u_rx_alignment/r_rxgearboxslip} add wave -noupdate -group rx_alignment {/tb_prbs_loopback/u_prbs_test/u_xm_top/u_teng_mac/g_mac[0]/u_rx/u_rx_alignment/r_sleep} -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_clk_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_rst_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_data_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_vldb_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_valid_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_last_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/rx_user_i -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/err_o -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_count -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/s_rx_prbs_check -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err1_cnt -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err2_cnt -add wave -noupdate -expand -group prbs_check /tb_prbs_loopback/u_prbs_test/u_prbs_check/r_err3_cnt TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {69979522 ps} 0} quietly wave cursor active 1