diff --git a/xm_v1_0/rtl/mac/axis2xgmii32.v b/xm_v1_0/rtl/mac/axis2xgmii32.v index 5ed7186..a0ae61e 100644 --- a/xm_v1_0/rtl/mac/axis2xgmii32.v +++ b/xm_v1_0/rtl/mac/axis2xgmii32.v @@ -58,6 +58,7 @@ module axis2xgmii32 ( reg [31:0] r_tdata_d1; reg [1:0] r_tvldb_d1; + reg r_tvalid_d1; reg [31:0] r_tdata_d2; reg [1:0] r_tvldb_d2; reg [1:0] r_crc_left; @@ -241,7 +242,9 @@ module axis2xgmii32 ( if(rst_i) begin r_tdata_d1 <= 'd0; r_tvldb_d1 <= 'd0; + r_tvalid_d1 <= 1'b0; end else begin + r_tvalid_d1 <= tvalid_i && s_ready; if(tvalid_i && s_ready) begin if(tlast_i) begin r_tdata_d1 <= tdata_i; @@ -294,14 +297,16 @@ module axis2xgmii32 ( r_crc_32_1b <= 'd0; r_crc_final <= 'd0; end else begin - if(r_state == P_START) begin - r_crc_32_4b <= crc4B(CRC802_3_PRESET,r_tdata_d1[31:0]); - end else begin - r_crc_32_4b <= crc4B(r_crc_32_4b,r_tdata_d1[31:0]); + if(r_tvalid_d1) begin + if(r_state == P_START) begin + r_crc_32_4b <= crc4B(CRC802_3_PRESET,r_tdata_d1[31:0]); + end else begin + r_crc_32_4b <= crc4B(r_crc_32_4b,r_tdata_d1[31:0]); + end + r_crc_32_3b <= crc3B(r_crc_32_4b,r_tdata_d1[23:0]); + r_crc_32_2b <= crc2B(r_crc_32_4b,r_tdata_d1[15:0]); + r_crc_32_1b <= crc1B(r_crc_32_4b,r_tdata_d1[7:0]); end - r_crc_32_3b <= crc3B(r_crc_32_4b,r_tdata_d1[23:0]); - r_crc_32_2b <= crc2B(r_crc_32_4b,r_tdata_d1[15:0]); - r_crc_32_1b <= crc1B(r_crc_32_4b,r_tdata_d1[7:0]); if(r_state == P_CRC) begin case(r_tvldb_d2) 2'd0: r_crc_final <= {24'h0,s_crc_32_1b[31:24]}; diff --git a/xm_v1_0/rtl/mac/xgmii2axis32.v b/xm_v1_0/rtl/mac/xgmii2axis32.v index fe57c77..67f54de 100644 --- a/xm_v1_0/rtl/mac/xgmii2axis32.v +++ b/xm_v1_0/rtl/mac/xgmii2axis32.v @@ -47,6 +47,7 @@ module xgmii2axis32 ( reg r_tlast_d1; reg [0:0] r_tuser_d1; + reg [0:0] r_tuser_ahead; wire s_first_byte_tchar; reg [31:0] r_tdata_d2; reg [1:0] r_tvldb_d2; @@ -68,6 +69,8 @@ module xgmii2axis32 ( wire [31:0] s_crc_32_2b; wire [31:0] s_crc_32_1b; + // reg [31:0] r_crc_32_4b_d1; + reg [31:0] r_good_frames; reg [31:0] r_bad_frames; /****************************************************************************** @@ -143,6 +146,15 @@ module xgmii2axis32 ( end end + always @(posedge clk_i) begin + if(rst_i) begin + r_tuser_ahead[0] <= 1'b0; + end else begin + if(s_xgmii_valid) begin + r_tuser_ahead[0] <= (s_crc_32_4b == s_d) && (s_c == 4'b0); + end + end + end always @(posedge clk_i) begin if(rst_i) begin r_tdata_d1 <= 'd0; @@ -192,9 +204,9 @@ module xgmii2axis32 ( if(is_tchar(s_d[7:0])) begin r_tlast_d1 <= 1'd1; end - if((s_crc_32_4b == r_d) && is_tchar(s_d[7:0])) begin - r_tuser_d1[0] <= 1'd1; - end + // if((r_crc_32_4b_d1 == r_d) && is_tchar(s_d[7:0])) begin + // r_tuser_d1[0] <= 1'd1; + // end end 4'b1110 : begin @@ -203,7 +215,7 @@ module xgmii2axis32 ( if(is_tchar(s_d[15:8])) begin r_tlast_d1 <= 1'd1; end - if((s_crc_32_3b == {s_d[7:0], r_d[31:8]}) && is_tchar(s_d[15:8])) begin + if((s_crc_32_1b == {s_d[7:0], r_d[31:8]}) && is_tchar(s_d[15:8])) begin r_tuser_d1[0] <= 1'd1; end end @@ -223,7 +235,7 @@ module xgmii2axis32 ( if(is_tchar(s_d[31:24])) begin r_tlast_d1 <= 1'd1; end - if((s_crc_32_1b == {s_d[23:0], r_d[31:24]}) && is_tchar(s_d[31:24])) begin + if((s_crc_32_3b == {s_d[23:0], r_d[31:24]}) && is_tchar(s_d[31:24])) begin r_tuser_d1[0] <= 1'd1; end end @@ -267,10 +279,12 @@ module xgmii2axis32 ( r_tdata_d2 <= r_tdata_d1; r_tvldb_d2 <= r_tvldb_d1; end - if((r_tlast_d1 & r_tvalid_d1) | (s_first_byte_tchar)) begin - r_tvalid_d2 <= 1'b0; - end else begin - r_tvalid_d2 <= r_tvalid_d1; + if(s_xgmii_valid) begin + if((r_tlast_d1 & r_tvalid_d1) | (s_first_byte_tchar)) begin + r_tvalid_d2 <= 1'b0; + end else begin + r_tvalid_d2 <= r_tvalid_d1; + end end end // not rst_i end //always @@ -287,7 +301,7 @@ module xgmii2axis32 ( end else begin if(r_state == P_IDLE) begin r_crc_32 <= CRC802_3_PRESET; - end else if(r_state == P_DATA) begin + end else if(r_state == P_DATA && s_xgmii_valid) begin r_crc_32 <= crc4B(r_crc_32,s_d); r_crc_32_3b <= crc3B(r_crc_32,s_d[23:0]); r_crc_32_2b <= crc2B(r_crc_32,s_d[15:0]); @@ -296,6 +310,13 @@ module xgmii2axis32 ( end end + // always @(posedge clk_i) begin + // if(rst_i) begin + // r_crc_32_4b_d1 <= 'd0; + // end else begin + // r_crc_32_4b_d1 <= s_crc_32_4b; + // end + // end assign s_crc_32_4b = ~crc_rev(r_crc_32); assign s_crc_32_3b = ~crc_rev(r_crc_32_3b); assign s_crc_32_2b = ~crc_rev(r_crc_32_2b); @@ -310,5 +331,5 @@ module xgmii2axis32 ( assign tvldb_o = r_tvldb_d1; assign tvalid_o = r_tvalid_d2 & s_xgmii_valid; assign tlast_o = r_tlast_d1 | s_first_byte_tchar; - assign tuser_o = r_tuser_d1; + assign tuser_o = r_tuser_d1 | (s_first_byte_tchar & r_tuser_ahead[0]); endmodule // xgmii2axis32 \ No newline at end of file diff --git a/xm_v1_0/sim/mac/tb_mac_loopback.sv b/xm_v1_0/sim/mac/tb_mac_loopback.sv index 38222b8..4e060bb 100644 --- a/xm_v1_0/sim/mac/tb_mac_loopback.sv +++ b/xm_v1_0/sim/mac/tb_mac_loopback.sv @@ -125,6 +125,25 @@ module tb_mac_loopback(); #1us; fork + // begin : tx + // q_pkt_t q_packet; + // int packet_len; + // packet_len = 59; + // repeat(SIM_NUM_OF_PACKETS) begin + // // packet_len = packet_len + 1; + // packet_len = random_between(60, 1514); + + // q_packet = {}; + // repeat(packet_len) begin + // q_packet.push_back(ramdom_bytes()); + // end + + // q_check_bytes = {q_check_bytes, q_packet}; + // q_check_len.push_back(q_packet.size()); + // mac_master.write(q_packet); + + // end + // end begin : tx q_pkt_t q_packet; int packet_len; @@ -173,6 +192,8 @@ module tb_mac_loopback(); end join + assert(mac_slave.crc_error_cnt == 0) + else $error("receive error packets : %d", mac_slave.crc_error_cnt); #5us; $display("sim done"); $stop; diff --git a/xm_v1_0/sim/stream_pkg.sv b/xm_v1_0/sim/stream_pkg.sv index 3fd7925..6588543 100644 --- a/xm_v1_0/sim/stream_pkg.sv +++ b/xm_v1_0/sim/stream_pkg.sv @@ -113,9 +113,11 @@ package stream_pkg; class StreamSlaveBfm #(int DATA_WIDTH = 64); virtual stream.slave #(DATA_WIDTH) rx_ck; + integer crc_error_cnt; function new(virtual stream.slave #(DATA_WIDTH) rx_ck); this.rx_ck = rx_ck; + this.crc_error_cnt = 0; endfunction task read(output q_pkt_t q_payload); @@ -137,6 +139,9 @@ package stream_pkg; if(rx_ck.mon_cb.eop) begin q_payload = this_packet_q; rx_ck.mon_cb.ready <= 1'b0; + if(rx_ck.mon_cb.user == 1'b0) begin + this.crc_error_cnt = this.crc_error_cnt + 1; + end break; end end