From 5839ce1d5131993f1b3b4d0ab77f11815cac5af0 Mon Sep 17 00:00:00 2001 From: Rishabh Joshi Date: Fri, 28 Oct 2016 00:57:53 +0530 Subject: [PATCH] Added ALU implementation. --- Lab4/Lab41.v | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Lab4/Lab41.v b/Lab4/Lab41.v index 96a7d40..6df1e74 100644 --- a/Lab4/Lab41.v +++ b/Lab4/Lab41.v @@ -144,4 +144,23 @@ module ALUControl(op,ALUOp,funct); assign op[1] = (~funct[2])|(~ALUOp[1]); assign op[2] = (funct[1] &ALUOp[1]) | ALUOp[0]; -endmodule \ No newline at end of file +endmodule + +// Alternate Implementation to ALU +module ALU(a, b, binv, cin, opn, result, cout); + input [31:0] a, b; + input binv, cin; + input [1:0] opn; + output cout; + output [31:0] result; + // binv 1 for subtraction 0 for add + // cin goes to full adder cin + // opn 00 for and, 01 for or, 10 for add/sub + wire [31:0] finalb, aandb, aorb, aopb; + + bit32_2to1mux bmux (finalb, binv, b, ~b); + bit32_AND aband (aandb, a, finalb); + bit32_OR abor (aorb, a, finalb); + bit32_FA_dataflow fa(cout, aopb, a, finalb, cin); + bit32_3to1mux selmux (result, opn, aandb, aorb, aopb); +endmodule