A host for small Verilog-Snippets brewed during Lab Sessions of Computer Architecture Course at BITS-Pilani.
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This repository will hold certain scratch-pad models of MIPS(Microprocessor without Interlocked Pipeline Stages) DataPath and Control Unit for different implementations.
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It may at later stages also contain certain parts related to Memory Segment.
Instructor-In-Charge: Sudeept Mohan
References :
- Computer Organisation and Design by Petterson,Hennesy
- Verilog HDL by Samir Palnitkar