CPU.hdl

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Central Processing unit (CPU).
 * Consists of an ALU and a set of registers, designed to fetch and 
 * execute instructions written in the Hack machine language.
 * In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine 
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input 
 * holds the value of this location. If the current instruction needs 
 * to write a value to M, the value is placed in outM, the address 
 * of the target location is placed in the addressM output, and the 
 * writeM control bit is asserted. (When writeM=0, any value may 
 * appear in outM). The outM and writeM outputs are combinational: 
 * they are affected instantaneously by the execution of the current 
 * instruction. The addressM and pc outputs are clocked: although they 
 * are affected by the execution of the current instruction, they commit 
 * to their new values only in the next time unit. If reset=1 then the 
 * CPU jumps to address 0 (i.e. sets pc=0 in next time unit) rather 
 * than to the address resulting from executing the current instruction. 
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset=1) or continue executing
                         // the current program (reset=0).

    OUT outM[16],        // M value output
        writeM,          // Write into M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    // A Register
    Not(in=instruction[15], out=a-command);
    Mux16(a=alu-output, b[15]=false, b[0..14]=instruction[0..14], sel=a-command, out=a-register-input);
    Or(a=a-command, b=instruction[5], out=a-register-load);
    ARegister(in=a-register-input, load=a-register-load, out=a-register-output, out[0..14]=addressM);
    
    // D Register
    And(a=instruction[4], b=instruction[15], out=load-d-register);
    DRegister(in=alu-output, load=load-d-register, out=alu-x-input);

    // ALU
    Mux16(a=a-register-output, b=inM, sel=instruction[12], out=alu-y-input);
    ALU(x=alu-x-input, zx=instruction[11], nx=instruction[10], y=alu-y-input, zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=alu-output, out=outM);

    // PC
    PCController(data=alu-output, jmp=instruction[0..2], type=instruction[15], inc=inc-pc, load=load-pc);
    PC(in=a-register-output, load=load-pc, inc=inc-pc, reset=reset, out[0..14]=pc);

    // writeM
    And(a=instruction[3], b=instruction[15], out=writeM);
}