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a/zh-cn/assets/image8-d242f7b7.png b/zh-cn/assets/image8-d242f7b7.png new file mode 100644 index 0000000..09b5be9 Binary files /dev/null and b/zh-cn/assets/image8-d242f7b7.png differ diff --git a/zh-cn/assets/image9-5e691a52.png b/zh-cn/assets/image9-5e691a52.png new file mode 100644 index 0000000..64418cb Binary files /dev/null and b/zh-cn/assets/image9-5e691a52.png differ diff --git a/zh-cn/assets/index-5968a39d.js b/zh-cn/assets/index-047539e4.js similarity index 93% rename from zh-cn/assets/index-5968a39d.js rename to zh-cn/assets/index-047539e4.js index 5096d7d..333cd8a 100644 --- a/zh-cn/assets/index-5968a39d.js +++ b/zh-cn/assets/index-047539e4.js @@ -1,4 +1,4 @@ -const o="/zh-cn/assets/cover-9c53ea5f.png",t="/zh-cn/assets/imgae1-084eb861.jpg",e=[o,t],s={label:"硬件敏捷开发与验证方法学研讨",description:"作为2022年第二届RISC-V中国峰会的同期活动,8月27日下午,达坦科技将在线上举办硬件敏捷开发与验证方法学研讨。",cover:"./cover.png",location:"新加坡",date:"2022-08-23",title:"Hardware Agile Development and Verification Methodology Workshop"},n=[],l=`
作为 2022 年第二届 RISC-V 中国峰会的同期活动,8 月 27 日下午,达坦科技将在线上举办硬件敏捷开发与验证方法学研讨。
+const o="/zh-cn/assets/cover-9c53ea5f.png",t="/zh-cn/assets/imgae1-084eb861.jpg",e=[o,t],n={label:"硬件敏捷开发与验证方法学研讨",description:"作为2022年第二届RISC-V中国峰会的同期活动,8月27日下午,达坦科技将在线上举办硬件敏捷开发与验证方法学研讨。",cover:"./cover.png",location:"新加坡",date:"2022-08-23",title:"Hardware Agile Development and Verification Methodology Workshop"},s=[],l=`作为 2022 年第二届 RISC-V 中国峰会的同期活动,8 月 27 日下午,达坦科技将在线上举办硬件敏捷开发与验证方法学研讨。
如何提升数字芯片的开发和验证效率一直是业界关注的焦点。近年来随着 Chisel、SpinalHDL 等等一众新一代 HDL 的推出,业界逐步感受到新一代 HDL 在数字芯片设计效率方面的提升。相比 Verilog 和 VHDL,这些新一代 HDL 在语法表达能力、代码简洁程度、错误检查等方面有不小的提升;相比高阶综合 HLS,这些新一代 HDL 支持 RTL 级描述能力,在芯片性能的把控方面远超 HLS。此外,基于 Python,以 Cocotb 和 pyuvm 为代表的新一代验证框架的推出,使得验证的周期得到一定程度的缩减,特别是基于 Python 的验证框架可以复用 Python 生态丰富的已有工具和模型,大大减少了 Golden Reference 的工作量。
更重要的是,这些新一代 HDL 打开了全新的数字芯片敏捷设计和验证的方法学大门。本次研讨将邀请业界多位专家分享他们在各自领域的硬件敏捷开发与验证实践经验,为业界提供一次深入探讨和交流的机会,促进硬件敏捷开发与验证方法学的发展与落地。
参与本次研讨的听众可以深入了解业界关于硬件敏捷开发与验证的最前沿探索,诸如:
@@ -11,4 +11,4 @@ const o="/zh-cn/assets/cover-9c53ea5f.png",t="/zh-cn/assets/imgae1-084eb861.jpg"活动时间:8 月 27 日,13:15-17:15
活动链接:https://t.elecfans.com/live/2113.html
感兴趣的听众可以添加海报中的群主二维码加入讨论群,添加时请注明硬件敏捷开发和验证方法学研讨。
新一代硬件描述语言 SpinalHDL 的发明人 Charles Papon 说,SpinalHDL 始于 2014 年,最初是作为 VHDL/Verilog 的替代而做的创新尝试,伴随着数年来开源硬件设计的蓬勃发展,基于开源技术的硬件设计方法和范式逐渐受到业界的关注,那么 SpinalHDL 有哪些最新的进展和落地实践呢?
+const t="/zh-cn/assets/cover-9c53ea5f.png",n="/zh-cn/assets/image1-52cf1c3c.jpg",s="/zh-cn/assets/image1-0a18e154.png",o=[t,n,s],a={label:"SpinalHDL应用前景探索线上研讨会",description:"新一代硬件描述语言SpinalHDL的发明人Charles Papon说,SpinalHDL始于2014年,最初是作为VHDL/Verilog的替代而做的创新尝试,伴随着数年来开源硬件设计的蓬勃发展,基于开源技术的硬件设计方法和范式逐渐受到业界的关注,那么SpinalHDL有哪些最新的进展和落地实践呢?",cover:"./cover.png",location:"中国香港",date:"2022-12-08",title:"SpinalHDL Application Prospect Exploration Online Seminar"},p=[{label:"线上研讨会",level:2}],r=`新一代硬件描述语言 SpinalHDL 的发明人 Charles Papon 说,SpinalHDL 始于 2014 年,最初是作为 VHDL/Verilog 的替代而做的创新尝试,伴随着数年来开源硬件设计的蓬勃发展,基于开源技术的硬件设计方法和范式逐渐受到业界的关注,那么 SpinalHDL 有哪些最新的进展和落地实践呢?
达坦科技(DatenLord) 致力于打造高性能跨云存储,其通过软硬件深度融合的方式打破云之间的壁垒,实现高性能跨云数据访问,提供海量异地、异构数据的统一存储访问机制,为云上应用提供高性能安全存储支持。达坦科技采用硬件加速提升存储性能,目前采用 FPGA、ASIC 实现存储相关场景的性能加速。SpinalHDL 是达坦科技在产品中使用的硬件描述语言之一,达坦科技也一直热心于推广 SpinalHDL 在业界的落地应用。
为了让对开源硬件感兴趣的朋友进一步了解 SpinalHDL,在北京时间 2022 年 12 月 16 日下午 17:00-21:00,达坦科技联合 SpinalHDL 社区举办一场题为《SpinalHDL 应用前景探索》的线上研讨会(Webinar),本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程 (Flow)。
@@ -11,4 +11,4 @@ const s="/zh-cn/assets/cover-9c53ea5f.png",n="/zh-cn/assets/image1-52cf1c3c.jpg" 会议号:830 6630 7799对开源硬件感兴趣的朋友,可以添加小助手微信,加入达坦科技硬件群。
-`;export{o as assetURLs,p as default,r as metadata,a as toc}; +`;export{o as assetURLs,r as default,a as metadata,p as toc}; diff --git a/zh-cn/assets/index-d735fd77.js b/zh-cn/assets/index-07db2d14.js similarity index 95% rename from zh-cn/assets/index-d735fd77.js rename to zh-cn/assets/index-07db2d14.js index 7ea28fa..61b1fc6 100644 --- a/zh-cn/assets/index-d735fd77.js +++ b/zh-cn/assets/index-07db2d14.js @@ -1,4 +1,4 @@ -const o="/zh-cn/assets/cover-964a3e23.png",e="/zh-cn/assets/image1-c300ce2e.png",n="/zh-cn/assets/image2-b3df764b.png",l="/zh-cn/assets/image3-6b1d2584.png",s="/zh-cn/assets/image4-034a33e9.png",t="/zh-cn/assets/image5-6a5e807d.png",i=[o,e,n,l,s,t],p={label:"达坦科技2023开源毕业设计实习招募中",description:"自1984年Richard Stallman发起GMU和Free Software Foundation,开源作为一种全新的软件开发和使用模式正式诞生。One for All, All for One的理念传播开后,之后的40年里在开源软件社区被无数开发者实践和传承。开源软件因其节省费用(不需要购买许可证,大大降低了IT投入成本)、安全稳定(安全漏洞少)、技术成熟、个性化定制、自主知识产权等优势获得喜人的发展,由此我们也见证了无数开源软件项目的成长和成熟",cover:"./cover.png",location:"海南",date:"2023-01-06",title:"Datan Technology 2023 Open Source Graduation Design Internship Recruitment"},r=[{label:"毕设项目的背景",level:2},{label:"细分方向",level:2},{label:"开源毕设导师组",level:2},{label:"开源毕设项目的流程",level:2},{label:"申请流程",level:2}],a=`自 1984 年 Richard Stallman 发起 GMU 和 Free Software Foundation,开源作为一种全新的软件开发和使用模式正式诞生。One for All, All for One 的理念传播开后,之后的 40 年里在开源软件社区被无数开发者实践和传承。开源软件因其节省费用(不需要购买许可证,大大降低了 IT 投入成本)、安全稳定(安全漏洞少)、技术成熟、个性化定制、自主知识产权等优势获得喜人的发展,由此我们也见证了无数开源软件项目的成长和成熟
+const i="/zh-cn/assets/cover-964a3e23.png",e="/zh-cn/assets/image1-c300ce2e.png",n="/zh-cn/assets/image2-b3df764b.png",l="/zh-cn/assets/image3-6b1d2584.png",s="/zh-cn/assets/image4-034a33e9.png",t="/zh-cn/assets/image5-6a5e807d.png",o=[i,e,n,l,s,t],p={label:"达坦科技2023开源毕业设计实习招募中",description:"自1984年Richard Stallman发起GMU和Free Software Foundation,开源作为一种全新的软件开发和使用模式正式诞生。One for All, All for One的理念传播开后,之后的40年里在开源软件社区被无数开发者实践和传承。开源软件因其节省费用(不需要购买许可证,大大降低了IT投入成本)、安全稳定(安全漏洞少)、技术成熟、个性化定制、自主知识产权等优势获得喜人的发展,由此我们也见证了无数开源软件项目的成长和成熟",cover:"./cover.png",location:"海南",date:"2023-01-06",title:"Datan Technology 2023 Open Source Graduation Design Internship Recruitment"},a=[{label:"毕设项目的背景",level:2},{label:"细分方向",level:2},{label:"开源毕设导师组",level:2},{label:"开源毕设项目的流程",level:2},{label:"申请流程",level:2}],r=`自 1984 年 Richard Stallman 发起 GMU 和 Free Software Foundation,开源作为一种全新的软件开发和使用模式正式诞生。One for All, All for One 的理念传播开后,之后的 40 年里在开源软件社区被无数开发者实践和传承。开源软件因其节省费用(不需要购买许可证,大大降低了 IT 投入成本)、安全稳定(安全漏洞少)、技术成熟、个性化定制、自主知识产权等优势获得喜人的发展,由此我们也见证了无数开源软件项目的成长和成熟
相比而言,硬件开源之路更为崎岖。因为对物理器件的依赖度更高,复杂度更高,修改难度大,硬件开源之路走得比较缓慢。虽然是一条少有人走的路,但其正确性毋庸置疑。开源芯片生态(Open Source Chip Ecosystem-OSCE)的优势,包括可以节约市场化时间,以及知识产权的成本,EDA 工具、设施和劳动力。硬件开发者也期盼硬件设计可以像软件设计一样简单。
@@ -46,4 +46,4 @@ const o="/zh-cn/assets/cover-964a3e23.png",e="/zh-cn/assets/image1-c300ce2e.png"欢迎您预约直播,或者登陆腾讯会议观看直播:
对开源毕设感兴趣的朋友,欢迎添加小助手微信,加入达坦科技开源毕设群。
-`;export{i as assetURLs,a as default,p as metadata,r as toc}; +`;export{o as assetURLs,r as default,p as metadata,a as toc}; diff --git a/zh-cn/assets/index-5689e7f4.js b/zh-cn/assets/index-0b547be0.js similarity index 95% rename from zh-cn/assets/index-5689e7f4.js rename to zh-cn/assets/index-0b547be0.js index 2586269..054bf5d 100644 --- a/zh-cn/assets/index-5689e7f4.js +++ b/zh-cn/assets/index-0b547be0.js @@ -1,4 +1,4 @@ -const n="/zh-cn/assets/cover-dcd7e2ce.jpeg",t="/zh-cn/assets/image1-3ae2277f.jpg",s="/zh-cn/assets/image1-0a18e154.png",o=[n,t,s],e={label:"分布式实验室直播 | 共识算法与跨数据中心一致性的元数据管理",description:"在 2021 年时,UC Berkeley 提出了天空计算(Sky Computing)的概念。所谓天空计算是云平台上的一层,其目标是打通彼此孤立的云,将分布式系统从数据中心范围扩展到全球范围。Xline 是一款开源分布式 kv 存储系统,基于 curp 共识算法实现,旨在提供跨云元数据管理功能。相比于传统共识协议 Raft 或 Paxos,curp 在天空计算的场景中有着更好的性能表现。",cover:"./cover.jpeg",location:"海南",date:"2023-02-01",title:"Consensus Algorithms and Metadata Management for Cross Data Center Consistency"},r=[],a=`在 2021 年时,UC Berkeley 提出了 天空计算(Sky Computing) 的概念。所谓天空计算是云平台上的一层,其目标是打通彼此孤立的云,将分布式系统从数据中心范围扩展到全球范围。 Xline 是一款开源分布式 kv 存储系统, 基于 curp 共识算法实现,旨在提供跨云元数据管理功能。相比于传统共识协议 Raft 或 Paxos,curp 在天空计算的场景中有着更好的性能表现
+const n="/zh-cn/assets/cover-dcd7e2ce.jpeg",t="/zh-cn/assets/image1-3ae2277f.jpg",s="/zh-cn/assets/image1-0a18e154.png",o=[n,t,s],e={label:"分布式实验室直播 | 共识算法与跨数据中心一致性的元数据管理",description:"在 2021 年时,UC Berkeley 提出了天空计算(Sky Computing)的概念。所谓天空计算是云平台上的一层,其目标是打通彼此孤立的云,将分布式系统从数据中心范围扩展到全球范围。Xline 是一款开源分布式 kv 存储系统,基于 curp 共识算法实现,旨在提供跨云元数据管理功能。相比于传统共识协议 Raft 或 Paxos,curp 在天空计算的场景中有着更好的性能表现。",cover:"./cover.jpeg",location:"海南",date:"2023-02-01",title:"Consensus Algorithms and Metadata Management for Cross Data Center Consistency"},r=[],i=`在 2021 年时,UC Berkeley 提出了 天空计算(Sky Computing) 的概念。所谓天空计算是云平台上的一层,其目标是打通彼此孤立的云,将分布式系统从数据中心范围扩展到全球范围。 Xline 是一款开源分布式 kv 存储系统, 基于 curp 共识算法实现,旨在提供跨云元数据管理功能。相比于传统共识协议 Raft 或 Paxos,curp 在天空计算的场景中有着更好的性能表现
本周四(2 月 2 日)晚上 8 点,达坦科技和分布式实验室合作,由达坦科技 Rust 分布式存储工程师赵佳炜讲述共识算法与跨数据中心一致性的元数据管理,并介绍 Xline 是如何实现高性能跨数据中心的数据一致性管理。
直播亮点:
@@ -11,4 +11,4 @@ const n="/zh-cn/assets/cover-dcd7e2ce.jpeg",t="/zh-cn/assets/image1-3ae2277f.jpg请添加分布式实验室小助手的微信,报名参与直播:
达坦科技(DatenLord)推出的开源分布式 KV 存储 Xline,针对多数据中心场景,实现数据的高性能跨云、跨数据中心共享访问,并保证数据的一致性,方便业务系统实现多地多中心多活部署。
-GitHub 链接:https://github.com/xline-kv/
`;export{o as assetURLs,a as default,e as metadata,r as toc}; +GitHub 链接:https://github.com/xline-kv/
`;export{o as assetURLs,i as default,e as metadata,r as toc}; diff --git a/zh-cn/assets/index-4d1333f2.js b/zh-cn/assets/index-16f06676.js similarity index 98% rename from zh-cn/assets/index-4d1333f2.js rename to zh-cn/assets/index-16f06676.js index 5b12e33..cfdab04 100644 --- a/zh-cn/assets/index-4d1333f2.js +++ b/zh-cn/assets/index-16f06676.js @@ -1,4 +1,4 @@ -const o="/zh-cn/assets/image1-fe10a0d4.jpg",t="/zh-cn/assets/image2-86112638.jpg",n=[o,t],r={label:"倒计时6天 | 机遇与挑战-生成式AI的发展趋势和落地应用",description:"生成式AI作为人工智能的重要分支,在语言模型、图像生成、音乐创作等领域都取得了突破性地进展。技术的发展,也伴随着机遇、挑战与难题。本周日(8月6日)在北京,将由亚马逊云科技和真格基金主办,达坦科技和INP协办举行一场关于生成式AI的闭门沙龙,主题为“机遇与挑战——生成式AI的发展趋势和落地应用”。",location:"新疆",date:"2023-08-01",title:"Countdown to 6 days l Opportunities and Challenges The Development Trend of Generative AI and its Application on the Ground"},s=[],e=`生成式 AI 作为人工智能的重要分支,在语言模型、图像生成、音乐创作等领域都取得了突破性地进展。技术的发展,也伴随着机遇、挑战与难题。本周日(8 月 6 日)在北京,将由亚马逊云科技和真格基金主办,达坦科技和 INP 协办举行一场关于生成式 AI 的闭门沙龙,主题为“机遇与挑战——生成式 AI 的发展趋势和落地应用”。
+const o="/zh-cn/assets/image1-fe10a0d4.jpg",t="/zh-cn/assets/image2-86112638.jpg",n=[o,t],r={label:"倒计时6天 | 机遇与挑战-生成式AI的发展趋势和落地应用",description:"生成式AI作为人工智能的重要分支,在语言模型、图像生成、音乐创作等领域都取得了突破性地进展。技术的发展,也伴随着机遇、挑战与难题。本周日(8月6日)在北京,将由亚马逊云科技和真格基金主办,达坦科技和INP协办举行一场关于生成式AI的闭门沙龙,主题为“机遇与挑战——生成式AI的发展趋势和落地应用”。",location:"新疆",date:"2023-08-01",title:"Countdown to 6 days l Opportunities and Challenges The Development Trend of Generative AI and its Application on the Ground"},e=[],s=`生成式 AI 作为人工智能的重要分支,在语言模型、图像生成、音乐创作等领域都取得了突破性地进展。技术的发展,也伴随着机遇、挑战与难题。本周日(8 月 6 日)在北京,将由亚马逊云科技和真格基金主办,达坦科技和 INP 协办举行一场关于生成式 AI 的闭门沙龙,主题为“机遇与挑战——生成式 AI 的发展趋势和落地应用”。
我们邀请了国内外知名的 AI Infra/应用创业者、硬核 NLP/LLM 专家、咨询大咖,分享在生成式 AI 研究和实践中的经验,通过具体的案例,探讨生成式 AI 在不同领域的落地应用和挑战,揭示其对产业升级和创新的重要作用。
本次闭门沙龙邀请到的 AI Infra/应用创业者、硬核 NLP/LLM 专家、咨询大咖有(以下介绍按照姓氏字母排序):
@@ -50,4 +50,4 @@ At Stochastic, he focus on developing Enterprise-ready LLM system that trains lo 通用工具与行业客户需求不匹配怎么办?SpinalHDL 是一种开源的高级硬件描述语言,它可以作为 VHDL 或 Verilog 的替代,Charles Papon 在 2014 年创建后,伴随着数年来开源硬件设计的蓬勃发展,在多方面显露出优势,譬如:它专注于高效的硬件描述,而不是事件驱动;作为一种基于 Scala 的 DSL,能够借助现有的 Scala 语言特性和开发工具提供强大、易用、高效的硬件设计能力。
+const n="/zh-cn/assets/image1-b917417e.jpg",o="/zh-cn/assets/image1-50beaba8.png",a=[n,o],p={label:"倒计时5天:SpinalHDL应用前景探索线上研讨会",description:"SpinalHDL是一种开源的高级硬件描述语言,它可以作为VHDL或Verilog的替代,Charles Papon 在2014年创建后,伴随着数年来开源硬件设计的蓬勃发展,在多方面显露出优势,譬如:它专注于高效的硬件描述,而不是事件驱动;作为一种基于Scala的DSL,能够借助现有的Scala语言特性和开发工具提供强大、易用、高效的硬件设计能力。达坦科技采用硬件加速提升存储性能,目前采用FPGA实现存储相关场景的性能加速。SpinalHDL是达坦科技在产品中使用的硬件描述语言之一,因此,达坦科技也一直热心于推广SpinalHDL在业界的落地应用。在2023年12月10日,我们将联合SpinalHDL社区及该语言的创建者 Charles Papon 举办 《2023 SpinalHDL应用前景探索》的线上研讨会,分为两个Track。",location:"中国香港",date:"2023-12-05",title:"Countdown to 5 days: SpinalHDL application prospect exploration online seminar"},t=[{label:"Tooling and flow:",level:2},{label:"Projects :",level:2}],s=`SpinalHDL 是一种开源的高级硬件描述语言,它可以作为 VHDL 或 Verilog 的替代,Charles Papon 在 2014 年创建后,伴随着数年来开源硬件设计的蓬勃发展,在多方面显露出优势,譬如:它专注于高效的硬件描述,而不是事件驱动;作为一种基于 Scala 的 DSL,能够借助现有的 Scala 语言特性和开发工具提供强大、易用、高效的硬件设计能力。
达坦科技采用硬件加速提升存储性能,目前采用 FPGA 实现存储相关场景的性能加速。SpinalHDL 是达坦科技在产品中使用的硬件描述语言之一,因此,达坦科技也一直热心于推广 SpinalHDL 在业界的落地应用。
在 2023 年 12 月 10 日,我们将联合 SpinalHDL 社区及该语言的创建者 Charles Papon 举办 《2023 SpinalHDL 应用前景探索》 的线上研讨会,分为两个 Track。
会议链接:
https://zoom.us/j/82302372789?pwd=OYsFCbiW06KqC4U83ZKsZwefM75gJr.1
对开源硬件和敏捷开发感兴趣的朋友,可以添加达坦科技小助手的微信,加入达坦科技硬件群。
-`;export{p as assetURLs,s as default,a as metadata,t as toc}; +`;export{a as assetURLs,s as default,p as metadata,t as toc}; diff --git a/zh-cn/assets/index-dfd283a0.js b/zh-cn/assets/index-2530d06d.js similarity index 95% rename from zh-cn/assets/index-dfd283a0.js rename to zh-cn/assets/index-2530d06d.js index 3bca56e..6fe7046 100644 --- a/zh-cn/assets/index-dfd283a0.js +++ b/zh-cn/assets/index-2530d06d.js @@ -1,4 +1,4 @@ -const l="/zh-cn/assets/image1-50beaba8.png",a=[l],n={label:"2023年SpinalHDL应用前景探索线上研讨会----征集演讲嘉宾",description:"SpinalHDL是一种开源的高级硬件描述语言,它可以作为VHDL或Verilog的替代,Charles Papon 在2014年创建后,伴随着数年来开源硬件设计的蓬勃发展,在多方面显露出优势,譬如:它专注于高效的硬件描述,而不是事件驱动;作为一种基于Scala的DSL,能够借助现有的Scala语言特性和开发工具提供强大、易用、高效的硬件设计能力。",location:"中国香港",date:"2023-11-09",title:"Exploring the Future of SpinalHDL Applications in 2023 Online Workshop"},p=[{label:"SpinalHDL 是什么?",level:2},{label:"达坦科技是谁?",level:2},{label:"为什么达坦科技要推广 SpinalHDL?",level:2},{label:"Call For Presenter",level:2}],i=`SpinalHDL 是一种开源的高级硬件描述语言,它可以作为 VHDL 或 Verilog 的替代,Charles Papon 在 2014 年创建后,伴随着数年来开源硬件设计的蓬勃发展,在多方面显露出优势,譬如:它专注于高效的硬件描述,而不是事件驱动;作为一种基于 Scala 的 DSL,能够借助现有的 Scala 语言特性和开发工具提供强大、易用、高效的硬件设计能力。
达坦科技(DatenLord)致力于打造高性能跨云存储,其通过软硬件深度融合的方式打破云之间的壁垒,实现高性能跨云数据访问,提供海量异地、异构数据的统一存储访问机制,为云上应用提供高性能安全存储支持。
@@ -18,4 +18,4 @@ const l="/zh-cn/assets/image1-50beaba8.png",a=[l],n={label:"2023年SpinalHDL应如您有意向社区,以及 SpinalHDL 的爱好者做分享,请于 2023 年 11 月 30 日之前,直接将姓名(或 GitHub 昵称)+ 议题摘要提交至以下 GitHub 链接:
https://github.com/SpinalHDL/SpinalHDL/discussions/1235
对开源硬件感兴趣的朋友可以添加达坦科技小助手微信加入达坦科技硬件群。
`;export{a as assetURLs,i as default,n as metadata,p as toc}; +对开源硬件感兴趣的朋友可以添加达坦科技小助手微信加入达坦科技硬件群。
`;export{n as assetURLs,i as default,a as metadata,p as toc}; diff --git a/zh-cn/assets/index-28199dec.js b/zh-cn/assets/index-28199dec.js new file mode 100644 index 0000000..f78ee0d --- /dev/null +++ b/zh-cn/assets/index-28199dec.js @@ -0,0 +1,39 @@ +const l="/zh-cn/assets/cover-6865ae02.png",i=[l],e={label:"Xline v0.6.1: 一个用于元数据管理的分布式KV存储",description:"Xline是一个基于Curp协议的,用于管理元数据的分布式KV存储。现有的分布式KV存储大多采用Raft共识协议,需要两次RTT才能完成一次请求。当部署在单个数据中心时,节点之间的延迟较低,因此不会对性能产生大的影响。但是,当跨数据中心部署时,节点之间的延迟可能是几十或几百毫秒,此时 Raft 协议将成为性能瓶颈。Curp 协议就是为了解决这个问题而设计的。它可以在命令不冲突的情况下减少一个RTT,从而提高性能。因此,Xline旨在实现高性能的数据访问和跨数据中心场景下的强一致性。",cover:"./cover.png",location:"新疆",author:["准备开社区会议的"],tags:["Xline"],date:"2024-01-18",title:"Xline v0.6.1: a distributed KV store for metadata management"},t=[{label:"Xline是什么?我们为什么要做Xline?",level:2},{label:"V0.6.1版本有什么新功能?",level:2},{label:"社区会议",level:2}],n=` +Xline是一个基于Curp协议的,用于管理元数据的分布式KV存储。 现有的分布式KV存储大多采用Raft共识协议,需要两次RTT才能完成一次请求。当部署在单个数据中心时,节点之间的延迟较低,因此不会对性能产生大的影响。
+但是,当跨数据中心部署时,节点之间的延迟可能是几十或几百毫秒,此时 Raft 协议将成为性能瓶颈。Curp 协议就是为了解决这个问题而设计的。它可以在命令不冲突的情况下减少一个RTT,从而提高性能。因此,Xline旨在实现高性能的数据访问和跨数据中心场景下的强一致性。
+v0.6.1新版本修复问题以及重构如下:
+🪲修复问题
+🛠️ 重构
+为了更全面地向大家介绍Xline的进展,同时促进Xline社区的发展,我们将于2024年1月27日北京时间上午10:00召开Xline社区会议。
+欢迎您届时登陆zoom观看直播: +会议号: 874 4309 5241 +密码: 124294 +会议链接: +https://zoom.us/j/87443095241?pwd=r3uJhJ9cb0caovHRsi1ay2pFuhBA1Q.1
`;export{i as assetURLs,n as default,e as metadata,t as toc}; diff --git a/zh-cn/assets/index-0c25eea3.js b/zh-cn/assets/index-2b1c59a2.js similarity index 97% rename from zh-cn/assets/index-0c25eea3.js rename to zh-cn/assets/index-2b1c59a2.js index 25c7558..88f473f 100644 --- a/zh-cn/assets/index-0c25eea3.js +++ b/zh-cn/assets/index-2b1c59a2.js @@ -1,4 +1,4 @@ -const t="/zh-cn/assets/cover-ae42e606.jpg",s="/zh-cn/assets/image1-4de20ee3.jpg",n="/zh-cn/assets/image2-9ad061db.jpg",o=[t,s,n],r={label:"Rust X DatenLord l Rust China Conf 2023 倒计时!",description:"Rust语言作为一种强调性能、安全和并发性的新的编程语言,吸引了越来越多的程序员想要尝试学习和使用Rust。达坦科技(DatenLord)旗下的开源项目Xline (用于元数据管理的分布式KV存储)就是用Rust写就的,我们也一直坚定地做Rust语言在中国的布道。",cover:"./cover.jpg",location:"中国香港",date:"2023-06-11",title:"Countdown to Rust X DatenLord l Rust China Conf 2023"},e=[{label:"倒计时",level:2},{label:"主会场",level:2},{label:"分论坛:Rust 语言与高性能实践",level:2},{label:"Workshop:Rust in System",level:2},{label:"报名注意事项",level:2}],g=` +const t="/zh-cn/assets/cover-ae42e606.jpg",s="/zh-cn/assets/image1-4de20ee3.jpg",n="/zh-cn/assets/image2-9ad061db.jpg",o=[t,s,n],r={label:"Rust X DatenLord l Rust China Conf 2023 倒计时!",description:"Rust语言作为一种强调性能、安全和并发性的新的编程语言,吸引了越来越多的程序员想要尝试学习和使用Rust。达坦科技(DatenLord)旗下的开源项目Xline (用于元数据管理的分布式KV存储)就是用Rust写就的,我们也一直坚定地做Rust语言在中国的布道。",cover:"./cover.jpg",location:"中国香港",date:"2023-06-11",title:"Countdown to Rust X DatenLord l Rust China Conf 2023"},e=[{label:"倒计时",level:2},{label:"主会场",level:2},{label:"分论坛:Rust 语言与高性能实践",level:2},{label:"Workshop:Rust in System",level:2},{label:"报名注意事项",level:2}],p=`Rust 语言作为一种强调性能、安全和并发性的新的编程语言,吸引了越来越多的程序员想要尝试学习和使用 Rust。达坦科技(DatenLord)旗下的开源项目 Xline (用于元数据管理的分布式 KV 存储)就是用 Rust 写就的,我们也一直坚定地做 Rust 语言在中国的布道。
因此,2023 年 6 月 17-18 日 我们也将奔赴上海,支持 Rust 语言中文社区在疫情之后首次举办的大型线下 Rust 开发者大会。达坦科技的两位创始人将在 Rust China Conf 2023 上分别做主题演讲,在 6 月 17 日晚,达坦科技还将赞助举办一场干货满满的 workshop。
@@ -31,4 +31,4 @@ const t="/zh-cn/assets/cover-ae42e606.jpg",s="/zh-cn/assets/image1-4de20ee3.jpg"添加小助手微信,进入达坦科技 Rust 前沿技术交流群
更多关于 Rust China Conf 2023 官方信息,请查阅
--https://rustcc.cn/2023rustchinaconf/
2021 年,UC Berkeley 的 Ion Stoica 和 Scott Shenker,在运行系统热点话题的研讨会上,发布了“从云计算到天空计算”的论文。不同于我们都熟知的 Cloud Computing(“云计算”),Sky Computing (“天空计算”),是云计算的未来,是指天空中有很多的云,如何解决跨云的问题,打破不同云之间的隔阂,最大化地利用跨云数据。
达坦科技的使命正如同论文中描述的“天空计算”的愿景:打造下一代云计算平台,让云之间没有隔阂。为此,新年伊始,我们翻译了这篇论文,将分两期发布。如下是“从云计算到天空计算”的第一部分。
虽然开源软件解决了天空计算中的绝大多数问题, 但是还有一个问题没有解决, 那就是存储问题, 因为每一家云厂商都会提供自己的存储接口。幸运的是已经有一个方案提供 S3 兼容的接口, 甚至一些云厂商自己也会提供 S3 兼容的接口。更进一步, 云平台之间的数据访问应该是可行的, 不会受到阻碍。
达坦科技(DatenLord)推出的开源分布式 KV 存储 Xline,就是针对多数据中心场景,实现数据的高性能跨云、跨数据中心共享访问,并保证数据的一致性,方便业务系统实现多地多中心多活部署。
-GitHub 链接:Https://github.com/datenlord/Xline
`;export{p as assetURLs,n as default,o as metadata,e as toc}; +GitHub 链接:Https://github.com/datenlord/Xline
`;export{t as assetURLs,n as default,o as metadata,e as toc}; diff --git a/zh-cn/assets/index-c832920a.js b/zh-cn/assets/index-30c7b3e8.js similarity index 89% rename from zh-cn/assets/index-c832920a.js rename to zh-cn/assets/index-30c7b3e8.js index 28e9c82..997cb22 100644 --- a/zh-cn/assets/index-c832920a.js +++ b/zh-cn/assets/index-30c7b3e8.js @@ -1,4 +1,4 @@ -const s="/zh-cn/assets/cover-48216986.png",t="/zh-cn/assets/image1-02771bf0.jpg",n="/zh-cn/assets/image1-f46bfcc6.jpg",r=[s,t,n],o={label:"当RDMA遇到Rust",description:"2022年8月5日-6日,一年一度的中国开源基础设施活动日(OpenInfra Days China)即将在线上举行。本次会议没有限定一个统一的主题,主要聚焦云计算基础设施、云原生技术与应用实践、开源治理、5G、算力网络与边缘计算五大主题方向。",cover:"./cover.png",location:"新加坡",date:"2022-08-04",title:"When RDMA meets Rust"},p=[],e=` +const s="/zh-cn/assets/cover-48216986.png",t="/zh-cn/assets/image1-02771bf0.jpg",n="/zh-cn/assets/image1-f46bfcc6.jpg",o=[s,t,n],r={label:"当RDMA遇到Rust",description:"2022年8月5日-6日,一年一度的中国开源基础设施活动日(OpenInfra Days China)即将在线上举行。本次会议没有限定一个统一的主题,主要聚焦云计算基础设施、云原生技术与应用实践、开源治理、5G、算力网络与边缘计算五大主题方向。",cover:"./cover.png",location:"新加坡",date:"2022-08-04",title:"When RDMA meets Rust"},p=[],c=`2022 年 8 月 5 日-6 日,**一年一度的中国开源基础设施活动日(OpenInfra Days China)**即将在线上举行。本次会议没有限定一个统一的主题,主要聚焦云计算基础设施、云原生技术与应用实践、开源治理、5G、算力网络与边缘计算五大主题方向。
云计算基础设施分论坛主要聚焦云计算基础设施领域的前沿技术和优秀实践,围绕多硬件架构和多操作系统支持、人工智能技术应用、网络与存储,数据处理 DPU 及其他加速硬件、硬件自动化和智能运维等方面展开技术分享和探讨。达坦科技联合创始人施继成将在这一分论坛做题为当 RDMA 遇到 Rust 的专题分享。
@@ -10,4 +10,4 @@ const s="/zh-cn/assets/cover-48216986.png",t="/zh-cn/assets/image1-02771bf0.jpg"想要了解更多达坦科技为什么选择 Rust 做 RDMA 库,以及开发设计背后的理念、逻辑、和实践经验,欢迎扫描海报二维码,免费注册报名。
有意加入 Rust 前沿交流讨论群,请添加小助手微信:
-`;export{r as assetURLs,e as default,o as metadata,p as toc}; +`;export{o as assetURLs,c as default,r as metadata,p as toc}; diff --git a/zh-cn/assets/index-a84bdbd8.js b/zh-cn/assets/index-35dfbee0.js similarity index 86% rename from zh-cn/assets/index-a84bdbd8.js rename to zh-cn/assets/index-35dfbee0.js index 02d062b..28c9d38 100644 --- a/zh-cn/assets/index-a84bdbd8.js +++ b/zh-cn/assets/index-35dfbee0.js @@ -1,4 +1,4 @@ -const t="/zh-cn/assets/cover-39643179.png",e="/zh-cn/assets/image1-a93ba076.jpg",p="/zh-cn/assets/image2-4624885a.gif",s="/zh-cn/assets/image3-ea54df7e.jpg",a=[t,e,p,s],c={label:"直播预告 | RDMA软件接口高层封装",description:"RDMA 作为高速通信协议被数据中心广泛使用,但是因为底层接口设计得过于繁复,对使用者造成了很大的不便,因此我们使用 Rust 语言对 RDMA 进行了一层高层封装。这次分享将介绍这层封装的做法和原理。",cover:"./cover.png",location:"香港",date:"2022-05-17",title:"RDMA Software Interface High Level Package"},l=[{label:"嘉宾介绍",level:2},{label:"讨论内容",level:2},{label:"观看方式",level:2},{label:"特别鸣谢",level:2}],o=`施继成
达坦科技联合创始人兼 CTO,复旦大学软件工程本硕,师从华为基础软件首席科学家、鸿蒙实验室主任陈海波教授。擅长操作系统内核开发、分布式系统、嵌入式系统,对分布式数据一致性有钻深的研究,发表多篇操作系统内核相关论文,累计数百次引用。毕业后曾在谷歌中国、微软亚太和阿里巴巴等公司从事分布式计算和存储等相关工作。入选 2022 年度 6 氪 S 级创业者名册,荣获中国“企业工具与底层软件”领域 “36 位 36 岁以下创业者“称号。
本次直播我们将在【腾讯会议】进行,欢迎大家观看,没时间观看直播的同学可以关注回放,会议结束后回放在阅码场官网上传,年卡阅码场会员和其他阅码场训练营专业群资深用户免费点播。
转发本文,文末留言提问、加群提问、或者现场提问,我们将赠送 1 本书,数量有限,送完为止。
↓ 扫码加入本次直播交流群;
-咨询的小伙伴,可添加小月@阅码场的微信 Linuxer2016 咨询
`;export{a as assetURLs,o as default,c as metadata,l as toc}; +咨询的小伙伴,可添加小月@阅码场的微信 Linuxer2016 咨询
`;export{a as assetURLs,n as default,c as metadata,l as toc}; diff --git a/zh-cn/assets/index-cc44974b.js b/zh-cn/assets/index-39a462da.js similarity index 88% rename from zh-cn/assets/index-cc44974b.js rename to zh-cn/assets/index-39a462da.js index 6662ee7..8dda345 100644 --- a/zh-cn/assets/index-cc44974b.js +++ b/zh-cn/assets/index-39a462da.js @@ -1,4 +1,4 @@ -const p="/zh-cn/assets/cover-9e502538.png",n="/zh-cn/assets/image1-09ca1c97.jpg",t="/zh-cn/assets/image2-f93efd4a.jpg",s="/zh-cn/assets/image1-50beaba8.png",o=[p,n,t,s],a={label:"SpinalHDL的使用和开发经验研讨会",description:"SpinalHDL始于2014年,最初是作为VHDL/Verilog的替代而做的创新尝试,伴随着数年来开源硬件设计的蓬勃发展,基于开源技术的硬件设计方法和范式逐渐受到业界的关注。",cover:"./cover.png",location:"中国香港",date:"2023-07-03",title:"SpinalHDL usage and development experience workshop"},r=[],g=`SpinalHDL 始于 2014 年,最初是作为 VHDL/Verilog 的替代而做的创新尝试,伴随着数年来开源硬件设计的蓬勃发展,基于开源技术的硬件设计方法和范式逐渐受到业界的关注。
+const a="/zh-cn/assets/cover-9e502538.png",n="/zh-cn/assets/image1-09ca1c97.jpg",s="/zh-cn/assets/image2-f93efd4a.jpg",t="/zh-cn/assets/image1-50beaba8.png",p=[a,n,s,t],o={label:"SpinalHDL的使用和开发经验研讨会",description:"SpinalHDL始于2014年,最初是作为VHDL/Verilog的替代而做的创新尝试,伴随着数年来开源硬件设计的蓬勃发展,基于开源技术的硬件设计方法和范式逐渐受到业界的关注。",cover:"./cover.png",location:"中国香港",date:"2023-07-03",title:"SpinalHDL usage and development experience workshop"},r=[],g=`SpinalHDL 始于 2014 年,最初是作为 VHDL/Verilog 的替代而做的创新尝试,伴随着数年来开源硬件设计的蓬勃发展,基于开源技术的硬件设计方法和范式逐渐受到业界的关注。
达坦科技(DatenLord) 致力于打造高性能跨云存储,其通过软硬件深度融合的方式打破云之间的壁垒,实现高性能跨云数据访问,提供海量异地、异构数据的统一存储访问机制,为云上应用提供高性能安全存储支持。
达坦科技采用硬件加速提升存储性能,目前采用 FPGA、ASIC 实现存储相关场景的性能加速。SpinalHDL 是达坦科技在产品中使用的硬件描述语言之一,达坦科技也一直热心于推广 SpinalHDL 在业界的落地应用。在 2022 年 12 月,达坦科技曾联合 SpinalHDL 社区举办一场题为《SpinalHDL 应用前景探索》的线上研讨会,收获海内外 SpinalHDL 爱好者的欢迎。
而在北京时间 2023 年 7 月 7 日下午 14:00-17:00,达坦科技将联合 SpinalHDL 社区,以及四川芯测电子技术有限公司举办一场题为 SpinalHDL 的使用和开发经验研讨会,旨在和大家分享 SpinalHDL 最新的实践、挑战和经验的分享。
@@ -11,6 +11,6 @@ const p="/zh-cn/assets/cover-9e502538.png",n="/zh-cn/assets/image1-09ca1c97.jpg"无法到现场的观众,也欢迎观看在线直播分享:
直播预约:腾讯会议+视频号
474-6575-9473
对开源硬件感兴趣的朋友,可以添加小助手微信,加入达坦科技硬件群。
-`;export{o as assetURLs,g as default,a as metadata,r as toc}; +`;export{p as assetURLs,g as default,o as metadata,r as toc}; diff --git a/zh-cn/assets/index-28c77317.js b/zh-cn/assets/index-405a2dbf.js similarity index 96% rename from zh-cn/assets/index-28c77317.js rename to zh-cn/assets/index-405a2dbf.js index 62e9054..b354475 100644 --- a/zh-cn/assets/index-28c77317.js +++ b/zh-cn/assets/index-405a2dbf.js @@ -1,4 +1,4 @@ -const n="/zh-cn/assets/cover-99998007.jpg",s="/zh-cn/assets/image1-6f9cec09.jpg",t=[n,s],e={label:"精彩回顾|硬件敏捷开发与验证方法学研讨",description:"8月27日,作为2022年第二届RISC-V中国峰会的同期活动,达坦科技成功举办硬件敏捷开发与验证方法学研讨。虽然是线上分享活动,但大家热情依旧,会后在“硬件敏捷开发和验证方法学讨论群”中积极互动提问。长达四小时的就新一代HDL在数字芯片设计方面的实践经验分享,究竟碰撞出了什么新的火花呢?下面我们一起来回顾研讨会的精彩内容。",cover:"./cover.jpg",location:"中国香港",date:"2022-09-08",title:"Discussion on Hardware Agile Development and Verification Methodology"},a=[{label:"芯片敏捷设计与验证之路",level:2},{label:"香山处理器敏捷开发与验证实践",level:2},{label:"通过 Chainsaw 实现硬件算子敏捷开发",level:2},{label:"Scala 在 IC 开发中的应用",level:2},{label:"NaxRiscv CPU: Introduction and Extension Demonstration",level:2},{label:"结束语",level:2}],o=` +const n="/zh-cn/assets/cover-99998007.jpg",s="/zh-cn/assets/image1-6f9cec09.jpg",e=[n,s],t={label:"精彩回顾|硬件敏捷开发与验证方法学研讨",description:"8月27日,作为2022年第二届RISC-V中国峰会的同期活动,达坦科技成功举办硬件敏捷开发与验证方法学研讨。虽然是线上分享活动,但大家热情依旧,会后在“硬件敏捷开发和验证方法学讨论群”中积极互动提问。长达四小时的就新一代HDL在数字芯片设计方面的实践经验分享,究竟碰撞出了什么新的火花呢?下面我们一起来回顾研讨会的精彩内容。",cover:"./cover.jpg",location:"中国香港",date:"2022-09-08",title:"Discussion on Hardware Agile Development and Verification Methodology"},o=[{label:"芯片敏捷设计与验证之路",level:2},{label:"香山处理器敏捷开发与验证实践",level:2},{label:"通过 Chainsaw 实现硬件算子敏捷开发",level:2},{label:"Scala 在 IC 开发中的应用",level:2},{label:"NaxRiscv CPU: Introduction and Extension Demonstration",level:2},{label:"结束语",level:2}],a=`8 月 27 日,作为 2022 年第二届 RISC-V 中国峰会的同期活动,达坦科技成功举办硬件敏捷开发与验证方法学研讨。虽然是线上分享活动,但大家热情依旧,会后在“硬件敏捷开发和验证方法学讨论群”中积极互动提问。长达四小时的就新一代 HDL 在数字芯片设计方面的实践经验分享,究竟碰撞出了什么新的火花呢?下面我们一起来回顾研讨会的精彩内容。
华南理工大学计算机科学与工程学院赖晓铮副教授首先分享了 “让硬件设计像软件设计一样简单”的愿景,即开发人员编写的代码只占工作量的 10%,剩下 90%由开源芯片生态系统提供。
@@ -23,4 +23,4 @@ const n="/zh-cn/assets/cover-99998007.jpg",s="/zh-cn/assets/image1-6f9cec09.jpg"请点击如下链接:
https://t.elecfans.com/live/2113.html收看本次研讨会的回放。
也欢迎添加小助手微信,加入“硬件敏捷开发和验证方法学讨论群”,进行延伸讨论与互动,并第一时间获得后续相关活动的讯息。
随着芯片技术自主可控成为国家重要的战略发展规划,对芯片设计相关领域的人才需求也在快速增长。体系结构课程相对于硬件设计的重要性可以类比于设计模式相对于软件设计的重要性,扎实的体系结构基础是设计复杂硬件的基石。然而现实情况是,虽然国内大专院校计算机学科、电子工程学科、微电子等都有开设体系结构或组成原理等相关课程,但由于前些年对相关教学重视度不够,导致教学实践环节存在诸多缺失,毕业生掌握的技能与工业界的期望之间存在较大差距。
由此,在 2023 年伊始,达坦科技发起成立了 MIT 体系结构公开课学习社区,邀请所有对硬件敏捷开发设计感兴趣的同学加入我们,组成拥有共同学习目标的互助自学小组,一起系统地学习计算机体系结构相关知识,并且通过动手项目来验证学习的成果。
@@ -46,4 +46,4 @@ const e="/zh-cn/assets/cover-2326b9d3.jpg",t="/zh-cn/assets/image1-62ba36d5.png"报名成功后,将收到邮件确认及学号。
关于 MIT 体系结构公开课学习社区项目有任何问题或疑问,可以邮件:ta@datenlord.com或添加DatenLord 小助手微信咨询。
-`;export{s as assetURLs,c as default,n as metadata,a as toc}; +`;export{l as assetURLs,c as default,n as metadata,a as toc}; diff --git a/zh-cn/assets/index-49be6f7a.js b/zh-cn/assets/index-49be6f7a.js new file mode 100644 index 0000000..b6214ae --- /dev/null +++ b/zh-cn/assets/index-49be6f7a.js @@ -0,0 +1,212 @@ +const l="/zh-cn/assets/cover-78ccac63.jpg",p="/zh-cn/assets/image1-bf7fa473.png",i="/zh-cn/assets/image2-1161bb88.png",a="/zh-cn/assets/image3-136f9458.png",e="/zh-cn/assets/image4-75f70bf1.png",o="/zh-cn/assets/image5-64f0abbf.png",n="/zh-cn/assets/image6-29b079bb.png",t="/zh-cn/assets/image7-f8d2626b.png",s="/zh-cn/assets/image8-d242f7b7.png",c="/zh-cn/assets/image9-5e691a52.png",r="/zh-cn/assets/image10-b3a0ad40.png",g="/zh-cn/assets/image11-98ffaf6b.png",D="/zh-cn/assets/image13-d816729e.png",H="/zh-cn/assets/image14-20340934.png",h="/zh-cn/assets/image15-512cff4d.png",L="/zh-cn/assets/image16-ee33a0ea.png",S="/zh-cn/assets/image17-e2c28396.png",m="/zh-cn/assets/image18-69fe4409.png",V="/zh-cn/assets/image19-dfed79f8.png",C="/zh-cn/assets/image20-a636b8b5.png",b="/zh-cn/assets/image21-487e6dd2.png",y="/zh-cn/assets/image22-27167bbd.png",d="/zh-cn/assets/image23-8660cc2c.png",P="/zh-cn/assets/image24-4d2461fd.png",f="/zh-cn/assets/image25-3af02a99.png",z="/zh-cn/assets/image26-a854b9f0.png",v="/zh-cn/assets/image27-5b3ff402.png",I="/zh-cn/assets/image28-f02ef5c0.png",R="/zh-cn/assets/image29-44cafcf0.png",u=[l,p,i,a,e,o,n,t,s,c,r,g,D,H,h,L,S,m,V,C,b,y,d,P,f,z,v,I,R],A={label:"使用SpinalHDL和Cocotb进行敏捷数字芯片设计和验证",description:"领域特定架构已成为计算机发展的一种趋势。在提供更高效算力的同时,它也给底层硬件的开发带来了更大的挑战。传统的芯片设计和验证技术已越来越无法应对这些新的要求和挑战。在芯片设计上,本文将介绍如何使用SpinalHDL,一种基于Scala的新型硬件描述语言(HDL),或者更准确地说是硬件构造语言,提高硬件设计的效率和质量。对于SpinalHDL,本文还介绍了如何利用Scala的类型系统高效地进行复杂硬件的设计。对于验证,本文将介绍基于Python的验证环境Cocotb,以及如何利用Python简洁高效的语言特性及其繁荣的开源社区,提升芯片验证的效率。",cover:"./cover.jpg",location:"新疆",author:["翁万正等"],date:"2024-01-25",title:"Agile Digital Chip Design and Verification with SpinalHDL and Cocotb"},T=[{label:"引言",level:2},{label:"1.1 背景",level:3},{label:"1.2 HDL的演变",level:3},{label:"SpinalHDL",level:2},{label:"2.1 SpinalHDL简介",level:3},{label:"2.2 与传统HDL相同的描述粒度",level:3},{label:"2.3 SpinalHDL相比传统HDL的优势",level:3},{label:"基于元语言构建数字逻辑电路",level:2},{label:"3.1 元语言的概念",level:3},{label:"3.2 硬件设计中的高级类型系统",level:3},{label:"3.3 SpinalHDL之外",level:3},{label:"3.4 HCL的编译流程",level:3},{label:"基于Cocotb的验证",level:2},{label:"4.1 Cocotb简介",level:3},{label:"4.2 基于Cocotb硬件验证的优势",level:3},{label:"4.3 基于Cocotb的验证示例",level:3},{label:"4.3.3 启动仿真",level:3},{label:"结论",level:2},{label:"参考文章",level:2}],F=` +摘要:
+领域特定架构已成为计算机发展的一种趋势。在提供更高效算力的同时,它也给底层硬件的开发带来了更大的挑战。传统的芯片设计和验证技术已越来越无法应对这些新的要求和挑战。在芯片设计上,本文将介绍如何使用SpinalHDL,一种基于Scala的新型硬件描述语言(HDL),或者更准确地说是硬件构造语言,提高硬件设计的效率和质量。对于SpinalHDL,本文还介绍了如何利用Scala的类型系统高效地进行复杂硬件的设计。对于验证,本文将介绍基于Python的验证环境Cocotb,以及如何利用Python简洁高效的语言特性及其繁荣的开源社区,提升芯片验证的效率。
近年来,计算需求不断演进并且多样化。就高性能计算而言,过去二十年间,互联网的迅速扩张产生了大量的数据,而深度学习等技术提供了许多有效利用这些数据的方法。然而,这些技术的实现对大规模高性能计算能力有着强烈的需求。例如,深度神经网络发展中的一个里程碑AlexNet的实现,很大程度上依赖于Nivida GPU的使用,后者为运行这一模型提供了足够的计算能力。与此同时,在工业应用中,提供节能型硬件以降低成本同时提供高计算能力也是相当重要的。在低功耗计算方面,随着物联网的快速发展,芯片的应用场景变得多样化,我们希望为每种场景选择最适合的芯片,这提出了多样化的芯片开发需求。
+随着摩尔定律和丹纳德缩放的减速,简单地通过提高CPU或GPU性能来实现这种计算能力的增长已经不能满足需求。而且,简单地将低功耗CPU部署到边缘场景无法满足低功耗和定制功能的需求。因此,许多特定领域架构设计任务出现了,其中大部分呈现出软硬件协同设计的范式。硬件架构的研究和设计成为业界和学术界的热门话题,毫无疑问,当前正处于架构创新的黄金时代。这也是硬件描述语言(HDL)创新最好的时代,因为HDL是描述计算机架构最直接的方式,我们需要更高效的HDL来加快我们的架构设计实现。
+与这些新兴的设计需求相比,目前业界主流的设计工具远远落后。Verilog和VHDL已经超过30年历史了,而SystemVerilog在设计方面只是对Verilog进行了一些小修改。与C等经典语言不同,Verilog/VHDL并没有通过多个版本的迭代演进,也没有发展大量的第三方库来补充语言,因此在很大程度上,我们使用Verilog/HDL时仍然像它们最初发布时一样。
+1.2.1 主流HDL的历史
+传统HDL的历史可追溯到20世纪60年代,其中在20世纪80年代发布的Verilog和VHDL是最受欢迎的两种语言。Verilog和VHDL被认为是HDL的黄金标准,因为几乎所有电子设计自动化(EDA)工具都广泛支持它们。
+最初,Verilog和VHDL用于记录和模拟以其他形式捕获和描述的电路设计,比如原理图文件。换句话说,它们并不是为了描述数字同步集成电路(IC)的RTL级模型而设计的。Verilog和VHDL的“读者”被认为是一个模拟器,而不是一个综合工具或工程师。在实践中,逻辑综合为HDL的引入将HDL从后台推到了数字硬件设计的前台,为此添加了“可综合”规则,但这些规则从未成为语言标准的一部分。
+21世纪的第一个十年见证了SystemVerilog的出现,它是Verilog的超集。在验证方面,SystemVerilog借鉴了许多高级语言的特性,例如面向对象、更丰富的类型系统等。然而,在设计方面,它只是添加了一些功能,例如:
+尽管如此,这些新引入的SystemVerilog设计功能直到现在也没有得到EDA供应商的全面支持,因此单独这些变化并不能使其具备处理复杂的软硬件协同设计任务的能力。
+1.2.2 其他HDL的历史
+与Verilog/VHDL不同,功能型HDL可以追溯到上世纪70年代,最早用于硬件形式化。众所周知,最早用于描述硬件的记号系统可以追溯到约翰·李的著作《计算机语义学》。与早期不同的是,自上世纪90年代以来,开发新的用于数字硬件设计的HDL有两个主要趋势:首先,鉴于Verilog和VHDL是主流EDA的事实标准,为了避免构建新的特定于某种语言的工具链,开发者选择首先生成Verilog/VHDL代码,然后使用生成的代码进行后续流程,包括综合和实现。在这种情况下,Verilog/VHDL的作用类似于汇编语言或新HDL与现有工具链之间的接口层。更精确地说,这些新的HDL,如Spinal、Chisel和Clash,通常被定义或称为HCL(HCL:Hardware Construction Language)。在本文中提到的HCL仍然是HDL的一部分,因为它们可以执行HDL的所有功能。这意味着单个HCL的内容必须是Verilog/VHDL核心部分的超集。
+其次,与从头开始不同,大多数这些新的HDL都嵌入到流行的高级编程语言中,或更准确地说,它们可以被视为高级程序语言的库。因此,它们可以重用现有成熟语言的基础设施,包括它们的编译器、测试系统、包管理系统、IDE(IDE:集成开发环境),以及最重要的是它们的社区。这种策略降低了学习的难度,并使这些新的HDL非常可扩展。例如,Lava(及其方言)和Clash嵌入到Haskell中,Chisel和SpinalHDL嵌入到Scala中,MyHDL嵌入到Python中。
+正如上面提到的,SpinalHDL[3]是基于Scala的HCL,或更准确地说,是Scala中的一个包,专用于数字芯片设计。与Chisel类似,SpinalHDL也是基于Scala的,并且主要用于RISC-V CPU设计。在Spinal中设计硬件的过程主要可以分为三个步骤:1)使用Scala和SpinalHDL包来描述硬件设计的结构和逻辑;2)编译和执行Scala程序,生成对应的SystemVerilog/VHDL代码,该代码与Scala代码描述的结构相同;3)使用任何类型的模拟器,如Iverilog、Verilator或Synopsys VCS,进行硬件模拟和验证。SpinalHDL基于传统的Verilog或VHDL进行硬件设计过程。Scala程序不能直接用于硬件模拟,而是需要首先执行以生成Verilog或VHDL代码,这意味着现有丰富的基于Verilog的设计工具链,包括模拟器、综合器和FPGA开发套件,可以在整个设计过程中使用。
+ +图1:基于SpinalHDL的设计流程
+与软件开发相比,SpinalHDL对于以Verilog为代表的传统HDL来说就像Java、C/C++和Python等高级编程语言对汇编语言的作用一样。显然,高级语言比汇编语言更具表达力和生产力,并大大降低了开发复杂软件系统(如操作系统)的难度。尽管高级编程语言提高了软件开发的效率,但与汇编语言相比,程序的性能也受到了很大的牺牲。类似地,与传统HDL相比,SpinalHDL具有各种优势,并提高了设计数字硬件的效率。然而,与高级语言不同的是,它不会牺牲生成的硬件的性能和资源利用率,而是简化和加速设计过程。SpinalHDL与传统HDL(如Verilog或VHDL)几乎具有相同的描述精度或粒度。它可以精细控制寄存器的数量和寄存器之间的逻辑路径的长度。关于近似描述粒度的最佳证明是,对于Verilog/VHDL中的所有RTL级语法元素,SpinalHDL都有对应的对应元素。为了明确起见,我们在图2中显示了RTL级描述的所有基本元素,并在表1中列出了从SpinalHDL到Verilog的映射。如图2所示,RTL级描述是具有一个或多个时钟域的同步数字系统的形式化定义,基本上由以下五个部分组成:
+图2:RTL级别描述中的元素。
+对于这五个部分中的每一个,SpinalHDL提供了完整的相同描述能力,列在表1中。对于最坏情况,尤其是对于初学者来说,您可以使用SpinalHDL作为带有不同关键字集的Verilog/VHDL。因此,对于因语义失真而导致性能损失的担忧是不必要的。
+ +表1:从SpinalHDL到Verilog的映射。
+2.3.1 可靠性
+使用SpinalHDL可以大大提高程序的可靠性,减少错误的可能性,从而减少验证和调试所花费的时间,加快项目开发的速度。SpinalHDL生成的代码的可靠性来自于以下方面:更精确的模型:对于表1中的时序类别,包括寄存器和内存,在Verilog中没有直接的语法元素。实际上,对于Verilog而言,寄存器的实现要求综合工具根据always关键字的敏感性列表中信号的行为推断出时序部分。这一思想,请见图3所示。
+ +图三:在 Verilog/VHDL 中设计寄存器的笨拙流程
+在实践中,Verilog的用户有时会通过将寄存器和内存封装在模块中并实例化它们来确保正确的描述。但是在SpinalHDL中,这些已经在语言层面上实现。为了避免使用令人困惑的always块和敏感性列表,SpinalHDL还直接描述了时钟域和时序元素。与此同时,Verilog中的阻塞和非阻塞赋值已经不再必要,可以在SpinalHDL代码的任何地方应用相同的赋值方法“:=”(我们更愿意称其为“连接”或“驱动”)。
+此外,SpinalHDL为信号提供了更丰富的类型系统,通过这些更具体的定义,将类型与其行为绑定在一起。信号不仅可以通过Verilog中的“wire”或“reg”进行定义,还可以通过Spinal中的“Bits”、“Bool”、“UInt”、“SInt”和“Vec”进行定义,并且通过这些更具体的定义具有更明确的语义。例如,“Bits”和“UInt”都表示具有多位的信号,但是只能在“UInt”类型中应用算术运算,不允许对“Bits”进行计算。
+更早的设计规约检查:有了更精确的模型,可以在设计流程的早期阶段检查更多的设计规约,包括:
+分离设计元素和仿真元素:鉴于Verilog和VHDL最初是为仿真和文档编写而开发的,一些语法元素必须在设计和仿真中发挥双重作用。出于向后兼容性考虑,类似SystemVerilog的Verilog更新无法解决这个问题。尤其对于初学者来说,很容易混淆可综合和不可综合的Verilog语法。
+一个例子是对'if/else'的使用。在Verilog中,它们被用于模拟软件条件和硬件复用器,这有时会引起混淆。在SpinalHDL中,我们使用'when/elseWhen/others'来模拟硬件复用器,因此可以“自由”地使用'if/else'来表示软件条件。
+一般来说,SpinalHDL中没有“可综合”这样的概念,只要代码可以执行并生成Verilog代码,它就自然“可综合”。唯一的例外是内存的行为可能不是“可综合”的,这取决于FPGA架构或提供给ASIC的工艺库。
+总结来说,通过以上特性,Verilog/VHDL编码的许多设计规则成为了语言本身的内置特点。因此,设计者不需要刻意记住和遵循这些规则,从而能够产生更可靠的代码。
+2.3.2 更强的表达能力
+在参数设计方面,SpinalHDL的表达能力优势主要体现在以下几个方面:在Verilog/VHDL中,通过使用参数/泛型来实现参数化(因此是广义的)设计,但是对于复杂的参数化要求,仅在原始的Verilog/VHDL源代码中“替换”一系列参数是不够的。另外,时不时地实例化复杂设计可能会非常令人沮丧。一个典型的例子是Xilinx DSP48E2模块的实例化模板,其中有50多个参数,构成了一个巨大的参数空间,但其中只有几个是有意义的。一方面,仅通过列出这些参数来定义设计是耗时且费力的。另一方面,由于参数之间的关系没有受到内置方法的约束(Xilinx有数百页的文档来描述约束),因此容易出错。
+Xilinx提供了几个带有相应初始化模板的IP,以帮助用户配置DSP功能,并在IP生成过程中使用高级语言并提供GUI界面。如果一开始就使用类似于SpinalHDL这样的生成器语言来描述模块,则可以节省额外的GUI程序,并且可以以更紧凑的方式实现整个项目,避免引入黑盒(IPs)。具体来说,我们可以在SpinalHDL中设计一个配置类来管理各个配置项及其之间的约束关系。
+软硬件协同设计的能力:软硬件协同设计适用于复杂算法的硬件实现。复杂的软硬件协同设计需要根据算法的需求灵活实现硬件。我们简要总结这种协同工作为以下几种情况:如图4所示,在最简单的情况下,算法决定硬件参数的生成方式。
+ +图4:软硬件协同设计的最简单情况。
+在更复杂的情况下,许多硬件设计本身无法直接描述,但可以通过算法来描述。例如各种网络拓扑、并行算法等。算法不仅确定了硬件的参数,还确定了硬件应包含的部分、不应包含的部分以及如何进行结构和路由。这要求我们的硬件描述语言也能够容纳更复杂的算法。仅通过带有参数的Verilog无法实现这种程度的协同工作。
+另外,硬件设计的另一个考虑因素是并行性。如果我们的应用程序有一个高效的并行算法,往往可以将算法重写为硬件生成算法,这将大大减少设计时间并提高设计可靠性。在SpinalHDL中,可以通过来自您组织或第三方库的可靠Scala/Java算法来实现这一点。
+强大的生成能力:SpinalHDL通过使用Scala语言的特性来实现算法的复杂硬件生成,包括:
+图5:Benes网络硬件:开关、路由和控制字ROM。
+在图5中,我们以Benes网络的硬件结构为例,说明了这些特性带来的好处:在此硬件的设计中,上述每种语言特性的特定应用被指定:
+使用Verilog/VHDL几乎不可能完成这个设计。但是通过HCL来完成是很常见的,因为实际上,设计者是使用高级语言作为Verilog生成器而不是直接描述硬件结构。
+近年来,领域特定的加速器设计已成为一个重要的课题。这些任务基本上以“将算法实现映射到硬件”形式表达。由于SpinalHDL的便利性,这些特性变得越来越重要,能够更好地实现复杂算法的实现。
+2.3.3 可重用性:
+与传统的硬件描述语言相比,SpinalHDL具有更好的可重用性,可以极大地提高开发效率。具体而言,通过SpinalHDL的更好可重用性,你可以更方便地在现有的高质量代码的基础上构建自己的设计。同时,通过逐步建立自己的代码库,你可以积累自己的能力和经验。随着时间的推移,你在重复性工作上花费的时间越来越少,更多的精力可以用来解决有价值的问题。只有在低成本的代码重用情况下,才能形成和发展一个开源硬件社区。SpinalHDL的可重用性主要来自以下几个方面:
+一些基本设计元素的良好封装:SpinalHDL本身为我们提供了一些基本且频繁使用的元素的良好封装,例如StateMachine、Stream、Flow和多种类型的总线。通过使用这些良好封装,你不必从头开始构建设计,这可以提高效率并减少错误的可能性。
+例如,SpinalHDL提供了方便的控制路径和数据路径的抽象,通过将它们建模为Stream,你可以将控制路径和数据路径视为从SoC输入端口到输出端口的一个或多个流:(1)每个模块的数据路径是将其输入流的有效负载数据转换并再次作为流发送到其输出端口;(2)对于控制路径,通过SpinalHDL对流模型提供的丰富功能,例如暂停/阻塞、继续、丢弃、分叉、合并等,可以非常容易地操作模块的输入流,例如具有背压/流量控制的流水线,再定时等。Stream是Scala提供的一个类,控制路径的不同操作被封装为类的方法。
+这里以Stream的m2sPipe()方法为例,它帮助用户更轻松地处理流水线中易出错的valid和ready信号的操作。通过使用m2sPipe,你可以更容易地实现带有背压的流水线,以解决时序问题。m2sPipe()生成的相应硬件结构如图6所示:
+ +图6:带有背压的流水线
+另一个例子是SpinalHDL为许多总线提供了非常好的封装,例如AXI、APB等。特别是AXI非常流行且难以实现。SpinalHDL基于前面提到的流模型实现了AXI接口,并提供了许多有用的与总线相关的功能,例如交叉开关、带/不带事务锁的总线仲裁器、总线解复用器、控制寄存器的总线驱动器等等。最重要的是,SpinalHDL提供的总线接口是防错的,因为SpinalHDL可以检查信号类型、信号宽度匹配、输入/输出方向、时钟域跨界等。通过SpinalHDL提供的这些方便的组件,它极大地促进了SoC的集成。
+Scala语言特性带来的可重用性:硬件设计所面临的问题通常是高度定制的。但是通过参数/泛型在Verilog/VHDL中提供的定制能力是不足的,而Verilog的代码很难应对许多情况。同时,Verilog/VHDL的自解释性很差,在许多情况下,即使有源代码可用,很难理解和使用其他人开发的源代码。传统HDL中代码难以理解的主要原因有两点:1)Verilog/VHDL中的描述是过于底层;2)不同团队使用的设计规则不一致。
+从语言特性的角度来看,Scala更高级和更复杂的功能使得设计能够支持更复杂的生成模式,从而具有更大的通用性,更容易为多种场景设计通用设计。此外,Scala的面向对象和类型系统的特性允许开发人员以更高的层次描述设计,提高程序的自解释能力。例如,通过SpinalHDL,我们可以使用“.”来索引类的方法,并扩展自定义类型来定义各种概念,如卷积编码的格雷码。从社区和工具的角度来看,如GitHub等已建立的社区提供了自然的协作和讨论环境。而Scala的库分发和包管理系统使得代码获取和部署非常容易,例如pypi-pip和maven-sbt。
+除了代码的重用,项目团队内部的另一个重用现象是设计规则/协议的重用。SpinalHDL可以为这种重用提供以下内容:
+总之,SpinalHDL提供的可重用性不仅通过语言特性实现,还通过包括IDE工具链在内的完整社区环境和高级主机语言实现。
+硬件构建语言(如SpinalHDL、Chisel、Migen和Clash)可以被视为电路之上的元语言层,与直接描述电路的传统HDL形成对比。元语言层使得硬件设计师能够更专注于电路的语义,而不是具体的结构,使得程序和人类更容易推理设计的正确性。
+ +传统的硬件设计结构方法的问题在于它与电路的功能规格不匹配。例如,为了将乘法功能高效地添加到经过优化的FPGA经典五阶段RISC流水线中(如图7所示),对应的逻辑必须在Decode、Execute、Memory和Writeback阶段分别实现,因为FPGA上的硬件乘法器通常具有超过1个周期的延迟。如图8所示,VexRiscv项目在SpinalHDL中展示了一种更好的抽象:通过插件方法将语义指定的函数与流水线结构解耦,其中函数在其自己的Scala模块中实现,并在净表生成过程中将自己插入到流水线中。
+嵌入式深度和嵌入式浅度的硬件构造语言:硬件构造语言有两类:嵌入式深度和嵌入式浅度。广泛使用的浅度嵌入式HCL包括SpinalHDL、Chisel和Migen,而Clash是一种领先的深度嵌入式HCL。
+传统的硬件描述语言(如Verilog、SystemVerilog和VHDL)的类型系统在表达能力和约束强度方面非常有限:
+与此同时,大多数现代硬件构造语言都可以访问具有和类型、参数化多态和高阶类型的先进类型系统。
+和类型、产品类型和私有类型构造器: 产品类型(在大多数编程语言中称为struct)是一种保存不同类型的零个或多个值的数据结构。在SpinalHDL中,产品类型用于表示信号的“Bundle”,例如:
+ +图8:从语义角度看,经典的RISC流水线由寄存器文件访问、缓存访问、指令获取/解码、算术运算和其他功能组成。
+ +和类型,也称为标记联合,是一种可以容纳来自固定数量的不同类型之一的单个值并保留所容纳值的类型的数据结构。虽然Verilog和传统软件编程语言如C都没有直接支持和类型,但我们可以在C中模拟其行为:
+ +一个简单但广为人知的和类型的例子是'Option'类型:
+ +表2:从SpinalHDL到Verilog的映射。
+当存在和类型和产品类型时,可以对可表示值的集合施加约束。例如,在深度嵌入式HCL中,由“VALID”信号门控的数据信号可以使用“Option”类型表示,这样在检查“VALID”是否为“高”之前,无法读取该值。
+在浅度嵌入式HCL中,和类型只能用于电路结构而不能用于数据,但我们仍然可以使用新类型模式模拟“Option[T]”的行为。我们创建一个函数:
+ +根据值选择onSome或onNone。由于DynamicOption类型构造器是私有的,所以只需要保护值免受未经意访问的影响而不必检查VALID。
+ +子类型和参数化多态:子类型(最常见的形式是继承)是一种构建类型层级结构的机制。参数化多态,也称为泛型,是一种编写以类型为输入并以单态类型或函数为输出的类型级别函数的机制。
+SpinalHDL成功地利用了Scala中的许多构造来提高硬件设计过程的效率,但是在从硬件中抽象出属性并在编译时进行验证方面还有更多的可能性。在本节中,我们介绍了来自不同软件编程语言的各种方法,我们认为这些方法也可以使硬件设计受益。
+类型级自然数: 众所周知,自然数可以编码为类型,并且可以对其进行计算。例如,如图9所示,具有m个分支因子的n级仲裁树可以使用以下Clash类型描述:
+ +泛型参数隐含地是约束“forall”,要求实现对所有的“n”和“m”值有效。未能满足类型签名的实现几乎总是不正确的,并报告为编译时错误。
+隐式的 “forall” 对类型级自然数等泛型参数的约束的一个主要好处是防止常量的混淆,这些常量“无意中”具有相同的值。如图10所示,一个例子是将缓冲区中的所有条目与大小为“m”的另外“n”个缓冲区进行匹配:
+让我们考虑n = m的配置族。对于不支持类型级自然数的硬件构造语言(如SpinalHDL),在设计中的n和m的混淆不会被报告为编译或Verilog生成中的错误,但逻辑将默默不正确。但对于Clash,类型级自然数被广泛地集成到硬件原语(如Vec和BitVector)中,编译器将确保逻辑通过类型检查对于n和m的所有值,而不仅仅是在配置中定义的值。
+ +图9:一个8路3级仲裁树。n = 3,m = 2。
+ +图10:匹配缓冲区中的所有条目与另外“n”个大小为“m”的缓冲区。
+细化类型: 细化类型是带有谓词的类型,指定原始类型的哪些值应该是细化类型的元素。对于硬件设计,细化类型可用于传递信号的属性。一个例子是固定点算术单元。在某些情况下,我们希望限制输入端信号的范围(例如将8位信号的值限制在0-200之间),并验证输出信号满足某些约束(例如,将范围在0-200之间的输入经过乘以2的电路应该具有0-400的取值范围)。使用细化类型,我们能够使用显式范围对输入类型进行细化,并使用SMT求解器检查输出信号的属性。
+将以硬件构造语言编码的数字设计编译为可合成的电路描述。由于所有主要的商业和开源综合工具链都支持Verilog作为一流的源语言,因此对于HCL来说,使用Verilog作为编译目标并将后端处理委托给综合工具链是一种自然的选择。如图10所示,对于浅嵌入式HCL,编译流程包括以下三个步骤:
+深度嵌入式HCL的编译流程略有不同:
+图11:基于Scala的浅嵌入式HCL需要,而基于Haskell的深嵌入式HCL Clash
+Cocotb是一个基于Python的测试平台环境,用于验证VHDL、Verilog和SystemVerilogRTL设计[5]。
+Cocotb的验证框架分为两个主要部分:一个基于Python的测试平台,用于向DUT(Design Under Test)的输入端提供刺激并监控输出端口,以及用于模拟硬件设计的模拟器。Python测试平台通过模拟器的标准VPI(Verilog Procedural Interface)、VHPI(VHDL Procedural Interface)或FLI(Foreign Language Interface)与DUT在仿真中进行交互。根据其工作原理,Cocotb可以与任何实现了行业标准VPI、VHPI或FLI接口的模拟器一起使用,这意味着Cocotb可以支持从商业到开源的大多数现有模拟器,包括Iverilog、Verilator、Synopsys VCS、Mentor ModelSim等。
+除了支持不同类型的模拟器外,Cocotb相对于使用Verilog、System Verilog或VHDL进行验证具有各种优势,这些优势可以加速整个硬件设计过程。以下是Cocotb的一些显著优势:
+4.2.1 简洁高效的语言特性
+比传统的用于验证的语言如Verilog、VHDL和System Verilog更高效、更具表现力和更简洁。与使用这些传统语言编码相比,使用Python来实现复杂功能需要更少的代码。
+ +图12: 基于Cocotb的验证框架
+与此同时,Python拥有简单的语法和丰富的在线学习资料,使初学者更容易掌握。此外,Python是一种高级编程语言,具有诸多高级特性,如面向对象编程,可以帮助程序员编写更可重用的代码。
+在大多数硬件验证的情况下,C/C++被用于构建DUT的参考模型,参考模型的代码通过DPI集成到SV(System Verilog)的测试代码中。Python比其他语言(如C/C++)在构建参考模型方面更高效的一个编程场景是涉及超过64位的大整数的算术运算。密码学算法如ECC和RSA以及哈希函数通常涉及128位到2048位范围内宽度的大整数运算。C/C++中的原始类型仅支持最大64位的数字。如果使用C/C++构建您的参考模型,处理这些大整数将会很麻烦。下面的C程序实现了两个超过64位宽度的大整数的加法运算:
+ +对任意位宽整数的加法操作的Python实现:
+ +在C程序中,超过64位宽度的整数以数组的格式存储,对这些数字进行加法和乘法等运算需要对数组的每个元素进行操作。然而,Python中的整数支持任意位宽,并且可以使用算术符号直接计算这些大整数的算术运算,而无需额外的代码。还有许多其他情况下,Python可以加速构建参考模型并减少错误的可能性。尽管Python在性能方面可能略逊于C/C++,但在硬件验证中,准确性和效率更为重要。
+4.2.2 繁荣的开源社区
+Python在许多编程场景中被广泛应用,并且具有多种类型的库或包。使用Cocotb,将这些现有的基于Python的算法或模型实现作为硬件设计的黄金模型进行重用是非常直接的。或者基于现有的Python库或包来构建参考模型也更加方便。例如,在设计深度学习加速器时,可以将Pytorch、Tensorflow和Caffe等Python库与Cocotb测试平台轻松结合。对于一些用于SoC集成的复杂总线协议(如AXI、PCIe等)的验证,Cocotb提供了相应的开源库。通过重用现有的Python库来构建黄金模型有两个显著的优势:
+图13: Cocotb验证中使用的不同包
+除了便于构建参考模型外,还有许多开源的Python库和包可以帮助我们编写、组织和执行验证代码。在芯片验证过程中,与模拟器进行交互并在其上执行测试台是不可避免的。Cocotb自身提供了一个Makefile模板,帮助开发人员在不使用特定的Linux命令的情况下与模拟器进行交互。编写和执行Makefile以使代码在模拟器上运行仍然有点麻烦。但是,cocotb-test包封装了对模拟器的操作,并将其作为Python函数提供给开发人员。使用cocotb-test包,用户只需要调用一个Python函数并指定其参数即可启动模拟,为cocotb提供了标准的Python单元测试功能。
+基于使用cocotb-test包,您可以使用pytest更高效地编写和管理测试程序,pytest是一个实现了完整功能的成熟Python测试工具的Python包。此外,您还可以使用pytest-xdist或pytest-parallel包在多核处理器上并行运行您的验证代码,这有助于充分利用计算能力以减少执行时间。同时,pyuvm包已经实现了UVM(通用验证方法学)的主要部分,UVM是业界最广泛使用的验证框架。基于cocotb和pyuvm,开发人员可以使用Python而不是SystemVerilog来应用UVM方法学进行验证。
+验证是整个芯片开发过程中不可或缺且至关重要的一部分,尤其在工业领域,它占据了芯片项目的大部分工作量。因此,已经有许多尝试来提高硬件验证的效率和速度。Cocotb试图提供一个用于验证的Python环境或平台。基于这个平台,您可以享受Python简洁语法和繁荣的社区带来的便利,从而大大加速验证过程。
+在本部分中,我们介绍了一种基于Cocotb的验证的具体示例,被测试的设计是用System Verilog实现的矩阵乘法器。DUT的参数和接口分别列在表3和表4中:
+ +表3:被测试矩阵乘法器的参数
+ +表4:被测试矩阵乘法器的接口
+4.3.1 构建参考模型
+矩阵乘法器的参考模型可以基于numpy实现,它是一个广泛应用的Python包,提供了丰富的矩阵运算功能。利用numpy,可以直接使用方法“matmul”来实现矩阵乘法,无需使用循环语法。参考模型的具体Python实现如下:
+ +4.3.2 搭建验证平台
+基于Cocotb构建的简单验证平台结构如下图所示。验证平台主要包括四个部分:1)驱动器;2)监控器;3)参考模型;4)缓冲区。驱动器使用Python包random生成随机的输入信号,包括“valid i”、“a i”和“b i”。当“valid i”为高电平时,生成的“a i”和“b i”被发送到参考模型,并获取相应的参考输出。参考输出通过Python包Queue实现的缓冲区存储,一旦输出信号“valid o”为高电平,监控器会抓取DUT的输出端口,并将其值与从缓冲区中取出的参考输出进行比较。驱动器和监控器的功能都是通过Python的协程实现的,类似于多线程,并且可以并行执行。
+ +图14:基于Cocotb的验证平台结构
+基于Cocotb的验证代码可以通过Makefile在仿真器上启动,而无需直接与仿真器进行交互。此外,使用cocotb-test包中提供的“simulator.run”方法,可以直接在Python函数中启动验证过程。然后可以直接运行该函数,或者使用pytest,一个成熟的Python测试框架,来管理所有测试的执行。
+ +一些pytest命令来管理测试单元的执行:
+ +本文主要讨论了基于新兴的开源工具SpinalHDL和Cocotb的数字硬件设计和验证,我们相信这些工具可以改变传统芯片开发过程。硬件设计的需求越来越多样化,但设计语言和工具并未明显改进。SpinalHDL和Cocotb试图将一些先进和高效的软件设计概念和方法引入到硬件开发流程中。与基于System Verilog或VHDL的传统设计和验证方法相比,SpinalHDL和Cocotb可以显著提高硬件开发的效率和质量。
+值得注意的是,SpinalHDL不是一种新的高级综合(HLS)工具,而是与Verilog或VHDL具有相同的描述层次。结合我们使用Spinal的开发经验,总结了它相对于Verilog和VHDL的三个主要优势,包括可靠性、表达性和可重用性。关于可靠性,Spinal可以提供更精确的基本电路元素抽象,在编译过程中提前检查一些设计规则,并分离设计和仿真元素。在表达性方面,SpinalHDL建立在Scala上,这是一种高级编程语言。基于Scala的特性,包括面向对象、函数式编程、递归和丰富的集合类型,更容易让硬件开发人员实现和参数化他们的设计。在可重用性方面,SpinalHDL本身提供了对常用电路元素的丰富封装来实现重用。对于设计师来说,使用Scala及其相关工具链更容易生成更具可重用性的代码和构建自己的代码库。
+至于Cocotb,它相对于传统的验证工具有两个主要优势。与Scala类似,Python是一种具有简洁语法、高度表达能力和一些先进语言特性的高级编程语言,极大地便利了硬件设计的验证。更重要的是,Python在许多编程案例中广泛应用,并拥有强大而繁荣的社区。基于现有丰富的Python包和库构建验证更加方便。
+[1] J. Bachrach, H. Vo, B. Richards, Y. Lee, A. Waterman, R. Aviˇzienis, J. Wawrzynek, and K. Asanovi´c, “Chisel: Constructing hardware in a scala embedded language,” in DAC Design Automation Con-ference 2012, 2012, pp. 1212–1221. +[2] A. Krizhevsky, I. Sutskever, and G. E. Hinton, “Imagenet classification with deep convolutional neural networks,” in Advances in Neural Information Processing Systems, F. Pereira, C. J. C. Burges,L. Bottou, and K. Q. Weinberger, Eds., vol. 25. Curran Associates, Inc., 2012. +[3] SpinalHDL, +“https://github.com/spinalhdl/spinalhdl.” +[4] B. J. Rosser, +“Cocotb: a python-based digital logic verification framework,” 2018. +[5] Cocotb, +“https://github.com/cocotb/cocotb.”
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+Science Technology
+摘要: bsc编译器是一个商业可用的编译器,在过去的二十年中被广泛使用,于2020年1月作为免费开源工具发布。本文简要介绍了bsc及其流程,提供了可用的教程材料,并介绍了多个可重用的开源设计案例,其中许多设计聚焦在RISC-V上(覆盖了从嵌入式到支持Linux的CPU和系统),所有设计均可部署在FPGA上。
+自2000年以来,bsc编译器及其库就一直在作为一款商业软件被开发。二十余年来,它曾是Bluespec公司的一款授权产品,尽管学术和研究许可证一直以来都是免费提供的。几家顶级半导体供应商和一家主要的搜索公司曾使用bsc来设计最新ASIC SoCs中复杂的IP。它被许多公司用于基于FPGA的原型开发,并且在许多大学里用于构建体系结构和复杂IP的研究。
+2020年1月,Bluespec公司以BSD 3-Clause许可证的形式免费开源了编译器、库以及一个图形用户界面。这些可以在以下网址找到:
+https://github.com/B-Lang-org/bsc
+https://github.com/B-Lang-org/bsc-contrib
+https://github.com/B-Lang-org/bdw
+bsc编译器接受以高级硬件描述语言BSV和BH(如下所述)编写的设计作为输入,并生成可用于标准RTL工具(仿真、综合、形式分析等)处理的Verilog代码。
本文将简要介绍BSV和BH、bsc及其流程,以及使用BSV/BH编写的几个免费开源设计。其中,许多设计都是RISC-V设计(包括CPU、IP和系统),并且这些设计都是高度可复用的,并可在FPGA上运行。
+BSV和BH起源于20世纪90年代在麻省理工学院的研究中[10],当时James Hoe和Arvind确认了将并发原子事务表达的行为编译高质量Verilog的可行性。这是很有吸引力的,因为它给对复杂并发系统进行形式化规范说明和分析的行为模型(例如,TLA+ [11],Event-B [12],UNITY [7])提供了一种选择。由于能够将这样的形式化规范说明编译成高质量的硬件,它可以成为自动化实现形式规范说明到实际硬件之间的桥梁。
+启用组合形式验证一直是BSV/BH的核心动机和特性(例如,请参见MIT的Kami项目,网址为https://github.com/mit-plv/kami)。原子事务语义还能够在日常的非形式化验证中帮助工程师增强系统的正确性。
+在2000年,Lennart Augustsson在一种新的语言BH(Bluespec Haskell)中实现了这些想法,该语言使用Haskell的语法和语义,包括具有多态和类型类的类型系统、单子和高阶函数,从而使其具有静态展开能力和非常强大的类型抽象和类型检查能力[2],[14]。
+在2004-2005年,我们创建了BSV,它只是一种新的,类似于SystemVerilog的前端语法[6],但在其他方面保留了BH的类似于Haskell的表达能力。
+在2005年,我们引入了对多个时钟和复位域的支持。强类型检查确保不可能将时钟和复位信号与普通信号混合在一起。通过bsc的静态检查保证了正确的时钟域规范。
+BSV/BH、VHDL、Verilog、SystemVerilog和Chisel[3]都是硬件描述语言(HDL):设计者直接描述架构和微架构。在这方面,它们与所谓的“HLS”(高级综合)[9]完全不同,HLS工具会自动生成架构和微架构(这可能是在设计者的高级指导下进行的)。但这并不意味着HDL必须是低级的:强大的抽象和组合机制允许像描述低级微架构一样流畅地描述高级参数化架构[14]。BSV/BH通过模仿Haskell实现了这一点,而Chisel则通过嵌入到Scala中实现了这一点。
+BSV和BH与像Lava[5]这样侧重于强大的、正确的电路结构组合机制,而不关注行为的语言有所不同。与其他直接表达架构的HDL一样,BSV/BH是通用的,不针对任何特定的应用领域。BSV/BH与所有其他HDL之间最基本、最具广泛和最重大的区别可能在于选择并发原子事务作为其表达行为的中心(也是唯一)方式。
+与其他硬件描述语言(HDL)类似,BSV/BH设计是模块实例化的层次结构,但相比其他HDL,由于受到Haskell语言语义启发而具有更强大的静态阐释能力。
+与其他HDL不同的是,在BSV/BH中,行为是通过规则来表示的,这些规则是全局原子事务。在其他HDL中,行为通常是通过同步时钟过程来表示的。
+与其他HDL不同的是,BSV/BH中的模块间通信是通过从规则(或从其他方法)中调用方法的概念来表达的,而不是基于输入和输出信号线路来表达的。方法调用的概念将规则的原子事务语义扩展为可以跨越模块边界的,即当设计扩展时,原子性会进行组合。模块的接口方法构成了一种一等公民的接口类型。
+与SystemVerilog类似,模块、接口和类型可以根据功能划分为称为包的源文件。bsc接受BSV或BH源文件(包)并生成可综合的Verilog代码,这就意味着可以直接使用现有的FPGA和ASIC综合工具。bsc通过单独的包编译实现了大型系统的快速增量重建。
+由bsc生成的Verilog代码可以在大多数知名的仿真器上运行,包括开源仿真器(Icarus、Verilator、CVC等)和商业仿真器(Synopsys、Cadence、Mentor、Xilinx)。它可以由大多数著名的综合工具(Design Compiler、Vivado、Quartus以及其他FPGA供应商的工具)进行综合。
+由BSV/BH中的bsc生成的Verilog可以被实例化在现有的VHDL/Verilog/SystemVerilog模块中。相反地,BSV/BH具有导入机制,可以在BSV/BH设计内实例化现有的Verilog模块。因此,可以在现有的流程中自由混合和匹配BSV/BH与现有的RTL。对于仿真,BSV/BH还具有DPI机制,可以导入任意的C代码。
+尽管BSV/BH在语义和类型方面广泛借鉴了Haskell的思想,但它并不是现有Haskell编译器或系统内的DSL。bsc是一个完全独立的、专为此目的而构建的编译器(但它恰好是用Haskell编写的)。bsc与其他HDL编译器(如Verilator和Chisel)的一个核心区别在于规则调度,即生成同步的,带有时钟和控制逻辑的verilog代码,且这些代码保留了原子事务行为语义。bsc使用开源SAT解算器分析规则条件之间的关系,从而产生优化的控制逻辑。
+除了生成Verilog代码外,bsc还可以生成C代码,并将其编译为独立的可执行仿真器(Bluesim),它与RTL仿真可以达到时钟周期级别的完全一致,并能够生成VCD文件。
+可以使用API中查询和控制编译器生成的中间对象文件。这个API有一个Tcl的Binding实现(bluetcl);实际上,Bluesim也只是一个Tcl脚本,这个脚本封装并在内部利用了这些API。
+尽管所有BSV/BH的开发都可以通过命令行完成,但Bluespec开发工作站(BDW)(https://github.com/B-Lang-org/bdw)提供了一个GUI界面,用户可以从中探索源代码层次结构,进行编译、构建和运行模拟,并在外部的VCD查看器(如GtkWave)上观察波形。BDW可以配置GtkWave以显示BSV源代码级别的波形类型(枚举、结构体、联合体、向量),而不是Verilog的扁平信号总线。BDW还提供了规则调度的图形显示,以帮助理解bsc如何将原子事务规则映射到时钟逻辑中。
+有多种免费和开源的教程资源可供学习BSV/BH和使用相关工具。https://github.com/BSVLang/Main 包含了Bluespec公司提供的BSV/BH免费开放培训课程,以及BSV by Example书籍的免费PDF副本 [15]。在参考文献[16]中,我们提供了"使用开源BH设计硬件系统和加速器"这个教程的教材链接和视频录像。此教程是在2020年国际函数式编程大会上进行的。麻省理工学院(美国)、卡内基梅隆大学(美国)、剑桥大学(英国)、首尔国立大学(韩国)、印度马德拉斯理工学院(印度)和达姆施塔特工业大学(德国)多年来一直在本科和研究生课程中使用BSV进行教学;其中一些教材可以在他们各自的公共网站上获取。在接下来的章节中列出的开源设计也是学习BSV/BH的丰富示例资源。
+多年来,许多公司都在产品ASIC SoCs中使用BSV和BH来开发复杂的IP子系统。这些包括用于机顶盒的一对多高速视频数据传输器,用于手持设备的显示控制器以及AI芯片加速器。许多公司利用BSV强大的抽象机制和类型系统,加速在FPGA上的原型设计以及后续的ASIC设计。虽然这些示例展示了BSV/BH和bsc的强大、可扩展和成熟性,但它们并不以开源的形式提供。
+然而,Bluespec公司和一些领先的大学提供了许多采用自由开源许可的设计;下面介绍其中的一些样例。其中大多数设计都相当庞大,并且可能非常具有吸引力。尽管这些设计是用BSV编写的,但bsc可以将它们编译成Verilog,并且它们可以作为IP在其他采用RTL设计的项目中使用(参见上文的"互操作性")。
+Bluespec公司开源了一系列的RISC-V处理器设计,从非常小型的(用于嵌入式和微控制器应用)到非常大型和复杂的。它们都可以在https://github.com/bluespec下面的Apache License, Version 2.0下获取。
+Piccolo和Flute可以参数化为构建标准的RISC-V非特权ISA选项的任意组合:RV32或RV64,I(整数),M(整数乘法/除法),A(原子操作),C(16位压缩指令)和FD(单精度和双精度IEEE浮点)。它们还可以选择为特权ISA级别M(机器),S(监管者)和U(用户)进行配置。对于S,它们支持标准的Sv32和Sv39虚拟内存方案。因此,它们都支持Linux。此外,这些处理器可以参数化为由简单到复杂的一系列不同内存系统实现:TCM(紧密耦合内存),仅L1(写回或写直通),以及具有缓存一致性的I-L1 + D-L1 + 共享L2。
+Toooba中的MIT RISCY-OOO处理器可以根据核心数量、超标量性、投机程度、重排序缓冲区和分支预测的大小和组织形式、MMU和缓存的大小及其组织形式等进行参数化。
+以下IP可以在https://github.com/bluespec下面的Apache License, Version 2.0下获取:
+AWSteria Infra是一个使用BSV编写的系统,用于简化由主机计算机上的软件与FPGA上的硬件进行通信的应用程序的设计。图1显示了AWSteria Infra和一个应用程序的结构。主机上的C代码和FPGA上的BSV代码为应用程序提供了简单的接口(AXI4和AXI4 Lite)。FPGA上的BSV代码还提供了对FPGA板上DDR内存的简单接口(AXI4)。这些接口类似于亚马逊的aws-fpga开发工具包中提供的所谓“shell”,但可用于更广泛的平台。
+AWSteria Infra实现可用于RTL模拟(使用TCP/IP进行通信),以及用于Xilinx VCU118和AWS F1 FPGA系统(两者都使用PCIe进行通信)。未来将支持更多平台。它可在Apache License 2.0下的https://github.com/bluespec/AWSteria Infra获取。
+ +Connectal也是使用BSV编写的,具有相同的整体目标,但提供了主机-FPGA通信的“远程方法”模型,可在双向上进行通信。它支持更广泛的平台,可在 MIT 许可下从 https://github.com/cambridgehackers/connectal获取。
+AWSteria-RISCV-Virtio是在FPGA上运行的RISC-V系统,可以启动多用户FreeBSD(它也支持Linux,但尚未测试)。它可以访问网络和块存储设备,甚至在没有(可访问的)内置网络或存储设备的云FPGA板上也可以做到这一点。它使用了一种名为"Virtio"的开放标准[18],该标准最初用于虚拟化领域,旨在为横跨多个主机的虚拟机监视器的客户操作系统提供可移植的设备服务。
+图2显示了AWSteria-RISCV-Virtio中的组件。FPGA端是一个带有BSV CPU(Flute, Toooba)、调试模块、PLIC、DDR内存、UART和用于Virtio的MMIO-to-host系统。主机端代码为RISC-V CPU提供了控制台TTY I/O、RISC-V CPU的GDB控制以及向RISC-V CPU上的操作系统提供Virtio设备服务(网络、块存储等)。主机端的Virtio设备由TinyEMU提供,这是Fabrice Bellard的用于RISC-V的开源系统仿真器[4](一个较小且较简单的版本的QEMU)。主机可以对FPGA DDR进行具有高速缓存一致性的访问,这是Virtio所需的。
+ +该系统构建在AWSteria Infra(第V-C节)之上,因此可以直接在任何受支持的平台上使用(当前支持RTL仿真、亚马逊AWS F1和Xilinx VCU118板)。AWSteria-RISCV-Virtio可在https://github.com/GaloisInc/BESSPIN-CloudGFE/tree/rsn3/AWSteria RISCV Virtio获取(将很快移至https://github.com/GaloisInc/BESSPIN-CloudGFE)。
+剑桥大学多年来一直在研究CHERI:能力型硬件增强的RISC指令。指令和内存系统被增强为具有“能力”,以实现安全计算,即消除传统设计中的安全漏洞[19]。这些设计是用BSV编写的,可在https://github.com/CTSRD-CHERI获得,采用基于Apache License 2.0的许可证。
+印度理工学院马德拉斯分校的Shakti计划正在构建一系列基于RISC-V的生产级处理器、SoCs、开发板和软件平台。这些处理器和SoCs是使用BSV语言编写的,并可在https://gitlab.com/shaktiproject上根据BSD 3-Clause许可证进行获取。
+CMU的Papamichael和Hoe开发了CONNECT,这是一个适用于FPGA的任意拓扑结构的多节点NoC(片上网络)生成器[17]。CONNECT是他们在MEMOCODE 2011硬件/软件协同设计竞赛中获奖作品的基础。最近,CONNECT已以BSD 3-Clause许可证的形式在https://github.com/crossroadsfpga/connect上开源。
+BlueCheck是在BSV中实现的Haskell的QuickCheck [8],利用BSV包含的与QuickCheck使用相同的Haskell特性:多态类型和类型类、单子和高阶函数。就像QuickCheck一样,它具有以下特点:
+原文链接: +https://woset-workshop.github.io/PDFs/2021/a02.pdf
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本期源码解读将聚焦 Xline 的 Curp 共识协议,DatenLord 分布式存储工程师赵佳炜将与大家分享在 Xline 中应用的 Curp 共识协议的设计与代码实现。
【直播预约】
欢迎您预约直播,或者登陆腾讯会议观看直播:
会议号:955-6910-3992
本文主要介绍了 DatenLord 团队在今年的 Xilinx 全球自适应计算挑战赛上获得 Big Data Analytics 赛道一等奖的作品——TRIDENT: Poseidon 哈希算法的硬件实现与加速。该项目基于 Xilinx Varium C1100 FPGA 加速卡,为 Filecoin 区块链应用中的 Poseidon 哈希算法提供了一套完整的硬件加速方案。在硬件方面,TRIDENT 基于 SpinalHDL 设计了 Poseidon 加速器 IP 并基于 Vivado 中 Block Design 工具搭建完整的 FPGA 硬件系统。在软件方面,我们为 Filecoin 软件实现 Lotus 提供了访问 FPGA 硬件加速器的接口。最终,TRIDENT 能够为 Filecoin 应用提供两倍于 AMD Ryzen 5900X 处理器的 Poseidon 计算加速效果。下文将主要从 Poseidon 哈希算法概述、基于 SpinalHDL 和 Cocotb 的硬件设计、总体方案设计、加速器 IP 设计和性能测试等方面对整个 TRIDENT 项目进行详细的介绍。
+const i="/zh-cn/assets/image1-9e1613a7.png",o="/zh-cn/assets/image2-7b7b20fc.png",e="/zh-cn/assets/image3-b15b4acb.png",n="/zh-cn/assets/image4-e5ed8af3.png",l="/zh-cn/assets/image5-74f0a1a0.png",t="/zh-cn/assets/image6-5ab2a1df.png",a="/zh-cn/assets/image7-bfc65522.png",p="/zh-cn/assets/image8-462cfa81.png",s="/zh-cn/assets/image9-ecae19a3.png",d="/zh-cn/assets/image10-1092617f.png",P="/zh-cn/assets/image11-2508217f.png",c="/zh-cn/assets/image12-69f6226d.png",r="/zh-cn/assets/image13-62fe53ff.png",h="/zh-cn/assets/image14-048f6e24.png",g="/zh-cn/assets/image15-c04accbc.png",m="/zh-cn/assets/image16-2de227b5.png",D="/zh-cn/assets/image17-ecbf7b1e.png",S="/zh-cn/assets/image18-88f5d1b8.png",F="/zh-cn/assets/image19-5df924ff.png",R="/zh-cn/assets/image20-5dfde1d6.png",T="/zh-cn/assets/image21-90c388d7.png",b=[i,o,e,n,l,t,a,p,s,d,P,c,r,h,g,m,D,S,F,R,T],A={label:"万字长文,详述TRIDENT:Poseidon 哈希算法的硬件加速与实现!",description:"本文主要介绍了DatenLord团队在今年的Xilinx全球自适应计算挑战赛上获得 Big Data Analytics赛道一等奖的作品——TRIDENT:Poseidon哈希算法的硬件实现与加速。该项目基于Xilinx Varium C1100 FPGA加速卡,为 Filecoin 区块链应用中的Poseidon哈希算法提供了一套完整的硬件加速方案。在硬件方面,TRIDENT基于 SpinalHDL 设计了Poseidon加速器 IP 并基于 Vivado中Block Design 工具搭建完整的FPGA硬件系统。在软件方面,我们为 Filecoin 软件实现 Lotus 提供了访问 FPGA 硬件加速器的接口。最终,TRIDENT 能够为Filecoin应用提供两倍于 AMD Ryzen 5900X 处理器的 Poseidon 计算加速效果。下文将主要从Poseidon哈希算法概述、基于SpinalHDL和Cocotb的硬件设计、总体方案设计、加速器 IP 设计和性能测试等方面对整个TRIDENT项目进行详细的介绍。",location:"中国香港",author:["翁万正"],tags:["硬件加速"],date:"2022-06-30",title:"Ten thousand words long article, detailing the hardware acceleration and implementation of TRIDENT: Poseidon hash algorithm!"},u=[{label:"引言",level:2},{label:"0.1 Poseidon 与零知识证明",level:3},{label:"0.2 Filecoin 分布式存储网络",level:3},{label:"Poseidon 哈希算法概述",level:2},{label:"1.1Poseidon 参数",level:3},{label:"1.2 Poseidon 详细计算流程",level:3},{label:"1.3Poseidon 算法特点",level:3},{label:"基于 SpinalHDL 和 Cocotb 的硬件设计与验证",level:2},{label:"2.1 SpinalHDL 和 Cocotb 概述",level:3},{label:"2.2 SpinalHDL 在硬件设计中的优势",level:3},{label:"2.3Cocotb 在验证中的优势",level:3},{label:"总体方案设计",level:2},{label:"3.1 开发平台",level:3},{label:"3.2 加速系统设计",level:3},{label:"加速器 IP 设计",level:2},{label:"4.1 模加电路的设计",level:3},{label:"4.2 模乘电路的设计",level:3},{label:"4.3 加速器架构设计",level:3},{label:"性能测试",level:2},{label:"5.1 Vivado Implementation 报告",level:3},{label:"总结",level:2}],L=`本文主要介绍了 DatenLord 团队在今年的 Xilinx 全球自适应计算挑战赛上获得 Big Data Analytics 赛道一等奖的作品——TRIDENT: Poseidon 哈希算法的硬件实现与加速。该项目基于 Xilinx Varium C1100 FPGA 加速卡,为 Filecoin 区块链应用中的 Poseidon 哈希算法提供了一套完整的硬件加速方案。在硬件方面,TRIDENT 基于 SpinalHDL 设计了 Poseidon 加速器 IP 并基于 Vivado 中 Block Design 工具搭建完整的 FPGA 硬件系统。在软件方面,我们为 Filecoin 软件实现 Lotus 提供了访问 FPGA 硬件加速器的接口。最终,TRIDENT 能够为 Filecoin 应用提供两倍于 AMD Ryzen 5900X 处理器的 Poseidon 计算加速效果。下文将主要从 Poseidon 哈希算法概述、基于 SpinalHDL 和 Cocotb 的硬件设计、总体方案设计、加速器 IP 设计和性能测试等方面对整个 TRIDENT 项目进行详细的介绍。
Poseidon 是一种全新的面向零知识证明(ZKP: Zero-Knowledge Proof)密码学协议设计的哈希算法。相比同类算法,包括经典的 SHA-256、SHA-3 以及 Pedersen 哈希函数,在零知识证明的应用场景下,Poseidon 能够显著地降低证明生成和验证的计算复杂度,极大地提升零知识证明系统整体的运行效率。基于上述优点,Poseidon 目前已被广泛应用在了各种区块链项目当中,包括去中心化存储系统 Filecoin、加密货币 Mina Protocol 和 Dusk Network 等,主要用于加速其中的零知识证明系统。
RF 次 Full Round 循环和 RP 次 Partial Round 循环组成。两种循环的计算流程基本相似,都依次包括 AddRoundConstant、SBox 和 MDSMixing 三个阶段,在这三个阶段分别完成常数模加、五次方模幂和向量—矩阵乘法,两者唯一的区别在于 Partial Round 在 Sbox 阶段只需要完成中间状态第一个元素的计算。Full Round 和 Partial Round 每次循环/迭代的计算流程如下图(a)和(b)所示。如果将 Poseidon 哈希函数的所有循环都依次展开,可以将其看成是一条单向的数据流,在该数据流上不断地进行模加、模幂和矩阵运算。
基于上述算法流程的定义,本次课题中实现的 Poseidon 加速器的具体硬件架构如下图所示。在 Poseidon 单次迭代的算法流程的基础上, 加速器的实现针对具体的 FPGA 架构特点和硬件资源限制做了如下几点优化:
- +TRIDENT 项目旨在为 Filecoin 分布式存储系统中涉及的 Poseidon 哈希计算实例提供一套完整的 FPGA 加速方案。硬件上,我们基于 Xilinx Varium C1100 FPGA 板卡搭建了一个完整的加速系统,该系统主要由 XDMA、FIFO 以及 Poseidon 加速器 IP 三部分组成,并通过 PCIe 接口与服务器主机进行数据传输。软件上,我们为 Filecoin 的具体软件实现 Lotus 提供了访问底层 FPGA 加速器的接口,并通过 Lotus-Bench 对加速器的计算性能进行测试和比较。
整个硬件加速系统的核心模块—Poseidon 加速器 IP 的设计主要可以分成单元运算电路和整体架构两个部分。其中单元运算电路包括 255-Bit 的模乘和模加,对于模加器,TRIDENT 中采用基于加法的取余方式避免了多余的比较器电路开销。对于 255-Bit 模乘电路,我们基于 Karatsuba-Offman 算法将高位宽的乘法分解成若干并行的小乘法器实现,同时采用 Montgomery Reduction 算法将取余过程中复杂的除法运算转换成乘法实现。在加速器架构的设计上,我们针对具体的 FPGA 硬件资源限制,基于流水线和折叠技术设计了一个串行的 Poseidon 计算架构。性能表现上,目前 FPGA 加速器电路能够工作在 100MHz 并为 Filecoin 提供两倍于 AMD Ryzen 5900X 处理器的加速性能。但和 RTX 3070 GPU 相比还存在 2~3 倍的差距,仍然有较大的提升空间。
@@ -278,4 +278,4 @@ const i="/zh-cn/assets/image1-9e1613a7.png",o="/zh-cn/assets/image2-7b7b20fc.png优化加速器架构:由于需要适配 Filecoin Poseidon 计算实例中不同大小的输入数据,目前在输入较小的情况下加速器中存在一些冗余的运算单元。通过进一步优化加速器的整体架构,使得在不同长度的输入数据下,所有运算单元都能得到更好的利用,能够进一步提升整体的加速性能。
传统单数据中心解决方案无法满足跨数据中心的场景对性能和一致性的需求。DatenLord 推出开源的分布式 KV 存储 Xline,针对多数据中心场景,实现数据的高性能跨云、跨数据中心共享访问,并且保证数据的一致性,方便业务系统实现多地多中心多活部署。
Xline 中所使用的共识协议,即非 Paxos ,也非 Raft,而是一种新的名为 Curp 的共识协议,其全称为 “Consistent Unordered Replication Protocol”。CURP 协议发表于 2019 年,其协议主要论述的是主从备份的场景,共识场景仅仅在附录中有简单表述,缺乏严肃验证。
@@ -6,4 +6,4 @@ const t="/zh-cn/assets/cover-ccfdc2fa.jpg",e="/zh-cn/assets/image1-9be7272d.jpg"本次直播分享,达坦科技联合思否,邀请达坦科技的联合创始人兼 CTO 施继成做一个关于 CURP 协议的工业化实践的直播,分享将论述 CURP 协议的正确性,同时以 KV 存储软件 Xline 为例子讲述如何在工业产品中使用该共识算法。
会议号:474-6575-9473
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随着互联网和云计算的业务规模越来越大,单个数据中心已经无法满足业务的需求,业务系统从单数据中心向多数据中心发展,多地多中心多活部署的需求也越来越普遍。多数据中心架构最大的挑战是,如何保证数据跨数据中心访问的一致性和性能。比如索引、权限、配置等这类需要跨数据中心共享访问的元数据,如何在多中心竞争修改的场景下,仍然能保持一致性,并且保证访问性能。
传统单数据中心解决方案无法满足跨数据中心的场景对性能和一致性的需求。DatenLord 推出开源的分布式 KV 存储 Xline,就是针对多数据中心场景,实现数据的高性能跨云、跨数据中心共享访问,并且保证数据的一致性,方便业务系统实现多地多中心多活部署。
本周六(10 月 15 日)下午 3 点,达坦科技和 Rust 语言中文社区合作,由达坦科技的联合创始人施继成在 Rust 唠嗑室做开源分布式存储技术的分享,介绍 Xline 是如何实现高性能跨数据中心的数据一致性管理。欢迎大家预约收看!
-`;export{n as assetURLs,a as default,e as metadata,o as toc}; +`;export{n as assetURLs,a as default,e as metadata,o as toc}; diff --git a/zh-cn/assets/index-90047cd2.js b/zh-cn/assets/index-6e810f9e.js similarity index 99% rename from zh-cn/assets/index-90047cd2.js rename to zh-cn/assets/index-6e810f9e.js index 28a7f70..11491b8 100644 --- a/zh-cn/assets/index-90047cd2.js +++ b/zh-cn/assets/index-6e810f9e.js @@ -1,4 +1,4 @@ -const e="/zh-cn/assets/cover-6865ae02.png",l="/zh-cn/assets/image1-1421d5c3.png",i="/zh-cn/assets/image2-03115587.png",t="/zh-cn/assets/image3-8a8d1c33.png",a="/zh-cn/assets/image4-c1593056.png",s=[e,l,i,t,a],p={label:"Xline 源码解读(一) —— 初识 CURP 协议",description:"Xline 是一款开源的分布式 KV 存储引擎,其核心目的是实现高性能的跨数据中心强一致性,提供跨数据中心的meatdata 管理。那么 Xline 是怎么实现这种高性能的跨数据中心强一致性的呢?这篇文章就将带领大家一起来一探究竟。",cover:"./cover.png",location:"中国香港",author:["赵佳炜"],tags:["Xline"],date:"2023-07-13",title:"Interpretation of Xline source code (1)——Introduction to CURP protocol"},n=[{label:"Xline 是什么",level:2},{label:"Xline 的整体架构",level:2},{label:"CURP 协议简介",level:2},{label:"CURP 是什么?",level:3},{label:"为什么选择 CURP 协议",level:3},{label:"fast path 与 slow path",level:3},{label:"Summary",level:2}],r=` +const e="/zh-cn/assets/cover-6865ae02.png",l="/zh-cn/assets/image1-1421d5c3.png",i="/zh-cn/assets/image2-03115587.png",t="/zh-cn/assets/image3-8a8d1c33.png",a="/zh-cn/assets/image4-c1593056.png",s=[e,l,i,t,a],p={label:"Xline 源码解读(一) —— 初识 CURP 协议",description:"Xline 是一款开源的分布式 KV 存储引擎,其核心目的是实现高性能的跨数据中心强一致性,提供跨数据中心的meatdata 管理。那么 Xline 是怎么实现这种高性能的跨数据中心强一致性的呢?这篇文章就将带领大家一起来一探究竟。",cover:"./cover.png",location:"中国香港",author:["赵佳炜"],tags:["Xline"],date:"2023-07-13",title:"Interpretation of Xline source code (1)——Introduction to CURP protocol"},n=[{label:"Xline 是什么",level:2},{label:"Xline 的整体架构",level:2},{label:"CURP 协议简介",level:2},{label:"CURP 是什么?",level:3},{label:"为什么选择 CURP 协议",level:3},{label:"fast path 与 slow path",level:3},{label:"Summary",level:2}],o=`Xline 是一款开源的分布式 KV 存储引擎,其核心目的是实现高性能的跨数据中心强一致性,提供跨数据中心的 meatdata 管理。那么 Xline 是怎么实现这种高性能的跨数据中心强一致性的呢?这篇文章就将带领大家一起来一探究竟。
Xline 是一款提供跨数据中心强一致性的分布式 KV 存储,其核心问题之一便是如何在跨数据中心这种高延迟的广域网环境中提供高性能的强一致性保证。传统的分布式共识算法,如 Raft 和 Multi-Paxos,通过让所有操作都满足持久化存储和有序性前提来保证状态机一致性。而 CURP 协议则是对达成共识的场景做了更细粒度的划分,将协议分割成了前端(fast path)和后端(slow path),前端只保证了提案会被持久化到集群当中,而后端不仅保证了持久化,也保证了所有保存了该提案的节点会按照相同的顺序执行命令,保证了状态机的一致性。
关于 CURP 协议的简介就到这里,更多的细节欢迎参考我们的其他文章和分享,如下:
Curp 共识协议的重新思考
DatenLord | Xline Geo-distributed KV Storage
`;export{s as assetURLs,r as default,p as metadata,n as toc}; +DatenLord | Xline Geo-distributed KV Storage
`;export{s as assetURLs,o as default,p as metadata,n as toc}; diff --git a/zh-cn/assets/index-4c405f89.js b/zh-cn/assets/index-817e2d04.js similarity index 98% rename from zh-cn/assets/index-4c405f89.js rename to zh-cn/assets/index-817e2d04.js index 08f6deb..b771b2c 100644 --- a/zh-cn/assets/index-4c405f89.js +++ b/zh-cn/assets/index-817e2d04.js @@ -1,4 +1,4 @@ -const v="/zh-cn/assets/cover-92745c95.jpg",e="/zh-cn/assets/image1-638abd39.png",s="/zh-cn/assets/image2-2a8f796e.gif",p="/zh-cn/assets/image3-ae1841b7.png",a="/zh-cn/assets/image4-5bf432ec.png",n="/zh-cn/assets/image5-81eb5b8d.png",l="/zh-cn/assets/image6-537c8738.png",o="/zh-cn/assets/image7-b58de99e.png",i="/zh-cn/assets/image8-c6334c83.png",t="/zh-cn/assets/image9-6340ddaa.png",c="/zh-cn/assets/image10-ac1b70de.png",r="/zh-cn/assets/image11-1f1870d2.png",_="/zh-cn/assets/image12-01c249ea.png",m="/zh-cn/assets/image13-a48112ad.png",d="/zh-cn/assets/image14-d780d4f2.png",u="/zh-cn/assets/image15-f58a4d86.png",h="/zh-cn/assets/image16-79c3985b.png",k="/zh-cn/assets/image17-863e7adb.png",f="/zh-cn/assets/image18-931263d9.png",g="/zh-cn/assets/image19-8f35c101.png",P="/zh-cn/assets/image20-ef5a452f.png",b="/zh-cn/assets/image21-ebff1568.png",j="/zh-cn/assets/image22-b3b3dbaa.png",F="/zh-cn/assets/image23-12fff2c5.png",w=[v,e,s,p,a,n,l,o,i,t,c,r,_,m,d,u,h,k,f,g,P,b,j,F],T={label:"数据流式编程在硬件设计中的应用",description:"数据流式编程(Dataflow Programming)是一种存在已久的程序设计范式,可以追溯到19世纪60年代,由MIT的Jack Dennis教授开创。",cover:"./cover.jpg",location:"中国香港",author:["米明恒"],tags:["硬件加速"],date:"2023-10-26",title:"Application of data flow programming in hardware design"},I=[{label:"数据流式编程的思想",level:2},{label:"数据流式编程思想简介",level:3},{label:"软件开发中的数据流式编程思想",level:3},{label:"软件数据流 vs 硬件数据流",level:3},{label:"数据流思想与状态机思想的对比",level:3},{label:"Bluespec 语言及其流式编程框架 PAClib",level:2},{label:"Bluespec SystemVerilog(BSV)和 PAClib 简介",level:3},{label:"PAClib 中的基础开发组件",level:3},{label:"IFFT 应用实例",level:2},{label:"需求背景",level:3},{label:"代码实现",level:3},{label:"写在最后",level:2}],y=`数据流式编程(Dataflow Programming)是一种存在已久的程序设计范式,可以追溯到 19 世纪 60 年代,由 MIT 的 Jack Dennis 教授开创。
@@ -158,7 +158,7 @@ endinterface PipeOut #(Tuple2 #(a, Bool)) poa) (PipeOut #(b)); - +图 14 mkIfThenElse 节点示意图
mkIfThenElse
可以实现分支逻辑。输入数据是一个 Tuple2#(a, Bool)
类型,该节点会根据 Bool 类型的取值将数据包路由到 pipeT
或者 pipeF
子节点。其内部具有一个 FIFO 结构用于存储 Token,从而实现在 pipeT 和 pipeF 两个节点所需处理周期不一致时起到保序的作用。
此外,PAClib 中还提供了 mkIfThenElse_unordered
变种实现,当对输入和输出之间的数据没有严格的顺序要求时,可以使用这个变种来简化设计。For 循环 使用 mkForLoop
可以创建条件分支,其定义及示意图如下:
图 15 mkForLoop 节点示意图
mkForLoop
需要通过 n_iters
参数传入循环次数。在实现逻辑上,Loop Control Logic 内部有一个共享队列,外部进入的新数据和经过循环体执行过一次处理的数据,都会被放到这个队列中。每个新进入的数据都会被打上一个 Tag,Tag 的值为循环次数,这个 Tag 伴随着数据在循环中流动,每流动一次,Tag 减一,Loop Control Logic 在从共享队列中取出数据时,会根据 Tag 的计数值决定将其送入 mkLoopBody
节点还是 mkFinal
节点。内部有两条 Rule,分别独立负责把新数据和正在循环的数据放入 FIFO 中,为循环提供了内在动力(图中 Pump 标注路径)。
注意,由于 mkLoopBody
也可能是一个需要多拍才能完成的节点,因此可以有多个数据包同时在流水线中进行循环。
如上述代码片段和图 20 所示,通过 mkMap_fn_with_funnel_indexed
函数的第一个参数来决定实例化多少个 f_radix4
计算单元,从而改变计算的并行度。
let permuter = mkFn_to_Pipe_Buffered (False, f_permute,
param_buf_permuter_output);
-
+
图 21 在不同位置插入流水线寄存器
如上述代码片段和图 21 所示,通过 mkFn_to_Pipe_Buffered
函数的两个输入参数来控制是否加入 FIFO,从而实现在流水线或组合逻辑之间的切换,使得程序可以在时序上做出简单的调整。
return mkCompose (grouper,
@@ -286,4 +286,4 @@ endfunction
参考资料:
[1] https://en.wikipedia.org/wiki/Dataflow_programming
[2] Rishiyur S. Nikhil. Two uses of FP techniques in HW design[EB/OL]. 2010[].
-http://www.cs.ox.ac.uk/ralf.hinze/WG2.8/27/slides/rishiyur2.pdf.
`;export{w as assetURLs,y as default,T as metadata,I as toc};
+http://www.cs.ox.ac.uk/ralf.hinze/WG2.8/27/slides/rishiyur2.pdf.
`;export{w as assetURLs,y as default,T as metadata,S as toc};
diff --git a/zh-cn/assets/index-1dde53bb.js b/zh-cn/assets/index-8c16a843.js
similarity index 97%
rename from zh-cn/assets/index-1dde53bb.js
rename to zh-cn/assets/index-8c16a843.js
index 23a48ca..529f710 100644
--- a/zh-cn/assets/index-1dde53bb.js
+++ b/zh-cn/assets/index-8c16a843.js
@@ -1,4 +1,4 @@
-const e="/zh-cn/assets/image1-145af1bc.png",a="/zh-cn/assets/image2-b5b0ee19.png",l="/zh-cn/assets/image3-204919ac.png",p="/zh-cn/assets/image4-e50f112d.png",t="/zh-cn/assets/image5-cdb8d1de.png",i=[e,a,l,p,t],n={label:"数据库隔离级别及MVCC",description:"数据库在同时处理多个事务时需要决定事务之间能否看到对方的修改,能看到多少等等。根据隔离的严格程度,从严到松可以分为 Serializable, Repeatable reads, Read committed, Read uncommitted。我们用下面这个 KV 存储的例子来解释这四个隔离级别。KV 存储的初始状态如下:",location:"中国香港",tags:["Xline"],date:"2023-02-16",title:"Database isolation level and MVCC"},o=[{label:"数据库隔离级别介绍",level:2},{label:"Read uncommitted",level:3},{label:"Repeatable read",level:3},{label:"Serializable",level:3},{label:"Snapshot 隔离级别及 MVCC",level:2},{label:"一点联想",level:2},{label:"总结",level:2}],s=`数据库隔离级别介绍
+const e="/zh-cn/assets/image1-145af1bc.png",a="/zh-cn/assets/image2-b5b0ee19.png",l="/zh-cn/assets/image3-204919ac.png",p="/zh-cn/assets/image4-e50f112d.png",t="/zh-cn/assets/image5-cdb8d1de.png",i=[e,a,l,p,t],o={label:"数据库隔离级别及MVCC",description:"数据库在同时处理多个事务时需要决定事务之间能否看到对方的修改,能看到多少等等。根据隔离的严格程度,从严到松可以分为 Serializable, Repeatable reads, Read committed, Read uncommitted。我们用下面这个 KV 存储的例子来解释这四个隔离级别。KV 存储的初始状态如下:",location:"中国香港",tags:["Xline"],date:"2023-02-16",title:"Database isolation level and MVCC"},n=[{label:"数据库隔离级别介绍",level:2},{label:"Read uncommitted",level:3},{label:"Repeatable read",level:3},{label:"Serializable",level:3},{label:"Snapshot 隔离级别及 MVCC",level:2},{label:"一点联想",level:2},{label:"总结",level:2}],s=`数据库隔离级别介绍
数据库在同时处理多个事务时需要决定事务之间能否看到对方的修改,能看到多少等等。根据隔离的严格程度,从严到松可以分为 Serializable, Repeatable reads, Read committed, Read uncommitted。我们用下面这个 KV 存储的例子来解释这四个隔离级别。KV 存储的初始状态如下:
Table 1:
@@ -43,4 +43,4 @@ const e="/zh-cn/assets/image1-145af1bc.png",a="/zh-cn/assets/image2-b5b0ee19.png
本文为大家介绍了数据库的四种隔离级别,分别用例子介绍了不同隔离级别之间的区别。然后详细介绍了 Snapshot 这个使用最广泛的隔离级别,并且说明了其最长用的实现方式 MVCC。最后结合了 MVCC 和 无锁数据结构的内存管理机制进行了对比和探讨。
达坦科技 Xline 项目专注于跨云元数据管理 KV 存储,并且目前正在实践应用 MVCC 做数据库隔离。如果您想了解更多相关信息,请参考 Xline GitHub 链接:
https://github.com/datenlord/Xline
-本周次条是 Xline 最新版本的发布,请阅读《Xline v.0.2.0:一个用于元数据管理的分布式 KV 存储》。
`;export{i as assetURLs,s as default,n as metadata,o as toc};
+本周次条是 Xline 最新版本的发布,请阅读《Xline v.0.2.0:一个用于元数据管理的分布式 KV 存储》。
`;export{i as assetURLs,s as default,o as metadata,n as toc};
diff --git a/zh-cn/assets/index-86e42443.js b/zh-cn/assets/index-90593fbc.js
similarity index 99%
rename from zh-cn/assets/index-86e42443.js
rename to zh-cn/assets/index-90593fbc.js
index e71ef1d..9099a01 100644
--- a/zh-cn/assets/index-86e42443.js
+++ b/zh-cn/assets/index-90593fbc.js
@@ -1,4 +1,4 @@
-const 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Cq3HThBmcQrTlgcEgmSoAQgEqI0kpLIUqf/2zMa9tlWq1dPVD9vBm9BWbPVFr+27sAhgAjVI2K7aJuRNlSXSG/EFPufFUYAcXJqqBOTmmXZOIEEGwDcaNWWgSjjz4bv8rvW0juOrNfZ5ijPtq3ZwbvP90GWFe+y8R1r8fIxrHvwMWuAysjtA+uUjg1bSp/o7rriJ4oVvxlp5ocIAzgHPTVigvgq20TFnkzZ3vEfV26qVlK+GpfDHP915Z/MAfy9hH0rBfDHqY08FXLOGh5Q7546Z0hmoEZ+7Lmy26Hfo/GDYBmVd0PLnUBcRnE9mAXMLsfQDN6bcplE9To03UQ/Vo3Hb4Fqb4Ak7bK2xIjyYa7vGB4iMlSMg7ganu1jD3BvgJ+duvj/wFEX2hUx6jvDsT1QH/BVM4E/QMAXMR+epQCWB4L+cvI7vo79w0om3GfxL1kR1Jn77IWAMPytZnxOs3AAv3s5i/w8+QHTSrvLUanCiIYaBMMPgNmKVHULERTMUxPXldievrDkG56MQGDFLY/VEBIHpdtgw2w6eQjLG+LMnsO9N5PAHh6eAZN6udQ0xe0gwKDLGu8GijBQL3giL9DaKqKs0MrL4C4iNWJcBTqf3Du/5yd9QIjjIOcTqgwobcljfVmMfPyhnbnRhqaDh48eKG5+ULhhinrOsSadsfrj3cXTwQCx36nlrYttWBY4asIA+suqOWNVRCFd1wOTXQ+NuQdp/47gTalbStYIPbuwzXLU87uhL9ep6iUwi0Oc9vk1AaLSatLWga0rd63a3CaUNNkO32VaRYCUfWE9xOQpbqi9bUS9Cv9VcehOa4MYq4DGQZTIduPVFsCMkyJEBSvhkBHMYbDC9fU+G9UdYu4zZvqDbN3grJWuoCgro7bALxTlX1eo2Yh+K6Igaj5Z2qWkaVrfQBqXzQSulzLTAdo00spjAF8wJ9dTHQGcTNg7q9GVhKcqZv0TEVN3/BBmmY+ozny0t1V6ycMADwMciPOVKbm+s3g8FLQKOxlzXTjCXRL/CmffVRuKl+dbiT9bXt2PQDUeCqGUUqO/PXGw6mDNZUO6AD8UyEPgJ9Owni4SFl79IQEO4YGMyP3r1gfpIQe+IvrSHOWPhiAf0CSWFGPXss0ZPEEtq+U4G3v7zAru9z0tEGCbSQYA1QnBkUDIzO2HiT+aQdHX+7QQcbX8ocj4uHq2/DEcAjEND3c28vnuoExI/rYXFmwZ11oGVOU4URX1tlTIM1ZysvGlkMsHCOUW08Src25UVxbwnL3ffK+709X9wseHubn0OgoKLPNyIrvon0A/jDZNDhYU9h2wAzy5IHPjBm0fn7dovFh7dmVPJQODEw+ItuOMMOiBCVr2fJ6KNNSbZvGmEyMTk8nDWb6l1o7zZlVUQ87VNVYHHO4m7oDAUOG/JauNCC0qsjG3hBvYwICBIUWs74PtJrbYdimPTsOHYJ7ZwUAVJZpSvJzm2+GPAzy4uTnfG0YGAllTiBK4EAWtFpCFgc7VJRDvCYUEO+rCa487d9RZWzs9zP1c+cKiGfNqG7xGqJcyuT5lqCXhnt7tF427j7B1mXIZl42LD5iXaaq94sw5s1xbK0I/T5P6DiwMmPyQrGikHDNE+fqEDI3Vy6Wk2GfC2o28gmLjbZdLHMtLA3r4+nha7hjZRTlUAoRgTP5jtO/t6UH6VSWO9rnEucJ6CaN5/NTQvnFfUzVhM8YaveKSyCG3M+Odhf0utAlLQtBF0gdFDPWmxYGkx1o27TvDGK3g019Dba3gggQc4LP0WsXCMsepgojd+mKPwM52xU9Z4qDZbYZzz7InXCKWyEKrzM71BdKzz9yuFa0KQLbW8E5sOfsXN0tPIt8YdHfI9i4BMJ/Dm81uqLoRKGPcypjZ02LnP/8i8TMgzMkQGRy3sx77lJ1EseyRvytKlS3nfOfoBdenrbIsTNUvnYjy8Qd1LXvLuuK/YnLe/IaUPye7W6vn/aQF9QqyWxDq/BQ1fKk6al0u5hWl/gKwNmlVayxf7IcW+y/Sb0RtC8oeXKa2IuLf3Zti07Om+qSpjPVltZbPAYOG6X79xpz5Q2257hKk2k78eN1nW3F+/F/yf4QUjvLsll7Cd/w8YQlDjPq6sdj0wvVn+hcU/2v6fQzY5Yq3CLtcqePjUsR3ujWZq7SnqHqH/jtC74ODbjf72kPyO2+u3pBXMvUC8JdqBeEu1AvCHehXhDuQr0g3IX+BVArSBMwv4MDAAAAAElFTkSuQmCC",l="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAFoAAABGCAAAAABp19w+AAAABGdBTUEAALGPC/xhBQAAACBjSFJNAAB6JgAAgIQAAPoAAACA6AAAdTAAAOpgAAA6mAAAF3CculE8AAAAAmJLR0QA/4ePzL8AAAPnSURBVFjD7ZZdTFtlGMd/UJhrGWAdlY91MO0mY4EOyFzAhIaBaYJbJMgFURc1DKfGiyGaxWYxdYshkixuQPwITozuioSQ7EInmhmihu7DlZZtpaFUmbU10kbo2jEYX1605RzkbAZkJkvOc3POeZ7/+Z2c//uc57xxC9yriL9nZBkto2W0jJbRMlpG/3/ohMUzdyAYDOVUrpgw6wwGgyHD9jujg/UAz6wcfdEEkLscvWhIXF0VkL/y99bUlgJ5ywtxwu5pthK6MlZhquM1NN3L06JldIFmNWSuwG6JtAg9CI+vhswAFN4dfQfFv8asRXqNBPScBQpWgx4BdZZEXuhr1xLFDZc7IV+nAJi+HC5JAbg6tE8ZLc9fd43l6FNjRpZyV7RYMfFFD0BWRzL0m4ADL8D3R/mpNVLv/8gD0FgDYIUiKbRgyICg6KnuUb/8SUeZ7zg4TaoTBXw2BefANgXwxyGTp9x82szJkaiRMavnwlLouf5Fq7tb0Z3an5d7EDt8zKniEAShErgFjDfZaDxakV1Rxi8RqzVRIwN1e3+VQI+AJhMASzuY04Br5OCyVW7yjsJGqKiCVJh/24exBgj7SAfsQldb/SgkvBYUnVCdAxNnOnkRK9X8AE8lAPvO7oiH805ogHnH+x79zqU9u/u5omwJ9KLCPgxXTZNeP6ojxdQY1XwFewASKQC6gPbbATeUmaJG6qOMB1+R6hBBcQ245UvONeaVJMK6dbg8qIoAnJTAvA1Uo0p1la5UGzNSejzE0ILCD8UnxJILUJ4I0KfeCRNAi16oDi4aeblr+mnxTI4XK4IuIAyblzz9EuwCCFirFBAGMkVVKxTi9cLFpk3Dx/wSaBsU8mlDCNIgLeZSAOA6bAU4QwWwEXgoWg/MRnp24a13mG+rOpSEQwJthfzb57YkwyMwHMn91VQ7DigjrD+/1G8DkjQQbd7e2g5+B3XmkK8Yu2f/kJ/tEmggvX/yScCg4scZgCv1tj2pgA7cMNVMIwB1cAlg+ngz5cTBNr7DwOY27bcUp4vQincjx6HfSPow8ch6SND24Uhx957ujH/9oAJI7WUwyfHBUFNkxOjsYz9vmDrf02rf1bIVVfeMV/25/qU4Vcb0ezMHdCJ07Afme9OH2hwZIpY2H6B+oiHqae/JSVC9YYzeMtn+NcBjz5cDWI5NssOcAfSZ+UYpgWbGdTM3JbZ8o2MbslMF0ZR3QvnoeuF63BPWZsXaNuRe0CsADl/Ye7hF/NUsrFXcNBgGxgxOIbF2uycFPNxszJXskP8YD9TzbPhVKa/XIMZvaEUzdU3R/4j7cxMso2W0jJbRMvr+QP8NsluKv9sZ0eAAAAAASUVORK5CYII=",p="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAIwAAABGCAAAAAA72CMwAAAABGdBTUEAALGPC/xhBQAAACBjSFJNAAB6JgAAgIQAAPoAAACA6AAAdTAAAOpgAAA6mAAAF3CculE8AAAAAmJLR0QA/4ePzL8AAAcdSURBVGje7Zh9UFTXFcB/sHzlKcIGt5ZvGgIFhEi0aIN0MQmlJpJhbFCridRxJtOksUmcqYwmEidWbSWZMU4S2wQjaaJt/WKcItUSU4LSiIiiIBSYUJdsXCWga/h4lM/tH2/38d7uggszQf/Y89e955w9+3vnvHvvedfDwr0jnncbwA3jhnHDuGHcMPeCuGHcMBMVr+/+Lzr3DoP3i9OAz6t8NAzGZd09mF6xtwZ+mA0MtLRC3MNjeXpMRafXuhbCP/YE+N0XH4aM6Tcl70y98ATGWgC+fnxslqmBqZ37NBQDiE0Pj+M3FTAj1fNikqg0Af8h6S7DGMQkcqAEqAv53jiOjqvp1qWLjV0kLkqZplK3fZWqmSRMvfAAC7XmY7/040KKrG2++YjHHTJzbcPSN0o0ob3lW548rQqYu2dkspm5OFeDdw7iv+irT5a11ZvedFjJFqUMHNDrs4+bLZa+f+r1+k9GDTcW61sslhvnyksO/NUyQRlefNhisdzU63MtNfoOWT30kr7IzlNVpvY8A5kv+QN+meHPUxg732r432ZxfQwcOQSE/2KCibkqPgTcn1lmqLscMlNWa/JXF4Vkjlmm9hcNZG/ylybxz8B71spY3mxJywbi04TJvDJEAyyF4vM/VuhnbmX7f8eC6X2lg0dfkRXZYPi3NKw9xRoP4LHtOyYBUyO9+QlxlDfOURpSktg3FsxeE8IoC7OAL6XhUZJjpFEIE5bhC9Z9LgfsdpkVnGl2DlNfDOsCFSYdtAFgqmSFI7urUicmSoN0gfAglSlVR5FTmP6dIGQoTUPwFQAlCLZaezBBOfPBq3xU0gPgs5wUtVHzFGe7nMF8aoRlvsr0mkEAGDpGss1tojDf7jggcu4tEYAs5tuZE6BOMZWX9llAlZirwAMAbSIP2ZQKmMGG89d0MbND5dS2NhOW7HWyypi+Wn7EgBOKiLoKe9Y4uJDmCNNfCdoIpWM9EAXQAgmOz9z2mhFBhLXPSCH+8j6AdlYTtM5JxjXxjzJUvexYpitAqsqxBoi0wvzA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持久化存储设计与实现",description:"在 Xline 早期的原型阶段,我们采用了基于内存的存储来实现数据的持久化。这虽然简化了 Xline 原型设计的复杂度,提高了项目的开发和迭代速度,但带来的影响也是显著的:由于数据都存储在内存当中,因此一旦当进程 crash 后,节点的数据恢复需要依赖于从其他正常节点上拉取全量数据,这就需要较长的恢复时间。基于此方面的考虑,Xline 在最新发布的版本 v0.3.0 中引入了一个 Persistent Storage Layer,来将数据持久化到磁盘当中,同时向上层调用方屏蔽掉无关的底层细节。",location:"中国香港",author:["达坦科技"],tags:["Xline"],date:"2023-05-25",title:"Xline Persistent Storage Design and Implementation"},k=[{label:"引言",level:2},{label:"B+ Tree 读写放大分析",level:3},{label:"LSM Tree 读写放大分析",level:3},{label:"总结",level:3},{label:"持久化存储层设计与实现",level:2},{label:"整体架构与写入流程",level:3},{label:"接口设计",level:3},{label:"实现相关",level:3},{label:"性能评估",level:2}],f=`引言
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Cq3HThBmcQrTlgcEgmSoAQgEqI0kpLIUqf/2zMa9tlWq1dPVD9vBm9BWbPVFr+27sAhgAjVI2K7aJuRNlSXSG/EFPufFUYAcXJqqBOTmmXZOIEEGwDcaNWWgSjjz4bv8rvW0juOrNfZ5ijPtq3ZwbvP90GWFe+y8R1r8fIxrHvwMWuAysjtA+uUjg1bSp/o7rriJ4oVvxlp5ocIAzgHPTVigvgq20TFnkzZ3vEfV26qVlK+GpfDHP915Z/MAfy9hH0rBfDHqY08FXLOGh5Q7546Z0hmoEZ+7Lmy26Hfo/GDYBmVd0PLnUBcRnE9mAXMLsfQDN6bcplE9To03UQ/Vo3Hb4Fqb4Ak7bK2xIjyYa7vGB4iMlSMg7ganu1jD3BvgJ+duvj/wFEX2hUx6jvDsT1QH/BVM4E/QMAXMR+epQCWB4L+cvI7vo79w0om3GfxL1kR1Jn77IWAMPytZnxOs3AAv3s5i/w8+QHTSrvLUanCiIYaBMMPgNmKVHULERTMUxPXldievrDkG56MQGDFLY/VEBIHpdtgw2w6eQjLG+LMnsO9N5PAHh6eAZN6udQ0xe0gwKDLGu8GijBQL3giL9DaKqKs0MrL4C4iNWJcBTqf3Du/5yd9QIjjIOcTqgwobcljfVmMfPyhnbnRhqaDh48eKG5+ULhhinrOsSadsfrj3cXTwQCx36nlrYttWBY4asIA+suqOWNVRCFd1wOTXQ+NuQdp/47gTalbStYIPbuwzXLU87uhL9ep6iUwi0Oc9vk1AaLSatLWga0rd63a3CaUNNkO32VaRYCUfWE9xOQpbqi9bUS9Cv9VcehOa4MYq4DGQZTIduPVFsCMkyJEBSvhkBHMYbDC9fU+G9UdYu4zZvqDbN3grJWuoCgro7bALxTlX1eo2Yh+K6Igaj5Z2qWkaVrfQBqXzQSulzLTAdo00spjAF8wJ9dTHQGcTNg7q9GVhKcqZv0TEVN3/BBmmY+ozny0t1V6ycMADwMciPOVKbm+s3g8FLQKOxlzXTjCXRL/CmffVRuKl+dbiT9bXt2PQDUeCqGUUqO/PXGw6mDNZUO6AD8UyEPgJ9Owni4SFl79IQEO4YGMyP3r1gfpIQe+IvrSHOWPhiAf0CSWFGPXss0ZPEEtq+U4G3v7zAru9z0tEGCbSQYA1QnBkUDIzO2HiT+aQdHX+7QQcbX8ocj4uHq2/DEcAjEND3c28vnuoExI/rYXFmwZ11oGVOU4URX1tlTIM1ZysvGlkMsHCOUW08Src25UVxbwnL3ffK+709X9wseHubn0OgoKLPNyIrvon0A/jDZNDhYU9h2wAzy5IHPjBm0fn7dovFh7dmVPJQODEw+ItuOMMOiBCVr2fJ6KNNSbZvGmEyMTk8nDWb6l1o7zZlVUQ87VNVYHHO4m7oDAUOG/JauNCC0qsjG3hBvYwICBIUWs74PtJrbYdimPTsOHYJ7ZwUAVJZpSvJzm2+GPAzy4uTnfG0YGAllTiBK4EAWtFpCFgc7VJRDvCYUEO+rCa487d9RZWzs9zP1c+cKiGfNqG7xGqJcyuT5lqCXhnt7tF427j7B1mXIZl42LD5iXaaq94sw5s1xbK0I/T5P6DiwMmPyQrGikHDNE+fqEDI3Vy6Wk2GfC2o28gmLjbZdLHMtLA3r4+nha7hjZRTlUAoRgTP5jtO/t6UH6VSWO9rnEucJ6CaN5/NTQvnFfUzVhM8YaveKSyCG3M+Odhf0utAlLQtBF0gdFDPWmxYGkx1o27TvDGK3g019Dba3gggQc4LP0WsXCMsepgojd+mKPwM52xU9Z4qDZbYZzz7InXCKWyEKrzM71BdKzz9yuFa0KQLbW8E5sOfsXN0tPIt8YdHfI9i4BMJ/Dm81uqLoRKGPcypjZ02LnP/8i8TMgzMkQGRy3sx77lJ1EseyRvytKlS3nfOfoBdenrbIsTNUvnYjy8Qd1LXvLuuK/YnLe/IaUPye7W6vn/aQF9QqyWxDq/BQ1fKk6al0u5hWl/gKwNmlVayxf7IcW+y/Sb0RtC8oeXKa2IuLf3Zti07Om+qSpjPVltZbPAYOG6X79xpz5Q2257hKk2k78eN1nW3F+/F/yf4QUjvLsll7Cd/w8YQlDjPq6sdj0wvVn+hcU/2v6fQzY5Yq3CLtcqePjUsR3ujWZq7SnqHqH/jtC74ODbjf72kPyO2+u3pBXMvUC8JdqBeEu1AvCHehXhDuQr0g3IX+BVArSBMwv4MDAAAAAElFTkSuQmCC",l="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAFoAAABGCAAAAABp19w+AAAABGdBTUEAALGPC/xhBQAAACBjSFJNAAB6JgAAgIQAAPoAAACA6AAAdTAAAOpgAAA6mAAAF3CculE8AAAAAmJLR0QA/4ePzL8AAAPnSURBVFjD7ZZdTFtlGMd/UJhrGWAdlY91MO0mY4EOyFzAhIaBaYJbJMgFURc1DKfGiyGaxWYxdYshkixuQPwITozuioSQ7EInmhmihu7DlZZtpaFUmbU10kbo2jEYX1605RzkbAZkJkvOc3POeZ7/+Z2c//uc57xxC9yriL9nZBkto2W0jJbRMlpG/3/ohMUzdyAYDOVUrpgw6wwGgyHD9jujg/UAz6wcfdEEkLscvWhIXF0VkL/y99bUlgJ5ywtxwu5pthK6MlZhquM1NN3L06JldIFmNWSuwG6JtAg9CI+vhswAFN4dfQfFv8asRXqNBPScBQpWgx4BdZZEXuhr1xLFDZc7IV+nAJi+HC5JAbg6tE8ZLc9fd43l6FNjRpZyV7RYMfFFD0BWRzL0m4ADL8D3R/mpNVLv/8gD0FgDYIUiKbRgyICg6KnuUb/8SUeZ7zg4TaoTBXw2BefANgXwxyGTp9x82szJkaiRMavnwlLouf5Fq7tb0Z3an5d7EDt8zKniEAShErgFjDfZaDxakV1Rxi8RqzVRIwN1e3+VQI+AJhMASzuY04Br5OCyVW7yjsJGqKiCVJh/24exBgj7SAfsQldb/SgkvBYUnVCdAxNnOnkRK9X8AE8lAPvO7oiH805ogHnH+x79zqU9u/u5omwJ9KLCPgxXTZNeP6ojxdQY1XwFewASKQC6gPbbATeUmaJG6qOMB1+R6hBBcQ245UvONeaVJMK6dbg8qIoAnJTAvA1Uo0p1la5UGzNSejzE0ILCD8UnxJILUJ4I0KfeCRNAi16oDi4aeblr+mnxTI4XK4IuIAyblzz9EuwCCFirFBAGMkVVKxTi9cLFpk3Dx/wSaBsU8mlDCNIgLeZSAOA6bAU4QwWwEXgoWg/MRnp24a13mG+rOpSEQwJthfzb57YkwyMwHMn91VQ7DigjrD+/1G8DkjQQbd7e2g5+B3XmkK8Yu2f/kJ/tEmggvX/yScCg4scZgCv1tj2pgA7cMNVMIwB1cAlg+ngz5cTBNr7DwOY27bcUp4vQincjx6HfSPow8ch6SND24Uhx957ujH/9oAJI7WUwyfHBUFNkxOjsYz9vmDrf02rf1bIVVfeMV/25/qU4Vcb0ezMHdCJ07Afme9OH2hwZIpY2H6B+oiHqae/JSVC9YYzeMtn+NcBjz5cDWI5NssOcAfSZ+UYpgWbGdTM3JbZ8o2MbslMF0ZR3QvnoeuF63BPWZsXaNuRe0CsADl/Ye7hF/NUsrFXcNBgGxgxOIbF2uycFPNxszJXskP8YD9TzbPhVKa/XIMZvaEUzdU3R/4j7cxMso2W0jJbRMvr+QP8NsluKv9sZ0eAAAAAASUVORK5CYII=",p="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAIwAAABGCAAAAAA72CMwAAAABGdBTUEAALGPC/xhBQAAACBjSFJNAAB6JgAAgIQAAPoAAACA6AAAdTAAAOpgAAA6mAAAF3CculE8AAAAAmJLR0QA/4ePzL8AAAcdSURBVGje7Zh9UFTXFcB/sHzlKcIGt5ZvGgIFhEi0aIN0MQmlJpJhbFCridRxJtOksUmcqYwmEidWbSWZMU4S2wQjaaJt/WKcItUSU4LSiIiiIBSYUJdsXCWga/h4lM/tH2/38d7uggszQf/Y89e955w9+3vnvHvvedfDwr0jnncbwA3jhnHDuGHcMPeCuGHcMBMVr+/+Lzr3DoP3i9OAz6t8NAzGZd09mF6xtwZ+mA0MtLRC3MNjeXpMRafXuhbCP/YE+N0XH4aM6Tcl70y98ATGWgC+fnxslqmBqZ37NBQDiE0Pj+M3FTAj1fNikqg0Af8h6S7DGMQkcqAEqAv53jiOjqvp1qWLjV0kLkqZplK3fZWqmSRMvfAAC7XmY7/040KKrG2++YjHHTJzbcPSN0o0ob3lW548rQqYu2dkspm5OFeDdw7iv+irT5a11ZvedFjJFqUMHNDrs4+bLZa+f+r1+k9GDTcW61sslhvnyksO/NUyQRlefNhisdzU63MtNfoOWT30kr7IzlNVpvY8A5kv+QN+meHPUxg732r432ZxfQwcOQSE/2KCibkqPgTcn1lmqLscMlNWa/JXF4Vkjlmm9hcNZG/ylybxz8B71spY3mxJywbi04TJvDJEAyyF4vM/VuhnbmX7f8eC6X2lg0dfkRXZYPi3NKw9xRoP4LHtOyYBUyO9+QlxlDfOURpSktg3FsxeE8IoC7OAL6XhUZJjpFEIE5bhC9Z9LgfsdpkVnGl2DlNfDOsCFSYdtAFgqmSFI7urUicmSoN0gfAglSlVR5FTmP6dIGQoTUPwFQAlCLZaezBBOfPBq3xU0gPgs5wUtVHzFGe7nMF8aoRlvsr0mkEAGDpGss1tojDf7jggcu4tEYAs5tuZE6BOMZWX9llAlZirwAMAbSIP2ZQKmMGG89d0MbND5dS2NhOW7HWyypi+Wn7EgBOKiLoKe9Y4uJDmCNNfCdoIpWM9EAXQAgmOz9z2mhFBhLXPSCH+8j6AdlYTtM5JxjXxjzJUvexYpitAqsqxBoi0wvzA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VdPb73yBRC8sw/A+lPbgrpQ9rgWRt00qosAuD6lK0LPEUVxsyAHQC4d26Wyp4j2gnHh0eTXAJeJ7hVEpRxNCuQCxUFPdSl1faLqL5w3NTJ6coKPqrvq2kSN4Bp1I3hObz6Q7s25BKG/5fRI58I4R/HPiuS1uZohzcc/eeUPsd84b1O76J+P06BNQT6GxRgrIrLevOr8oxXR7mdLkuGQWVEshyVJ2uUYuJkklYnCtqR9iqLckaR5SqFUK44USIbbqjUVVRS33tpC4q7pfuCduBl+KLAP3Fstvx8uKivkMYB/IpXFF4OeFEcS0s0fNneaqFuLKzGs8rU6o+bCd7bcKF+UPW9QTTMSBpAMOWefUaclPbr8q84QzctqeXFZR4cBKv+0NouOMt9LNa3QWvuoSI6bYtQIzRscvdIJYmsNOgeBQYCtcvuJVaWJtnO23ZYCLrsiLpQd7hHGHHjPTxgKgCoAavJ5Tb1KsTza2pikI3igE8JrDvml7hAtWaB7WZS2wjUActGp8n3y+wx25DYB9EsjAWebBCfcIfKqIfUxMRlm0AG0HiBWfCoaNmTL/PWlDMAMxrsgvKM4Lbgdu/s0oAqiAhgBUCUzRhwY8KuYzd9xtRhTZb2/SxQt+aAfJuqMQChAGUTxUPY0FLsmqgSYqNIVAiE2xPAu1qs11Tlfa8PtD4oqUcVApCiryQfCAW7AEx3deU6rVR0yg+9L0QBT7Z2+0OCKsAB6ce4+YEF/gCZ0jmo3XVIRzIWD49srzD+bQsFxMencInyAAeLcHNDNAuAuwm5JTlYhZus362ldWHZljVhHLdx1rUUI8EBQHQTmW/PTJOQJ4MhH76Z8Y23W1Zgzoe/roDr50WN2jSIEqBOC+BHCDHZJm2q+paWUQNXPHQrXnWqkdY1iqG1rWO1Bpow+y9vqDKReNduQCbbzY8Da6RnAbfBXScz0d0VoF8JxexgtnxvRbQxwFzXWHWM/FSevjAKKYJwouGetrROC1EjIvA/AraW/EbZtpH3ET10luEC8VvRr9jNehWjCXRRoMgIwLThp/tf0dVopaZscl7wfTpk6Q5zoKt8SusYpT+JmdbyBhOzevqd6NQCzU8S7chSUDhL8uhpiaD2Wp1kyBICdp6KyfFWIUohwh8B7UfLViqr+IcPC1RNi4NIkwS+BiOaMO76m4MUAh7ePX/e4ulgltgPUBQGBgS/gan5h5RdF/yLxlhXDPn3V+iyf3TBllZa9lnRBcY4J3m5q0YU9S2mj4J7Ff0nUqn76gESgbLlhtRbyxHVu1CKeAd35vpixm19md3j11RyJfqePz340cGMlg/cqbQ1lcwX9QYImPCQicGbOntQOYQnojTPXJWgAywozWwAY4pDLB0gVg+rWa/MczI7LrZj4nLfl5VcA7lTbewXEYVk3VTVd6Y7tkgwN9vY8KVtRDNJRZWO2W+3NJKmg8xfOTm3uNHOW7WprrCQWzAQ0H4pwJ21dLy9Sv5R0D+H1QVz+T9bmZQiHCbAj2O3H0VZjYppTV7cSpSiNSw2tiqIoykHpM0VRCg1SUrk7Xa30scWp66G/WFv/HtEXaC8P1XZzRo8/irtvj8Z/IB6EB+FBPKqI/wBouXdVWw1KjgAAAABJRU5ErkJggg==",i="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAKQAAABGCAAAAABnUmAUAAAABGdBTUEAALGPC/xhBQAAACBjSFJNAAB6JgAAgIQAAPoAAACA6AAAdTAAAOpgAAA6mAAAF3CculE8AAAAAmJLR0QA/4ePzL8AAAhlSURBVGje7Zl/VJRVGsc/iMg4pTJL5AoKKIKLSpiJhuLrj9TF1Q6nFAwxf6b9EI/aWqda2bI019pTcdTKtB8Wx1VRdDV3jXQRYyXBVBiYA5McwFEUUUYBB4gf7/7xzo/3ZQaaIy3Lnub56977fJ/7fu9z733uc+/rJtL9pcf/moCLpIuki6SLZDcXF0kXye4mLpK/KpI9u/h7yXXQY04IULrXw4MWz5Xdj2SLsSEbGjYAdyvyYdBEZ6zcujozb51lgtQHAb5+d/N4p2y6fE2WmubA1wBc83GOY9eTLFCvUJPaCHD+USdtupzk+dGqOEyZQL3u4W5KsjXnEWZDKqDjISeN7Hd39cXzuhpGTo64T9Fcfnm8+y9AsswUhs+UDL1uOPm+Po4Qjdkhvj9D8uoHORDip8/I4C1B1q5N9H30lyCpVQ+BORkcGs4PEQ4RjVvYOlTZpAxBTak70Cyf4EXD6U2wfIFVUbnYtCuYynJTXU2PpzpD8vXmTcDSEtJ6z9ww2SEkd51mZxsfizK5vlAQNtZIZZ0gCGctivpnhEOiKG4TBEFIEDshLdGpoiiK/xCEL88JVe2APhWW1Cka5BuncmUZMa/2kSqhCbC91TyQd/VRMUBolLqTs11qCgOYouZg7qAH2gEtCit5T9EgI3l3TRVT1lgbYqDs31LxwgkWuwFTN73dSZL5DAVQPYHxbxHtgdyXcOLHdkjuqkBt40h/4JJUPMioYKnkS+fkXKS0+x4HwttFjQ7kC8cktWmQ6CVT+UA5ABVZzLMf071IXZaZ2YAoOoiSbvPJKnJEsnELqKfJoc1wGYCjqC0HmFtnKOpSnuNYqtTnkwz6TfvISXDKEclvDRDrKdO0GEEN0HyYURZYp0gm7zRg2CatttGBQgdI1XCyZVVrMM8GFI4sBYYAlJtsMyMj2VSYe9UneISfdSpKihk4qufx7w2Tnna8KnbIym67OxxPuK6s2uZpC8nGLND4y3FaIBBAD8Ptuyn/kwG1CZYmSF3s2QGg6V8EJeGjOuNwgBGQbwv1ljEXAMrs7hwQYCY52K6X0wsNw786dng+n61qAsR3djBz21/CjEVjP4Lb7X+95XJxjRMkB1s2rcKT+cDv5LCKLCAY4Brc37aTiiRC3lehedYnWffFcsg5xqB1PfF7moKBb5smWHHfKs1aL574CQZN88OxTLcU+sAde5L1gEaOTwWW9gWoQ223xrZCjApg1pfGlKhQMmFqT/APLDNpJ8hwZ5VmpZeCvBv0hs8jvHAktvxS7ZDkfUA/Gd6YBuo5ANzGrstrZ0CKSp5RR8kMpcrWeaUcuF5hVjU36g0PbsRyKe1nAq6HYs1YSAYATTLUEWCxNMt19rNdBphP3n5QDIE51AOYpJNKLh+X3Kpe9RgAhWSlLOHBx48aC8MAKDokZQc9eqgmhSvCm8ZotFUsIwoAbsocuReCYizjaLHzpGKURTABslqhuAz16DZY060So3kNekIN4A8VUkPtXX16ekGtqeZ62uplBXbObOvJgUD27y2tTUkmNFtUUsW7qrotyVagSepFBBOMeuxkxcboq/thQ+822BdPvY45iR3z3K15wA0sCygiIn0TG4OAH58peemQSuYl+tp70uN5yLC4snGzFvU7lsRTg83z5hTZT5pZJPcHQks+mpMvfVDh88lYu/WVx1izKzziE32gNRdCLcoC1IMBgiMxldpsGqRd0saTxGYUkZTcC6Dyz0UEbbQmPF5Wr1lJDgUM/SwzPwmuVM1aW1xxf4ijFDEXZWzPKOPZvjZlpOSnO9ZVDlCHI0/i/poPuqXfGWt178cVEfehLSnzAut8t0AL4BMDOQDcOA/T4DaFzSNnjHfE8aZBmZTVbmVGvFVZgbSGS3WEye4MRsUBYruIBaR8ts8ghYz4ufKvhUKRZcvWQX2LOyw8bdw9Yhz89CE87w8DKYsP8ejZq7d32AhPJckCGMad4/8KTlQBNL9hjFnjJlOOBLi+lkB5Ql0EwxyRRPXCE5dKy/sG+Af3UXwlHAonAZBy3ADG2d5rH3lg++qql6cFN2fqWRAHeE8+ZTQHbs3LyuM1jzEepWtDLhdFTgDE984tWuImU1JbIDZ893fiEmTzS4E5ubEjCQMGOHrk8goqyZNKdw1qT2g0NIPfrsP7TpyAPyzuD6AvtM3Uq58qbqS5PKxfvcL/rBTIPj+2ai68OT3SoiQJMLJmVi+50Q+Mk211nLjifSIIdxw0N+ovaG9KxepoIUHf0NJaX33mRUFIkqNuCcLH0emiVlhRK4riEeEbURRrhTxJWSUIh0VRFK+sE6L1MqMKQTgjqzrzPjk7hWPx9s29gq3F700kBQMqVeTYRJ2uzZLcs2gqI9M9gey/BlXvFZtKLHcly5L0S1xo2pZsMzqC7zhZH86QHPBk2r7YDoGy+OE+UFclV11Eze7Mzb6eQMkrlHwEgLekvGCOkgTARZuN6TCx8sPdqZvVfIyZHQIi4E3zyZ+ZzhTl6ko4MLFsWTNSZipJmHnr5DBaImCEEJvNNyb1dEX/Tj08fCXE3OkQsEcQntp3ta465zVBWCl/mTAKgla8Igg3mhPy7ayuC0KqVNoqCHttzdFCjgLn3Jt5wpV/btnY0SUsfsTO/O3bAdTzFsj71MEw7oImz2Cf3ueZ77WtB1IZM9fS2vyW6QXlw4FzJN3+WJl1ILYjxENbKwtumty8/cKVb29axnrgrzbV7Yxpk/A1nW7YD8Vl7i03MvUsm2e126WdEdfm804+7NeuLz94L09/b558ZSbs305Icpt3JG2itegTsei31srNORPXq5TQ//bfh9qqIQANV4d04sre5b9I7kX+L37buUi6SHY3cZF0kexu4iL5qyL5H376DahXLluHAAAAAElFTkSuQmCC",h="/zh-cn/assets/003b1add7c7cb3a3e1dc779588014fab-6e38a540.png",j="/zh-cn/assets/bfdd9f38cc1b1220f25734c917e16153-633580be.png",g="/zh-cn/assets/e05d5510aaeaf46a9e2cdf6ae3b818a2-b38efa29.png",d="/zh-cn/assets/7e948d626ced5b735cff1801c43863a5-6ab26544.png",u="/zh-cn/assets/dd296480837e3618f70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持久化存储设计与实现",description:"在 Xline 早期的原型阶段,我们采用了基于内存的存储来实现数据的持久化。这虽然简化了 Xline 原型设计的复杂度,提高了项目的开发和迭代速度,但带来的影响也是显著的:由于数据都存储在内存当中,因此一旦当进程 crash 后,节点的数据恢复需要依赖于从其他正常节点上拉取全量数据,这就需要较长的恢复时间。基于此方面的考虑,Xline 在最新发布的版本 v0.3.0 中引入了一个 Persistent Storage Layer,来将数据持久化到磁盘当中,同时向上层调用方屏蔽掉无关的底层细节。",location:"中国香港",author:["达坦科技"],tags:["Xline"],date:"2023-05-25",title:"Xline Persistent Storage Design and Implementation"},f=[{label:"引言",level:2},{label:"B+ Tree 读写放大分析",level:3},{label:"LSM Tree 读写放大分析",level:3},{label:"总结",level:3},{label:"持久化存储层设计与实现",level:2},{label:"整体架构与写入流程",level:3},{label:"接口设计",level:3},{label:"实现相关",level:3},{label:"性能评估",level:2}],k=`引言
在 Xline 早期的原型阶段,我们采用了基于内存的存储来实现数据的持久化。这虽然简化了 Xline 原型设计的复杂度,提高了项目的开发和迭代速度,但带来的影响也是显著的:由于数据都存储在内存当中,因此一旦当进程 crash 后,节点的数据恢复需要依赖于从其他正常节点上拉取全量数据,这就需要较长的恢复时间。
基于此方面的考虑,Xline 在最新发布的版本 v0.3.0 中引入了一个 Persistent Storage Layer,来将数据持久化到磁盘当中,同时向上层调用方屏蔽掉无关的底层细节。
## 存储引擎选型
@@ -476,4 +476,4 @@ StorageEngine Trait 定义(engine/src/engine_api.rs):
性能评估
在 v0.3.0 的新版本中,我们除了引入了 Persistent Storage Layer 以外,还对 CURP 的部分内容做了一些大型的重构。在重构完毕,添加新功能后,前不久通过了 validation test 和 Integration test。性能部分的测试信息,已经在 Xlinev0.4.0 中释放出来。
性能报告请参考链接:
-https://github.com/datenlord/Xline/blob/master/img/xline-key-perf.png
`;export{m as assetURLs,f as default,y as metadata,k as toc};
+https://github.com/datenlord/Xline/blob/master/img/xline-key-perf.png
`;export{m as assetURLs,k as default,y as metadata,f as toc};
diff --git a/zh-cn/assets/index-148365b0.js b/zh-cn/assets/index-93097ad1.js
similarity index 95%
rename from zh-cn/assets/index-148365b0.js
rename to zh-cn/assets/index-93097ad1.js
index d6740dd..a90e605 100644
--- a/zh-cn/assets/index-148365b0.js
+++ b/zh-cn/assets/index-93097ad1.js
@@ -1,4 +1,4 @@
-const e="/zh-cn/assets/cover-6865ae02.png",i=[e],l={label:"Xline v0.4.1:一个用于元数据管理的分布式KV存储",description:"Xline是一个基于Curp协议的,用于管理元数据的分布式KV存储。现有的分布式KV存储大多采用Raft共识协议,需要两次RTT才能完成一次请求。当部署在单个数据中心时,节点之间的延迟较低,因此不会对性能产生大的影响。",cover:"./cover.png",location:"中国香港",author:["达坦科技"],tags:["Xline"],date:"2023-06-21",title:"Xline v0.4.1: A distributed KV store for metadata management"},t=[{label:"Xline 是什么?我们为什么要做 Xline?",level:2},{label:"V0.4.0 版本有什么新功能?",level:3},{label:"欢迎参与到 Xline 项目中",level:2},{label:"相关链接",level:2}],s=`
+const i="/zh-cn/assets/cover-6865ae02.png",e=[i],l={label:"Xline v0.4.1:一个用于元数据管理的分布式KV存储",description:"Xline是一个基于Curp协议的,用于管理元数据的分布式KV存储。现有的分布式KV存储大多采用Raft共识协议,需要两次RTT才能完成一次请求。当部署在单个数据中心时,节点之间的延迟较低,因此不会对性能产生大的影响。",cover:"./cover.png",location:"中国香港",author:["达坦科技"],tags:["Xline"],date:"2023-06-21",title:"Xline v0.4.1: A distributed KV store for metadata management"},t=[{label:"Xline 是什么?我们为什么要做 Xline?",level:2},{label:"V0.4.0 版本有什么新功能?",level:3},{label:"欢迎参与到 Xline 项目中",level:2},{label:"相关链接",level:2}],s=`
Xline 是什么?我们为什么要做 Xline?
Xline 是一个基于 Curp 协议的,用于管理元数据的分布式 KV 存储。 现有的分布式 KV 存储大多采用 Raft 共识协议,需要两次 RTT 才能完成一次请求。当部署在单个数据中心时,节点之间的延迟较低,因此不会对性能产生大的影响。
但是,当跨数据中心部署时,节点之间的延迟可能是几十或几百毫秒,此时 Raft 协议将成为性能瓶颈。Curp 协议就是为了解决这个问题而设计的。它可以在命令不冲突的情况下减少一个 RTT,从而提高性能。因此,Xline 旨在实现高性能的数据访问和跨数据中心场景下的强一致性。
@@ -43,4 +43,4 @@ const e="/zh-cn/assets/cover-6865ae02.png",i=[e],l={label:"Xline v0.4.1:一个
Curp 相关文章:
https://medium.com/@datenlord/curp-revisit-the-consensus-protocol-384464be1600
Xline 官网:www.xline.cloud
-`;export{i as assetURLs,s as default,l as metadata,t as toc};
+`;export{e as assetURLs,s as default,l as metadata,t as toc};
diff --git a/zh-cn/assets/index-11e55415.js b/zh-cn/assets/index-982981c3.js
similarity index 88%
rename from zh-cn/assets/index-11e55415.js
rename to zh-cn/assets/index-982981c3.js
index 029e640..ad62cf6 100644
--- a/zh-cn/assets/index-11e55415.js
+++ b/zh-cn/assets/index-982981c3.js
@@ -1,4 +1,4 @@
-var GE=(e,t)=>()=>(t||e((t={exports:{}}).exports,t),t.exports);var kK=GE((DK,Gc)=>{(function(){const t=document.createElement("link").relList;if(t&&t.supports&&t.supports("modulepreload"))return;for(const i of document.querySelectorAll('link[rel="modulepreload"]'))n(i);new MutationObserver(i=>{for(const o of i)if(o.type==="childList")for(const a of o.addedNodes)a.tagName==="LINK"&&a.rel==="modulepreload"&&n(a)}).observe(document,{childList:!0,subtree:!0});function r(i){const o={};return i.integrity&&(o.integrity=i.integrity),i.referrerPolicy&&(o.referrerPolicy=i.referrerPolicy),i.crossOrigin==="use-credentials"?o.credentials="include":i.crossOrigin==="anonymous"?o.credentials="omit":o.credentials="same-origin",o}function n(i){if(i.ep)return;i.ep=!0;const o=r(i);fetch(i.href,o)}})();var Fo=typeof globalThis<"u"?globalThis:typeof window<"u"?window:typeof global<"u"?global:typeof self<"u"?self:{};function Uw(e){return e&&e.__esModule&&Object.prototype.hasOwnProperty.call(e,"default")?e.default:e}function XE(e){if(e.__esModule)return e;var t=e.default;if(typeof t=="function"){var r=function n(){if(this instanceof n){var i=[null];i.push.apply(i,arguments);var o=Function.bind.apply(t,i);return new o}return t.apply(this,arguments)};r.prototype=t.prototype}else r={};return Object.defineProperty(r,"__esModule",{value:!0}),Object.keys(e).forEach(function(n){var i=Object.getOwnPropertyDescriptor(e,n);Object.defineProperty(r,n,i.get?i:{enumerable:!0,get:function(){return e[n]}})}),r}var l={},KE={get exports(){return l},set exports(e){l=e}},Uu={},N={},QE={get exports(){return N},set exports(e){N=e}},ke={};/**
+var GE=(e,t)=>()=>(t||e((t={exports:{}}).exports,t),t.exports);var kK=GE((DK,Gc)=>{(function(){const t=document.createElement("link").relList;if(t&&t.supports&&t.supports("modulepreload"))return;for(const i of document.querySelectorAll('link[rel="modulepreload"]'))n(i);new MutationObserver(i=>{for(const o of i)if(o.type==="childList")for(const a of o.addedNodes)a.tagName==="LINK"&&a.rel==="modulepreload"&&n(a)}).observe(document,{childList:!0,subtree:!0});function r(i){const o={};return i.integrity&&(o.integrity=i.integrity),i.referrerPolicy&&(o.referrerPolicy=i.referrerPolicy),i.crossOrigin==="use-credentials"?o.credentials="include":i.crossOrigin==="anonymous"?o.credentials="omit":o.credentials="same-origin",o}function n(i){if(i.ep)return;i.ep=!0;const o=r(i);fetch(i.href,o)}})();var Vo=typeof globalThis<"u"?globalThis:typeof window<"u"?window:typeof global<"u"?global:typeof self<"u"?self:{};function Uw(e){return e&&e.__esModule&&Object.prototype.hasOwnProperty.call(e,"default")?e.default:e}function XE(e){if(e.__esModule)return e;var t=e.default;if(typeof t=="function"){var r=function n(){if(this instanceof n){var i=[null];i.push.apply(i,arguments);var o=Function.bind.apply(t,i);return new o}return t.apply(this,arguments)};r.prototype=t.prototype}else r={};return Object.defineProperty(r,"__esModule",{value:!0}),Object.keys(e).forEach(function(n){var i=Object.getOwnPropertyDescriptor(e,n);Object.defineProperty(r,n,i.get?i:{enumerable:!0,get:function(){return e[n]}})}),r}var l={},KE={get exports(){return l},set exports(e){l=e}},Uu={},N={},QE={get exports(){return N},set exports(e){N=e}},ke={};/**
* @license React
* react.production.min.js
*
@@ -22,7 +22,7 @@ var GE=(e,t)=>()=>(t||e((t={exports:{}}).exports,t),t.exports);var kK=GE((DK,Gc)
*
* This source code is licensed under the MIT license found in the
* LICENSE file in the root directory of this source tree.
- */(function(e){function t(W,le){var Q=W.length;W.push(le);e:for(;0>>1,he=W[ue];if(0>>1;uei(X,Q))$ti(tr,X)?(W[ue]=tr,W[$t]=Q,ue=$t):(W[ue]=X,W[Fe]=Q,ue=Fe);else if($ti(tr,Q))W[ue]=tr,W[$t]=Q,ue=$t;else break e}}return le}function i(W,le){var Q=W.sortIndex-le.sortIndex;return Q!==0?Q:W.id-le.id}if(typeof performance=="object"&&typeof performance.now=="function"){var o=performance;e.unstable_now=function(){return o.now()}}else{var a=Date,c=a.now();e.unstable_now=function(){return a.now()-c}}var d=[],h=[],g=1,v=null,x=3,b=!1,k=!1,C=!1,E=typeof setTimeout=="function"?setTimeout:null,y=typeof clearTimeout=="function"?clearTimeout:null,w=typeof setImmediate<"u"?setImmediate:null;typeof navigator<"u"&&navigator.scheduling!==void 0&&navigator.scheduling.isInputPending!==void 0&&navigator.scheduling.isInputPending.bind(navigator.scheduling);function S(W){for(var le=r(h);le!==null;){if(le.callback===null)n(h);else if(le.startTime<=W)n(h),le.sortIndex=le.expirationTime,t(d,le);else break;le=r(h)}}function T(W){if(C=!1,S(W),!k)if(r(d)!==null)k=!0,$e(O);else{var le=r(h);le!==null&&ht(T,le.startTime-W)}}function O(W,le){k=!1,C&&(C=!1,y(R),R=-1),b=!0;var Q=x;try{for(S(le),v=r(d);v!==null&&(!(v.expirationTime>le)||W&&!ee());){var ue=v.callback;if(typeof ue=="function"){v.callback=null,x=v.priorityLevel;var he=ue(v.expirationTime<=le);le=e.unstable_now(),typeof he=="function"?v.callback=he:v===r(d)&&n(d),S(le)}else n(d);v=r(d)}if(v!==null)var st=!0;else{var Fe=r(h);Fe!==null&&ht(T,Fe.startTime-le),st=!1}return st}finally{v=null,x=Q,b=!1}}var P=!1,M=null,R=-1,$=5,z=-1;function ee(){return!(e.unstable_now()-z<$)}function te(){if(M!==null){var W=e.unstable_now();z=W;var le=!0;try{le=M(!0,W)}finally{le?G():(P=!1,M=null)}}else P=!1}var G;if(typeof w=="function")G=function(){w(te)};else if(typeof MessageChannel<"u"){var lt=new MessageChannel,Te=lt.port2;lt.port1.onmessage=te,G=function(){Te.postMessage(null)}}else G=function(){E(te,0)};function $e(W){M=W,P||(P=!0,G())}function ht(W,le){R=E(function(){W(e.unstable_now())},le)}e.unstable_IdlePriority=5,e.unstable_ImmediatePriority=1,e.unstable_LowPriority=4,e.unstable_NormalPriority=3,e.unstable_Profiling=null,e.unstable_UserBlockingPriority=2,e.unstable_cancelCallback=function(W){W.callback=null},e.unstable_continueExecution=function(){k||b||(k=!0,$e(O))},e.unstable_forceFrameRate=function(W){0>W||125ue?(W.sortIndex=Q,t(h,W),r(d)===null&&W===r(h)&&(C?(y(R),R=-1):C=!0,ht(T,Q-ue))):(W.sortIndex=he,t(d,W),k||b||(k=!0,$e(O))),W},e.unstable_shouldYield=ee,e.unstable_wrapCallback=function(W){var le=x;return function(){var Q=x;x=le;try{return W.apply(this,arguments)}finally{x=Q}}}})(e_);(function(e){e.exports=e_})(wT);/**
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* @license React
* react-dom.production.min.js
*
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*
* This source code is licensed under the MIT license found in the
* LICENSE file in the root directory of this source tree.
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* React Router v6.11.1
*
* Copyright (c) Remix Software Inc.
@@ -55,7 +55,7 @@ Error generating stack: `+o.message+`
* LICENSE.md file in the root directory of this source tree.
*
* @license MIT
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+ */function wu(){return wu=Object.assign?Object.assign.bind():function(e){for(var t=1;tc.pathnameBase)),o=N.useRef(!1);return hx(()=>{o.current=!0}),N.useCallback(function(c,d){if(d===void 0&&(d={}),!o.current)return;if(typeof c=="number"){t.go(c);return}let h=H0(c,JSON.parse(i),n,d.relative==="path");e!=="/"&&(h.pathname=h.pathname==="/"?e:Un([e,h.pathname])),(d.replace?t.replace:t.push)(h,d.state,d)},[e,t,i,n])}const dP=N.createContext(null);function fP(e){let t=N.useContext(ei).outlet;return t&&N.createElement(dP.Provider,{value:e},t)}function gn(){let{matches:e}=N.useContext(ei),t=e[e.length-1];return t?t.params:{}}function mx(e,t){let{relative:r}=t===void 0?{}:t,{matches:n}=N.useContext(ei),{pathname:i}=ti(),o=JSON.stringify(ad(n).map(a=>a.pathnameBase));return N.useMemo(()=>H0(e,JSON.parse(o),i,r==="path"),[e,o,i,r])}function hP(e,t,r){yl()||be(!1);let{navigator:n}=N.useContext(Ns),{matches:i}=N.useContext(ei),o=i[i.length-1],a=o?o.params:{};o&&o.pathname;let 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i.track=a}),Se(xe(i),"adaptHeight",function(){if(i.props.adaptiveHeight&&i.list){var a=i.list.querySelector('[data-index="'.concat(i.state.currentSlide,'"]'));i.list.style.height=(0,rt.getHeight)(a)+"px"}}),Se(xe(i),"componentDidMount",function(){if(i.props.onInit&&i.props.onInit(),i.props.lazyLoad){var a=(0,rt.getOnDemandLazySlides)(de(de({},i.props),i.state));a.length>0&&(i.setState(function(d){return{lazyLoadedList:d.lazyLoadedList.concat(a)}}),i.props.onLazyLoad&&i.props.onLazyLoad(a))}var c=de({listRef:i.list,trackRef:i.track},i.props);i.updateState(c,!0,function(){i.adaptHeight(),i.props.autoplay&&i.autoPlay("update")}),i.props.lazyLoad==="progressive"&&(i.lazyLoadTimer=setInterval(i.progressiveLazyLoad,1e3)),i.ro=new JL.default(function(){i.state.animating?(i.onWindowResized(!1),i.callbackTimers.push(setTimeout(function(){return i.onWindowResized()},i.props.speed))):i.onWindowResized()}),i.ro.observe(i.list),document.querySelectorAll&&Array.prototype.forEach.call(document.querySelectorAll(".slick-slide"),function(d){d.onfocus=i.props.pauseOnFocus?i.onSlideFocus:null,d.onblur=i.props.pauseOnFocus?i.onSlideBlur:null}),window.addEventListener?window.addEventListener("resize",i.onWindowResized):window.attachEvent("onresize",i.onWindowResized)}),Se(xe(i),"componentWillUnmount",function(){i.animationEndCallback&&clearTimeout(i.animationEndCallback),i.lazyLoadTimer&&clearInterval(i.lazyLoadTimer),i.callbackTimers.length&&(i.callbackTimers.forEach(function(a){return clearTimeout(a)}),i.callbackTimers=[]),window.addEventListener?window.removeEventListener("resize",i.onWindowResized):window.detachEvent("onresize",i.onWindowResized),i.autoplayTimer&&clearInterval(i.autoplayTimer),i.ro.disconnect()}),Se(xe(i),"componentDidUpdate",function(a){if(i.checkImagesLoad(),i.props.onReInit&&i.props.onReInit(),i.props.lazyLoad){var c=(0,rt.getOnDemandLazySlides)(de(de({},i.props),i.state));c.length>0&&(i.setState(function(g){return{lazyLoadedList:g.lazyLoadedList.concat(c)}}),i.props.onLazyLoad&&i.props.onLazyLoad(c))}i.adaptHeight();var d=de(de({listRef:i.list,trackRef:i.track},i.props),i.state),h=i.didPropsChange(a);h&&i.updateState(d,h,function(){i.state.currentSlide>=Qt.default.Children.count(i.props.children)&&i.changeSlide({message:"index",index:Qt.default.Children.count(i.props.children)-i.props.slidesToShow,currentSlide:i.state.currentSlide}),i.props.autoplay?i.autoPlay("update"):i.pause("paused")})}),Se(xe(i),"onWindowResized",function(a){i.debouncedResize&&i.debouncedResize.cancel(),i.debouncedResize=(0,KL.default)(function(){return i.resizeWindow(a)},50),i.debouncedResize()}),Se(xe(i),"resizeWindow",function(){var a=arguments.length>0&&arguments[0]!==void 0?arguments[0]:!0,c=!!(i.track&&i.track.node);if(c){var d=de(de({listRef:i.list,trackRef:i.track},i.props),i.state);i.updateState(d,a,function(){i.props.autoplay?i.autoPlay("update"):i.pause("paused")}),i.setState({animating:!1}),clearTimeout(i.animationEndCallback),delete i.animationEndCallback}}),Se(xe(i),"updateState",function(a,c,d){var h=(0,rt.initializedState)(a);a=de(de(de({},a),h),{},{slideIndex:h.currentSlide});var g=(0,rt.getTrackLeft)(a);a=de(de({},a),{},{left:g});var v=(0,rt.getTrackCSS)(a);(c||Qt.default.Children.count(i.props.children)!==Qt.default.Children.count(a.children))&&(h.trackStyle=v),i.setState(h,d)}),Se(xe(i),"ssrInit",function(){if(i.props.variableWidth){var a=0,c=0,d=[],h=(0,rt.getPreClones)(de(de(de({},i.props),i.state),{},{slideCount:i.props.children.length})),g=(0,rt.getPostClones)(de(de(de({},i.props),i.state),{},{slideCount:i.props.children.length}));i.props.children.forEach(function(M){d.push(M.props.style.width),a+=M.props.style.width});for(var v=0;v=c&&i.onWindowResized()};if(!h.onclick)h.onclick=function(){return h.parentNode.focus()};else{var v=h.onclick;h.onclick=function(){v(),h.parentNode.focus()}}h.onload||(i.props.lazyLoad?h.onload=function(){i.adaptHeight(),i.callbackTimers.push(setTimeout(i.onWindowResized,i.props.speed))}:(h.onload=g,h.onerror=function(){g(),i.props.onLazyLoadError&&i.props.onLazyLoadError()}))})}),Se(xe(i),"progressiveLazyLoad",function(){for(var a=[],c=de(de({},i.props),i.state),d=i.state.currentSlide;d=-(0,rt.getPreClones)(c);h--)if(i.state.lazyLoadedList.indexOf(h)<0){a.push(h);break}a.length>0?(i.setState(function(g){return{lazyLoadedList:g.lazyLoadedList.concat(a)}}),i.props.onLazyLoad&&i.props.onLazyLoad(a)):i.lazyLoadTimer&&(clearInterval(i.lazyLoadTimer),delete i.lazyLoadTimer)}),Se(xe(i),"slideHandler",function(a){var c=arguments.length>1&&arguments[1]!==void 0?arguments[1]:!1,d=i.props,h=d.asNavFor,g=d.beforeChange,v=d.onLazyLoad,x=d.speed,b=d.afterChange,k=i.state.currentSlide,D=(0,rt.slideHandler)(de(de(de({index:a},i.props),i.state),{},{trackRef:i.track,useCSS:i.props.useCSS&&!c})),E=D.state,y=D.nextState;if(E){g&&g(k,E.currentSlide);var w=E.lazyLoadedList.filter(function(S){return i.state.lazyLoadedList.indexOf(S)<0});v&&w.length>0&&v(w),!i.props.waitForAnimate&&i.animationEndCallback&&(clearTimeout(i.animationEndCallback),b&&b(k),delete i.animationEndCallback),i.setState(E,function(){h&&i.asNavForIndex!==a&&(i.asNavForIndex=a,h.innerSlider.slideHandler(a)),y&&(i.animationEndCallback=setTimeout(function(){var S=y.animating,T=e3(y,["animating"]);i.setState(T,function(){i.callbackTimers.push(setTimeout(function(){return i.setState({animating:S})},10)),b&&b(E.currentSlide),delete i.animationEndCallback})},x))})}}),Se(xe(i),"changeSlide",function(a){var c=arguments.length>1&&arguments[1]!==void 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c=i.state.autoplaying;a==="paused"?i.setState({autoplaying:"paused"}):a==="focused"?(c==="hovered"||c==="playing")&&i.setState({autoplaying:"focused"}):c==="playing"&&i.setState({autoplaying:"hovered"})}),Se(xe(i),"onDotsOver",function(){return i.props.autoplay&&i.pause("hovered")}),Se(xe(i),"onDotsLeave",function(){return i.props.autoplay&&i.state.autoplaying==="hovered"&&i.autoPlay("leave")}),Se(xe(i),"onTrackOver",function(){return i.props.autoplay&&i.pause("hovered")}),Se(xe(i),"onTrackLeave",function(){return i.props.autoplay&&i.state.autoplaying==="hovered"&&i.autoPlay("leave")}),Se(xe(i),"onSlideFocus",function(){return i.props.autoplay&&i.pause("focused")}),Se(xe(i),"onSlideBlur",function(){return i.props.autoplay&&i.state.autoplaying==="focused"&&i.autoPlay("blur")}),Se(xe(i),"render",function(){var a=(0,QL.default)("slick-slider",i.props.className,{"slick-vertical":i.props.vertical,"slick-initialized":!0}),c=de(de({},i.props),i.state),d=(0,rt.extractObject)(c,["fade","cssEase","speed","infinite","centerMode","focusOnSelect","currentSlide","lazyLoad","lazyLoadedList","rtl","slideWidth","slideHeight","listHeight","vertical","slidesToShow","slidesToScroll","slideCount","trackStyle","variableWidth","unslick","centerPadding","targetSlide","useCSS"]),h=i.props.pauseOnHover;d=de(de({},d),{},{onMouseEnter:h?i.onTrackOver:null,onMouseLeave:h?i.onTrackLeave:null,onMouseOver:h?i.onTrackOver:null,focusOnSelect:i.props.focusOnSelect&&i.clickable?i.selectHandler:null});var g;if(i.props.dots===!0&&i.state.slideCount>=i.props.slidesToShow){var v=(0,rt.extractObject)(c,["dotsClass","slideCount","slidesToShow","currentSlide","slidesToScroll","clickHandler","children","customPaging","infinite","appendDots"]),x=i.props.pauseOnDotsHover;v=de(de({},v),{},{clickHandler:i.changeSlide,onMouseEnter:x?i.onDotsLeave:null,onMouseOver:x?i.onDotsOver:null,onMouseLeave:x?i.onDotsLeave:null}),g=Qt.default.createElement(ZL.Dots,v)}var b,k,D=(0,rt.extractObject)(c,["infinite","centerMode","currentSlide","slideCount","slidesToShow","prevArrow","nextArrow"]);D.clickHandler=i.changeSlide,i.props.arrows&&(b=Qt.default.createElement(D1.PrevArrow,D),k=Qt.default.createElement(D1.NextArrow,D));var E=null;i.props.vertical&&(E={height:i.state.listHeight});var y=null;i.props.vertical===!1?i.props.centerMode===!0&&(y={padding:"0px "+i.props.centerPadding}):i.props.centerMode===!0&&(y={padding:i.props.centerPadding+" 0px"});var w=de(de({},E),y),S=i.props.touchMove,T={className:"slick-list",style:w,onClick:i.clickHandler,onMouseDown:S?i.swipeStart:null,onMouseMove:i.state.dragging&&S?i.swipeMove:null,onMouseUp:S?i.swipeEnd:null,onMouseLeave:i.state.dragging&&S?i.swipeEnd:null,onTouchStart:S?i.swipeStart:null,onTouchMove:i.state.dragging&&S?i.swipeMove:null,onTouchEnd:S?i.touchEnd:null,onTouchCancel:i.state.dragging&&S?i.swipeEnd:null,onKeyDown:i.props.accessibility?i.keyHandler:null},O={className:a,dir:"ltr",style:i.props.style};return i.props.unslick&&(T={className:"slick-list"},O={className:a}),Qt.default.createElement("div",O,i.props.unslick?"":b,Qt.default.createElement("div",Pu({ref:i.listRefHandler},T),Qt.default.createElement(qL.Track,Pu({ref:i.trackRefHandler},d),i.props.children)),i.props.unslick?"":k,i.props.unslick?"":g)}),i.list=null,i.track=null,i.state=de(de({},XL.default),{},{currentSlide:i.props.initialSlide,slideCount:Qt.default.Children.count(i.props.children)}),i.callbackTimers=[],i.clickable=!0,i.debouncedResize=null;var o=i.ssrInit();return i.state=de(de({},i.state),o),i}return n3(r,[{key:"didPropsChange",value:function(i){for(var o=!1,a=0,c=Object.keys(this.props);a"u"||!Reflect.construct||Reflect.construct.sham)return!1;if(typeof Proxy=="function")return!0;try{return Boolean.prototype.valueOf.call(Reflect.construct(Boolean,[],function(){})),!0}catch{return!1}}function T(R){return T=Object.setPrototypeOf?Object.getPrototypeOf:function(z){return z.__proto__||Object.getPrototypeOf(z)},T(R)}function O(R,$,z){return $ in R?Object.defineProperty(R,$,{value:z,enumerable:!0,configurable:!0,writable:!0}):R[$]=z,R}var P=(0,a.canUseDOM)()&&y3(),M=function(R){k(z,R);var $=E(z);function z(ee){var te;return v(this,z),te=$.call(this,ee),O(w(te),"innerSliderRefHandler",function(G){return te.innerSlider=G}),O(w(te),"slickPrev",function(){return te.innerSlider.slickPrev()}),O(w(te),"slickNext",function(){return te.innerSlider.slickNext()}),O(w(te),"slickGoTo",function(G){var lt=arguments.length>1&&arguments[1]!==void 0?arguments[1]:!1;return te.innerSlider.slickGoTo(G,lt)}),O(w(te),"slickPause",function(){return te.innerSlider.pause("paused")}),O(w(te),"slickPlay",function(){return te.innerSlider.autoPlay("play")}),te.state={breakpoint:null},te._responsiveMediaHandlers=[],te}return b(z,[{key:"media",value:function(te,G){P.register(te,G),this._responsiveMediaHandlers.push({query:te,handler:G})}},{key:"componentDidMount",value:function(){var te=this;if(this.props.responsive){var G=this.props.responsive.map(function(Te){return Te.breakpoint});G.sort(function(Te,$e){return Te-$e}),G.forEach(function(Te,$e){var ht;$e===0?ht=(0,i.default)({minWidth:0,maxWidth:Te}):ht=(0,i.default)({minWidth:G[$e-1]+1,maxWidth:Te}),(0,a.canUseDOM)()&&te.media(ht,function(){te.setState({breakpoint:Te})})});var lt=(0,i.default)({minWidth:G.slice(-1)[0]});(0,a.canUseDOM)()&&this.media(lt,function(){te.setState({breakpoint:null})})}}},{key:"componentWillUnmount",value:function(){this._responsiveMediaHandlers.forEach(function(te){P.unregister(te.query,te.handler)})}},{key:"render",value:function(){var te=this,G,lt;this.state.breakpoint?(lt=this.props.responsive.filter(function(Ve){return Ve.breakpoint===te.state.breakpoint}),G=lt[0].settings==="unslick"?"unslick":g(g(g({},o.default),this.props),lt[0].settings)):G=g(g({},o.default),this.props),G.centerMode&&(G.slidesToScroll>1,G.slidesToScroll=1),G.fade&&(G.slidesToShow>1,G.slidesToScroll>1,G.slidesToShow=1,G.slidesToScroll=1);var Te=r.default.Children.toArray(this.props.children);Te=Te.filter(function(Ve){return typeof Ve=="string"?!!Ve.trim():!!Ve}),G.variableWidth&&(G.rows>1||G.slidesPerRow>1)&&(console.warn("variableWidth is not supported in case of rows > 1 or slidesPerRow > 1"),G.variableWidth=!1);for(var $e=[],ht=null,W=0;W=Te.length));he+=1)ue.push(r.default.cloneElement(Te[he],{key:100*W+10*Q+he,tabIndex:-1,style:{width:"".concat(100/G.slidesPerRow,"%"),display:"inline-block"}}));le.push(r.default.createElement("div",{key:10*W+Q},ue))}G.variableWidth?$e.push(r.default.createElement("div",{key:W,style:{width:ht}},le)):$e.push(r.default.createElement("div",{key:W},le))}if(G==="unslick"){var st="regular slider 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padding-block: 0.12rem;
padding-inline: 0.34rem;
color: inherit;
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`,Y3=f.img`
width: 0.14rem;
cursor: pointer;
-`,F3=f.p`
+`,V3=f.p`
font-size: 0.16rem;
line-height: 0.3rem;
-`,V3=new Map([["distributed-storage","company1"],["data-access","/solutions/data-access"],["metadata-management","/solutions/metadata-management"],["hardware-acceleration","/solutions"],["open-source","/resources1"]]),W3=()=>{const e=wt();return l.jsx(L3,{children:D3.map(({key:t,label:r,content:n,url:i})=>l.jsx(A3,{children:l.jsxs(I3,{children:[l.jsxs(N3,{children:[l.jsx($3,{children:r}),l.jsx(z3,{src:k3}),l.jsx(H3,{onClick:()=>{e(i)},children:"更多"}),l.jsx(Y3,{src:C3})]}),n.type==="ul"?null:l.jsx(F3,{children:n.content})]})},t))})},U3=({items:e})=>{const t=wt(),{key:r,title:n,description:i}=e;return l.jsx(R3,{bg:r,children:l.jsxs(M3,{children:[l.jsx(j3,{style:{marginBottom:"0.32rem"},children:n}),l.jsx(O3,{style:{maxWidth:"6.12rem",textAlign:"center",marginBottom:"0.7rem"},children:i}),l.jsx(fn,{style:{marginBottom:"1.49rem"},onClick:()=>{t(V3.get(r))},children:"了解更多"}),l.jsx(W3,{})]})})},B3=f.div`
+`,F3=new Map([["distributed-storage","company1"],["data-access","/solutions/data-access"],["metadata-management","/solutions/metadata-management"],["hardware-acceleration","/solutions"],["open-source","/resources1"]]),W3=()=>{const e=wt();return l.jsx(L3,{children:D3.map(({key:t,label:r,content:n,url:i})=>l.jsx(A3,{children:l.jsxs(I3,{children:[l.jsxs(N3,{children:[l.jsx($3,{children:r}),l.jsx(z3,{src:k3}),l.jsx(H3,{onClick:()=>{e(i)},children:"更多"}),l.jsx(Y3,{src:C3})]}),n.type==="ul"?null:l.jsx(V3,{children:n.content})]})},t))})},U3=({items:e})=>{const t=wt(),{key:r,title:n,description:i}=e;return l.jsx(R3,{bg:r,children:l.jsxs(M3,{children:[l.jsx(j3,{style:{marginBottom:"0.32rem"},children:n}),l.jsx(O3,{style:{maxWidth:"6.12rem",textAlign:"center",marginBottom:"0.7rem"},children:i}),l.jsx(fn,{style:{marginBottom:"1.49rem"},onClick:()=>{t(F3.get(r))},children:"了解更多"}),l.jsx(W3,{})]})})},B3=f.div`
background-color: #000;
`,G3={dots:!0,infinite:!0,speed:1e3,slidesToShow:1,slidesToScroll:1,arrows:!1,fade:!0,autoplay:!0,autoplaySpeed:6e3,pauseOnFocus:!0},X3=({items:e})=>l.jsx(B3,{children:l.jsx(w3,{...G3,children:e.map(t=>l.jsx(U3,{items:t},t.key))})}),K3="/zh-cn/assets/logo-dark-027b6609.svg",Q3="/zh-cn/assets/xline-logo-126dc1a3.svg",I1="/zh-cn/assets/cone-62ca8bad.png",{Heading:q3,Paragraph:Z3}=Me,{CNHead4:zd,CNTitleLarge:J3}=q3,{CNBodyLarge:Hd}=Z3,eA=f.section`
background: #ededf6;
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Linux”相关知识介绍。",date:"2022.11.08",url:"https://www.bilibili.com/video/BV1G8411a7CE/"},{key:12,image:uH,title:"Intel用户态中断",text:"本场workshop由韩明聪进行内容分享,主要进行了“Intel用户态中断”相关知识介绍。",date:"2022.11.08",url:"https://www.bilibili.com/video/BV1tG4y1t7Lg/"},{key:13,image:dH,title:"VLSI DSP Sharing",text:"本场workshop由达坦科技DatenLord李天瑞进行内容分享,主要进行了“VLSI DSP Intro”相关知识介绍。",date:"2022.11.11",url:"https://www.bilibili.com/video/BV18P4y1y7iP/"},{key:14,image:fH,title:"DSP Sharing Part2",text:"本场workshop由达坦科技DatenLord李天瑞进行内容分享,主要就DSP相关知识进行第二次workshop分享",date:"2022.11.12",url:"https://www.bilibili.com/video/BV1bM411k7YP/"},{key:15,image:hH,title:"eunomia-bpf: 结合 wasm 的 ebpf 轻量级开发框架",text:"本场workshop由浙江大学学生/eunomia-bpf 开发者 郑昱笙进行内容分享,主要内容围绕“eunomia-bpf: 结合 wasm 的 ebpf 轻量级开发框架”相关知识。",date:"2022.11.20",url:"https://www.bilibili.com/video/BV1u84y1C7pQ/"},{key:16,image:mH,title:"RDMA网络拥塞管理架构",text:"本场workshop由北京邮电大学网络与交换国家重点实验室、计算机学院,副研究员、博导:张乙然进行内容分享,主要内容围绕“RDMA网络拥塞管理架构”进行知识介绍。",date:"2022.11.27",url:"https://www.bilibili.com/video/BV1Ve4y1g7gx/"},{key:17,image:pH,title:"使用RDMA加速服务器无感知计算容器启动",text:"本场workshop由上海交通大学助理教授魏星达进行分享,主要内容围绕“使用RDMA加速服务器无感知计算容器启动”进行知识介绍。",date:"2022.12.04",url:"https://www.bilibili.com/video/BV1qG4y1G784/"},{key:19,image:gH,title:"基于智能网卡的数据处理系统",text:"本场workshop由浙江大学百人计划研究员 王则可进行分享,主要内容为“基于智能网卡的数据处理系统”介绍。",date:"2022.12.18",url:"https://www.bilibili.com/video/BV1Eg411J7fJ/"},{key:20,image:vH,title:"异步事件驱动的电路机制 & 基于RISC-V的全异步超标量CPU体系结构",text:"本场workshop由何安平副教授进行分享,主要内容为“异步事件驱动的电路机制 & 基于RISC-V的全异步超标量CPU体系结构”介绍。",date:"2022.12.25",url:"https://www.bilibili.com/video/BV1sA411D7on/"},{key:21,image:yH,title:"使用 TLA+ 为分布式算法验证正确性",text:"本场workshop由达坦科技DatenLord田野进行分享,主要内容为“使用 TLA+ 为分布式算法验证正确性”介绍。",date:"2023.01.09",url:"https://www.bilibili.com/video/BV1pG4y1y7an/"},{key:22,image:wH,title:"喷泉码技术简介",text:"本场workshop由兰州大学信息科学与工程学院副教授、通信工程专业系主任袁磊 进行分享,主要内容为“喷泉码技术简介”介绍。",date:"2023.01.15",url:"https://www.bilibili.com/video/BV1SM411b77k/"},{key:23,image:_H,title:"数据库隔离级别及MVCC",text:"本场workshop由达坦科技DatenLord施继成进行分享,主要内容为“数据库隔离级别及MVCC”介绍。",date:"2023.01.29",url:"https://www.bilibili.com/video/BV1sR4y1b7Cu/"},{key:24,image:xH,title:"互联网传输协议优化研究",text:"本场workshop由中国人民大学副教授李彤教授进行分享,主要内容为“互联网传输协议优化研究”介绍。",date:"2023.02.06",url:"https://www.bilibili.com/video/BV1X84y157vL/"},{key:25,image:SH,title:"高性能RDMA网络协议栈",text:"高性能RDMA网络协议栈是RDMA高性能网络的核心组成部分之一,它提供了支持RDMA技术的网络协议和驱动程序。在本周的前沿科技分享中,我们邀请到了湖南大学信息科学与工程学院的陈果教授来给我们分享高性能RDMA网络协议栈的话题。",date:"2023.02.28",url:"https://www.bilibili.com/video/BV1Y24y1n7Dk/"},{key:26,image:bH,title:"GPU抢占式任务调度",text:"GPU编程可以大幅提升计算速度和效率,从而使得许多计算任务得以在合理时间内完成。随着GPU硬件技术的发展和大规模数据处理需求的增加,GPU编程的应用范围不断扩大。在本周的前沿科技分享中,我们邀请到了上海交通大学并行与分布式研究所的韩明聪博士来给我们分享GPU抢占式任务调度。",date:"2023.03.05",url:"https://www.bilibili.com/video/BV1cY4y1y7ND/"},{key:27,image:kH,title:"聊聊RaptorQ纠错码",text:"喷泉码具有极高的纠错能力,且具有低延迟、地复杂度、高效率等优点,使其在冷存储、分布式存储、无线通信等领域得到广泛应用。达坦科技致力于软硬件融合的解决方案,喷泉码的高效实现在硬件上,作为公司长期的技术储备,在本周的前沿科技分享中,达坦科技的联合创始人兼CTO施继成将为大家分享聊聊 RaptorQ 纠错码 。",date:"2023.03.15",url:"https://www.bilibili.com/video/BV1wL411C7DL/"},{key:28,image:CH,title:"Buddy Compiler 简介和愿景",text:"在本次分享中,中国科学院软件研究所博士生张洪滨将介绍Buddy Compiler 编译流程、协同设计、硬件支持。Buddy Compiler 是领域特定的编译器框架,致力于打造基于 MLIR 和 RISC-V 的软硬件协同设计生态。其目标是实现从 DSL 到 DSA 的编译流程和协同设计,愿景是让领域特定的协同设计不再困难。",date:"2023.03.21",url:"https://www.bilibili.com/video/BV1YT41167GB/"},{key:29,image:DH,title:"新一代计算架构:超异构计算",text:"AGI带来的变化之一是算力将进一步从CPU转到GPU,在本周的前沿技术分享中,我们邀请到了上海矩向科技创始人兼CEO黄朝波为大家分享新一代计算架构:超异构计算。",date:"2023.04.04",url:"https://www.bilibili.com/video/BV1Rm4y1q7Dx/"},{key:30,image:EH,title:"通过Chainsaw设计DSP电路",text:"DSP在数据压缩、编码和加密方面都发挥了重要的作用;SpinalHDL具有更高的抽象层次和更强的表达能力,可以大大简化DSP电路设计的复杂度和提高开发效率;而Chainsaw框架可以在不同的FPGA平台上运行,提高了设计的灵活性和可移植性。在本周的前沿技术分享中,我们邀请到了中山大学在读博士李天瑞为大家分享通过Chainsaw设计DSP电路。",date:"2023.04.18",url:"https://www.bilibili.com/video/BV14o4y1j7bH/"},{key:31,image:TH,title:"Something About Cache Security",text:"在本周的前沿技术分享中,我们邀请到了浙江大学在读硕士研究生缪晨露为大家分享她在MICRO和HPCA上发表的两篇论文的精华,演讲主题是Something About Cache Security。",date:"2023.04.25",url:"https://www.bilibili.com/video/BV1p24y1F7fN/"},{key:32,image:jH,title:"Rust嵌入式开发生态介绍及入门",text:"在本周的前沿技术分享中,我们邀请到了一位爱好硬件的软件工程师米明恒,来为大家分享Rust嵌入式开发生态介绍及入门。",date:"2023.05.04",url:"https://www.bilibili.com/video/BV1J24y1T7EH/"},{key:33,image:OH,title:"RDMA赋能数据中心/超算中心间远程互联",text:"在本周的前沿技术分享中,我们邀请到了南京大学田臣教授,来为大家分享RDMA赋能数据中心/超算中心间远程互联。",date:"2023.06.04",url:"https://www.bilibili.com/video/BV1cz4y1B7cx/"},{key:34,image:PH,title:"Paper Reading: DPU任务卸载",text:"达坦科技一直在探索用硬件加速做分布式跨云存储,在本周的前沿技术分享中,我们邀请到了中南大学在读博士生卢军,来为大家分享DPU任务卸载的相关研究。",date:"2023.06.17",url:"https://www.bilibili.com/video/BV1R14y1S79T/"},{key:35,image:RH,title:"Rust在物理引擎研发中的应用",text:"在本周的前沿技术分享中,我们邀请到了Motphys CEO崔汉青,来为大家分享Rust在物理引擎研发中的应用。",date:"2023.06.27",url:"https://b23.tv/BZuSvyW"},{key:40,image:MH,title:"基于BSV的RTL仿真加速设计研究",text:"BSV的仿真加速可以提升硬件开发调试的效率。在本周的前沿技术分享中,我们邀请到了梁之杰,来为大家分享基于BSV的RTL仿真加速设计研究。",date:"2023.07.09",url:"https://www.bilibili.com/video/BV1ou411L7Yy/"},{key:41,image:LH,title:"RDMA网络的系统测试方案",text:"在本周的前沿技术分享中,我们邀请到了孔心皓,来为大家分享RDMA 网络的系统测试方案。",date:"2023.07.16",url:"https://www.bilibili.com/video/BV1tz4y147rw/"},{key:42,image:AH,title:"RapidWright技术分享会",text:"在本周的前沿技术分享中,我们邀请到了西南交通大学邸志雄副教授和他的学生向瀚章,来为大家分享开源FPGA设计工具RapidWright技术。",date:"2023.07.28",url:"https://www.bilibili.com/video/BV14z4y1x7a8/"},{key:43,image:IH,title:"基于Karmada实现Kubernetes应用跨集群故障转移",text:"在本周的前沿技术分享中,我们邀请到了开源爱好者,云兴科技软件研发工程师梁远鹏,来为大家分享基于Karmada实现Kubernetes应用跨集群故障转移。",date:"2023.08.01",url:"https://www.bilibili.com/video/BV1rN411Y7aZ/"},{key:50,image:NH,title:"大模型训练和基础设施",text:"在本周的前沿技术分享中,我们邀请到了范一呈,来为大家分享大模型训练和基础设施。",date:"2023.09.01",url:"https://www.bilibili.com/video/BV1ZN4y1R7HP/"},{key:51,image:$H,title:"RustBelt与Rust形式化方法",text:"在本周的前沿技术分享中,我们邀请到了王俊吉,来为大家分享RustBelt与Rust形式化方法。",date:"2023.09.04",url:"https://www.bilibili.com/video/BV1Vw411D7rT/"},{key:52,image:zH,title:"网络的智能该放在哪里:网卡、交换机还是xPU",text:"在本周的前沿技术分享中,我们邀请到了Logenic AI联合创始人、前华为天才少年李博杰,来为大家分享网络的智能该放在哪里:网卡、交换机还是xPU。",date:"2023.09.25",url:"https://www.bilibili.com/video/BV1Kw411Y7Cj/"},{key:53,image:HH,title:"以ARM为镜的RISC-V",text:"在本周的前沿技术分享中,我们邀请到了Logenic AI联合创始人、前华为天才少年李博杰,来为大家分享网络的智能该放在哪里:网卡、交换机还是xPU。",date:"2023.09.25",url:"https://www.bilibili.com/video/BV1Kw411Y7Cj/"},{key:54,image:YH,title:"面向网络测量的可编程交换机优化技术",text:"在本周的前沿技术分享中,我们邀请到了北京大学计算机学院黄群助理教授,来为大家分享面向网络测量的可编程交换机优化技术。",date:"2023.10.20",url:"https://www.bilibili.com/video/BV1i84y1974F/"}],VH="/zh-cn/assets/cover1-42e6189a.jpg",WH="/zh-cn/assets/cover2-af26ed46.jpg",UH="/zh-cn/assets/cover3-9c9d21fa.jpg",BH=[{key:1,image:VH,title:"Xline-跨数据中心一致性的元数据管理",text:"天空计算是云平台上的一层,其目标是打通彼此孤立的云,将分布式系统从数据中心范围扩展到全球范围。Xline是一款开源分布式KV存储系统,基于Curp共识算法实现,旨在提供跨云元数据管理的功能。相比于传统共识协议Raft或Paxos,Curp在天空计算的场景中有着更好的性能表现。本次分享将聚焦于共识算法,从天空计算的背景和挑战出发,介绍Curp共识算法,以及Revision机制与Curp无序性语义之间的冲突,最后,简述下Xline未来的优化方向。欢迎了解更多关于Xline的信息:Https://github.com/datenlord/Xline",date:"2023.02.09",url:"https://www.bilibili.com/video/BV1XY411q7X8/"},{key:2,image:WH,title:"源码解读:Xline Curp共识协议的设计与实现",text:"传统单数据中心解决方案无法满足跨数据中心的场景对性能和一致性的需求。DatenLord推出开源分布式KV存储Xline,针对多数据中心场景,可以实现数据的高性能跨云、跨数据中心共享访问,并且保证数据的一致性。",date:"2023.04.30",url:"https://www.bilibili.com/video/BV1dL411h7YK/"},{key:3,image:UH,title:"Xline的Lease机制与实现",text:"传统单数据中心解决方案无法满足跨数据中心的场景对性能和一致性的需求。DatenLord推出开源分布式KV存储Xline,针对多数据中心场景,可以实现数据的高性能跨云、跨数据中心共享访问,并且保证数据的一致性。",date:"2023.06.09",url:"https://www.bilibili.com/video/BV1FX4y1h7X5/"}],GH="/zh-cn/assets/cover1-a1358db9.jpg",XH="/zh-cn/assets/cover2-b899ea12.jpg",KH="/zh-cn/assets/cover3-e0bf4798.jpg",QH="/zh-cn/assets/cover4-15b0b4f1.jpg",qH="/zh-cn/assets/cover5-7c4c2482.jpg",ZH="/zh-cn/assets/cover6-1c4d5c5f.jpg",JH="/zh-cn/assets/cover7-4f7454c0.jpg",eY="/zh-cn/assets/cover8-7e30c0fc.jpg",tY="/zh-cn/assets/cover9-e8c86c60.jpg",rY="/zh-cn/assets/cover10-bb13b118.jpg",nY="/zh-cn/assets/cover11-c29e9692.jpg",iY="/zh-cn/assets/cover12-6877e246.jpg",oY="/zh-cn/assets/cover13-5a4d97b0.jpg",sY="/zh-cn/assets/cover14-052a8b36.jpg",aY=[{key:7,image:JH,title:"2022年Rust开发者大会Workshop One:用Rust实现RDMA高性能编程",text:"2022年7月31日,北京达坦科技有限公司获邀参加Rust China大会,并做公司专题workshop。这是本场workshop的第一部分,将为大家介绍如何用Rust实现RDMA高性能编程。",date:"2022.08.03",url:"https://www.bilibili.com/video/BV13e4y1D7Ch/"},{key:8,image:eY,title:"2022年Rust开发者大会Workshop Two:Async RDMA",text:"2022年7月31日,北京达坦科技有限公司获邀参加Rust China大会,并做公司专题workshop。这是第二部分workshop,将为大家介绍Async RDMA。",date:"2022.08.04",url:"https://www.bilibili.com/video/BV1Rh411M7EP/"},{key:9,image:tY,title:"2022年Rust开发者大会Workshop Three:Workshop动手实验环节",text:"2022年7月31日,北京达坦科技有限公司获邀参加Rust China大会,并做公司专题Workshop。这是本场Worshop的第三个部分:workshop动手环节 方便大家体验用Rust构建RDMA应用。",date:"2022.08.04",url:"https://www.bilibili.com/video/BV1oN4y1V7Hn/"},{key:1,image:GH,title:"Rust China Hackathon2022空中路演",text:"由Rust中文社区举办的题为「Rust For Fun」的首届Rust China Hackathon已经顺利完赛。达坦科技作为本届Hackathon的协办方,赞助参与本次企业组赛道。最终获得优胜奖的两支队伍在线上了举办一场空中路演。分享了:他们是如何思考拆解赛题的?在着手设计时碰到哪些难点和挑战?以及最终提交的代码设计思路和亮点。欢迎对Concurrent Indexing感兴趣的伙伴观看本条视频。",date:"2023.01.15",url:"https://www.bilibili.com/video/BV1xY41197Za/"},{key:2,image:XH,title:"4.8 Beijing Rust Meetup|张汉东《理解 Unsafe Rust》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场分享由《Rust 编程之道》作者、Rust 中文社区布道者张汉东老师进行,主题为《理解 Unsafe Rust》。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1c24y1A7aK/"},{key:3,image:KH,title:"4.8 Beijing Rust Meetup|冯洋《RUFES》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场由南京大学计算机科学与技术系助理研究员冯洋老师进行《基于实际场景应用分析的Rust库模糊测试技术报告》的演讲分享。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1Qo4y1n7tS/"},{key:4,image:QH,title:"4.8 Beijing Rust Meetup|施继成《Rust for Linux 6.2》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场分享由达坦科技联合创始人兼CTO施继成进行,演讲主题是《Rust for Linux 6.2》。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1Bs4y117Ze/"},{key:5,image:qH,title:"4.8 Beijing Rust Meetup|叶天星《用Rust实现Git传输协议、Git对象解析和数据库存储》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场分享由达坦科技联合创始人兼CTO施继成进行,演讲主题是《Rust for Linux 6.2》。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1Bs4y117Ze/"},{key:6,image:ZH,title:"4.8 Beijing Rust Meetup|茌海《Monoio:一个基于 io-uring 的 Rust Runtime》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场分享由达坦科技联合创始人兼CTO施继成进行,演讲主题是《Rust for Linux 6.2》。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1Rh411M7EP/"},{key:10,image:rY,title:"如何用Rust写分布式系统",text:"分享会介绍分布式KV Store (Xline) 整体的组成,以及不同组件之间如何去交互。在广域网下的分布式系统如何高效地达成共识,以及分布式系统如何实现容错。",date:"2023.06.24",url:"https://www.bilibili.com/video/BV1Hs4y1r7dD/"},{key:11,image:nY,title:"Building microsecond-scale system with modern networking in Rust",text:"随着新型网络技术,如RDMA的普及,现代分布式应用的延迟降到了毫秒甚至微秒级别。这为构建系统软件带来了新的挑战。Rust的zero-cost抽象及内存管理能力能够为构建新型分布式应用带来新的机遇。我将分享利用Rust在用户态及内核态构建新型系统软件的相关经验,包括如何利用Rust抽象RDMA硬件的底层抽象及如何在内核构建一个毫秒级的容器启动机制。",date:"2023.06.24",url:"https://www.bilibili.com/video/BV1Zo4y1P7Sg/"},{key:12,image:iY,title:"30分钟体验Rust for Linux内核模块开发",text:"本主题会提供构建好的docker开发环境,在30分钟内演示如何使用r4l开发一个简易内核模块,并介绍目前r4l的发展现状。可以自备好电脑现场体验。",date:"2023.06.24",url:"https://www.bilibili.com/video/BV12j411U78o/"},{key:13,image:oY,title:"DatenLord 2023 Hackathon赛题宣讲会",text:"达坦科技基于其跨云分布式文件系统DatenLord项目,结合AI大模型时代背景,搭建了擂台,在此正式向您发出邀约!本次大赛主题为 Explore the Possibilities 赛题深刻有趣,奖品丰厚多样,借此机会您不仅可以尽情施展才华、与来自全国各地优秀的青年才俊们同台PK,更将有机会与优秀的评委教师对话交流。Clock is Ticking!无需犹豫,行动起来吧!",date:"2023.11.25",url:"https://www.bilibili.com/video/BV1su4y157iB/"},{key:14,image:sY,title:"DatenLord Hackathon2023空中路演",text:"DatenLord Hackathon 2023已经顺利完赛。达坦科技基于其跨云分布式文件系统DatenLord项目,结合AI大模型时代背景,搭建了擂台。我们邀请参赛者为DatenLord的极端场景设计并实现缓存 p2p 传输和同步模块。本次空中路演邀请了最终获得优胜奖的两支队伍进行思路分享,包括他们的解题思路,碰到的难点和挑战,以及如何应对的方法和设计亮点。欢迎感兴趣的大家进行观看,有问题也欢迎在评论区进行交流~~不要忘记一键三连哦~~",date:"2024.01.07",url:"https://www.bilibili.com/video/BV1ic411t7Nf/"}],lY="/zh-cn/assets/cover1-b9371555.jpg",cY="/zh-cn/assets/cover2-41a903e3.jpg",uY="/zh-cn/assets/cover2-41a903e3.jpg",dY="/zh-cn/assets/cover2-41a903e3.jpg",fY="/zh-cn/assets/cover2-41a903e3.jpg",hY="/zh-cn/assets/cover2-41a903e3.jpg",mY="/zh-cn/assets/cover2-41a903e3.jpg",pY="/zh-cn/assets/cover2-41a903e3.jpg",gY="/zh-cn/assets/cover2-41a903e3.jpg",vY="/zh-cn/assets/cover13-a69a12b0.jpg",yY="/zh-cn/assets/cover14-3a97e013.jpg",wY="/zh-cn/assets/cover14-3a97e013.jpg",_Y="/zh-cn/assets/cover14-3a97e013.jpg",xY="/zh-cn/assets/cover14-3a97e013.jpg",SY="/zh-cn/assets/cover14-3a97e013.jpg",bY="/zh-cn/assets/cover14-3a97e013.jpg",kY="/zh-cn/assets/cover20-c97bc11b.jpg",CY="/zh-cn/assets/cover21-9f52ba13.jpg",DY="/zh-cn/assets/cover22-187b655a.jpg",EY="/zh-cn/assets/cover23-1e515665.jpg",TY="/zh-cn/assets/cover24-020d0c34.jpg",jY="/zh-cn/assets/cover25-cb84d871.jpg",OY="/zh-cn/assets/cover26-7a726e97.jpg",PY="/zh-cn/assets/cover27-401eea81.jpg",RY="/zh-cn/assets/cover28-6ddc6bee.jpg",MY="/zh-cn/assets/cover29-0d2deb11.jpg",LY=[{key:1,image:lY,title:"Utilizing SpinalHDL for Large-scale Datapath Design",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的一个workshop:Utilizing SpinalHDL for Large-scale Datapath Design,由李天瑞进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1PM411m7DB/"},{key:2,image:cY,title:"A Network Attached Deep Learning Accelerator for FPGA Clusters",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的三个workshop:A Network Attached Deep Learning Accelerator for FPGA Clusters,由Philipp Kreowsky Justin Knapheide进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1HM411m7mS/"},{key:3,image:uY,title:"Coding a microprogrammed protocol receiver in SpinalHDL",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的五个workshop:Coding a microprogrammed protocol receiver in SpinalHDL,由Michael Meier进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1oK411z7VD/"},{key:4,image:dY,title:"Utilizing SpinalHDL to Accelerate Neuroscience",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的二个workshop:Utilizing SpinalHDL to Accelerate Neuroscience,由Jeff-Ciesielski进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1GG4y1J7gU/"},{key:5,image:fY,title:"SpinalHDL in Computer Architecture Research",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的四个workshop:SpinalHDL in Computer Architecture Research,由Sallar Ahmadi-Pour ( saahm)进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1gA411X7f8/"},{key:6,image:hY,title:"NaxRiscv: A Pipeline/Plugins/SpinalHDL/Scala mix",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的第六个workshop:NaxRiscv: A Pipeline/Plugins/SpinalHDL/Scala mix,由Dolu1990进行分享。",date:"2022.12.21",url:"https://www.bilibili.com/video/BV13K41167q5/"},{key:7,image:mY,title:"Recent progress on formal verification support on SpinalHDL",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的第七个workshop:Recent progress on formal verification support on SpinalHDL,由Xiao Yindong (Readon)进行分享。",date:"2022.12.21",url:"https://www.bilibili.com/video/BV1bG411N7fk/"},{key:8,image:pY,title:"SpinalHDL for ASIC",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的第八个workshop:SpinalHDL for ASIC,由Sebastien-riou进行分享。",date:"2022.12.21",url:"https://www.bilibili.com/video/BV16e4y1L7dV/"},{key:9,image:gY,title:"From Peripheral Plugins to Product documentation",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的第九个workshop:From Peripheral Plugins to Product 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硕士研究生李钊进行内容分享,主要进行了Corumdum相关知识介绍。",date:"2022.10.16",url:"https://www.bilibili.com/video/BV1qG41177Pq/"},{key:8,image:sH,title:"可编程交换机:原理与使用",text:"本场workshop由上海交通大学IPADS实验室博士二年级 张汉泽进行内容分享,主要进行了“可编程交换机:原理与使用”相关知识分享。可编程交换机由安装包处理规则的控制面与负责高速包处理的数据面构成,两者由一根PCIe总线相连。控制面支持高级语言编程,而数据面逻辑需要用P4语言编写。在可编程交换机上设计系统主要面临数据面内存有限与P4编程模型受限两大挑战。",date:"2022.10.23",url:"https://www.bilibili.com/video/BV1jm4y1w7w3/"},{key:9,image:aH,title:"形式化验证入门",text:"本场workshop由达坦科技DatenLord王璞进行内容分享,主要进行了形式化验证入门相关知识介绍。",date:"2022.10.26",url:"https://www.bilibili.com/video/BV1DG411L78p/"},{key:10,image:lH,title:"利用RDMA加速FaaS服务",text:"本场workshop由达坦科技DatenLord李弘宇进行内容分享,主要进行了“利用RDMA加速FaaS服务”相关知识介绍。",date:"2022.11.06",url:"https://www.bilibili.com/video/BV1et4y1K7Sw/"},{key:11,image:cH,title:"Rust for Linux",text:"本场workshop由苏宇恒进行内容分享,主要进行了“Rust for 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轻量级开发框架”相关知识。",date:"2022.11.20",url:"https://www.bilibili.com/video/BV1u84y1C7pQ/"},{key:16,image:mH,title:"RDMA网络拥塞管理架构",text:"本场workshop由北京邮电大学网络与交换国家重点实验室、计算机学院,副研究员、博导:张乙然进行内容分享,主要内容围绕“RDMA网络拥塞管理架构”进行知识介绍。",date:"2022.11.27",url:"https://www.bilibili.com/video/BV1Ve4y1g7gx/"},{key:17,image:pH,title:"使用RDMA加速服务器无感知计算容器启动",text:"本场workshop由上海交通大学助理教授魏星达进行分享,主要内容围绕“使用RDMA加速服务器无感知计算容器启动”进行知识介绍。",date:"2022.12.04",url:"https://www.bilibili.com/video/BV1qG4y1G784/"},{key:19,image:gH,title:"基于智能网卡的数据处理系统",text:"本场workshop由浙江大学百人计划研究员 王则可进行分享,主要内容为“基于智能网卡的数据处理系统”介绍。",date:"2022.12.18",url:"https://www.bilibili.com/video/BV1Eg411J7fJ/"},{key:20,image:vH,title:"异步事件驱动的电路机制 & 基于RISC-V的全异步超标量CPU体系结构",text:"本场workshop由何安平副教授进行分享,主要内容为“异步事件驱动的电路机制 & 基于RISC-V的全异步超标量CPU体系结构”介绍。",date:"2022.12.25",url:"https://www.bilibili.com/video/BV1sA411D7on/"},{key:21,image:yH,title:"使用 TLA+ 为分布式算法验证正确性",text:"本场workshop由达坦科技DatenLord田野进行分享,主要内容为“使用 TLA+ 为分布式算法验证正确性”介绍。",date:"2023.01.09",url:"https://www.bilibili.com/video/BV1pG4y1y7an/"},{key:22,image:wH,title:"喷泉码技术简介",text:"本场workshop由兰州大学信息科学与工程学院副教授、通信工程专业系主任袁磊 进行分享,主要内容为“喷泉码技术简介”介绍。",date:"2023.01.15",url:"https://www.bilibili.com/video/BV1SM411b77k/"},{key:23,image:_H,title:"数据库隔离级别及MVCC",text:"本场workshop由达坦科技DatenLord施继成进行分享,主要内容为“数据库隔离级别及MVCC”介绍。",date:"2023.01.29",url:"https://www.bilibili.com/video/BV1sR4y1b7Cu/"},{key:24,image:xH,title:"互联网传输协议优化研究",text:"本场workshop由中国人民大学副教授李彤教授进行分享,主要内容为“互联网传输协议优化研究”介绍。",date:"2023.02.06",url:"https://www.bilibili.com/video/BV1X84y157vL/"},{key:25,image:SH,title:"高性能RDMA网络协议栈",text:"高性能RDMA网络协议栈是RDMA高性能网络的核心组成部分之一,它提供了支持RDMA技术的网络协议和驱动程序。在本周的前沿科技分享中,我们邀请到了湖南大学信息科学与工程学院的陈果教授来给我们分享高性能RDMA网络协议栈的话题。",date:"2023.02.28",url:"https://www.bilibili.com/video/BV1Y24y1n7Dk/"},{key:26,image:bH,title:"GPU抢占式任务调度",text:"GPU编程可以大幅提升计算速度和效率,从而使得许多计算任务得以在合理时间内完成。随着GPU硬件技术的发展和大规模数据处理需求的增加,GPU编程的应用范围不断扩大。在本周的前沿科技分享中,我们邀请到了上海交通大学并行与分布式研究所的韩明聪博士来给我们分享GPU抢占式任务调度。",date:"2023.03.05",url:"https://www.bilibili.com/video/BV1cY4y1y7ND/"},{key:27,image:kH,title:"聊聊RaptorQ纠错码",text:"喷泉码具有极高的纠错能力,且具有低延迟、地复杂度、高效率等优点,使其在冷存储、分布式存储、无线通信等领域得到广泛应用。达坦科技致力于软硬件融合的解决方案,喷泉码的高效实现在硬件上,作为公司长期的技术储备,在本周的前沿科技分享中,达坦科技的联合创始人兼CTO施继成将为大家分享聊聊 RaptorQ 纠错码 。",date:"2023.03.15",url:"https://www.bilibili.com/video/BV1wL411C7DL/"},{key:28,image:CH,title:"Buddy Compiler 简介和愿景",text:"在本次分享中,中国科学院软件研究所博士生张洪滨将介绍Buddy Compiler 编译流程、协同设计、硬件支持。Buddy Compiler 是领域特定的编译器框架,致力于打造基于 MLIR 和 RISC-V 的软硬件协同设计生态。其目标是实现从 DSL 到 DSA 的编译流程和协同设计,愿景是让领域特定的协同设计不再困难。",date:"2023.03.21",url:"https://www.bilibili.com/video/BV1YT41167GB/"},{key:29,image:DH,title:"新一代计算架构:超异构计算",text:"AGI带来的变化之一是算力将进一步从CPU转到GPU,在本周的前沿技术分享中,我们邀请到了上海矩向科技创始人兼CEO黄朝波为大家分享新一代计算架构:超异构计算。",date:"2023.04.04",url:"https://www.bilibili.com/video/BV1Rm4y1q7Dx/"},{key:30,image:EH,title:"通过Chainsaw设计DSP电路",text:"DSP在数据压缩、编码和加密方面都发挥了重要的作用;SpinalHDL具有更高的抽象层次和更强的表达能力,可以大大简化DSP电路设计的复杂度和提高开发效率;而Chainsaw框架可以在不同的FPGA平台上运行,提高了设计的灵活性和可移植性。在本周的前沿技术分享中,我们邀请到了中山大学在读博士李天瑞为大家分享通过Chainsaw设计DSP电路。",date:"2023.04.18",url:"https://www.bilibili.com/video/BV14o4y1j7bH/"},{key:31,image:TH,title:"Something About Cache Security",text:"在本周的前沿技术分享中,我们邀请到了浙江大学在读硕士研究生缪晨露为大家分享她在MICRO和HPCA上发表的两篇论文的精华,演讲主题是Something About Cache Security。",date:"2023.04.25",url:"https://www.bilibili.com/video/BV1p24y1F7fN/"},{key:32,image:jH,title:"Rust嵌入式开发生态介绍及入门",text:"在本周的前沿技术分享中,我们邀请到了一位爱好硬件的软件工程师米明恒,来为大家分享Rust嵌入式开发生态介绍及入门。",date:"2023.05.04",url:"https://www.bilibili.com/video/BV1J24y1T7EH/"},{key:33,image:OH,title:"RDMA赋能数据中心/超算中心间远程互联",text:"在本周的前沿技术分享中,我们邀请到了南京大学田臣教授,来为大家分享RDMA赋能数据中心/超算中心间远程互联。",date:"2023.06.04",url:"https://www.bilibili.com/video/BV1cz4y1B7cx/"},{key:34,image:PH,title:"Paper Reading: DPU任务卸载",text:"达坦科技一直在探索用硬件加速做分布式跨云存储,在本周的前沿技术分享中,我们邀请到了中南大学在读博士生卢军,来为大家分享DPU任务卸载的相关研究。",date:"2023.06.17",url:"https://www.bilibili.com/video/BV1R14y1S79T/"},{key:35,image:RH,title:"Rust在物理引擎研发中的应用",text:"在本周的前沿技术分享中,我们邀请到了Motphys CEO崔汉青,来为大家分享Rust在物理引擎研发中的应用。",date:"2023.06.27",url:"https://b23.tv/BZuSvyW"},{key:40,image:MH,title:"基于BSV的RTL仿真加速设计研究",text:"BSV的仿真加速可以提升硬件开发调试的效率。在本周的前沿技术分享中,我们邀请到了梁之杰,来为大家分享基于BSV的RTL仿真加速设计研究。",date:"2023.07.09",url:"https://www.bilibili.com/video/BV1ou411L7Yy/"},{key:41,image:LH,title:"RDMA网络的系统测试方案",text:"在本周的前沿技术分享中,我们邀请到了孔心皓,来为大家分享RDMA 网络的系统测试方案。",date:"2023.07.16",url:"https://www.bilibili.com/video/BV1tz4y147rw/"},{key:42,image:AH,title:"RapidWright技术分享会",text:"在本周的前沿技术分享中,我们邀请到了西南交通大学邸志雄副教授和他的学生向瀚章,来为大家分享开源FPGA设计工具RapidWright技术。",date:"2023.07.28",url:"https://www.bilibili.com/video/BV14z4y1x7a8/"},{key:43,image:IH,title:"基于Karmada实现Kubernetes应用跨集群故障转移",text:"在本周的前沿技术分享中,我们邀请到了开源爱好者,云兴科技软件研发工程师梁远鹏,来为大家分享基于Karmada实现Kubernetes应用跨集群故障转移。",date:"2023.08.01",url:"https://www.bilibili.com/video/BV1rN411Y7aZ/"},{key:50,image:NH,title:"大模型训练和基础设施",text:"在本周的前沿技术分享中,我们邀请到了范一呈,来为大家分享大模型训练和基础设施。",date:"2023.09.01",url:"https://www.bilibili.com/video/BV1ZN4y1R7HP/"},{key:51,image:$H,title:"RustBelt与Rust形式化方法",text:"在本周的前沿技术分享中,我们邀请到了王俊吉,来为大家分享RustBelt与Rust形式化方法。",date:"2023.09.04",url:"https://www.bilibili.com/video/BV1Vw411D7rT/"},{key:52,image:zH,title:"网络的智能该放在哪里:网卡、交换机还是xPU",text:"在本周的前沿技术分享中,我们邀请到了Logenic AI联合创始人、前华为天才少年李博杰,来为大家分享网络的智能该放在哪里:网卡、交换机还是xPU。",date:"2023.09.25",url:"https://www.bilibili.com/video/BV1Kw411Y7Cj/"},{key:53,image:HH,title:"以ARM为镜的RISC-V",text:"在本周的前沿技术分享中,我们邀请到了Logenic AI联合创始人、前华为天才少年李博杰,来为大家分享网络的智能该放在哪里:网卡、交换机还是xPU。",date:"2023.09.25",url:"https://www.bilibili.com/video/BV1Kw411Y7Cj/"},{key:54,image:YH,title:"面向网络测量的可编程交换机优化技术",text:"在本周的前沿技术分享中,我们邀请到了北京大学计算机学院黄群助理教授,来为大家分享面向网络测量的可编程交换机优化技术。",date:"2023.10.20",url:"https://www.bilibili.com/video/BV1i84y1974F/"}],FH="/zh-cn/assets/cover1-42e6189a.jpg",WH="/zh-cn/assets/cover2-af26ed46.jpg",UH="/zh-cn/assets/cover3-9c9d21fa.jpg",BH=[{key:1,image:FH,title:"Xline-跨数据中心一致性的元数据管理",text:"天空计算是云平台上的一层,其目标是打通彼此孤立的云,将分布式系统从数据中心范围扩展到全球范围。Xline是一款开源分布式KV存储系统,基于Curp共识算法实现,旨在提供跨云元数据管理的功能。相比于传统共识协议Raft或Paxos,Curp在天空计算的场景中有着更好的性能表现。本次分享将聚焦于共识算法,从天空计算的背景和挑战出发,介绍Curp共识算法,以及Revision机制与Curp无序性语义之间的冲突,最后,简述下Xline未来的优化方向。欢迎了解更多关于Xline的信息:Https://github.com/datenlord/Xline",date:"2023.02.09",url:"https://www.bilibili.com/video/BV1XY411q7X8/"},{key:2,image:WH,title:"源码解读:Xline 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One:用Rust实现RDMA高性能编程",text:"2022年7月31日,北京达坦科技有限公司获邀参加Rust China大会,并做公司专题workshop。这是本场workshop的第一部分,将为大家介绍如何用Rust实现RDMA高性能编程。",date:"2022.08.03",url:"https://www.bilibili.com/video/BV13e4y1D7Ch/"},{key:8,image:eY,title:"2022年Rust开发者大会Workshop Two:Async RDMA",text:"2022年7月31日,北京达坦科技有限公司获邀参加Rust China大会,并做公司专题workshop。这是第二部分workshop,将为大家介绍Async RDMA。",date:"2022.08.04",url:"https://www.bilibili.com/video/BV1Rh411M7EP/"},{key:9,image:tY,title:"2022年Rust开发者大会Workshop Three:Workshop动手实验环节",text:"2022年7月31日,北京达坦科技有限公司获邀参加Rust China大会,并做公司专题Workshop。这是本场Worshop的第三个部分:workshop动手环节 方便大家体验用Rust构建RDMA应用。",date:"2022.08.04",url:"https://www.bilibili.com/video/BV1oN4y1V7Hn/"},{key:1,image:GH,title:"Rust China Hackathon2022空中路演",text:"由Rust中文社区举办的题为「Rust For Fun」的首届Rust China Hackathon已经顺利完赛。达坦科技作为本届Hackathon的协办方,赞助参与本次企业组赛道。最终获得优胜奖的两支队伍在线上了举办一场空中路演。分享了:他们是如何思考拆解赛题的?在着手设计时碰到哪些难点和挑战?以及最终提交的代码设计思路和亮点。欢迎对Concurrent Indexing感兴趣的伙伴观看本条视频。",date:"2023.01.15",url:"https://www.bilibili.com/video/BV1xY41197Za/"},{key:2,image:XH,title:"4.8 Beijing Rust Meetup|张汉东《理解 Unsafe Rust》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场分享由《Rust 编程之道》作者、Rust 中文社区布道者张汉东老师进行,主题为《理解 Unsafe Rust》。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1c24y1A7aK/"},{key:3,image:KH,title:"4.8 Beijing Rust Meetup|冯洋《RUFES》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场由南京大学计算机科学与技术系助理研究员冯洋老师进行《基于实际场景应用分析的Rust库模糊测试技术报告》的演讲分享。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1Qo4y1n7tS/"},{key:4,image:QH,title:"4.8 Beijing Rust Meetup|施继成《Rust for Linux 6.2》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场分享由达坦科技联合创始人兼CTO施继成进行,演讲主题是《Rust for Linux 6.2》。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1Bs4y117Ze/"},{key:5,image:qH,title:"4.8 Beijing Rust Meetup|叶天星《用Rust实现Git传输协议、Git对象解析和数据库存储》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场分享由达坦科技联合创始人兼CTO施继成进行,演讲主题是《Rust for Linux 6.2》。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1Bs4y117Ze/"},{key:6,image:ZH,title:"4.8 Beijing Rust Meetup|茌海《Monoio:一个基于 io-uring 的 Rust Runtime》",text:"2023年4月8日,达坦科技联合南京大学、CloudWeGo、华为等技术专家成功举办了题为Rust 💡X的meetup。本场分享由达坦科技联合创始人兼CTO施继成进行,演讲主题是《Rust for Linux 6.2》。",date:"2023.04.12",url:"https://www.bilibili.com/video/BV1Rh411M7EP/"},{key:10,image:rY,title:"如何用Rust写分布式系统",text:"分享会介绍分布式KV Store (Xline) 整体的组成,以及不同组件之间如何去交互。在广域网下的分布式系统如何高效地达成共识,以及分布式系统如何实现容错。",date:"2023.06.24",url:"https://www.bilibili.com/video/BV1Hs4y1r7dD/"},{key:11,image:nY,title:"Building microsecond-scale system with modern networking in Rust",text:"随着新型网络技术,如RDMA的普及,现代分布式应用的延迟降到了毫秒甚至微秒级别。这为构建系统软件带来了新的挑战。Rust的zero-cost抽象及内存管理能力能够为构建新型分布式应用带来新的机遇。我将分享利用Rust在用户态及内核态构建新型系统软件的相关经验,包括如何利用Rust抽象RDMA硬件的底层抽象及如何在内核构建一个毫秒级的容器启动机制。",date:"2023.06.24",url:"https://www.bilibili.com/video/BV1Zo4y1P7Sg/"},{key:12,image:iY,title:"30分钟体验Rust for Linux内核模块开发",text:"本主题会提供构建好的docker开发环境,在30分钟内演示如何使用r4l开发一个简易内核模块,并介绍目前r4l的发展现状。可以自备好电脑现场体验。",date:"2023.06.24",url:"https://www.bilibili.com/video/BV12j411U78o/"},{key:13,image:oY,title:"DatenLord 2023 Hackathon赛题宣讲会",text:"达坦科技基于其跨云分布式文件系统DatenLord项目,结合AI大模型时代背景,搭建了擂台,在此正式向您发出邀约!本次大赛主题为 Explore the Possibilities 赛题深刻有趣,奖品丰厚多样,借此机会您不仅可以尽情施展才华、与来自全国各地优秀的青年才俊们同台PK,更将有机会与优秀的评委教师对话交流。Clock is Ticking!无需犹豫,行动起来吧!",date:"2023.11.25",url:"https://www.bilibili.com/video/BV1su4y157iB/"},{key:14,image:sY,title:"DatenLord Hackathon2023空中路演",text:"DatenLord Hackathon 2023已经顺利完赛。达坦科技基于其跨云分布式文件系统DatenLord项目,结合AI大模型时代背景,搭建了擂台。我们邀请参赛者为DatenLord的极端场景设计并实现缓存 p2p 传输和同步模块。本次空中路演邀请了最终获得优胜奖的两支队伍进行思路分享,包括他们的解题思路,碰到的难点和挑战,以及如何应对的方法和设计亮点。欢迎感兴趣的大家进行观看,有问题也欢迎在评论区进行交流~~不要忘记一键三连哦~~",date:"2024.01.07",url:"https://www.bilibili.com/video/BV1ic411t7Nf/"}],lY="/zh-cn/assets/cover1-b9371555.jpg",cY="/zh-cn/assets/cover2-41a903e3.jpg",uY="/zh-cn/assets/cover2-41a903e3.jpg",dY="/zh-cn/assets/cover2-41a903e3.jpg",fY="/zh-cn/assets/cover2-41a903e3.jpg",hY="/zh-cn/assets/cover2-41a903e3.jpg",mY="/zh-cn/assets/cover2-41a903e3.jpg",pY="/zh-cn/assets/cover2-41a903e3.jpg",gY="/zh-cn/assets/cover2-41a903e3.jpg",vY="/zh-cn/assets/cover13-a69a12b0.jpg",yY="/zh-cn/assets/cover14-3a97e013.jpg",wY="/zh-cn/assets/cover14-3a97e013.jpg",_Y="/zh-cn/assets/cover14-3a97e013.jpg",xY="/zh-cn/assets/cover14-3a97e013.jpg",SY="/zh-cn/assets/cover14-3a97e013.jpg",bY="/zh-cn/assets/cover14-3a97e013.jpg",kY="/zh-cn/assets/cover20-c97bc11b.jpg",CY="/zh-cn/assets/cover21-9f52ba13.jpg",DY="/zh-cn/assets/cover22-187b655a.jpg",EY="/zh-cn/assets/cover23-1e515665.jpg",TY="/zh-cn/assets/cover24-020d0c34.jpg",jY="/zh-cn/assets/cover25-cb84d871.jpg",OY="/zh-cn/assets/cover26-7a726e97.jpg",PY="/zh-cn/assets/cover27-401eea81.jpg",RY="/zh-cn/assets/cover28-6ddc6bee.jpg",MY="/zh-cn/assets/cover29-0d2deb11.jpg",LY=[{key:1,image:lY,title:"Utilizing SpinalHDL for Large-scale Datapath Design",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的一个workshop:Utilizing SpinalHDL for Large-scale Datapath Design,由李天瑞进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1PM411m7DB/"},{key:2,image:cY,title:"A Network Attached Deep Learning Accelerator for FPGA Clusters",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的三个workshop:A Network Attached Deep Learning Accelerator for FPGA Clusters,由Philipp Kreowsky Justin Knapheide进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1HM411m7mS/"},{key:3,image:uY,title:"Coding a microprogrammed protocol receiver in SpinalHDL",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的五个workshop:Coding a microprogrammed protocol receiver in SpinalHDL,由Michael Meier进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1oK411z7VD/"},{key:4,image:dY,title:"Utilizing SpinalHDL to Accelerate Neuroscience",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的二个workshop:Utilizing SpinalHDL to Accelerate Neuroscience,由Jeff-Ciesielski进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1GG4y1J7gU/"},{key:5,image:fY,title:"SpinalHDL in Computer Architecture Research",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的四个workshop:SpinalHDL in Computer Architecture Research,由Sallar Ahmadi-Pour ( saahm)进行分享。",date:"2022.12.20",url:"https://www.bilibili.com/video/BV1gA411X7f8/"},{key:6,image:hY,title:"NaxRiscv: A Pipeline/Plugins/SpinalHDL/Scala mix",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的第六个workshop:NaxRiscv: A Pipeline/Plugins/SpinalHDL/Scala mix,由Dolu1990进行分享。",date:"2022.12.21",url:"https://www.bilibili.com/video/BV13K41167q5/"},{key:7,image:mY,title:"Recent progress on formal verification support on SpinalHDL",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的第七个workshop:Recent progress on formal verification support on SpinalHDL,由Xiao Yindong (Readon)进行分享。",date:"2022.12.21",url:"https://www.bilibili.com/video/BV1bG411N7fk/"},{key:8,image:pY,title:"SpinalHDL for ASIC",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的第八个workshop:SpinalHDL for ASIC,由Sebastien-riou进行分享。",date:"2022.12.21",url:"https://www.bilibili.com/video/BV16e4y1L7dV/"},{key:9,image:gY,title:"From Peripheral Plugins to Product documentation",text:"为了让对开源硬件感兴趣的朋友进一步了解SpinalHDL,达坦科技联合SpinalHDL社区举办一场题为《SpinalHDL应用前景探索》的线上研讨会(Webinar)。本研讨会分三个讨论分主题,分别为:数据通路加速(Datapath/Accelerations)、复杂系统设计案例(Design)、硬件设计流程(Flow)。这是本场研讨会的第九个workshop:From Peripheral Plugins to Product documentation,由Andreas Wallner进行分享。",date:"2022.12.21",url:"https://www.bilibili.com/video/BV12v4y1Q7cg/"},{key:13,image:vY,title:"Coroutines Applied to a Tilelink Interconnect Elaboration",text:"SpinalHDL始于2014年,最初是作为VHDL/Verilog的替代而做的创新尝试,伴随着数年来开源硬件设计的蓬勃发展,基于开源技术的硬件设计方法和范式逐渐受到业界的关注。达坦科技联合了SpinalHDL社区,以及四川芯测电子技术有限公司举办了一场题为SpinalHDL的使用和开发经验研讨会,旨在和大家分享SpinalHDL最新的实践、挑战和经验的分享。本视频为Workshop的第一部分,由Charles Popen进行分享。",date:"2023.07.08",url:"https://www.bilibili.com/video/BV1Vz4y1J7ck/"},{key:14,image:yY,title:"RISC-V敏捷硬件开发-软件定义芯片",text:"2023年8月23日至25日, 2023 RISC-V中国峰会在北京香格里拉饭店举办。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技在线上举办了第二届硬件敏捷开发与验证方法学研讨会。本次研讨会邀请了业界多位专家分享他们在各自领域的硬件敏捷开发与验证实践经验,为业界提供一次深入探讨和交流的机会,促进硬件敏捷开发与验证方法学的发展与落地。这是本场研讨会的第一个分享《RISC-V敏捷硬件开发-软件定义芯片》。",date:"2023.08.25",url:"https://www.bilibili.com/video/BV1Qh4y1K7pH/"},{key:15,image:wY,title:"香山处理器与敏捷开发工具链的最新进展",text:"2023年8月23日至25日, 2023 RISC-V中国峰会在北京香格里拉饭店举办。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技在线上举办了第二届硬件敏捷开发与验证方法学研讨会。本次研讨会邀请了业界多位专家分享他们在各自领域的硬件敏捷开发与验证实践经验,为业界提供一次深入探讨和交流的机会,促进硬件敏捷开发与验证方法学的发展与落地。这是本场研讨会的第二个分享《香山处理器与敏捷开发工具链的最新进展》。",date:"2023.08.25",url:"https://www.bilibili.com/video/BV1Dz4y1T7V6/"},{key:16,image:_Y,title:"数据流式编程在硬件设计中的应用",text:"2023年8月23日至25日, 2023 RISC-V中国峰会在北京香格里拉饭店举办。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技在线上举办了第二届硬件敏捷开发与验证方法学研讨会。本次研讨会邀请了业界多位专家分享他们在各自领域的硬件敏捷开发与验证实践经验,为业界提供一次深入探讨和交流的机会,促进硬件敏捷开发与验证方法学的发展与落地。这是本场研讨会的第三个分享《数据流式编程在硬件设计中的应用》。",date:"2023.08.25",url:"https://www.bilibili.com/video/BV12N411B7TN/"},{key:17,image:xY,title:"EDA创新推动敏捷芯片设计",text:"2023年8月23日至25日, 2023 RISC-V中国峰会在北京香格里拉饭店举办。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技在线上举办了第二届硬件敏捷开发与验证方法学研讨会。本次研讨会邀请了业界多位专家分享他们在各自领域的硬件敏捷开发与验证实践经验,为业界提供一次深入探讨和交流的机会,促进硬件敏捷开发与验证方法学的发展与落地。这是本场研讨会的第四个分享《EDA创新推动敏捷芯片设计》。",date:"2023.08.25",url:"https://www.bilibili.com/video/BV1Tz4y1M7vt/"},{key:18,image:SY,title:"Automated CPU design with AI",text:"2023年8月23日至25日, 2023 RISC-V中国峰会在北京香格里拉饭店举办。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技在线上举办了第二届硬件敏捷开发与验证方法学研讨会。本次研讨会邀请了业界多位专家分享他们在各自领域的硬件敏捷开发与验证实践经验,为业界提供一次深入探讨和交流的机会,促进硬件敏捷开发与验证方法学的发展与落地。这是本场研讨会的第五个分享《Automated CPU design with AI》。",date:"2023.08.25",url:"https://www.bilibili.com/video/BV13w411Q7zi/"},{key:19,image:bY,title:"MetaHVL硬件敏捷验证与协同仿真",text:"2023年8月23日至25日, 2023 RISC-V中国峰会在北京香格里拉饭店举办。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技在线上举办了第二届硬件敏捷开发与验证方法学研讨会。本次研讨会邀请了业界多位专家分享他们在各自领域的硬件敏捷开发与验证实践经验,为业界提供一次深入探讨和交流的机会,促进硬件敏捷开发与验证方法学的发展与落地。这是本场研讨会的第六个分享《MetaHVL硬件敏捷验证与协同仿》。",date:"2023.08.26",url:"https://www.bilibili.com/video/BV1DN4y197Pm/"},{key:20,image:kY,title:"计算机体系结构MIT课程学习社区经验分享",text:"在2023年初,达坦科技发起成立硬件设计学习社区,邀请所有有志于从事数字芯片设计的同学加入我们的学习互助自学小组,以理解数字芯片设计的精髓,强化理论知识的同时提升实操技能,继而整体提升设计能力。本场分享主题为【计算机体系结构MIT课程学习社区经验分享】,旨在了解学习社区各位同学学习的状态和面临的挑战,邀请已完成课程的学员分享学习和动手操作LAB的经验和教训,以此更好地辅助大家完成课程。",date:"2023.07.08",url:"https://www.bilibili.com/video/BV1cs4y1r7T3/"},{key:21,image:CY,title:"计算机体系结构 l MIT课程学习新手上路宣讲",text:"达坦科技在2023年始,发起成立计算机体系结构- MIT课程学习社区,号召感兴趣的工程师和同学系统地学习计算机体系结构相关知识,并且通过动手项目来验证学习的成果。为此,达坦科技软硬件联合开发工程师米明恒在2023年9月23日(周六)上午10:30为大家带来了一场计算机体系结构 l MIT课程学习新手上路宣讲。",date:"2023.09.24",url:"https://www.bilibili.com/video/BV1u8411i7Qw/"},{key:22,image:DY,title:"Stream Transaction Extender设计与验证",text:"达坦科技联合了SpinalHDL社区,以及四川芯测电子技术有限公司举办了一场题为SpinalHDL的使用和开发经验研讨会,旨在和大家分享SpinalHDL最新的实践、挑战和经验的分享。本视频为Workshop的第二部分,由电子科技大学副教授肖寅东(Readon)进行分享。",date:"2023.07.08",url:"https://www.bilibili.com/video/BV1pM4y1j7Lm/"},{key:23,image:EY,title:"面向Multi-Die FPGA的设计与部署自动化方法探索",text:"达坦科技联合了SpinalHDL社区,以及四川芯测电子技术有限公司举办了一场题为SpinalHDL的使用和开发经验研讨会,旨在和大家分享SpinalHDL最新的实践、挑战和经验的分享。本视频为Workshop的第三部分,由西安交通大学副教授邸志雄进行分享。",date:"2023.07.08",url:"https://www.bilibili.com/video/BV1og4y1c7RS/"},{key:24,image:TY,title:"Get Started with SpinalHDL with a Simplified Setup",text:"在2023年12月10日,达坦科技联合SpinalHDL社区及该语言的创建者 Charles Papon 举办了 《2023 SpinalHDL应用前景探索》的线上研讨会,这是研讨会第一个视频,Get Started with SpinalHDL with a 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Users”。",date:"2023.12.17",url:"https://www.bilibili.com/video/BV1Mw41147aS/"},{key:28,image:RY,title:"Pcie Brief Introduction",text:"在2023年12月10日,达坦科技联合SpinalHDL社区及该语言的创建者 Charles Papon 举办 了《2023 SpinalHDL应用前景探索》的线上研讨会,分为两个Track。这是第五个视频,由Chenbo带来“Pcie Brief Introduction”。",date:"2023.12.17",url:"https://www.bilibili.com/video/BV1Mw41147aS/"},{key:29,image:MY,title:"The J1Sc Family",text:"在2023年12月10日,达坦科技联合SpinalHDL社区及该语言的创建者 Charles Papon 举办 了《2023 SpinalHDL应用前景探索》的线上研讨会,分为两个Track。这是第六个视频,由Christopher Lozinsk带来“The J1Sc Family”。",date:"2023.12.17",url:"https://www.bilibili.com/video/BV1Jc411o7A6/"}],{Heading:AY,Paragraph:IY}=Me,{CNHead4:NY,CNTitleLarge:$Y}=AY,{CNMarkSmall:zY,CNBodySmall:HY}=IY,mc=new Map([["tech-talk",{label:"前沿科技分享",description:"探索前沿技术,拥抱创新与改变",list:VH,recommend:27}],["oss-showcase",{label:"开源产品分享",description:"软硬件融合创新实践的观察与输出",list:BH,recommend:2}],["rust-showcase",{label:"Rust语言应用及案例分享",description:"Rust编程语言的应用、实践与探索",list:aY,recommend:12}],["hardware-acceleration",{label:"硬件加速",description:"硬件加速领域的实践、经验与挑战",list:LY,recommend:21}]]),YY=f.main``,VY=f.div`
max-width: 1440px;
margin-inline: auto;
padding: 1rem 1.76rem 1.68rem;
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`,Th=f(NY)`
padding-bottom: 0.48rem;
text-align: center;
-`,VY=f.div`
+`,FY=f.div`
display: grid;
grid-template-rows: repeat(2, 1fr);
grid-template-columns: repeat(2, 1fr);
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height: 0.215rem;
`,wc=f(HY)`
color: #667085;
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//! version : 2.29.4
//! authors : Tim Wood, Iskren Chernev, Moment.js contributors
//! license : MIT
@@ -2100,8 +2100,8 @@ Error generating stack: `+o.message+`
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发起 CRC 计算时原始数据需要按照大端字节序进行传输,即高位字节需要优先传输。假设 CRC 电路输入 AXI-Stream 总线数据位宽为 32-bit (4-byte), 若要传输 80-bit (10-byte)的数据,那么每一帧需要传输的内容如下图所示:
- +blue-crc 项目基于 Bluespec SystemVerilog 硬件描述语言实现,因此对于使用 BSV 的设计者,可以直接通过实例化的方式使用 CRC 模块。详细的使用步骤如下:
[1] Y. Sun and M. S. Kim, "A Table-Based Algorithm for Pipelined CRC Calculation," 2010 IEEE International Conference on Communications, Cape Town, South Africa, 2010, pp. 1-5, doi: 10.1109/ICC.2010.5501903.
-[2] Sun Y, Kim M S. A pipelined CRC calculation using lookup tables[C]//2010 7th IEEE Consumer Communications and Networking Conference. IEEE, 2010: 1-2.
`;export{f as assetURLs,w as default,y as metadata,x as toc}; +[2] Sun Y, Kim M S. A pipelined CRC calculation using lookup tables[C]//2010 7th IEEE Consumer Communications and Networking Conference. IEEE, 2010: 1-2.
`;export{y as assetURLs,F as default,E as metadata,x as toc}; diff --git a/zh-cn/assets/index-696ef44a.js b/zh-cn/assets/index-a154d453.js similarity index 98% rename from zh-cn/assets/index-696ef44a.js rename to zh-cn/assets/index-a154d453.js index cc57ed1..0e9d7ef 100644 --- a/zh-cn/assets/index-696ef44a.js +++ b/zh-cn/assets/index-a154d453.js @@ -1,4 +1,4 @@ -const t="/zh-cn/assets/cover-cf0f8eeb.png",e=[t],a={label:"第二届硬件敏捷开发与方法学研讨会 l 2023 RISC-V中国峰会同期活动顺利举办",description:"作为2023RISC-V中国峰会的同期活动,8月25日下午,达坦科技成功在线上举办第二届硬件敏捷开发与验证方法学研讨。长达三小时的就新一代HDL在数字芯片设计开发和验证效率方面的实践经验分享,究竟碰撞出了什么新的火花呢?下面我们一起来回顾研讨会的精彩内容。",cover:"./cover.png",location:"中国香港",date:"2023-09-07",title:"The 2nd Hardware Agile Development and Methodology Workshop l 2023 RISC V China Summit Concurrent Events Successfully Held"},l=[{label:"Part.1",level:2},{label:"Part.2",level:2},{label:"Part.3",level:2},{label:"Part.4",level:2},{label:"Part.5",level:2},{label:"Part.6",level:2},{label:"结束语",level:2}],r=` +const t="/zh-cn/assets/cover-cf0f8eeb.png",e=[t],a={label:"第二届硬件敏捷开发与方法学研讨会 l 2023 RISC-V中国峰会同期活动顺利举办",description:"作为2023RISC-V中国峰会的同期活动,8月25日下午,达坦科技成功在线上举办第二届硬件敏捷开发与验证方法学研讨。长达三小时的就新一代HDL在数字芯片设计开发和验证效率方面的实践经验分享,究竟碰撞出了什么新的火花呢?下面我们一起来回顾研讨会的精彩内容。",cover:"./cover.png",location:"中国香港",date:"2023-09-07",title:"The 2nd Hardware Agile Development and Methodology Workshop l 2023 RISC V China Summit Concurrent Events Successfully Held"},l=[{label:"Part.1",level:2},{label:"Part.2",level:2},{label:"Part.3",level:2},{label:"Part.4",level:2},{label:"Part.5",level:2},{label:"Part.6",level:2},{label:"结束语",level:2}],p=`作为2023RISC-V中国峰会的同期活动,8月25日下午,达坦科技成功在线上举办第二届硬件敏捷开发与验证方法学研讨会。长达三小时的就新一代HDL在数字芯片设计开发和验证效率方面的实践经验分享,究竟碰撞出了什么新的火花呢?下面我们一起来回顾研讨会的精彩内容。
《RISC-V敏捷硬件开发-软件定义芯片》
@@ -19,4 +19,4 @@ const t="/zh-cn/assets/cover-cf0f8eeb.png",e=[t],a={label:"第二届硬件敏捷《MetaHVL硬件敏捷验证与协同仿真》
华南理工大学计算机学院副教授赖晓铮的分享主题是《MetaHVL硬件敏捷验证与协同仿真》。赖老师从芯片设计的规模和芯片设计的成本是不成比例(规模是线性提升,成本是指数提升)的现状出发,提出硬件设计的流程有更敏捷的需求。而敏捷是包含设计和验证两个维度的全流程敏捷。他分享了运用创新EDA方法学和工具以进一步分离设计与实现;此外,提高设计抽象层次的同时,也需要提高验证的抽象层次。赖老师介绍了他在Meta-HVL项目研究的中期结论,即小规模设计的加速比明显,规模越大,DUT运行时间占比越大,则验证加速起到的作用越小。因此,时间应该花在提高验证的效率上,而不是把时间和资源花在加速验证代码的运行上。
如何提升数字芯片的开发和验证效率一直是业界关注的焦点。新一代HDL打开了全新的数字芯片敏捷设计和验证的方法学大门。在本次研讨会上,业界和学界的各位专家分享了他们在各自领域的硬件敏捷开发与验证实践经验,希望这些前沿的探索可以为关注该领域的学习者和实践者提供一次深入探讨和交流的机会,以此进一步促进硬件敏捷开发与验证方法学的发展与落地。
`;export{e as assetURLs,r as default,a as metadata,l as toc}; +如何提升数字芯片的开发和验证效率一直是业界关注的焦点。新一代HDL打开了全新的数字芯片敏捷设计和验证的方法学大门。在本次研讨会上,业界和学界的各位专家分享了他们在各自领域的硬件敏捷开发与验证实践经验,希望这些前沿的探索可以为关注该领域的学习者和实践者提供一次深入探讨和交流的机会,以此进一步促进硬件敏捷开发与验证方法学的发展与落地。
`;export{e as assetURLs,p as default,a as metadata,l as toc}; diff --git a/zh-cn/assets/index-b28c82c1.js b/zh-cn/assets/index-a2ebb372.js similarity index 97% rename from zh-cn/assets/index-b28c82c1.js rename to zh-cn/assets/index-a2ebb372.js index 0941791..6d99e97 100644 --- a/zh-cn/assets/index-b28c82c1.js +++ b/zh-cn/assets/index-a2ebb372.js @@ -1,4 +1,4 @@ -const e="/zh-cn/assets/cover-c17c52cc.png",s="/zh-cn/assets/image1-0dff4570.png",c="/zh-cn/assets/image2-e09cfdc8.png",o="/zh-cn/assets/image3-2b589463.png",a="/zh-cn/assets/image4-5841c9d6.png",p="/zh-cn/assets/image5-92344f1d.png",d="/zh-cn/assets/image6-b429f851.png",r="/zh-cn/assets/image7-97920b5a.png",i="/zh-cn/assets/image8-ecf5c6f3.png",t="/zh-cn/assets/image9-f47bad66.png",n="/zh-cn/assets/image10-b50adc27.png",l="/zh-cn/assets/image11-99ec2a51.png",m=[e,s,c,o,a,p,d,r,i,t,n,l],h={label:"从数学角度思考程序与验证正确性",description:"本文旨在为没有接触过形式化方法的读者提供一种新的视角看待计算机系统与算法,而非形式化方法或 TLA+ 教程。因此本文的重点是如何从数学角度思考程序,不会使用大篇幅讲解 TLA+ 的语法。",cover:"./cover.png",location:"中国香港",author:["田野"],tags:["Xline"],date:"2023-03-02",title:"Thinking about programs mathematically and verifying correctness"},g=[{label:"我们该如何写出正确的程序?",level:2},{label:"程序中会有什么样错误?",level:3},{label:"经验",level:3},{label:"形式化方法",level:3},{label:"TLA+",level:2},{label:"简单的例子",level:3},{label:"Two-Phase Commit",level:2},{label:"总结",level:2},{label:"我们的项目:Xline",level:2}],A=` +const e="/zh-cn/assets/cover-c17c52cc.png",s="/zh-cn/assets/image1-0dff4570.png",c="/zh-cn/assets/image2-e09cfdc8.png",o="/zh-cn/assets/image3-2b589463.png",p="/zh-cn/assets/image4-5841c9d6.png",a="/zh-cn/assets/image5-92344f1d.png",d="/zh-cn/assets/image6-b429f851.png",i="/zh-cn/assets/image7-97920b5a.png",r="/zh-cn/assets/image8-ecf5c6f3.png",t="/zh-cn/assets/image9-f47bad66.png",n="/zh-cn/assets/image10-b50adc27.png",l="/zh-cn/assets/image11-99ec2a51.png",m=[e,s,c,o,p,a,d,i,r,t,n,l],g={label:"从数学角度思考程序与验证正确性",description:"本文旨在为没有接触过形式化方法的读者提供一种新的视角看待计算机系统与算法,而非形式化方法或 TLA+ 教程。因此本文的重点是如何从数学角度思考程序,不会使用大篇幅讲解 TLA+ 的语法。",cover:"./cover.png",location:"中国香港",author:["田野"],tags:["Xline"],date:"2023-03-02",title:"Thinking about programs mathematically and verifying correctness"},h=[{label:"我们该如何写出正确的程序?",level:2},{label:"程序中会有什么样错误?",level:3},{label:"经验",level:3},{label:"形式化方法",level:3},{label:"TLA+",level:2},{label:"简单的例子",level:3},{label:"Two-Phase Commit",level:2},{label:"总结",level:2},{label:"我们的项目:Xline",level:2}],T=`本文旨在为没有接触过形式化方法的读者提供一种新的视角看待计算机系统与算法,而非形式化方法或 TLA+ 教程。因此本文的重点是如何从数学角度思考程序,不会使用大篇幅讲解 TLA+ 的语法。
程序设计的目标永远是写出正确的程序。随着时间的推移,我们的程序越来越复杂,其中可能存在的错误也越来越多。想要写出正确的程序,首先应该了解程序中可能出现的错误有哪些。
@@ -67,7 +67,7 @@ const e="/zh-cn/assets/cover-c17c52cc.png",s="/zh-cn/assets/image1-0dff4570.png"在其中用到了"或"连接两个状态,我们可以用布尔逻辑中的逻辑或 ∨
来表示。这样,我们就可以清晰地表示出程序的状态转换关系了。为了美观,在 TLA+ 中,首句前也可以补上相同的布尔逻辑符号:
我们最终得到了这个简单程序在初始状态后的两个状态,下面我们将初始状态补全,并按照 TLA+ 语言的要求补全整个 specification:
- +二阶段提交(英语:Two-phase Commit)是指在计算机网络以及数据库领域内,为了使基于分布式系统架构下的所有节点在进行事务提交时保持一致性而设计的一种算法。通常,二阶段提交也被称为是一种协议(Protocol)。在分布式系统中,每个节点虽然可以知晓自己的操作时成功或者失败,却无法知道其他节点的操作的成功或失败。当一个事务跨越多个节点时,为了保持事务的 ACID 特性,需要引入一个作为协调者的组件来统一掌控所有节点(称作参与者)的操作结果并最终指示这些节点是否要把操作结果进行真正的提交(比如将更新后的数据写入磁盘等等)。因此,二阶段提交的算法思路可以概括为:参与者将操作成败通知协调者,再由协调者根据所有参与者的反馈情报决定各参与者是否要提交操作还是中止操作。—— Two-Phase Commit (Wikipedia)
在 Leslie Lamport's The TLA+ Video Course 中,Lamport 以这样的方式类比解释 Two-Phase Commit:
- +在婚礼上,牧师是协调者,新郎和新娘是参与者。当新郎和新娘都同意婚事时,牧师才会正式宣布婚事。如果有一方不同意,牧师就会中止婚事:
msgs
作为消息池,用于记录所有正在传输的消息,初始值是一个空集。下面我们来定义系统做可能发生的动作。
- +[type → "prepare", rm → r]
是一个 TLA+ 中的 record,类似于其它编程语言中的 struct。UNCHANGED ⟨rmState, tmState, msgs⟩
表示这个动作不会改变 rmState
、tmState
、msgs
这三个变量的值。在 TLA+ 中,每一个变量的值是否改变都需要显式地声明。当 TM
的状态为 init
,且在消息池中存在来自 r
的 Prepared
消息,tmPrepared
在下一个状态的值会是 tmPrepared
和 {r}
的并集。
上面的两个动作分别是 Transaction Manager 进行 Commit 与 Abort。
上述 4 个 Resource Manager 动作分别是 Resource Manager 选择 Prepare 与 Abort,以及处理由 Transaction Manager 决定的 Commit 与 Abort。
@@ -149,4 +149,4 @@ Next 用于定义状态转换关系。TLA+被广泛用于分布式系统算法的研究和开发中。在我们的项目 Xline 中,TLA+被用来在设计阶段验证共识算法的正确性。
Xline 是一个用于元数据管理的分布式 KV 存储。我们在 Xline 中使用 CURP 协议(https://www.usenix.org/system/files/nsdi19-park.pdf)的修改版作为共识协议,TLA+将被用于其正确性验证中。
-如果你想了解更多关于 Xline 的信息,请参考我们的 Github:https://github.com/datenlord/Xline
`;export{m as assetURLs,A as default,h as metadata,g as toc}; +如果你想了解更多关于 Xline 的信息,请参考我们的 Github:https://github.com/datenlord/Xline
`;export{m as assetURLs,T as default,g as metadata,h as toc}; diff --git a/zh-cn/assets/index-38c14a45.js b/zh-cn/assets/index-a325ad17.js similarity index 99% rename from zh-cn/assets/index-38c14a45.js rename to zh-cn/assets/index-a325ad17.js index 752b35f..2cf7596 100644 --- a/zh-cn/assets/index-38c14a45.js +++ b/zh-cn/assets/index-a325ad17.js @@ -1,4 +1,4 @@ -const e="/zh-cn/assets/cover-1329fc54.png",l="/zh-cn/assets/image1-03c3323d.png",i="/zh-cn/assets/image2-19f32eff.png",s="/zh-cn/assets/image3-7a5e2db9.png",a="/zh-cn/assets/image4-a055bd84.png",t="/zh-cn/assets/image5-b8622f96.png",p="/zh-cn/assets/image6-5093ee75.png",n="/zh-cn/assets/image7-9fa09d91.png",o="/zh-cn/assets/image8-84dd6aec.png",c="/zh-cn/assets/image9-2f762488.png",r="/zh-cn/assets/image10-f2b55246.png",h="/zh-cn/assets/image11-c5d501bb.png",d="/zh-cn/assets/image12-56434254.png",m="/zh-cn/assets/image13-1c12a6c5.png",u="/zh-cn/assets/image14-69943dbe.png",b="/zh-cn/assets/image15-45a7b638.png",g="/zh-cn/assets/image16-5b765721.jpg",f="/zh-cn/assets/image17-8fb19d7c.jpg",R="/zh-cn/assets/image18-c8c4d5a1.jpg",y="/zh-cn/assets/image19-fb1e5167.png",S="/zh-cn/assets/image20-a391e7d8.jpg",_=[e,l,i,s,a,t,p,n,o,c,r,h,d,m,u,b,g,f,R,y,S],v={label:"计算机体系结构|MIT6.175和MIT6.375学习笔记",description:"在2023年初,达坦科技发起成立硬件设计学习社区,邀请所有有志于从事数字芯片设计的同学加入我们的学习互助自学小组,以理解数字芯片设计的精髓,强化理论知识的同时提升实操技能,继而整体提升设计能力。现在,完成第一期学习的同学整理了MIT6.175和MIT6.375的关键内容以及Lab实践的学习笔记。",cover:"./cover.png",location:"中国香港",author:["kazutoiris"],tags:["硬件加速"],date:"2023-05-17",title:"Computer Architecture|MIT6.175 and MIT6.375 Study Notes"},M=[{label:"MIT 6.175",level:2},{label:"环境搭建",level:3},{label:"四种 FIFO (Lab 4)",level:3},{label:"Ready 和 Valid 握手",level:3},{label:"EHR 寄存器 (Lab4)",level:3},{label:"RISC-V (Lab5)",level:3},{label:"Branch Prediction (Lab6)",level:3},{label:"DDR3 Memory (Lab7)",level:3},{label:"Cache Coherence (Project)",level:3},{label:"MIT 6.375",level:2},{label:"Bluespec 中的一些特性",level:3},{label:"CORDIC 算法",level:3},{label:"一些常用的概念",level:2},{label:"Setup Time 、Hold Time 和 Clock-to-Q Time",level:3},{label:"SRAM",level:3},{label:"DRAM",level:3},{label:"References",level:2}],C=` +const e="/zh-cn/assets/cover-1329fc54.png",l="/zh-cn/assets/image1-03c3323d.png",s="/zh-cn/assets/image2-19f32eff.png",i="/zh-cn/assets/image3-7a5e2db9.png",a="/zh-cn/assets/image4-a055bd84.png",t="/zh-cn/assets/image5-b8622f96.png",p="/zh-cn/assets/image6-5093ee75.png",n="/zh-cn/assets/image7-9fa09d91.png",o="/zh-cn/assets/image8-84dd6aec.png",c="/zh-cn/assets/image9-2f762488.png",r="/zh-cn/assets/image10-f2b55246.png",d="/zh-cn/assets/image11-c5d501bb.png",h="/zh-cn/assets/image12-56434254.png",m="/zh-cn/assets/image13-1c12a6c5.png",u="/zh-cn/assets/image14-69943dbe.png",b="/zh-cn/assets/image15-45a7b638.png",g="/zh-cn/assets/image16-5b765721.jpg",f="/zh-cn/assets/image17-8fb19d7c.jpg",R="/zh-cn/assets/image18-c8c4d5a1.jpg",y="/zh-cn/assets/image19-fb1e5167.png",S="/zh-cn/assets/image20-a391e7d8.jpg",_=[e,l,s,i,a,t,p,n,o,c,r,d,h,m,u,b,g,f,R,y,S],v={label:"计算机体系结构|MIT6.175和MIT6.375学习笔记",description:"在2023年初,达坦科技发起成立硬件设计学习社区,邀请所有有志于从事数字芯片设计的同学加入我们的学习互助自学小组,以理解数字芯片设计的精髓,强化理论知识的同时提升实操技能,继而整体提升设计能力。现在,完成第一期学习的同学整理了MIT6.175和MIT6.375的关键内容以及Lab实践的学习笔记。",cover:"./cover.png",location:"中国香港",author:["kazutoiris"],tags:["硬件加速"],date:"2023-05-17",title:"Computer Architecture|MIT6.175 and MIT6.375 Study Notes"},M=[{label:"MIT 6.175",level:2},{label:"环境搭建",level:3},{label:"四种 FIFO (Lab 4)",level:3},{label:"Ready 和 Valid 握手",level:3},{label:"EHR 寄存器 (Lab4)",level:3},{label:"RISC-V (Lab5)",level:3},{label:"Branch Prediction (Lab6)",level:3},{label:"DDR3 Memory (Lab7)",level:3},{label:"Cache Coherence (Project)",level:3},{label:"MIT 6.375",level:2},{label:"Bluespec 中的一些特性",level:3},{label:"CORDIC 算法",level:3},{label:"一些常用的概念",level:2},{label:"Setup Time 、Hold Time 和 Clock-to-Q Time",level:3},{label:"SRAM",level:3},{label:"DRAM",level:3},{label:"References",level:2}],C=`在 2023 年初,达坦科技发起成立硬件设计学习社区,邀请所有有志于从事数字芯片设计的同学加入我们的学习互助自学小组,以理解数字芯片设计的精髓,强化理论知识的同时提升实操技能,继而整体提升设计能力。现在,完成第一期学习的同学整理了 MIT6.175 和 MIT6.375 的关键内容以及 Lab 实践的学习笔记。
6.175 和 6.375 的课程和 Lab 学习都有一定的难度,要求采用 Bluespec 语言实现 RISC-V 处理器,并支持多级流水、分支预测、缓存、异常处理、缓存一致性等功能。此外,Lab 环节还涉及软硬件联合开发,要求基于所实现的 RISC-V 处理器运行真实的 RISC-V 程序,并给出性能评估。希望第一期学员(GitHub:kazutoiris )的学习笔记对想从事数字芯片设计的工程师有所帮助。
因为 Valid 快于 Ready,所以当 Ready 由有效变为无效时,线路上多发了一拍数据。这一拍数据就要新增一个 buffer 去进行缓存。
因为第一拍数据送入之前为满,而之后都是处于空的状态,所以可以当成 Depth-1 Bypass FIFO ,在空时可同时进行 deq 和 enq 操作。
(这里可以考虑一下传给 master 的 Ready 信号。如果 buffer 为空,那么必然是 Ready 的;如果 buffer 为满,那么必然不是 Ready 的。这样就可以省掉一个寄存器去为 slave 的 Ready 打一拍。)
@@ -92,7 +92,7 @@ case class Delay2() extends CReady 从有效变为无效的时候,Ready 到达晚一拍,Valid 有一拍有效数据已经送出去了。等 Ready 到达 master,已经多送出了两拍有效数据。所以这两拍数据必须被缓存起来
在数据传输刚开始的时候,第一拍数据是从 FIFO 中直出的。第二拍的时候,slave 的 Ready 送至 master。在之后的数据传输过程中,其中停滞的只有一个数据。
显而易见,可以使用 Depth-2 Conflict-Free FIFO,在非满非空的时候可以同时 deq 和 enq。master 的 Ready 信号就是 notFull,slave 的 Valid 信号就是 notEmpty。可见,所有输出均为寄存器输出。
@@ -223,12 +223,12 @@ case class Delay3() extends CMESI 协议将“Exclusive”状态添加到 MSI 状态机中,可以减少只在单个缓存中存在的缓存行的回写次数。
MOSI 协议将“Owner”状态添加到 MSI,可以减少由从其他处理器读取而触发的写回操作。
在上一篇源码解读的文章(
Xline 源码解读(三) —— CURP Server 的实现
)中,我们简单阐述了 Xline 的 Curp Server 是如何实现的。接下来,就让我们话接上回,继续深入地来了解 Curp Server 中的一些核心的数据结构,特别是 conflict_checked_channel 和 command worker,它们相互协作,共同推动着 CURP Server 内部状态机状态转换。
@@ -25,12 +25,12 @@ const e="/zh-cn/assets/e4031380f79f643b21d6bdfd37c46a1c-95e167c8.jpeg",s="/zh-cn针对第一个问题,我们可以将所有的命令都看成是一张有向无环图中的顶点,而将冲突关系视为图中顶点之间的有向边。假设命令 A 和命令 B 之间存在冲突(命令的抵达顺序为先 A 后 B),我们便可将冲突关系看成是 A 和 B 之间的一条弧<A, B>,其中弧头总是指向后进来的顶点(这一顺序性就保证了图中不会出现环形冲突)。
一旦我们将冲突关系定义为一个有向无环的非连通图中的一条边,那么执行某个命令时所需要计算的冲突顺序问题,就转换成了一个求有向无环图中,该命令所在的连通分量的拓扑排序问题。针对每个命令,successors(也就是后继) 保存了哪些 cmd 与当前 cmd 冲突,successors 的长度就是该 顶点的出度。而 predecessor_cnt (前驱数)则代表了这个 cmd 与之前的多少个 cmd 存在冲突,也就是该顶点元素的入度。
同样回到我们前面所提到的 A、B、C 的例子当中,当我们使用 DAG 来描述命令的冲突关系,其情况如下图所示。
- +当 cmd_worker 从 channel 当中接收命令时,channel 只需要遍历这个有向无环图中的每一个连通分量,并找到第一个入度为 0 的顶点即可。只有当 command 执行完毕后,channel 才会更新 B 的 predecessor_cnt,以解决 A 与 B 之间的冲突关系。
正如我们在文章开头所说的那样,冲突检测队列和 command worker 共同组成了 Curp Server 的状态机引擎。冲突检测队列向 command worker 提供无冲突的命令,而 command worker 则负责执行这些命令,并根据结果推动更新冲突检测队列当中的冲突关系。
从结构上来看,Curp Server 状态机引擎是由三对 channel 和一个 filter 构成,其中这三对 channel 分别为:(send_tx,filter_rx)、(filter_tx, recv_rx) 以及 (done_tx, done_rx)具体的结构可以参考下图。
- +其数据流方向为:send_tx -> filter_rx -> filter -> filter_tx -> recv_rx -> done_tx -> done_rx
其中,send_tx 为 RawCurp 对象所拥有,负责在 propose(对应了 curp 的 fast path)、以及应用日志 apply(对应了 curp 的 slow path) 时向冲突检测队列投递对应的 CEEvent。冲突检测队列则会在计算出冲突顺序后,将 CEEvent 转换成为 Task 并通过 (filter_tx, recv_rx) 投递到 command worker 当中执行。command worker 在执行完 Task 后将结果通过 (done_tx, done_rx) 反馈到冲突检测队列中,并更新队列中依赖图中的顶点信息。
在 2023 年初,达坦科技发起成立硬件设计学习社区,邀请所有有志于从事数字芯片设计的同学加入我们的学习互助自学小组,以理解数字芯片设计的精髓,强化理论知识的同时提升实操技能,继而整体提升设计能力。6.175 和 6.375 的课程和 Lab 学习都有一定的难度,要求采用 Bluespec 语言实现 RISC-V 处理器,并支持多级流水、分支预测、缓存、异常处理、缓存一致性等功能。此外,Lab 环节还涉及软硬件联合开发,要求基于所实现的 RISC-V 处理器运行真实的 RISC-V 程序,并给出性能评估。
继 MIT6.175 和 MIT6.375 学习笔记之后,我们又整理了到目前为止,硬件设计学习社区里大家碰到的一些共同问题,希望我们的回复以及学习贴士对于想啃下这两门高难度课程,并想从事数字芯片设计的工程师或同学有所帮助。
计算机体系结构| MIT6.175 和 MIT6.375 学习笔记
达坦科技硬件设计学习社区持续开放,若想询问加入细节,请添加下方小助手微信号或邮件info@datenlord.com
-`;export{t as assetURLs,n as default,r as metadata,i as toc}; +`;export{t as assetURLs,i as default,r as metadata,c as toc}; diff --git a/zh-cn/assets/index-71801d47.js b/zh-cn/assets/index-c429f64c.js similarity index 93% rename from zh-cn/assets/index-71801d47.js rename to zh-cn/assets/index-c429f64c.js index 1fe4386..ae0ce58 100644 --- a/zh-cn/assets/index-71801d47.js +++ b/zh-cn/assets/index-c429f64c.js @@ -1,4 +1,4 @@ -const t="/zh-cn/assets/cover-cf0f8eeb.png",o="/zh-cn/assets/image1-6485c4dd.jpg",s=[t,o],e={label:"活动预告 | 第二届硬件敏捷开发与验证方法学研讨会",description:"2023年8月23日至25日, 2023 RISC-V中国峰会将在北京香格里拉饭店举办。本届峰会采用“主会议+主题活动+展览展示+同期活动”的会议组织方式,将邀请RISC-V国际基金会、业界专家、企业代表及社区伙伴等共同探讨RISC-V发展趋势与机遇。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技将在线上举办第二届硬件敏捷开发与验证方法学研讨会。",cover:"./cover.png",location:"新加坡",date:"2023-08-20",title:"Upcoming Events l 2nd Hardware Agile Development and Verification Methodology Workshop"},n=[{label:"2023 RISC-V中国峰会",level:2},{label:"活动信息",level:2}],r=` +const t="/zh-cn/assets/cover-cf0f8eeb.png",o="/zh-cn/assets/image1-6485c4dd.jpg",e=[t,o],s={label:"活动预告 | 第二届硬件敏捷开发与验证方法学研讨会",description:"2023年8月23日至25日, 2023 RISC-V中国峰会将在北京香格里拉饭店举办。本届峰会采用“主会议+主题活动+展览展示+同期活动”的会议组织方式,将邀请RISC-V国际基金会、业界专家、企业代表及社区伙伴等共同探讨RISC-V发展趋势与机遇。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技将在线上举办第二届硬件敏捷开发与验证方法学研讨会。",cover:"./cover.png",location:"新加坡",date:"2023-08-20",title:"Upcoming Events l 2nd Hardware Agile Development and Verification Methodology Workshop"},r=[{label:"2023 RISC-V中国峰会",level:2},{label:"活动信息",level:2}],n=`2023年8月23日至25日, 2023 RISC-V中国峰会将在北京香格里拉饭店举办。本届峰会采用“主会议+主题活动+展览展示+同期活动”的会议组织方式,将邀请RISC-V国际基金会、业界专家、企业代表及社区伙伴等共同探讨RISC-V发展趋势与机遇。作为本届RISC-V中国峰会的同期活动,8月25日下午,达坦科技将在线上举办第二届硬件敏捷开发与验证方法学研讨会。
随着数字芯片的设计规模和复杂度越来越大,加之芯片市场的竞争越来越激烈,如何提升数字芯片的开发和验证效率成为业界关注的焦点。虽然各种设计工具、验证方法学层出不穷,但是一直没有得到业界广泛认可。目前业界普遍采用的还是基于Verilog、SystemVerilog、VHDL和UVM的工具和方法。
@@ -16,4 +16,4 @@ const t="/zh-cn/assets/cover-cf0f8eeb.png",o="/zh-cn/assets/image1-6485c4dd.jpg"收看链接:
https://wx.vzan.com/live/tvchat-904511107?v=1691984417574
或欢迎点击下方链接预约公众号直播。
感兴趣的观众可以添加海报中的达坦科技小助手二维码加入讨论群,添加时请注明硬件敏捷开发和验证方法学研讨。
`;export{s as assetURLs,r as default,e as metadata,n as toc}; +感兴趣的观众可以添加海报中的达坦科技小助手二维码加入讨论群,添加时请注明硬件敏捷开发和验证方法学研讨。
`;export{e as assetURLs,n as default,s as metadata,r as toc}; diff --git a/zh-cn/assets/index-38e8d7df.js b/zh-cn/assets/index-c8b4647e.js similarity index 88% rename from zh-cn/assets/index-38e8d7df.js rename to zh-cn/assets/index-c8b4647e.js index 1f4cf8f..597d7e9 100644 --- a/zh-cn/assets/index-38e8d7df.js +++ b/zh-cn/assets/index-c8b4647e.js @@ -1,6 +1,6 @@ -const t="/zh-cn/assets/cover-3674aa81.jpg",s="/zh-cn/assets/image1-b73fb0ee.jpg",e=[t,s],n={label:"Rust唠嗑室:Xline-跨数据中心一致性管理",description:"随着互联网和云计算的业务规模越来越大,单个数据中心已经无法满足业务的需求,业务系统从单数据中心向多数据中心发展,多地多中心多活部署的需求也越来越普遍。多数据中心架构最大的挑战是,如何保证数据跨数据中心访问的一致性和性能。比如索引、权限、配置等这类需要跨数据中心共享访问的元数据,如何在多中心竞争修改的场景下,仍然能保持一致性,并且保证访问性能。",cover:"./cover.jpg",location:"中国香港",tags:["Xline"],date:"2022-10-11",title:"Rust Chat Room: Xline Cross Data Center Consistency Management"},o=[{label:"内容简介",level:2}],a=` +const s="/zh-cn/assets/cover-3674aa81.jpg",t="/zh-cn/assets/image1-b73fb0ee.jpg",e=[s,t],n={label:"Rust唠嗑室:Xline-跨数据中心一致性管理",description:"随着互联网和云计算的业务规模越来越大,单个数据中心已经无法满足业务的需求,业务系统从单数据中心向多数据中心发展,多地多中心多活部署的需求也越来越普遍。多数据中心架构最大的挑战是,如何保证数据跨数据中心访问的一致性和性能。比如索引、权限、配置等这类需要跨数据中心共享访问的元数据,如何在多中心竞争修改的场景下,仍然能保持一致性,并且保证访问性能。",cover:"./cover.jpg",location:"中国香港",tags:["Xline"],date:"2022-10-11",title:"Rust Chat Room: Xline Cross Data Center Consistency Management"},o=[{label:"内容简介",level:2}],a=`随着互联网和云计算的业务规模越来越大,单个数据中心已经无法满足业务的需求,业务系统从单数据中心向多数据中心发展,多地多中心多活部署的需求也越来越普遍。多数据中心架构最大的挑战是,如何保证数据跨数据中心访问的一致性和性能。比如索引、权限、配置等这类需要跨数据中心共享访问的元数据,如何在多中心竞争修改的场景下,仍然能保持一致性,并且保证访问性能。
传统单数据中心解决方案无法满足跨数据中心的场景对性能和一致性的需求。DatenLord 推出开源的分布式 KV 存储 Xline,就是针对多数据中心场景,实现数据的高性能跨云、跨数据中心共享访问,并且保证数据的一致性,方便业务系统实现多地多中心多活部署。
本周六(10 月 15 日)下午 3 点,达坦科技和 Rust 语言中文社区合作,由达坦科技的联合创始人施继成在 Rust 唠嗑室做开源分布式存储技术的分享,介绍 Xline 是如何实现高性能跨数据中心的数据一致性管理。欢迎大家预约收看!
-`;export{e as assetURLs,a as default,n as metadata,o as toc}; +`;export{e as assetURLs,a as default,n as metadata,o as toc}; diff --git a/zh-cn/assets/index-b21d7686.js b/zh-cn/assets/index-dca43e15.js similarity index 99% rename from zh-cn/assets/index-b21d7686.js rename to zh-cn/assets/index-dca43e15.js index 4f83997..7789e23 100644 --- a/zh-cn/assets/index-b21d7686.js +++ b/zh-cn/assets/index-dca43e15.js @@ -1,4 +1,4 @@ -const e="/zh-cn/assets/07123c0a1614c5c0256c2c44fccab7ad-82d2cfc4.jpeg",a="/zh-cn/assets/dbb615367665aefe1e8dc131faf7135d-ab0138b7.png",t="/zh-cn/assets/7e55ab5e49360b59ae14ad51bd9f8266-a3540f96.png",p="/zh-cn/assets/50e844cef87960be41630d431f7dba76-74a09282.png",s="/zh-cn/assets/da011de83bcdac4720de4265f06487fa-a09f8943.png",r="/zh-cn/assets/ab91fcebd0198e3ba3e68a1f0ede0dcb-2954efad.png",n="/zh-cn/assets/d6753cc7dafac128a184192d73a671d0-cbc3aa8e.png",l="/zh-cn/assets/8140b483b2b9992795a40af43149d92e-6324a4f1.png",c="/zh-cn/assets/261faba035c5925dd1bf0052673a2819-65bae75e.png",d="/zh-cn/assets/7ccbe7094043e218ad241cc3c2e3c871-e3e8431a.png",i="/zh-cn/assets/7a18e9fc6512a89b6e74a92a92580823-5ee6182a.png",o="/zh-cn/assets/3df9c5c4ff35c6cde20f54a80ed5bb0d-6b5bfe86.png",m="/zh-cn/assets/03beb98ee570de53f1aa4b866838924b-60f7cb4e.jpeg",u="/zh-cn/assets/13065eb252d78f86c7d84a7537e730d7-9522963a.png",h="/zh-cn/assets/0f55765329135bae263d77175baf52b7-2df179ec.png",I=[e,a,t,p,s,r,n,l,c,d,i,o,m,u,h],P={label:"blue-ethernet 高性能FPGA网络数据包处理项目详解",description:"blue-ethernet项目使用Bluespec SystemVerilog(BSV)硬件描述语言实现了一系列在FPGA上加速网络数据包处理的硬件模块。具体来说,其提供了用于生成和解析Ethernet/IP/UDP网络报文的硬件模块。此外,还提供了一个具有非阻塞高速缓存的APR报文处理单元,用于自动解析设备的物理MAC地址。",cover:"./07123c0a1614c5c0256c2c44fccab7ad.jpeg",location:"中国香港",author:["翁万正"],tags:["硬件加速"],date:"2023-11-02",title:"blue ethernet High Performance FPGA Network Packet Processing Project Details"},D=[{label:"简介",level:2},{label:"文件目录概览",level:2},{label:"组件",level:2},{label:"数据流处理模块",level:3},{label:"UdpIpLayer",level:3},{label:"UdpIpLayerForRdma",level:3},{label:"MacLayer",level:2},{label:"ARP Processor",level:3},{label:"UdpIpEthRx",level:3},{label:"UdpIpEthTx",level:3},{label:"UdpIpArpEthRxTx",level:3},{label:"PriorityFlowContro",level:3},{label:"性能和面积",level:2},{label:"入门教程",level:2},{label:"仿真测试",level:3},{label:"使用方法",level:3},{label:"相关链接",level:2}],A=` +const e="/zh-cn/assets/07123c0a1614c5c0256c2c44fccab7ad-82d2cfc4.jpeg",a="/zh-cn/assets/dbb615367665aefe1e8dc131faf7135d-ab0138b7.png",t="/zh-cn/assets/7e55ab5e49360b59ae14ad51bd9f8266-a3540f96.png",p="/zh-cn/assets/50e844cef87960be41630d431f7dba76-74a09282.png",s="/zh-cn/assets/da011de83bcdac4720de4265f06487fa-a09f8943.png",r="/zh-cn/assets/ab91fcebd0198e3ba3e68a1f0ede0dcb-2954efad.png",n="/zh-cn/assets/d6753cc7dafac128a184192d73a671d0-cbc3aa8e.png",l="/zh-cn/assets/8140b483b2b9992795a40af43149d92e-6324a4f1.png",c="/zh-cn/assets/261faba035c5925dd1bf0052673a2819-65bae75e.png",i="/zh-cn/assets/7ccbe7094043e218ad241cc3c2e3c871-e3e8431a.png",d="/zh-cn/assets/7a18e9fc6512a89b6e74a92a92580823-5ee6182a.png",o="/zh-cn/assets/3df9c5c4ff35c6cde20f54a80ed5bb0d-6b5bfe86.png",m="/zh-cn/assets/03beb98ee570de53f1aa4b866838924b-60f7cb4e.jpeg",u="/zh-cn/assets/13065eb252d78f86c7d84a7537e730d7-9522963a.png",h="/zh-cn/assets/0f55765329135bae263d77175baf52b7-2df179ec.png",I=[e,a,t,p,s,r,n,l,c,i,d,o,m,u,h],P={label:"blue-ethernet 高性能FPGA网络数据包处理项目详解",description:"blue-ethernet项目使用Bluespec SystemVerilog(BSV)硬件描述语言实现了一系列在FPGA上加速网络数据包处理的硬件模块。具体来说,其提供了用于生成和解析Ethernet/IP/UDP网络报文的硬件模块。此外,还提供了一个具有非阻塞高速缓存的APR报文处理单元,用于自动解析设备的物理MAC地址。",cover:"./07123c0a1614c5c0256c2c44fccab7ad.jpeg",location:"中国香港",author:["翁万正"],tags:["硬件加速"],date:"2023-11-02",title:"blue ethernet High Performance FPGA Network Packet Processing Project Details"},D=[{label:"简介",level:2},{label:"文件目录概览",level:2},{label:"组件",level:2},{label:"数据流处理模块",level:3},{label:"UdpIpLayer",level:3},{label:"UdpIpLayerForRdma",level:3},{label:"MacLayer",level:2},{label:"ARP Processor",level:3},{label:"UdpIpEthRx",level:3},{label:"UdpIpEthTx",level:3},{label:"UdpIpArpEthRxTx",level:3},{label:"PriorityFlowContro",level:3},{label:"性能和面积",level:2},{label:"入门教程",level:2},{label:"仿真测试",level:3},{label:"使用方法",level:3},{label:"相关链接",level:2}],C=`blue-ethernet 项目使用 Bluespec SystemVerilog(BSV)硬件描述语言实现了一系列在 FPGA 上加速网络数据包处理的硬件模块。具体来说,其提供了用于生成和解析 Ethernet/IP/UDP 网络报文的硬件模块。此外,还提供了一个具有非阻塞高速缓存的 APR 报文处理单元,用于自动解析设备的物理 MAC 地址。
除了构建标准的 UDP/IP/Ethernet 协议栈,blue-ethernet 还增加了对 RoCE(RDMA over Converged Ethernet)协议的支持,具体包括:
@@ -201,7 +201,7 @@ module mkMacMetaDataAndUdpIpStream#(mkArpProcessor 集成了 MAC 地址信息缓存单元 mkArpCache 以及对 ARP 报文的解析和生成模块。在处理 ARP 请求和响应时,mkArpProcessor 既可作为请求端,在 Cache Miss 时发出 ARP 请求报文并接收从目标设备返回的 ARP 响应报文。同时也可作为被请求端,接收其他设备发出的 ARP 请求报文并将自己的 MAC 地址信息通过 ARP 响应返回给请求端。
- +interface ArpProcessor;
interface PipeOut#(DataStream) arpStreamOut;
interface PipeOut#(MacMetaData) macMetaDataOut;
@@ -231,7 +231,7 @@ endinterface
module mkGenericUdpIpEthRx#(Bool isSupportRdma)(UdpIpEthRx)
-
+
关于项目更多的详细信息可关注链接:
-https://github.com/wengwz/blue-ethernet
`;export{I as assetURLs,A as default,P as metadata,D as toc}; +https://github.com/wengwz/blue-ethernet
`;export{I as assetURLs,C as default,P as metadata,D as toc}; diff --git a/zh-cn/assets/index-d758c903.js b/zh-cn/assets/index-ee7da202.js similarity index 95% rename from zh-cn/assets/index-d758c903.js rename to zh-cn/assets/index-ee7da202.js index 362a09e..282e74e 100644 --- a/zh-cn/assets/index-d758c903.js +++ b/zh-cn/assets/index-ee7da202.js @@ -1,4 +1,4 @@ -const t="/zh-cn/assets/cover-0645adbc.jpg",o="/zh-cn/assets/image1-4a25d469.jpg",e="/zh-cn/assets/image2-ee430ce0.png",a=[t,o,e],s={label:"达坦科技受邀在2022中国计算机学会芯片大会做硬件加速研究分享",description:"2022年7月29日至7月30日,由中国计算机学会(CCF)集成电路设计专业委员会、容错计算专业委员会、体系结构专业委员会和信息存储技术专业委员会联合举办的学术大会中国计算机学会芯片大会在江苏南京如期圆满举行。",cover:"./cover.jpg",location:"新加坡",date:"2022-08-04",title:"Dartan Technology Invited to Do Hardware Acceleration Research Sharing at 2022 China Computer Society Chip Conference"},n=[],c=` +const t="/zh-cn/assets/cover-0645adbc.jpg",o="/zh-cn/assets/image1-4a25d469.jpg",e="/zh-cn/assets/image2-ee430ce0.png",a=[t,o,e],n={label:"达坦科技受邀在2022中国计算机学会芯片大会做硬件加速研究分享",description:"2022年7月29日至7月30日,由中国计算机学会(CCF)集成电路设计专业委员会、容错计算专业委员会、体系结构专业委员会和信息存储技术专业委员会联合举办的学术大会中国计算机学会芯片大会在江苏南京如期圆满举行。",cover:"./cover.jpg",location:"新加坡",date:"2022-08-04",title:"Dartan Technology Invited to Do Hardware Acceleration Research Sharing at 2022 China Computer Society Chip Conference"},s=[],i=`2022 年 7 月 29 日至 7 月 30 日,由中国计算机学会(CCF)集成电路设计专业委员会、容错计算专业委员会、体系结构专业委员会和信息存储技术专业委员会联合举办的学术大会中国计算机学会芯片大会在江苏南京如期圆满举行。
2022 年 CCF 芯片大会由中科院计算所孙凝晖院士、中科院微电子所刘明院士担任大会主席,集结国内外知名专家学者,围绕智能化时代的芯片技术主题,论述芯片领域国际最前沿、权威和新颖的学术观点,包括芯片设计与 EDA、新型体系架构、前沿存储技术、容错计算应用等方面的关键技术和应用前景。
达坦科技致力于软硬件深度融合的跨云存储平台,其硬件负责人吴迪带领研发团队在今年的Xilinx 全球自适应计算挑战赛上刚获得Big Data Analytics 赛道一等奖。此次,达坦科技提交的论文“基于 SpinalHDL 和 Cocotb 的 Poseidon 哈希算法硬件加速器的敏捷开发”也成功入选,并受邀在大会做分享。达坦科技的翁万正在 30 日下午领域专用架构与敏捷设计论文分组,向与会者介绍了研究背景、方法技术和实验结果。
@@ -6,4 +6,4 @@ const t="/zh-cn/assets/cover-0645adbc.jpg",o="/zh-cn/assets/image1-4a25d469.jpg"Poseidon 是一种全新的面向零知识证明的(ZKP:Zero-Knowledge Proof)密码学协议设计的哈希算法。相比经典的 SHA-256 和 Keccak 哈希函数, 在零知识证明的应用场景下, Poseidon 能够显著地减少哈希函数的约束条件进而降低证明的计算复杂度, 极大提升零知识证明系统的运行效率。Poseidon 哈希函数的计算涉及高位宽模乘和矩阵乘法运算, 需要消耗大量计算资源。为了提升哈希计算的效率, 达坦基于流水线和折叠技术提出了一种面向 FPGA 平台的 Poseidon 硬件加速器架构。
在该整体架构下, 针对高位宽模乘, 达坦科技基于 Karatsuba 乘法拆分算法实现了一种高性能蒙哥马利模乘器。针对函数中的向量—矩阵乘法计算, 达坦科技基于脉动矩阵结构提出了一种高吞吐率的硬件实现。最终, 在搭载有 Xilinx Virtex Ultrascale+ FPGA 芯片的 Varium C1100 加速卡上, 硬件加速器每秒最高能完成 0.99M 次哈希计算, 达到 AMD Ryzen 5900X 处理器 Poseidon 计算速度的两倍。
-除了打造全新的广域网共识算法,达坦科技专注于自研面向存储网络的硬件加速,以期软硬件的深度融合能提升存储的性能。目前达坦科技的硬件项目 TRIDENT,已经在 Github 上开源,欢迎参与讨论:https://github.com/datenlord/TRIDENT。
`;export{a as assetURLs,c as default,s as metadata,n as toc}; +除了打造全新的广域网共识算法,达坦科技专注于自研面向存储网络的硬件加速,以期软硬件的深度融合能提升存储的性能。目前达坦科技的硬件项目 TRIDENT,已经在 Github 上开源,欢迎参与讨论:https://github.com/datenlord/TRIDENT。
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l SpinalHDL应用前景探索线上研讨会",description:"2022年12月16日,达坦科技联合SpinalHDL社区,举办了SpinalHDL Webinar 2022。在题为《SpinalHDL应用前景探索》的线上研讨会上,九位分享人在三个讨论分主题下做了各自领域内应用Spinal HDL的实践、挑战和经验的分享。",location:"中国香港",date:"2022-12-12",title:"SpinalHDL Application Prospect Exploration Online Seminar"},C=[{label:"数据通路加速",level:2},{label:"复杂系统设计案例",level:2},{label:"硬件设计流程",level:2},{label:"推荐阅读",level:2}],h=`2022 年 12 月 16 日,达坦科技联合 SpinalHDL 社区,举办了 SpinalHDL Webinar 2022。在题为《SpinalHDL 应用前景探索》的线上研讨会上,九位分享人在三个讨论分主题下做了各自领域内应用 Spinal HDL 的实践、挑战和经验的分享。
分享人:Tianrui Li
@@ -32,12 +32,12 @@ const e="/zh-cn/assets/image1-b974e0d0.png",i="/zh-cn/assets/image2-599a44cc.jpg演讲摘要: This presentation / live demo shows how the NaxRiscv project (Out-of-order / superscalar RISC-V CPU) mix Scala and the SpinalHDL API to describe its hardware. By many aspect, it goes beyond the VexRiscv project, and should provide some usefull / interresting design patterns for the public.
分享人:Readon
演讲主题: Recent progress on formal verification support on SpinalHDL
演讲摘要: The formal verification is a technology to verify design, which helps to find the corner cases. SpinalHDL have provided an integration of this tech with SymbiYosys easily. The brief introduction on how to verify a design would be presented by example. Some new build blocks helping to simplify the verification process would be introduced. At last, a short overview of the verification of some facilities in SpinalHDL's lib would also be summarized.
分享人:Sebastien-riou
演讲主题: SpinalHDL for ASIC
演讲摘要: The presentation is a highlights of a ASIC done entirely in SpinalHDL, fabricated in GF22FDX. Focus on pads, RAMs and FPGA for ASIC verification.
diff --git a/zh-cn/assets/index-a1a1a279.js b/zh-cn/assets/index-ffd93bc8.js similarity index 95% rename from zh-cn/assets/index-a1a1a279.js rename to zh-cn/assets/index-ffd93bc8.js index 6149306..0305554 100644 --- a/zh-cn/assets/index-a1a1a279.js +++ b/zh-cn/assets/index-ffd93bc8.js @@ -1,4 +1,4 @@ -const e="/zh-cn/assets/cover-c938ebe8.png",t="/zh-cn/assets/image1-a88ec652.jpg",s="/zh-cn/assets/image2-0d688c12.png",r=[e,t,s],n={label:"4.8 Beijing Rust Meetup | Call For Presenters",description:"如果你有兴趣参与探讨Rust作为一种强调性能、安全和并发性的编程语言的各种应用、实践和无限可能性的头脑风暴,就一定不能错过这场来自达坦科技、南京大学、CloudWeGo、华为等技术专家带来的关于Rust编程语言相关应用的线下Meetup。我们的主题是Rust💡X,意在探讨用Rust编程语言“点亮”的任何应用、实践和探索。",cover:"./cover.png",location:"中国香港",date:"2023-03-31",title:"4.8 Beijing Rust Meetup | Call For Presenters"},i=[{label:"嘉宾演讲 (Presenter & Topic)",level:2},{label:"提交议题 (Call for Presenters)",level:2},{label:"Meetup 报名方式 (Registration)",level:2}],o=`如果你有兴趣参与探讨 Rust 作为一种强调性能、安全和并发性的编程语言的各种应用、实践和无限可能性的头脑风暴,就一定不能错过这场来自达坦科技、南京大学、CloudWeGo、华为等技术专家带来的关于 Rust 编程语言相关应用的线下 Meetup。我们的主题是 Rust💡X,意在探讨用 Rust 编程语言“点亮”的任何应用、实践和探索。
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时间: 2023 年 4 月 8 日 14:00 地点: 环球财讯中心 M 层 北京市西城区宣武门外大街甲 1 号
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