diff --git a/chapters/verilog/memory/drills/tasks/sequential_multiplier/sequential_multiplier.v b/chapters/verilog/memory/drills/tasks/sequential_multiplier/sequential_multiplier.v index 677e613b..5116f8ad 100644 --- a/chapters/verilog/memory/drills/tasks/sequential_multiplier/sequential_multiplier.v +++ b/chapters/verilog/memory/drills/tasks/sequential_multiplier/sequential_multiplier.v @@ -2,6 +2,8 @@ module sequential_multiplier #( parameter p_data_width = 4 )( output wire [(2*p_data_width-1):0] o_w_out, + output wire [(p_data_width-1):0] o_w_disp_a, + output wire [(p_data_width-1):0] o_w_disp_b, input wire [(p_data_width-1):0] i_w_a, input wire [(p_data_width-1):0] i_w_b, input wire i_w_clk, @@ -16,6 +18,7 @@ module sequential_multiplier #( wire [(p_data_width-1):0] l_w_a_out; register #(.p_data_width(p_data_width)) l_m_register_0 ( .o_w_out(l_w_a_out), + .o_w_disp_out(o_w_disp_a), .i_w_clk(i_w_clk), .i_w_reset(i_w_reset), .i_w_in(i_w_a), @@ -28,6 +31,7 @@ module sequential_multiplier #( wire [(p_data_width-1):0] l_w_b_out; register #(.p_data_width(p_data_width)) l_m_register_1 ( .o_w_out(l_w_b_out), + .o_w_disp_out(o_w_disp_b), .i_w_clk(i_w_clk), .i_w_reset(i_w_reset), .i_w_in(i_w_b), diff --git a/chapters/verilog/memory/drills/tasks/sequential_multiplier/sequential_multiplier.xdc b/chapters/verilog/memory/drills/tasks/sequential_multiplier/sequential_multiplier.xdc index e5092ae7..146934c1 100644 --- a/chapters/verilog/memory/drills/tasks/sequential_multiplier/sequential_multiplier.xdc +++ b/chapters/verilog/memory/drills/tasks/sequential_multiplier/sequential_multiplier.xdc @@ -6,7 +6,7 @@ ## Clock signal #set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; - +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {i_w_clk_IBUF}] ##Switches set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { i_w_a[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] @@ -19,8 +19,8 @@ set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[ set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { i_w_b[3] }]; #IO_L5N_T0_D07_14 Sch=sw[7] set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { i_w_multiply }]; #IO_L24N_T3_34 Sch=sw[8] set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { i_w_write }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { i_w_reset }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { i_w_display }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { i_w_reset }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] #set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] #set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] #set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] @@ -35,14 +35,14 @@ set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { o_w_ou set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { o_w_out[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { o_w_out[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { o_w_out[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { o_w_disp_a[0] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { o_w_disp_a[1] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { o_w_disp_a[2] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { o_w_disp_a[3] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { o_w_disp_b[0] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { o_w_disp_b[1] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { o_w_disp_b[2] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { o_w_disp_b[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] ## RGB LEDs #set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b