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Introduce BiDf protocol #109
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Original file line number | Diff line number | Diff line change |
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@@ -30,6 +30,7 @@ module Protocols ( | |
-- * Basic circuits | ||
idC, | ||
repeatC, | ||
repeatWithIndexC, | ||
prod2C, | ||
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-- * Simulation | ||
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{-# OPTIONS_GHC -fplugin Protocols.Plugin #-} | ||
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-- | Bi-directional request/response-style 'Df' channels. | ||
module Protocols.BiDf ( | ||
BiDf, | ||
-- * Conversion | ||
fromDfs, | ||
toDfs, | ||
fromBiDf, | ||
toBiDf, | ||
-- * Trivial combinators | ||
void, | ||
loopback, | ||
-- * Mapping | ||
dimap, | ||
-- * Fan-in | ||
fanin | ||
) where | ||
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import Prelude () | ||
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import Clash.Prelude | ||
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import Protocols | ||
import qualified Protocols.Df as Df | ||
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-- | A 'Protocol' allowing requests to be passed downstream, with corresponding | ||
-- responses being passed back upstream. Responses are provided in the order that | ||
-- their corresponding requests were submitted. | ||
-- | ||
-- *Correctness conditions* | ||
-- | ||
-- - The response channel must not produce a value before the request channel | ||
-- has produced a value. The response may be produced in the same cycle the | ||
-- request is acknowledged (but see the law about a combinational path | ||
-- below). | ||
-- | ||
-- - Each request must be paired with exactly one response. | ||
-- | ||
-- - Responses must be issued in the order that their corresponding requests arrived. | ||
-- | ||
-- - Both the request and response channels must obey usual 'Df' correctness | ||
-- conditions. | ||
-- | ||
-- - There must not be a combinational path from the request channel to the | ||
-- response channel. | ||
-- | ||
type BiDf dom req resp = | ||
(Df dom req, Reverse (Df dom resp)) | ||
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-- | Convert a circuit of 'Df's to a 'BiDf' circuit. | ||
toBiDf | ||
:: Circuit (Df dom req) (Df dom resp) | ||
-> Circuit (BiDf dom req resp) () | ||
toBiDf c = circuit $ \bidf -> do | ||
resp <- c -< req | ||
req <- toDfs -< (bidf, resp) | ||
idC -< () | ||
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-- | Convert a 'BiDf' circuit to a circuit of 'Df's. | ||
fromBiDf | ||
:: Circuit (BiDf dom req resp) () | ||
-> Circuit (Df dom req) (Df dom resp) | ||
fromBiDf c = circuit $ \req -> do | ||
(biDf, resp) <- fromDfs -< req | ||
c -< biDf | ||
idC -< resp | ||
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-- | Convert a pair of a request and response 'Df`s into a 'BiDf'. | ||
toDfs :: Circuit (BiDf dom req resp, Df dom resp) (Df dom req) | ||
toDfs = fromSignals $ \(~((reqData, respAck), respData), reqAck) -> | ||
(((reqAck, respData), respAck), reqData) | ||
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-- | Convert a 'BiDf' into a pair of request and response 'Df`s. | ||
fromDfs :: Circuit (Df dom req) (BiDf dom req resp, Df dom resp) | ||
fromDfs = fromSignals $ \(reqData, ~((reqAck, respData), respAck)) -> | ||
(reqAck, ((reqData, respAck), respData)) | ||
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-- | Ignore all requests, never providing responses. | ||
void :: (HiddenClockResetEnable dom) => Circuit (BiDf dom req resp') () | ||
void = circuit $ \biDf -> do | ||
req <- toDfs -< (biDf, resp) | ||
resp <- Df.empty -< () | ||
Df.void -< req | ||
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-- | Return mapped requests as responses. | ||
loopback | ||
:: (HiddenClockResetEnable dom, NFDataX req) | ||
=> (req -> resp) | ||
-> Circuit (BiDf dom req resp) () | ||
loopback f = circuit $ \biDf -> do | ||
req <- toDfs -< (biDf, resp) | ||
resp <- Df.map f <| Df.registerFwd -< req | ||
idC -< () | ||
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-- | Map both requests and responses. | ||
dimap | ||
:: (req -> req') | ||
-> (resp -> resp') | ||
-> Circuit (BiDf dom req resp') (BiDf dom req' resp) | ||
dimap f g = circuit $ \biDf -> do | ||
req <- toDfs -< (biDf, resp') | ||
req' <- Df.map f -< req | ||
resp' <- Df.map g -< resp | ||
(biDf', resp) <- fromDfs -< req' | ||
idC -< biDf' | ||
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-- | Merge a number of 'BiDf's, preferring requests from the last channel. | ||
fanin | ||
:: forall n dom req resp. | ||
( KnownNat n | ||
, 1 <= n | ||
, NFDataX req | ||
, NFDataX resp | ||
, HiddenClockResetEnable dom | ||
) | ||
=> Circuit (Vec n (BiDf dom req resp)) (BiDf dom req resp) | ||
fanin = fromSignals $ \(upFwds, (reqAck, respData)) -> | ||
let reqDatas :: Vec n (Signal dom (Df.Data req)) | ||
reqDatas = map fst upFwds | ||
respAcks :: Vec n (Signal dom Ack) | ||
respAcks = map snd upFwds | ||
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((reqAcks, respAck), (respDatas, reqData)) = | ||
toSignals fanin' ((reqDatas, respData), (respAcks, reqAck)) | ||
in (zip reqAcks respDatas, (reqData, respAck)) | ||
where | ||
fanin' | ||
:: Circuit (Vec n (Df dom req), Df dom resp) | ||
(Vec n (Df dom resp), Df dom req) | ||
fanin' = circuit $ \(reqs, resp) -> do | ||
[fwd0, fwd1] | ||
<- Df.fanout | ||
<| Df.roundrobinCollect @n Df.Parallel | ||
<| repeatWithIndexC (\i -> Df.map (\x -> (i,x))) | ||
-< reqs | ||
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activeN <- Df.map fst -< fwd1 | ||
resps <- Df.route <| Df.zip -< (activeN, resp) | ||
req <- Df.map snd -< fwd0 | ||
idC -< (resps, req) |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,104 @@ | ||
{-# OPTIONS_GHC -fplugin Protocols.Plugin #-} | ||
{-# LANGUAGE TemplateHaskell #-} | ||
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module Tests.Protocols.BiDf (tests) where | ||
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-- clash-prelude | ||
import Clash.Prelude as C | ||
import qualified Clash.Sized.Vector as Vector | ||
import Clash.Hedgehog.Sized.Vector | ||
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-- clash-protocols | ||
import Protocols | ||
import Protocols.Hedgehog | ||
import Protocols.BiDf as BiDf | ||
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-- hedgehog | ||
import Hedgehog | ||
import qualified Hedgehog.Gen as Gen | ||
import qualified Hedgehog.Range as Range | ||
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-- tasty | ||
import Test.Tasty | ||
import Test.Tasty.Hedgehog.Extra (testProperty) | ||
import Test.Tasty.TH (testGroupGenerator) | ||
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-- | Ensure that 'BiDf.toDfs' composed with 'BiDf.fromDfs' behaves as an | ||
-- identity. | ||
prop_toDfs_fromDfs_id :: Property | ||
prop_toDfs_fromDfs_id = | ||
idWithModelSingleDomain @System defExpectOptions gen (\_ _ _ -> id) (exposeClockResetEnable impl) | ||
where | ||
gen :: Gen [Int] | ||
gen = Gen.list (Range.linear 0 10) (Gen.integral (Range.linear 0 100)) | ||
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impl :: forall dom a. (HiddenClockResetEnable dom, NFDataX a) | ||
=> Circuit (Df dom a) (Df dom a) | ||
impl = BiDf.toDfs <| BiDf.fromDfs | ||
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-- | Ensure that 'BiDf.loopback' behaves as an identity. | ||
prop_loopback_id :: Property | ||
prop_loopback_id = | ||
idWithModelSingleDomain @System defExpectOptions gen (\_ _ _ -> id) (exposeClockResetEnable impl) | ||
where | ||
gen :: Gen [Int] | ||
gen = Gen.list (Range.linear 0 10) (Gen.integral (Range.linear 0 100)) | ||
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impl :: forall dom a. (HiddenClockResetEnable dom, NFDataX a) | ||
=> Circuit (Df dom a) (Df dom a) | ||
impl = circuit $ \req -> do | ||
(biDf, resp) <- BiDf.fromDfs -< req | ||
BiDf.loopback id -< biDf | ||
idC -< resp | ||
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-- | Test that 'BiDf.fanin' on a single 'BiDf' channel behaves as an identity. | ||
prop_fanin_id :: Property | ||
prop_fanin_id = | ||
idWithModelSingleDomain @System defExpectOptions gen (\_ _ _ -> id) (exposeClockResetEnable impl) | ||
where | ||
gen :: Gen [Int] | ||
gen = Gen.list (Range.linear 0 10) (Gen.integral (Range.linear 0 100)) | ||
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impl | ||
:: forall dom a. (HiddenClockResetEnable dom, NFDataX a) | ||
=> Circuit (Df dom a) (Df dom a) | ||
impl = circuit $ \req -> do | ||
(biDf, resp) <- BiDf.fromDfs -< req | ||
BiDf.loopback id <| BiDf.fanin @1 -< [biDf] | ||
idC -< resp | ||
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-- | Test that 'BiDf.fanin' on a number of 'BiDf' channels behaves as an | ||
-- identity on each channel. | ||
prop_fanin :: Property | ||
prop_fanin = | ||
idWithModelSingleDomain @System expectOpts | ||
(gen @3) | ||
(\_ _ _ -> id) | ||
(exposeClockResetEnable impl) | ||
where | ||
expectOpts = defExpectOptions | ||
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gen :: forall n. KnownNat n => Gen (Vec n [(Index n, Int)]) | ||
gen = do | ||
xs <- genVec @Gen @n $ Gen.list (Range.linear 0 10) (Gen.integral (Range.linear 0 100)) | ||
return $ C.zipWith (\i -> fmap (\x -> (i,x))) indicesI xs | ||
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impl | ||
:: forall n dom a. | ||
(HiddenClockResetEnable dom, KnownNat n, 1 <= n, NFDataX a) | ||
=> Circuit (Vec n (Df dom a)) (Vec n (Df dom a)) | ||
impl = circuit $ \reqs -> do | ||
(biDfs, resps) <- unbundleC <| repeatC BiDf.fromDfs -< reqs | ||
BiDf.loopback id <| BiDf.fanin @n -< biDfs | ||
idC -< resps | ||
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unbundleC :: forall n a b. Circuit (Vec n (a, b)) (Vec n a, Vec n b) | ||
unbundleC = fromSignals $ \(fwd, (bwdA, bwdB)) -> | ||
let fwdA :: Vec n (Fwd a) | ||
fwdB :: Vec n (Fwd b) | ||
(fwdA, fwdB) = Vector.unzip fwd | ||
in (Vector.zip bwdA bwdB, (fwdA, fwdB)) | ||
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tests :: TestTree | ||
tests = | ||
$(testGroupGenerator) |
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Am I reading correctly that this disallows stateless circuits such as:
If so, why would that not be allowed?