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workgroups.html
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<div class="container main-content">
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<div id="fws_621e4bf55d88e" data-column-margin="default" data-midnight="light" data-top-percent="5%" data-bottom-percent="5%" class="wpb_row vc_row-fluid vc_row top-level full-width-section first-section loaded" style="padding-top: 40.8px; padding-bottom: 40.8px;"><div class="row-bg-wrap" data-bg-animation="none" data-bg-overlay="false"><div class="inner-wrap using-image"><div class="row-bg viewport-desktop using-image" style="background-image: url(https://chipsalliance.org/wp-content/uploads/sites/83/2019/03/ca_bg_1.jpg); background-position: left top; background-repeat: no-repeat; "></div></div></div><div class="row_col_wrap_12 col span_12 light left">
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<h1 style="color: #ffffff;text-align: left" class="vc_custom_heading">Workgroups</h1>
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<p>The CHIPS Alliance hosts multiple open source Projects. Similar Projects are organized into Workgroups. Each Project elects a representative to participate on the TSC.</p>
<p><span style="font-weight: 400;">CHIPS Alliance will be adding Projects over time as the community gets started and may spin up or wind down Workgroups as needed to reflect our work across the SoC and tooling ecosystem. We welcome code, engineer involvement and partnership collaborations to further define and focus projects into relevant and strategically critical opportunities. Members and non-members alike are invited to participate in our work to change the landscape of chip development to be more open source. Please join the </span><a href="https://lists.chipsalliance.org/g/technical-discuss"><span style="font-weight: 400;">technical-discuss mailing list</span></a><span style="font-weight: 400;"> to get started!</span></p>
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<div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>Analog Workgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<p><span style="font-weight: 400;">The Analog workgroup was formed by the CHIPS Alliance TSC to explore collaborations in open source Analog/Mixed-Signal design and verification. It focuses on sharing best practices, ideas, tooling (analog automation), and other challenge areas in the design space. The workgroup is composed of both industry and university members.</span></p>
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> <a href="mailto:[email protected]">Mailing list</a>: [email protected]</li>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> Meetings: Every other Tuesday at 8:00 a.m. PT</li>
</ul>
</div><div class="divider-wrap" data-alignment="default"><div style="height: 30px;" class="divider"></div></div><div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>Chisel Workgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<p><span style="font-weight: 400;">The </span><a href="https://www.chisel-lang.org/"><span style="font-weight: 400;">Chisel</span></a><span style="font-weight: 400;"> Workgroup is formed around the eponymous hardware design language (HDL) that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the </span><a href="https://www.scala-lang.org/"><span style="font-weight: 400;">Scala</span></a><span style="font-weight: 400;"> programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. Chisel is powered by </span><a href="https://github.com/chipsalliance/firrtl"><span style="font-weight: 400;">FIRRTL (Flexible Intermediate Representation for RTL)</span></a><span style="font-weight: 400;">, a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations on an Intermediate Representation. The WG also covers tools such as </span><a href="https://github.com/chipsalliance/treadle"><span style="font-weight: 400;">Treadle</span></a><span style="font-weight: 400;"> which is an experimental circuit simulator that executes the Firrtl IR. </span></p>
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> <a href="https://lists.chipsalliance.org/g/chisel-wg/topics">Mailing list</a></li>
</ul>
</div><div class="divider-wrap" data-alignment="default"><div style="height: 30px;" class="divider"></div></div><div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>Cores Workgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<p><span style="font-weight: 400;">We are currently looking for more contributors to reboot our Cores Workgroup. If you are interested in working around open source implementation and verification methodologies and other tooling for cores, reach out to <a href="mailto:[email protected]">[email protected]</a></span></p>
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> <a href="https://lists.chipsalliance.org/g/cores-wg">Mailing list</a></li>
</ul>
</div><div class="divider-wrap" data-alignment="default"><div style="height: 30px;" class="divider"></div></div><div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>F4PGA Workgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<p>The F4PGA Workgroup was formed to drive open source tooling, IP cores and research for FPGA devices. It includes three major groups whose collaboration is critical to the success of the open source approach in this space: FPGA vendors, industrial users and university members. Its main focus is enabling rapid prototyping and software-driven development of FPGA-oriented systems in areas such as ML and video processing. The workgroup provides an open collaboration platform for its members, aiming at accelerating the speed of innovation in FPGAs and the general availability of the technology. The initial projects contributed into CHIPS Alliance within the F4PGA Workgroup are focused around the free and open source FPGA toolchain formerly known as SymbiFlow, as well as the so-called FPGA Interchange format.</p>
</div><div class="divider-wrap" data-alignment="default"><div style="height: 30px;" class="divider"></div></div><div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>Interconnects Workgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> <a href="https://lists.chipsalliance.org/g/interconnects-wg">Mailing list</a></li>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> Meetings: Once a month at 10:30 a.m. PT
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> <a href="https://lists.chipsalliance.org/g/interconnects-wg/calendar">Calendar</a></li>
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<div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>Rocket Workgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<p><span style="font-weight: 400;">The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using </span><a href="http://chisel.eecs.berkeley.edu/"><span style="font-weight: 400;">Chisel</span></a><span style="font-weight: 400;"> and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.</span></p>
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> <a href="https://lists.chipsalliance.org/g/rocket-wg">Mailing list</a></li>
</ul>
</div><div class="divider-wrap" data-alignment="default"><div style="height: 30px;" class="divider"></div></div><div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>Tools Workgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<p><span style="font-weight: 400;">The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.</span></p>
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> <a href="https://lists.chipsalliance.org/g/tools-wg">Mailing list</a></li>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> Meetings: Every other Friday (currently odd weeks) at 7 a.m. PT, <a href="https://meet.google.com/ncy-rzzp-tfv?hs=122">Google Meet link</a></li>
</ul>
</div><div class="divider-wrap" data-alignment="default"><div style="height: 30px;" class="divider"></div></div><div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>RISC-V DV Subgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<p><span style="font-weight: 400;">RISC-V DV is an open source verification tool for RISC-V processors, a SystemVerilog based random RISC-V instruction generator that checks the execution against multiple ISS for correctness and compliance. This Subgroup of the Tools Workgroup is concerned with the development of the RISC-V DV framework and related technologies.</span></p>
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> <a href="https://lists.chipsalliance.org/g/tools-wg">Mailing list:</a> <a href="mailto:[email protected]">[email protected]</a></li>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> Meetings: Every other Friday (currently even weeks) at 9:00 a.m. PT, <a href="https://meet.google.com/soh-ovxy-vez">Google Meet Link</a></li>
</ul>
</div><div class="divider-wrap" data-alignment="default"><div style="height: 30px;" class="divider"></div></div><div class="nectar-gradient-text" data-direction="diagonal" data-color="extra-color-gradient-1" style="margin-top: 25px; margin-bottom: 25px; "><h3>SystemVerilog Subgroup</h3></div><div class="nectar-fancy-ul" data-list-icon="fa fa-angle-double-right" data-animation="false" data-animation-delay="0" data-color="accent-color" data-spacing="default" data-alignment="left">
<p><span style="font-weight: 400;">This Subgroup of the Tools Workgroup gathers projects related to the SystemVerilog (SV) Hardware Description Language (HDL) and making it work in open source tooling. This includes CHIPS Alliance projects such as Verible and Surelog and integration with well-established open source tools like Verilator and Yosys.</span></p>
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> Meetings:
<ul>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> Users meet as part of the regular Tools Workgroup meetings</li>
<li><i class="icon-default-style fa fa-angle-double-right accent-color"></i> Developers meet Tuesdays at 9:00 a.m. PT</li>
</ul>
</li>
</ul>
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