Format OpenTitan codebase with Verible SystemVerilog code formatter

[ghost]

Use Verible formatter to format OpenTitan (https://github.com/lowRISC/opentitan) codebase.

Modify formatter so it complies with lowRISC Verilog Coding Style and use it with OpenTitan codebase.

Current formatting results
https://github.com/ldalek-antmicro/opentitan/commit/034e844c171ae86c475311f3e561fb6eb7efdc6e

Previous tests and related issues

1. [format] Verible formatter experiment v0.0-808-g1e17daa lowRISC/ibex#1215
2. Verible Format experiment msfschaffner/opentitan#7
3. hzeller/opentitan@e28c2f6
4. [tracking] Use Verible's verilog_format for code formatting lowRISC/ibex#687

OpenTitan related issues

All-in-one-place status

Style compliance report (WIP)

OpenTitan fileset coverage status

Fileset	Number
OpenTitan	1441
Verible-formatted	202
Work-In-Progress	230
Auto-generated (skipped)	2
Error	24
TODO	986

Files triggering internal (Verible) bugs

Files unaffected by formatting

Files properly formatted (candidates for verible-format-allow-list.txt)

Files improperly formatted (bugs/usupported features)

[hzeller]

(If there are parse errors, there is one open pull request #697 that works on one parsing issue, not sure if this is one that is problematic here)

[hzeller]

Also as we had looked at before: relevant are these pull request, in which OpenTitan folks commented on the format output, which helps give us insight which is most important.

lowRISC/ibex#1215
msfschaffner/opentitan#7 (older)

Might be good if we can pair these comments with existing issues mentioned in https://github.com/google/verible/labels/formatter and increase priority as they are clearly needed.

[hzeller]

In this run I did a while back hzeller/opentitan@e28c2f6
David also added some links to existing bugs.